1 /* $OpenBSD: if_rtwnreg.h,v 1.3 2015/06/14 08:02:47 stsp Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2015 Stefan Sperling <stsp@openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 * 19 * $FreeBSD$ 20 */ 21 22 #define R92C_MAX_CHAINS 2 23 24 /* Maximum number of output pipes is 3. */ 25 #define R92C_MAX_EPOUT 3 26 27 #define R92C_MAX_TX_PWR 0x3f 28 29 #define R92C_PUBQ_NPAGES 176 30 #define R92C_HPQ_NPAGES 41 31 #define R92C_LPQ_NPAGES 28 32 #define R92C_TXPKTBUF_COUNT 256 33 #define R92C_TX_PAGE_COUNT \ 34 (R92C_PUBQ_NPAGES + R92C_HPQ_NPAGES + R92C_LPQ_NPAGES) 35 #define R92C_TX_PAGE_BOUNDARY (R92C_TX_PAGE_COUNT + 1) 36 37 #define R92C_H2C_NBOX 4 38 39 /* USB Requests. */ 40 #define R92C_REQ_REGS 0x05 41 42 /* 43 * MAC registers. 44 */ 45 /* System Configuration. */ 46 #define R92C_SYS_ISO_CTRL 0x000 47 #define R92C_SYS_FUNC_EN 0x002 48 #define R92C_APS_FSMCO 0x004 49 #define R92C_SYS_CLKR 0x008 50 #define R92C_AFE_MISC 0x010 51 #define R92C_SPS0_CTRL 0x011 52 #define R92C_SPS_OCP_CFG 0x018 53 #define R92C_RSV_CTRL 0x01c 54 #define R92C_RF_CTRL 0x01f 55 #define R92C_LDOA15_CTRL 0x020 56 #define R92C_LDOV12D_CTRL 0x021 57 #define R92C_LDOHCI12_CTRL 0x022 58 #define R92C_LPLDO_CTRL 0x023 59 #define R92C_AFE_XTAL_CTRL 0x024 60 #define R92C_AFE_PLL_CTRL 0x028 61 #define R92C_EFUSE_CTRL 0x030 62 #define R92C_EFUSE_TEST 0x034 63 #define R92C_PWR_DATA 0x038 64 #define R92C_CAL_TIMER 0x03c 65 #define R92C_ACLK_MON 0x03e 66 #define R92C_GPIO_MUXCFG 0x040 67 #define R92C_GPIO_IO_SEL 0x042 68 #define R92C_MAC_PINMUX_CFG 0x043 69 #define R92C_GPIO_PIN_CTRL 0x044 70 #define R92C_GPIO_INTM 0x048 71 #define R92C_LEDCFG0 0x04c 72 #define R92C_LEDCFG1 0x04d 73 #define R92C_LEDCFG2 0x04e 74 #define R92C_LEDCFG3 0x04f 75 #define R92C_FSIMR 0x050 76 #define R92C_FSISR 0x054 77 #define R92C_HSIMR 0x058 78 #define R92C_HSISR 0x05c 79 #define R92C_MCUFWDL 0x080 80 #define R92C_HMEBOX_EXT(idx) (0x088 + (idx) * 2) 81 #define R92C_BIST_SCAN 0x0d0 82 #define R92C_BIST_RPT 0x0d4 83 #define R92C_BIST_ROM_RPT 0x0d8 84 #define R92C_USB_SIE_INTF 0x0e0 85 #define R92C_PCIE_MIO_INTF 0x0e4 86 #define R92C_PCIE_MIO_INTD 0x0e8 87 #define R92C_HPON_FSM 0x0ec 88 #define R92C_SYS_CFG 0x0f0 89 /* MAC General Configuration. */ 90 #define R92C_CR 0x100 91 #define R92C_PBP 0x104 92 #define R92C_TRXDMA_CTRL 0x10c 93 #define R92C_TRXFF_BNDY 0x114 94 #define R92C_TRXFF_STATUS 0x118 95 #define R92C_RXFF_PTR 0x11c 96 #define R92C_HIMR 0x120 97 #define R92C_HISR 0x124 98 #define R92C_HIMRE 0x128 99 #define R92C_HISRE 0x12c 100 #define R92C_CPWM 0x12f 101 #define R92C_FWIMR 0x130 102 #define R92C_FWISR 0x134 103 #define R92C_PKTBUF_DBG_CTRL 0x140 104 #define R92C_PKTBUF_DBG_DATA_L 0x144 105 #define R92C_PKTBUF_DBG_DATA_H 0x148 106 #define R92C_TC0_CTRL(i) (0x150 + (i) * 4) 107 #define R92C_TCUNIT_BASE 0x164 108 #define R92C_MBIST_START 0x174 109 #define R92C_MBIST_DONE 0x178 110 #define R92C_MBIST_FAIL 0x17c 111 #define R92C_C2HEVT_MSG_NORMAL 0x1a0 112 #define R92C_C2HEVT_MSG_TEST 0x1b8 113 #define R92C_C2HEVT_CLEAR 0x1bf 114 #define R92C_MCUTST_1 0x1c0 115 #define R92C_FMETHR 0x1c8 116 #define R92C_HMETFR 0x1cc 117 #define R92C_HMEBOX(idx) (0x1d0 + (idx) * 4) 118 #define R92C_LLT_INIT 0x1e0 119 #define R92C_BB_ACCESS_CTRL 0x1e8 120 #define R92C_BB_ACCESS_DATA 0x1ec 121 /* Tx DMA Configuration. */ 122 #define R92C_RQPN 0x200 123 #define R92C_FIFOPAGE 0x204 124 #define R92C_TDECTRL 0x208 125 #define R92C_TXDMA_OFFSET_CHK 0x20c 126 #define R92C_TXDMA_STATUS 0x210 127 #define R92C_RQPN_NPQ 0x214 128 /* Rx DMA Configuration. */ 129 #define R92C_RXDMA_AGG_PG_TH 0x280 130 #define R92C_RXPKT_NUM 0x284 131 #define R92C_RXDMA_STATUS 0x288 132 133 #define R92C_PCIE_CTRL_REG 0x300 134 #define R92C_INT_MIG 0x304 135 #define R92C_BCNQ_DESA 0x308 136 #define R92C_HQ_DESA 0x310 137 #define R92C_MGQ_DESA 0x318 138 #define R92C_VOQ_DESA 0x320 139 #define R92C_VIQ_DESA 0x328 140 #define R92C_BEQ_DESA 0x330 141 #define R92C_BKQ_DESA 0x338 142 #define R92C_RX_DESA 0x340 143 #define R92C_DBI 0x348 144 #define R92C_MDIO 0x354 145 #define R92C_DBG_SEL 0x360 146 #define R92C_PCIE_HRPWM 0x361 147 #define R92C_PCIE_HCPWM 0x363 148 #define R92C_UART_CTRL 0x364 149 #define R92C_UART_TX_DES 0x370 150 #define R92C_UART_RX_DES 0x378 151 152 #define R92C_VOQ_INFORMATION 0x0400 153 #define R92C_VIQ_INFORMATION 0x0404 154 #define R92C_BEQ_INFORMATION 0x0408 155 #define R92C_BKQ_INFORMATION 0x040C 156 #define R92C_MGQ_INFORMATION 0x0410 157 #define R92C_HGQ_INFORMATION 0x0414 158 #define R92C_BCNQ_INFORMATION 0x0418 159 #define R92C_CPU_MGQ_INFORMATION 0x041C 160 161 /* Protocol Configuration. */ 162 #define R92C_FWHW_TXQ_CTRL 0x420 163 #define R92C_HWSEQ_CTRL 0x423 164 #define R92C_TXPKTBUF_BCNQ_BDNY 0x424 165 #define R92C_TXPKTBUF_MGQ_BDNY 0x425 166 #define R92C_SPEC_SIFS 0x428 167 #define R92C_RL 0x42a 168 #define R92C_DARFRC 0x430 169 #define R92C_RARFRC 0x438 170 #define R92C_RRSR 0x440 171 #define R92C_ARFR(i) (0x444 + (i) * 4) 172 #define R92C_AGGLEN_LMT 0x458 173 #define R92C_AMPDU_MIN_SPACE 0x45c 174 #define R92C_TXPKTBUF_WMAC_LBK_BF_HD 0x45d 175 #define R92C_FAST_EDCA_CTRL 0x460 176 #define R92C_RD_RESP_PKT_TH 0x463 177 #define R92C_INIRTS_RATE_SEL 0x480 178 #define R92C_INIDATA_RATE_SEL(macid) (0x484 + (macid)) 179 /* EDCA Configuration. */ 180 #define R92C_EDCA_VO_PARAM 0x500 181 #define R92C_EDCA_VI_PARAM 0x504 182 #define R92C_EDCA_BE_PARAM 0x508 183 #define R92C_EDCA_BK_PARAM 0x50c 184 #define R92C_BCNTCFG 0x510 185 #define R92C_PIFS 0x512 186 #define R92C_RDG_PIFS 0x513 187 #define R92C_SIFS_CCK 0x514 188 #define R92C_SIFS_OFDM 0x516 189 #define R92C_AGGR_BREAK_TIME 0x51a 190 #define R92C_SLOT 0x51b 191 #define R92C_TX_PTCL_CTRL 0x520 192 #define R92C_TXPAUSE 0x522 193 #define R92C_DIS_TXREQ_CLR 0x523 194 #define R92C_RD_CTRL 0x524 195 #define R92C_TBTT_PROHIBIT 0x540 196 #define R92C_RD_NAV_NXT 0x544 197 #define R92C_NAV_PROT_LEN 0x546 198 #define R92C_BCN_CTRL 0x550 199 #define R92C_USTIME_TSF 0x551 200 #define R92C_MBID_NUM 0x552 201 #define R92C_DUAL_TSF_RST 0x553 202 #define R92C_BCN_INTERVAL 0x554 203 #define R92C_DRVERLYINT 0x558 204 #define R92C_BCNDMATIM 0x559 205 #define R92C_ATIMWND 0x55a 206 #define R92C_BCN_MAX_ERR 0x55d 207 #define R92C_RXTSF_OFFSET_CCK 0x55e 208 #define R92C_RXTSF_OFFSET_OFDM 0x55f 209 #define R92C_TSFTR 0x560 210 #define R92C_INIT_TSFTR 0x564 211 #define R92C_PSTIMER 0x580 212 #define R92C_TIMER0 0x584 213 #define R92C_TIMER1 0x588 214 #define R92C_ACMHWCTRL 0x5c0 215 #define R92C_ACMRSTCTRL 0x5c1 216 #define R92C_ACMAVG 0x5c2 217 #define R92C_VO_ADMTIME 0x5c4 218 #define R92C_VI_ADMTIME 0x5c6 219 #define R92C_BE_ADMTIME 0x5c8 220 #define R92C_EDCA_RANDOM_GEN 0x5cc 221 #define R92C_SCH_TXCMD 0x5d0 222 /* WMAC Configuration. */ 223 #define R92C_APSD_CTRL 0x600 224 #define R92C_BWOPMODE 0x603 225 #define R92C_TCR 0x604 226 #define R92C_RCR 0x608 227 #define R92C_RX_DRVINFO_SZ 0x60f 228 #define R92C_MACID 0x610 229 #define R92C_BSSID 0x618 230 #define R92C_MAR 0x620 231 #define R92C_MAC_SPEC_SIFS 0x63a 232 #define R92C_R2T_SIFS 0x63c 233 #define R92C_T2T_SIFS 0x63e 234 #define R92C_ACKTO 0x640 235 #define R92C_CAMCMD 0x670 236 #define R92C_CAMWRITE 0x674 237 #define R92C_CAMREAD 0x678 238 #define R92C_CAMDBG 0x67c 239 #define R92C_SECCFG 0x680 240 #define R92C_RXFLTMAP0 0x6a0 241 #define R92C_RXFLTMAP1 0x6a2 242 #define R92C_RXFLTMAP2 0x6a4 243 244 /* Bits for R92C_SYS_ISO_CTRL. */ 245 #define R92C_SYS_ISO_CTRL_MD2PP 0x0001 246 #define R92C_SYS_ISO_CTRL_UA2USB 0x0002 247 #define R92C_SYS_ISO_CTRL_UD2CORE 0x0004 248 #define R92C_SYS_ISO_CTRL_PA2PCIE 0x0008 249 #define R92C_SYS_ISO_CTRL_PD2CORE 0x0010 250 #define R92C_SYS_ISO_CTRL_IP2MAC 0x0020 251 #define R92C_SYS_ISO_CTRL_DIOP 0x0040 252 #define R92C_SYS_ISO_CTRL_DIOE 0x0080 253 #define R92C_SYS_ISO_CTRL_EB2CORE 0x0100 254 #define R92C_SYS_ISO_CTRL_DIOR 0x0200 255 #define R92C_SYS_ISO_CTRL_PWC_EV25V 0x4000 256 #define R92C_SYS_ISO_CTRL_PWC_EV12V 0x8000 257 258 /* Bits for R92C_SYS_FUNC_EN. */ 259 #define R92C_SYS_FUNC_EN_BBRSTB 0x0001 260 #define R92C_SYS_FUNC_EN_BB_GLB_RST 0x0002 261 #define R92C_SYS_FUNC_EN_USBA 0x0004 262 #define R92C_SYS_FUNC_EN_UPLL 0x0008 263 #define R92C_SYS_FUNC_EN_USBD 0x0010 264 #define R92C_SYS_FUNC_EN_DIO_PCIE 0x0020 265 #define R92C_SYS_FUNC_EN_PCIEA 0x0040 266 #define R92C_SYS_FUNC_EN_PPLL 0x0080 267 #define R92C_SYS_FUNC_EN_PCIED 0x0100 268 #define R92C_SYS_FUNC_EN_DIOE 0x0200 269 #define R92C_SYS_FUNC_EN_CPUEN 0x0400 270 #define R92C_SYS_FUNC_EN_DCORE 0x0800 271 #define R92C_SYS_FUNC_EN_ELDR 0x1000 272 #define R92C_SYS_FUNC_EN_DIO_RF 0x2000 273 #define R92C_SYS_FUNC_EN_HWPDN 0x4000 274 #define R92C_SYS_FUNC_EN_MREGEN 0x8000 275 276 /* Bits for R92C_APS_FSMCO. */ 277 #define R92C_APS_FSMCO_PFM_LDALL 0x00000001 278 #define R92C_APS_FSMCO_PFM_ALDN 0x00000002 279 #define R92C_APS_FSMCO_PFM_LDKP 0x00000004 280 #define R92C_APS_FSMCO_PFM_WOWL 0x00000008 281 #define R92C_APS_FSMCO_PDN_EN 0x00000010 282 #define R92C_APS_FSMCO_PDN_PL 0x00000020 283 #define R92C_APS_FSMCO_APFM_ONMAC 0x00000100 284 #define R92C_APS_FSMCO_APFM_OFF 0x00000200 285 #define R92C_APS_FSMCO_APFM_RSM 0x00000400 286 #define R92C_APS_FSMCO_AFSM_HSUS 0x00000800 287 #define R92C_APS_FSMCO_AFSM_PCIE 0x00001000 288 #define R92C_APS_FSMCO_APDM_MAC 0x00002000 289 #define R92C_APS_FSMCO_APDM_HOST 0x00004000 290 #define R92C_APS_FSMCO_APDM_HPDN 0x00008000 291 #define R92C_APS_FSMCO_RDY_MACON 0x00010000 292 #define R92C_APS_FSMCO_SUS_HOST 0x00020000 293 #define R92C_APS_FSMCO_ROP_ALD 0x00100000 294 #define R92C_APS_FSMCO_ROP_PWR 0x00200000 295 #define R92C_APS_FSMCO_ROP_SPS 0x00400000 296 #define R92C_APS_FSMCO_SOP_MRST 0x02000000 297 #define R92C_APS_FSMCO_SOP_FUSE 0x04000000 298 #define R92C_APS_FSMCO_SOP_ABG 0x08000000 299 #define R92C_APS_FSMCO_SOP_AMB 0x10000000 300 #define R92C_APS_FSMCO_SOP_RCK 0x20000000 301 #define R92C_APS_FSMCO_SOP_A8M 0x40000000 302 #define R92C_APS_FSMCO_XOP_BTCK 0x80000000 303 304 /* Bits for R92C_SYS_CLKR. */ 305 #define R92C_SYS_CLKR_ANAD16V_EN 0x00000001 306 #define R92C_SYS_CLKR_ANA8M 0x00000002 307 #define R92C_SYS_CLKR_MACSLP 0x00000010 308 #define R92C_SYS_CLKR_LOADER_EN 0x00000020 309 #define R92C_SYS_CLKR_80M_SSC_DIS 0x00000080 310 #define R92C_SYS_CLKR_80M_SSC_EN_HO 0x00000100 311 #define R92C_SYS_CLKR_PHY_SSC_RSTB 0x00000200 312 #define R92C_SYS_CLKR_SEC_EN 0x00000400 313 #define R92C_SYS_CLKR_MAC_EN 0x00000800 314 #define R92C_SYS_CLKR_SYS_EN 0x00001000 315 #define R92C_SYS_CLKR_RING_EN 0x00002000 316 317 /* Bits for R92C_RF_CTRL. */ 318 #define R92C_RF_CTRL_EN 0x01 319 #define R92C_RF_CTRL_RSTB 0x02 320 #define R92C_RF_CTRL_SDMRSTB 0x04 321 322 /* Bits for R92C_LDOV12D_CTRL. */ 323 #define R92C_LDOV12D_CTRL_LDV12_EN 0x01 324 325 /* Bits for R92C_EFUSE_CTRL. */ 326 #define R92C_EFUSE_CTRL_DATA_M 0x000000ff 327 #define R92C_EFUSE_CTRL_DATA_S 0 328 #define R92C_EFUSE_CTRL_ADDR_M 0x0003ff00 329 #define R92C_EFUSE_CTRL_ADDR_S 8 330 #define R92C_EFUSE_CTRL_VALID 0x80000000 331 332 /* Bits for R92C_GPIO_MUXCFG. */ 333 #define R92C_GPIO_MUXCFG_RFKILL 0x0008 334 #define R92C_GPIO_MUXCFG_ENBT 0x0020 335 336 /* Bits for R92C_GPIO_IO_SEL. */ 337 #define R92C_GPIO_IO_SEL_RFKILL 0x0008 338 339 /* Bits for R92C_LEDCFG0. */ 340 #define R92C_LEDCFG0_DIS 0x08 341 342 /* Bits for R92C_LEDCFG2. */ 343 #define R92C_LEDCFG2_EN 0x60 344 #define R92C_LEDCFG2_DIS 0x68 345 346 /* Bits for R92C_MCUFWDL. */ 347 #define R92C_MCUFWDL_EN 0x00000001 348 #define R92C_MCUFWDL_RDY 0x00000002 349 #define R92C_MCUFWDL_CHKSUM_RPT 0x00000004 350 #define R92C_MCUFWDL_MACINI_RDY 0x00000008 351 #define R92C_MCUFWDL_BBINI_RDY 0x00000010 352 #define R92C_MCUFWDL_RFINI_RDY 0x00000020 353 #define R92C_MCUFWDL_WINTINI_RDY 0x00000040 354 #define R92C_MCUFWDL_RAM_DL_SEL 0x00000080 /* 1: RAM, 0: ROM */ 355 #define R92C_MCUFWDL_PAGE_M 0x00070000 356 #define R92C_MCUFWDL_PAGE_S 16 357 #define R92C_MCUFWDL_CPRST 0x00800000 358 359 /* Bits for R92C_HPON_FSM. */ 360 #define R92C_HPON_FSM_CHIP_BONDING_ID_S 22 361 #define R92C_HPON_FSM_CHIP_BONDING_ID_M 0x00c00000 362 #define R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R 1 363 364 /* Bits for R92C_SYS_CFG. */ 365 #define R92C_SYS_CFG_XCLK_VLD 0x00000001 366 #define R92C_SYS_CFG_ACLK_VLD 0x00000002 367 #define R92C_SYS_CFG_UCLK_VLD 0x00000004 368 #define R92C_SYS_CFG_PCLK_VLD 0x00000008 369 #define R92C_SYS_CFG_PCIRSTB 0x00000010 370 #define R92C_SYS_CFG_V15_VLD 0x00000020 371 #define R92C_SYS_CFG_TRP_B15V_EN 0x00000080 372 #define R92C_SYS_CFG_SIC_IDLE 0x00000100 373 #define R92C_SYS_CFG_BD_MAC2 0x00000200 374 #define R92C_SYS_CFG_BD_MAC1 0x00000400 375 #define R92C_SYS_CFG_IC_MACPHY_MODE 0x00000800 376 #define R92C_SYS_CFG_CHIP_VER_RTL_M 0x0000f000 377 #define R92C_SYS_CFG_CHIP_VER_RTL_S 12 378 #define R92C_SYS_CFG_BT_FUNC 0x00010000 379 #define R92C_SYS_CFG_VENDOR_UMC 0x00080000 380 #define R92C_SYS_CFG_PAD_HWPD_IDN 0x00400000 381 #define R92C_SYS_CFG_TRP_VAUX_EN 0x00800000 382 #define R92C_SYS_CFG_TRP_BT_EN 0x01000000 383 #define R92C_SYS_CFG_BD_PKG_SEL 0x02000000 384 #define R92C_SYS_CFG_BD_HCI_SEL 0x04000000 385 #define R92C_SYS_CFG_TYPE_92C 0x08000000 386 387 /* Bits for R92C_CR. */ 388 #define R92C_CR_HCI_TXDMA_EN 0x00000001 389 #define R92C_CR_HCI_RXDMA_EN 0x00000002 390 #define R92C_CR_TXDMA_EN 0x00000004 391 #define R92C_CR_RXDMA_EN 0x00000008 392 #define R92C_CR_PROTOCOL_EN 0x00000010 393 #define R92C_CR_SCHEDULE_EN 0x00000020 394 #define R92C_CR_MACTXEN 0x00000040 395 #define R92C_CR_MACRXEN 0x00000080 396 #define R92C_CR_ENSEC 0x00000200 397 #define R92C_CR_NETTYPE_S 16 398 #define R92C_CR_NETTYPE_M 0x00030000 399 #define R92C_CR_NETTYPE_NOLINK 0 400 #define R92C_CR_NETTYPE_ADHOC 1 401 #define R92C_CR_NETTYPE_INFRA 2 402 #define R92C_CR_NETTYPE_AP 3 403 404 /* Bits for R92C_PBP. */ 405 #define R92C_PBP_PSRX_M 0x0f 406 #define R92C_PBP_PSRX_S 0 407 #define R92C_PBP_PSTX_M 0xf0 408 #define R92C_PBP_PSTX_S 4 409 #define R92C_PBP_64 0 410 #define R92C_PBP_128 1 411 #define R92C_PBP_256 2 412 #define R92C_PBP_512 3 413 #define R92C_PBP_1024 4 414 415 /* Bits for R92C_TRXDMA_CTRL. */ 416 #define R92C_TRXDMA_CTRL_RXDMA_AGG_EN 0x0004 417 #define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_M 0x0030 418 #define R92C_TRXDMA_CTRL_TXDMA_VOQ_MAP_S 4 419 #define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_M 0x00c0 420 #define R92C_TRXDMA_CTRL_TXDMA_VIQ_MAP_S 6 421 #define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_M 0x0300 422 #define R92C_TRXDMA_CTRL_TXDMA_BEQ_MAP_S 8 423 #define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_M 0x0c00 424 #define R92C_TRXDMA_CTRL_TXDMA_BKQ_MAP_S 10 425 #define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_M 0x3000 426 #define R92C_TRXDMA_CTRL_TXDMA_MGQ_MAP_S 12 427 #define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_M 0xc000 428 #define R92C_TRXDMA_CTRL_TXDMA_HIQ_MAP_S 14 429 #define R92C_TRXDMA_CTRL_QUEUE_LOW 1 430 #define R92C_TRXDMA_CTRL_QUEUE_NORMAL 2 431 #define R92C_TRXDMA_CTRL_QUEUE_HIGH 3 432 #define R92C_TRXDMA_CTRL_QMAP_M 0xfff0 433 #define R92C_TRXDMA_CTRL_QMAP_S 4 434 /* Shortcuts. */ 435 #define R92C_TRXDMA_CTRL_QMAP_3EP 0xf5b0 436 #define R92C_TRXDMA_CTRL_QMAP_HQ_LQ 0xf5f0 437 #define R92C_TRXDMA_CTRL_QMAP_HQ_NQ 0xfaf0 438 #define R92C_TRXDMA_CTRL_QMAP_LQ 0x5550 439 #define R92C_TRXDMA_CTRL_QMAP_NQ 0xaaa0 440 #define R92C_TRXDMA_CTRL_QMAP_HQ 0xfff0 441 442 /* Bits for R92C_LLT_INIT. */ 443 #define R92C_LLT_INIT_DATA_M 0x000000ff 444 #define R92C_LLT_INIT_DATA_S 0 445 #define R92C_LLT_INIT_ADDR_M 0x0000ff00 446 #define R92C_LLT_INIT_ADDR_S 8 447 #define R92C_LLT_INIT_OP_M 0xc0000000 448 #define R92C_LLT_INIT_OP_S 30 449 #define R92C_LLT_INIT_OP_NO_ACTIVE 0 450 #define R92C_LLT_INIT_OP_WRITE 1 451 452 /* Bits for R92C_RQPN. */ 453 #define R92C_RQPN_HPQ_M 0x000000ff 454 #define R92C_RQPN_HPQ_S 0 455 #define R92C_RQPN_LPQ_M 0x0000ff00 456 #define R92C_RQPN_LPQ_S 8 457 #define R92C_RQPN_PUBQ_M 0x00ff0000 458 #define R92C_RQPN_PUBQ_S 16 459 #define R92C_RQPN_LD 0x80000000 460 461 /* Bits for R92C_TDECTRL. */ 462 #define R92C_TDECTRL_BLK_DESC_NUM_M 0x0000000f 463 #define R92C_TDECTRL_BLK_DESC_NUM_S 4 464 465 /* Bits for R92C_FWHW_TXQ_CTRL. */ 466 #define R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW 0x80 467 468 /* Bits for R92C_SPEC_SIFS. */ 469 #define R92C_SPEC_SIFS_CCK_M 0x00ff 470 #define R92C_SPEC_SIFS_CCK_S 0 471 #define R92C_SPEC_SIFS_OFDM_M 0xff00 472 #define R92C_SPEC_SIFS_OFDM_S 8 473 474 /* Bits for R92C_RL. */ 475 #define R92C_RL_LRL_M 0x003f 476 #define R92C_RL_LRL_S 0 477 #define R92C_RL_SRL_M 0x3f00 478 #define R92C_RL_SRL_S 8 479 480 /* Bits for R92C_RRSR. */ 481 #define R92C_RRSR_RATE_BITMAP_M 0x000fffff 482 #define R92C_RRSR_RATE_BITMAP_S 0 483 #define R92C_RRSR_RATE_CCK_ONLY_1M 0xffff1 484 #define R92C_RRSR_RATE_ALL 0xfffff 485 #define R92C_RRSR_RSC_LOWSUBCHNL 0x00200000 486 #define R92C_RRSR_RSC_UPSUBCHNL 0x00400000 487 #define R92C_RRSR_SHORT 0x00800000 488 489 /* Bits for R92C_EDCA_XX_PARAM. */ 490 #define R92C_EDCA_PARAM_AIFS_M 0x000000ff 491 #define R92C_EDCA_PARAM_AIFS_S 0 492 #define R92C_EDCA_PARAM_ECWMIN_M 0x00000f00 493 #define R92C_EDCA_PARAM_ECWMIN_S 8 494 #define R92C_EDCA_PARAM_ECWMAX_M 0x0000f000 495 #define R92C_EDCA_PARAM_ECWMAX_S 12 496 #define R92C_EDCA_PARAM_TXOP_M 0xffff0000 497 #define R92C_EDCA_PARAM_TXOP_S 16 498 499 /* Bits for R92C_TXPAUSE. */ 500 #define R92C_TXPAUSE_AC_VO 0x01 501 #define R92C_TXPAUSE_AC_VI 0x02 502 #define R92C_TXPAUSE_AC_BE 0x04 503 #define R92C_TXPAUSE_AC_BK 0x08 504 505 /* Bits for R92C_BCN_CTRL. */ 506 #define R92C_BCN_CTRL_EN_MBSSID 0x02 507 #define R92C_BCN_CTRL_TXBCN_RPT 0x04 508 #define R92C_BCN_CTRL_EN_BCN 0x08 509 #define R92C_BCN_CTRL_DIS_TSF_UDT0 0x10 510 511 /* Bits for R92C_APSD_CTRL. */ 512 #define R92C_APSD_CTRL_OFF 0x40 513 #define R92C_APSD_CTRL_OFF_STATUS 0x80 514 515 /* Bits for R92C_BWOPMODE. */ 516 #define R92C_BWOPMODE_11J 0x01 517 #define R92C_BWOPMODE_5G 0x02 518 #define R92C_BWOPMODE_20MHZ 0x04 519 520 /* Bits for R92C_TCR. */ 521 #define R92C_TCR_TSFRST 0x00000001 522 #define R92C_TCR_DIS_GCLK 0x00000002 523 #define R92C_TCR_PAD_SEL 0x00000004 524 #define R92C_TCR_PWR_ST 0x00000040 525 #define R92C_TCR_PWRBIT_OW_EN 0x00000080 526 #define R92C_TCR_ACRC 0x00000100 527 #define R92C_TCR_CFENDFORM 0x00000200 528 #define R92C_TCR_ICV 0x00000400 529 530 /* Bits for R92C_RCR. */ 531 #define R92C_RCR_AAP 0x00000001 532 #define R92C_RCR_APM 0x00000002 533 #define R92C_RCR_AM 0x00000004 534 #define R92C_RCR_AB 0x00000008 535 #define R92C_RCR_ADD3 0x00000010 536 #define R92C_RCR_APWRMGT 0x00000020 537 #define R92C_RCR_CBSSID_DATA 0x00000040 538 #define R92C_RCR_CBSSID_BCN 0x00000080 539 #define R92C_RCR_ACRC32 0x00000100 540 #define R92C_RCR_AICV 0x00000200 541 #define R92C_RCR_ADF 0x00000800 542 #define R92C_RCR_ACF 0x00001000 543 #define R92C_RCR_AMF 0x00002000 544 #define R92C_RCR_HTC_LOC_CTRL 0x00004000 545 #define R92C_RCR_MFBEN 0x00400000 546 #define R92C_RCR_LSIGEN 0x00800000 547 #define R92C_RCR_ENMBID 0x01000000 548 #define R92C_RCR_APP_BA_SSN 0x08000000 549 #define R92C_RCR_APP_PHYSTS 0x10000000 550 #define R92C_RCR_APP_ICV 0x20000000 551 #define R92C_RCR_APP_MIC 0x40000000 552 #define R92C_RCR_APPFCS 0x80000000 553 554 /* Bits for R92C_CAMCMD. */ 555 #define R92C_CAMCMD_ADDR_M 0x0000ffff 556 #define R92C_CAMCMD_ADDR_S 0 557 #define R92C_CAMCMD_WRITE 0x00010000 558 #define R92C_CAMCMD_CLR 0x40000000 559 #define R92C_CAMCMD_POLLING 0x80000000 560 561 /* IMR */ 562 563 /*Beacon DMA interrupt 6 */ 564 #define R92C_IMR_BCNDMAINT6 0x80000000 565 /*Beacon DMA interrupt 5 */ 566 #define R92C_IMR_BCNDMAINT5 0x40000000 567 /*Beacon DMA interrupt 4 */ 568 #define R92C_IMR_BCNDMAINT4 0x20000000 569 /*Beacon DMA interrupt 3 */ 570 #define R92C_IMR_BCNDMAINT3 0x10000000 571 /*Beacon DMA interrupt 2 */ 572 #define R92C_IMR_BCNDMAINT2 0x08000000 573 /*Beacon DMA interrupt 1 */ 574 #define R92C_IMR_BCNDMAINT1 0x04000000 575 /*Beacon Queue DMA OK interrupt 8 */ 576 #define R92C_IMR_BCNDOK8 0x02000000 577 /*Beacon Queue DMA OK interrupt 7 */ 578 #define R92C_IMR_BCNDOK7 0x01000000 579 /*Beacon Queue DMA OK interrupt 6 */ 580 #define R92C_IMR_BCNDOK6 0x00800000 581 /*Beacon Queue DMA OK interrupt 5 */ 582 #define R92C_IMR_BCNDOK5 0x00400000 583 /*Beacon Queue DMA OK interrupt 4 */ 584 #define R92C_IMR_BCNDOK4 0x00200000 585 /*Beacon Queue DMA OK interrupt 3 */ 586 #define R92C_IMR_BCNDOK3 0x00100000 587 /*Beacon Queue DMA OK interrupt 2 */ 588 #define R92C_IMR_BCNDOK2 0x00080000 589 /*Beacon Queue DMA OK interrupt 1 */ 590 #define R92C_IMR_BCNDOK1 0x00040000 591 /*Timeout interrupt 2 */ 592 #define R92C_IMR_TIMEOUT2 0x00020000 593 /*Timeout interrupt 1 */ 594 #define R92C_IMR_TIMEOUT1 0x00010000 595 /*Transmit FIFO Overflow */ 596 #define R92C_IMR_TXFOVW 0x00008000 597 /*Power save time out interrupt */ 598 #define R92C_IMR_PSTIMEOUT 0x00004000 599 /*Beacon DMA interrupt 0 */ 600 #define R92C_IMR_BCNINT 0x00002000 601 /*Receive FIFO Overflow */ 602 #define R92C_IMR_RXFOVW 0x00001000 603 /*Receive Descriptor Unavailable */ 604 #define R92C_IMR_RDU 0x00000800 605 /*For 92C,ATIM Window End interrupt */ 606 #define R92C_IMR_ATIMEND 0x00000400 607 /*Beacon Queue DMA OK interrupt */ 608 #define R92C_IMR_BDOK 0x00000200 609 /*High Queue DMA OK interrupt */ 610 #define R92C_IMR_HIGHDOK 0x00000100 611 /*Transmit Beacon OK interrupt */ 612 #define R92C_IMR_TBDOK 0x00000080 613 /*Management Queue DMA OK interrupt */ 614 #define R92C_IMR_MGNTDOK 0x00000040 615 /*For 92C,Transmit Beacon Error interrupt */ 616 #define R92C_IMR_TBDER 0x00000020 617 /*AC_BK DMA OK interrupt */ 618 #define R92C_IMR_BKDOK 0x00000010 619 /*AC_BE DMA OK interrupt */ 620 #define R92C_IMR_BEDOK 0x00000008 621 /*AC_VI DMA OK interrupt */ 622 #define R92C_IMR_VIDOK 0x00000004 623 /*AC_VO DMA interrupt */ 624 #define R92C_IMR_VODOK 0x00000002 625 /*Receive DMA OK interrupt */ 626 #define R92C_IMR_ROK 0x00000001 627 628 #define R92C_IBSS_INT_MASK (R92C_IMR_BCNINT | R92C_IMR_TBDOK | R92C_IMR_TBDER) 629 630 /* 631 * Baseband registers. 632 */ 633 #define R92C_FPGA0_RFMOD 0x800 634 #define R92C_FPGA0_TXINFO 0x804 635 #define R92C_HSSI_PARAM1(chain) (0x820 + (chain) * 8) 636 #define R92C_HSSI_PARAM2(chain) (0x824 + (chain) * 8) 637 #define R92C_TXAGC_RATE18_06(i) (((i) == 0) ? 0xe00 : 0x830) 638 #define R92C_TXAGC_RATE54_24(i) (((i) == 0) ? 0xe04 : 0x834) 639 #define R92C_TXAGC_A_CCK1_MCS32 0xe08 640 #define R92C_TXAGC_B_CCK1_55_MCS32 0x838 641 #define R92C_TXAGC_B_CCK11_A_CCK2_11 0x86c 642 #define R92C_TXAGC_MCS03_MCS00(i) (((i) == 0) ? 0xe10 : 0x83c) 643 #define R92C_TXAGC_MCS07_MCS04(i) (((i) == 0) ? 0xe14 : 0x848) 644 #define R92C_TXAGC_MCS11_MCS08(i) (((i) == 0) ? 0xe18 : 0x84c) 645 #define R92C_TXAGC_MCS15_MCS12(i) (((i) == 0) ? 0xe1c : 0x868) 646 #define R92C_LSSI_PARAM(chain) (0x840 + (chain) * 4) 647 #define R92C_FPGA0_RFIFACEOE(chain) (0x860 + (chain) * 4) 648 #define R92C_FPGA0_RFIFACESW(idx) (0x870 + (idx) * 4) 649 #define R92C_FPGA0_RFPARAM(idx) (0x878 + (idx) * 4) 650 #define R92C_FPGA0_ANAPARAM2 0x884 651 #define R92C_LSSI_READBACK(chain) (0x8a0 + (chain) * 4) 652 #define R92C_HSPI_READBACK(chain) (0x8b8 + (chain) * 4) 653 #define R92C_FPGA1_RFMOD 0x900 654 #define R92C_FPGA1_TXINFO 0x90c 655 #define R92C_CCK0_SYSTEM 0xa00 656 #define R92C_CCK0_AFESETTING 0xa04 657 #define R92C_OFDM0_TRXPATHENA 0xc04 658 #define R92C_OFDM0_TRMUXPAR 0xc08 659 #define R92C_OFDM0_RXIQIMBALANCE(chain) (0xc14 + (chain) * 8) 660 #define R92C_OFDM0_ECCATHRESHOLD 0xc4c 661 #define R92C_OFDM0_AGCCORE1(chain) (0xc50 + (chain) * 8) 662 #define R92C_OFDM0_AGCPARAM1 0xc70 663 #define R92C_OFDM0_AGCRSSITABLE 0xc78 664 #define R92C_OFDM0_TXIQIMBALANCE(chain) (0xc80 + (chain) * 8) 665 #define R92C_OFDM0_TXAFE(chain) (0xc94 + (chain) * 8) 666 #define R92C_OFDM0_RXIQEXTANTA 0xca0 667 #define R92C_OFDM1_LSTF 0xd00 668 669 /* Bits for R92C_FPGA[01]_RFMOD. */ 670 #define R92C_RFMOD_40MHZ 0x00000001 671 #define R92C_RFMOD_JAPAN 0x00000002 672 #define R92C_RFMOD_CCK_TXSC 0x00000030 673 #define R92C_RFMOD_CCK_EN 0x01000000 674 #define R92C_RFMOD_OFDM_EN 0x02000000 675 676 /* Bits for R92C_HSSI_PARAM1(i). */ 677 #define R92C_HSSI_PARAM1_PI 0x00000100 678 679 /* Bits for R92C_HSSI_PARAM2(i). */ 680 #define R92C_HSSI_PARAM2_CCK_HIPWR 0x00000200 681 #define R92C_HSSI_PARAM2_ADDR_LENGTH 0x00000400 682 #define R92C_HSSI_PARAM2_DATA_LENGTH 0x00000800 683 #define R92C_HSSI_PARAM2_READ_ADDR_M 0x7f800000 684 #define R92C_HSSI_PARAM2_READ_ADDR_S 23 685 #define R92C_HSSI_PARAM2_READ_EDGE 0x80000000 686 687 /* Bits for R92C_TXAGC_A_CCK1_MCS32. */ 688 #define R92C_TXAGC_A_CCK1_M 0x0000ff00 689 #define R92C_TXAGC_A_CCK1_S 8 690 691 /* Bits for R92C_TXAGC_B_CCK11_A_CCK2_11. */ 692 #define R92C_TXAGC_B_CCK11_M 0x000000ff 693 #define R92C_TXAGC_B_CCK11_S 0 694 #define R92C_TXAGC_A_CCK2_M 0x0000ff00 695 #define R92C_TXAGC_A_CCK2_S 8 696 #define R92C_TXAGC_A_CCK55_M 0x00ff0000 697 #define R92C_TXAGC_A_CCK55_S 16 698 #define R92C_TXAGC_A_CCK11_M 0xff000000 699 #define R92C_TXAGC_A_CCK11_S 24 700 701 /* Bits for R92C_TXAGC_B_CCK1_55_MCS32. */ 702 #define R92C_TXAGC_B_CCK1_M 0x0000ff00 703 #define R92C_TXAGC_B_CCK1_S 8 704 #define R92C_TXAGC_B_CCK2_M 0x00ff0000 705 #define R92C_TXAGC_B_CCK2_S 16 706 #define R92C_TXAGC_B_CCK55_M 0xff000000 707 #define R92C_TXAGC_B_CCK55_S 24 708 709 /* Bits for R92C_TXAGC_RATE18_06(x). */ 710 #define R92C_TXAGC_RATE06_M 0x000000ff 711 #define R92C_TXAGC_RATE06_S 0 712 #define R92C_TXAGC_RATE09_M 0x0000ff00 713 #define R92C_TXAGC_RATE09_S 8 714 #define R92C_TXAGC_RATE12_M 0x00ff0000 715 #define R92C_TXAGC_RATE12_S 16 716 #define R92C_TXAGC_RATE18_M 0xff000000 717 #define R92C_TXAGC_RATE18_S 24 718 719 /* Bits for R92C_TXAGC_RATE54_24(x). */ 720 #define R92C_TXAGC_RATE24_M 0x000000ff 721 #define R92C_TXAGC_RATE24_S 0 722 #define R92C_TXAGC_RATE36_M 0x0000ff00 723 #define R92C_TXAGC_RATE36_S 8 724 #define R92C_TXAGC_RATE48_M 0x00ff0000 725 #define R92C_TXAGC_RATE48_S 16 726 #define R92C_TXAGC_RATE54_M 0xff000000 727 #define R92C_TXAGC_RATE54_S 24 728 729 /* Bits for R92C_TXAGC_MCS03_MCS00(x). */ 730 #define R92C_TXAGC_MCS00_M 0x000000ff 731 #define R92C_TXAGC_MCS00_S 0 732 #define R92C_TXAGC_MCS01_M 0x0000ff00 733 #define R92C_TXAGC_MCS01_S 8 734 #define R92C_TXAGC_MCS02_M 0x00ff0000 735 #define R92C_TXAGC_MCS02_S 16 736 #define R92C_TXAGC_MCS03_M 0xff000000 737 #define R92C_TXAGC_MCS03_S 24 738 739 /* Bits for R92C_TXAGC_MCS07_MCS04(x). */ 740 #define R92C_TXAGC_MCS04_M 0x000000ff 741 #define R92C_TXAGC_MCS04_S 0 742 #define R92C_TXAGC_MCS05_M 0x0000ff00 743 #define R92C_TXAGC_MCS05_S 8 744 #define R92C_TXAGC_MCS06_M 0x00ff0000 745 #define R92C_TXAGC_MCS06_S 16 746 #define R92C_TXAGC_MCS07_M 0xff000000 747 #define R92C_TXAGC_MCS07_S 24 748 749 /* Bits for R92C_TXAGC_MCS11_MCS08(x). */ 750 #define R92C_TXAGC_MCS08_M 0x000000ff 751 #define R92C_TXAGC_MCS08_S 0 752 #define R92C_TXAGC_MCS09_M 0x0000ff00 753 #define R92C_TXAGC_MCS09_S 8 754 #define R92C_TXAGC_MCS10_M 0x00ff0000 755 #define R92C_TXAGC_MCS10_S 16 756 #define R92C_TXAGC_MCS11_M 0xff000000 757 #define R92C_TXAGC_MCS11_S 24 758 759 /* Bits for R92C_TXAGC_MCS15_MCS12(x). */ 760 #define R92C_TXAGC_MCS12_M 0x000000ff 761 #define R92C_TXAGC_MCS12_S 0 762 #define R92C_TXAGC_MCS13_M 0x0000ff00 763 #define R92C_TXAGC_MCS13_S 8 764 #define R92C_TXAGC_MCS14_M 0x00ff0000 765 #define R92C_TXAGC_MCS14_S 16 766 #define R92C_TXAGC_MCS15_M 0xff000000 767 #define R92C_TXAGC_MCS15_S 24 768 769 /* Bits for R92C_LSSI_PARAM(i). */ 770 #define R92C_LSSI_PARAM_DATA_M 0x000fffff 771 #define R92C_LSSI_PARAM_DATA_S 0 772 #define R92C_LSSI_PARAM_ADDR_M 0x03f00000 773 #define R92C_LSSI_PARAM_ADDR_S 20 774 775 /* Bits for R92C_FPGA0_ANAPARAM2. */ 776 #define R92C_FPGA0_ANAPARAM2_CBW20 0x00000400 777 778 /* Bits for R92C_LSSI_READBACK(i). */ 779 #define R92C_LSSI_READBACK_DATA_M 0x000fffff 780 #define R92C_LSSI_READBACK_DATA_S 0 781 782 /* Bits for R92C_OFDM0_AGCCORE1(i). */ 783 #define R92C_OFDM0_AGCCORE1_GAIN_M 0x0000007f 784 #define R92C_OFDM0_AGCCORE1_GAIN_S 0 785 786 787 /* 788 * USB registers. 789 */ 790 #define R92C_USB_INFO 0xfe17 791 #define R92C_USB_SPECIAL_OPTION 0xfe55 792 #define R92C_USB_HCPWM 0xfe57 793 #define R92C_USB_HRPWM 0xfe58 794 #define R92C_USB_DMA_AGG_TO 0xfe5b 795 #define R92C_USB_AGG_TO 0xfe5c 796 #define R92C_USB_AGG_TH 0xfe5d 797 #define R92C_USB_VID 0xfe60 798 #define R92C_USB_PID 0xfe62 799 #define R92C_USB_OPTIONAL 0xfe64 800 #define R92C_USB_EP 0xfe65 801 #define R92C_USB_PHY 0xfe68 802 #define R92C_USB_MAC_ADDR 0xfe70 803 #define R92C_USB_STRING 0xfe80 804 805 /* Bits for R92C_USB_SPECIAL_OPTION. */ 806 #define R92C_USB_SPECIAL_OPTION_AGG_EN 0x08 807 808 /* Bits for R92C_USB_EP. */ 809 #define R92C_USB_EP_HQ_M 0x000f 810 #define R92C_USB_EP_HQ_S 0 811 #define R92C_USB_EP_NQ_M 0x00f0 812 #define R92C_USB_EP_NQ_S 4 813 #define R92C_USB_EP_LQ_M 0x0f00 814 #define R92C_USB_EP_LQ_S 8 815 816 817 /* 818 * Firmware base address. 819 */ 820 #define R92C_FW_START_ADDR 0x1000 821 #define R92C_FW_PAGE_SIZE 4096 822 823 824 /* 825 * RF (6052) registers. 826 */ 827 #define R92C_RF_AC 0x00 828 #define R92C_RF_IQADJ_G(i) (0x01 + (i)) 829 #define R92C_RF_POW_TRSW 0x05 830 #define R92C_RF_GAIN_RX 0x06 831 #define R92C_RF_GAIN_TX 0x07 832 #define R92C_RF_TXM_IDAC 0x08 833 #define R92C_RF_BS_IQGEN 0x0f 834 #define R92C_RF_MODE1 0x10 835 #define R92C_RF_MODE2 0x11 836 #define R92C_RF_RX_AGC_HP 0x12 837 #define R92C_RF_TX_AGC 0x13 838 #define R92C_RF_BIAS 0x14 839 #define R92C_RF_IPA 0x15 840 #define R92C_RF_POW_ABILITY 0x17 841 #define R92C_RF_CHNLBW 0x18 842 #define R92C_RF_RX_G1 0x1a 843 #define R92C_RF_RX_G2 0x1b 844 #define R92C_RF_RX_BB2 0x1c 845 #define R92C_RF_RX_BB1 0x1d 846 #define R92C_RF_RCK1 0x1e 847 #define R92C_RF_RCK2 0x1f 848 #define R92C_RF_TX_G(i) (0x20 + (i)) 849 #define R92C_RF_TX_BB1 0x23 850 #define R92C_RF_T_METER 0x24 851 #define R92C_RF_SYN_G(i) (0x25 + (i)) 852 #define R92C_RF_RCK_OS 0x30 853 #define R92C_RF_TXPA_G(i) (0x31 + (i)) 854 855 /* Bits for R92C_RF_AC. */ 856 #define R92C_RF_AC_MODE_M 0x70000 857 #define R92C_RF_AC_MODE_S 16 858 #define R92C_RF_AC_MODE_STANDBY 1 859 860 /* Bits for R92C_RF_CHNLBW. */ 861 #define R92C_RF_CHNLBW_CHNL_M 0x003ff 862 #define R92C_RF_CHNLBW_CHNL_S 0 863 #define R92C_RF_CHNLBW_BW20 0x00400 864 #define R92C_RF_CHNLBW_LCSTART 0x08000 865 866 867 /* 868 * CAM entries. 869 */ 870 #define R92C_CAM_ENTRY_COUNT 32 871 872 #define R92C_CAM_CTL0(entry) ((entry) * 8 + 0) 873 #define R92C_CAM_CTL1(entry) ((entry) * 8 + 1) 874 #define R92C_CAM_KEY(entry, i) ((entry) * 8 + 2 + (i)) 875 876 /* Bits for R92C_CAM_CTL0(i). */ 877 #define R92C_CAM_KEYID_M 0x00000003 878 #define R92C_CAM_KEYID_S 0 879 #define R92C_CAM_ALGO_M 0x0000001c 880 #define R92C_CAM_ALGO_S 2 881 #define R92C_CAM_ALGO_NONE 0 882 #define R92C_CAM_ALGO_WEP40 1 883 #define R92C_CAM_ALGO_TKIP 2 884 #define R92C_CAM_ALGO_AES 4 885 #define R92C_CAM_ALGO_WEP104 5 886 #define R92C_CAM_VALID 0x00008000 887 #define R92C_CAM_MACLO_M 0xffff0000 888 #define R92C_CAM_MACLO_S 16 889 890 /* Rate adaptation modes. */ 891 #define R92C_RAID_11GN 1 892 #define R92C_RAID_11N 3 893 #define R92C_RAID_11BG 4 894 #define R92C_RAID_11G 5 /* "pure" 11g */ 895 #define R92C_RAID_11B 6 896 897 898 /* Macros to access unaligned little-endian memory. */ 899 #define LE_READ_2(x) ((x)[0] | (x)[1] << 8) 900 #define LE_READ_4(x) ((x)[0] | (x)[1] << 8 | (x)[2] << 16 | (x)[3] << 24) 901 902 /* 903 * Macros to access subfields in registers. 904 */ 905 /* Mask and Shift (getter). */ 906 #define MS(val, field) \ 907 (((val) & field##_M) >> field##_S) 908 909 /* Shift and Mask (setter). */ 910 #define SM(field, val) \ 911 (((val) << field##_S) & field##_M) 912 913 /* Rewrite. */ 914 #define RW(var, field, val) \ 915 (((var) & ~field##_M) | SM(field, val)) 916 917 /* 918 * Firmware image header. 919 */ 920 struct r92c_fw_hdr { 921 /* QWORD0 */ 922 uint16_t signature; 923 uint8_t category; 924 uint8_t function; 925 uint16_t version; 926 uint16_t subversion; 927 /* QWORD1 */ 928 uint8_t month; 929 uint8_t date; 930 uint8_t hour; 931 uint8_t minute; 932 uint16_t ramcodesize; 933 uint16_t reserved2; 934 /* QWORD2 */ 935 uint32_t svnidx; 936 uint32_t reserved3; 937 /* QWORD3 */ 938 uint32_t reserved4; 939 uint32_t reserved5; 940 } __packed; 941 942 /* 943 * Host to firmware commands. 944 */ 945 struct r92c_fw_cmd { 946 uint8_t id; 947 #define R92C_CMD_AP_OFFLOAD 0 948 #define R92C_CMD_SET_PWRMODE 1 949 #define R92C_CMD_JOINBSS_RPT 2 950 #define R92C_CMD_RSVD_PAGE 3 951 #define R92C_CMD_RSSI 4 952 #define R92C_CMD_RSSI_SETTING 5 953 #define R92C_CMD_MACID_CONFIG 6 954 #define R92C_CMD_MACID_PS_MODE 7 955 #define R92C_CMD_P2P_PS_OFFLOAD 8 956 #define R92C_CMD_SELECTIVE_SUSPEND 9 957 #define R92C_CMD_FLAG_EXT 0x80 958 959 uint8_t msg[5]; 960 } __packed; 961 962 /* Structure for R92C_CMD_RSSI_SETTING. */ 963 struct r92c_fw_cmd_rssi { 964 uint8_t macid; 965 uint8_t reserved; 966 uint8_t pwdb; 967 } __packed; 968 969 /* Structure for R92C_CMD_MACID_CONFIG. */ 970 struct r92c_fw_cmd_macid_cfg { 971 uint32_t mask; 972 uint8_t macid; 973 #define RTWN_MACID_BSS 0 974 #define RTWN_MACID_BC 4 /* Broadcast. */ 975 #define RTWN_MACID_VALID 0x80 976 } __packed; 977 978 /* 979 * RTL8192CU ROM image. 980 */ 981 struct r92c_rom { 982 uint16_t id; /* 0x8129 */ 983 uint8_t reserved1[5]; 984 uint8_t dbg_sel; 985 uint16_t reserved2; 986 uint16_t vid; 987 uint16_t pid; 988 uint8_t usb_opt; 989 uint8_t ep_setting; 990 uint16_t reserved3; 991 uint8_t usb_phy; 992 uint8_t reserved4[3]; 993 uint8_t macaddr[6]; 994 uint8_t string[61]; /* "Realtek" */ 995 uint8_t subcustomer_id; 996 uint8_t cck_tx_pwr[R92C_MAX_CHAINS][3]; 997 uint8_t ht40_1s_tx_pwr[R92C_MAX_CHAINS][3]; 998 uint8_t ht40_2s_tx_pwr_diff[3]; 999 uint8_t ht20_tx_pwr_diff[3]; 1000 uint8_t ofdm_tx_pwr_diff[3]; 1001 uint8_t ht40_max_pwr[3]; 1002 uint8_t ht20_max_pwr[3]; 1003 uint8_t xtal_calib; 1004 uint8_t tssi[R92C_MAX_CHAINS]; 1005 uint8_t thermal_meter; 1006 uint8_t rf_opt1; 1007 #define R92C_ROM_RF1_REGULATORY_M 0x07 1008 #define R92C_ROM_RF1_REGULATORY_S 0 1009 #define R92C_ROM_RF1_BOARD_TYPE_M 0xe0 1010 #define R92C_ROM_RF1_BOARD_TYPE_S 5 1011 #define R92C_BOARD_TYPE_DONGLE 0 1012 #define R92C_BOARD_TYPE_HIGHPA 1 1013 #define R92C_BOARD_TYPE_MINICARD 2 1014 #define R92C_BOARD_TYPE_SOLO 3 1015 #define R92C_BOARD_TYPE_COMBO 4 1016 1017 uint8_t rf_opt2; 1018 uint8_t rf_opt3; 1019 uint8_t rf_opt4; 1020 uint8_t channel_plan; 1021 uint8_t version; 1022 uint8_t curstomer_id; 1023 } __packed; 1024 1025 /* Rx MAC descriptor. */ 1026 struct r92c_rx_desc { 1027 uint32_t rxdw0; 1028 #define R92C_RXDW0_PKTLEN_M 0x00003fff 1029 #define R92C_RXDW0_PKTLEN_S 0 1030 #define R92C_RXDW0_CRCERR 0x00004000 1031 #define R92C_RXDW0_ICVERR 0x00008000 1032 #define R92C_RXDW0_INFOSZ_M 0x000f0000 1033 #define R92C_RXDW0_INFOSZ_S 16 1034 #define R92C_RXDW0_QOS 0x00800000 1035 #define R92C_RXDW0_SHIFT_M 0x03000000 1036 #define R92C_RXDW0_SHIFT_S 24 1037 #define R92C_RXDW0_PHYST 0x04000000 1038 #define R92C_RXDW0_DECRYPTED 0x08000000 1039 #define R92C_RXDW0_LS 0x10000000 1040 #define R92C_RXDW0_FS 0x20000000 1041 #define R92C_RXDW0_EOR 0x40000000 1042 #define R92C_RXDW0_OWN 0x80000000 1043 1044 uint32_t rxdw1; 1045 uint32_t rxdw2; 1046 #define R92C_RXDW2_PKTCNT_M 0x00ff0000 1047 #define R92C_RXDW2_PKTCNT_S 16 1048 1049 uint32_t rxdw3; 1050 #define R92C_RXDW3_RATE_M 0x0000003f 1051 #define R92C_RXDW3_RATE_S 0 1052 #define R92C_RXDW3_HT 0x00000040 1053 #define R92C_RXDW3_HTC 0x00000400 1054 1055 uint32_t rxdw4; 1056 uint32_t rxdw5; 1057 1058 uint32_t rxbufaddr; 1059 uint32_t rxbufaddr64; 1060 } __packed __attribute__((aligned(4))); 1061 1062 /* Rx PHY descriptor. */ 1063 struct r92c_rx_phystat { 1064 uint32_t phydw0; 1065 uint32_t phydw1; 1066 uint32_t phydw2; 1067 uint32_t phydw3; 1068 uint32_t phydw4; 1069 uint32_t phydw5; 1070 uint32_t phydw6; 1071 uint32_t phydw7; 1072 } __packed __attribute__((aligned(4))); 1073 1074 /* Rx PHY CCK descriptor. */ 1075 struct r92c_rx_cck { 1076 uint8_t adc_pwdb[4]; 1077 uint8_t sq_rpt; 1078 uint8_t agc_rpt; 1079 } __packed; 1080 1081 /* Tx MAC descriptor. */ 1082 struct r92c_tx_desc { 1083 uint32_t txdw0; 1084 #define R92C_TXDW0_PKTLEN_M 0x0000ffff 1085 #define R92C_TXDW0_PKTLEN_S 0 1086 #define R92C_TXDW0_OFFSET_M 0x00ff0000 1087 #define R92C_TXDW0_OFFSET_S 16 1088 #define R92C_TXDW0_BMCAST 0x01000000 1089 #define R92C_TXDW0_LSG 0x04000000 1090 #define R92C_TXDW0_FSG 0x08000000 1091 #define R92C_TXDW0_OWN 0x80000000 1092 1093 uint32_t txdw1; 1094 #define R92C_TXDW1_MACID_M 0x0000001f 1095 #define R92C_TXDW1_MACID_S 0 1096 #define R92C_TXDW1_AGGEN 0x00000020 1097 #define R92C_TXDW1_AGGBK 0x00000040 1098 #define R92C_TXDW1_QSEL_M 0x00001f00 1099 #define R92C_TXDW1_QSEL_S 8 1100 #define R92C_TXDW1_QSEL_BE 0x00 1101 #define R92C_TXDW1_QSEL_BK 0x02 1102 #define R92C_TXDW1_QSEL_VI 0x05 1103 #define R92C_TXDW1_QSEL_VO 0x07 1104 #define R92C_TXDW1_QSEL_BEACON 0x10 1105 #define R92C_TXDW1_QSEL_HIGH 0x11 1106 #define R92C_TXDW1_QSEL_MGNT 0x12 1107 #define R92C_TXDW1_QSEL_CMD 0x13 1108 #define R92C_TXDW1_RAID_M 0x000f0000 1109 #define R92C_TXDW1_RAID_S 16 1110 #define R92C_TXDW1_CIPHER_M 0x00c00000 1111 #define R92C_TXDW1_CIPHER_S 22 1112 #define R92C_TXDW1_CIPHER_NONE 0 1113 #define R92C_TXDW1_CIPHER_RC4 1 1114 #define R92C_TXDW1_CIPHER_AES 3 1115 #define R92C_TXDW1_PKTOFF_M 0x7c000000 1116 #define R92C_TXDW1_PKTOFF_S 26 1117 1118 uint32_t txdw2; 1119 uint16_t txdw3; 1120 uint16_t txdseq; 1121 1122 uint32_t txdw4; 1123 #define R92C_TXDW4_RTSRATE_M 0x0000003f 1124 #define R92C_TXDW4_RTSRATE_S 0 1125 #define R92C_TXDW4_QOS 0x00000040 1126 #define R92C_TXDW4_HWSEQ 0x00000080 1127 #define R92C_TXDW4_DRVRATE 0x00000100 1128 #define R92C_TXDW4_CTS2SELF 0x00000800 1129 #define R92C_TXDW4_RTSEN 0x00001000 1130 #define R92C_TXDW4_HWRTSEN 0x00002000 1131 #define R92C_TXDW4_SCO_M 0x003f0000 1132 #define R92C_TXDW4_SCO_S 20 1133 #define R92C_TXDW4_SCO_SCA 1 1134 #define R92C_TXDW4_SCO_SCB 2 1135 #define R92C_TXDW4_40MHZ 0x02000000 1136 1137 uint32_t txdw5; 1138 #define R92C_TXDW5_DATARATE_M 0x0000003f 1139 #define R92C_TXDW5_DATARATE_S 0 1140 #define R92C_TXDW5_SGI 0x00000040 1141 #define R92C_TXDW5_DATARATE_FBLIMIT_M 0x00001f00 1142 #define R92C_TXDW5_DATARATE_FBLIMIT_S 8 1143 #define R92C_TXDW5_RTSRATE_FBLIMIT_M 0x0001e000 1144 #define R92C_TXDW5_RTSRATE_FBLIMIT_S 13 1145 #define R92C_TXDW5_RETRY_LIMIT_ENABLE 0x00020000 1146 #define R92C_TXDW5_DATA_RETRY_LIMIT_M 0x00fc0000 1147 #define R92C_TXDW5_DATA_RETRY_LIMIT_S 18 1148 #define R92C_TXDW5_AGGNUM_M 0xff000000 1149 #define R92C_TXDW5_AGGNUM_S 24 1150 1151 uint32_t txdw6; 1152 1153 uint16_t txbufsize; 1154 uint16_t pad; 1155 1156 uint32_t txbufaddr; 1157 uint32_t txbufaddr64; 1158 1159 uint32_t nextdescaddr; 1160 uint32_t nextdescaddr64; 1161 1162 uint32_t reserved[4]; 1163 } __packed __attribute__((aligned(4))); 1164 1165 1166 /* 1167 * Driver definitions. 1168 */ 1169 #define RTWN_NTXQUEUES 9 1170 #define RTWN_RX_LIST_COUNT 256 1171 #define RTWN_TX_LIST_COUNT 256 1172 #define RTWN_HOST_CMD_RING_COUNT 32 1173 1174 /* TX queue indices. */ 1175 #define RTWN_BK_QUEUE 0 1176 #define RTWN_BE_QUEUE 1 1177 #define RTWN_VI_QUEUE 2 1178 #define RTWN_VO_QUEUE 3 1179 #define RTWN_BEACON_QUEUE 4 1180 #define RTWN_TXCMD_QUEUE 5 1181 #define RTWN_MGNT_QUEUE 6 1182 #define RTWN_HIGH_QUEUE 7 1183 #define RTWN_HCCA_QUEUE 8 1184 1185 /* RX queue indices. */ 1186 #define RTWN_RX_QUEUE 0 1187 1188 #define RTWN_RXBUFSZ (16 * 1024) 1189 #define RTWN_TXBUFSZ (sizeof(struct r92c_tx_desc) + IEEE80211_MAX_LEN) 1190 1191 #define RTWN_RIDX_COUNT 28 1192 1193 #define RTWN_TX_TIMEOUT 5000 /* ms */ 1194 1195 #define RTWN_LED_LINK 0 1196 #define RTWN_LED_DATA 1 1197 1198 struct rtwn_rx_radiotap_header { 1199 struct ieee80211_radiotap_header wr_ihdr; 1200 uint8_t wr_flags; 1201 uint8_t wr_rate; 1202 uint16_t wr_chan_freq; 1203 uint16_t wr_chan_flags; 1204 uint8_t wr_dbm_antsignal; 1205 } __packed; 1206 1207 #define RTWN_RX_RADIOTAP_PRESENT \ 1208 (1 << IEEE80211_RADIOTAP_FLAGS | \ 1209 1 << IEEE80211_RADIOTAP_RATE | \ 1210 1 << IEEE80211_RADIOTAP_CHANNEL | \ 1211 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) 1212 1213 struct rtwn_tx_radiotap_header { 1214 struct ieee80211_radiotap_header wt_ihdr; 1215 uint8_t wt_flags; 1216 uint16_t wt_chan_freq; 1217 uint16_t wt_chan_flags; 1218 } __packed; 1219 1220 #define RTWN_TX_RADIOTAP_PRESENT \ 1221 (1 << IEEE80211_RADIOTAP_FLAGS | \ 1222 1 << IEEE80211_RADIOTAP_CHANNEL) 1223 1224 struct rtwn_softc; 1225 1226 struct rtwn_rx_data { 1227 bus_dmamap_t map; 1228 struct mbuf *m; 1229 bus_addr_t paddr; 1230 }; 1231 1232 struct rtwn_rx_ring { 1233 struct r92c_rx_desc *desc; 1234 bus_addr_t paddr; 1235 bus_dma_tag_t desc_dmat; 1236 bus_dmamap_t desc_map; 1237 bus_dma_tag_t data_dmat; 1238 bus_dma_segment_t seg; 1239 struct rtwn_rx_data rx_data[RTWN_RX_LIST_COUNT]; 1240 1241 }; 1242 struct rtwn_tx_data { 1243 bus_dmamap_t map; 1244 struct mbuf *m; 1245 struct ieee80211_node *ni; 1246 }; 1247 1248 struct rtwn_tx_ring { 1249 bus_addr_t paddr; 1250 bus_dma_tag_t desc_dmat; 1251 bus_dmamap_t desc_map; 1252 bus_dma_tag_t data_dmat; 1253 bus_dma_segment_t seg; 1254 struct r92c_tx_desc *desc; 1255 struct rtwn_tx_data tx_data[RTWN_TX_LIST_COUNT]; 1256 int queued; 1257 int cur; 1258 }; 1259 1260 struct rtwn_host_cmd { 1261 void (*cb)(struct rtwn_softc *, void *); 1262 uint8_t data[256]; 1263 }; 1264 1265 struct rtwn_cmd_key { 1266 struct ieee80211_key key; 1267 uint16_t associd; 1268 }; 1269 1270 struct rtwn_host_cmd_ring { 1271 struct rtwn_host_cmd cmd[RTWN_HOST_CMD_RING_COUNT]; 1272 int cur; 1273 int next; 1274 int queued; 1275 }; 1276 1277 struct rtwn_vap { 1278 struct ieee80211vap vap; 1279 int (*newstate)(struct ieee80211vap *, 1280 enum ieee80211_state, int); 1281 }; 1282 #define RTWN_VAP(vap) ((struct rtwn_vap *)(vap)) 1283 1284 struct rtwn_softc { 1285 device_t sc_dev; 1286 struct mtx sc_mtx; 1287 struct ieee80211com sc_ic; 1288 struct mbufq sc_snd; 1289 1290 struct resource *irq; 1291 struct resource *mem; 1292 bus_space_tag_t sc_st; 1293 bus_space_handle_t sc_sh; 1294 void *sc_ih; 1295 bus_size_t sc_mapsize; 1296 int sc_cap_off; 1297 1298 struct callout calib_to; 1299 struct callout watchdog_to; 1300 1301 int sc_debug; 1302 1303 u_int sc_flags; 1304 #define RTWN_FLAG_CCK_HIPWR 0x01 1305 #define RTWN_FLAG_BUSY 0x02 1306 #define RTWN_RUNNING 0x04 1307 1308 u_int chip; 1309 #define RTWN_CHIP_88C 0x00 1310 #define RTWN_CHIP_92C 0x01 1311 #define RTWN_CHIP_92C_1T2R 0x02 1312 #define RTWN_CHIP_UMC 0x04 1313 #define RTWN_CHIP_UMC_A_CUT 0x08 1314 1315 uint8_t board_type; 1316 uint8_t regulatory; 1317 uint8_t pa_setting; 1318 int avg_pwdb; 1319 int thcal_state; 1320 int thcal_lctemp; 1321 int ntxchains; 1322 int nrxchains; 1323 int ledlink; 1324 1325 int sc_tx_timer; 1326 int fwcur; 1327 struct rtwn_rx_ring rx_ring; 1328 struct rtwn_tx_ring tx_ring[RTWN_NTXQUEUES]; 1329 uint32_t qfullmsk; 1330 struct r92c_rom rom; 1331 1332 uint32_t rf_chnlbw[R92C_MAX_CHAINS]; 1333 1334 struct rtwn_rx_radiotap_header sc_rxtap; 1335 struct rtwn_tx_radiotap_header sc_txtap; 1336 }; 1337 1338 /* 1339 * MAC initialization values. 1340 */ 1341 static const struct { 1342 uint16_t reg; 1343 uint8_t val; 1344 } rtl8192ce_mac[] = { 1345 { 0x420, 0x80 }, { 0x423, 0x00 }, { 0x430, 0x00 }, { 0x431, 0x00 }, 1346 { 0x432, 0x00 }, { 0x433, 0x01 }, { 0x434, 0x04 }, { 0x435, 0x05 }, 1347 { 0x436, 0x06 }, { 0x437, 0x07 }, { 0x438, 0x00 }, { 0x439, 0x00 }, 1348 { 0x43a, 0x00 }, { 0x43b, 0x01 }, { 0x43c, 0x04 }, { 0x43d, 0x05 }, 1349 { 0x43e, 0x06 }, { 0x43f, 0x07 }, { 0x440, 0x5d }, { 0x441, 0x01 }, 1350 { 0x442, 0x00 }, { 0x444, 0x15 }, { 0x445, 0xf0 }, { 0x446, 0x0f }, 1351 { 0x447, 0x00 }, { 0x458, 0x41 }, { 0x459, 0xa8 }, { 0x45a, 0x72 }, 1352 { 0x45b, 0xb9 }, { 0x460, 0x88 }, { 0x461, 0x88 }, { 0x462, 0x06 }, 1353 { 0x463, 0x03 }, { 0x4c8, 0x04 }, { 0x4c9, 0x08 }, { 0x4cc, 0x02 }, 1354 { 0x4cd, 0x28 }, { 0x4ce, 0x01 }, { 0x500, 0x26 }, { 0x501, 0xa2 }, 1355 { 0x502, 0x2f }, { 0x503, 0x00 }, { 0x504, 0x28 }, { 0x505, 0xa3 }, 1356 { 0x506, 0x5e }, { 0x507, 0x00 }, { 0x508, 0x2b }, { 0x509, 0xa4 }, 1357 { 0x50a, 0x5e }, { 0x50b, 0x00 }, { 0x50c, 0x4f }, { 0x50d, 0xa4 }, 1358 { 0x50e, 0x00 }, { 0x50f, 0x00 }, { 0x512, 0x1c }, { 0x514, 0x0a }, 1359 { 0x515, 0x10 }, { 0x516, 0x0a }, { 0x517, 0x10 }, { 0x51a, 0x16 }, 1360 { 0x524, 0x0f }, { 0x525, 0x4f }, { 0x546, 0x20 }, { 0x547, 0x00 }, 1361 { 0x559, 0x02 }, { 0x55a, 0x02 }, { 0x55d, 0xff }, { 0x605, 0x30 }, 1362 { 0x608, 0x0e }, { 0x609, 0x2a }, { 0x652, 0x20 }, { 0x63c, 0x0a }, 1363 { 0x63d, 0x0e }, { 0x700, 0x21 }, { 0x701, 0x43 }, { 0x702, 0x65 }, 1364 { 0x703, 0x87 }, { 0x708, 0x21 }, { 0x709, 0x43 }, { 0x70a, 0x65 }, 1365 { 0x70b, 0x87 } 1366 }; 1367 1368 /* 1369 * Baseband initialization values. 1370 */ 1371 struct rtwn_bb_prog { 1372 int count; 1373 const uint16_t *regs; 1374 const uint32_t *vals; 1375 int agccount; 1376 const uint32_t *agcvals; 1377 }; 1378 1379 /* 1380 * RTL8192CU and RTL8192CE-VAU. 1381 */ 1382 static const uint16_t rtl8192ce_bb_regs[] = { 1383 0x024, 0x028, 0x800, 0x804, 0x808, 0x80c, 0x810, 0x814, 0x818, 1384 0x81c, 0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, 0x83c, 1385 0x840, 0x844, 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c, 0x860, 1386 0x864, 0x868, 0x86c, 0x870, 0x874, 0x878, 0x87c, 0x880, 0x884, 1387 0x888, 0x88c, 0x890, 0x894, 0x898, 0x89c, 0x900, 0x904, 0x908, 1388 0x90c, 0xa00, 0xa04, 0xa08, 0xa0c, 0xa10, 0xa14, 0xa18, 0xa1c, 1389 0xa20, 0xa24, 0xa28, 0xa2c, 0xa70, 0xa74, 0xc00, 0xc04, 0xc08, 1390 0xc0c, 0xc10, 0xc14, 0xc18, 0xc1c, 0xc20, 0xc24, 0xc28, 0xc2c, 1391 0xc30, 0xc34, 0xc38, 0xc3c, 0xc40, 0xc44, 0xc48, 0xc4c, 0xc50, 1392 0xc54, 0xc58, 0xc5c, 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 0xc74, 1393 0xc78, 0xc7c, 0xc80, 0xc84, 0xc88, 0xc8c, 0xc90, 0xc94, 0xc98, 1394 0xc9c, 0xca0, 0xca4, 0xca8, 0xcac, 0xcb0, 0xcb4, 0xcb8, 0xcbc, 1395 0xcc0, 0xcc4, 0xcc8, 0xccc, 0xcd0, 0xcd4, 0xcd8, 0xcdc, 0xce0, 1396 0xce4, 0xce8, 0xcec, 0xd00, 0xd04, 0xd08, 0xd0c, 0xd10, 0xd14, 1397 0xd18, 0xd2c, 0xd30, 0xd34, 0xd38, 0xd3c, 0xd40, 0xd44, 0xd48, 1398 0xd4c, 0xd50, 0xd54, 0xd58, 0xd5c, 0xd60, 0xd64, 0xd68, 0xd6c, 1399 0xd70, 0xd74, 0xd78, 0xe00, 0xe04, 0xe08, 0xe10, 0xe14, 0xe18, 1400 0xe1c, 0xe28, 0xe30, 0xe34, 0xe38, 0xe3c, 0xe40, 0xe44, 0xe48, 1401 0xe4c, 0xe50, 0xe54, 0xe58, 0xe5c, 0xe60, 0xe68, 0xe6c, 0xe70, 1402 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 0xed0, 0xed4, 1403 0xed8, 0xedc, 0xee0, 0xeec, 0xf14, 0xf4c, 0xf00 1404 }; 1405 1406 static const uint32_t rtl8192ce_bb_vals_2t[] = { 1407 0x0011800f, 0x00ffdb83, 0x80040002, 0x00000003, 0x0000fc00, 1408 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1409 0x01000100, 0x00390004, 0x01000100, 0x00390004, 0x27272727, 1410 0x27272727, 0x27272727, 0x27272727, 0x00010000, 0x00010000, 1411 0x27272727, 0x27272727, 0x00000000, 0x00000000, 0x569a569a, 1412 0x0c1b25a4, 0x66e60230, 0x061f0130, 0x27272727, 0x2b2b2b27, 1413 0x07000700, 0x22184000, 0x08080808, 0x00000000, 0xc0083070, 1414 0x000004d5, 0x00000000, 0xcc0000c0, 0x00000800, 0xfffffffe, 1415 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1416 0x81121313, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1417 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1418 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1419 0x48071d40, 0x03a05633, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1420 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1421 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1422 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1423 0x69543420, 0x43bc0094, 0x69543420, 0x433c0094, 0x00000000, 1424 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 1425 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 1426 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1427 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1428 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1429 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1430 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1431 0x00080740, 0x00020403, 0x0000907f, 0x20010201, 0xa0633333, 1432 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1433 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1434 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1435 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1436 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1437 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1438 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1439 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1440 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 0x63db25a4, 1441 0x63db25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 1442 0x63db25a4, 0x0c1b25a4, 0x63db25a4, 0x63db25a4, 0x63db25a4, 1443 0x63db25a4, 0x001b25a4, 0x001b25a4, 0x6fdb25a4, 0x00000003, 1444 0x00000000, 0x00000300 1445 }; 1446 1447 static const uint32_t rtl8192ce_bb_vals_1t[] = { 1448 0x0011800f, 0x00ffdb83, 0x80040000, 0x00000001, 0x0000fc00, 1449 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1450 0x01000100, 0x00390004, 0x00000000, 0x00000000, 0x00000000, 1451 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000, 1452 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x569a569a, 1453 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 0x32323200, 1454 0x07000700, 0x22004000, 0x00000808, 0x00000000, 0xc0083070, 1455 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 0xfffffffe, 1456 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1457 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1458 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1459 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1460 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1461 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1462 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1463 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1464 0x69543420, 0x43bc0094, 0x69543420, 0x433c0094, 0x00000000, 1465 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 1466 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 1467 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1468 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1469 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1470 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1471 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1472 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 0xa0633333, 1473 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1474 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1475 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1476 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1477 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1478 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1479 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1480 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1481 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 0x631b25a0, 1482 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 1483 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 0x631b25a0, 1484 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 0x00000003, 1485 0x00000000, 0x00000300, 1486 }; 1487 1488 static const uint32_t rtl8192ce_agc_vals[] = { 1489 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001, 1490 0x7b050001, 0x7a060001, 0x79070001, 0x78080001, 0x77090001, 1491 0x760a0001, 0x750b0001, 0x740c0001, 0x730d0001, 0x720e0001, 1492 0x710f0001, 0x70100001, 0x6f110001, 0x6e120001, 0x6d130001, 1493 0x6c140001, 0x6b150001, 0x6a160001, 0x69170001, 0x68180001, 1494 0x67190001, 0x661a0001, 0x651b0001, 0x641c0001, 0x631d0001, 1495 0x621e0001, 0x611f0001, 0x60200001, 0x49210001, 0x48220001, 1496 0x47230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001, 1497 0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001, 1498 0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001, 1499 0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001, 1500 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001, 1501 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001, 1502 0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001, 1503 0x7a460001, 0x79470001, 0x78480001, 0x77490001, 0x764a0001, 1504 0x754b0001, 0x744c0001, 0x734d0001, 0x724e0001, 0x714f0001, 1505 0x70500001, 0x6f510001, 0x6e520001, 0x6d530001, 0x6c540001, 1506 0x6b550001, 0x6a560001, 0x69570001, 0x68580001, 0x67590001, 1507 0x665a0001, 0x655b0001, 0x645c0001, 0x635d0001, 0x625e0001, 1508 0x615f0001, 0x60600001, 0x49610001, 0x48620001, 0x47630001, 1509 0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001, 1510 0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001, 1511 0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001, 1512 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001, 1513 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001, 1514 0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e, 1515 0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e, 1516 0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e, 1517 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e, 1518 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e, 1519 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e, 1520 0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e 1521 }; 1522 1523 static const struct rtwn_bb_prog rtl8192ce_bb_prog_2t = { 1524 nitems(rtl8192ce_bb_regs), 1525 rtl8192ce_bb_regs, 1526 rtl8192ce_bb_vals_2t, 1527 nitems(rtl8192ce_agc_vals), 1528 rtl8192ce_agc_vals 1529 }; 1530 1531 static const struct rtwn_bb_prog rtl8192ce_bb_prog_1t = { 1532 nitems(rtl8192ce_bb_regs), 1533 rtl8192ce_bb_regs, 1534 rtl8192ce_bb_vals_1t, 1535 nitems(rtl8192ce_agc_vals), 1536 rtl8192ce_agc_vals 1537 }; 1538 1539 /* 1540 * RTL8188CU. 1541 */ 1542 static const uint32_t rtl8192cu_bb_vals[] = { 1543 0x0011800d, 0x00ffdb83, 0x80040002, 0x00000003, 0x0000fc00, 1544 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1545 0x01000100, 0x00390004, 0x01000100, 0x00390004, 0x27272727, 1546 0x27272727, 0x27272727, 0x27272727, 0x00010000, 0x00010000, 1547 0x27272727, 0x27272727, 0x00000000, 0x00000000, 0x569a569a, 1548 0x0c1b25a4, 0x66e60230, 0x061f0130, 0x27272727, 0x2b2b2b27, 1549 0x07000700, 0x22184000, 0x08080808, 0x00000000, 0xc0083070, 1550 0x000004d5, 0x00000000, 0xcc0000c0, 0x00000800, 0xfffffffe, 1551 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1552 0x81121313, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1553 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1554 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1555 0x48071d40, 0x03a05633, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1556 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1557 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1558 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1559 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 1560 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x0186115b, 1561 0x0000001f, 0x00b99612, 0x40000100, 0x20f60000, 0x40000100, 1562 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1563 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1564 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1565 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1566 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1567 0x00080740, 0x00020403, 0x0000907f, 0x20010201, 0xa0633333, 1568 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1569 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1570 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1571 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1572 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1573 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1574 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1575 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1576 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 0x63db25a4, 1577 0x63db25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 1578 0x63db25a4, 0x0c1b25a4, 0x63db25a4, 0x63db25a4, 0x63db25a4, 1579 0x63db25a4, 0x001b25a4, 0x001b25a4, 0x6fdb25a4, 0x00000003, 1580 0x00000000, 0x00000300 1581 }; 1582 1583 static const struct rtwn_bb_prog rtl8192cu_bb_prog = { 1584 nitems(rtl8192ce_bb_regs), 1585 rtl8192ce_bb_regs, 1586 rtl8192cu_bb_vals, 1587 nitems(rtl8192ce_agc_vals), 1588 rtl8192ce_agc_vals 1589 }; 1590 1591 /* 1592 * RTL8188CE-VAU. 1593 */ 1594 static const uint32_t rtl8188ce_bb_vals[] = { 1595 0x0011800d, 0x00ffdb83, 0x80040000, 0x00000001, 0x0000fc00, 1596 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1597 0x01000100, 0x00390004, 0x00000000, 0x00000000, 0x00000000, 1598 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000, 1599 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x569a569a, 1600 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 0x32323200, 1601 0x07000700, 0x22004000, 0x00000808, 0x00000000, 0xc0083070, 1602 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 0xfffffffe, 1603 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1604 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1605 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1606 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1607 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1608 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1609 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1610 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1611 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 1612 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 1613 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 1614 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1615 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1616 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1617 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1618 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1619 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 0xa0633333, 1620 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1621 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1622 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1623 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1624 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1625 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1626 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1627 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1628 0x02140102, 0x28160d05, 0x00000008, 0x001b25a4, 0x631b25a0, 1629 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 1630 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 0x631b25a0, 1631 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 0x00000003, 1632 0x00000000, 0x00000300 1633 }; 1634 1635 static const uint32_t rtl8188ce_agc_vals[] = { 1636 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001, 1637 0x7b050001, 0x7a060001, 0x79070001, 0x78080001, 0x77090001, 1638 0x760a0001, 0x750b0001, 0x740c0001, 0x730d0001, 0x720e0001, 1639 0x710f0001, 0x70100001, 0x6f110001, 0x6e120001, 0x6d130001, 1640 0x6c140001, 0x6b150001, 0x6a160001, 0x69170001, 0x68180001, 1641 0x67190001, 0x661a0001, 0x651b0001, 0x641c0001, 0x631d0001, 1642 0x621e0001, 0x611f0001, 0x60200001, 0x49210001, 0x48220001, 1643 0x47230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001, 1644 0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001, 1645 0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001, 1646 0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001, 1647 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001, 1648 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001, 1649 0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001, 1650 0x7a460001, 0x79470001, 0x78480001, 0x77490001, 0x764a0001, 1651 0x754b0001, 0x744c0001, 0x734d0001, 0x724e0001, 0x714f0001, 1652 0x70500001, 0x6f510001, 0x6e520001, 0x6d530001, 0x6c540001, 1653 0x6b550001, 0x6a560001, 0x69570001, 0x68580001, 0x67590001, 1654 0x665a0001, 0x655b0001, 0x645c0001, 0x635d0001, 0x625e0001, 1655 0x615f0001, 0x60600001, 0x49610001, 0x48620001, 0x47630001, 1656 0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001, 1657 0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001, 1658 0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001, 1659 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001, 1660 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001, 1661 0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e, 1662 0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e, 1663 0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e, 1664 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e, 1665 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e, 1666 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e, 1667 0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e 1668 }; 1669 1670 static const struct rtwn_bb_prog rtl8188ce_bb_prog = { 1671 nitems(rtl8192ce_bb_regs), 1672 rtl8192ce_bb_regs, 1673 rtl8188ce_bb_vals, 1674 nitems(rtl8188ce_agc_vals), 1675 rtl8188ce_agc_vals 1676 }; 1677 1678 static const uint32_t rtl8188cu_bb_vals[] = { 1679 0x0011800d, 0x00ffdb83, 0x80040000, 0x00000001, 0x0000fc00, 1680 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000, 1681 0x01000100, 0x00390004, 0x00000000, 0x00000000, 0x00000000, 1682 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000, 1683 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x569a569a, 1684 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 0x32323200, 1685 0x07000700, 0x22004000, 0x00000808, 0x00000000, 0xc0083070, 1686 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 0xfffffffe, 1687 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000, 1688 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f, 1689 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000, 1690 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007, 1691 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, 1692 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000, 1693 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994, 1694 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 1695 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000, 1696 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db, 1697 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100, 1698 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f, 1699 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000, 1700 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000, 1701 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 1702 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 1703 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 0xa0633333, 1704 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000, 1705 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000, 1706 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064, 1707 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 1708 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a, 1709 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000, 1710 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 1711 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 1712 0x02140102, 0x28160d05, 0x00000008, 0x001b25a4, 0x631b25a0, 1713 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 1714 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 0x631b25a0, 1715 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 0x00000003, 1716 0x00000000, 0x00000300 1717 }; 1718 1719 static const struct rtwn_bb_prog rtl8188cu_bb_prog = { 1720 nitems(rtl8192ce_bb_regs), 1721 rtl8192ce_bb_regs, 1722 rtl8188cu_bb_vals, 1723 nitems(rtl8188ce_agc_vals), 1724 rtl8188ce_agc_vals 1725 }; 1726 1727 /* 1728 * RTL8188RU. 1729 */ 1730 static const uint16_t rtl8188ru_bb_regs[] = { 1731 0x024, 0x028, 0x040, 0x800, 0x804, 0x808, 0x80c, 0x810, 0x814, 1732 0x818, 0x81c, 0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, 1733 0x83c, 0x840, 0x844, 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c, 1734 0x860, 0x864, 0x868, 0x86c, 0x870, 0x874, 0x878, 0x87c, 0x880, 1735 0x884, 0x888, 0x88c, 0x890, 0x894, 0x898, 0x89c, 0x900, 0x904, 1736 0x908, 0x90c, 0xa00, 0xa04, 0xa08, 0xa0c, 0xa10, 0xa14, 0xa18, 1737 0xa1c, 0xa20, 0xa24, 0xa28, 0xa2c, 0xa70, 0xa74, 0xc00, 0xc04, 1738 0xc08, 0xc0c, 0xc10, 0xc14, 0xc18, 0xc1c, 0xc20, 0xc24, 0xc28, 1739 0xc2c, 0xc30, 0xc34, 0xc38, 0xc3c, 0xc40, 0xc44, 0xc48, 0xc4c, 1740 0xc50, 0xc54, 0xc58, 0xc5c, 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 1741 0xc74, 0xc78, 0xc7c, 0xc80, 0xc84, 0xc88, 0xc8c, 0xc90, 0xc94, 1742 0xc98, 0xc9c, 0xca0, 0xca4, 0xca8, 0xcac, 0xcb0, 0xcb4, 0xcb8, 1743 0xcbc, 0xcc0, 0xcc4, 0xcc8, 0xccc, 0xcd0, 0xcd4, 0xcd8, 0xcdc, 1744 0xce0, 0xce4, 0xce8, 0xcec, 0xd00, 0xd04, 0xd08, 0xd0c, 0xd10, 1745 0xd14, 0xd18, 0xd2c, 0xd30, 0xd34, 0xd38, 0xd3c, 0xd40, 0xd44, 1746 0xd48, 0xd4c, 0xd50, 0xd54, 0xd58, 0xd5c, 0xd60, 0xd64, 0xd68, 1747 0xd6c, 0xd70, 0xd74, 0xd78, 0xe00, 0xe04, 0xe08, 0xe10, 0xe14, 1748 0xe18, 0xe1c, 0xe28, 0xe30, 0xe34, 0xe38, 0xe3c, 0xe40, 0xe44, 1749 0xe48, 0xe4c, 0xe50, 0xe54, 0xe58, 0xe5c, 0xe60, 0xe68, 0xe6c, 1750 0xe70, 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 0xed0, 1751 0xed4, 0xed8, 0xedc, 0xee0, 0xeec, 0xee8, 0xf14, 0xf4c, 0xf00 1752 }; 1753 1754 static const uint32_t rtl8188ru_bb_vals[] = { 1755 0x0011800d, 0x00ffdb83, 0x000c0004, 0x80040000, 0x00000001, 1756 0x0000fc00, 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 1757 0x00000000, 0x01000100, 0x00390204, 0x00000000, 0x00000000, 1758 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00010000, 1759 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 1760 0x569a569a, 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 1761 0x32323200, 0x03000300, 0x22004000, 0x00000808, 0x00ffc3f1, 1762 0xc0083070, 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 1763 0xfffffffe, 0x40302010, 0x00706050, 0x00000000, 0x00000023, 1764 0x00000000, 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 1765 0x2e68120f, 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 1766 0x15160000, 0x070b0f12, 0x00000104, 0x00d30000, 0x101fbf00, 1767 0x00000007, 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 1768 0x08800000, 0x40000100, 0x08800000, 0x40000100, 0x00000000, 1769 0x00000000, 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 1770 0x49795994, 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 1771 0x007f037f, 0x6954342e, 0x43bc0094, 0x6954342f, 0x433c0094, 1772 0x00000000, 0x5116848b, 0x47c00bff, 0x00000036, 0x2c56000d, 1773 0x018610db, 0x0000001f, 0x00b91612, 0x24000090, 0x20f60000, 1774 0x24000090, 0x20200000, 0x00121820, 0x00000000, 0x00121820, 1775 0x00007f7f, 0x00000000, 0x00000080, 0x00000000, 0x00000000, 1776 0x00000000, 0x00000000, 0x00000000, 0x28000000, 0x00000000, 1777 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 1778 0x64b22427, 0x00766932, 0x00222222, 0x00000000, 0x37644302, 1779 0x2f97d40c, 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 1780 0xa0633333, 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 1781 0x80608000, 0x00000000, 0x00027293, 0x00000000, 0x00000000, 1782 0x00000000, 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 1783 0x30032064, 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 1784 0x1812362e, 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 1785 0x03902a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 1786 0x00000000, 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 1787 0x01007c00, 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 1788 0x10008c1f, 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 1789 0x631b25a0, 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 1790 0x081b25a0, 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 1791 0x631b25a0, 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 1792 0x31555448, 0x00000003, 0x00000000, 0x00000300 1793 }; 1794 1795 static const uint32_t rtl8188ru_agc_vals[] = { 1796 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001, 1797 0x7b050001, 0x7b060001, 0x7b070001, 0x7b080001, 0x7a090001, 1798 0x790a0001, 0x780b0001, 0x770c0001, 0x760d0001, 0x750e0001, 1799 0x740f0001, 0x73100001, 0x72110001, 0x71120001, 0x70130001, 1800 0x6f140001, 0x6e150001, 0x6d160001, 0x6c170001, 0x6b180001, 1801 0x6a190001, 0x691a0001, 0x681b0001, 0x671c0001, 0x661d0001, 1802 0x651e0001, 0x641f0001, 0x63200001, 0x62210001, 0x61220001, 1803 0x60230001, 0x46240001, 0x45250001, 0x44260001, 0x43270001, 1804 0x42280001, 0x41290001, 0x402a0001, 0x262b0001, 0x252c0001, 1805 0x242d0001, 0x232e0001, 0x222f0001, 0x21300001, 0x20310001, 1806 0x06320001, 0x05330001, 0x04340001, 0x03350001, 0x02360001, 1807 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001, 1808 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001, 1809 0x7b410001, 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001, 1810 0x7b460001, 0x7b470001, 0x7b480001, 0x7a490001, 0x794a0001, 1811 0x784b0001, 0x774c0001, 0x764d0001, 0x754e0001, 0x744f0001, 1812 0x73500001, 0x72510001, 0x71520001, 0x70530001, 0x6f540001, 1813 0x6e550001, 0x6d560001, 0x6c570001, 0x6b580001, 0x6a590001, 1814 0x695a0001, 0x685b0001, 0x675c0001, 0x665d0001, 0x655e0001, 1815 0x645f0001, 0x63600001, 0x62610001, 0x61620001, 0x60630001, 1816 0x46640001, 0x45650001, 0x44660001, 0x43670001, 0x42680001, 1817 0x41690001, 0x406a0001, 0x266b0001, 0x256c0001, 0x246d0001, 1818 0x236e0001, 0x226f0001, 0x21700001, 0x20710001, 0x06720001, 1819 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001, 1820 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001, 1821 0x007d0001, 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e, 1822 0x3802001e, 0x3803001e, 0x3804001e, 0x3805001e, 0x3806001e, 1823 0x3807001e, 0x3808001e, 0x3c09001e, 0x3e0a001e, 0x400b001e, 1824 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e, 0x5210001e, 1825 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e, 1826 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e, 1827 0x621b001e, 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e 1828 }; 1829 1830 static const struct rtwn_bb_prog rtl8188ru_bb_prog = { 1831 nitems(rtl8188ru_bb_regs), 1832 rtl8188ru_bb_regs, 1833 rtl8188ru_bb_vals, 1834 nitems(rtl8188ru_agc_vals), 1835 rtl8188ru_agc_vals 1836 }; 1837 1838 /* 1839 * RF initialization values. 1840 */ 1841 struct rtwn_rf_prog { 1842 int count; 1843 const uint8_t *regs; 1844 const uint32_t *vals; 1845 }; 1846 1847 /* 1848 * RTL8192CU and RTL8192CE-VAU. 1849 */ 1850 static const uint8_t rtl8192ce_rf1_regs[] = { 1851 0x00, 0x01, 0x02, 0x03, 0x04, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 1852 0x0f, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 0x20, 0x21, 0x22, 1853 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2a, 0x2b, 1854 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 1855 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 1856 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 1857 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 1858 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b, 1859 0x2c, 0x2a, 0x10, 0x11, 0x10, 0x11, 0x10, 0x11, 0x10, 0x11, 0x10, 1860 0x11, 0x10, 0x11, 0x10, 0x11, 0x12, 0x12, 0x12, 0x12, 0x13, 0x13, 1861 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x14, 0x14, 1862 0x14, 0x14, 0x15, 0x15, 0x15, 0x15, 0x16, 0x16, 0x16, 0x16, 0x00, 1863 0x18, 0xfe, 0xfe, 0x1f, 0xfe, 0xfe, 0x1e, 0x1f, 0x00 1864 }; 1865 1866 static const uint32_t rtl8192ce_rf1_vals[] = { 1867 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 1868 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255, 1869 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 1870 0x00000, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x577c0, 1871 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 1872 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 1873 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 1874 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 1875 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 1876 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 1877 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 1878 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 1879 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 1880 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 1881 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000, 1882 0x71000, 0xb0000, 0xfc000, 0x287af, 0x244b7, 0x204ab, 0x1c49f, 1883 0x18493, 0x14297, 0x10295, 0x0c298, 0x0819c, 0x040a8, 0x0001c, 1884 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, 1885 0xcf424, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 1886 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 1887 0x30159 1888 }; 1889 1890 static const uint8_t rtl8192ce_rf2_regs[] = { 1891 0x00, 0x01, 0x02, 0x03, 0x04, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 1892 0x0f, 0x12, 0x12, 0x12, 0x12, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 1893 0x13, 0x13, 0x13, 0x13, 0x13, 0x14, 0x14, 0x14, 0x14, 0x15, 0x15, 1894 0x15, 0x15, 0x16, 0x16, 0x16, 0x16 1895 }; 1896 1897 static const uint32_t rtl8192ce_rf2_vals[] = { 1898 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 1899 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x32000, 0x71000, 1900 0xb0000, 0xfc000, 0x287af, 0x244b7, 0x204ab, 0x1c49f, 0x18493, 1901 0x14297, 0x10295, 0x0c298, 0x0819c, 0x040a8, 0x0001c, 0x1944c, 1902 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, 0xcf424, 1903 0xe0330, 0xa0330, 0x60330, 0x20330 1904 }; 1905 1906 static const struct rtwn_rf_prog rtl8192ce_rf_prog[] = { 1907 { 1908 nitems(rtl8192ce_rf1_regs), 1909 rtl8192ce_rf1_regs, 1910 rtl8192ce_rf1_vals 1911 }, 1912 { 1913 nitems(rtl8192ce_rf2_regs), 1914 rtl8192ce_rf2_regs, 1915 rtl8192ce_rf2_vals 1916 } 1917 }; 1918 1919 /* 1920 * RTL8188CE-VAU. 1921 */ 1922 static const uint32_t rtl8188ce_rf_vals[] = { 1923 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 1924 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255, 1925 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 1926 0x00000, 0x01558, 0x00060, 0x00483, 0x4f200, 0xec7d9, 0x577c0, 1927 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 1928 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 1929 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 1930 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 1931 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 1932 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 1933 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 1934 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 1935 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 1936 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 1937 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000, 1938 0x71000, 0xb0000, 0xfc000, 0x287b3, 0x244b7, 0x204ab, 0x1c49f, 1939 0x18493, 0x1429b, 0x10299, 0x0c29c, 0x081a0, 0x040ac, 0x00020, 1940 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, 1941 0xcf424, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 1942 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 1943 0x30159 1944 }; 1945 1946 static const struct rtwn_rf_prog rtl8188ce_rf_prog[] = { 1947 { 1948 nitems(rtl8192ce_rf1_regs), 1949 rtl8192ce_rf1_regs, 1950 rtl8188ce_rf_vals 1951 } 1952 }; 1953 1954 1955 /* 1956 * RTL8188CU. 1957 */ 1958 static const uint32_t rtl8188cu_rf_vals[] = { 1959 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 1960 0x54867, 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255, 1961 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 1962 0x00000, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x577c0, 1963 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 1964 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 1965 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 1966 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 1967 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 1968 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 1969 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 1970 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 1971 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 1972 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 1973 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0x32000, 1974 0x71000, 0xb0000, 0xfc000, 0x287b3, 0x244b7, 0x204ab, 0x1c49f, 1975 0x18493, 0x1429b, 0x10299, 0x0c29c, 0x081a0, 0x040ac, 0x00020, 1976 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f405, 0x4f405, 0x8f405, 1977 0xcf405, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 1978 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 1979 0x30159 1980 }; 1981 1982 static const struct rtwn_rf_prog rtl8188cu_rf_prog[] = { 1983 { 1984 nitems(rtl8192ce_rf1_regs), 1985 rtl8192ce_rf1_regs, 1986 rtl8188cu_rf_vals 1987 } 1988 }; 1989 1990 /* 1991 * RTL8188RU. 1992 */ 1993 static const uint32_t rtl8188ru_rf_vals[] = { 1994 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb0, 1995 0x54867, 0x8992e, 0x0e529, 0x39ce7, 0x00451, 0x00000, 0x00255, 1996 0x60a00, 0xfc378, 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 1997 0x0083c, 0x01558, 0x00060, 0x00483, 0x4f000, 0xec7d9, 0x977c0, 1998 0x04783, 0x00001, 0x21334, 0x00000, 0x00054, 0x00001, 0x00808, 1999 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333, 0x0000d, 0x00003, 2000 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333, 0x0000d, 2001 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333, 2002 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 2003 0x4b333, 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 2004 0x0060a, 0x5b333, 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 2005 0x0000c, 0x0060a, 0x6b333, 0x0000d, 0x0000d, 0x0060a, 0x73333, 2006 0x0000d, 0x0000e, 0x0050b, 0x66666, 0x0001a, 0xe0000, 0x4000f, 2007 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9, 0x3000f, 0xff500, 2008 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100, 0xd8000, 2009 0x90000, 0x51000, 0x12000, 0x28fb4, 0x24fa8, 0x207a4, 0x1c798, 2010 0x183a4, 0x14398, 0x101a4, 0x0c198, 0x080a4, 0x04098, 0x00014, 2011 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f405, 0x4f405, 0x8f405, 2012 0xcf405, 0xe0330, 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 2013 0x00000, 0x00000, 0x80003, 0x00000, 0x00000, 0x44457, 0x80000, 2014 0x30159 2015 }; 2016 2017 static const struct rtwn_rf_prog rtl8188ru_rf_prog[] = { 2018 { 2019 nitems(rtl8192ce_rf1_regs), 2020 rtl8192ce_rf1_regs, 2021 rtl8188ru_rf_vals 2022 } 2023 }; 2024 2025 struct rtwn_txpwr { 2026 uint8_t pwr[3][28]; 2027 }; 2028 2029 /* 2030 * Per RF chain/group/rate Tx gain values. 2031 */ 2032 static const struct rtwn_txpwr rtl8192cu_txagc[] = { 2033 { { /* Chain 0. */ 2034 { /* Group 0. */ 2035 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2036 0x0c, 0x0c, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02, /* OFDM6~54. */ 2037 0x0e, 0x0d, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02, /* MCS0~7. */ 2038 0x0e, 0x0d, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02 /* MCS8~15. */ 2039 }, 2040 { /* Group 1. */ 2041 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2042 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2043 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2044 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2045 }, 2046 { /* Group 2. */ 2047 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2048 0x04, 0x04, 0x04, 0x04, 0x04, 0x02, 0x02, 0x00, /* OFDM6~54. */ 2049 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2050 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2051 } 2052 } }, 2053 { { /* Chain 1. */ 2054 { /* Group 0. */ 2055 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2056 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2057 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2058 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2059 }, 2060 { /* Group 1. */ 2061 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2062 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2063 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2064 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2065 }, 2066 { /* Group 2. */ 2067 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2068 0x04, 0x04, 0x04, 0x04, 0x04, 0x02, 0x02, 0x00, /* OFDM6~54. */ 2069 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2070 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2071 } 2072 } } 2073 }; 2074 2075 static const struct rtwn_txpwr rtl8188ru_txagc[] = { 2076 { { /* Chain 0. */ 2077 { /* Group 0. */ 2078 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2079 0x08, 0x08, 0x08, 0x06, 0x06, 0x04, 0x04, 0x00, /* OFDM6~54. */ 2080 0x08, 0x06, 0x06, 0x04, 0x04, 0x02, 0x02, 0x00, /* MCS0~7. */ 2081 0x08, 0x06, 0x06, 0x04, 0x04, 0x02, 0x02, 0x00 /* MCS8~15. */ 2082 }, 2083 { /* Group 1. */ 2084 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2085 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2086 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2087 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2088 }, 2089 { /* Group 2. */ 2090 0x00, 0x00, 0x00, 0x00, /* CCK1~11. */ 2091 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* OFDM6~54. */ 2092 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* MCS0~7. */ 2093 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /* MCS8~15. */ 2094 } 2095 } } 2096 }; 2097 2098 #define RTWN_LOCK_INIT(_sc) \ 2099 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 2100 MTX_NETWORK_LOCK, MTX_DEF) 2101 #define RTWN_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 2102 #define RTWN_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 2103 #define RTWN_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 2104 #define RTWN_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 2105 2106