xref: /freebsd/sys/dev/rtwn/if_rtwn.c (revision 55620f43deef5c0eb5b4b0f675de18b30c8d1c2d)
1 /*	$OpenBSD: if_rtwn.c,v 1.6 2015/08/28 00:03:53 deraadt Exp $	*/
2 
3 /*-
4  * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
5  * Copyright (c) 2015 Stefan Sperling <stsp@openbsd.org>
6  *
7  * Permission to use, copy, modify, and distribute this software for any
8  * purpose with or without fee is hereby granted, provided that the above
9  * copyright notice and this permission notice appear in all copies.
10  *
11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18  */
19 
20 #include <sys/cdefs.h>
21 __FBSDID("$FreeBSD$");
22 
23 /*
24  * Driver for Realtek RTL8188CE
25  */
26 
27 #include <sys/param.h>
28 #include <sys/sysctl.h>
29 #include <sys/sockio.h>
30 #include <sys/mbuf.h>
31 #include <sys/kernel.h>
32 #include <sys/socket.h>
33 #include <sys/systm.h>
34 #include <sys/malloc.h>
35 #include <sys/lock.h>
36 #include <sys/mutex.h>
37 #include <sys/module.h>
38 #include <sys/bus.h>
39 #include <sys/endian.h>
40 #include <sys/firmware.h>
41 
42 #include <machine/bus.h>
43 #include <machine/resource.h>
44 #include <sys/rman.h>
45 
46 #include <dev/pci/pcireg.h>
47 #include <dev/pci/pcivar.h>
48 
49 #include <net/bpf.h>
50 #include <net/if.h>
51 #include <net/if_var.h>
52 #include <net/if_arp.h>
53 #include <net/ethernet.h>
54 #include <net/if_dl.h>
55 #include <net/if_media.h>
56 #include <net/if_types.h>
57 
58 #include <net80211/ieee80211_var.h>
59 #include <net80211/ieee80211_radiotap.h>
60 #include <net80211/ieee80211_regdomain.h>
61 #include <net80211/ieee80211_ratectl.h>
62 
63 #include <netinet/in.h>
64 #include <netinet/in_systm.h>
65 #include <netinet/in_var.h>
66 #include <netinet/ip.h>
67 #include <netinet/if_ether.h>
68 
69 #include <dev/rtwn/if_rtwnreg.h>
70 
71 #define	RTWN_DEBUG
72 #ifdef RTWN_DEBUG
73 #define	DPRINTF(x)	do { if (sc->sc_debug > 0) printf x; } while (0)
74 #define	DPRINTFN(n, x)	do { if (sc->sc_debug >= (n)) printf x; } while (0)
75 #else
76 #define	DPRINTF(x)
77 #define	DPRINTFN(n, x)
78 #endif
79 
80 /*
81  * PCI configuration space registers.
82  */
83 #define	RTWN_PCI_IOBA		0x10	/* i/o mapped base */
84 #define	RTWN_PCI_MMBA		0x18	/* memory mapped base */
85 
86 #define RTWN_INT_ENABLE	(R92C_IMR_ROK | R92C_IMR_VODOK | R92C_IMR_VIDOK | \
87 			R92C_IMR_BEDOK | R92C_IMR_BKDOK | R92C_IMR_MGNTDOK | \
88 			R92C_IMR_HIGHDOK | R92C_IMR_BDOK | R92C_IMR_RDU | \
89 			R92C_IMR_RXFOVW)
90 
91 struct rtwn_ident {
92 	uint16_t	vendor;
93 	uint16_t	device;
94 	const char	*name;
95 };
96 
97 
98 static const struct rtwn_ident rtwn_ident_table[] = {
99 	{ 0x10ec, 0x8176, "Realtek RTL8188CE" },
100 	{ 0, 0, NULL }
101 };
102 
103 
104 static void	rtwn_dma_map_addr(void *, bus_dma_segment_t *, int, int);
105 static void	rtwn_setup_rx_desc(struct rtwn_softc *, struct r92c_rx_desc *,
106 		    bus_addr_t, size_t, int);
107 static int	rtwn_alloc_rx_list(struct rtwn_softc *);
108 static void	rtwn_reset_rx_list(struct rtwn_softc *);
109 static void	rtwn_free_rx_list(struct rtwn_softc *);
110 static int	rtwn_alloc_tx_list(struct rtwn_softc *, int);
111 static void	rtwn_reset_tx_list(struct rtwn_softc *, int);
112 static void	rtwn_free_tx_list(struct rtwn_softc *, int);
113 static struct ieee80211vap *rtwn_vap_create(struct ieee80211com *,
114 		    const char [IFNAMSIZ], int, enum ieee80211_opmode, int,
115 		    const uint8_t [IEEE80211_ADDR_LEN],
116 		    const uint8_t [IEEE80211_ADDR_LEN]);
117 static void	rtwn_vap_delete(struct ieee80211vap *);
118 static void	rtwn_write_1(struct rtwn_softc *, uint16_t, uint8_t);
119 static void	rtwn_write_2(struct rtwn_softc *, uint16_t, uint16_t);
120 static void	rtwn_write_4(struct rtwn_softc *, uint16_t, uint32_t);
121 static uint8_t	rtwn_read_1(struct rtwn_softc *, uint16_t);
122 static uint16_t	rtwn_read_2(struct rtwn_softc *, uint16_t);
123 static uint32_t	rtwn_read_4(struct rtwn_softc *, uint16_t);
124 static int	rtwn_fw_cmd(struct rtwn_softc *, uint8_t, const void *, int);
125 static void	rtwn_rf_write(struct rtwn_softc *, int, uint8_t, uint32_t);
126 static uint32_t	rtwn_rf_read(struct rtwn_softc *, int, uint8_t);
127 static int	rtwn_llt_write(struct rtwn_softc *, uint32_t, uint32_t);
128 static uint8_t	rtwn_efuse_read_1(struct rtwn_softc *, uint16_t);
129 static void	rtwn_efuse_read(struct rtwn_softc *);
130 static int	rtwn_read_chipid(struct rtwn_softc *);
131 static void	rtwn_read_rom(struct rtwn_softc *);
132 static int	rtwn_ra_init(struct rtwn_softc *);
133 static void	rtwn_tsf_sync_enable(struct rtwn_softc *);
134 static void	rtwn_set_led(struct rtwn_softc *, int, int);
135 static void	rtwn_calib_to(void *);
136 static int	rtwn_newstate(struct ieee80211vap *, enum ieee80211_state, int);
137 static int	rtwn_updateedca(struct ieee80211com *);
138 static void	rtwn_update_avgrssi(struct rtwn_softc *, int, int8_t);
139 static int8_t	rtwn_get_rssi(struct rtwn_softc *, int, void *);
140 static void	rtwn_rx_frame(struct rtwn_softc *, struct r92c_rx_desc *,
141 		    struct rtwn_rx_data *, int);
142 static int	rtwn_tx(struct rtwn_softc *, struct mbuf *,
143 		    struct ieee80211_node *);
144 static void	rtwn_tx_done(struct rtwn_softc *, int);
145 static int	rtwn_raw_xmit(struct ieee80211_node *, struct mbuf *,
146 		    const struct ieee80211_bpf_params *);
147 static int	rtwn_transmit(struct ieee80211com *, struct mbuf *);
148 static void	rtwn_parent(struct ieee80211com *);
149 static void	rtwn_start(struct rtwn_softc *sc);
150 static void	rtwn_watchdog(void *);
151 static int	rtwn_power_on(struct rtwn_softc *);
152 static int	rtwn_llt_init(struct rtwn_softc *);
153 static void	rtwn_fw_reset(struct rtwn_softc *);
154 static void	rtwn_fw_loadpage(struct rtwn_softc *, int, const uint8_t *,
155 		    int);
156 static int	rtwn_load_firmware(struct rtwn_softc *);
157 static int	rtwn_dma_init(struct rtwn_softc *);
158 static void	rtwn_mac_init(struct rtwn_softc *);
159 static void	rtwn_bb_init(struct rtwn_softc *);
160 static void	rtwn_rf_init(struct rtwn_softc *);
161 static void	rtwn_cam_init(struct rtwn_softc *);
162 static void	rtwn_pa_bias_init(struct rtwn_softc *);
163 static void	rtwn_rxfilter_init(struct rtwn_softc *);
164 static void	rtwn_edca_init(struct rtwn_softc *);
165 static void	rtwn_write_txpower(struct rtwn_softc *, int, uint16_t[]);
166 static void	rtwn_get_txpower(struct rtwn_softc *, int,
167 		    struct ieee80211_channel *, struct ieee80211_channel *,
168 		    uint16_t[]);
169 static void	rtwn_set_txpower(struct rtwn_softc *,
170 		    struct ieee80211_channel *, struct ieee80211_channel *);
171 static void	rtwn_set_rx_bssid_all(struct rtwn_softc *, int);
172 static void	rtwn_set_gain(struct rtwn_softc *, uint8_t);
173 static void	rtwn_scan_start(struct ieee80211com *);
174 static void	rtwn_scan_end(struct ieee80211com *);
175 static void	rtwn_getradiocaps(struct ieee80211com *, int, int *,
176 		    struct ieee80211_channel[]);
177 static void	rtwn_set_channel(struct ieee80211com *);
178 static void	rtwn_update_mcast(struct ieee80211com *);
179 static void	rtwn_set_chan(struct rtwn_softc *,
180 		    struct ieee80211_channel *, struct ieee80211_channel *);
181 static int	rtwn_iq_calib_chain(struct rtwn_softc *, int, uint16_t[2],
182 		    uint16_t[2]);
183 static void	rtwn_iq_calib_run(struct rtwn_softc *, int, uint16_t[2][2],
184 		    uint16_t[2][2]);
185 static int	rtwn_iq_calib_compare_results(uint16_t[2][2], uint16_t[2][2],
186 		    uint16_t[2][2], uint16_t[2][2], int);
187 static void	rtwn_iq_calib_write_results(struct rtwn_softc *, uint16_t[2],
188 		    uint16_t[2], int);
189 static void	rtwn_iq_calib(struct rtwn_softc *);
190 static void	rtwn_lc_calib(struct rtwn_softc *);
191 static void	rtwn_temp_calib(struct rtwn_softc *);
192 static int	rtwn_init(struct rtwn_softc *);
193 static void	rtwn_stop_locked(struct rtwn_softc *);
194 static void	rtwn_stop(struct rtwn_softc *);
195 static void	rtwn_intr(void *);
196 
197 /* Aliases. */
198 #define	rtwn_bb_write	rtwn_write_4
199 #define rtwn_bb_read	rtwn_read_4
200 
201 static int	rtwn_probe(device_t);
202 static int	rtwn_attach(device_t);
203 static int	rtwn_detach(device_t);
204 static int	rtwn_shutdown(device_t);
205 static int	rtwn_suspend(device_t);
206 static int	rtwn_resume(device_t);
207 
208 static device_method_t rtwn_methods[] = {
209 	/* Device interface */
210 	DEVMETHOD(device_probe,		rtwn_probe),
211 	DEVMETHOD(device_attach,	rtwn_attach),
212 	DEVMETHOD(device_detach,	rtwn_detach),
213 	DEVMETHOD(device_shutdown,	rtwn_shutdown),
214 	DEVMETHOD(device_suspend,	rtwn_suspend),
215 	DEVMETHOD(device_resume,	rtwn_resume),
216 
217 	DEVMETHOD_END
218 };
219 
220 static driver_t rtwn_driver = {
221 	"rtwn",
222 	rtwn_methods,
223 	sizeof (struct rtwn_softc)
224 };
225 static devclass_t rtwn_devclass;
226 
227 DRIVER_MODULE(rtwn, pci, rtwn_driver, rtwn_devclass, NULL, NULL);
228 
229 MODULE_VERSION(rtwn, 1);
230 
231 MODULE_DEPEND(rtwn, pci,  1, 1, 1);
232 MODULE_DEPEND(rtwn, wlan, 1, 1, 1);
233 MODULE_DEPEND(rtwn, firmware, 1, 1, 1);
234 
235 static const uint8_t rtwn_chan_2ghz[] =
236 	{ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 };
237 
238 static int
239 rtwn_probe(device_t dev)
240 {
241 	const struct rtwn_ident *ident;
242 
243 	for (ident = rtwn_ident_table; ident->name != NULL; ident++) {
244 		if (pci_get_vendor(dev) == ident->vendor &&
245 		    pci_get_device(dev) == ident->device) {
246 			device_set_desc(dev, ident->name);
247 			return (BUS_PROBE_DEFAULT);
248 		}
249 	}
250 	return (ENXIO);
251 }
252 
253 static int
254 rtwn_attach(device_t dev)
255 {
256 	struct rtwn_softc *sc = device_get_softc(dev);
257 	struct ieee80211com *ic = &sc->sc_ic;
258 	uint32_t lcsr;
259 	int i, count, error, rid;
260 
261 	sc->sc_dev = dev;
262 	sc->sc_debug = 0;
263 
264 	/*
265 	 * Get the offset of the PCI Express Capability Structure in PCI
266 	 * Configuration Space.
267 	 */
268 	error = pci_find_cap(dev, PCIY_EXPRESS, &sc->sc_cap_off);
269 	if (error != 0) {
270 		device_printf(dev, "PCIe capability structure not found!\n");
271 		return (error);
272 	}
273 
274 	/* Enable bus-mastering. */
275 	pci_enable_busmaster(dev);
276 
277 	rid = PCIR_BAR(2);
278 	sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
279 	    RF_ACTIVE);
280 	if (sc->mem == NULL) {
281 		device_printf(dev, "can't map mem space\n");
282 		return (ENOMEM);
283 	}
284 	sc->sc_st = rman_get_bustag(sc->mem);
285 	sc->sc_sh = rman_get_bushandle(sc->mem);
286 
287 	/* Install interrupt handler. */
288 	count = 1;
289 	rid = 0;
290 	if (pci_alloc_msi(dev, &count) == 0)
291 		rid = 1;
292 	sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE |
293 	    (rid != 0 ? 0 : RF_SHAREABLE));
294 	if (sc->irq == NULL) {
295 		device_printf(dev, "can't map interrupt\n");
296 		return (ENXIO);
297 	}
298 
299 	RTWN_LOCK_INIT(sc);
300 	callout_init_mtx(&sc->calib_to, &sc->sc_mtx, 0);
301 	callout_init_mtx(&sc->watchdog_to, &sc->sc_mtx, 0);
302 	mbufq_init(&sc->sc_snd, ifqmaxlen);
303 
304 	error = rtwn_read_chipid(sc);
305 	if (error != 0) {
306 		device_printf(dev, "unsupported test chip\n");
307 		goto fail;
308 	}
309 
310 	/* Disable PCIe Active State Power Management (ASPM). */
311 	lcsr = pci_read_config(sc->sc_dev, sc->sc_cap_off + PCIER_LINK_CTL, 4);
312 	lcsr &= ~PCIEM_LINK_CTL_ASPMC;
313 	pci_write_config(sc->sc_dev, sc->sc_cap_off + PCIER_LINK_CTL, lcsr, 4);
314 
315 	/* Allocate Tx/Rx buffers. */
316 	error = rtwn_alloc_rx_list(sc);
317 	if (error != 0) {
318 		device_printf(dev, "could not allocate Rx buffers\n");
319 		goto fail;
320 	}
321 	for (i = 0; i < RTWN_NTXQUEUES; i++) {
322 		error = rtwn_alloc_tx_list(sc, i);
323 		if (error != 0) {
324 			device_printf(dev, "could not allocate Tx buffers\n");
325 			goto fail;
326 		}
327 	}
328 
329 	/* Determine number of Tx/Rx chains. */
330 	if (sc->chip & RTWN_CHIP_92C) {
331 		sc->ntxchains = (sc->chip & RTWN_CHIP_92C_1T2R) ? 1 : 2;
332 		sc->nrxchains = 2;
333 	} else {
334 		sc->ntxchains = 1;
335 		sc->nrxchains = 1;
336 	}
337 	rtwn_read_rom(sc);
338 
339 	device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n",
340 	    (sc->chip & RTWN_CHIP_92C) ? "8192CE" : "8188CE",
341 	    sc->ntxchains, sc->nrxchains);
342 
343 	ic->ic_softc = sc;
344 	ic->ic_name = device_get_nameunit(dev);
345 	ic->ic_opmode = IEEE80211_M_STA;
346 	ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
347 
348 	/* set device capabilities */
349 	ic->ic_caps =
350 		  IEEE80211_C_STA		/* station mode */
351 		| IEEE80211_C_MONITOR		/* monitor mode */
352 		| IEEE80211_C_SHPREAMBLE	/* short preamble supported */
353 		| IEEE80211_C_SHSLOT		/* short slot time supported */
354 		| IEEE80211_C_WPA		/* capable of WPA1+WPA2 */
355 		| IEEE80211_C_BGSCAN		/* capable of bg scanning */
356 		| IEEE80211_C_WME		/* 802.11e */
357 		;
358 
359 	/* XXX TODO: setup regdomain if R92C_CHANNEL_PLAN_BY_HW bit is set. */
360 
361 	rtwn_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans,
362 	    ic->ic_channels);
363 
364 	ieee80211_ifattach(ic);
365 
366 	ic->ic_wme.wme_update = rtwn_updateedca;
367 	ic->ic_update_mcast = rtwn_update_mcast;
368 	ic->ic_scan_start = rtwn_scan_start;
369 	ic->ic_scan_end = rtwn_scan_end;
370 	ic->ic_getradiocaps = rtwn_getradiocaps;
371 	ic->ic_set_channel = rtwn_set_channel;
372 	ic->ic_raw_xmit = rtwn_raw_xmit;
373 	ic->ic_transmit = rtwn_transmit;
374 	ic->ic_parent = rtwn_parent;
375 	ic->ic_vap_create = rtwn_vap_create;
376 	ic->ic_vap_delete = rtwn_vap_delete;
377 
378 	ieee80211_radiotap_attach(ic,
379 	    &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap),
380 		RTWN_TX_RADIOTAP_PRESENT,
381 	    &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap),
382 		RTWN_RX_RADIOTAP_PRESENT);
383 
384 	/*
385 	 * Hook our interrupt after all initialization is complete.
386 	 */
387 	error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE,
388 	    NULL, rtwn_intr, sc, &sc->sc_ih);
389 	if (error != 0) {
390 		device_printf(dev, "can't establish interrupt, error %d\n",
391 		    error);
392 		goto fail;
393 	}
394 
395 	if (bootverbose)
396 		ieee80211_announce(ic);
397 
398 	return (0);
399 
400 fail:
401 	rtwn_detach(dev);
402 	return (error);
403 }
404 
405 
406 static int
407 rtwn_detach(device_t dev)
408 {
409 	struct rtwn_softc *sc = device_get_softc(dev);
410 	int i;
411 
412 	if (sc->sc_ic.ic_softc != NULL) {
413 		rtwn_stop(sc);
414 
415 		callout_drain(&sc->calib_to);
416 		callout_drain(&sc->watchdog_to);
417 		ieee80211_ifdetach(&sc->sc_ic);
418 		mbufq_drain(&sc->sc_snd);
419 	}
420 
421 	/* Uninstall interrupt handler. */
422 	if (sc->irq != NULL) {
423 		bus_teardown_intr(dev, sc->irq, sc->sc_ih);
424 		bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq),
425 		    sc->irq);
426 		pci_release_msi(dev);
427 	}
428 
429 	/* Free Tx/Rx buffers. */
430 	for (i = 0; i < RTWN_NTXQUEUES; i++)
431 		rtwn_free_tx_list(sc, i);
432 	rtwn_free_rx_list(sc);
433 
434 	if (sc->mem != NULL)
435 		bus_release_resource(dev, SYS_RES_MEMORY,
436 		    rman_get_rid(sc->mem), sc->mem);
437 
438 	RTWN_LOCK_DESTROY(sc);
439 	return (0);
440 }
441 
442 static int
443 rtwn_shutdown(device_t dev)
444 {
445 
446 	return (0);
447 }
448 
449 static int
450 rtwn_suspend(device_t dev)
451 {
452 	return (0);
453 }
454 
455 static int
456 rtwn_resume(device_t dev)
457 {
458 
459 	return (0);
460 }
461 
462 static void
463 rtwn_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
464 {
465 
466 	if (error != 0)
467 		return;
468 	KASSERT(nsegs == 1, ("too many DMA segments, %d should be 1", nsegs));
469 	*(bus_addr_t *)arg = segs[0].ds_addr;
470 }
471 
472 static void
473 rtwn_setup_rx_desc(struct rtwn_softc *sc, struct r92c_rx_desc *desc,
474     bus_addr_t addr, size_t len, int idx)
475 {
476 
477 	memset(desc, 0, sizeof(*desc));
478 	desc->rxdw0 = htole32(SM(R92C_RXDW0_PKTLEN, len) |
479 		((idx == RTWN_RX_LIST_COUNT - 1) ? R92C_RXDW0_EOR : 0));
480 	desc->rxbufaddr = htole32(addr);
481 	bus_space_barrier(sc->sc_st, sc->sc_sh, 0, sc->sc_mapsize,
482 	    BUS_SPACE_BARRIER_WRITE);
483 	desc->rxdw0 |= htole32(R92C_RXDW0_OWN);
484 }
485 
486 static int
487 rtwn_alloc_rx_list(struct rtwn_softc *sc)
488 {
489 	struct rtwn_rx_ring *rx_ring = &sc->rx_ring;
490 	struct rtwn_rx_data *rx_data;
491 	bus_size_t size;
492 	int i, error;
493 
494 	/* Allocate Rx descriptors. */
495 	size = sizeof(struct r92c_rx_desc) * RTWN_RX_LIST_COUNT;
496 	error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
497 	    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
498 	    size, 1, size, 0, NULL, NULL, &rx_ring->desc_dmat);
499 	if (error != 0) {
500 		device_printf(sc->sc_dev, "could not create rx desc DMA tag\n");
501 		goto fail;
502 	}
503 
504 	error = bus_dmamem_alloc(rx_ring->desc_dmat, (void **)&rx_ring->desc,
505 	    BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
506 	    &rx_ring->desc_map);
507 	if (error != 0) {
508 		device_printf(sc->sc_dev, "could not allocate rx desc\n");
509 		goto fail;
510 	}
511 	error = bus_dmamap_load(rx_ring->desc_dmat, rx_ring->desc_map,
512 	    rx_ring->desc, size, rtwn_dma_map_addr, &rx_ring->paddr, 0);
513 	if (error != 0) {
514 		device_printf(sc->sc_dev, "could not load rx desc DMA map\n");
515 		goto fail;
516 	}
517 	bus_dmamap_sync(rx_ring->desc_dmat, rx_ring->desc_map,
518 	    BUS_DMASYNC_PREWRITE);
519 
520 	/* Create RX buffer DMA tag. */
521 	error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
522 	    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES,
523 	    1, MCLBYTES, 0, NULL, NULL, &rx_ring->data_dmat);
524 	if (error != 0) {
525 		device_printf(sc->sc_dev, "could not create rx buf DMA tag\n");
526 		goto fail;
527 	}
528 
529 	/* Allocate Rx buffers. */
530 	for (i = 0; i < RTWN_RX_LIST_COUNT; i++) {
531 		rx_data = &rx_ring->rx_data[i];
532 		error = bus_dmamap_create(rx_ring->data_dmat, 0, &rx_data->map);
533 		if (error != 0) {
534 			device_printf(sc->sc_dev,
535 			    "could not create rx buf DMA map\n");
536 			goto fail;
537 		}
538 
539 		rx_data->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
540 		if (rx_data->m == NULL) {
541 			device_printf(sc->sc_dev,
542 			    "could not allocate rx mbuf\n");
543 			error = ENOMEM;
544 			goto fail;
545 		}
546 
547 		error = bus_dmamap_load(rx_ring->data_dmat, rx_data->map,
548 		    mtod(rx_data->m, void *), MCLBYTES, rtwn_dma_map_addr,
549 		    &rx_data->paddr, BUS_DMA_NOWAIT);
550 		if (error != 0) {
551 			device_printf(sc->sc_dev,
552 			    "could not load rx buf DMA map");
553 			goto fail;
554 		}
555 
556 		rtwn_setup_rx_desc(sc, &rx_ring->desc[i], rx_data->paddr,
557 		    MCLBYTES, i);
558 	}
559 	return (0);
560 
561 fail:
562 	rtwn_free_rx_list(sc);
563 	return (error);
564 }
565 
566 static void
567 rtwn_reset_rx_list(struct rtwn_softc *sc)
568 {
569 	struct rtwn_rx_ring *rx_ring = &sc->rx_ring;
570 	struct rtwn_rx_data *rx_data;
571 	int i;
572 
573 	for (i = 0; i < RTWN_RX_LIST_COUNT; i++) {
574 		rx_data = &rx_ring->rx_data[i];
575 		rtwn_setup_rx_desc(sc, &rx_ring->desc[i], rx_data->paddr,
576 		    MCLBYTES, i);
577 	}
578 }
579 
580 static void
581 rtwn_free_rx_list(struct rtwn_softc *sc)
582 {
583 	struct rtwn_rx_ring *rx_ring = &sc->rx_ring;
584 	struct rtwn_rx_data *rx_data;
585 	int i;
586 
587 	if (rx_ring->desc_dmat != NULL) {
588 		if (rx_ring->desc != NULL) {
589 			bus_dmamap_unload(rx_ring->desc_dmat,
590 			    rx_ring->desc_map);
591 			bus_dmamem_free(rx_ring->desc_dmat, rx_ring->desc,
592 			    rx_ring->desc_map);
593 			rx_ring->desc = NULL;
594 		}
595 		bus_dma_tag_destroy(rx_ring->desc_dmat);
596 		rx_ring->desc_dmat = NULL;
597 	}
598 
599 	for (i = 0; i < RTWN_RX_LIST_COUNT; i++) {
600 		rx_data = &rx_ring->rx_data[i];
601 
602 		if (rx_data->m != NULL) {
603 			bus_dmamap_unload(rx_ring->data_dmat, rx_data->map);
604 			m_freem(rx_data->m);
605 			rx_data->m = NULL;
606 		}
607 		bus_dmamap_destroy(rx_ring->data_dmat, rx_data->map);
608 		rx_data->map = NULL;
609 	}
610 	if (rx_ring->data_dmat != NULL) {
611 		bus_dma_tag_destroy(rx_ring->data_dmat);
612 		rx_ring->data_dmat = NULL;
613 	}
614 }
615 
616 static int
617 rtwn_alloc_tx_list(struct rtwn_softc *sc, int qid)
618 {
619 	struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid];
620 	struct rtwn_tx_data *tx_data;
621 	bus_size_t size;
622 	int i, error;
623 
624 	size = sizeof(struct r92c_tx_desc) * RTWN_TX_LIST_COUNT;
625 	error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), PAGE_SIZE, 0,
626 	    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
627 	    size, 1, size, 0, NULL, NULL, &tx_ring->desc_dmat);
628 	if (error != 0) {
629 		device_printf(sc->sc_dev, "could not create tx ring DMA tag\n");
630 		goto fail;
631 	}
632 
633 	error = bus_dmamem_alloc(tx_ring->desc_dmat, (void **)&tx_ring->desc,
634 	    BUS_DMA_NOWAIT | BUS_DMA_ZERO, &tx_ring->desc_map);
635 	if (error != 0) {
636 		device_printf(sc->sc_dev, "can't map tx ring DMA memory\n");
637 		goto fail;
638 	}
639 	error = bus_dmamap_load(tx_ring->desc_dmat, tx_ring->desc_map,
640 	    tx_ring->desc, size, rtwn_dma_map_addr, &tx_ring->paddr,
641 	    BUS_DMA_NOWAIT);
642 	if (error != 0) {
643 		device_printf(sc->sc_dev, "could not load desc DMA map\n");
644 		goto fail;
645 	}
646 
647 	error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
648 	    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES,
649 	    1, MCLBYTES, 0, NULL, NULL, &tx_ring->data_dmat);
650 	if (error != 0) {
651 		device_printf(sc->sc_dev, "could not create tx buf DMA tag\n");
652 		goto fail;
653 	}
654 
655 	for (i = 0; i < RTWN_TX_LIST_COUNT; i++) {
656 		struct r92c_tx_desc *desc = &tx_ring->desc[i];
657 
658 		/* setup tx desc */
659 		desc->nextdescaddr = htole32(tx_ring->paddr +
660 		    + sizeof(struct r92c_tx_desc)
661 		    * ((i + 1) % RTWN_TX_LIST_COUNT));
662 		tx_data = &tx_ring->tx_data[i];
663 		error = bus_dmamap_create(tx_ring->data_dmat, 0, &tx_data->map);
664 		if (error != 0) {
665 			device_printf(sc->sc_dev,
666 			    "could not create tx buf DMA map\n");
667 			goto fail;
668 		}
669 		tx_data->m = NULL;
670 		tx_data->ni = NULL;
671 	}
672 	return (0);
673 
674 fail:
675 	rtwn_free_tx_list(sc, qid);
676 	return (error);
677 }
678 
679 static void
680 rtwn_reset_tx_list(struct rtwn_softc *sc, int qid)
681 {
682 	struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid];
683 	int i;
684 
685 	for (i = 0; i < RTWN_TX_LIST_COUNT; i++) {
686 		struct r92c_tx_desc *desc = &tx_ring->desc[i];
687 		struct rtwn_tx_data *tx_data = &tx_ring->tx_data[i];
688 
689 		memset(desc, 0, sizeof(*desc) -
690 		    (sizeof(desc->reserved) + sizeof(desc->nextdescaddr64) +
691 		    sizeof(desc->nextdescaddr)));
692 
693 		if (tx_data->m != NULL) {
694 			bus_dmamap_unload(tx_ring->data_dmat, tx_data->map);
695 			m_freem(tx_data->m);
696 			tx_data->m = NULL;
697 		}
698 		if (tx_data->ni != NULL) {
699 			ieee80211_free_node(tx_data->ni);
700 			tx_data->ni = NULL;
701 		}
702 	}
703 
704 	bus_dmamap_sync(tx_ring->desc_dmat, tx_ring->desc_map,
705 	    BUS_DMASYNC_POSTWRITE);
706 
707 	sc->qfullmsk &= ~(1 << qid);
708 	tx_ring->queued = 0;
709 	tx_ring->cur = 0;
710 }
711 
712 static void
713 rtwn_free_tx_list(struct rtwn_softc *sc, int qid)
714 {
715 	struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid];
716 	struct rtwn_tx_data *tx_data;
717 	int i;
718 
719 	if (tx_ring->desc_dmat != NULL) {
720 		if (tx_ring->desc != NULL) {
721 			bus_dmamap_unload(tx_ring->desc_dmat,
722 			    tx_ring->desc_map);
723 			bus_dmamem_free(tx_ring->desc_dmat, tx_ring->desc,
724 			    tx_ring->desc_map);
725 		}
726 		bus_dma_tag_destroy(tx_ring->desc_dmat);
727 	}
728 
729 	for (i = 0; i < RTWN_TX_LIST_COUNT; i++) {
730 		tx_data = &tx_ring->tx_data[i];
731 
732 		if (tx_data->m != NULL) {
733 			bus_dmamap_unload(tx_ring->data_dmat, tx_data->map);
734 			m_freem(tx_data->m);
735 			tx_data->m = NULL;
736 		}
737 	}
738 	if (tx_ring->data_dmat != NULL) {
739 		bus_dma_tag_destroy(tx_ring->data_dmat);
740 		tx_ring->data_dmat = NULL;
741 	}
742 
743 	sc->qfullmsk &= ~(1 << qid);
744 	tx_ring->queued = 0;
745 	tx_ring->cur = 0;
746 }
747 
748 
749 static struct ieee80211vap *
750 rtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
751     enum ieee80211_opmode opmode, int flags,
752     const uint8_t bssid[IEEE80211_ADDR_LEN],
753     const uint8_t mac[IEEE80211_ADDR_LEN])
754 {
755 	struct rtwn_vap *rvp;
756 	struct ieee80211vap *vap;
757 
758 	if (!TAILQ_EMPTY(&ic->ic_vaps))
759 		return (NULL);
760 
761 	rvp = malloc(sizeof(struct rtwn_vap), M_80211_VAP, M_WAITOK | M_ZERO);
762 	vap = &rvp->vap;
763 	if (ieee80211_vap_setup(ic, vap, name, unit, opmode,
764 	    flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) {
765 		/* out of memory */
766 		 free(rvp, M_80211_VAP);
767 		 return (NULL);
768 	}
769 
770 	/* Override state transition machine. */
771 	rvp->newstate = vap->iv_newstate;
772 	vap->iv_newstate = rtwn_newstate;
773 
774 	/* Complete setup. */
775 	ieee80211_vap_attach(vap, ieee80211_media_change,
776 	    ieee80211_media_status, mac);
777 	ic->ic_opmode = opmode;
778 	return (vap);
779 }
780 
781 static void
782 rtwn_vap_delete(struct ieee80211vap *vap)
783 {
784 	struct rtwn_vap *rvp = RTWN_VAP(vap);
785 
786 	ieee80211_vap_detach(vap);
787 	free(rvp, M_80211_VAP);
788 }
789 
790 static void
791 rtwn_write_1(struct rtwn_softc *sc, uint16_t addr, uint8_t val)
792 {
793 
794 	bus_space_write_1(sc->sc_st, sc->sc_sh, addr, val);
795 }
796 
797 static void
798 rtwn_write_2(struct rtwn_softc *sc, uint16_t addr, uint16_t val)
799 {
800 
801 	val = htole16(val);
802 	bus_space_write_2(sc->sc_st, sc->sc_sh, addr, val);
803 }
804 
805 static void
806 rtwn_write_4(struct rtwn_softc *sc, uint16_t addr, uint32_t val)
807 {
808 
809 	val = htole32(val);
810 	bus_space_write_4(sc->sc_st, sc->sc_sh, addr, val);
811 }
812 
813 static uint8_t
814 rtwn_read_1(struct rtwn_softc *sc, uint16_t addr)
815 {
816 
817 	return (bus_space_read_1(sc->sc_st, sc->sc_sh, addr));
818 }
819 
820 static uint16_t
821 rtwn_read_2(struct rtwn_softc *sc, uint16_t addr)
822 {
823 
824 	return (bus_space_read_2(sc->sc_st, sc->sc_sh, addr));
825 }
826 
827 static uint32_t
828 rtwn_read_4(struct rtwn_softc *sc, uint16_t addr)
829 {
830 
831 	return (bus_space_read_4(sc->sc_st, sc->sc_sh, addr));
832 }
833 
834 static int
835 rtwn_fw_cmd(struct rtwn_softc *sc, uint8_t id, const void *buf, int len)
836 {
837 	struct r92c_fw_cmd cmd;
838 	int ntries;
839 
840 	/* Wait for current FW box to be empty. */
841 	for (ntries = 0; ntries < 100; ntries++) {
842 		if (!(rtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur)))
843 			break;
844 		DELAY(1);
845 	}
846 	if (ntries == 100) {
847 		device_printf(sc->sc_dev,
848 		    "could not send firmware command %d\n", id);
849 		return (ETIMEDOUT);
850 	}
851 	memset(&cmd, 0, sizeof(cmd));
852 	cmd.id = id;
853 	if (len > 3)
854 		cmd.id |= R92C_CMD_FLAG_EXT;
855 	KASSERT(len <= sizeof(cmd.msg), ("rtwn_fw_cmd\n"));
856 	memcpy(cmd.msg, buf, len);
857 
858 	/* Write the first word last since that will trigger the FW. */
859 	rtwn_write_2(sc, R92C_HMEBOX_EXT(sc->fwcur), *((uint8_t *)&cmd + 4));
860 	rtwn_write_4(sc, R92C_HMEBOX(sc->fwcur), *((uint8_t *)&cmd + 0));
861 
862 	sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX;
863 
864 	/* Give firmware some time for processing. */
865 	DELAY(2000);
866 
867 	return (0);
868 }
869 
870 static void
871 rtwn_rf_write(struct rtwn_softc *sc, int chain, uint8_t addr, uint32_t val)
872 {
873 	rtwn_bb_write(sc, R92C_LSSI_PARAM(chain),
874 	    SM(R92C_LSSI_PARAM_ADDR, addr) |
875 	    SM(R92C_LSSI_PARAM_DATA, val));
876 }
877 
878 static uint32_t
879 rtwn_rf_read(struct rtwn_softc *sc, int chain, uint8_t addr)
880 {
881 	uint32_t reg[R92C_MAX_CHAINS], val;
882 
883 	reg[0] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(0));
884 	if (chain != 0)
885 		reg[chain] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(chain));
886 
887 	rtwn_bb_write(sc, R92C_HSSI_PARAM2(0),
888 	    reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE);
889 	DELAY(1000);
890 
891 	rtwn_bb_write(sc, R92C_HSSI_PARAM2(chain),
892 	    RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) |
893 	    R92C_HSSI_PARAM2_READ_EDGE);
894 	DELAY(1000);
895 
896 	rtwn_bb_write(sc, R92C_HSSI_PARAM2(0),
897 	    reg[0] | R92C_HSSI_PARAM2_READ_EDGE);
898 	DELAY(1000);
899 
900 	if (rtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI)
901 		val = rtwn_bb_read(sc, R92C_HSPI_READBACK(chain));
902 	else
903 		val = rtwn_bb_read(sc, R92C_LSSI_READBACK(chain));
904 	return (MS(val, R92C_LSSI_READBACK_DATA));
905 }
906 
907 static int
908 rtwn_llt_write(struct rtwn_softc *sc, uint32_t addr, uint32_t data)
909 {
910 	int ntries;
911 
912 	rtwn_write_4(sc, R92C_LLT_INIT,
913 	    SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) |
914 	    SM(R92C_LLT_INIT_ADDR, addr) |
915 	    SM(R92C_LLT_INIT_DATA, data));
916 	/* Wait for write operation to complete. */
917 	for (ntries = 0; ntries < 20; ntries++) {
918 		if (MS(rtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) ==
919 		    R92C_LLT_INIT_OP_NO_ACTIVE)
920 			return (0);
921 		DELAY(5);
922 	}
923 	return (ETIMEDOUT);
924 }
925 
926 static uint8_t
927 rtwn_efuse_read_1(struct rtwn_softc *sc, uint16_t addr)
928 {
929 	uint32_t reg;
930 	int ntries;
931 
932 	reg = rtwn_read_4(sc, R92C_EFUSE_CTRL);
933 	reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr);
934 	reg &= ~R92C_EFUSE_CTRL_VALID;
935 	rtwn_write_4(sc, R92C_EFUSE_CTRL, reg);
936 	/* Wait for read operation to complete. */
937 	for (ntries = 0; ntries < 100; ntries++) {
938 		reg = rtwn_read_4(sc, R92C_EFUSE_CTRL);
939 		if (reg & R92C_EFUSE_CTRL_VALID)
940 			return (MS(reg, R92C_EFUSE_CTRL_DATA));
941 		DELAY(5);
942 	}
943 	device_printf(sc->sc_dev,
944 	    "could not read efuse byte at address 0x%x\n", addr);
945 	return (0xff);
946 }
947 
948 static void
949 rtwn_efuse_read(struct rtwn_softc *sc)
950 {
951 	uint8_t *rom = (uint8_t *)&sc->rom;
952 	uint16_t addr = 0;
953 	uint32_t reg;
954 	uint8_t off, msk;
955 	int i;
956 
957 	reg = rtwn_read_2(sc, R92C_SYS_ISO_CTRL);
958 	if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) {
959 		rtwn_write_2(sc, R92C_SYS_ISO_CTRL,
960 		    reg | R92C_SYS_ISO_CTRL_PWC_EV12V);
961 	}
962 	reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN);
963 	if (!(reg & R92C_SYS_FUNC_EN_ELDR)) {
964 		rtwn_write_2(sc, R92C_SYS_FUNC_EN,
965 		    reg | R92C_SYS_FUNC_EN_ELDR);
966 	}
967 	reg = rtwn_read_2(sc, R92C_SYS_CLKR);
968 	if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) !=
969 	    (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) {
970 		rtwn_write_2(sc, R92C_SYS_CLKR,
971 		    reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M);
972 	}
973 	memset(&sc->rom, 0xff, sizeof(sc->rom));
974 	while (addr < 512) {
975 		reg = rtwn_efuse_read_1(sc, addr);
976 		if (reg == 0xff)
977 			break;
978 		addr++;
979 		off = reg >> 4;
980 		msk = reg & 0xf;
981 		for (i = 0; i < 4; i++) {
982 			if (msk & (1 << i))
983 				continue;
984 			rom[off * 8 + i * 2 + 0] =
985 			    rtwn_efuse_read_1(sc, addr);
986 			addr++;
987 			rom[off * 8 + i * 2 + 1] =
988 			    rtwn_efuse_read_1(sc, addr);
989 			addr++;
990 		}
991 	}
992 #ifdef RTWN_DEBUG
993 	if (sc->sc_debug >= 2) {
994 		/* Dump ROM content. */
995 		printf("\n");
996 		for (i = 0; i < sizeof(sc->rom); i++)
997 			printf("%02x:", rom[i]);
998 		printf("\n");
999 	}
1000 #endif
1001 }
1002 
1003 static int
1004 rtwn_read_chipid(struct rtwn_softc *sc)
1005 {
1006 	uint32_t reg;
1007 
1008 	reg = rtwn_read_4(sc, R92C_SYS_CFG);
1009 	if (reg & R92C_SYS_CFG_TRP_VAUX_EN)
1010 		/* Unsupported test chip. */
1011 		return (EIO);
1012 
1013 	if (reg & R92C_SYS_CFG_TYPE_92C) {
1014 		sc->chip |= RTWN_CHIP_92C;
1015 		/* Check if it is a castrated 8192C. */
1016 		if (MS(rtwn_read_4(sc, R92C_HPON_FSM),
1017 		    R92C_HPON_FSM_CHIP_BONDING_ID) ==
1018 		    R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R)
1019 			sc->chip |= RTWN_CHIP_92C_1T2R;
1020 	}
1021 	if (reg & R92C_SYS_CFG_VENDOR_UMC) {
1022 		sc->chip |= RTWN_CHIP_UMC;
1023 		if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0)
1024 			sc->chip |= RTWN_CHIP_UMC_A_CUT;
1025 	}
1026 	return (0);
1027 }
1028 
1029 static void
1030 rtwn_read_rom(struct rtwn_softc *sc)
1031 {
1032 	struct r92c_rom *rom = &sc->rom;
1033 
1034 	/* Read full ROM image. */
1035 	rtwn_efuse_read(sc);
1036 
1037 	if (rom->id != 0x8129)
1038 		device_printf(sc->sc_dev, "invalid EEPROM ID 0x%x\n", rom->id);
1039 
1040 	/* XXX Weird but this is what the vendor driver does. */
1041 	sc->pa_setting = rtwn_efuse_read_1(sc, 0x1fa);
1042 	DPRINTF(("PA setting=0x%x\n", sc->pa_setting));
1043 
1044 	sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE);
1045 
1046 	sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY);
1047 	DPRINTF(("regulatory type=%d\n", sc->regulatory));
1048 
1049 	IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr);
1050 }
1051 
1052 static __inline uint8_t
1053 rate2ridx(uint8_t rate)
1054 {
1055 	switch (rate) {
1056 	case 12:	return 4;
1057 	case 18:	return 5;
1058 	case 24:	return 6;
1059 	case 36:	return 7;
1060 	case 48:	return 8;
1061 	case 72:	return 9;
1062 	case 96:	return 10;
1063 	case 108:	return 11;
1064 	case 2:		return 0;
1065 	case 4:		return 1;
1066 	case 11:	return 2;
1067 	case 22:	return 3;
1068 	default:	return RTWN_RIDX_UNKNOWN;
1069 	}
1070 }
1071 
1072 /*
1073  * Initialize rate adaptation in firmware.
1074  */
1075 static int
1076 rtwn_ra_init(struct rtwn_softc *sc)
1077 {
1078 	struct ieee80211com *ic = &sc->sc_ic;
1079 	struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
1080 	struct ieee80211_node *ni = ieee80211_ref_node(vap->iv_bss);
1081 	struct ieee80211_rateset *rs = &ni->ni_rates;
1082 	struct r92c_fw_cmd_macid_cfg cmd;
1083 	uint32_t rates, basicrates;
1084 	uint8_t maxrate, maxbasicrate, mode, ridx;
1085 	int error, i;
1086 
1087 	/* Get normal and basic rates mask. */
1088 	rates = basicrates = 0;
1089 	maxrate = maxbasicrate = 0;
1090 	for (i = 0; i < rs->rs_nrates; i++) {
1091 		/* Convert 802.11 rate to HW rate index. */
1092 		ridx = rate2ridx(IEEE80211_RV(rs->rs_rates[i]));
1093 		if (ridx == RTWN_RIDX_UNKNOWN)	/* Unknown rate, skip. */
1094 			continue;
1095 		rates |= 1 << ridx;
1096 		if (ridx > maxrate)
1097 			maxrate = ridx;
1098 		if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) {
1099 			basicrates |= 1 << ridx;
1100 			if (ridx > maxbasicrate)
1101 				maxbasicrate = ridx;
1102 		}
1103 	}
1104 	if (ic->ic_curmode == IEEE80211_MODE_11B)
1105 		mode = R92C_RAID_11B;
1106 	else
1107 		mode = R92C_RAID_11BG;
1108 	DPRINTF(("mode=0x%x rates=0x%08x, basicrates=0x%08x\n",
1109 	    mode, rates, basicrates));
1110 
1111 	/* Set rates mask for group addressed frames. */
1112 	cmd.macid = RTWN_MACID_BC | RTWN_MACID_VALID;
1113 	cmd.mask = htole32(mode << 28 | basicrates);
1114 	error = rtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd));
1115 	if (error != 0) {
1116 		device_printf(sc->sc_dev,
1117 		    "could not add broadcast station\n");
1118 		return (error);
1119 	}
1120 	/* Set initial MRR rate. */
1121 	DPRINTF(("maxbasicrate=%d\n", maxbasicrate));
1122 	rtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BC),
1123 	    maxbasicrate);
1124 
1125 	/* Set rates mask for unicast frames. */
1126 	cmd.macid = RTWN_MACID_BSS | RTWN_MACID_VALID;
1127 	cmd.mask = htole32(mode << 28 | rates);
1128 	error = rtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd));
1129 	if (error != 0) {
1130 		device_printf(sc->sc_dev, "could not add BSS station\n");
1131 		return (error);
1132 	}
1133 	/* Set initial MRR rate. */
1134 	DPRINTF(("maxrate=%d\n", maxrate));
1135 	rtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BSS),
1136 	    maxrate);
1137 
1138 	/* Configure Automatic Rate Fallback Register. */
1139 	if (ic->ic_curmode == IEEE80211_MODE_11B) {
1140 		if (rates & 0x0c)
1141 			rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0d));
1142 		else
1143 			rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0f));
1144 	} else
1145 		rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0ff5));
1146 
1147 	/* Indicate highest supported rate. */
1148 	ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1];
1149 	return (0);
1150 }
1151 
1152 static void
1153 rtwn_tsf_sync_enable(struct rtwn_softc *sc)
1154 {
1155 	struct ieee80211com *ic = &sc->sc_ic;
1156 	struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
1157 	struct ieee80211_node *ni = vap->iv_bss;
1158 	uint64_t tsf;
1159 
1160 	/* Enable TSF synchronization. */
1161 	rtwn_write_1(sc, R92C_BCN_CTRL,
1162 	    rtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0);
1163 
1164 	rtwn_write_1(sc, R92C_BCN_CTRL,
1165 	    rtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN);
1166 
1167 	/* Set initial TSF. */
1168 	memcpy(&tsf, ni->ni_tstamp.data, 8);
1169 	tsf = le64toh(tsf);
1170 	tsf = tsf - (tsf % (vap->iv_bss->ni_intval * IEEE80211_DUR_TU));
1171 	tsf -= IEEE80211_DUR_TU;
1172 	rtwn_write_4(sc, R92C_TSFTR + 0, tsf);
1173 	rtwn_write_4(sc, R92C_TSFTR + 4, tsf >> 32);
1174 
1175 	rtwn_write_1(sc, R92C_BCN_CTRL,
1176 	    rtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN);
1177 }
1178 
1179 static void
1180 rtwn_set_led(struct rtwn_softc *sc, int led, int on)
1181 {
1182 	uint8_t reg;
1183 
1184 	if (led == RTWN_LED_LINK) {
1185 		reg = rtwn_read_1(sc, R92C_LEDCFG2) & 0xf0;
1186 		if (!on)
1187 			reg |= R92C_LEDCFG2_DIS;
1188 		else
1189 			reg |= R92C_LEDCFG2_EN;
1190 		rtwn_write_1(sc, R92C_LEDCFG2, reg);
1191 		sc->ledlink = on;	/* Save LED state. */
1192 	}
1193 }
1194 
1195 static void
1196 rtwn_calib_to(void *arg)
1197 {
1198 	struct rtwn_softc *sc = arg;
1199 	struct r92c_fw_cmd_rssi cmd;
1200 
1201 	if (sc->avg_pwdb != -1) {
1202 		/* Indicate Rx signal strength to FW for rate adaptation. */
1203 		memset(&cmd, 0, sizeof(cmd));
1204 		cmd.macid = 0;	/* BSS. */
1205 		cmd.pwdb = sc->avg_pwdb;
1206 		DPRINTFN(3, ("sending RSSI command avg=%d\n", sc->avg_pwdb));
1207 		rtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, sizeof(cmd));
1208 	}
1209 
1210 	/* Do temperature compensation. */
1211 	rtwn_temp_calib(sc);
1212 
1213 	callout_reset(&sc->calib_to, hz * 2, rtwn_calib_to, sc);
1214 }
1215 
1216 static int
1217 rtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
1218 {
1219 	struct rtwn_vap *rvp = RTWN_VAP(vap);
1220 	struct ieee80211com *ic = vap->iv_ic;
1221 	struct ieee80211_node *ni = vap->iv_bss;
1222 	struct rtwn_softc *sc = ic->ic_softc;
1223 	uint32_t reg;
1224 
1225 	IEEE80211_UNLOCK(ic);
1226 	RTWN_LOCK(sc);
1227 
1228 	if (vap->iv_state == IEEE80211_S_RUN) {
1229 		/* Stop calibration. */
1230 		callout_stop(&sc->calib_to);
1231 
1232 		/* Turn link LED off. */
1233 		rtwn_set_led(sc, RTWN_LED_LINK, 0);
1234 
1235 		/* Set media status to 'No Link'. */
1236 		reg = rtwn_read_4(sc, R92C_CR);
1237 		reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_NOLINK);
1238 		rtwn_write_4(sc, R92C_CR, reg);
1239 
1240 		/* Stop Rx of data frames. */
1241 		rtwn_write_2(sc, R92C_RXFLTMAP2, 0);
1242 
1243 		/* Rest TSF. */
1244 		rtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03);
1245 
1246 		/* Disable TSF synchronization. */
1247 		rtwn_write_1(sc, R92C_BCN_CTRL,
1248 		    rtwn_read_1(sc, R92C_BCN_CTRL) |
1249 		    R92C_BCN_CTRL_DIS_TSF_UDT0);
1250 
1251 		/* Reset EDCA parameters. */
1252 		rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217);
1253 		rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317);
1254 		rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320);
1255 		rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444);
1256 	}
1257 	switch (nstate) {
1258 	case IEEE80211_S_INIT:
1259 		/* Turn link LED off. */
1260 		rtwn_set_led(sc, RTWN_LED_LINK, 0);
1261 		break;
1262 	case IEEE80211_S_SCAN:
1263 		/* Make link LED blink during scan. */
1264 		rtwn_set_led(sc, RTWN_LED_LINK, !sc->ledlink);
1265 
1266 		/* Pause AC Tx queues. */
1267 		rtwn_write_1(sc, R92C_TXPAUSE,
1268 		    rtwn_read_1(sc, R92C_TXPAUSE) | 0x0f);
1269 		break;
1270 	case IEEE80211_S_AUTH:
1271 		rtwn_set_chan(sc, ic->ic_curchan, NULL);
1272 		break;
1273 	case IEEE80211_S_RUN:
1274 		if (ic->ic_opmode == IEEE80211_M_MONITOR) {
1275 			/* Enable Rx of data frames. */
1276 			rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff);
1277 
1278 			/* Turn link LED on. */
1279 			rtwn_set_led(sc, RTWN_LED_LINK, 1);
1280 			break;
1281 		}
1282 
1283 		/* Set media status to 'Associated'. */
1284 		reg = rtwn_read_4(sc, R92C_CR);
1285 		reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA);
1286 		rtwn_write_4(sc, R92C_CR, reg);
1287 
1288 		/* Set BSSID. */
1289 		rtwn_write_4(sc, R92C_BSSID + 0, le32dec(&ni->ni_bssid[0]));
1290 		rtwn_write_4(sc, R92C_BSSID + 4, le16dec(&ni->ni_bssid[4]));
1291 
1292 		if (ic->ic_curmode == IEEE80211_MODE_11B)
1293 			rtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0);
1294 		else	/* 802.11b/g */
1295 			rtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3);
1296 
1297 		/* Enable Rx of data frames. */
1298 		rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff);
1299 
1300 		/* Flush all AC queues. */
1301 		rtwn_write_1(sc, R92C_TXPAUSE, 0);
1302 
1303 		/* Set beacon interval. */
1304 		rtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval);
1305 
1306 		/* Allow Rx from our BSSID only. */
1307 		rtwn_write_4(sc, R92C_RCR,
1308 		    rtwn_read_4(sc, R92C_RCR) |
1309 		    R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN);
1310 
1311 		/* Enable TSF synchronization. */
1312 		rtwn_tsf_sync_enable(sc);
1313 
1314 		rtwn_write_1(sc, R92C_SIFS_CCK + 1, 10);
1315 		rtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10);
1316 		rtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10);
1317 		rtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10);
1318 		rtwn_write_1(sc, R92C_R2T_SIFS + 1, 10);
1319 		rtwn_write_1(sc, R92C_T2T_SIFS + 1, 10);
1320 
1321 		/* Intialize rate adaptation. */
1322 		rtwn_ra_init(sc);
1323 		/* Turn link LED on. */
1324 		rtwn_set_led(sc, RTWN_LED_LINK, 1);
1325 
1326 		sc->avg_pwdb = -1;	/* Reset average RSSI. */
1327 		/* Reset temperature calibration state machine. */
1328 		sc->thcal_state = 0;
1329 		sc->thcal_lctemp = 0;
1330 		/* Start periodic calibration. */
1331 		callout_reset(&sc->calib_to, hz * 2, rtwn_calib_to, sc);
1332 		break;
1333 	default:
1334 		break;
1335 	}
1336 	RTWN_UNLOCK(sc);
1337 	IEEE80211_LOCK(ic);
1338 	return (rvp->newstate(vap, nstate, arg));
1339 }
1340 
1341 static int
1342 rtwn_updateedca(struct ieee80211com *ic)
1343 {
1344 	struct rtwn_softc *sc = ic->ic_softc;
1345 	const uint16_t aci2reg[WME_NUM_AC] = {
1346 		R92C_EDCA_BE_PARAM,
1347 		R92C_EDCA_BK_PARAM,
1348 		R92C_EDCA_VI_PARAM,
1349 		R92C_EDCA_VO_PARAM
1350 	};
1351 	int aci, aifs, slottime;
1352 
1353 	IEEE80211_LOCK(ic);
1354 	slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20;
1355 	for (aci = 0; aci < WME_NUM_AC; aci++) {
1356 		const struct wmeParams *ac =
1357 		    &ic->ic_wme.wme_chanParams.cap_wmeParams[aci];
1358 		/* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */
1359 		aifs = ac->wmep_aifsn * slottime + 10;
1360 		rtwn_write_4(sc, aci2reg[aci],
1361 		    SM(R92C_EDCA_PARAM_TXOP, ac->wmep_txopLimit) |
1362 		    SM(R92C_EDCA_PARAM_ECWMIN, ac->wmep_logcwmin) |
1363 		    SM(R92C_EDCA_PARAM_ECWMAX, ac->wmep_logcwmax) |
1364 		    SM(R92C_EDCA_PARAM_AIFS, aifs));
1365 	}
1366 	IEEE80211_UNLOCK(ic);
1367 	return (0);
1368 }
1369 
1370 static void
1371 rtwn_update_avgrssi(struct rtwn_softc *sc, int rate, int8_t rssi)
1372 {
1373 	int pwdb;
1374 
1375 	/* Convert antenna signal to percentage. */
1376 	if (rssi <= -100 || rssi >= 20)
1377 		pwdb = 0;
1378 	else if (rssi >= 0)
1379 		pwdb = 100;
1380 	else
1381 		pwdb = 100 + rssi;
1382 	if (RTWN_RATE_IS_CCK(rate)) {
1383 		/* CCK gain is smaller than OFDM/MCS gain. */
1384 		pwdb += 6;
1385 		if (pwdb > 100)
1386 			pwdb = 100;
1387 		if (pwdb <= 14)
1388 			pwdb -= 4;
1389 		else if (pwdb <= 26)
1390 			pwdb -= 8;
1391 		else if (pwdb <= 34)
1392 			pwdb -= 6;
1393 		else if (pwdb <= 42)
1394 			pwdb -= 2;
1395 	}
1396 	if (sc->avg_pwdb == -1)	/* Init. */
1397 		sc->avg_pwdb = pwdb;
1398 	else if (sc->avg_pwdb < pwdb)
1399 		sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1;
1400 	else
1401 		sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20);
1402 	DPRINTFN(4, ("PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb));
1403 }
1404 
1405 static int8_t
1406 rtwn_get_rssi(struct rtwn_softc *sc, int rate, void *physt)
1407 {
1408 	static const int8_t cckoff[] = { 16, -12, -26, -46 };
1409 	struct r92c_rx_phystat *phy;
1410 	struct r92c_rx_cck *cck;
1411 	uint8_t rpt;
1412 	int8_t rssi;
1413 
1414 	if (RTWN_RATE_IS_CCK(rate)) {
1415 		cck = (struct r92c_rx_cck *)physt;
1416 		if (sc->sc_flags & RTWN_FLAG_CCK_HIPWR) {
1417 			rpt = (cck->agc_rpt >> 5) & 0x3;
1418 			rssi = (cck->agc_rpt & 0x1f) << 1;
1419 		} else {
1420 			rpt = (cck->agc_rpt >> 6) & 0x3;
1421 			rssi = cck->agc_rpt & 0x3e;
1422 		}
1423 		rssi = cckoff[rpt] - rssi;
1424 	} else {	/* OFDM/HT. */
1425 		phy = (struct r92c_rx_phystat *)physt;
1426 		rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110;
1427 	}
1428 	return (rssi);
1429 }
1430 
1431 static void
1432 rtwn_rx_frame(struct rtwn_softc *sc, struct r92c_rx_desc *rx_desc,
1433     struct rtwn_rx_data *rx_data, int desc_idx)
1434 {
1435 	struct ieee80211com *ic = &sc->sc_ic;
1436 	struct ieee80211_frame_min *wh;
1437 	struct ieee80211_node *ni;
1438 	struct r92c_rx_phystat *phy = NULL;
1439 	uint32_t rxdw0, rxdw3;
1440 	struct mbuf *m, *m1;
1441 	bus_dma_segment_t segs[1];
1442 	bus_addr_t physaddr;
1443 	uint8_t rate;
1444 	int8_t rssi = 0, nf;
1445 	int infosz, nsegs, pktlen, shift, error;
1446 
1447 	rxdw0 = le32toh(rx_desc->rxdw0);
1448 	rxdw3 = le32toh(rx_desc->rxdw3);
1449 
1450 	if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) {
1451 		/*
1452 		 * This should not happen since we setup our Rx filter
1453 		 * to not receive these frames.
1454 		 */
1455 		counter_u64_add(ic->ic_ierrors, 1);
1456 		return;
1457 	}
1458 
1459 	pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN);
1460 	if (__predict_false(pktlen < sizeof(struct ieee80211_frame_ack) ||
1461 	    pktlen > MCLBYTES)) {
1462 		counter_u64_add(ic->ic_ierrors, 1);
1463 		return;
1464 	}
1465 
1466 	rate = MS(rxdw3, R92C_RXDW3_RATE);
1467 	infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8;
1468 	if (infosz > sizeof(struct r92c_rx_phystat))
1469 		infosz = sizeof(struct r92c_rx_phystat);
1470 	shift = MS(rxdw0, R92C_RXDW0_SHIFT);
1471 
1472 	/* Get RSSI from PHY status descriptor if present. */
1473 	if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) {
1474 		phy = mtod(rx_data->m, struct r92c_rx_phystat *);
1475 		rssi = rtwn_get_rssi(sc, rate, phy);
1476 		/* Update our average RSSI. */
1477 		rtwn_update_avgrssi(sc, rate, rssi);
1478 	}
1479 
1480 	DPRINTFN(5, ("Rx frame len=%d rate=%d infosz=%d shift=%d rssi=%d\n",
1481 	    pktlen, rate, infosz, shift, rssi));
1482 
1483 	m1 = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1484 	if (m1 == NULL) {
1485 		counter_u64_add(ic->ic_ierrors, 1);
1486 		return;
1487 	}
1488 	bus_dmamap_unload(sc->rx_ring.data_dmat, rx_data->map);
1489 
1490 	error = bus_dmamap_load(sc->rx_ring.data_dmat, rx_data->map,
1491 	     mtod(m1, void *), MCLBYTES, rtwn_dma_map_addr,
1492 	     &physaddr, 0);
1493 	if (error != 0) {
1494 		m_freem(m1);
1495 
1496 		if (bus_dmamap_load_mbuf_sg(sc->rx_ring.data_dmat,
1497 		    rx_data->map, rx_data->m, segs, &nsegs, 0))
1498 			panic("%s: could not load old RX mbuf",
1499 			    device_get_name(sc->sc_dev));
1500 
1501 		/* Physical address may have changed. */
1502 		rtwn_setup_rx_desc(sc, rx_desc, physaddr, MCLBYTES, desc_idx);
1503 		counter_u64_add(ic->ic_ierrors, 1);
1504 		return;
1505 	}
1506 
1507 	/* Finalize mbuf. */
1508 	m = rx_data->m;
1509 	rx_data->m = m1;
1510 	m->m_pkthdr.len = m->m_len = pktlen + infosz + shift;
1511 
1512 	/* Update RX descriptor. */
1513 	rtwn_setup_rx_desc(sc, rx_desc, physaddr, MCLBYTES, desc_idx);
1514 
1515 	/* Get ieee80211 frame header. */
1516 	if (rxdw0 & R92C_RXDW0_PHYST)
1517 		m_adj(m, infosz + shift);
1518 	else
1519 		m_adj(m, shift);
1520 
1521 	nf = -95;
1522 	if (ieee80211_radiotap_active(ic)) {
1523 		struct rtwn_rx_radiotap_header *tap = &sc->sc_rxtap;
1524 
1525 		tap->wr_flags = 0;
1526 		if (!(rxdw3 & R92C_RXDW3_HT)) {
1527 			tap->wr_rate = ridx2rate[rate];
1528 		} else if (rate >= 12) {	/* MCS0~15. */
1529 			/* Bit 7 set means HT MCS instead of rate. */
1530 			tap->wr_rate = 0x80 | (rate - 12);
1531 		}
1532 		tap->wr_dbm_antsignal = rssi;
1533 		tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq);
1534 		tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags);
1535 	}
1536 
1537 	RTWN_UNLOCK(sc);
1538 	wh = mtod(m, struct ieee80211_frame_min *);
1539 	if (m->m_len >= sizeof(*wh))
1540 		ni = ieee80211_find_rxnode(ic, wh);
1541 	else
1542 		ni = NULL;
1543 
1544 	/* Send the frame to the 802.11 layer. */
1545 	if (ni != NULL) {
1546 		(void)ieee80211_input(ni, m, rssi - nf, nf);
1547 		/* Node is no longer needed. */
1548 		ieee80211_free_node(ni);
1549 	} else
1550 		(void)ieee80211_input_all(ic, m, rssi - nf, nf);
1551 
1552 	RTWN_LOCK(sc);
1553 }
1554 
1555 static int
1556 rtwn_tx(struct rtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni)
1557 {
1558 	struct ieee80211com *ic = &sc->sc_ic;
1559 	struct ieee80211vap *vap = ni->ni_vap;
1560 	struct ieee80211_frame *wh;
1561 	struct ieee80211_key *k = NULL;
1562 	struct rtwn_tx_ring *tx_ring;
1563 	struct rtwn_tx_data *data;
1564 	struct r92c_tx_desc *txd;
1565 	bus_dma_segment_t segs[1];
1566 	uint16_t qos;
1567 	uint8_t raid, type, tid, qid;
1568 	int nsegs, error;
1569 
1570 	wh = mtod(m, struct ieee80211_frame *);
1571 	type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
1572 
1573 	/* Encrypt the frame if need be. */
1574 	if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
1575 		k = ieee80211_crypto_encap(ni, m);
1576 		if (k == NULL) {
1577 			m_freem(m);
1578 			return (ENOBUFS);
1579 		}
1580 		/* 802.11 header may have moved. */
1581 		wh = mtod(m, struct ieee80211_frame *);
1582 	}
1583 
1584 	if (IEEE80211_QOS_HAS_SEQ(wh)) {
1585 		qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0];
1586 		tid = qos & IEEE80211_QOS_TID;
1587 	} else {
1588 		qos = 0;
1589 		tid = 0;
1590 	}
1591 
1592 	switch (type) {
1593 	case IEEE80211_FC0_TYPE_CTL:
1594 	case IEEE80211_FC0_TYPE_MGT:
1595 		qid = RTWN_VO_QUEUE;
1596 		break;
1597 	default:
1598 		qid = M_WME_GETAC(m);
1599 		break;
1600 	}
1601 
1602 	/* Grab a Tx buffer from the ring. */
1603 	tx_ring = &sc->tx_ring[qid];
1604 	data = &tx_ring->tx_data[tx_ring->cur];
1605 	if (data->m != NULL) {
1606 		m_freem(m);
1607 		return (ENOBUFS);
1608 	}
1609 
1610 	/* Fill Tx descriptor. */
1611 	txd = &tx_ring->desc[tx_ring->cur];
1612 	if (htole32(txd->txdw0) & R92C_RXDW0_OWN) {
1613 		m_freem(m);
1614 		return (ENOBUFS);
1615 	}
1616 	txd->txdw0 = htole32(
1617 	    SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) |
1618 	    SM(R92C_TXDW0_OFFSET, sizeof(*txd)) |
1619 	    R92C_TXDW0_FSG | R92C_TXDW0_LSG);
1620 	if (IEEE80211_IS_MULTICAST(wh->i_addr1))
1621 		txd->txdw0 |= htole32(R92C_TXDW0_BMCAST);
1622 
1623 	txd->txdw1 = 0;
1624 	txd->txdw4 = 0;
1625 	txd->txdw5 = 0;
1626 
1627 	/* XXX TODO: rate control; implement low-rate for EAPOL */
1628 	if (!IEEE80211_IS_MULTICAST(wh->i_addr1) &&
1629 	    type == IEEE80211_FC0_TYPE_DATA) {
1630 		if (ic->ic_curmode == IEEE80211_MODE_11B)
1631 			raid = R92C_RAID_11B;
1632 		else
1633 			raid = R92C_RAID_11BG;
1634 		txd->txdw1 |= htole32(
1635 		    SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) |
1636 		    SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) |
1637 		    SM(R92C_TXDW1_RAID, raid) |
1638 		    R92C_TXDW1_AGGBK);
1639 
1640 		if (ic->ic_flags & IEEE80211_F_USEPROT) {
1641 			if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) {
1642 				txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF |
1643 				    R92C_TXDW4_HWRTSEN);
1644 			} else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) {
1645 				txd->txdw4 |= htole32(R92C_TXDW4_RTSEN |
1646 				    R92C_TXDW4_HWRTSEN);
1647 			}
1648 		}
1649 
1650 		/* XXX TODO: implement rate control */
1651 
1652 		/* Send RTS at OFDM24. */
1653 		txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE,
1654 		    RTWN_RIDX_OFDM24));
1655 		txd->txdw5 |= htole32(SM(R92C_TXDW5_RTSRATE_FBLIMIT, 0xf));
1656 		/* Send data at OFDM54. */
1657 		txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE,
1658 		    RTWN_RIDX_OFDM54));
1659 		txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE_FBLIMIT, 0x1f));
1660 
1661 	} else {
1662 		txd->txdw1 |= htole32(
1663 		    SM(R92C_TXDW1_MACID, 0) |
1664 		    SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) |
1665 		    SM(R92C_TXDW1_RAID, R92C_RAID_11B));
1666 
1667 		/* Force CCK1. */
1668 		txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE);
1669 		txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, RTWN_RIDX_CCK1));
1670 	}
1671 	/* Set sequence number (already little endian). */
1672 	txd->txdseq = htole16(M_SEQNO_GET(m) % IEEE80211_SEQ_RANGE);
1673 
1674 	if (!qos) {
1675 		/* Use HW sequence numbering for non-QoS frames. */
1676 		txd->txdw4  |= htole32(R92C_TXDW4_HWSEQ);
1677 		txd->txdseq |= htole16(0x8000);
1678 	} else
1679 		txd->txdw4 |= htole32(R92C_TXDW4_QOS);
1680 
1681 	error = bus_dmamap_load_mbuf_sg(tx_ring->data_dmat, data->map, m, segs,
1682 	    &nsegs, BUS_DMA_NOWAIT);
1683 	if (error != 0 && error != EFBIG) {
1684 		device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", error);
1685 		m_freem(m);
1686 		return (error);
1687 	}
1688 	if (error != 0) {
1689 		struct mbuf *mnew;
1690 
1691 		mnew = m_defrag(m, M_NOWAIT);
1692 		if (mnew == NULL) {
1693 			device_printf(sc->sc_dev,
1694 			    "can't defragment mbuf\n");
1695 			m_freem(m);
1696 			return (ENOBUFS);
1697 		}
1698 		m = mnew;
1699 
1700 		error = bus_dmamap_load_mbuf_sg(tx_ring->data_dmat, data->map,
1701 		    m, segs, &nsegs, BUS_DMA_NOWAIT);
1702 		if (error != 0) {
1703 			device_printf(sc->sc_dev,
1704 			    "can't map mbuf (error %d)\n", error);
1705 			m_freem(m);
1706 			return (error);
1707 		}
1708 	}
1709 
1710 	txd->txbufaddr = htole32(segs[0].ds_addr);
1711 	txd->txbufsize = htole16(m->m_pkthdr.len);
1712 	bus_space_barrier(sc->sc_st, sc->sc_sh, 0, sc->sc_mapsize,
1713 	    BUS_SPACE_BARRIER_WRITE);
1714 	txd->txdw0 |= htole32(R92C_TXDW0_OWN);
1715 
1716 	bus_dmamap_sync(tx_ring->desc_dmat, tx_ring->desc_map,
1717 	    BUS_DMASYNC_POSTWRITE);
1718 	bus_dmamap_sync(tx_ring->data_dmat, data->map, BUS_DMASYNC_POSTWRITE);
1719 
1720 	data->m = m;
1721 	data->ni = ni;
1722 
1723 	if (ieee80211_radiotap_active_vap(vap)) {
1724 		struct rtwn_tx_radiotap_header *tap = &sc->sc_txtap;
1725 
1726 		tap->wt_flags = 0;
1727 		tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq);
1728 		tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags);
1729 
1730 		ieee80211_radiotap_tx(vap, m);
1731 	}
1732 
1733 	tx_ring->cur = (tx_ring->cur + 1) % RTWN_TX_LIST_COUNT;
1734 	tx_ring->queued++;
1735 
1736 	if (tx_ring->queued >= (RTWN_TX_LIST_COUNT - 1))
1737 		sc->qfullmsk |= (1 << qid);
1738 
1739 	/* Kick TX. */
1740 	rtwn_write_2(sc, R92C_PCIE_CTRL_REG, (1 << qid));
1741 	return (0);
1742 }
1743 
1744 static void
1745 rtwn_tx_done(struct rtwn_softc *sc, int qid)
1746 {
1747 	struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid];
1748 	struct rtwn_tx_data *tx_data;
1749 	struct r92c_tx_desc *tx_desc;
1750 	int i;
1751 
1752 	bus_dmamap_sync(tx_ring->desc_dmat, tx_ring->desc_map,
1753 	    BUS_DMASYNC_POSTREAD);
1754 
1755 	for (i = 0; i < RTWN_TX_LIST_COUNT; i++) {
1756 		tx_data = &tx_ring->tx_data[i];
1757 		if (tx_data->m == NULL)
1758 			continue;
1759 
1760 		tx_desc = &tx_ring->desc[i];
1761 		if (le32toh(tx_desc->txdw0) & R92C_TXDW0_OWN)
1762 			continue;
1763 
1764 		bus_dmamap_unload(tx_ring->desc_dmat, tx_ring->desc_map);
1765 
1766 		/*
1767 		 * XXX TODO: figure out whether the transmit succeeded or not.
1768 		 * .. and then notify rate control.
1769 		 */
1770 		ieee80211_tx_complete(tx_data->ni, tx_data->m, 0);
1771 		tx_data->ni = NULL;
1772 		tx_data->m = NULL;
1773 
1774 		sc->sc_tx_timer = 0;
1775 		tx_ring->queued--;
1776 	}
1777 
1778 	if (tx_ring->queued < (RTWN_TX_LIST_COUNT - 1))
1779 		sc->qfullmsk &= ~(1 << qid);
1780 	rtwn_start(sc);
1781 }
1782 
1783 static int
1784 rtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
1785     const struct ieee80211_bpf_params *params)
1786 {
1787 	struct ieee80211com *ic = ni->ni_ic;
1788 	struct rtwn_softc *sc = ic->ic_softc;
1789 
1790 	RTWN_LOCK(sc);
1791 
1792 	/* Prevent management frames from being sent if we're not ready. */
1793 	if (!(sc->sc_flags & RTWN_RUNNING)) {
1794 		RTWN_UNLOCK(sc);
1795 		m_freem(m);
1796 		return (ENETDOWN);
1797 	}
1798 
1799 	if (rtwn_tx(sc, m, ni) != 0) {
1800 		RTWN_UNLOCK(sc);
1801 		return (EIO);
1802 	}
1803 	sc->sc_tx_timer = 5;
1804 	RTWN_UNLOCK(sc);
1805 	return (0);
1806 }
1807 
1808 static int
1809 rtwn_transmit(struct ieee80211com *ic, struct mbuf *m)
1810 {
1811 	struct rtwn_softc *sc = ic->ic_softc;
1812 	int error;
1813 
1814 	RTWN_LOCK(sc);
1815 	if ((sc->sc_flags & RTWN_RUNNING) == 0) {
1816 		RTWN_UNLOCK(sc);
1817 		return (ENXIO);
1818 	}
1819 	error = mbufq_enqueue(&sc->sc_snd, m);
1820 	if (error) {
1821 		RTWN_UNLOCK(sc);
1822 		return (error);
1823 	}
1824 	rtwn_start(sc);
1825 	RTWN_UNLOCK(sc);
1826 	return (0);
1827 }
1828 
1829 static void
1830 rtwn_parent(struct ieee80211com *ic)
1831 {
1832 	struct rtwn_softc *sc = ic->ic_softc;
1833 	struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
1834 
1835 	if (ic->ic_nrunning > 0) {
1836 		if (rtwn_init(sc) == 0)
1837 			ieee80211_start_all(ic);
1838 		else
1839 			ieee80211_stop(vap);
1840 	} else
1841 		rtwn_stop(sc);
1842 }
1843 
1844 static void
1845 rtwn_start(struct rtwn_softc *sc)
1846 {
1847 	struct ieee80211_node *ni;
1848 	struct mbuf *m;
1849 
1850 	RTWN_LOCK_ASSERT(sc);
1851 
1852 	if ((sc->sc_flags & RTWN_RUNNING) == 0)
1853 		return;
1854 
1855 	while (sc->qfullmsk == 0 && (m = mbufq_dequeue(&sc->sc_snd)) != NULL) {
1856 		ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
1857 		if (rtwn_tx(sc, m, ni) != 0) {
1858 			if_inc_counter(ni->ni_vap->iv_ifp,
1859 			    IFCOUNTER_OERRORS, 1);
1860 			ieee80211_free_node(ni);
1861 			continue;
1862 		}
1863 		sc->sc_tx_timer = 5;
1864 	}
1865 }
1866 
1867 static void
1868 rtwn_watchdog(void *arg)
1869 {
1870 	struct rtwn_softc *sc = arg;
1871 	struct ieee80211com *ic = &sc->sc_ic;
1872 
1873 	RTWN_LOCK_ASSERT(sc);
1874 
1875 	KASSERT(sc->sc_flags & RTWN_RUNNING, ("not running"));
1876 
1877 	if (sc->sc_tx_timer != 0 && --sc->sc_tx_timer == 0) {
1878 		ic_printf(ic, "device timeout\n");
1879 		ieee80211_restart_all(ic);
1880 		return;
1881 	}
1882 	callout_reset(&sc->watchdog_to, hz, rtwn_watchdog, sc);
1883 }
1884 
1885 static int
1886 rtwn_power_on(struct rtwn_softc *sc)
1887 {
1888 	uint32_t reg;
1889 	int ntries;
1890 
1891 	/* Wait for autoload done bit. */
1892 	for (ntries = 0; ntries < 1000; ntries++) {
1893 		if (rtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN)
1894 			break;
1895 		DELAY(5);
1896 	}
1897 	if (ntries == 1000) {
1898 		device_printf(sc->sc_dev,
1899 		    "timeout waiting for chip autoload\n");
1900 		return (ETIMEDOUT);
1901 	}
1902 
1903 	/* Unlock ISO/CLK/Power control register. */
1904 	rtwn_write_1(sc, R92C_RSV_CTRL, 0);
1905 
1906 	/* TODO: check if we need this for 8188CE */
1907 	if (sc->board_type != R92C_BOARD_TYPE_DONGLE) {
1908 		/* bt coex */
1909 		reg = rtwn_read_4(sc, R92C_APS_FSMCO);
1910 		reg |= (R92C_APS_FSMCO_SOP_ABG |
1911 			R92C_APS_FSMCO_SOP_AMB |
1912 			R92C_APS_FSMCO_XOP_BTCK);
1913 		rtwn_write_4(sc, R92C_APS_FSMCO, reg);
1914 	}
1915 
1916 	/* Move SPS into PWM mode. */
1917 	rtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b);
1918 
1919 	/* Set low byte to 0x0f, leave others unchanged. */
1920 	rtwn_write_4(sc, R92C_AFE_XTAL_CTRL,
1921 	    (rtwn_read_4(sc, R92C_AFE_XTAL_CTRL) & 0xffffff00) | 0x0f);
1922 
1923 	/* TODO: check if we need this for 8188CE */
1924 	if (sc->board_type != R92C_BOARD_TYPE_DONGLE) {
1925 		/* bt coex */
1926 		reg = rtwn_read_4(sc, R92C_AFE_XTAL_CTRL);
1927 		reg &= (~0x00024800); /* XXX magic from linux */
1928 		rtwn_write_4(sc, R92C_AFE_XTAL_CTRL, reg);
1929 	}
1930 
1931 	rtwn_write_2(sc, R92C_SYS_ISO_CTRL,
1932 	  (rtwn_read_2(sc, R92C_SYS_ISO_CTRL) & 0xff) |
1933 	  R92C_SYS_ISO_CTRL_PWC_EV12V | R92C_SYS_ISO_CTRL_DIOR);
1934 	DELAY(200);
1935 
1936 	/* TODO: linux does additional btcoex stuff here */
1937 
1938 	/* Auto enable WLAN. */
1939 	rtwn_write_2(sc, R92C_APS_FSMCO,
1940 	    rtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC);
1941 	for (ntries = 0; ntries < 1000; ntries++) {
1942 		if (!(rtwn_read_2(sc, R92C_APS_FSMCO) &
1943 		    R92C_APS_FSMCO_APFM_ONMAC))
1944 			break;
1945 		DELAY(5);
1946 	}
1947 	if (ntries == 1000) {
1948 		device_printf(sc->sc_dev, "timeout waiting for MAC auto ON\n");
1949 		return (ETIMEDOUT);
1950 	}
1951 
1952 	/* Enable radio, GPIO and LED functions. */
1953 	rtwn_write_2(sc, R92C_APS_FSMCO,
1954 	    R92C_APS_FSMCO_AFSM_PCIE |
1955 	    R92C_APS_FSMCO_PDN_EN |
1956 	    R92C_APS_FSMCO_PFM_ALDN);
1957 	/* Release RF digital isolation. */
1958 	rtwn_write_2(sc, R92C_SYS_ISO_CTRL,
1959 	    rtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR);
1960 
1961 	if (sc->chip & RTWN_CHIP_92C)
1962 		rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 3, 0x77);
1963 	else
1964 		rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 3, 0x22);
1965 
1966 	rtwn_write_4(sc, R92C_INT_MIG, 0);
1967 
1968 	if (sc->board_type != R92C_BOARD_TYPE_DONGLE) {
1969 		/* bt coex */
1970 		reg = rtwn_read_4(sc, R92C_AFE_XTAL_CTRL + 2);
1971 		reg &= 0xfd; /* XXX magic from linux */
1972 		rtwn_write_4(sc, R92C_AFE_XTAL_CTRL + 2, reg);
1973 	}
1974 
1975 	rtwn_write_1(sc, R92C_GPIO_MUXCFG,
1976 	    rtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_RFKILL);
1977 
1978 	reg = rtwn_read_1(sc, R92C_GPIO_IO_SEL);
1979 	if (!(reg & R92C_GPIO_IO_SEL_RFKILL)) {
1980 		device_printf(sc->sc_dev,
1981 		    "radio is disabled by hardware switch\n");
1982 		return (EPERM);
1983 	}
1984 
1985 	/* Initialize MAC. */
1986 	reg = rtwn_read_1(sc, R92C_APSD_CTRL);
1987 	rtwn_write_1(sc, R92C_APSD_CTRL,
1988 	    rtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF);
1989 	for (ntries = 0; ntries < 200; ntries++) {
1990 		if (!(rtwn_read_1(sc, R92C_APSD_CTRL) &
1991 		    R92C_APSD_CTRL_OFF_STATUS))
1992 			break;
1993 		DELAY(500);
1994 	}
1995 	if (ntries == 200) {
1996 		device_printf(sc->sc_dev,
1997 		    "timeout waiting for MAC initialization\n");
1998 		return (ETIMEDOUT);
1999 	}
2000 
2001 	/* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
2002 	reg = rtwn_read_2(sc, R92C_CR);
2003 	reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |
2004 	    R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN |
2005 	    R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN |
2006 	    R92C_CR_ENSEC;
2007 	rtwn_write_2(sc, R92C_CR, reg);
2008 
2009 	rtwn_write_1(sc, 0xfe10, 0x19);
2010 
2011 	return (0);
2012 }
2013 
2014 static int
2015 rtwn_llt_init(struct rtwn_softc *sc)
2016 {
2017 	int i, error;
2018 
2019 	/* Reserve pages [0; R92C_TX_PAGE_COUNT]. */
2020 	for (i = 0; i < R92C_TX_PAGE_COUNT; i++) {
2021 		if ((error = rtwn_llt_write(sc, i, i + 1)) != 0)
2022 			return (error);
2023 	}
2024 	/* NB: 0xff indicates end-of-list. */
2025 	if ((error = rtwn_llt_write(sc, i, 0xff)) != 0)
2026 		return (error);
2027 	/*
2028 	 * Use pages [R92C_TX_PAGE_COUNT + 1; R92C_TXPKTBUF_COUNT - 1]
2029 	 * as ring buffer.
2030 	 */
2031 	for (++i; i < R92C_TXPKTBUF_COUNT - 1; i++) {
2032 		if ((error = rtwn_llt_write(sc, i, i + 1)) != 0)
2033 			return (error);
2034 	}
2035 	/* Make the last page point to the beginning of the ring buffer. */
2036 	error = rtwn_llt_write(sc, i, R92C_TX_PAGE_COUNT + 1);
2037 	return (error);
2038 }
2039 
2040 static void
2041 rtwn_fw_reset(struct rtwn_softc *sc)
2042 {
2043 	uint16_t reg;
2044 	int ntries;
2045 
2046 	/* Tell 8051 to reset itself. */
2047 	rtwn_write_1(sc, R92C_HMETFR + 3, 0x20);
2048 
2049 	/* Wait until 8051 resets by itself. */
2050 	for (ntries = 0; ntries < 100; ntries++) {
2051 		reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN);
2052 		if (!(reg & R92C_SYS_FUNC_EN_CPUEN))
2053 			goto sleep;
2054 		DELAY(50);
2055 	}
2056 	/* Force 8051 reset. */
2057 	rtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN);
2058 sleep:
2059 	/*
2060 	 * We must sleep for one second to let the firmware settle.
2061 	 * Accessing registers too early will hang the whole system.
2062 	 */
2063 	if (msleep(&reg, &sc->sc_mtx, 0, "rtwnrst", hz)) {
2064 		device_printf(sc->sc_dev, "timeout waiting for firmware "
2065 		    "initialization to complete\n");
2066 	}
2067 }
2068 
2069 static void
2070 rtwn_fw_loadpage(struct rtwn_softc *sc, int page, const uint8_t *buf, int len)
2071 {
2072 	uint32_t reg;
2073 	int off, mlen, i;
2074 
2075 	reg = rtwn_read_4(sc, R92C_MCUFWDL);
2076 	reg = RW(reg, R92C_MCUFWDL_PAGE, page);
2077 	rtwn_write_4(sc, R92C_MCUFWDL, reg);
2078 
2079 	DELAY(5);
2080 
2081 	off = R92C_FW_START_ADDR;
2082 	while (len > 0) {
2083 		if (len > 196)
2084 			mlen = 196;
2085 		else if (len > 4)
2086 			mlen = 4;
2087 		else
2088 			mlen = 1;
2089 		for (i = 0; i < mlen; i++)
2090 			rtwn_write_1(sc, off++, buf[i]);
2091 		buf += mlen;
2092 		len -= mlen;
2093 	}
2094 }
2095 
2096 static int
2097 rtwn_load_firmware(struct rtwn_softc *sc)
2098 {
2099 	const struct firmware *fw;
2100 	const struct r92c_fw_hdr *hdr;
2101 	const char *name;
2102 	const u_char *ptr;
2103 	size_t len;
2104 	uint32_t reg;
2105 	int mlen, ntries, page, error = 0;
2106 
2107 	/* Read firmware image from the filesystem. */
2108 	if ((sc->chip & (RTWN_CHIP_UMC_A_CUT | RTWN_CHIP_92C)) ==
2109 	    RTWN_CHIP_UMC_A_CUT)
2110 		name = "rtwn-rtl8192cfwU";
2111 	else
2112 		name = "rtwn-rtl8192cfwU_B";
2113 	RTWN_UNLOCK(sc);
2114 	fw = firmware_get(name);
2115 	RTWN_LOCK(sc);
2116 	if (fw == NULL) {
2117 		device_printf(sc->sc_dev,
2118 		    "could not read firmware %s\n", name);
2119 		return (ENOENT);
2120 	}
2121 	len = fw->datasize;
2122 	if (len < sizeof(*hdr)) {
2123 		device_printf(sc->sc_dev, "firmware too short\n");
2124 		error = EINVAL;
2125 		goto fail;
2126 	}
2127 	ptr = fw->data;
2128 	hdr = (const struct r92c_fw_hdr *)ptr;
2129 	/* Check if there is a valid FW header and skip it. */
2130 	if ((le16toh(hdr->signature) >> 4) == 0x88c ||
2131 	    (le16toh(hdr->signature) >> 4) == 0x92c) {
2132 		DPRINTF(("FW V%d.%d %02d-%02d %02d:%02d\n",
2133 		    le16toh(hdr->version), le16toh(hdr->subversion),
2134 		    hdr->month, hdr->date, hdr->hour, hdr->minute));
2135 		ptr += sizeof(*hdr);
2136 		len -= sizeof(*hdr);
2137 	}
2138 
2139 	if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL)
2140 		rtwn_fw_reset(sc);
2141 
2142 	/* Enable FW download. */
2143 	rtwn_write_2(sc, R92C_SYS_FUNC_EN,
2144 	    rtwn_read_2(sc, R92C_SYS_FUNC_EN) |
2145 	    R92C_SYS_FUNC_EN_CPUEN);
2146 	rtwn_write_1(sc, R92C_MCUFWDL,
2147 	    rtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN);
2148 	rtwn_write_1(sc, R92C_MCUFWDL + 2,
2149 	    rtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08);
2150 
2151 	/* Reset the FWDL checksum. */
2152 	rtwn_write_1(sc, R92C_MCUFWDL,
2153 	    rtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT);
2154 
2155 	for (page = 0; len > 0; page++) {
2156 		mlen = MIN(len, R92C_FW_PAGE_SIZE);
2157 		rtwn_fw_loadpage(sc, page, ptr, mlen);
2158 		ptr += mlen;
2159 		len -= mlen;
2160 	}
2161 
2162 	/* Disable FW download. */
2163 	rtwn_write_1(sc, R92C_MCUFWDL,
2164 	    rtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN);
2165 	rtwn_write_1(sc, R92C_MCUFWDL + 1, 0);
2166 
2167 	/* Wait for checksum report. */
2168 	for (ntries = 0; ntries < 1000; ntries++) {
2169 		if (rtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT)
2170 			break;
2171 		DELAY(5);
2172 	}
2173 	if (ntries == 1000) {
2174 		device_printf(sc->sc_dev,
2175 		    "timeout waiting for checksum report\n");
2176 		error = ETIMEDOUT;
2177 		goto fail;
2178 	}
2179 
2180 	reg = rtwn_read_4(sc, R92C_MCUFWDL);
2181 	reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY;
2182 	rtwn_write_4(sc, R92C_MCUFWDL, reg);
2183 	/* Wait for firmware readiness. */
2184 	for (ntries = 0; ntries < 2000; ntries++) {
2185 		if (rtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY)
2186 			break;
2187 		DELAY(50);
2188 	}
2189 	if (ntries == 1000) {
2190 		device_printf(sc->sc_dev,
2191 		    "timeout waiting for firmware readiness\n");
2192 		error = ETIMEDOUT;
2193 		goto fail;
2194 	}
2195 fail:
2196 	firmware_put(fw, FIRMWARE_UNLOAD);
2197 	return (error);
2198 }
2199 
2200 static int
2201 rtwn_dma_init(struct rtwn_softc *sc)
2202 {
2203 	uint32_t reg;
2204 	int error;
2205 
2206 	/* Initialize LLT table. */
2207 	error = rtwn_llt_init(sc);
2208 	if (error != 0)
2209 		return error;
2210 
2211 	/* Set number of pages for normal priority queue. */
2212 	rtwn_write_2(sc, R92C_RQPN_NPQ, 0);
2213 	rtwn_write_4(sc, R92C_RQPN,
2214 	    /* Set number of pages for public queue. */
2215 	    SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) |
2216 	    /* Set number of pages for high priority queue. */
2217 	    SM(R92C_RQPN_HPQ, R92C_HPQ_NPAGES) |
2218 	    /* Set number of pages for low priority queue. */
2219 	    SM(R92C_RQPN_LPQ, R92C_LPQ_NPAGES) |
2220 	    /* Load values. */
2221 	    R92C_RQPN_LD);
2222 
2223 	rtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY);
2224 	rtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY);
2225 	rtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY);
2226 	rtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY);
2227 	rtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY);
2228 
2229 	reg = rtwn_read_2(sc, R92C_TRXDMA_CTRL);
2230 	reg &= ~R92C_TRXDMA_CTRL_QMAP_M;
2231 	reg |= 0xF771;
2232 	rtwn_write_2(sc, R92C_TRXDMA_CTRL, reg);
2233 
2234 	rtwn_write_4(sc, R92C_TCR, R92C_TCR_CFENDFORM | (1 << 12) | (1 << 13));
2235 
2236 	/* Configure Tx DMA. */
2237 	rtwn_write_4(sc, R92C_BKQ_DESA, sc->tx_ring[RTWN_BK_QUEUE].paddr);
2238 	rtwn_write_4(sc, R92C_BEQ_DESA, sc->tx_ring[RTWN_BE_QUEUE].paddr);
2239 	rtwn_write_4(sc, R92C_VIQ_DESA, sc->tx_ring[RTWN_VI_QUEUE].paddr);
2240 	rtwn_write_4(sc, R92C_VOQ_DESA, sc->tx_ring[RTWN_VO_QUEUE].paddr);
2241 	rtwn_write_4(sc, R92C_BCNQ_DESA, sc->tx_ring[RTWN_BEACON_QUEUE].paddr);
2242 	rtwn_write_4(sc, R92C_MGQ_DESA, sc->tx_ring[RTWN_MGNT_QUEUE].paddr);
2243 	rtwn_write_4(sc, R92C_HQ_DESA, sc->tx_ring[RTWN_HIGH_QUEUE].paddr);
2244 
2245 	/* Configure Rx DMA. */
2246 	rtwn_write_4(sc, R92C_RX_DESA, sc->rx_ring.paddr);
2247 
2248 	/* Set Tx/Rx transfer page boundary. */
2249 	rtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff);
2250 
2251 	/* Set Tx/Rx transfer page size. */
2252 	rtwn_write_1(sc, R92C_PBP,
2253 	    SM(R92C_PBP_PSRX, R92C_PBP_128) |
2254 	    SM(R92C_PBP_PSTX, R92C_PBP_128));
2255 	return (0);
2256 }
2257 
2258 static void
2259 rtwn_mac_init(struct rtwn_softc *sc)
2260 {
2261 	int i;
2262 
2263 	/* Write MAC initialization values. */
2264 	for (i = 0; i < nitems(rtl8192ce_mac); i++)
2265 		rtwn_write_1(sc, rtl8192ce_mac[i].reg, rtl8192ce_mac[i].val);
2266 }
2267 
2268 static void
2269 rtwn_bb_init(struct rtwn_softc *sc)
2270 {
2271 	const struct rtwn_bb_prog *prog;
2272 	uint32_t reg;
2273 	int i;
2274 
2275 	/* Enable BB and RF. */
2276 	rtwn_write_2(sc, R92C_SYS_FUNC_EN,
2277 	    rtwn_read_2(sc, R92C_SYS_FUNC_EN) |
2278 	    R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST |
2279 	    R92C_SYS_FUNC_EN_DIO_RF);
2280 
2281 	rtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83);
2282 
2283 	rtwn_write_1(sc, R92C_RF_CTRL,
2284 	    R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB);
2285 
2286 	rtwn_write_1(sc, R92C_SYS_FUNC_EN,
2287 	    R92C_SYS_FUNC_EN_DIO_PCIE | R92C_SYS_FUNC_EN_PCIEA |
2288 	    R92C_SYS_FUNC_EN_PPLL | R92C_SYS_FUNC_EN_BB_GLB_RST |
2289 	    R92C_SYS_FUNC_EN_BBRSTB);
2290 
2291 	rtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80);
2292 
2293 	rtwn_write_4(sc, R92C_LEDCFG0,
2294 	    rtwn_read_4(sc, R92C_LEDCFG0) | 0x00800000);
2295 
2296 	/* Select BB programming. */
2297 	prog = (sc->chip & RTWN_CHIP_92C) ?
2298 	    &rtl8192ce_bb_prog_2t : &rtl8192ce_bb_prog_1t;
2299 
2300 	/* Write BB initialization values. */
2301 	for (i = 0; i < prog->count; i++) {
2302 		rtwn_bb_write(sc, prog->regs[i], prog->vals[i]);
2303 		DELAY(1);
2304 	}
2305 
2306 	if (sc->chip & RTWN_CHIP_92C_1T2R) {
2307 		/* 8192C 1T only configuration. */
2308 		reg = rtwn_bb_read(sc, R92C_FPGA0_TXINFO);
2309 		reg = (reg & ~0x00000003) | 0x2;
2310 		rtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg);
2311 
2312 		reg = rtwn_bb_read(sc, R92C_FPGA1_TXINFO);
2313 		reg = (reg & ~0x00300033) | 0x00200022;
2314 		rtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg);
2315 
2316 		reg = rtwn_bb_read(sc, R92C_CCK0_AFESETTING);
2317 		reg = (reg & ~0xff000000) | 0x45 << 24;
2318 		rtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg);
2319 
2320 		reg = rtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA);
2321 		reg = (reg & ~0x000000ff) | 0x23;
2322 		rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg);
2323 
2324 		reg = rtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1);
2325 		reg = (reg & ~0x00000030) | 1 << 4;
2326 		rtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg);
2327 
2328 		reg = rtwn_bb_read(sc, 0xe74);
2329 		reg = (reg & ~0x0c000000) | 2 << 26;
2330 		rtwn_bb_write(sc, 0xe74, reg);
2331 		reg = rtwn_bb_read(sc, 0xe78);
2332 		reg = (reg & ~0x0c000000) | 2 << 26;
2333 		rtwn_bb_write(sc, 0xe78, reg);
2334 		reg = rtwn_bb_read(sc, 0xe7c);
2335 		reg = (reg & ~0x0c000000) | 2 << 26;
2336 		rtwn_bb_write(sc, 0xe7c, reg);
2337 		reg = rtwn_bb_read(sc, 0xe80);
2338 		reg = (reg & ~0x0c000000) | 2 << 26;
2339 		rtwn_bb_write(sc, 0xe80, reg);
2340 		reg = rtwn_bb_read(sc, 0xe88);
2341 		reg = (reg & ~0x0c000000) | 2 << 26;
2342 		rtwn_bb_write(sc, 0xe88, reg);
2343 	}
2344 
2345 	/* Write AGC values. */
2346 	for (i = 0; i < prog->agccount; i++) {
2347 		rtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE,
2348 		    prog->agcvals[i]);
2349 		DELAY(1);
2350 	}
2351 
2352 	if (rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) &
2353 	    R92C_HSSI_PARAM2_CCK_HIPWR)
2354 		sc->sc_flags |= RTWN_FLAG_CCK_HIPWR;
2355 }
2356 
2357 static void
2358 rtwn_rf_init(struct rtwn_softc *sc)
2359 {
2360 	const struct rtwn_rf_prog *prog;
2361 	uint32_t reg, type;
2362 	int i, j, idx, off;
2363 
2364 	/* Select RF programming based on board type. */
2365 	if (!(sc->chip & RTWN_CHIP_92C)) {
2366 		if (sc->board_type == R92C_BOARD_TYPE_MINICARD)
2367 			prog = rtl8188ce_rf_prog;
2368 		else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA)
2369 			prog = rtl8188ru_rf_prog;
2370 		else
2371 			prog = rtl8188cu_rf_prog;
2372 	} else
2373 		prog = rtl8192ce_rf_prog;
2374 
2375 	for (i = 0; i < sc->nrxchains; i++) {
2376 		/* Save RF_ENV control type. */
2377 		idx = i / 2;
2378 		off = (i % 2) * 16;
2379 		reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx));
2380 		type = (reg >> off) & 0x10;
2381 
2382 		/* Set RF_ENV enable. */
2383 		reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i));
2384 		reg |= 0x100000;
2385 		rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg);
2386 		DELAY(1);
2387 		/* Set RF_ENV output high. */
2388 		reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i));
2389 		reg |= 0x10;
2390 		rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg);
2391 		DELAY(1);
2392 		/* Set address and data lengths of RF registers. */
2393 		reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i));
2394 		reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH;
2395 		rtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg);
2396 		DELAY(1);
2397 		reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i));
2398 		reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH;
2399 		rtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg);
2400 		DELAY(1);
2401 
2402 		/* Write RF initialization values for this chain. */
2403 		for (j = 0; j < prog[i].count; j++) {
2404 			if (prog[i].regs[j] >= 0xf9 &&
2405 			    prog[i].regs[j] <= 0xfe) {
2406 				/*
2407 				 * These are fake RF registers offsets that
2408 				 * indicate a delay is required.
2409 				 */
2410 				DELAY(50);
2411 				continue;
2412 			}
2413 			rtwn_rf_write(sc, i, prog[i].regs[j],
2414 			    prog[i].vals[j]);
2415 			DELAY(1);
2416 		}
2417 
2418 		/* Restore RF_ENV control type. */
2419 		reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx));
2420 		reg &= ~(0x10 << off) | (type << off);
2421 		rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg);
2422 
2423 		/* Cache RF register CHNLBW. */
2424 		sc->rf_chnlbw[i] = rtwn_rf_read(sc, i, R92C_RF_CHNLBW);
2425 	}
2426 
2427 	if ((sc->chip & (RTWN_CHIP_UMC_A_CUT | RTWN_CHIP_92C)) ==
2428 	    RTWN_CHIP_UMC_A_CUT) {
2429 		rtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255);
2430 		rtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00);
2431 	}
2432 }
2433 
2434 static void
2435 rtwn_cam_init(struct rtwn_softc *sc)
2436 {
2437 	/* Invalidate all CAM entries. */
2438 	rtwn_write_4(sc, R92C_CAMCMD,
2439 	    R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR);
2440 }
2441 
2442 static void
2443 rtwn_pa_bias_init(struct rtwn_softc *sc)
2444 {
2445 	uint8_t reg;
2446 	int i;
2447 
2448 	for (i = 0; i < sc->nrxchains; i++) {
2449 		if (sc->pa_setting & (1 << i))
2450 			continue;
2451 		rtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406);
2452 		rtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406);
2453 		rtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406);
2454 		rtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406);
2455 	}
2456 	if (!(sc->pa_setting & 0x10)) {
2457 		reg = rtwn_read_1(sc, 0x16);
2458 		reg = (reg & ~0xf0) | 0x90;
2459 		rtwn_write_1(sc, 0x16, reg);
2460 	}
2461 }
2462 
2463 static void
2464 rtwn_rxfilter_init(struct rtwn_softc *sc)
2465 {
2466 	/* Initialize Rx filter. */
2467 	/* TODO: use better filter for monitor mode. */
2468 	rtwn_write_4(sc, R92C_RCR,
2469 	    R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB |
2470 	    R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL |
2471 	    R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS);
2472 	/* Accept all multicast frames. */
2473 	rtwn_write_4(sc, R92C_MAR + 0, 0xffffffff);
2474 	rtwn_write_4(sc, R92C_MAR + 4, 0xffffffff);
2475 	/* Accept all management frames. */
2476 	rtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff);
2477 	/* Reject all control frames. */
2478 	rtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000);
2479 	/* Accept all data frames. */
2480 	rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff);
2481 }
2482 
2483 static void
2484 rtwn_edca_init(struct rtwn_softc *sc)
2485 {
2486 
2487 	rtwn_write_2(sc, R92C_SPEC_SIFS, 0x1010);
2488 	rtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x1010);
2489 	rtwn_write_2(sc, R92C_SIFS_CCK, 0x1010);
2490 	rtwn_write_2(sc, R92C_SIFS_OFDM, 0x0e0e);
2491 	rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b);
2492 	rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f);
2493 	rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4322);
2494 	rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3222);
2495 }
2496 
2497 static void
2498 rtwn_write_txpower(struct rtwn_softc *sc, int chain,
2499     uint16_t power[RTWN_RIDX_COUNT])
2500 {
2501 	uint32_t reg;
2502 
2503 	/* Write per-CCK rate Tx power. */
2504 	if (chain == 0) {
2505 		reg = rtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32);
2506 		reg = RW(reg, R92C_TXAGC_A_CCK1,  power[0]);
2507 		rtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg);
2508 		reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);
2509 		reg = RW(reg, R92C_TXAGC_A_CCK2,  power[1]);
2510 		reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]);
2511 		reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]);
2512 		rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);
2513 	} else {
2514 		reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32);
2515 		reg = RW(reg, R92C_TXAGC_B_CCK1,  power[0]);
2516 		reg = RW(reg, R92C_TXAGC_B_CCK2,  power[1]);
2517 		reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]);
2518 		rtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg);
2519 		reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);
2520 		reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]);
2521 		rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);
2522 	}
2523 	/* Write per-OFDM rate Tx power. */
2524 	rtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain),
2525 	    SM(R92C_TXAGC_RATE06, power[ 4]) |
2526 	    SM(R92C_TXAGC_RATE09, power[ 5]) |
2527 	    SM(R92C_TXAGC_RATE12, power[ 6]) |
2528 	    SM(R92C_TXAGC_RATE18, power[ 7]));
2529 	rtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain),
2530 	    SM(R92C_TXAGC_RATE24, power[ 8]) |
2531 	    SM(R92C_TXAGC_RATE36, power[ 9]) |
2532 	    SM(R92C_TXAGC_RATE48, power[10]) |
2533 	    SM(R92C_TXAGC_RATE54, power[11]));
2534 	/* Write per-MCS Tx power. */
2535 	rtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain),
2536 	    SM(R92C_TXAGC_MCS00,  power[12]) |
2537 	    SM(R92C_TXAGC_MCS01,  power[13]) |
2538 	    SM(R92C_TXAGC_MCS02,  power[14]) |
2539 	    SM(R92C_TXAGC_MCS03,  power[15]));
2540 	rtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain),
2541 	    SM(R92C_TXAGC_MCS04,  power[16]) |
2542 	    SM(R92C_TXAGC_MCS05,  power[17]) |
2543 	    SM(R92C_TXAGC_MCS06,  power[18]) |
2544 	    SM(R92C_TXAGC_MCS07,  power[19]));
2545 	rtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain),
2546 	    SM(R92C_TXAGC_MCS08,  power[20]) |
2547 	    SM(R92C_TXAGC_MCS09,  power[21]) |
2548 	    SM(R92C_TXAGC_MCS10,  power[22]) |
2549 	    SM(R92C_TXAGC_MCS11,  power[23]));
2550 	rtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain),
2551 	    SM(R92C_TXAGC_MCS12,  power[24]) |
2552 	    SM(R92C_TXAGC_MCS13,  power[25]) |
2553 	    SM(R92C_TXAGC_MCS14,  power[26]) |
2554 	    SM(R92C_TXAGC_MCS15,  power[27]));
2555 }
2556 
2557 static void
2558 rtwn_get_txpower(struct rtwn_softc *sc, int chain,
2559     struct ieee80211_channel *c, struct ieee80211_channel *extc,
2560     uint16_t power[RTWN_RIDX_COUNT])
2561 {
2562 	struct ieee80211com *ic = &sc->sc_ic;
2563 	struct r92c_rom *rom = &sc->rom;
2564 	uint16_t cckpow, ofdmpow, htpow, diff, max;
2565 	const struct rtwn_txpwr *base;
2566 	int ridx, chan, group;
2567 
2568 	/* Determine channel group. */
2569 	chan = ieee80211_chan2ieee(ic, c);	/* XXX center freq! */
2570 	if (chan <= 3)
2571 		group = 0;
2572 	else if (chan <= 9)
2573 		group = 1;
2574 	else
2575 		group = 2;
2576 
2577 	/* Get original Tx power based on board type and RF chain. */
2578 	if (!(sc->chip & RTWN_CHIP_92C)) {
2579 		if (sc->board_type == R92C_BOARD_TYPE_HIGHPA)
2580 			base = &rtl8188ru_txagc[chain];
2581 		else
2582 			base = &rtl8192cu_txagc[chain];
2583 	} else
2584 		base = &rtl8192cu_txagc[chain];
2585 
2586 	memset(power, 0, RTWN_RIDX_COUNT * sizeof(power[0]));
2587 	if (sc->regulatory == 0) {
2588 		for (ridx = RTWN_RIDX_CCK1; ridx <= RTWN_RIDX_CCK11; ridx++)
2589 			power[ridx] = base->pwr[0][ridx];
2590 	}
2591 	for (ridx = RTWN_RIDX_OFDM6; ridx < RTWN_RIDX_COUNT; ridx++) {
2592 		if (sc->regulatory == 3) {
2593 			power[ridx] = base->pwr[0][ridx];
2594 			/* Apply vendor limits. */
2595 			if (extc != NULL)
2596 				max = rom->ht40_max_pwr[group];
2597 			else
2598 				max = rom->ht20_max_pwr[group];
2599 			max = (max >> (chain * 4)) & 0xf;
2600 			if (power[ridx] > max)
2601 				power[ridx] = max;
2602 		} else if (sc->regulatory == 1) {
2603 			if (extc == NULL)
2604 				power[ridx] = base->pwr[group][ridx];
2605 		} else if (sc->regulatory != 2)
2606 			power[ridx] = base->pwr[0][ridx];
2607 	}
2608 
2609 	/* Compute per-CCK rate Tx power. */
2610 	cckpow = rom->cck_tx_pwr[chain][group];
2611 	for (ridx = RTWN_RIDX_CCK1; ridx <= RTWN_RIDX_CCK11; ridx++) {
2612 		power[ridx] += cckpow;
2613 		if (power[ridx] > R92C_MAX_TX_PWR)
2614 			power[ridx] = R92C_MAX_TX_PWR;
2615 	}
2616 
2617 	htpow = rom->ht40_1s_tx_pwr[chain][group];
2618 	if (sc->ntxchains > 1) {
2619 		/* Apply reduction for 2 spatial streams. */
2620 		diff = rom->ht40_2s_tx_pwr_diff[group];
2621 		diff = (diff >> (chain * 4)) & 0xf;
2622 		htpow = (htpow > diff) ? htpow - diff : 0;
2623 	}
2624 
2625 	/* Compute per-OFDM rate Tx power. */
2626 	diff = rom->ofdm_tx_pwr_diff[group];
2627 	diff = (diff >> (chain * 4)) & 0xf;
2628 	ofdmpow = htpow + diff;	/* HT->OFDM correction. */
2629 	for (ridx = RTWN_RIDX_OFDM6; ridx <= RTWN_RIDX_OFDM54; ridx++) {
2630 		power[ridx] += ofdmpow;
2631 		if (power[ridx] > R92C_MAX_TX_PWR)
2632 			power[ridx] = R92C_MAX_TX_PWR;
2633 	}
2634 
2635 	/* Compute per-MCS Tx power. */
2636 	if (extc == NULL) {
2637 		diff = rom->ht20_tx_pwr_diff[group];
2638 		diff = (diff >> (chain * 4)) & 0xf;
2639 		htpow += diff;	/* HT40->HT20 correction. */
2640 	}
2641 	for (ridx = RTWN_RIDX_MCS0; ridx <= RTWN_RIDX_MCS15; ridx++) {
2642 		power[ridx] += htpow;
2643 		if (power[ridx] > R92C_MAX_TX_PWR)
2644 			power[ridx] = R92C_MAX_TX_PWR;
2645 	}
2646 #ifdef RTWN_DEBUG
2647 	if (sc->sc_debug >= 4) {
2648 		/* Dump per-rate Tx power values. */
2649 		printf("Tx power for chain %d:\n", chain);
2650 		for (ridx = RTWN_RIDX_CCK1; ridx < RTWN_RIDX_COUNT; ridx++)
2651 			printf("Rate %d = %u\n", ridx, power[ridx]);
2652 	}
2653 #endif
2654 }
2655 
2656 static void
2657 rtwn_set_txpower(struct rtwn_softc *sc, struct ieee80211_channel *c,
2658     struct ieee80211_channel *extc)
2659 {
2660 	uint16_t power[RTWN_RIDX_COUNT];
2661 	int i;
2662 
2663 	for (i = 0; i < sc->ntxchains; i++) {
2664 		/* Compute per-rate Tx power values. */
2665 		rtwn_get_txpower(sc, i, c, extc, power);
2666 		/* Write per-rate Tx power values to hardware. */
2667 		rtwn_write_txpower(sc, i, power);
2668 	}
2669 }
2670 
2671 static void
2672 rtwn_set_rx_bssid_all(struct rtwn_softc *sc, int enable)
2673 {
2674 	uint32_t reg;
2675 
2676 	reg = rtwn_read_4(sc, R92C_RCR);
2677 	if (enable)
2678 		reg &= ~R92C_RCR_CBSSID_BCN;
2679 	else
2680 		reg |= R92C_RCR_CBSSID_BCN;
2681 	rtwn_write_4(sc, R92C_RCR, reg);
2682 }
2683 
2684 static void
2685 rtwn_set_gain(struct rtwn_softc *sc, uint8_t gain)
2686 {
2687 	uint32_t reg;
2688 
2689 	reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0));
2690 	reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain);
2691 	rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg);
2692 
2693 	reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1));
2694 	reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, gain);
2695 	rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg);
2696 }
2697 
2698 static void
2699 rtwn_scan_start(struct ieee80211com *ic)
2700 {
2701 	struct rtwn_softc *sc = ic->ic_softc;
2702 
2703 	RTWN_LOCK(sc);
2704 	/* Receive beacons / probe responses from any BSSID. */
2705 	rtwn_set_rx_bssid_all(sc, 1);
2706 	/* Set gain for scanning. */
2707 	rtwn_set_gain(sc, 0x20);
2708 	RTWN_UNLOCK(sc);
2709 }
2710 
2711 static void
2712 rtwn_scan_end(struct ieee80211com *ic)
2713 {
2714 	struct rtwn_softc *sc = ic->ic_softc;
2715 
2716 	RTWN_LOCK(sc);
2717 	/* Restore limitations. */
2718 	rtwn_set_rx_bssid_all(sc, 0);
2719 	/* Set gain under link. */
2720 	rtwn_set_gain(sc, 0x32);
2721 	RTWN_UNLOCK(sc);
2722 }
2723 
2724 static void
2725 rtwn_getradiocaps(struct ieee80211com *ic,
2726     int maxchans, int *nchans, struct ieee80211_channel chans[])
2727 {
2728 	uint8_t bands[IEEE80211_MODE_BYTES];
2729 
2730 	memset(bands, 0, sizeof(bands));
2731 	setbit(bands, IEEE80211_MODE_11B);
2732 	setbit(bands, IEEE80211_MODE_11G);
2733 	ieee80211_add_channel_list_2ghz(chans, maxchans, nchans,
2734 	    rtwn_chan_2ghz, nitems(rtwn_chan_2ghz), bands, 0);
2735 }
2736 
2737 static void
2738 rtwn_set_channel(struct ieee80211com *ic)
2739 {
2740 	struct rtwn_softc *sc = ic->ic_softc;
2741 	struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
2742 
2743 	RTWN_LOCK(sc);
2744 	if (vap->iv_state == IEEE80211_S_SCAN) {
2745 		/* Make link LED blink during scan. */
2746 		rtwn_set_led(sc, RTWN_LED_LINK, !sc->ledlink);
2747 	}
2748 	rtwn_set_chan(sc, ic->ic_curchan, NULL);
2749 	RTWN_UNLOCK(sc);
2750 }
2751 
2752 static void
2753 rtwn_update_mcast(struct ieee80211com *ic)
2754 {
2755 
2756 	/* XXX do nothing?  */
2757 }
2758 
2759 static void
2760 rtwn_set_chan(struct rtwn_softc *sc, struct ieee80211_channel *c,
2761     struct ieee80211_channel *extc)
2762 {
2763 	struct ieee80211com *ic = &sc->sc_ic;
2764 	u_int chan;
2765 	int i;
2766 
2767 	chan = ieee80211_chan2ieee(ic, c);	/* XXX center freq! */
2768 	if (chan == 0 || chan == IEEE80211_CHAN_ANY) {
2769 		device_printf(sc->sc_dev,
2770 		    "%s: invalid channel %x\n", __func__, chan);
2771 		return;
2772 	}
2773 
2774 	/* Set Tx power for this new channel. */
2775 	rtwn_set_txpower(sc, c, extc);
2776 
2777 	for (i = 0; i < sc->nrxchains; i++) {
2778 		rtwn_rf_write(sc, i, R92C_RF_CHNLBW,
2779 		    RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan));
2780 	}
2781 #ifndef IEEE80211_NO_HT
2782 	if (extc != NULL) {
2783 		uint32_t reg;
2784 
2785 		/* Is secondary channel below or above primary? */
2786 		int prichlo = c->ic_freq < extc->ic_freq;
2787 
2788 		rtwn_write_1(sc, R92C_BWOPMODE,
2789 		    rtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ);
2790 
2791 		reg = rtwn_read_1(sc, R92C_RRSR + 2);
2792 		reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5;
2793 		rtwn_write_1(sc, R92C_RRSR + 2, reg);
2794 
2795 		rtwn_bb_write(sc, R92C_FPGA0_RFMOD,
2796 		    rtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ);
2797 		rtwn_bb_write(sc, R92C_FPGA1_RFMOD,
2798 		    rtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ);
2799 
2800 		/* Set CCK side band. */
2801 		reg = rtwn_bb_read(sc, R92C_CCK0_SYSTEM);
2802 		reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4;
2803 		rtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg);
2804 
2805 		reg = rtwn_bb_read(sc, R92C_OFDM1_LSTF);
2806 		reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10;
2807 		rtwn_bb_write(sc, R92C_OFDM1_LSTF, reg);
2808 
2809 		rtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2,
2810 		    rtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) &
2811 		    ~R92C_FPGA0_ANAPARAM2_CBW20);
2812 
2813 		reg = rtwn_bb_read(sc, 0x818);
2814 		reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26;
2815 		rtwn_bb_write(sc, 0x818, reg);
2816 
2817 		/* Select 40MHz bandwidth. */
2818 		rtwn_rf_write(sc, 0, R92C_RF_CHNLBW,
2819 		    (sc->rf_chnlbw[0] & ~0xfff) | chan);
2820 	} else
2821 #endif
2822 	{
2823 		rtwn_write_1(sc, R92C_BWOPMODE,
2824 		    rtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ);
2825 
2826 		rtwn_bb_write(sc, R92C_FPGA0_RFMOD,
2827 		    rtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ);
2828 		rtwn_bb_write(sc, R92C_FPGA1_RFMOD,
2829 		    rtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ);
2830 
2831 		rtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2,
2832 		    rtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) |
2833 		    R92C_FPGA0_ANAPARAM2_CBW20);
2834 
2835 		/* Select 20MHz bandwidth. */
2836 		rtwn_rf_write(sc, 0, R92C_RF_CHNLBW,
2837 		    (sc->rf_chnlbw[0] & ~0xfff) | R92C_RF_CHNLBW_BW20 | chan);
2838 	}
2839 }
2840 
2841 static int
2842 rtwn_iq_calib_chain(struct rtwn_softc *sc, int chain, uint16_t tx[2],
2843     uint16_t rx[2])
2844 {
2845 	uint32_t status;
2846 	int offset = chain * 0x20;
2847 
2848 	if (chain == 0) {	/* IQ calibration for chain 0. */
2849 		/* IQ calibration settings for chain 0. */
2850 		rtwn_bb_write(sc, 0xe30, 0x10008c1f);
2851 		rtwn_bb_write(sc, 0xe34, 0x10008c1f);
2852 		rtwn_bb_write(sc, 0xe38, 0x82140102);
2853 
2854 		if (sc->ntxchains > 1) {
2855 			rtwn_bb_write(sc, 0xe3c, 0x28160202);	/* 2T */
2856 			/* IQ calibration settings for chain 1. */
2857 			rtwn_bb_write(sc, 0xe50, 0x10008c22);
2858 			rtwn_bb_write(sc, 0xe54, 0x10008c22);
2859 			rtwn_bb_write(sc, 0xe58, 0x82140102);
2860 			rtwn_bb_write(sc, 0xe5c, 0x28160202);
2861 		} else
2862 			rtwn_bb_write(sc, 0xe3c, 0x28160502);	/* 1T */
2863 
2864 		/* LO calibration settings. */
2865 		rtwn_bb_write(sc, 0xe4c, 0x001028d1);
2866 		/* We're doing LO and IQ calibration in one shot. */
2867 		rtwn_bb_write(sc, 0xe48, 0xf9000000);
2868 		rtwn_bb_write(sc, 0xe48, 0xf8000000);
2869 
2870 	} else {		/* IQ calibration for chain 1. */
2871 		/* We're doing LO and IQ calibration in one shot. */
2872 		rtwn_bb_write(sc, 0xe60, 0x00000002);
2873 		rtwn_bb_write(sc, 0xe60, 0x00000000);
2874 	}
2875 
2876 	/* Give LO and IQ calibrations the time to complete. */
2877 	DELAY(1000);
2878 
2879 	/* Read IQ calibration status. */
2880 	status = rtwn_bb_read(sc, 0xeac);
2881 
2882 	if (status & (1 << (28 + chain * 3)))
2883 		return (0);	/* Tx failed. */
2884 	/* Read Tx IQ calibration results. */
2885 	tx[0] = (rtwn_bb_read(sc, 0xe94 + offset) >> 16) & 0x3ff;
2886 	tx[1] = (rtwn_bb_read(sc, 0xe9c + offset) >> 16) & 0x3ff;
2887 	if (tx[0] == 0x142 || tx[1] == 0x042)
2888 		return (0);	/* Tx failed. */
2889 
2890 	if (status & (1 << (27 + chain * 3)))
2891 		return (1);	/* Rx failed. */
2892 	/* Read Rx IQ calibration results. */
2893 	rx[0] = (rtwn_bb_read(sc, 0xea4 + offset) >> 16) & 0x3ff;
2894 	rx[1] = (rtwn_bb_read(sc, 0xeac + offset) >> 16) & 0x3ff;
2895 	if (rx[0] == 0x132 || rx[1] == 0x036)
2896 		return (1);	/* Rx failed. */
2897 
2898 	return (3);	/* Both Tx and Rx succeeded. */
2899 }
2900 
2901 static void
2902 rtwn_iq_calib_run(struct rtwn_softc *sc, int n, uint16_t tx[2][2],
2903     uint16_t rx[2][2])
2904 {
2905 	/* Registers to save and restore during IQ calibration. */
2906 	struct iq_cal_regs {
2907 		uint32_t	adda[16];
2908 		uint8_t		txpause;
2909 		uint8_t		bcn_ctrl;
2910 		uint8_t		ustime_tsf;
2911 		uint32_t	gpio_muxcfg;
2912 		uint32_t	ofdm0_trxpathena;
2913 		uint32_t	ofdm0_trmuxpar;
2914 		uint32_t	fpga0_rfifacesw1;
2915 	} iq_cal_regs;
2916 	static const uint16_t reg_adda[16] = {
2917 		0x85c, 0xe6c, 0xe70, 0xe74,
2918 		0xe78, 0xe7c, 0xe80, 0xe84,
2919 		0xe88, 0xe8c, 0xed0, 0xed4,
2920 		0xed8, 0xedc, 0xee0, 0xeec
2921 	};
2922 	int i, chain;
2923 	uint32_t hssi_param1;
2924 
2925 	if (n == 0) {
2926 		for (i = 0; i < nitems(reg_adda); i++)
2927 			iq_cal_regs.adda[i] = rtwn_bb_read(sc, reg_adda[i]);
2928 
2929 		iq_cal_regs.txpause = rtwn_read_1(sc, R92C_TXPAUSE);
2930 		iq_cal_regs.bcn_ctrl = rtwn_read_1(sc, R92C_BCN_CTRL);
2931 		iq_cal_regs.ustime_tsf = rtwn_read_1(sc, R92C_USTIME_TSF);
2932 		iq_cal_regs.gpio_muxcfg = rtwn_read_4(sc, R92C_GPIO_MUXCFG);
2933 	}
2934 
2935 	if (sc->ntxchains == 1) {
2936 		rtwn_bb_write(sc, reg_adda[0], 0x0b1b25a0);
2937 		for (i = 1; i < nitems(reg_adda); i++)
2938 			rtwn_bb_write(sc, reg_adda[i], 0x0bdb25a0);
2939 	} else {
2940 		for (i = 0; i < nitems(reg_adda); i++)
2941 			rtwn_bb_write(sc, reg_adda[i], 0x04db25a4);
2942 	}
2943 
2944 	hssi_param1 = rtwn_bb_read(sc, R92C_HSSI_PARAM1(0));
2945 	if (!(hssi_param1 & R92C_HSSI_PARAM1_PI)) {
2946 		rtwn_bb_write(sc, R92C_HSSI_PARAM1(0),
2947 		    hssi_param1 | R92C_HSSI_PARAM1_PI);
2948 		rtwn_bb_write(sc, R92C_HSSI_PARAM1(1),
2949 		    hssi_param1 | R92C_HSSI_PARAM1_PI);
2950 	}
2951 
2952 	if (n == 0) {
2953 		iq_cal_regs.ofdm0_trxpathena =
2954 		    rtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA);
2955 		iq_cal_regs.ofdm0_trmuxpar =
2956 		    rtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR);
2957 		iq_cal_regs.fpga0_rfifacesw1 =
2958 		    rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1));
2959 	}
2960 
2961 	rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, 0x03a05600);
2962 	rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, 0x000800e4);
2963 	rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), 0x22204000);
2964 	if (sc->ntxchains > 1) {
2965 		rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00010000);
2966 		rtwn_bb_write(sc, R92C_LSSI_PARAM(1), 0x00010000);
2967 	}
2968 
2969 	rtwn_write_1(sc, R92C_TXPAUSE, 0x3f);
2970 	rtwn_write_1(sc, R92C_BCN_CTRL, iq_cal_regs.bcn_ctrl & ~(0x08));
2971 	rtwn_write_1(sc, R92C_USTIME_TSF, iq_cal_regs.ustime_tsf & ~(0x08));
2972 	rtwn_write_1(sc, R92C_GPIO_MUXCFG,
2973 	    iq_cal_regs.gpio_muxcfg & ~(0x20));
2974 
2975 	rtwn_bb_write(sc, 0x0b68, 0x00080000);
2976 	if (sc->ntxchains > 1)
2977 		rtwn_bb_write(sc, 0x0b6c, 0x00080000);
2978 
2979 	rtwn_bb_write(sc, 0x0e28, 0x80800000);
2980 	rtwn_bb_write(sc, 0x0e40, 0x01007c00);
2981 	rtwn_bb_write(sc, 0x0e44, 0x01004800);
2982 
2983 	rtwn_bb_write(sc, 0x0b68, 0x00080000);
2984 
2985 	for (chain = 0; chain < sc->ntxchains; chain++) {
2986 		if (chain > 0) {
2987 			/* Put chain 0 on standby. */
2988 			rtwn_bb_write(sc, 0x0e28, 0x00);
2989 			rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00010000);
2990 			rtwn_bb_write(sc, 0x0e28, 0x80800000);
2991 
2992 			/* Enable chain 1. */
2993 			for (i = 0; i < nitems(reg_adda); i++)
2994 				rtwn_bb_write(sc, reg_adda[i], 0x0b1b25a4);
2995 		}
2996 
2997 		/* Run IQ calibration twice. */
2998 		for (i = 0; i < 2; i++) {
2999 			int ret;
3000 
3001 			ret = rtwn_iq_calib_chain(sc, chain,
3002 			    tx[chain], rx[chain]);
3003 			if (ret == 0) {
3004 				DPRINTF(("%s: chain %d: Tx failed.\n",
3005 				    __func__, chain));
3006 				tx[chain][0] = 0xff;
3007 				tx[chain][1] = 0xff;
3008 				rx[chain][0] = 0xff;
3009 				rx[chain][1] = 0xff;
3010 			} else if (ret == 1) {
3011 				DPRINTF(("%s: chain %d: Rx failed.\n",
3012 				    __func__, chain));
3013 				rx[chain][0] = 0xff;
3014 				rx[chain][1] = 0xff;
3015 			} else if (ret == 3) {
3016 				DPRINTF(("%s: chain %d: Both Tx and Rx "
3017 				    "succeeded.\n", __func__, chain));
3018 			}
3019 		}
3020 
3021 		DPRINTF(("%s: results for run %d chain %d: tx[0]=0x%x, "
3022 		    "tx[1]=0x%x rx[0]=0x%x rx[1]=0x%x\n", __func__, n, chain,
3023 		    tx[chain][0], tx[chain][1], rx[chain][0], rx[chain][1]));
3024 	}
3025 
3026 	rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA,
3027 	    iq_cal_regs.ofdm0_trxpathena);
3028 	rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1),
3029 	    iq_cal_regs.fpga0_rfifacesw1);
3030 	rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, iq_cal_regs.ofdm0_trmuxpar);
3031 
3032 	rtwn_bb_write(sc, 0x0e28, 0x00);
3033 	rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00032ed3);
3034 	if (sc->ntxchains > 1)
3035 		rtwn_bb_write(sc, R92C_LSSI_PARAM(1), 0x00032ed3);
3036 
3037 	if (n != 0) {
3038 		if (!(hssi_param1 & R92C_HSSI_PARAM1_PI)) {
3039 			rtwn_bb_write(sc, R92C_HSSI_PARAM1(0), hssi_param1);
3040 			rtwn_bb_write(sc, R92C_HSSI_PARAM1(1), hssi_param1);
3041 		}
3042 
3043 		for (i = 0; i < nitems(reg_adda); i++)
3044 			rtwn_bb_write(sc, reg_adda[i], iq_cal_regs.adda[i]);
3045 
3046 		rtwn_write_1(sc, R92C_TXPAUSE, iq_cal_regs.txpause);
3047 		rtwn_write_1(sc, R92C_BCN_CTRL, iq_cal_regs.bcn_ctrl);
3048 		rtwn_write_1(sc, R92C_USTIME_TSF, iq_cal_regs.ustime_tsf);
3049 		rtwn_write_4(sc, R92C_GPIO_MUXCFG, iq_cal_regs.gpio_muxcfg);
3050 	}
3051 }
3052 
3053 #define RTWN_IQ_CAL_MAX_TOLERANCE 5
3054 static int
3055 rtwn_iq_calib_compare_results(uint16_t tx1[2][2], uint16_t rx1[2][2],
3056     uint16_t tx2[2][2], uint16_t rx2[2][2], int ntxchains)
3057 {
3058 	int chain, i, tx_ok[2], rx_ok[2];
3059 
3060 	tx_ok[0] = tx_ok[1] = rx_ok[0] = rx_ok[1] = 0;
3061 	for (chain = 0; chain < ntxchains; chain++) {
3062 		for (i = 0; i < 2; i++)	{
3063 			if (tx1[chain][i] == 0xff || tx2[chain][i] == 0xff ||
3064 			    rx1[chain][i] == 0xff || rx2[chain][i] == 0xff)
3065 				continue;
3066 
3067 			tx_ok[chain] = (abs(tx1[chain][i] - tx2[chain][i]) <=
3068 			    RTWN_IQ_CAL_MAX_TOLERANCE);
3069 
3070 			rx_ok[chain] = (abs(rx1[chain][i] - rx2[chain][i]) <=
3071 			    RTWN_IQ_CAL_MAX_TOLERANCE);
3072 		}
3073 	}
3074 
3075 	if (ntxchains > 1)
3076 		return (tx_ok[0] && tx_ok[1] && rx_ok[0] && rx_ok[1]);
3077 	else
3078 		return (tx_ok[0] && rx_ok[0]);
3079 }
3080 #undef RTWN_IQ_CAL_MAX_TOLERANCE
3081 
3082 static void
3083 rtwn_iq_calib_write_results(struct rtwn_softc *sc, uint16_t tx[2],
3084     uint16_t rx[2], int chain)
3085 {
3086 	uint32_t reg, val, x;
3087 	long y, tx_c;
3088 
3089 	if (tx[0] == 0xff || tx[1] == 0xff)
3090 		return;
3091 
3092 	reg = rtwn_bb_read(sc, R92C_OFDM0_TXIQIMBALANCE(chain));
3093 	val = ((reg >> 22) & 0x3ff);
3094 	x = tx[0];
3095 	if (x & 0x0200)
3096 		x |= 0xfc00;
3097 	reg = (((x * val) >> 8) & 0x3ff);
3098 	rtwn_bb_write(sc, R92C_OFDM0_TXIQIMBALANCE(chain), reg);
3099 
3100 	reg = rtwn_bb_read(sc, R92C_OFDM0_ECCATHRESHOLD);
3101 	if (((x * val) >> 7) & 0x01)
3102 		reg |= 0x80000000;
3103 	else
3104 		reg &= ~0x80000000;
3105 	rtwn_bb_write(sc, R92C_OFDM0_ECCATHRESHOLD, reg);
3106 
3107 	y = tx[1];
3108 	if (y & 0x00000200)
3109 		y |= 0xfffffc00;
3110 	tx_c = (y * val) >> 8;
3111 	reg = rtwn_bb_read(sc, R92C_OFDM0_TXAFE(chain));
3112 	reg |= ((((tx_c & 0x3c0) >> 6) << 24) & 0xf0000000);
3113 	rtwn_bb_write(sc, R92C_OFDM0_TXAFE(chain), reg);
3114 
3115 	reg = rtwn_bb_read(sc, R92C_OFDM0_TXIQIMBALANCE(chain));
3116 	reg |= (((tx_c & 0x3f) << 16) & 0x003F0000);
3117 	rtwn_bb_write(sc, R92C_OFDM0_TXIQIMBALANCE(chain), reg);
3118 
3119 	reg = rtwn_bb_read(sc, R92C_OFDM0_ECCATHRESHOLD);
3120 	if (((y * val) >> 7) & 0x01)
3121 		reg |= 0x20000000;
3122 	else
3123 		reg &= ~0x20000000;
3124 	rtwn_bb_write(sc, R92C_OFDM0_ECCATHRESHOLD, reg);
3125 
3126 	if (rx[0] == 0xff || rx[1] == 0xff)
3127 		return;
3128 
3129 	reg = rtwn_bb_read(sc, R92C_OFDM0_RXIQIMBALANCE(chain));
3130 	reg |= (rx[0] & 0x3ff);
3131 	rtwn_bb_write(sc, R92C_OFDM0_RXIQIMBALANCE(chain), reg);
3132 	reg |= (((rx[1] & 0x03f) << 8) & 0xFC00);
3133 	rtwn_bb_write(sc, R92C_OFDM0_RXIQIMBALANCE(chain), reg);
3134 
3135 	if (chain == 0) {
3136 		reg = rtwn_bb_read(sc, R92C_OFDM0_RXIQEXTANTA);
3137 		reg |= (((rx[1] & 0xf) >> 6) & 0x000f);
3138 		rtwn_bb_write(sc, R92C_OFDM0_RXIQEXTANTA, reg);
3139 	} else {
3140 		reg = rtwn_bb_read(sc, R92C_OFDM0_AGCRSSITABLE);
3141 		reg |= ((((rx[1] & 0xf) >> 6) << 12) & 0xf000);
3142 		rtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, reg);
3143 	}
3144 }
3145 
3146 #define RTWN_IQ_CAL_NRUN	3
3147 static void
3148 rtwn_iq_calib(struct rtwn_softc *sc)
3149 {
3150 	uint16_t tx[RTWN_IQ_CAL_NRUN][2][2], rx[RTWN_IQ_CAL_NRUN][2][2];
3151 	int n, valid;
3152 
3153 	valid = 0;
3154 	for (n = 0; n < RTWN_IQ_CAL_NRUN; n++) {
3155 		rtwn_iq_calib_run(sc, n, tx[n], rx[n]);
3156 
3157 		if (n == 0)
3158 			continue;
3159 
3160 		/* Valid results remain stable after consecutive runs. */
3161 		valid = rtwn_iq_calib_compare_results(tx[n - 1], rx[n - 1],
3162 		    tx[n], rx[n], sc->ntxchains);
3163 		if (valid)
3164 			break;
3165 	}
3166 
3167 	if (valid) {
3168 		rtwn_iq_calib_write_results(sc, tx[n][0], rx[n][0], 0);
3169 		if (sc->ntxchains > 1)
3170 			rtwn_iq_calib_write_results(sc, tx[n][1], rx[n][1], 1);
3171 	}
3172 }
3173 #undef RTWN_IQ_CAL_NRUN
3174 
3175 static void
3176 rtwn_lc_calib(struct rtwn_softc *sc)
3177 {
3178 	uint32_t rf_ac[2];
3179 	uint8_t txmode;
3180 	int i;
3181 
3182 	txmode = rtwn_read_1(sc, R92C_OFDM1_LSTF + 3);
3183 	if ((txmode & 0x70) != 0) {
3184 		/* Disable all continuous Tx. */
3185 		rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70);
3186 
3187 		/* Set RF mode to standby mode. */
3188 		for (i = 0; i < sc->nrxchains; i++) {
3189 			rf_ac[i] = rtwn_rf_read(sc, i, R92C_RF_AC);
3190 			rtwn_rf_write(sc, i, R92C_RF_AC,
3191 			    RW(rf_ac[i], R92C_RF_AC_MODE,
3192 				R92C_RF_AC_MODE_STANDBY));
3193 		}
3194 	} else {
3195 		/* Block all Tx queues. */
3196 		rtwn_write_1(sc, R92C_TXPAUSE, 0xff);
3197 	}
3198 	/* Start calibration. */
3199 	rtwn_rf_write(sc, 0, R92C_RF_CHNLBW,
3200 	    rtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART);
3201 
3202 	/* Give calibration the time to complete. */
3203 	DELAY(100);
3204 
3205 	/* Restore configuration. */
3206 	if ((txmode & 0x70) != 0) {
3207 		/* Restore Tx mode. */
3208 		rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode);
3209 		/* Restore RF mode. */
3210 		for (i = 0; i < sc->nrxchains; i++)
3211 			rtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]);
3212 	} else {
3213 		/* Unblock all Tx queues. */
3214 		rtwn_write_1(sc, R92C_TXPAUSE, 0x00);
3215 	}
3216 }
3217 
3218 static void
3219 rtwn_temp_calib(struct rtwn_softc *sc)
3220 {
3221 	int temp;
3222 
3223 	if (sc->thcal_state == 0) {
3224 		/* Start measuring temperature. */
3225 		rtwn_rf_write(sc, 0, R92C_RF_T_METER, 0x60);
3226 		sc->thcal_state = 1;
3227 		return;
3228 	}
3229 	sc->thcal_state = 0;
3230 
3231 	/* Read measured temperature. */
3232 	temp = rtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f;
3233 	if (temp == 0)	/* Read failed, skip. */
3234 		return;
3235 	DPRINTFN(2, ("temperature=%d\n", temp));
3236 
3237 	/*
3238 	 * Redo IQ and LC calibration if temperature changed significantly
3239 	 * since last calibration.
3240 	 */
3241 	if (sc->thcal_lctemp == 0) {
3242 		/* First calibration is performed in rtwn_init(). */
3243 		sc->thcal_lctemp = temp;
3244 	} else if (abs(temp - sc->thcal_lctemp) > 1) {
3245 		DPRINTF(("IQ/LC calib triggered by temp: %d -> %d\n",
3246 		    sc->thcal_lctemp, temp));
3247 		rtwn_iq_calib(sc);
3248 		rtwn_lc_calib(sc);
3249 		/* Record temperature of last calibration. */
3250 		sc->thcal_lctemp = temp;
3251 	}
3252 }
3253 
3254 static int
3255 rtwn_init(struct rtwn_softc *sc)
3256 {
3257 	struct ieee80211com *ic = &sc->sc_ic;
3258 	struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
3259 	uint32_t reg;
3260 	uint8_t macaddr[IEEE80211_ADDR_LEN];
3261 	int i, error;
3262 
3263 	RTWN_LOCK(sc);
3264 
3265 	if (sc->sc_flags & RTWN_RUNNING) {
3266 		RTWN_UNLOCK(sc);
3267 		return 0;
3268 	}
3269 	sc->sc_flags |= RTWN_RUNNING;
3270 
3271 	/* Init firmware commands ring. */
3272 	sc->fwcur = 0;
3273 
3274 	/* Power on adapter. */
3275 	error = rtwn_power_on(sc);
3276 	if (error != 0) {
3277 		device_printf(sc->sc_dev, "could not power on adapter\n");
3278 		goto fail;
3279 	}
3280 
3281 	/* Initialize DMA. */
3282 	error = rtwn_dma_init(sc);
3283 	if (error != 0) {
3284 		device_printf(sc->sc_dev, "could not initialize DMA\n");
3285 		goto fail;
3286 	}
3287 
3288 	/* Set info size in Rx descriptors (in 64-bit words). */
3289 	rtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4);
3290 
3291 	/* Disable interrupts. */
3292 	rtwn_write_4(sc, R92C_HISR, 0x00000000);
3293 	rtwn_write_4(sc, R92C_HIMR, 0x00000000);
3294 
3295 	/* Set MAC address. */
3296 	IEEE80211_ADDR_COPY(macaddr, vap ? vap->iv_myaddr : ic->ic_macaddr);
3297 	for (i = 0; i < IEEE80211_ADDR_LEN; i++)
3298 		rtwn_write_1(sc, R92C_MACID + i, macaddr[i]);
3299 
3300 	/* Set initial network type. */
3301 	reg = rtwn_read_4(sc, R92C_CR);
3302 	reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA);
3303 	rtwn_write_4(sc, R92C_CR, reg);
3304 
3305 	rtwn_rxfilter_init(sc);
3306 
3307 	reg = rtwn_read_4(sc, R92C_RRSR);
3308 	reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_ALL);
3309 	rtwn_write_4(sc, R92C_RRSR, reg);
3310 
3311 	/* Set short/long retry limits. */
3312 	rtwn_write_2(sc, R92C_RL,
3313 	    SM(R92C_RL_SRL, 0x07) | SM(R92C_RL_LRL, 0x07));
3314 
3315 	/* Initialize EDCA parameters. */
3316 	rtwn_edca_init(sc);
3317 
3318 	/* Set data and response automatic rate fallback retry counts. */
3319 	rtwn_write_4(sc, R92C_DARFRC + 0, 0x01000000);
3320 	rtwn_write_4(sc, R92C_DARFRC + 4, 0x07060504);
3321 	rtwn_write_4(sc, R92C_RARFRC + 0, 0x01000000);
3322 	rtwn_write_4(sc, R92C_RARFRC + 4, 0x07060504);
3323 
3324 	rtwn_write_2(sc, R92C_FWHW_TXQ_CTRL, 0x1f80);
3325 
3326 	/* Set ACK timeout. */
3327 	rtwn_write_1(sc, R92C_ACKTO, 0x40);
3328 
3329 	/* Initialize beacon parameters. */
3330 	rtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404);
3331 	rtwn_write_1(sc, R92C_DRVERLYINT, 0x05);
3332 	rtwn_write_1(sc, R92C_BCNDMATIM, 0x02);
3333 	rtwn_write_2(sc, R92C_BCNTCFG, 0x660f);
3334 
3335 	/* Setup AMPDU aggregation. */
3336 	rtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631);	/* MCS7~0 */
3337 	rtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16);
3338 
3339 	rtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff);
3340 	rtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0);
3341 
3342 	rtwn_write_4(sc, R92C_PIFS, 0x1c);
3343 	rtwn_write_4(sc, R92C_MCUTST_1, 0x0);
3344 
3345 	/* Load 8051 microcode. */
3346 	error = rtwn_load_firmware(sc);
3347 	if (error != 0)
3348 		goto fail;
3349 
3350 	/* Initialize MAC/BB/RF blocks. */
3351 	rtwn_mac_init(sc);
3352 	rtwn_bb_init(sc);
3353 	rtwn_rf_init(sc);
3354 
3355 	/* Turn CCK and OFDM blocks on. */
3356 	reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD);
3357 	reg |= R92C_RFMOD_CCK_EN;
3358 	rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg);
3359 	reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD);
3360 	reg |= R92C_RFMOD_OFDM_EN;
3361 	rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg);
3362 
3363 	/* Clear per-station keys table. */
3364 	rtwn_cam_init(sc);
3365 
3366 	/* Enable hardware sequence numbering. */
3367 	rtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff);
3368 
3369 	/* Perform LO and IQ calibrations. */
3370 	rtwn_iq_calib(sc);
3371 	/* Perform LC calibration. */
3372 	rtwn_lc_calib(sc);
3373 
3374 	rtwn_pa_bias_init(sc);
3375 
3376 	/* Initialize GPIO setting. */
3377 	rtwn_write_1(sc, R92C_GPIO_MUXCFG,
3378 	    rtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT);
3379 
3380 	/* Fix for lower temperature. */
3381 	rtwn_write_1(sc, 0x15, 0xe9);
3382 
3383 	/* CLear pending interrupts. */
3384 	rtwn_write_4(sc, R92C_HISR, 0xffffffff);
3385 
3386 	/* Enable interrupts. */
3387 	rtwn_write_4(sc, R92C_HIMR, RTWN_INT_ENABLE);
3388 
3389 	callout_reset(&sc->watchdog_to, hz, rtwn_watchdog, sc);
3390 
3391 fail:
3392 	if (error != 0)
3393 		rtwn_stop_locked(sc);
3394 
3395 	RTWN_UNLOCK(sc);
3396 
3397 	return error;
3398 }
3399 
3400 static void
3401 rtwn_stop_locked(struct rtwn_softc *sc)
3402 {
3403 	uint16_t reg;
3404 	int i;
3405 
3406 	RTWN_LOCK_ASSERT(sc);
3407 
3408 	if (!(sc->sc_flags & RTWN_RUNNING))
3409 		return;
3410 
3411 	sc->sc_tx_timer = 0;
3412 	callout_stop(&sc->watchdog_to);
3413 	callout_stop(&sc->calib_to);
3414 	sc->sc_flags &= ~RTWN_RUNNING;
3415 
3416 	/* Disable interrupts. */
3417 	rtwn_write_4(sc, R92C_HISR, 0x00000000);
3418 	rtwn_write_4(sc, R92C_HIMR, 0x00000000);
3419 
3420 	/* Stop hardware. */
3421 	rtwn_write_1(sc, R92C_TXPAUSE, 0xff);
3422 	rtwn_write_1(sc, R92C_RF_CTRL, 0x00);
3423 	reg = rtwn_read_1(sc, R92C_SYS_FUNC_EN);
3424 	reg |= R92C_SYS_FUNC_EN_BB_GLB_RST;
3425 	rtwn_write_1(sc, R92C_SYS_FUNC_EN, reg);
3426 	reg &= ~R92C_SYS_FUNC_EN_BB_GLB_RST;
3427 	rtwn_write_1(sc, R92C_SYS_FUNC_EN, reg);
3428 	reg = rtwn_read_2(sc, R92C_CR);
3429 	reg &= ~(R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |
3430 	    R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN |
3431 	    R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN |
3432 	    R92C_CR_ENSEC);
3433 	rtwn_write_2(sc, R92C_CR, reg);
3434 	if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL)
3435 		rtwn_fw_reset(sc);
3436 	/* TODO: linux does additional btcoex stuff here */
3437 	rtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0x80); /* linux magic number */
3438 	rtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); /* ditto */
3439 	rtwn_write_1(sc, R92C_AFE_XTAL_CTRL, 0x0e); /* different with btcoex */
3440 	rtwn_write_1(sc, R92C_RSV_CTRL, 0x0e);
3441 	rtwn_write_1(sc, R92C_APS_FSMCO, R92C_APS_FSMCO_PDN_EN);
3442 
3443 	for (i = 0; i < RTWN_NTXQUEUES; i++)
3444 		rtwn_reset_tx_list(sc, i);
3445 	rtwn_reset_rx_list(sc);
3446 }
3447 
3448 static void
3449 rtwn_stop(struct rtwn_softc *sc)
3450 {
3451 	RTWN_LOCK(sc);
3452 	rtwn_stop_locked(sc);
3453 	RTWN_UNLOCK(sc);
3454 }
3455 
3456 static void
3457 rtwn_intr(void *arg)
3458 {
3459 	struct rtwn_softc *sc = arg;
3460 	uint32_t status;
3461 	int i;
3462 
3463 	RTWN_LOCK(sc);
3464 	status = rtwn_read_4(sc, R92C_HISR);
3465 	if (status == 0 || status == 0xffffffff) {
3466 		RTWN_UNLOCK(sc);
3467 		return;
3468 	}
3469 
3470 	/* Disable interrupts. */
3471 	rtwn_write_4(sc, R92C_HIMR, 0x00000000);
3472 
3473 	/* Ack interrupts. */
3474 	rtwn_write_4(sc, R92C_HISR, status);
3475 
3476 	/* Vendor driver treats RX errors like ROK... */
3477 	if (status & (R92C_IMR_ROK | R92C_IMR_RXFOVW | R92C_IMR_RDU)) {
3478 		bus_dmamap_sync(sc->rx_ring.desc_dmat, sc->rx_ring.desc_map,
3479 		    BUS_DMASYNC_POSTREAD);
3480 
3481 		for (i = 0; i < RTWN_RX_LIST_COUNT; i++) {
3482 			struct r92c_rx_desc *rx_desc = &sc->rx_ring.desc[i];
3483 			struct rtwn_rx_data *rx_data = &sc->rx_ring.rx_data[i];
3484 
3485 			if (le32toh(rx_desc->rxdw0) & R92C_RXDW0_OWN)
3486 				continue;
3487 
3488 			rtwn_rx_frame(sc, rx_desc, rx_data, i);
3489 		}
3490 	}
3491 
3492 	if (status & R92C_IMR_BDOK)
3493 		rtwn_tx_done(sc, RTWN_BEACON_QUEUE);
3494 	if (status & R92C_IMR_HIGHDOK)
3495 		rtwn_tx_done(sc, RTWN_HIGH_QUEUE);
3496 	if (status & R92C_IMR_MGNTDOK)
3497 		rtwn_tx_done(sc, RTWN_MGNT_QUEUE);
3498 	if (status & R92C_IMR_BKDOK)
3499 		rtwn_tx_done(sc, RTWN_BK_QUEUE);
3500 	if (status & R92C_IMR_BEDOK)
3501 		rtwn_tx_done(sc, RTWN_BE_QUEUE);
3502 	if (status & R92C_IMR_VIDOK)
3503 		rtwn_tx_done(sc, RTWN_VI_QUEUE);
3504 	if (status & R92C_IMR_VODOK)
3505 		rtwn_tx_done(sc, RTWN_VO_QUEUE);
3506 
3507 	/* Enable interrupts. */
3508 	rtwn_write_4(sc, R92C_HIMR, RTWN_INT_ENABLE);
3509 
3510 	RTWN_UNLOCK(sc);
3511 }
3512