1 /* $OpenBSD: if_rtwn.c,v 1.6 2015/08/28 00:03:53 deraadt Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2015 Stefan Sperling <stsp@openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include <sys/cdefs.h> 21 __FBSDID("$FreeBSD$"); 22 23 /* 24 * Driver for Realtek RTL8188CE 25 */ 26 27 #include <sys/param.h> 28 #include <sys/sysctl.h> 29 #include <sys/sockio.h> 30 #include <sys/mbuf.h> 31 #include <sys/kernel.h> 32 #include <sys/socket.h> 33 #include <sys/systm.h> 34 #include <sys/malloc.h> 35 #include <sys/lock.h> 36 #include <sys/mutex.h> 37 #include <sys/module.h> 38 #include <sys/bus.h> 39 #include <sys/endian.h> 40 #include <sys/firmware.h> 41 42 #include <machine/bus.h> 43 #include <machine/resource.h> 44 #include <sys/rman.h> 45 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcivar.h> 48 49 #include <net/bpf.h> 50 #include <net/if.h> 51 #include <net/if_var.h> 52 #include <net/if_arp.h> 53 #include <net/ethernet.h> 54 #include <net/if_dl.h> 55 #include <net/if_media.h> 56 #include <net/if_types.h> 57 58 #include <net80211/ieee80211_var.h> 59 #include <net80211/ieee80211_radiotap.h> 60 #include <net80211/ieee80211_regdomain.h> 61 #include <net80211/ieee80211_ratectl.h> 62 63 #include <netinet/in.h> 64 #include <netinet/in_systm.h> 65 #include <netinet/in_var.h> 66 #include <netinet/ip.h> 67 #include <netinet/if_ether.h> 68 69 #include <dev/rtwn/if_rtwnreg.h> 70 71 #define RTWN_DEBUG 72 #ifdef RTWN_DEBUG 73 #define DPRINTF(x) do { if (sc->sc_debug > 0) printf x; } while (0) 74 #define DPRINTFN(n, x) do { if (sc->sc_debug >= (n)) printf x; } while (0) 75 #else 76 #define DPRINTF(x) 77 #define DPRINTFN(n, x) 78 #endif 79 80 /* 81 * PCI configuration space registers. 82 */ 83 #define RTWN_PCI_IOBA 0x10 /* i/o mapped base */ 84 #define RTWN_PCI_MMBA 0x18 /* memory mapped base */ 85 86 #define RTWN_INT_ENABLE (R92C_IMR_ROK | R92C_IMR_VODOK | R92C_IMR_VIDOK | \ 87 R92C_IMR_BEDOK | R92C_IMR_BKDOK | R92C_IMR_MGNTDOK | \ 88 R92C_IMR_HIGHDOK | R92C_IMR_BDOK | R92C_IMR_RDU | \ 89 R92C_IMR_RXFOVW) 90 91 struct rtwn_ident { 92 uint16_t vendor; 93 uint16_t device; 94 const char *name; 95 }; 96 97 98 static const struct rtwn_ident rtwn_ident_table[] = { 99 { 0x10ec, 0x8176, "Realtek RTL8188CE" }, 100 { 0, 0, NULL } 101 }; 102 103 104 static void rtwn_dma_map_addr(void *, bus_dma_segment_t *, int, int); 105 static void rtwn_setup_rx_desc(struct rtwn_softc *, struct r92c_rx_desc *, 106 bus_addr_t, size_t, int); 107 static int rtwn_alloc_rx_list(struct rtwn_softc *); 108 static void rtwn_reset_rx_list(struct rtwn_softc *); 109 static void rtwn_free_rx_list(struct rtwn_softc *); 110 static int rtwn_alloc_tx_list(struct rtwn_softc *, int); 111 static void rtwn_reset_tx_list(struct rtwn_softc *, int); 112 static void rtwn_free_tx_list(struct rtwn_softc *, int); 113 static struct ieee80211vap *rtwn_vap_create(struct ieee80211com *, 114 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 115 const uint8_t [IEEE80211_ADDR_LEN], 116 const uint8_t [IEEE80211_ADDR_LEN]); 117 static void rtwn_vap_delete(struct ieee80211vap *); 118 static void rtwn_write_1(struct rtwn_softc *, uint16_t, uint8_t); 119 static void rtwn_write_2(struct rtwn_softc *, uint16_t, uint16_t); 120 static void rtwn_write_4(struct rtwn_softc *, uint16_t, uint32_t); 121 static uint8_t rtwn_read_1(struct rtwn_softc *, uint16_t); 122 static uint16_t rtwn_read_2(struct rtwn_softc *, uint16_t); 123 static uint32_t rtwn_read_4(struct rtwn_softc *, uint16_t); 124 static int rtwn_fw_cmd(struct rtwn_softc *, uint8_t, const void *, int); 125 static void rtwn_rf_write(struct rtwn_softc *, int, uint8_t, uint32_t); 126 static uint32_t rtwn_rf_read(struct rtwn_softc *, int, uint8_t); 127 static int rtwn_llt_write(struct rtwn_softc *, uint32_t, uint32_t); 128 static uint8_t rtwn_efuse_read_1(struct rtwn_softc *, uint16_t); 129 static void rtwn_efuse_read(struct rtwn_softc *); 130 static int rtwn_read_chipid(struct rtwn_softc *); 131 static void rtwn_read_rom(struct rtwn_softc *); 132 static int rtwn_ra_init(struct rtwn_softc *); 133 static void rtwn_tsf_sync_enable(struct rtwn_softc *); 134 static void rtwn_set_led(struct rtwn_softc *, int, int); 135 static void rtwn_calib_to(void *); 136 static int rtwn_newstate(struct ieee80211vap *, enum ieee80211_state, int); 137 static int rtwn_updateedca(struct ieee80211com *); 138 static void rtwn_update_avgrssi(struct rtwn_softc *, int, int8_t); 139 static int8_t rtwn_get_rssi(struct rtwn_softc *, int, void *); 140 static void rtwn_rx_frame(struct rtwn_softc *, struct r92c_rx_desc *, 141 struct rtwn_rx_data *, int); 142 static int rtwn_tx(struct rtwn_softc *, struct mbuf *, 143 struct ieee80211_node *); 144 static void rtwn_tx_done(struct rtwn_softc *, int); 145 static int rtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 146 const struct ieee80211_bpf_params *); 147 static int rtwn_transmit(struct ieee80211com *, struct mbuf *); 148 static void rtwn_parent(struct ieee80211com *); 149 static void rtwn_start(struct rtwn_softc *sc); 150 static void rtwn_watchdog(void *); 151 static int rtwn_power_on(struct rtwn_softc *); 152 static int rtwn_llt_init(struct rtwn_softc *); 153 static void rtwn_fw_reset(struct rtwn_softc *); 154 static void rtwn_fw_loadpage(struct rtwn_softc *, int, const uint8_t *, 155 int); 156 static int rtwn_load_firmware(struct rtwn_softc *); 157 static int rtwn_dma_init(struct rtwn_softc *); 158 static void rtwn_mac_init(struct rtwn_softc *); 159 static void rtwn_bb_init(struct rtwn_softc *); 160 static void rtwn_rf_init(struct rtwn_softc *); 161 static void rtwn_cam_init(struct rtwn_softc *); 162 static void rtwn_pa_bias_init(struct rtwn_softc *); 163 static void rtwn_rxfilter_init(struct rtwn_softc *); 164 static void rtwn_edca_init(struct rtwn_softc *); 165 static void rtwn_write_txpower(struct rtwn_softc *, int, uint16_t[]); 166 static void rtwn_get_txpower(struct rtwn_softc *, int, 167 struct ieee80211_channel *, struct ieee80211_channel *, 168 uint16_t[]); 169 static void rtwn_set_txpower(struct rtwn_softc *, 170 struct ieee80211_channel *, struct ieee80211_channel *); 171 static void rtwn_scan_start(struct ieee80211com *); 172 static void rtwn_scan_end(struct ieee80211com *); 173 static void rtwn_set_channel(struct ieee80211com *); 174 static void rtwn_update_mcast(struct ieee80211com *); 175 static void rtwn_set_chan(struct rtwn_softc *, 176 struct ieee80211_channel *, struct ieee80211_channel *); 177 static int rtwn_iq_calib_chain(struct rtwn_softc *, int, uint16_t[2], 178 uint16_t[2]); 179 static void rtwn_iq_calib_run(struct rtwn_softc *, int, uint16_t[2][2], 180 uint16_t[2][2]); 181 static int rtwn_iq_calib_compare_results(uint16_t[2][2], uint16_t[2][2], 182 uint16_t[2][2], uint16_t[2][2], int); 183 static void rtwn_iq_calib_write_results(struct rtwn_softc *, uint16_t[2], 184 uint16_t[2], int); 185 static void rtwn_iq_calib(struct rtwn_softc *); 186 static void rtwn_lc_calib(struct rtwn_softc *); 187 static void rtwn_temp_calib(struct rtwn_softc *); 188 static void rtwn_init_locked(struct rtwn_softc *); 189 static void rtwn_init(struct rtwn_softc *); 190 static void rtwn_stop_locked(struct rtwn_softc *); 191 static void rtwn_stop(struct rtwn_softc *); 192 static void rtwn_intr(void *); 193 static void rtwn_hw_reset(void *, int); 194 195 /* Aliases. */ 196 #define rtwn_bb_write rtwn_write_4 197 #define rtwn_bb_read rtwn_read_4 198 199 static int rtwn_probe(device_t); 200 static int rtwn_attach(device_t); 201 static int rtwn_detach(device_t); 202 static int rtwn_shutdown(device_t); 203 static int rtwn_suspend(device_t); 204 static int rtwn_resume(device_t); 205 206 static device_method_t rtwn_methods[] = { 207 /* Device interface */ 208 DEVMETHOD(device_probe, rtwn_probe), 209 DEVMETHOD(device_attach, rtwn_attach), 210 DEVMETHOD(device_detach, rtwn_detach), 211 DEVMETHOD(device_shutdown, rtwn_shutdown), 212 DEVMETHOD(device_suspend, rtwn_suspend), 213 DEVMETHOD(device_resume, rtwn_resume), 214 215 DEVMETHOD_END 216 }; 217 218 static driver_t rtwn_driver = { 219 "rtwn", 220 rtwn_methods, 221 sizeof (struct rtwn_softc) 222 }; 223 static devclass_t rtwn_devclass; 224 225 DRIVER_MODULE(rtwn, pci, rtwn_driver, rtwn_devclass, NULL, NULL); 226 227 MODULE_VERSION(rtwn, 1); 228 229 MODULE_DEPEND(rtwn, pci, 1, 1, 1); 230 MODULE_DEPEND(rtwn, wlan, 1, 1, 1); 231 MODULE_DEPEND(rtwn, firmware, 1, 1, 1); 232 233 static int 234 rtwn_probe(device_t dev) 235 { 236 const struct rtwn_ident *ident; 237 238 for (ident = rtwn_ident_table; ident->name != NULL; ident++) { 239 if (pci_get_vendor(dev) == ident->vendor && 240 pci_get_device(dev) == ident->device) { 241 device_set_desc(dev, ident->name); 242 return (BUS_PROBE_DEFAULT); 243 } 244 } 245 return (ENXIO); 246 } 247 248 static int 249 rtwn_attach(device_t dev) 250 { 251 struct rtwn_softc *sc = device_get_softc(dev); 252 struct ieee80211com *ic = &sc->sc_ic; 253 uint32_t lcsr; 254 uint8_t bands[howmany(IEEE80211_MODE_MAX, 8)]; 255 int i, count, error, rid; 256 257 sc->sc_dev = dev; 258 sc->sc_debug = 0; 259 260 /* 261 * Get the offset of the PCI Express Capability Structure in PCI 262 * Configuration Space. 263 */ 264 error = pci_find_cap(dev, PCIY_EXPRESS, &sc->sc_cap_off); 265 if (error != 0) { 266 device_printf(dev, "PCIe capability structure not found!\n"); 267 return (error); 268 } 269 270 /* Enable bus-mastering. */ 271 pci_enable_busmaster(dev); 272 273 rid = PCIR_BAR(2); 274 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 275 RF_ACTIVE); 276 if (sc->mem == NULL) { 277 device_printf(dev, "can't map mem space\n"); 278 return (ENOMEM); 279 } 280 sc->sc_st = rman_get_bustag(sc->mem); 281 sc->sc_sh = rman_get_bushandle(sc->mem); 282 283 /* Install interrupt handler. */ 284 count = 1; 285 rid = 0; 286 if (pci_alloc_msi(dev, &count) == 0) 287 rid = 1; 288 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE | 289 (rid != 0 ? 0 : RF_SHAREABLE)); 290 if (sc->irq == NULL) { 291 device_printf(dev, "can't map interrupt\n"); 292 return (ENXIO); 293 } 294 295 RTWN_LOCK_INIT(sc); 296 callout_init_mtx(&sc->calib_to, &sc->sc_mtx, 0); 297 callout_init_mtx(&sc->watchdog_to, &sc->sc_mtx, 0); 298 TASK_INIT(&sc->sc_reinit_task, 0, rtwn_hw_reset, sc); 299 mbufq_init(&sc->sc_snd, ifqmaxlen); 300 301 error = rtwn_read_chipid(sc); 302 if (error != 0) { 303 device_printf(dev, "unsupported test chip\n"); 304 goto fail; 305 } 306 307 /* Disable PCIe Active State Power Management (ASPM). */ 308 lcsr = pci_read_config(sc->sc_dev, sc->sc_cap_off + PCIER_LINK_CTL, 4); 309 lcsr &= ~PCIEM_LINK_CTL_ASPMC; 310 pci_write_config(sc->sc_dev, sc->sc_cap_off + PCIER_LINK_CTL, lcsr, 4); 311 312 /* Allocate Tx/Rx buffers. */ 313 error = rtwn_alloc_rx_list(sc); 314 if (error != 0) { 315 device_printf(dev, "could not allocate Rx buffers\n"); 316 goto fail; 317 } 318 for (i = 0; i < RTWN_NTXQUEUES; i++) { 319 error = rtwn_alloc_tx_list(sc, i); 320 if (error != 0) { 321 device_printf(dev, "could not allocate Tx buffers\n"); 322 goto fail; 323 } 324 } 325 326 /* Determine number of Tx/Rx chains. */ 327 if (sc->chip & RTWN_CHIP_92C) { 328 sc->ntxchains = (sc->chip & RTWN_CHIP_92C_1T2R) ? 1 : 2; 329 sc->nrxchains = 2; 330 } else { 331 sc->ntxchains = 1; 332 sc->nrxchains = 1; 333 } 334 rtwn_read_rom(sc); 335 336 device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n", 337 (sc->chip & RTWN_CHIP_92C) ? "8192CE" : "8188CE", 338 sc->ntxchains, sc->nrxchains); 339 340 ic->ic_softc = sc; 341 ic->ic_name = device_get_nameunit(dev); 342 ic->ic_opmode = IEEE80211_M_STA; 343 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 344 345 /* set device capabilities */ 346 ic->ic_caps = 347 IEEE80211_C_STA /* station mode */ 348 | IEEE80211_C_MONITOR /* monitor mode */ 349 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 350 | IEEE80211_C_SHSLOT /* short slot time supported */ 351 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 352 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 353 | IEEE80211_C_WME /* 802.11e */ 354 ; 355 356 memset(bands, 0, sizeof(bands)); 357 setbit(bands, IEEE80211_MODE_11B); 358 setbit(bands, IEEE80211_MODE_11G); 359 ieee80211_init_channels(ic, NULL, bands); 360 361 ieee80211_ifattach(ic); 362 363 ic->ic_wme.wme_update = rtwn_updateedca; 364 ic->ic_update_mcast = rtwn_update_mcast; 365 ic->ic_scan_start =rtwn_scan_start; 366 ic->ic_scan_end = rtwn_scan_end; 367 ic->ic_set_channel = rtwn_set_channel; 368 ic->ic_raw_xmit = rtwn_raw_xmit; 369 ic->ic_transmit = rtwn_transmit; 370 ic->ic_parent = rtwn_parent; 371 ic->ic_vap_create = rtwn_vap_create; 372 ic->ic_vap_delete = rtwn_vap_delete; 373 374 ieee80211_radiotap_attach(ic, 375 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 376 RTWN_TX_RADIOTAP_PRESENT, 377 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 378 RTWN_RX_RADIOTAP_PRESENT); 379 380 /* 381 * Hook our interrupt after all initialization is complete. 382 */ 383 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 384 NULL, rtwn_intr, sc, &sc->sc_ih); 385 if (error != 0) { 386 device_printf(dev, "can't establish interrupt, error %d\n", 387 error); 388 goto fail; 389 } 390 391 if (bootverbose) 392 ieee80211_announce(ic); 393 394 return (0); 395 396 fail: 397 rtwn_detach(dev); 398 return (error); 399 } 400 401 402 static int 403 rtwn_detach(device_t dev) 404 { 405 struct rtwn_softc *sc = device_get_softc(dev); 406 int i; 407 408 if (sc->sc_ic.ic_softc != NULL) { 409 ieee80211_draintask(&sc->sc_ic, &sc->sc_reinit_task); 410 rtwn_stop(sc); 411 412 callout_drain(&sc->calib_to); 413 callout_drain(&sc->watchdog_to); 414 ieee80211_ifdetach(&sc->sc_ic); 415 mbufq_drain(&sc->sc_snd); 416 } 417 418 /* Uninstall interrupt handler. */ 419 if (sc->irq != NULL) { 420 bus_teardown_intr(dev, sc->irq, sc->sc_ih); 421 bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq), 422 sc->irq); 423 pci_release_msi(dev); 424 } 425 426 /* Free Tx/Rx buffers. */ 427 for (i = 0; i < RTWN_NTXQUEUES; i++) 428 rtwn_free_tx_list(sc, i); 429 rtwn_free_rx_list(sc); 430 431 if (sc->mem != NULL) 432 bus_release_resource(dev, SYS_RES_MEMORY, 433 rman_get_rid(sc->mem), sc->mem); 434 435 RTWN_LOCK_DESTROY(sc); 436 return (0); 437 } 438 439 static int 440 rtwn_shutdown(device_t dev) 441 { 442 443 return (0); 444 } 445 446 static int 447 rtwn_suspend(device_t dev) 448 { 449 return (0); 450 } 451 452 static int 453 rtwn_resume(device_t dev) 454 { 455 456 return (0); 457 } 458 459 static void 460 rtwn_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 461 { 462 463 if (error != 0) 464 return; 465 KASSERT(nsegs == 1, ("too many DMA segments, %d should be 1", nsegs)); 466 *(bus_addr_t *)arg = segs[0].ds_addr; 467 } 468 469 static void 470 rtwn_setup_rx_desc(struct rtwn_softc *sc, struct r92c_rx_desc *desc, 471 bus_addr_t addr, size_t len, int idx) 472 { 473 474 memset(desc, 0, sizeof(*desc)); 475 desc->rxdw0 = htole32(SM(R92C_RXDW0_PKTLEN, len) | 476 ((idx == RTWN_RX_LIST_COUNT - 1) ? R92C_RXDW0_EOR : 0)); 477 desc->rxbufaddr = htole32(addr); 478 bus_space_barrier(sc->sc_st, sc->sc_sh, 0, sc->sc_mapsize, 479 BUS_SPACE_BARRIER_WRITE); 480 desc->rxdw0 |= htole32(R92C_RXDW0_OWN); 481 } 482 483 static int 484 rtwn_alloc_rx_list(struct rtwn_softc *sc) 485 { 486 struct rtwn_rx_ring *rx_ring = &sc->rx_ring; 487 struct rtwn_rx_data *rx_data; 488 bus_size_t size; 489 int i, error; 490 491 /* Allocate Rx descriptors. */ 492 size = sizeof(struct r92c_rx_desc) * RTWN_RX_LIST_COUNT; 493 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 494 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 495 size, 1, size, 0, NULL, NULL, &rx_ring->desc_dmat); 496 if (error != 0) { 497 device_printf(sc->sc_dev, "could not create rx desc DMA tag\n"); 498 goto fail; 499 } 500 501 error = bus_dmamem_alloc(rx_ring->desc_dmat, (void **)&rx_ring->desc, 502 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 503 &rx_ring->desc_map); 504 if (error != 0) { 505 device_printf(sc->sc_dev, "could not allocate rx desc\n"); 506 goto fail; 507 } 508 error = bus_dmamap_load(rx_ring->desc_dmat, rx_ring->desc_map, 509 rx_ring->desc, size, rtwn_dma_map_addr, &rx_ring->paddr, 0); 510 if (error != 0) { 511 device_printf(sc->sc_dev, "could not load rx desc DMA map\n"); 512 goto fail; 513 } 514 bus_dmamap_sync(rx_ring->desc_dmat, rx_ring->desc_map, 515 BUS_DMASYNC_PREWRITE); 516 517 /* Create RX buffer DMA tag. */ 518 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 519 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 520 1, MCLBYTES, 0, NULL, NULL, &rx_ring->data_dmat); 521 if (error != 0) { 522 device_printf(sc->sc_dev, "could not create rx buf DMA tag\n"); 523 goto fail; 524 } 525 526 /* Allocate Rx buffers. */ 527 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 528 rx_data = &rx_ring->rx_data[i]; 529 error = bus_dmamap_create(rx_ring->data_dmat, 0, &rx_data->map); 530 if (error != 0) { 531 device_printf(sc->sc_dev, 532 "could not create rx buf DMA map\n"); 533 goto fail; 534 } 535 536 rx_data->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 537 if (rx_data->m == NULL) { 538 device_printf(sc->sc_dev, 539 "could not allocate rx mbuf\n"); 540 error = ENOMEM; 541 goto fail; 542 } 543 544 error = bus_dmamap_load(rx_ring->data_dmat, rx_data->map, 545 mtod(rx_data->m, void *), MCLBYTES, rtwn_dma_map_addr, 546 &rx_data->paddr, BUS_DMA_NOWAIT); 547 if (error != 0) { 548 device_printf(sc->sc_dev, 549 "could not load rx buf DMA map"); 550 goto fail; 551 } 552 553 rtwn_setup_rx_desc(sc, &rx_ring->desc[i], rx_data->paddr, 554 MCLBYTES, i); 555 } 556 return (0); 557 558 fail: 559 rtwn_free_rx_list(sc); 560 return (error); 561 } 562 563 static void 564 rtwn_reset_rx_list(struct rtwn_softc *sc) 565 { 566 struct rtwn_rx_ring *rx_ring = &sc->rx_ring; 567 struct rtwn_rx_data *rx_data; 568 int i; 569 570 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 571 rx_data = &rx_ring->rx_data[i]; 572 rtwn_setup_rx_desc(sc, &rx_ring->desc[i], rx_data->paddr, 573 MCLBYTES, i); 574 } 575 } 576 577 static void 578 rtwn_free_rx_list(struct rtwn_softc *sc) 579 { 580 struct rtwn_rx_ring *rx_ring = &sc->rx_ring; 581 struct rtwn_rx_data *rx_data; 582 int i; 583 584 if (rx_ring->desc_dmat != NULL) { 585 if (rx_ring->desc != NULL) { 586 bus_dmamap_unload(rx_ring->desc_dmat, 587 rx_ring->desc_map); 588 bus_dmamem_free(rx_ring->desc_dmat, rx_ring->desc, 589 rx_ring->desc_map); 590 rx_ring->desc = NULL; 591 } 592 bus_dma_tag_destroy(rx_ring->desc_dmat); 593 rx_ring->desc_dmat = NULL; 594 } 595 596 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 597 rx_data = &rx_ring->rx_data[i]; 598 599 if (rx_data->m != NULL) { 600 bus_dmamap_unload(rx_ring->data_dmat, rx_data->map); 601 m_freem(rx_data->m); 602 rx_data->m = NULL; 603 } 604 bus_dmamap_destroy(rx_ring->data_dmat, rx_data->map); 605 rx_data->map = NULL; 606 } 607 if (rx_ring->data_dmat != NULL) { 608 bus_dma_tag_destroy(rx_ring->data_dmat); 609 rx_ring->data_dmat = NULL; 610 } 611 } 612 613 static int 614 rtwn_alloc_tx_list(struct rtwn_softc *sc, int qid) 615 { 616 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 617 struct rtwn_tx_data *tx_data; 618 bus_size_t size; 619 int i, error; 620 621 size = sizeof(struct r92c_tx_desc) * RTWN_TX_LIST_COUNT; 622 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), PAGE_SIZE, 0, 623 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 624 size, 1, size, 0, NULL, NULL, &tx_ring->desc_dmat); 625 if (error != 0) { 626 device_printf(sc->sc_dev, "could not create tx ring DMA tag\n"); 627 goto fail; 628 } 629 630 error = bus_dmamem_alloc(tx_ring->desc_dmat, (void **)&tx_ring->desc, 631 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &tx_ring->desc_map); 632 if (error != 0) { 633 device_printf(sc->sc_dev, "can't map tx ring DMA memory\n"); 634 goto fail; 635 } 636 error = bus_dmamap_load(tx_ring->desc_dmat, tx_ring->desc_map, 637 tx_ring->desc, size, rtwn_dma_map_addr, &tx_ring->paddr, 638 BUS_DMA_NOWAIT); 639 if (error != 0) { 640 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 641 goto fail; 642 } 643 644 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 645 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 646 1, MCLBYTES, 0, NULL, NULL, &tx_ring->data_dmat); 647 if (error != 0) { 648 device_printf(sc->sc_dev, "could not create tx buf DMA tag\n"); 649 goto fail; 650 } 651 652 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 653 struct r92c_tx_desc *desc = &tx_ring->desc[i]; 654 655 /* setup tx desc */ 656 desc->nextdescaddr = htole32(tx_ring->paddr + 657 + sizeof(struct r92c_tx_desc) 658 * ((i + 1) % RTWN_TX_LIST_COUNT)); 659 tx_data = &tx_ring->tx_data[i]; 660 error = bus_dmamap_create(tx_ring->data_dmat, 0, &tx_data->map); 661 if (error != 0) { 662 device_printf(sc->sc_dev, 663 "could not create tx buf DMA map\n"); 664 goto fail; 665 } 666 tx_data->m = NULL; 667 tx_data->ni = NULL; 668 } 669 return (0); 670 671 fail: 672 rtwn_free_tx_list(sc, qid); 673 return (error); 674 } 675 676 static void 677 rtwn_reset_tx_list(struct rtwn_softc *sc, int qid) 678 { 679 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 680 int i; 681 682 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 683 struct r92c_tx_desc *desc = &tx_ring->desc[i]; 684 struct rtwn_tx_data *tx_data = &tx_ring->tx_data[i]; 685 686 memset(desc, 0, sizeof(*desc) - 687 (sizeof(desc->reserved) + sizeof(desc->nextdescaddr64) + 688 sizeof(desc->nextdescaddr))); 689 690 if (tx_data->m != NULL) { 691 bus_dmamap_unload(tx_ring->data_dmat, tx_data->map); 692 m_freem(tx_data->m); 693 tx_data->m = NULL; 694 } 695 if (tx_data->ni != NULL) { 696 ieee80211_free_node(tx_data->ni); 697 tx_data->ni = NULL; 698 } 699 } 700 701 bus_dmamap_sync(tx_ring->desc_dmat, tx_ring->desc_map, 702 BUS_DMASYNC_POSTWRITE); 703 704 sc->qfullmsk &= ~(1 << qid); 705 tx_ring->queued = 0; 706 tx_ring->cur = 0; 707 } 708 709 static void 710 rtwn_free_tx_list(struct rtwn_softc *sc, int qid) 711 { 712 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 713 struct rtwn_tx_data *tx_data; 714 int i; 715 716 if (tx_ring->desc_dmat != NULL) { 717 if (tx_ring->desc != NULL) { 718 bus_dmamap_unload(tx_ring->desc_dmat, 719 tx_ring->desc_map); 720 bus_dmamem_free(tx_ring->desc_dmat, tx_ring->desc, 721 tx_ring->desc_map); 722 } 723 bus_dma_tag_destroy(tx_ring->desc_dmat); 724 } 725 726 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 727 tx_data = &tx_ring->tx_data[i]; 728 729 if (tx_data->m != NULL) { 730 bus_dmamap_unload(tx_ring->data_dmat, tx_data->map); 731 m_freem(tx_data->m); 732 tx_data->m = NULL; 733 } 734 } 735 if (tx_ring->data_dmat != NULL) { 736 bus_dma_tag_destroy(tx_ring->data_dmat); 737 tx_ring->data_dmat = NULL; 738 } 739 740 sc->qfullmsk &= ~(1 << qid); 741 tx_ring->queued = 0; 742 tx_ring->cur = 0; 743 } 744 745 746 static struct ieee80211vap * 747 rtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 748 enum ieee80211_opmode opmode, int flags, 749 const uint8_t bssid[IEEE80211_ADDR_LEN], 750 const uint8_t mac[IEEE80211_ADDR_LEN]) 751 { 752 struct rtwn_vap *rvp; 753 struct ieee80211vap *vap; 754 755 if (!TAILQ_EMPTY(&ic->ic_vaps)) 756 return (NULL); 757 758 rvp = malloc(sizeof(struct rtwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); 759 vap = &rvp->vap; 760 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 761 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 762 /* out of memory */ 763 free(rvp, M_80211_VAP); 764 return (NULL); 765 } 766 767 /* Override state transition machine. */ 768 rvp->newstate = vap->iv_newstate; 769 vap->iv_newstate = rtwn_newstate; 770 771 /* Complete setup. */ 772 ieee80211_vap_attach(vap, ieee80211_media_change, 773 ieee80211_media_status, mac); 774 ic->ic_opmode = opmode; 775 return (vap); 776 } 777 778 static void 779 rtwn_vap_delete(struct ieee80211vap *vap) 780 { 781 struct rtwn_vap *rvp = RTWN_VAP(vap); 782 783 ieee80211_vap_detach(vap); 784 free(rvp, M_80211_VAP); 785 } 786 787 static void 788 rtwn_write_1(struct rtwn_softc *sc, uint16_t addr, uint8_t val) 789 { 790 791 bus_space_write_1(sc->sc_st, sc->sc_sh, addr, val); 792 } 793 794 static void 795 rtwn_write_2(struct rtwn_softc *sc, uint16_t addr, uint16_t val) 796 { 797 798 val = htole16(val); 799 bus_space_write_2(sc->sc_st, sc->sc_sh, addr, val); 800 } 801 802 static void 803 rtwn_write_4(struct rtwn_softc *sc, uint16_t addr, uint32_t val) 804 { 805 806 val = htole32(val); 807 bus_space_write_4(sc->sc_st, sc->sc_sh, addr, val); 808 } 809 810 static uint8_t 811 rtwn_read_1(struct rtwn_softc *sc, uint16_t addr) 812 { 813 814 return (bus_space_read_1(sc->sc_st, sc->sc_sh, addr)); 815 } 816 817 static uint16_t 818 rtwn_read_2(struct rtwn_softc *sc, uint16_t addr) 819 { 820 821 return (bus_space_read_2(sc->sc_st, sc->sc_sh, addr)); 822 } 823 824 static uint32_t 825 rtwn_read_4(struct rtwn_softc *sc, uint16_t addr) 826 { 827 828 return (bus_space_read_4(sc->sc_st, sc->sc_sh, addr)); 829 } 830 831 static int 832 rtwn_fw_cmd(struct rtwn_softc *sc, uint8_t id, const void *buf, int len) 833 { 834 struct r92c_fw_cmd cmd; 835 int ntries; 836 837 /* Wait for current FW box to be empty. */ 838 for (ntries = 0; ntries < 100; ntries++) { 839 if (!(rtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 840 break; 841 DELAY(1); 842 } 843 if (ntries == 100) { 844 device_printf(sc->sc_dev, 845 "could not send firmware command %d\n", id); 846 return (ETIMEDOUT); 847 } 848 memset(&cmd, 0, sizeof(cmd)); 849 cmd.id = id; 850 if (len > 3) 851 cmd.id |= R92C_CMD_FLAG_EXT; 852 KASSERT(len <= sizeof(cmd.msg), ("rtwn_fw_cmd\n")); 853 memcpy(cmd.msg, buf, len); 854 855 /* Write the first word last since that will trigger the FW. */ 856 rtwn_write_2(sc, R92C_HMEBOX_EXT(sc->fwcur), *((uint8_t *)&cmd + 4)); 857 rtwn_write_4(sc, R92C_HMEBOX(sc->fwcur), *((uint8_t *)&cmd + 0)); 858 859 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 860 861 /* Give firmware some time for processing. */ 862 DELAY(2000); 863 864 return (0); 865 } 866 867 static void 868 rtwn_rf_write(struct rtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 869 { 870 rtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 871 SM(R92C_LSSI_PARAM_ADDR, addr) | 872 SM(R92C_LSSI_PARAM_DATA, val)); 873 } 874 875 static uint32_t 876 rtwn_rf_read(struct rtwn_softc *sc, int chain, uint8_t addr) 877 { 878 uint32_t reg[R92C_MAX_CHAINS], val; 879 880 reg[0] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 881 if (chain != 0) 882 reg[chain] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 883 884 rtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 885 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 886 DELAY(1000); 887 888 rtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 889 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 890 R92C_HSSI_PARAM2_READ_EDGE); 891 DELAY(1000); 892 893 rtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 894 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 895 DELAY(1000); 896 897 if (rtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 898 val = rtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 899 else 900 val = rtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 901 return (MS(val, R92C_LSSI_READBACK_DATA)); 902 } 903 904 static int 905 rtwn_llt_write(struct rtwn_softc *sc, uint32_t addr, uint32_t data) 906 { 907 int ntries; 908 909 rtwn_write_4(sc, R92C_LLT_INIT, 910 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 911 SM(R92C_LLT_INIT_ADDR, addr) | 912 SM(R92C_LLT_INIT_DATA, data)); 913 /* Wait for write operation to complete. */ 914 for (ntries = 0; ntries < 20; ntries++) { 915 if (MS(rtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 916 R92C_LLT_INIT_OP_NO_ACTIVE) 917 return (0); 918 DELAY(5); 919 } 920 return (ETIMEDOUT); 921 } 922 923 static uint8_t 924 rtwn_efuse_read_1(struct rtwn_softc *sc, uint16_t addr) 925 { 926 uint32_t reg; 927 int ntries; 928 929 reg = rtwn_read_4(sc, R92C_EFUSE_CTRL); 930 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 931 reg &= ~R92C_EFUSE_CTRL_VALID; 932 rtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 933 /* Wait for read operation to complete. */ 934 for (ntries = 0; ntries < 100; ntries++) { 935 reg = rtwn_read_4(sc, R92C_EFUSE_CTRL); 936 if (reg & R92C_EFUSE_CTRL_VALID) 937 return (MS(reg, R92C_EFUSE_CTRL_DATA)); 938 DELAY(5); 939 } 940 device_printf(sc->sc_dev, 941 "could not read efuse byte at address 0x%x\n", addr); 942 return (0xff); 943 } 944 945 static void 946 rtwn_efuse_read(struct rtwn_softc *sc) 947 { 948 uint8_t *rom = (uint8_t *)&sc->rom; 949 uint16_t addr = 0; 950 uint32_t reg; 951 uint8_t off, msk; 952 int i; 953 954 reg = rtwn_read_2(sc, R92C_SYS_ISO_CTRL); 955 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 956 rtwn_write_2(sc, R92C_SYS_ISO_CTRL, 957 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 958 } 959 reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN); 960 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 961 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 962 reg | R92C_SYS_FUNC_EN_ELDR); 963 } 964 reg = rtwn_read_2(sc, R92C_SYS_CLKR); 965 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 966 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 967 rtwn_write_2(sc, R92C_SYS_CLKR, 968 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 969 } 970 memset(&sc->rom, 0xff, sizeof(sc->rom)); 971 while (addr < 512) { 972 reg = rtwn_efuse_read_1(sc, addr); 973 if (reg == 0xff) 974 break; 975 addr++; 976 off = reg >> 4; 977 msk = reg & 0xf; 978 for (i = 0; i < 4; i++) { 979 if (msk & (1 << i)) 980 continue; 981 rom[off * 8 + i * 2 + 0] = 982 rtwn_efuse_read_1(sc, addr); 983 addr++; 984 rom[off * 8 + i * 2 + 1] = 985 rtwn_efuse_read_1(sc, addr); 986 addr++; 987 } 988 } 989 #ifdef RTWN_DEBUG 990 if (sc->sc_debug >= 2) { 991 /* Dump ROM content. */ 992 printf("\n"); 993 for (i = 0; i < sizeof(sc->rom); i++) 994 printf("%02x:", rom[i]); 995 printf("\n"); 996 } 997 #endif 998 } 999 1000 static int 1001 rtwn_read_chipid(struct rtwn_softc *sc) 1002 { 1003 uint32_t reg; 1004 1005 reg = rtwn_read_4(sc, R92C_SYS_CFG); 1006 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 1007 /* Unsupported test chip. */ 1008 return (EIO); 1009 1010 if (reg & R92C_SYS_CFG_TYPE_92C) { 1011 sc->chip |= RTWN_CHIP_92C; 1012 /* Check if it is a castrated 8192C. */ 1013 if (MS(rtwn_read_4(sc, R92C_HPON_FSM), 1014 R92C_HPON_FSM_CHIP_BONDING_ID) == 1015 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 1016 sc->chip |= RTWN_CHIP_92C_1T2R; 1017 } 1018 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1019 sc->chip |= RTWN_CHIP_UMC; 1020 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 1021 sc->chip |= RTWN_CHIP_UMC_A_CUT; 1022 } 1023 return (0); 1024 } 1025 1026 static void 1027 rtwn_read_rom(struct rtwn_softc *sc) 1028 { 1029 struct r92c_rom *rom = &sc->rom; 1030 1031 /* Read full ROM image. */ 1032 rtwn_efuse_read(sc); 1033 1034 if (rom->id != 0x8129) 1035 device_printf(sc->sc_dev, "invalid EEPROM ID 0x%x\n", rom->id); 1036 1037 /* XXX Weird but this is what the vendor driver does. */ 1038 sc->pa_setting = rtwn_efuse_read_1(sc, 0x1fa); 1039 DPRINTF(("PA setting=0x%x\n", sc->pa_setting)); 1040 1041 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1042 1043 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1044 DPRINTF(("regulatory type=%d\n", sc->regulatory)); 1045 1046 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr); 1047 } 1048 1049 /* 1050 * Initialize rate adaptation in firmware. 1051 */ 1052 static int 1053 rtwn_ra_init(struct rtwn_softc *sc) 1054 { 1055 static const uint8_t map[] = 1056 { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 }; 1057 struct ieee80211com *ic = &sc->sc_ic; 1058 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1059 struct ieee80211_node *ni = ieee80211_ref_node(vap->iv_bss); 1060 struct ieee80211_rateset *rs = &ni->ni_rates; 1061 struct r92c_fw_cmd_macid_cfg cmd; 1062 uint32_t rates, basicrates; 1063 uint8_t mode; 1064 int maxrate, maxbasicrate, error, i, j; 1065 1066 /* Get normal and basic rates mask. */ 1067 rates = basicrates = 0; 1068 maxrate = maxbasicrate = 0; 1069 for (i = 0; i < rs->rs_nrates; i++) { 1070 /* Convert 802.11 rate to HW rate index. */ 1071 for (j = 0; j < nitems(map); j++) 1072 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) 1073 break; 1074 if (j == nitems(map)) /* Unknown rate, skip. */ 1075 continue; 1076 rates |= 1 << j; 1077 if (j > maxrate) 1078 maxrate = j; 1079 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1080 basicrates |= 1 << j; 1081 if (j > maxbasicrate) 1082 maxbasicrate = j; 1083 } 1084 } 1085 if (ic->ic_curmode == IEEE80211_MODE_11B) 1086 mode = R92C_RAID_11B; 1087 else 1088 mode = R92C_RAID_11BG; 1089 DPRINTF(("mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 1090 mode, rates, basicrates)); 1091 1092 /* Set rates mask for group addressed frames. */ 1093 cmd.macid = RTWN_MACID_BC | RTWN_MACID_VALID; 1094 cmd.mask = htole32(mode << 28 | basicrates); 1095 error = rtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1096 if (error != 0) { 1097 device_printf(sc->sc_dev, 1098 "could not add broadcast station\n"); 1099 return (error); 1100 } 1101 /* Set initial MRR rate. */ 1102 DPRINTF(("maxbasicrate=%d\n", maxbasicrate)); 1103 rtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BC), 1104 maxbasicrate); 1105 1106 /* Set rates mask for unicast frames. */ 1107 cmd.macid = RTWN_MACID_BSS | RTWN_MACID_VALID; 1108 cmd.mask = htole32(mode << 28 | rates); 1109 error = rtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1110 if (error != 0) { 1111 device_printf(sc->sc_dev, "could not add BSS station\n"); 1112 return (error); 1113 } 1114 /* Set initial MRR rate. */ 1115 DPRINTF(("maxrate=%d\n", maxrate)); 1116 rtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BSS), 1117 maxrate); 1118 1119 /* Configure Automatic Rate Fallback Register. */ 1120 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1121 if (rates & 0x0c) 1122 rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0d)); 1123 else 1124 rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0f)); 1125 } else 1126 rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0ff5)); 1127 1128 /* Indicate highest supported rate. */ 1129 ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1]; 1130 return (0); 1131 } 1132 1133 static void 1134 rtwn_tsf_sync_enable(struct rtwn_softc *sc) 1135 { 1136 struct ieee80211com *ic = &sc->sc_ic; 1137 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1138 struct ieee80211_node *ni = vap->iv_bss; 1139 uint64_t tsf; 1140 1141 /* Enable TSF synchronization. */ 1142 rtwn_write_1(sc, R92C_BCN_CTRL, 1143 rtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1144 1145 rtwn_write_1(sc, R92C_BCN_CTRL, 1146 rtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1147 1148 /* Set initial TSF. */ 1149 memcpy(&tsf, ni->ni_tstamp.data, 8); 1150 tsf = le64toh(tsf); 1151 tsf = tsf - (tsf % (vap->iv_bss->ni_intval * IEEE80211_DUR_TU)); 1152 tsf -= IEEE80211_DUR_TU; 1153 rtwn_write_4(sc, R92C_TSFTR + 0, tsf); 1154 rtwn_write_4(sc, R92C_TSFTR + 4, tsf >> 32); 1155 1156 rtwn_write_1(sc, R92C_BCN_CTRL, 1157 rtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1158 } 1159 1160 static void 1161 rtwn_set_led(struct rtwn_softc *sc, int led, int on) 1162 { 1163 uint8_t reg; 1164 1165 if (led == RTWN_LED_LINK) { 1166 reg = rtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1167 if (!on) 1168 reg |= R92C_LEDCFG2_DIS; 1169 else 1170 reg |= R92C_LEDCFG2_EN; 1171 rtwn_write_1(sc, R92C_LEDCFG2, reg); 1172 sc->ledlink = on; /* Save LED state. */ 1173 } 1174 } 1175 1176 static void 1177 rtwn_calib_to(void *arg) 1178 { 1179 struct rtwn_softc *sc = arg; 1180 struct r92c_fw_cmd_rssi cmd; 1181 1182 if (sc->avg_pwdb != -1) { 1183 /* Indicate Rx signal strength to FW for rate adaptation. */ 1184 memset(&cmd, 0, sizeof(cmd)); 1185 cmd.macid = 0; /* BSS. */ 1186 cmd.pwdb = sc->avg_pwdb; 1187 DPRINTFN(3, ("sending RSSI command avg=%d\n", sc->avg_pwdb)); 1188 rtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, sizeof(cmd)); 1189 } 1190 1191 /* Do temperature compensation. */ 1192 rtwn_temp_calib(sc); 1193 1194 callout_reset(&sc->calib_to, hz * 2, rtwn_calib_to, sc); 1195 } 1196 1197 static int 1198 rtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1199 { 1200 struct rtwn_vap *rvp = RTWN_VAP(vap); 1201 struct ieee80211com *ic = vap->iv_ic; 1202 struct ieee80211_node *ni = vap->iv_bss; 1203 struct rtwn_softc *sc = ic->ic_softc; 1204 uint32_t reg; 1205 1206 IEEE80211_UNLOCK(ic); 1207 RTWN_LOCK(sc); 1208 1209 if (vap->iv_state == IEEE80211_S_RUN) { 1210 /* Stop calibration. */ 1211 callout_stop(&sc->calib_to); 1212 1213 /* Turn link LED off. */ 1214 rtwn_set_led(sc, RTWN_LED_LINK, 0); 1215 1216 /* Set media status to 'No Link'. */ 1217 reg = rtwn_read_4(sc, R92C_CR); 1218 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_NOLINK); 1219 rtwn_write_4(sc, R92C_CR, reg); 1220 1221 /* Stop Rx of data frames. */ 1222 rtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1223 1224 /* Rest TSF. */ 1225 rtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1226 1227 /* Disable TSF synchronization. */ 1228 rtwn_write_1(sc, R92C_BCN_CTRL, 1229 rtwn_read_1(sc, R92C_BCN_CTRL) | 1230 R92C_BCN_CTRL_DIS_TSF_UDT0); 1231 1232 /* Reset EDCA parameters. */ 1233 rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1234 rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1235 rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1236 rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1237 } 1238 switch (nstate) { 1239 case IEEE80211_S_INIT: 1240 /* Turn link LED off. */ 1241 rtwn_set_led(sc, RTWN_LED_LINK, 0); 1242 break; 1243 case IEEE80211_S_SCAN: 1244 if (vap->iv_state != IEEE80211_S_SCAN) { 1245 /* Allow Rx from any BSSID. */ 1246 rtwn_write_4(sc, R92C_RCR, 1247 rtwn_read_4(sc, R92C_RCR) & 1248 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1249 1250 /* Set gain for scanning. */ 1251 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1252 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1253 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1254 1255 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1256 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1257 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1258 } 1259 1260 /* Make link LED blink during scan. */ 1261 rtwn_set_led(sc, RTWN_LED_LINK, !sc->ledlink); 1262 1263 /* Pause AC Tx queues. */ 1264 rtwn_write_1(sc, R92C_TXPAUSE, 1265 rtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1266 break; 1267 case IEEE80211_S_AUTH: 1268 /* Set initial gain under link. */ 1269 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1270 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1271 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1272 1273 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1274 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1275 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1276 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1277 break; 1278 case IEEE80211_S_RUN: 1279 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1280 /* Enable Rx of data frames. */ 1281 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1282 1283 /* Turn link LED on. */ 1284 rtwn_set_led(sc, RTWN_LED_LINK, 1); 1285 break; 1286 } 1287 1288 /* Set media status to 'Associated'. */ 1289 reg = rtwn_read_4(sc, R92C_CR); 1290 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 1291 rtwn_write_4(sc, R92C_CR, reg); 1292 1293 /* Set BSSID. */ 1294 rtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1295 rtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1296 1297 if (ic->ic_curmode == IEEE80211_MODE_11B) 1298 rtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1299 else /* 802.11b/g */ 1300 rtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1301 1302 /* Enable Rx of data frames. */ 1303 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1304 1305 /* Flush all AC queues. */ 1306 rtwn_write_1(sc, R92C_TXPAUSE, 0); 1307 1308 /* Set beacon interval. */ 1309 rtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1310 1311 /* Allow Rx from our BSSID only. */ 1312 rtwn_write_4(sc, R92C_RCR, 1313 rtwn_read_4(sc, R92C_RCR) | 1314 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1315 1316 /* Enable TSF synchronization. */ 1317 rtwn_tsf_sync_enable(sc); 1318 1319 rtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 1320 rtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 1321 rtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 1322 rtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 1323 rtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 1324 rtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 1325 1326 /* Intialize rate adaptation. */ 1327 rtwn_ra_init(sc); 1328 /* Turn link LED on. */ 1329 rtwn_set_led(sc, RTWN_LED_LINK, 1); 1330 1331 sc->avg_pwdb = -1; /* Reset average RSSI. */ 1332 /* Reset temperature calibration state machine. */ 1333 sc->thcal_state = 0; 1334 sc->thcal_lctemp = 0; 1335 /* Start periodic calibration. */ 1336 callout_reset(&sc->calib_to, hz * 2, rtwn_calib_to, sc); 1337 break; 1338 default: 1339 break; 1340 } 1341 RTWN_UNLOCK(sc); 1342 IEEE80211_LOCK(ic); 1343 return (rvp->newstate(vap, nstate, arg)); 1344 } 1345 1346 static int 1347 rtwn_updateedca(struct ieee80211com *ic) 1348 { 1349 struct rtwn_softc *sc = ic->ic_softc; 1350 const uint16_t aci2reg[WME_NUM_AC] = { 1351 R92C_EDCA_BE_PARAM, 1352 R92C_EDCA_BK_PARAM, 1353 R92C_EDCA_VI_PARAM, 1354 R92C_EDCA_VO_PARAM 1355 }; 1356 int aci, aifs, slottime; 1357 1358 IEEE80211_LOCK(ic); 1359 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 1360 for (aci = 0; aci < WME_NUM_AC; aci++) { 1361 const struct wmeParams *ac = 1362 &ic->ic_wme.wme_chanParams.cap_wmeParams[aci]; 1363 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 1364 aifs = ac->wmep_aifsn * slottime + 10; 1365 rtwn_write_4(sc, aci2reg[aci], 1366 SM(R92C_EDCA_PARAM_TXOP, ac->wmep_txopLimit) | 1367 SM(R92C_EDCA_PARAM_ECWMIN, ac->wmep_logcwmin) | 1368 SM(R92C_EDCA_PARAM_ECWMAX, ac->wmep_logcwmax) | 1369 SM(R92C_EDCA_PARAM_AIFS, aifs)); 1370 } 1371 IEEE80211_UNLOCK(ic); 1372 return (0); 1373 } 1374 1375 static void 1376 rtwn_update_avgrssi(struct rtwn_softc *sc, int rate, int8_t rssi) 1377 { 1378 int pwdb; 1379 1380 /* Convert antenna signal to percentage. */ 1381 if (rssi <= -100 || rssi >= 20) 1382 pwdb = 0; 1383 else if (rssi >= 0) 1384 pwdb = 100; 1385 else 1386 pwdb = 100 + rssi; 1387 if (rate <= 3) { 1388 /* CCK gain is smaller than OFDM/MCS gain. */ 1389 pwdb += 6; 1390 if (pwdb > 100) 1391 pwdb = 100; 1392 if (pwdb <= 14) 1393 pwdb -= 4; 1394 else if (pwdb <= 26) 1395 pwdb -= 8; 1396 else if (pwdb <= 34) 1397 pwdb -= 6; 1398 else if (pwdb <= 42) 1399 pwdb -= 2; 1400 } 1401 if (sc->avg_pwdb == -1) /* Init. */ 1402 sc->avg_pwdb = pwdb; 1403 else if (sc->avg_pwdb < pwdb) 1404 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 1405 else 1406 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 1407 DPRINTFN(4, ("PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb)); 1408 } 1409 1410 static int8_t 1411 rtwn_get_rssi(struct rtwn_softc *sc, int rate, void *physt) 1412 { 1413 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 1414 struct r92c_rx_phystat *phy; 1415 struct r92c_rx_cck *cck; 1416 uint8_t rpt; 1417 int8_t rssi; 1418 1419 if (rate <= 3) { 1420 cck = (struct r92c_rx_cck *)physt; 1421 if (sc->sc_flags & RTWN_FLAG_CCK_HIPWR) { 1422 rpt = (cck->agc_rpt >> 5) & 0x3; 1423 rssi = (cck->agc_rpt & 0x1f) << 1; 1424 } else { 1425 rpt = (cck->agc_rpt >> 6) & 0x3; 1426 rssi = cck->agc_rpt & 0x3e; 1427 } 1428 rssi = cckoff[rpt] - rssi; 1429 } else { /* OFDM/HT. */ 1430 phy = (struct r92c_rx_phystat *)physt; 1431 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1432 } 1433 return (rssi); 1434 } 1435 1436 static void 1437 rtwn_rx_frame(struct rtwn_softc *sc, struct r92c_rx_desc *rx_desc, 1438 struct rtwn_rx_data *rx_data, int desc_idx) 1439 { 1440 struct ieee80211com *ic = &sc->sc_ic; 1441 struct ieee80211_frame_min *wh; 1442 struct ieee80211_node *ni; 1443 struct r92c_rx_phystat *phy = NULL; 1444 uint32_t rxdw0, rxdw3; 1445 struct mbuf *m, *m1; 1446 bus_dma_segment_t segs[1]; 1447 bus_addr_t physaddr; 1448 uint8_t rate; 1449 int8_t rssi = 0, nf; 1450 int infosz, nsegs, pktlen, shift, error; 1451 1452 rxdw0 = le32toh(rx_desc->rxdw0); 1453 rxdw3 = le32toh(rx_desc->rxdw3); 1454 1455 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 1456 /* 1457 * This should not happen since we setup our Rx filter 1458 * to not receive these frames. 1459 */ 1460 counter_u64_add(ic->ic_ierrors, 1); 1461 return; 1462 } 1463 1464 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 1465 if (__predict_false(pktlen < sizeof(struct ieee80211_frame_ack) || 1466 pktlen > MCLBYTES)) { 1467 counter_u64_add(ic->ic_ierrors, 1); 1468 return; 1469 } 1470 1471 rate = MS(rxdw3, R92C_RXDW3_RATE); 1472 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1473 if (infosz > sizeof(struct r92c_rx_phystat)) 1474 infosz = sizeof(struct r92c_rx_phystat); 1475 shift = MS(rxdw0, R92C_RXDW0_SHIFT); 1476 1477 /* Get RSSI from PHY status descriptor if present. */ 1478 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 1479 phy = mtod(rx_data->m, struct r92c_rx_phystat *); 1480 rssi = rtwn_get_rssi(sc, rate, phy); 1481 /* Update our average RSSI. */ 1482 rtwn_update_avgrssi(sc, rate, rssi); 1483 } 1484 1485 DPRINTFN(5, ("Rx frame len=%d rate=%d infosz=%d shift=%d rssi=%d\n", 1486 pktlen, rate, infosz, shift, rssi)); 1487 1488 m1 = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1489 if (m1 == NULL) { 1490 counter_u64_add(ic->ic_ierrors, 1); 1491 return; 1492 } 1493 bus_dmamap_unload(sc->rx_ring.data_dmat, rx_data->map); 1494 1495 error = bus_dmamap_load(sc->rx_ring.data_dmat, rx_data->map, 1496 mtod(m1, void *), MCLBYTES, rtwn_dma_map_addr, 1497 &physaddr, 0); 1498 if (error != 0) { 1499 m_freem(m1); 1500 1501 if (bus_dmamap_load_mbuf_sg(sc->rx_ring.data_dmat, 1502 rx_data->map, rx_data->m, segs, &nsegs, 0)) 1503 panic("%s: could not load old RX mbuf", 1504 device_get_name(sc->sc_dev)); 1505 1506 /* Physical address may have changed. */ 1507 rtwn_setup_rx_desc(sc, rx_desc, physaddr, MCLBYTES, desc_idx); 1508 counter_u64_add(ic->ic_ierrors, 1); 1509 return; 1510 } 1511 1512 /* Finalize mbuf. */ 1513 m = rx_data->m; 1514 rx_data->m = m1; 1515 m->m_pkthdr.len = m->m_len = pktlen + infosz + shift; 1516 1517 /* Update RX descriptor. */ 1518 rtwn_setup_rx_desc(sc, rx_desc, physaddr, MCLBYTES, desc_idx); 1519 1520 /* Get ieee80211 frame header. */ 1521 if (rxdw0 & R92C_RXDW0_PHYST) 1522 m_adj(m, infosz + shift); 1523 else 1524 m_adj(m, shift); 1525 1526 nf = -95; 1527 if (ieee80211_radiotap_active(ic)) { 1528 struct rtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 1529 1530 tap->wr_flags = 0; 1531 if (!(rxdw3 & R92C_RXDW3_HT)) { 1532 switch (rate) { 1533 /* CCK. */ 1534 case 0: tap->wr_rate = 2; break; 1535 case 1: tap->wr_rate = 4; break; 1536 case 2: tap->wr_rate = 11; break; 1537 case 3: tap->wr_rate = 22; break; 1538 /* OFDM. */ 1539 case 4: tap->wr_rate = 12; break; 1540 case 5: tap->wr_rate = 18; break; 1541 case 6: tap->wr_rate = 24; break; 1542 case 7: tap->wr_rate = 36; break; 1543 case 8: tap->wr_rate = 48; break; 1544 case 9: tap->wr_rate = 72; break; 1545 case 10: tap->wr_rate = 96; break; 1546 case 11: tap->wr_rate = 108; break; 1547 } 1548 } else if (rate >= 12) { /* MCS0~15. */ 1549 /* Bit 7 set means HT MCS instead of rate. */ 1550 tap->wr_rate = 0x80 | (rate - 12); 1551 } 1552 tap->wr_dbm_antsignal = rssi; 1553 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 1554 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 1555 } 1556 1557 RTWN_UNLOCK(sc); 1558 wh = mtod(m, struct ieee80211_frame_min *); 1559 if (m->m_len >= sizeof(*wh)) 1560 ni = ieee80211_find_rxnode(ic, wh); 1561 else 1562 ni = NULL; 1563 1564 /* Send the frame to the 802.11 layer. */ 1565 if (ni != NULL) { 1566 (void)ieee80211_input(ni, m, rssi - nf, nf); 1567 /* Node is no longer needed. */ 1568 ieee80211_free_node(ni); 1569 } else 1570 (void)ieee80211_input_all(ic, m, rssi - nf, nf); 1571 1572 RTWN_LOCK(sc); 1573 } 1574 1575 static int 1576 rtwn_tx(struct rtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 1577 { 1578 struct ieee80211com *ic = &sc->sc_ic; 1579 struct ieee80211vap *vap = ni->ni_vap; 1580 struct ieee80211_frame *wh; 1581 struct ieee80211_key *k = NULL; 1582 struct rtwn_tx_ring *tx_ring; 1583 struct rtwn_tx_data *data; 1584 struct r92c_tx_desc *txd; 1585 bus_dma_segment_t segs[1]; 1586 uint16_t qos; 1587 uint8_t raid, type, tid, qid; 1588 int nsegs, error; 1589 1590 wh = mtod(m, struct ieee80211_frame *); 1591 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1592 1593 /* Encrypt the frame if need be. */ 1594 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1595 k = ieee80211_crypto_encap(ni, m); 1596 if (k == NULL) { 1597 m_freem(m); 1598 return (ENOBUFS); 1599 } 1600 /* 802.11 header may have moved. */ 1601 wh = mtod(m, struct ieee80211_frame *); 1602 } 1603 1604 if (IEEE80211_QOS_HAS_SEQ(wh)) { 1605 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 1606 tid = qos & IEEE80211_QOS_TID; 1607 } else { 1608 qos = 0; 1609 tid = 0; 1610 } 1611 1612 switch (type) { 1613 case IEEE80211_FC0_TYPE_CTL: 1614 case IEEE80211_FC0_TYPE_MGT: 1615 qid = RTWN_VO_QUEUE; 1616 break; 1617 default: 1618 qid = M_WME_GETAC(m); 1619 break; 1620 } 1621 1622 /* Grab a Tx buffer from the ring. */ 1623 tx_ring = &sc->tx_ring[qid]; 1624 data = &tx_ring->tx_data[tx_ring->cur]; 1625 if (data->m != NULL) { 1626 m_freem(m); 1627 return (ENOBUFS); 1628 } 1629 1630 /* Fill Tx descriptor. */ 1631 txd = &tx_ring->desc[tx_ring->cur]; 1632 if (htole32(txd->txdw0) & R92C_RXDW0_OWN) { 1633 m_freem(m); 1634 return (ENOBUFS); 1635 } 1636 txd->txdw0 = htole32( 1637 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 1638 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1639 R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1640 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1641 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1642 1643 txd->txdw1 = 0; 1644 txd->txdw4 = 0; 1645 txd->txdw5 = 0; 1646 1647 /* XXX TODO: rate control; implement low-rate for EAPOL */ 1648 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1649 type == IEEE80211_FC0_TYPE_DATA) { 1650 if (ic->ic_curmode == IEEE80211_MODE_11B) 1651 raid = R92C_RAID_11B; 1652 else 1653 raid = R92C_RAID_11BG; 1654 txd->txdw1 |= htole32( 1655 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 1656 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1657 SM(R92C_TXDW1_RAID, raid) | 1658 R92C_TXDW1_AGGBK); 1659 1660 if (ic->ic_flags & IEEE80211_F_USEPROT) { 1661 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1662 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1663 R92C_TXDW4_HWRTSEN); 1664 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1665 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1666 R92C_TXDW4_HWRTSEN); 1667 } 1668 } 1669 1670 /* XXX TODO: implement rate control */ 1671 1672 /* Send RTS at OFDM24. */ 1673 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 1674 txd->txdw5 |= htole32(SM(R92C_TXDW5_RTSRATE_FBLIMIT, 0xf)); 1675 /* Send data at OFDM54. */ 1676 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 1677 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE_FBLIMIT, 0x1f)); 1678 1679 } else { 1680 txd->txdw1 |= htole32( 1681 SM(R92C_TXDW1_MACID, 0) | 1682 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1683 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1684 1685 /* Force CCK1. */ 1686 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1687 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 1688 } 1689 /* Set sequence number (already little endian). */ 1690 txd->txdseq = htole16(M_SEQNO_GET(m) % IEEE80211_SEQ_RANGE); 1691 1692 if (!qos) { 1693 /* Use HW sequence numbering for non-QoS frames. */ 1694 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 1695 txd->txdseq |= htole16(0x8000); 1696 } else 1697 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 1698 1699 error = bus_dmamap_load_mbuf_sg(tx_ring->data_dmat, data->map, m, segs, 1700 &nsegs, BUS_DMA_NOWAIT); 1701 if (error != 0 && error != EFBIG) { 1702 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", error); 1703 m_freem(m); 1704 return (error); 1705 } 1706 if (error != 0) { 1707 struct mbuf *mnew; 1708 1709 mnew = m_defrag(m, M_NOWAIT); 1710 if (mnew == NULL) { 1711 device_printf(sc->sc_dev, 1712 "can't defragment mbuf\n"); 1713 m_freem(m); 1714 return (ENOBUFS); 1715 } 1716 m = mnew; 1717 1718 error = bus_dmamap_load_mbuf_sg(tx_ring->data_dmat, data->map, 1719 m, segs, &nsegs, BUS_DMA_NOWAIT); 1720 if (error != 0) { 1721 device_printf(sc->sc_dev, 1722 "can't map mbuf (error %d)\n", error); 1723 m_freem(m); 1724 return (error); 1725 } 1726 } 1727 1728 txd->txbufaddr = htole32(segs[0].ds_addr); 1729 txd->txbufsize = htole16(m->m_pkthdr.len); 1730 bus_space_barrier(sc->sc_st, sc->sc_sh, 0, sc->sc_mapsize, 1731 BUS_SPACE_BARRIER_WRITE); 1732 txd->txdw0 |= htole32(R92C_TXDW0_OWN); 1733 1734 bus_dmamap_sync(tx_ring->desc_dmat, tx_ring->desc_map, 1735 BUS_DMASYNC_POSTWRITE); 1736 bus_dmamap_sync(tx_ring->data_dmat, data->map, BUS_DMASYNC_POSTWRITE); 1737 1738 data->m = m; 1739 data->ni = ni; 1740 1741 if (ieee80211_radiotap_active_vap(vap)) { 1742 struct rtwn_tx_radiotap_header *tap = &sc->sc_txtap; 1743 1744 tap->wt_flags = 0; 1745 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1746 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1747 1748 ieee80211_radiotap_tx(vap, m); 1749 } 1750 1751 tx_ring->cur = (tx_ring->cur + 1) % RTWN_TX_LIST_COUNT; 1752 tx_ring->queued++; 1753 1754 if (tx_ring->queued >= (RTWN_TX_LIST_COUNT - 1)) 1755 sc->qfullmsk |= (1 << qid); 1756 1757 /* Kick TX. */ 1758 rtwn_write_2(sc, R92C_PCIE_CTRL_REG, (1 << qid)); 1759 return (0); 1760 } 1761 1762 static void 1763 rtwn_tx_done(struct rtwn_softc *sc, int qid) 1764 { 1765 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 1766 struct rtwn_tx_data *tx_data; 1767 struct r92c_tx_desc *tx_desc; 1768 int i; 1769 1770 bus_dmamap_sync(tx_ring->desc_dmat, tx_ring->desc_map, 1771 BUS_DMASYNC_POSTREAD); 1772 1773 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 1774 tx_data = &tx_ring->tx_data[i]; 1775 if (tx_data->m == NULL) 1776 continue; 1777 1778 tx_desc = &tx_ring->desc[i]; 1779 if (le32toh(tx_desc->txdw0) & R92C_TXDW0_OWN) 1780 continue; 1781 1782 bus_dmamap_unload(tx_ring->desc_dmat, tx_ring->desc_map); 1783 1784 /* 1785 * XXX TODO: figure out whether the transmit succeeded or not. 1786 * .. and then notify rate control. 1787 */ 1788 ieee80211_tx_complete(tx_data->ni, tx_data->m, 0); 1789 tx_data->ni = NULL; 1790 tx_data->m = NULL; 1791 1792 sc->sc_tx_timer = 0; 1793 tx_ring->queued--; 1794 } 1795 1796 if (tx_ring->queued < (RTWN_TX_LIST_COUNT - 1)) 1797 sc->qfullmsk &= ~(1 << qid); 1798 rtwn_start(sc); 1799 } 1800 1801 static int 1802 rtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1803 const struct ieee80211_bpf_params *params) 1804 { 1805 struct ieee80211com *ic = ni->ni_ic; 1806 struct rtwn_softc *sc = ic->ic_softc; 1807 1808 RTWN_LOCK(sc); 1809 1810 /* Prevent management frames from being sent if we're not ready. */ 1811 if (!(sc->sc_flags & RTWN_RUNNING)) { 1812 RTWN_UNLOCK(sc); 1813 m_freem(m); 1814 return (ENETDOWN); 1815 } 1816 1817 if (rtwn_tx(sc, m, ni) != 0) { 1818 m_freem(m); 1819 RTWN_UNLOCK(sc); 1820 return (EIO); 1821 } 1822 sc->sc_tx_timer = 5; 1823 RTWN_UNLOCK(sc); 1824 return (0); 1825 } 1826 1827 static int 1828 rtwn_transmit(struct ieee80211com *ic, struct mbuf *m) 1829 { 1830 struct rtwn_softc *sc = ic->ic_softc; 1831 int error; 1832 1833 RTWN_LOCK(sc); 1834 if ((sc->sc_flags & RTWN_RUNNING) == 0) { 1835 RTWN_UNLOCK(sc); 1836 return (ENXIO); 1837 } 1838 error = mbufq_enqueue(&sc->sc_snd, m); 1839 if (error) { 1840 RTWN_UNLOCK(sc); 1841 return (error); 1842 } 1843 rtwn_start(sc); 1844 RTWN_UNLOCK(sc); 1845 return (0); 1846 } 1847 1848 static void 1849 rtwn_parent(struct ieee80211com *ic) 1850 { 1851 struct rtwn_softc *sc = ic->ic_softc; 1852 int startall = 0; 1853 1854 RTWN_LOCK(sc); 1855 if (ic->ic_nrunning> 0) { 1856 if (!(sc->sc_flags & RTWN_RUNNING)) { 1857 rtwn_init_locked(sc); 1858 startall = 1; 1859 } 1860 } else if (sc->sc_flags & RTWN_RUNNING) 1861 rtwn_stop_locked(sc); 1862 RTWN_UNLOCK(sc); 1863 if (startall) 1864 ieee80211_start_all(ic); 1865 } 1866 1867 static void 1868 rtwn_start(struct rtwn_softc *sc) 1869 { 1870 struct ieee80211_node *ni; 1871 struct mbuf *m; 1872 1873 RTWN_LOCK_ASSERT(sc); 1874 1875 if ((sc->sc_flags & RTWN_RUNNING) == 0) 1876 return; 1877 1878 while (sc->qfullmsk == 0 && (m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1879 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1880 if (rtwn_tx(sc, m, ni) != 0) { 1881 if_inc_counter(ni->ni_vap->iv_ifp, 1882 IFCOUNTER_OERRORS, 1); 1883 ieee80211_free_node(ni); 1884 continue; 1885 } 1886 sc->sc_tx_timer = 5; 1887 } 1888 } 1889 1890 static void 1891 rtwn_watchdog(void *arg) 1892 { 1893 struct rtwn_softc *sc = arg; 1894 struct ieee80211com *ic = &sc->sc_ic; 1895 1896 RTWN_LOCK_ASSERT(sc); 1897 1898 KASSERT(sc->sc_flags & RTWN_RUNNING, ("not running")); 1899 1900 if (sc->sc_tx_timer != 0 && --sc->sc_tx_timer == 0) { 1901 ic_printf(ic, "device timeout\n"); 1902 ieee80211_runtask(ic, &sc->sc_reinit_task); 1903 return; 1904 } 1905 callout_reset(&sc->watchdog_to, hz, rtwn_watchdog, sc); 1906 } 1907 1908 static int 1909 rtwn_power_on(struct rtwn_softc *sc) 1910 { 1911 uint32_t reg; 1912 int ntries; 1913 1914 /* Wait for autoload done bit. */ 1915 for (ntries = 0; ntries < 1000; ntries++) { 1916 if (rtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 1917 break; 1918 DELAY(5); 1919 } 1920 if (ntries == 1000) { 1921 device_printf(sc->sc_dev, 1922 "timeout waiting for chip autoload\n"); 1923 return (ETIMEDOUT); 1924 } 1925 1926 /* Unlock ISO/CLK/Power control register. */ 1927 rtwn_write_1(sc, R92C_RSV_CTRL, 0); 1928 1929 /* TODO: check if we need this for 8188CE */ 1930 if (sc->board_type != R92C_BOARD_TYPE_DONGLE) { 1931 /* bt coex */ 1932 reg = rtwn_read_4(sc, R92C_APS_FSMCO); 1933 reg |= (R92C_APS_FSMCO_SOP_ABG | 1934 R92C_APS_FSMCO_SOP_AMB | 1935 R92C_APS_FSMCO_XOP_BTCK); 1936 rtwn_write_4(sc, R92C_APS_FSMCO, reg); 1937 } 1938 1939 /* Move SPS into PWM mode. */ 1940 rtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 1941 1942 /* Set low byte to 0x0f, leave others unchanged. */ 1943 rtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 1944 (rtwn_read_4(sc, R92C_AFE_XTAL_CTRL) & 0xffffff00) | 0x0f); 1945 1946 /* TODO: check if we need this for 8188CE */ 1947 if (sc->board_type != R92C_BOARD_TYPE_DONGLE) { 1948 /* bt coex */ 1949 reg = rtwn_read_4(sc, R92C_AFE_XTAL_CTRL); 1950 reg &= (~0x00024800); /* XXX magic from linux */ 1951 rtwn_write_4(sc, R92C_AFE_XTAL_CTRL, reg); 1952 } 1953 1954 rtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1955 (rtwn_read_2(sc, R92C_SYS_ISO_CTRL) & 0xff) | 1956 R92C_SYS_ISO_CTRL_PWC_EV12V | R92C_SYS_ISO_CTRL_DIOR); 1957 DELAY(200); 1958 1959 /* TODO: linux does additional btcoex stuff here */ 1960 1961 /* Auto enable WLAN. */ 1962 rtwn_write_2(sc, R92C_APS_FSMCO, 1963 rtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 1964 for (ntries = 0; ntries < 1000; ntries++) { 1965 if (!(rtwn_read_2(sc, R92C_APS_FSMCO) & 1966 R92C_APS_FSMCO_APFM_ONMAC)) 1967 break; 1968 DELAY(5); 1969 } 1970 if (ntries == 1000) { 1971 device_printf(sc->sc_dev, "timeout waiting for MAC auto ON\n"); 1972 return (ETIMEDOUT); 1973 } 1974 1975 /* Enable radio, GPIO and LED functions. */ 1976 rtwn_write_2(sc, R92C_APS_FSMCO, 1977 R92C_APS_FSMCO_AFSM_PCIE | 1978 R92C_APS_FSMCO_PDN_EN | 1979 R92C_APS_FSMCO_PFM_ALDN); 1980 /* Release RF digital isolation. */ 1981 rtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1982 rtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 1983 1984 if (sc->chip & RTWN_CHIP_92C) 1985 rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 3, 0x77); 1986 else 1987 rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 3, 0x22); 1988 1989 rtwn_write_4(sc, R92C_INT_MIG, 0); 1990 1991 if (sc->board_type != R92C_BOARD_TYPE_DONGLE) { 1992 /* bt coex */ 1993 reg = rtwn_read_4(sc, R92C_AFE_XTAL_CTRL + 2); 1994 reg &= 0xfd; /* XXX magic from linux */ 1995 rtwn_write_4(sc, R92C_AFE_XTAL_CTRL + 2, reg); 1996 } 1997 1998 rtwn_write_1(sc, R92C_GPIO_MUXCFG, 1999 rtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_RFKILL); 2000 2001 reg = rtwn_read_1(sc, R92C_GPIO_IO_SEL); 2002 if (!(reg & R92C_GPIO_IO_SEL_RFKILL)) { 2003 device_printf(sc->sc_dev, 2004 "radio is disabled by hardware switch\n"); 2005 return (EPERM); 2006 } 2007 2008 /* Initialize MAC. */ 2009 reg = rtwn_read_1(sc, R92C_APSD_CTRL); 2010 rtwn_write_1(sc, R92C_APSD_CTRL, 2011 rtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2012 for (ntries = 0; ntries < 200; ntries++) { 2013 if (!(rtwn_read_1(sc, R92C_APSD_CTRL) & 2014 R92C_APSD_CTRL_OFF_STATUS)) 2015 break; 2016 DELAY(500); 2017 } 2018 if (ntries == 200) { 2019 device_printf(sc->sc_dev, 2020 "timeout waiting for MAC initialization\n"); 2021 return (ETIMEDOUT); 2022 } 2023 2024 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2025 reg = rtwn_read_2(sc, R92C_CR); 2026 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2027 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2028 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2029 R92C_CR_ENSEC; 2030 rtwn_write_2(sc, R92C_CR, reg); 2031 2032 rtwn_write_1(sc, 0xfe10, 0x19); 2033 2034 return (0); 2035 } 2036 2037 static int 2038 rtwn_llt_init(struct rtwn_softc *sc) 2039 { 2040 int i, error; 2041 2042 /* Reserve pages [0; R92C_TX_PAGE_COUNT]. */ 2043 for (i = 0; i < R92C_TX_PAGE_COUNT; i++) { 2044 if ((error = rtwn_llt_write(sc, i, i + 1)) != 0) 2045 return (error); 2046 } 2047 /* NB: 0xff indicates end-of-list. */ 2048 if ((error = rtwn_llt_write(sc, i, 0xff)) != 0) 2049 return (error); 2050 /* 2051 * Use pages [R92C_TX_PAGE_COUNT + 1; R92C_TXPKTBUF_COUNT - 1] 2052 * as ring buffer. 2053 */ 2054 for (++i; i < R92C_TXPKTBUF_COUNT - 1; i++) { 2055 if ((error = rtwn_llt_write(sc, i, i + 1)) != 0) 2056 return (error); 2057 } 2058 /* Make the last page point to the beginning of the ring buffer. */ 2059 error = rtwn_llt_write(sc, i, R92C_TX_PAGE_COUNT + 1); 2060 return (error); 2061 } 2062 2063 static void 2064 rtwn_fw_reset(struct rtwn_softc *sc) 2065 { 2066 uint16_t reg; 2067 int ntries; 2068 2069 /* Tell 8051 to reset itself. */ 2070 rtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 2071 2072 /* Wait until 8051 resets by itself. */ 2073 for (ntries = 0; ntries < 100; ntries++) { 2074 reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN); 2075 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 2076 goto sleep; 2077 DELAY(50); 2078 } 2079 /* Force 8051 reset. */ 2080 rtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2081 sleep: 2082 /* 2083 * We must sleep for one second to let the firmware settle. 2084 * Accessing registers too early will hang the whole system. 2085 */ 2086 if (msleep(®, &sc->sc_mtx, 0, "rtwnrst", hz)) { 2087 device_printf(sc->sc_dev, "timeout waiting for firmware " 2088 "initialization to complete\n"); 2089 } 2090 } 2091 2092 static void 2093 rtwn_fw_loadpage(struct rtwn_softc *sc, int page, const uint8_t *buf, int len) 2094 { 2095 uint32_t reg; 2096 int off, mlen, i; 2097 2098 reg = rtwn_read_4(sc, R92C_MCUFWDL); 2099 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2100 rtwn_write_4(sc, R92C_MCUFWDL, reg); 2101 2102 DELAY(5); 2103 2104 off = R92C_FW_START_ADDR; 2105 while (len > 0) { 2106 if (len > 196) 2107 mlen = 196; 2108 else if (len > 4) 2109 mlen = 4; 2110 else 2111 mlen = 1; 2112 for (i = 0; i < mlen; i++) 2113 rtwn_write_1(sc, off++, buf[i]); 2114 buf += mlen; 2115 len -= mlen; 2116 } 2117 } 2118 2119 static int 2120 rtwn_load_firmware(struct rtwn_softc *sc) 2121 { 2122 const struct firmware *fw; 2123 const struct r92c_fw_hdr *hdr; 2124 const char *name; 2125 const u_char *ptr; 2126 size_t len; 2127 uint32_t reg; 2128 int mlen, ntries, page, error = 0; 2129 2130 /* Read firmware image from the filesystem. */ 2131 if ((sc->chip & (RTWN_CHIP_UMC_A_CUT | RTWN_CHIP_92C)) == 2132 RTWN_CHIP_UMC_A_CUT) 2133 name = "rtwn-rtl8192cfwU"; 2134 else 2135 name = "rtwn-rtl8192cfwU_B"; 2136 RTWN_UNLOCK(sc); 2137 fw = firmware_get(name); 2138 RTWN_LOCK(sc); 2139 if (fw == NULL) { 2140 device_printf(sc->sc_dev, 2141 "could not read firmware %s\n", name); 2142 return (ENOENT); 2143 } 2144 len = fw->datasize; 2145 if (len < sizeof(*hdr)) { 2146 device_printf(sc->sc_dev, "firmware too short\n"); 2147 error = EINVAL; 2148 goto fail; 2149 } 2150 ptr = fw->data; 2151 hdr = (const struct r92c_fw_hdr *)ptr; 2152 /* Check if there is a valid FW header and skip it. */ 2153 if ((le16toh(hdr->signature) >> 4) == 0x88c || 2154 (le16toh(hdr->signature) >> 4) == 0x92c) { 2155 DPRINTF(("FW V%d.%d %02d-%02d %02d:%02d\n", 2156 le16toh(hdr->version), le16toh(hdr->subversion), 2157 hdr->month, hdr->date, hdr->hour, hdr->minute)); 2158 ptr += sizeof(*hdr); 2159 len -= sizeof(*hdr); 2160 } 2161 2162 if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) 2163 rtwn_fw_reset(sc); 2164 2165 /* Enable FW download. */ 2166 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 2167 rtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2168 R92C_SYS_FUNC_EN_CPUEN); 2169 rtwn_write_1(sc, R92C_MCUFWDL, 2170 rtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 2171 rtwn_write_1(sc, R92C_MCUFWDL + 2, 2172 rtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 2173 2174 /* Reset the FWDL checksum. */ 2175 rtwn_write_1(sc, R92C_MCUFWDL, 2176 rtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 2177 2178 for (page = 0; len > 0; page++) { 2179 mlen = MIN(len, R92C_FW_PAGE_SIZE); 2180 rtwn_fw_loadpage(sc, page, ptr, mlen); 2181 ptr += mlen; 2182 len -= mlen; 2183 } 2184 2185 /* Disable FW download. */ 2186 rtwn_write_1(sc, R92C_MCUFWDL, 2187 rtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 2188 rtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 2189 2190 /* Wait for checksum report. */ 2191 for (ntries = 0; ntries < 1000; ntries++) { 2192 if (rtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 2193 break; 2194 DELAY(5); 2195 } 2196 if (ntries == 1000) { 2197 device_printf(sc->sc_dev, 2198 "timeout waiting for checksum report\n"); 2199 error = ETIMEDOUT; 2200 goto fail; 2201 } 2202 2203 reg = rtwn_read_4(sc, R92C_MCUFWDL); 2204 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 2205 rtwn_write_4(sc, R92C_MCUFWDL, reg); 2206 /* Wait for firmware readiness. */ 2207 for (ntries = 0; ntries < 2000; ntries++) { 2208 if (rtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 2209 break; 2210 DELAY(50); 2211 } 2212 if (ntries == 1000) { 2213 device_printf(sc->sc_dev, 2214 "timeout waiting for firmware readiness\n"); 2215 error = ETIMEDOUT; 2216 goto fail; 2217 } 2218 fail: 2219 firmware_put(fw, FIRMWARE_UNLOAD); 2220 return (error); 2221 } 2222 2223 static int 2224 rtwn_dma_init(struct rtwn_softc *sc) 2225 { 2226 uint32_t reg; 2227 int error; 2228 2229 /* Initialize LLT table. */ 2230 error = rtwn_llt_init(sc); 2231 if (error != 0) 2232 return error; 2233 2234 /* Set number of pages for normal priority queue. */ 2235 rtwn_write_2(sc, R92C_RQPN_NPQ, 0); 2236 rtwn_write_4(sc, R92C_RQPN, 2237 /* Set number of pages for public queue. */ 2238 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 2239 /* Set number of pages for high priority queue. */ 2240 SM(R92C_RQPN_HPQ, R92C_HPQ_NPAGES) | 2241 /* Set number of pages for low priority queue. */ 2242 SM(R92C_RQPN_LPQ, R92C_LPQ_NPAGES) | 2243 /* Load values. */ 2244 R92C_RQPN_LD); 2245 2246 rtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2247 rtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2248 rtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 2249 rtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 2250 rtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 2251 2252 reg = rtwn_read_2(sc, R92C_TRXDMA_CTRL); 2253 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2254 reg |= 0xF771; 2255 rtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2256 2257 rtwn_write_4(sc, R92C_TCR, R92C_TCR_CFENDFORM | (1 << 12) | (1 << 13)); 2258 2259 /* Configure Tx DMA. */ 2260 rtwn_write_4(sc, R92C_BKQ_DESA, sc->tx_ring[RTWN_BK_QUEUE].paddr); 2261 rtwn_write_4(sc, R92C_BEQ_DESA, sc->tx_ring[RTWN_BE_QUEUE].paddr); 2262 rtwn_write_4(sc, R92C_VIQ_DESA, sc->tx_ring[RTWN_VI_QUEUE].paddr); 2263 rtwn_write_4(sc, R92C_VOQ_DESA, sc->tx_ring[RTWN_VO_QUEUE].paddr); 2264 rtwn_write_4(sc, R92C_BCNQ_DESA, sc->tx_ring[RTWN_BEACON_QUEUE].paddr); 2265 rtwn_write_4(sc, R92C_MGQ_DESA, sc->tx_ring[RTWN_MGNT_QUEUE].paddr); 2266 rtwn_write_4(sc, R92C_HQ_DESA, sc->tx_ring[RTWN_HIGH_QUEUE].paddr); 2267 2268 /* Configure Rx DMA. */ 2269 rtwn_write_4(sc, R92C_RX_DESA, sc->rx_ring.paddr); 2270 2271 /* Set Tx/Rx transfer page boundary. */ 2272 rtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 2273 2274 /* Set Tx/Rx transfer page size. */ 2275 rtwn_write_1(sc, R92C_PBP, 2276 SM(R92C_PBP_PSRX, R92C_PBP_128) | 2277 SM(R92C_PBP_PSTX, R92C_PBP_128)); 2278 return (0); 2279 } 2280 2281 static void 2282 rtwn_mac_init(struct rtwn_softc *sc) 2283 { 2284 int i; 2285 2286 /* Write MAC initialization values. */ 2287 for (i = 0; i < nitems(rtl8192ce_mac); i++) 2288 rtwn_write_1(sc, rtl8192ce_mac[i].reg, rtl8192ce_mac[i].val); 2289 } 2290 2291 static void 2292 rtwn_bb_init(struct rtwn_softc *sc) 2293 { 2294 const struct rtwn_bb_prog *prog; 2295 uint32_t reg; 2296 int i; 2297 2298 /* Enable BB and RF. */ 2299 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 2300 rtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2301 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2302 R92C_SYS_FUNC_EN_DIO_RF); 2303 2304 rtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 2305 2306 rtwn_write_1(sc, R92C_RF_CTRL, 2307 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2308 2309 rtwn_write_1(sc, R92C_SYS_FUNC_EN, 2310 R92C_SYS_FUNC_EN_DIO_PCIE | R92C_SYS_FUNC_EN_PCIEA | 2311 R92C_SYS_FUNC_EN_PPLL | R92C_SYS_FUNC_EN_BB_GLB_RST | 2312 R92C_SYS_FUNC_EN_BBRSTB); 2313 2314 rtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2315 2316 rtwn_write_4(sc, R92C_LEDCFG0, 2317 rtwn_read_4(sc, R92C_LEDCFG0) | 0x00800000); 2318 2319 /* Select BB programming. */ 2320 prog = (sc->chip & RTWN_CHIP_92C) ? 2321 &rtl8192ce_bb_prog_2t : &rtl8192ce_bb_prog_1t; 2322 2323 /* Write BB initialization values. */ 2324 for (i = 0; i < prog->count; i++) { 2325 rtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2326 DELAY(1); 2327 } 2328 2329 if (sc->chip & RTWN_CHIP_92C_1T2R) { 2330 /* 8192C 1T only configuration. */ 2331 reg = rtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2332 reg = (reg & ~0x00000003) | 0x2; 2333 rtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2334 2335 reg = rtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2336 reg = (reg & ~0x00300033) | 0x00200022; 2337 rtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2338 2339 reg = rtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2340 reg = (reg & ~0xff000000) | 0x45 << 24; 2341 rtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2342 2343 reg = rtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2344 reg = (reg & ~0x000000ff) | 0x23; 2345 rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2346 2347 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2348 reg = (reg & ~0x00000030) | 1 << 4; 2349 rtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2350 2351 reg = rtwn_bb_read(sc, 0xe74); 2352 reg = (reg & ~0x0c000000) | 2 << 26; 2353 rtwn_bb_write(sc, 0xe74, reg); 2354 reg = rtwn_bb_read(sc, 0xe78); 2355 reg = (reg & ~0x0c000000) | 2 << 26; 2356 rtwn_bb_write(sc, 0xe78, reg); 2357 reg = rtwn_bb_read(sc, 0xe7c); 2358 reg = (reg & ~0x0c000000) | 2 << 26; 2359 rtwn_bb_write(sc, 0xe7c, reg); 2360 reg = rtwn_bb_read(sc, 0xe80); 2361 reg = (reg & ~0x0c000000) | 2 << 26; 2362 rtwn_bb_write(sc, 0xe80, reg); 2363 reg = rtwn_bb_read(sc, 0xe88); 2364 reg = (reg & ~0x0c000000) | 2 << 26; 2365 rtwn_bb_write(sc, 0xe88, reg); 2366 } 2367 2368 /* Write AGC values. */ 2369 for (i = 0; i < prog->agccount; i++) { 2370 rtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 2371 prog->agcvals[i]); 2372 DELAY(1); 2373 } 2374 2375 if (rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 2376 R92C_HSSI_PARAM2_CCK_HIPWR) 2377 sc->sc_flags |= RTWN_FLAG_CCK_HIPWR; 2378 } 2379 2380 static void 2381 rtwn_rf_init(struct rtwn_softc *sc) 2382 { 2383 const struct rtwn_rf_prog *prog; 2384 uint32_t reg, type; 2385 int i, j, idx, off; 2386 2387 /* Select RF programming based on board type. */ 2388 if (!(sc->chip & RTWN_CHIP_92C)) { 2389 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2390 prog = rtl8188ce_rf_prog; 2391 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2392 prog = rtl8188ru_rf_prog; 2393 else 2394 prog = rtl8188cu_rf_prog; 2395 } else 2396 prog = rtl8192ce_rf_prog; 2397 2398 for (i = 0; i < sc->nrxchains; i++) { 2399 /* Save RF_ENV control type. */ 2400 idx = i / 2; 2401 off = (i % 2) * 16; 2402 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2403 type = (reg >> off) & 0x10; 2404 2405 /* Set RF_ENV enable. */ 2406 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2407 reg |= 0x100000; 2408 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2409 DELAY(1); 2410 /* Set RF_ENV output high. */ 2411 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2412 reg |= 0x10; 2413 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2414 DELAY(1); 2415 /* Set address and data lengths of RF registers. */ 2416 reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2417 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 2418 rtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2419 DELAY(1); 2420 reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2421 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 2422 rtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2423 DELAY(1); 2424 2425 /* Write RF initialization values for this chain. */ 2426 for (j = 0; j < prog[i].count; j++) { 2427 if (prog[i].regs[j] >= 0xf9 && 2428 prog[i].regs[j] <= 0xfe) { 2429 /* 2430 * These are fake RF registers offsets that 2431 * indicate a delay is required. 2432 */ 2433 DELAY(50); 2434 continue; 2435 } 2436 rtwn_rf_write(sc, i, prog[i].regs[j], 2437 prog[i].vals[j]); 2438 DELAY(1); 2439 } 2440 2441 /* Restore RF_ENV control type. */ 2442 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2443 reg &= ~(0x10 << off) | (type << off); 2444 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 2445 2446 /* Cache RF register CHNLBW. */ 2447 sc->rf_chnlbw[i] = rtwn_rf_read(sc, i, R92C_RF_CHNLBW); 2448 } 2449 2450 if ((sc->chip & (RTWN_CHIP_UMC_A_CUT | RTWN_CHIP_92C)) == 2451 RTWN_CHIP_UMC_A_CUT) { 2452 rtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 2453 rtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 2454 } 2455 } 2456 2457 static void 2458 rtwn_cam_init(struct rtwn_softc *sc) 2459 { 2460 /* Invalidate all CAM entries. */ 2461 rtwn_write_4(sc, R92C_CAMCMD, 2462 R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 2463 } 2464 2465 static void 2466 rtwn_pa_bias_init(struct rtwn_softc *sc) 2467 { 2468 uint8_t reg; 2469 int i; 2470 2471 for (i = 0; i < sc->nrxchains; i++) { 2472 if (sc->pa_setting & (1 << i)) 2473 continue; 2474 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 2475 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 2476 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 2477 rtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 2478 } 2479 if (!(sc->pa_setting & 0x10)) { 2480 reg = rtwn_read_1(sc, 0x16); 2481 reg = (reg & ~0xf0) | 0x90; 2482 rtwn_write_1(sc, 0x16, reg); 2483 } 2484 } 2485 2486 static void 2487 rtwn_rxfilter_init(struct rtwn_softc *sc) 2488 { 2489 /* Initialize Rx filter. */ 2490 /* TODO: use better filter for monitor mode. */ 2491 rtwn_write_4(sc, R92C_RCR, 2492 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 2493 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 2494 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 2495 /* Accept all multicast frames. */ 2496 rtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 2497 rtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 2498 /* Accept all management frames. */ 2499 rtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 2500 /* Reject all control frames. */ 2501 rtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 2502 /* Accept all data frames. */ 2503 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2504 } 2505 2506 static void 2507 rtwn_edca_init(struct rtwn_softc *sc) 2508 { 2509 2510 rtwn_write_2(sc, R92C_SPEC_SIFS, 0x1010); 2511 rtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x1010); 2512 rtwn_write_2(sc, R92C_SIFS_CCK, 0x1010); 2513 rtwn_write_2(sc, R92C_SIFS_OFDM, 0x0e0e); 2514 rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 2515 rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 2516 rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4322); 2517 rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3222); 2518 } 2519 2520 static void 2521 rtwn_write_txpower(struct rtwn_softc *sc, int chain, 2522 uint16_t power[RTWN_RIDX_COUNT]) 2523 { 2524 uint32_t reg; 2525 2526 /* Write per-CCK rate Tx power. */ 2527 if (chain == 0) { 2528 reg = rtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 2529 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 2530 rtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 2531 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2532 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 2533 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 2534 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 2535 rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2536 } else { 2537 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 2538 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 2539 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 2540 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 2541 rtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 2542 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2543 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 2544 rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2545 } 2546 /* Write per-OFDM rate Tx power. */ 2547 rtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 2548 SM(R92C_TXAGC_RATE06, power[ 4]) | 2549 SM(R92C_TXAGC_RATE09, power[ 5]) | 2550 SM(R92C_TXAGC_RATE12, power[ 6]) | 2551 SM(R92C_TXAGC_RATE18, power[ 7])); 2552 rtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 2553 SM(R92C_TXAGC_RATE24, power[ 8]) | 2554 SM(R92C_TXAGC_RATE36, power[ 9]) | 2555 SM(R92C_TXAGC_RATE48, power[10]) | 2556 SM(R92C_TXAGC_RATE54, power[11])); 2557 /* Write per-MCS Tx power. */ 2558 rtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 2559 SM(R92C_TXAGC_MCS00, power[12]) | 2560 SM(R92C_TXAGC_MCS01, power[13]) | 2561 SM(R92C_TXAGC_MCS02, power[14]) | 2562 SM(R92C_TXAGC_MCS03, power[15])); 2563 rtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 2564 SM(R92C_TXAGC_MCS04, power[16]) | 2565 SM(R92C_TXAGC_MCS05, power[17]) | 2566 SM(R92C_TXAGC_MCS06, power[18]) | 2567 SM(R92C_TXAGC_MCS07, power[19])); 2568 rtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 2569 SM(R92C_TXAGC_MCS08, power[20]) | 2570 SM(R92C_TXAGC_MCS09, power[21]) | 2571 SM(R92C_TXAGC_MCS10, power[22]) | 2572 SM(R92C_TXAGC_MCS11, power[23])); 2573 rtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 2574 SM(R92C_TXAGC_MCS12, power[24]) | 2575 SM(R92C_TXAGC_MCS13, power[25]) | 2576 SM(R92C_TXAGC_MCS14, power[26]) | 2577 SM(R92C_TXAGC_MCS15, power[27])); 2578 } 2579 2580 static void 2581 rtwn_get_txpower(struct rtwn_softc *sc, int chain, 2582 struct ieee80211_channel *c, struct ieee80211_channel *extc, 2583 uint16_t power[RTWN_RIDX_COUNT]) 2584 { 2585 struct ieee80211com *ic = &sc->sc_ic; 2586 struct r92c_rom *rom = &sc->rom; 2587 uint16_t cckpow, ofdmpow, htpow, diff, max; 2588 const struct rtwn_txpwr *base; 2589 int ridx, chan, group; 2590 2591 /* Determine channel group. */ 2592 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2593 if (chan <= 3) 2594 group = 0; 2595 else if (chan <= 9) 2596 group = 1; 2597 else 2598 group = 2; 2599 2600 /* Get original Tx power based on board type and RF chain. */ 2601 if (!(sc->chip & RTWN_CHIP_92C)) { 2602 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2603 base = &rtl8188ru_txagc[chain]; 2604 else 2605 base = &rtl8192cu_txagc[chain]; 2606 } else 2607 base = &rtl8192cu_txagc[chain]; 2608 2609 memset(power, 0, RTWN_RIDX_COUNT * sizeof(power[0])); 2610 if (sc->regulatory == 0) { 2611 for (ridx = 0; ridx <= 3; ridx++) 2612 power[ridx] = base->pwr[0][ridx]; 2613 } 2614 for (ridx = 4; ridx < RTWN_RIDX_COUNT; ridx++) { 2615 if (sc->regulatory == 3) { 2616 power[ridx] = base->pwr[0][ridx]; 2617 /* Apply vendor limits. */ 2618 if (extc != NULL) 2619 max = rom->ht40_max_pwr[group]; 2620 else 2621 max = rom->ht20_max_pwr[group]; 2622 max = (max >> (chain * 4)) & 0xf; 2623 if (power[ridx] > max) 2624 power[ridx] = max; 2625 } else if (sc->regulatory == 1) { 2626 if (extc == NULL) 2627 power[ridx] = base->pwr[group][ridx]; 2628 } else if (sc->regulatory != 2) 2629 power[ridx] = base->pwr[0][ridx]; 2630 } 2631 2632 /* Compute per-CCK rate Tx power. */ 2633 cckpow = rom->cck_tx_pwr[chain][group]; 2634 for (ridx = 0; ridx <= 3; ridx++) { 2635 power[ridx] += cckpow; 2636 if (power[ridx] > R92C_MAX_TX_PWR) 2637 power[ridx] = R92C_MAX_TX_PWR; 2638 } 2639 2640 htpow = rom->ht40_1s_tx_pwr[chain][group]; 2641 if (sc->ntxchains > 1) { 2642 /* Apply reduction for 2 spatial streams. */ 2643 diff = rom->ht40_2s_tx_pwr_diff[group]; 2644 diff = (diff >> (chain * 4)) & 0xf; 2645 htpow = (htpow > diff) ? htpow - diff : 0; 2646 } 2647 2648 /* Compute per-OFDM rate Tx power. */ 2649 diff = rom->ofdm_tx_pwr_diff[group]; 2650 diff = (diff >> (chain * 4)) & 0xf; 2651 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 2652 for (ridx = 4; ridx <= 11; ridx++) { 2653 power[ridx] += ofdmpow; 2654 if (power[ridx] > R92C_MAX_TX_PWR) 2655 power[ridx] = R92C_MAX_TX_PWR; 2656 } 2657 2658 /* Compute per-MCS Tx power. */ 2659 if (extc == NULL) { 2660 diff = rom->ht20_tx_pwr_diff[group]; 2661 diff = (diff >> (chain * 4)) & 0xf; 2662 htpow += diff; /* HT40->HT20 correction. */ 2663 } 2664 for (ridx = 12; ridx <= 27; ridx++) { 2665 power[ridx] += htpow; 2666 if (power[ridx] > R92C_MAX_TX_PWR) 2667 power[ridx] = R92C_MAX_TX_PWR; 2668 } 2669 #ifdef RTWN_DEBUG 2670 if (sc->sc_debug >= 4) { 2671 /* Dump per-rate Tx power values. */ 2672 printf("Tx power for chain %d:\n", chain); 2673 for (ridx = 0; ridx < RTWN_RIDX_COUNT; ridx++) 2674 printf("Rate %d = %u\n", ridx, power[ridx]); 2675 } 2676 #endif 2677 } 2678 2679 static void 2680 rtwn_set_txpower(struct rtwn_softc *sc, struct ieee80211_channel *c, 2681 struct ieee80211_channel *extc) 2682 { 2683 uint16_t power[RTWN_RIDX_COUNT]; 2684 int i; 2685 2686 for (i = 0; i < sc->ntxchains; i++) { 2687 /* Compute per-rate Tx power values. */ 2688 rtwn_get_txpower(sc, i, c, extc, power); 2689 /* Write per-rate Tx power values to hardware. */ 2690 rtwn_write_txpower(sc, i, power); 2691 } 2692 } 2693 2694 static void 2695 rtwn_scan_start(struct ieee80211com *ic) 2696 { 2697 2698 /* XXX do nothing? */ 2699 } 2700 2701 static void 2702 rtwn_scan_end(struct ieee80211com *ic) 2703 { 2704 2705 /* XXX do nothing? */ 2706 } 2707 2708 static void 2709 rtwn_set_channel(struct ieee80211com *ic) 2710 { 2711 struct rtwn_softc *sc = ic->ic_softc; 2712 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2713 2714 RTWN_LOCK(sc); 2715 if (vap->iv_state == IEEE80211_S_SCAN) { 2716 /* Make link LED blink during scan. */ 2717 rtwn_set_led(sc, RTWN_LED_LINK, !sc->ledlink); 2718 } 2719 rtwn_set_chan(sc, ic->ic_curchan, NULL); 2720 RTWN_UNLOCK(sc); 2721 } 2722 2723 static void 2724 rtwn_update_mcast(struct ieee80211com *ic) 2725 { 2726 2727 /* XXX do nothing? */ 2728 } 2729 2730 static void 2731 rtwn_set_chan(struct rtwn_softc *sc, struct ieee80211_channel *c, 2732 struct ieee80211_channel *extc) 2733 { 2734 struct ieee80211com *ic = &sc->sc_ic; 2735 u_int chan; 2736 int i; 2737 2738 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2739 if (chan == 0 || chan == IEEE80211_CHAN_ANY) { 2740 device_printf(sc->sc_dev, 2741 "%s: invalid channel %x\n", __func__, chan); 2742 return; 2743 } 2744 2745 /* Set Tx power for this new channel. */ 2746 rtwn_set_txpower(sc, c, extc); 2747 2748 for (i = 0; i < sc->nrxchains; i++) { 2749 rtwn_rf_write(sc, i, R92C_RF_CHNLBW, 2750 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 2751 } 2752 #ifndef IEEE80211_NO_HT 2753 if (extc != NULL) { 2754 uint32_t reg; 2755 2756 /* Is secondary channel below or above primary? */ 2757 int prichlo = c->ic_freq < extc->ic_freq; 2758 2759 rtwn_write_1(sc, R92C_BWOPMODE, 2760 rtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 2761 2762 reg = rtwn_read_1(sc, R92C_RRSR + 2); 2763 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 2764 rtwn_write_1(sc, R92C_RRSR + 2, reg); 2765 2766 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, 2767 rtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 2768 rtwn_bb_write(sc, R92C_FPGA1_RFMOD, 2769 rtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 2770 2771 /* Set CCK side band. */ 2772 reg = rtwn_bb_read(sc, R92C_CCK0_SYSTEM); 2773 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 2774 rtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 2775 2776 reg = rtwn_bb_read(sc, R92C_OFDM1_LSTF); 2777 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 2778 rtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 2779 2780 rtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 2781 rtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 2782 ~R92C_FPGA0_ANAPARAM2_CBW20); 2783 2784 reg = rtwn_bb_read(sc, 0x818); 2785 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 2786 rtwn_bb_write(sc, 0x818, reg); 2787 2788 /* Select 40MHz bandwidth. */ 2789 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 2790 (sc->rf_chnlbw[0] & ~0xfff) | chan); 2791 } else 2792 #endif 2793 { 2794 rtwn_write_1(sc, R92C_BWOPMODE, 2795 rtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 2796 2797 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, 2798 rtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 2799 rtwn_bb_write(sc, R92C_FPGA1_RFMOD, 2800 rtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 2801 2802 rtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 2803 rtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 2804 R92C_FPGA0_ANAPARAM2_CBW20); 2805 2806 /* Select 20MHz bandwidth. */ 2807 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 2808 (sc->rf_chnlbw[0] & ~0xfff) | R92C_RF_CHNLBW_BW20 | chan); 2809 } 2810 } 2811 2812 static int 2813 rtwn_iq_calib_chain(struct rtwn_softc *sc, int chain, uint16_t tx[2], 2814 uint16_t rx[2]) 2815 { 2816 uint32_t status; 2817 int offset = chain * 0x20; 2818 2819 if (chain == 0) { /* IQ calibration for chain 0. */ 2820 /* IQ calibration settings for chain 0. */ 2821 rtwn_bb_write(sc, 0xe30, 0x10008c1f); 2822 rtwn_bb_write(sc, 0xe34, 0x10008c1f); 2823 rtwn_bb_write(sc, 0xe38, 0x82140102); 2824 2825 if (sc->ntxchains > 1) { 2826 rtwn_bb_write(sc, 0xe3c, 0x28160202); /* 2T */ 2827 /* IQ calibration settings for chain 1. */ 2828 rtwn_bb_write(sc, 0xe50, 0x10008c22); 2829 rtwn_bb_write(sc, 0xe54, 0x10008c22); 2830 rtwn_bb_write(sc, 0xe58, 0x82140102); 2831 rtwn_bb_write(sc, 0xe5c, 0x28160202); 2832 } else 2833 rtwn_bb_write(sc, 0xe3c, 0x28160502); /* 1T */ 2834 2835 /* LO calibration settings. */ 2836 rtwn_bb_write(sc, 0xe4c, 0x001028d1); 2837 /* We're doing LO and IQ calibration in one shot. */ 2838 rtwn_bb_write(sc, 0xe48, 0xf9000000); 2839 rtwn_bb_write(sc, 0xe48, 0xf8000000); 2840 2841 } else { /* IQ calibration for chain 1. */ 2842 /* We're doing LO and IQ calibration in one shot. */ 2843 rtwn_bb_write(sc, 0xe60, 0x00000002); 2844 rtwn_bb_write(sc, 0xe60, 0x00000000); 2845 } 2846 2847 /* Give LO and IQ calibrations the time to complete. */ 2848 DELAY(1000); 2849 2850 /* Read IQ calibration status. */ 2851 status = rtwn_bb_read(sc, 0xeac); 2852 2853 if (status & (1 << (28 + chain * 3))) 2854 return (0); /* Tx failed. */ 2855 /* Read Tx IQ calibration results. */ 2856 tx[0] = (rtwn_bb_read(sc, 0xe94 + offset) >> 16) & 0x3ff; 2857 tx[1] = (rtwn_bb_read(sc, 0xe9c + offset) >> 16) & 0x3ff; 2858 if (tx[0] == 0x142 || tx[1] == 0x042) 2859 return (0); /* Tx failed. */ 2860 2861 if (status & (1 << (27 + chain * 3))) 2862 return (1); /* Rx failed. */ 2863 /* Read Rx IQ calibration results. */ 2864 rx[0] = (rtwn_bb_read(sc, 0xea4 + offset) >> 16) & 0x3ff; 2865 rx[1] = (rtwn_bb_read(sc, 0xeac + offset) >> 16) & 0x3ff; 2866 if (rx[0] == 0x132 || rx[1] == 0x036) 2867 return (1); /* Rx failed. */ 2868 2869 return (3); /* Both Tx and Rx succeeded. */ 2870 } 2871 2872 static void 2873 rtwn_iq_calib_run(struct rtwn_softc *sc, int n, uint16_t tx[2][2], 2874 uint16_t rx[2][2]) 2875 { 2876 /* Registers to save and restore during IQ calibration. */ 2877 struct iq_cal_regs { 2878 uint32_t adda[16]; 2879 uint8_t txpause; 2880 uint8_t bcn_ctrl; 2881 uint8_t ustime_tsf; 2882 uint32_t gpio_muxcfg; 2883 uint32_t ofdm0_trxpathena; 2884 uint32_t ofdm0_trmuxpar; 2885 uint32_t fpga0_rfifacesw1; 2886 } iq_cal_regs; 2887 static const uint16_t reg_adda[16] = { 2888 0x85c, 0xe6c, 0xe70, 0xe74, 2889 0xe78, 0xe7c, 0xe80, 0xe84, 2890 0xe88, 0xe8c, 0xed0, 0xed4, 2891 0xed8, 0xedc, 0xee0, 0xeec 2892 }; 2893 int i, chain; 2894 uint32_t hssi_param1; 2895 2896 if (n == 0) { 2897 for (i = 0; i < nitems(reg_adda); i++) 2898 iq_cal_regs.adda[i] = rtwn_bb_read(sc, reg_adda[i]); 2899 2900 iq_cal_regs.txpause = rtwn_read_1(sc, R92C_TXPAUSE); 2901 iq_cal_regs.bcn_ctrl = rtwn_read_1(sc, R92C_BCN_CTRL); 2902 iq_cal_regs.ustime_tsf = rtwn_read_1(sc, R92C_USTIME_TSF); 2903 iq_cal_regs.gpio_muxcfg = rtwn_read_4(sc, R92C_GPIO_MUXCFG); 2904 } 2905 2906 if (sc->ntxchains == 1) { 2907 rtwn_bb_write(sc, reg_adda[0], 0x0b1b25a0); 2908 for (i = 1; i < nitems(reg_adda); i++) 2909 rtwn_bb_write(sc, reg_adda[i], 0x0bdb25a0); 2910 } else { 2911 for (i = 0; i < nitems(reg_adda); i++) 2912 rtwn_bb_write(sc, reg_adda[i], 0x04db25a4); 2913 } 2914 2915 hssi_param1 = rtwn_bb_read(sc, R92C_HSSI_PARAM1(0)); 2916 if (!(hssi_param1 & R92C_HSSI_PARAM1_PI)) { 2917 rtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 2918 hssi_param1 | R92C_HSSI_PARAM1_PI); 2919 rtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 2920 hssi_param1 | R92C_HSSI_PARAM1_PI); 2921 } 2922 2923 if (n == 0) { 2924 iq_cal_regs.ofdm0_trxpathena = 2925 rtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2926 iq_cal_regs.ofdm0_trmuxpar = 2927 rtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR); 2928 iq_cal_regs.fpga0_rfifacesw1 = 2929 rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1)); 2930 } 2931 2932 rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, 0x03a05600); 2933 rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, 0x000800e4); 2934 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), 0x22204000); 2935 if (sc->ntxchains > 1) { 2936 rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00010000); 2937 rtwn_bb_write(sc, R92C_LSSI_PARAM(1), 0x00010000); 2938 } 2939 2940 rtwn_write_1(sc, R92C_TXPAUSE, 0x3f); 2941 rtwn_write_1(sc, R92C_BCN_CTRL, iq_cal_regs.bcn_ctrl & ~(0x08)); 2942 rtwn_write_1(sc, R92C_USTIME_TSF, iq_cal_regs.ustime_tsf & ~(0x08)); 2943 rtwn_write_1(sc, R92C_GPIO_MUXCFG, 2944 iq_cal_regs.gpio_muxcfg & ~(0x20)); 2945 2946 rtwn_bb_write(sc, 0x0b68, 0x00080000); 2947 if (sc->ntxchains > 1) 2948 rtwn_bb_write(sc, 0x0b6c, 0x00080000); 2949 2950 rtwn_bb_write(sc, 0x0e28, 0x80800000); 2951 rtwn_bb_write(sc, 0x0e40, 0x01007c00); 2952 rtwn_bb_write(sc, 0x0e44, 0x01004800); 2953 2954 rtwn_bb_write(sc, 0x0b68, 0x00080000); 2955 2956 for (chain = 0; chain < sc->ntxchains; chain++) { 2957 if (chain > 0) { 2958 /* Put chain 0 on standby. */ 2959 rtwn_bb_write(sc, 0x0e28, 0x00); 2960 rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00010000); 2961 rtwn_bb_write(sc, 0x0e28, 0x80800000); 2962 2963 /* Enable chain 1. */ 2964 for (i = 0; i < nitems(reg_adda); i++) 2965 rtwn_bb_write(sc, reg_adda[i], 0x0b1b25a4); 2966 } 2967 2968 /* Run IQ calibration twice. */ 2969 for (i = 0; i < 2; i++) { 2970 int ret; 2971 2972 ret = rtwn_iq_calib_chain(sc, chain, 2973 tx[chain], rx[chain]); 2974 if (ret == 0) { 2975 DPRINTF(("%s: chain %d: Tx failed.\n", 2976 __func__, chain)); 2977 tx[chain][0] = 0xff; 2978 tx[chain][1] = 0xff; 2979 rx[chain][0] = 0xff; 2980 rx[chain][1] = 0xff; 2981 } else if (ret == 1) { 2982 DPRINTF(("%s: chain %d: Rx failed.\n", 2983 __func__, chain)); 2984 rx[chain][0] = 0xff; 2985 rx[chain][1] = 0xff; 2986 } else if (ret == 3) { 2987 DPRINTF(("%s: chain %d: Both Tx and Rx " 2988 "succeeded.\n", __func__, chain)); 2989 } 2990 } 2991 2992 DPRINTF(("%s: results for run %d chain %d: tx[0]=0x%x, " 2993 "tx[1]=0x%x rx[0]=0x%x rx[1]=0x%x\n", __func__, n, chain, 2994 tx[chain][0], tx[chain][1], rx[chain][0], rx[chain][1])); 2995 } 2996 2997 rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, 2998 iq_cal_regs.ofdm0_trxpathena); 2999 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), 3000 iq_cal_regs.fpga0_rfifacesw1); 3001 rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, iq_cal_regs.ofdm0_trmuxpar); 3002 3003 rtwn_bb_write(sc, 0x0e28, 0x00); 3004 rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00032ed3); 3005 if (sc->ntxchains > 1) 3006 rtwn_bb_write(sc, R92C_LSSI_PARAM(1), 0x00032ed3); 3007 3008 if (n != 0) { 3009 if (!(hssi_param1 & R92C_HSSI_PARAM1_PI)) { 3010 rtwn_bb_write(sc, R92C_HSSI_PARAM1(0), hssi_param1); 3011 rtwn_bb_write(sc, R92C_HSSI_PARAM1(1), hssi_param1); 3012 } 3013 3014 for (i = 0; i < nitems(reg_adda); i++) 3015 rtwn_bb_write(sc, reg_adda[i], iq_cal_regs.adda[i]); 3016 3017 rtwn_write_1(sc, R92C_TXPAUSE, iq_cal_regs.txpause); 3018 rtwn_write_1(sc, R92C_BCN_CTRL, iq_cal_regs.bcn_ctrl); 3019 rtwn_write_1(sc, R92C_USTIME_TSF, iq_cal_regs.ustime_tsf); 3020 rtwn_write_4(sc, R92C_GPIO_MUXCFG, iq_cal_regs.gpio_muxcfg); 3021 } 3022 } 3023 3024 #define RTWN_IQ_CAL_MAX_TOLERANCE 5 3025 static int 3026 rtwn_iq_calib_compare_results(uint16_t tx1[2][2], uint16_t rx1[2][2], 3027 uint16_t tx2[2][2], uint16_t rx2[2][2], int ntxchains) 3028 { 3029 int chain, i, tx_ok[2], rx_ok[2]; 3030 3031 tx_ok[0] = tx_ok[1] = rx_ok[0] = rx_ok[1] = 0; 3032 for (chain = 0; chain < ntxchains; chain++) { 3033 for (i = 0; i < 2; i++) { 3034 if (tx1[chain][i] == 0xff || tx2[chain][i] == 0xff || 3035 rx1[chain][i] == 0xff || rx2[chain][i] == 0xff) 3036 continue; 3037 3038 tx_ok[chain] = (abs(tx1[chain][i] - tx2[chain][i]) <= 3039 RTWN_IQ_CAL_MAX_TOLERANCE); 3040 3041 rx_ok[chain] = (abs(rx1[chain][i] - rx2[chain][i]) <= 3042 RTWN_IQ_CAL_MAX_TOLERANCE); 3043 } 3044 } 3045 3046 if (ntxchains > 1) 3047 return (tx_ok[0] && tx_ok[1] && rx_ok[0] && rx_ok[1]); 3048 else 3049 return (tx_ok[0] && rx_ok[0]); 3050 } 3051 #undef RTWN_IQ_CAL_MAX_TOLERANCE 3052 3053 static void 3054 rtwn_iq_calib_write_results(struct rtwn_softc *sc, uint16_t tx[2], 3055 uint16_t rx[2], int chain) 3056 { 3057 uint32_t reg, val, x; 3058 long y, tx_c; 3059 3060 if (tx[0] == 0xff || tx[1] == 0xff) 3061 return; 3062 3063 reg = rtwn_bb_read(sc, R92C_OFDM0_TXIQIMBALANCE(chain)); 3064 val = ((reg >> 22) & 0x3ff); 3065 x = tx[0]; 3066 if (x & 0x0200) 3067 x |= 0xfc00; 3068 reg = (((x * val) >> 8) & 0x3ff); 3069 rtwn_bb_write(sc, R92C_OFDM0_TXIQIMBALANCE(chain), reg); 3070 3071 reg = rtwn_bb_read(sc, R92C_OFDM0_ECCATHRESHOLD); 3072 if (((x * val) >> 7) & 0x01) 3073 reg |= 0x80000000; 3074 else 3075 reg &= ~0x80000000; 3076 rtwn_bb_write(sc, R92C_OFDM0_ECCATHRESHOLD, reg); 3077 3078 y = tx[1]; 3079 if (y & 0x00000200) 3080 y |= 0xfffffc00; 3081 tx_c = (y * val) >> 8; 3082 reg = rtwn_bb_read(sc, R92C_OFDM0_TXAFE(chain)); 3083 reg |= ((((tx_c & 0x3c0) >> 6) << 24) & 0xf0000000); 3084 rtwn_bb_write(sc, R92C_OFDM0_TXAFE(chain), reg); 3085 3086 reg = rtwn_bb_read(sc, R92C_OFDM0_TXIQIMBALANCE(chain)); 3087 reg |= (((tx_c & 0x3f) << 16) & 0x003F0000); 3088 rtwn_bb_write(sc, R92C_OFDM0_TXIQIMBALANCE(chain), reg); 3089 3090 reg = rtwn_bb_read(sc, R92C_OFDM0_ECCATHRESHOLD); 3091 if (((y * val) >> 7) & 0x01) 3092 reg |= 0x20000000; 3093 else 3094 reg &= ~0x20000000; 3095 rtwn_bb_write(sc, R92C_OFDM0_ECCATHRESHOLD, reg); 3096 3097 if (rx[0] == 0xff || rx[1] == 0xff) 3098 return; 3099 3100 reg = rtwn_bb_read(sc, R92C_OFDM0_RXIQIMBALANCE(chain)); 3101 reg |= (rx[0] & 0x3ff); 3102 rtwn_bb_write(sc, R92C_OFDM0_RXIQIMBALANCE(chain), reg); 3103 reg |= (((rx[1] & 0x03f) << 8) & 0xFC00); 3104 rtwn_bb_write(sc, R92C_OFDM0_RXIQIMBALANCE(chain), reg); 3105 3106 if (chain == 0) { 3107 reg = rtwn_bb_read(sc, R92C_OFDM0_RXIQEXTANTA); 3108 reg |= (((rx[1] & 0xf) >> 6) & 0x000f); 3109 rtwn_bb_write(sc, R92C_OFDM0_RXIQEXTANTA, reg); 3110 } else { 3111 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCRSSITABLE); 3112 reg |= ((((rx[1] & 0xf) >> 6) << 12) & 0xf000); 3113 rtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, reg); 3114 } 3115 } 3116 3117 #define RTWN_IQ_CAL_NRUN 3 3118 static void 3119 rtwn_iq_calib(struct rtwn_softc *sc) 3120 { 3121 uint16_t tx[RTWN_IQ_CAL_NRUN][2][2], rx[RTWN_IQ_CAL_NRUN][2][2]; 3122 int n, valid; 3123 3124 valid = 0; 3125 for (n = 0; n < RTWN_IQ_CAL_NRUN; n++) { 3126 rtwn_iq_calib_run(sc, n, tx[n], rx[n]); 3127 3128 if (n == 0) 3129 continue; 3130 3131 /* Valid results remain stable after consecutive runs. */ 3132 valid = rtwn_iq_calib_compare_results(tx[n - 1], rx[n - 1], 3133 tx[n], rx[n], sc->ntxchains); 3134 if (valid) 3135 break; 3136 } 3137 3138 if (valid) { 3139 rtwn_iq_calib_write_results(sc, tx[n][0], rx[n][0], 0); 3140 if (sc->ntxchains > 1) 3141 rtwn_iq_calib_write_results(sc, tx[n][1], rx[n][1], 1); 3142 } 3143 } 3144 #undef RTWN_IQ_CAL_NRUN 3145 3146 static void 3147 rtwn_lc_calib(struct rtwn_softc *sc) 3148 { 3149 uint32_t rf_ac[2]; 3150 uint8_t txmode; 3151 int i; 3152 3153 txmode = rtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 3154 if ((txmode & 0x70) != 0) { 3155 /* Disable all continuous Tx. */ 3156 rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 3157 3158 /* Set RF mode to standby mode. */ 3159 for (i = 0; i < sc->nrxchains; i++) { 3160 rf_ac[i] = rtwn_rf_read(sc, i, R92C_RF_AC); 3161 rtwn_rf_write(sc, i, R92C_RF_AC, 3162 RW(rf_ac[i], R92C_RF_AC_MODE, 3163 R92C_RF_AC_MODE_STANDBY)); 3164 } 3165 } else { 3166 /* Block all Tx queues. */ 3167 rtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3168 } 3169 /* Start calibration. */ 3170 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3171 rtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 3172 3173 /* Give calibration the time to complete. */ 3174 DELAY(100); 3175 3176 /* Restore configuration. */ 3177 if ((txmode & 0x70) != 0) { 3178 /* Restore Tx mode. */ 3179 rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 3180 /* Restore RF mode. */ 3181 for (i = 0; i < sc->nrxchains; i++) 3182 rtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 3183 } else { 3184 /* Unblock all Tx queues. */ 3185 rtwn_write_1(sc, R92C_TXPAUSE, 0x00); 3186 } 3187 } 3188 3189 static void 3190 rtwn_temp_calib(struct rtwn_softc *sc) 3191 { 3192 int temp; 3193 3194 if (sc->thcal_state == 0) { 3195 /* Start measuring temperature. */ 3196 rtwn_rf_write(sc, 0, R92C_RF_T_METER, 0x60); 3197 sc->thcal_state = 1; 3198 return; 3199 } 3200 sc->thcal_state = 0; 3201 3202 /* Read measured temperature. */ 3203 temp = rtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 3204 if (temp == 0) /* Read failed, skip. */ 3205 return; 3206 DPRINTFN(2, ("temperature=%d\n", temp)); 3207 3208 /* 3209 * Redo IQ and LC calibration if temperature changed significantly 3210 * since last calibration. 3211 */ 3212 if (sc->thcal_lctemp == 0) { 3213 /* First calibration is performed in rtwn_init(). */ 3214 sc->thcal_lctemp = temp; 3215 } else if (abs(temp - sc->thcal_lctemp) > 1) { 3216 DPRINTF(("IQ/LC calib triggered by temp: %d -> %d\n", 3217 sc->thcal_lctemp, temp)); 3218 rtwn_iq_calib(sc); 3219 rtwn_lc_calib(sc); 3220 /* Record temperature of last calibration. */ 3221 sc->thcal_lctemp = temp; 3222 } 3223 } 3224 3225 static void 3226 rtwn_init_locked(struct rtwn_softc *sc) 3227 { 3228 struct ieee80211com *ic = &sc->sc_ic; 3229 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3230 uint32_t reg; 3231 uint8_t macaddr[IEEE80211_ADDR_LEN]; 3232 int i, error; 3233 3234 RTWN_LOCK_ASSERT(sc); 3235 3236 /* Init firmware commands ring. */ 3237 sc->fwcur = 0; 3238 3239 /* Power on adapter. */ 3240 error = rtwn_power_on(sc); 3241 if (error != 0) { 3242 device_printf(sc->sc_dev, "could not power on adapter\n"); 3243 goto fail; 3244 } 3245 3246 /* Initialize DMA. */ 3247 error = rtwn_dma_init(sc); 3248 if (error != 0) { 3249 device_printf(sc->sc_dev, "could not initialize DMA\n"); 3250 goto fail; 3251 } 3252 3253 /* Set info size in Rx descriptors (in 64-bit words). */ 3254 rtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 3255 3256 /* Disable interrupts. */ 3257 rtwn_write_4(sc, R92C_HISR, 0x00000000); 3258 rtwn_write_4(sc, R92C_HIMR, 0x00000000); 3259 3260 /* Set MAC address. */ 3261 IEEE80211_ADDR_COPY(macaddr, vap ? vap->iv_myaddr : ic->ic_macaddr); 3262 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 3263 rtwn_write_1(sc, R92C_MACID + i, macaddr[i]); 3264 3265 /* Set initial network type. */ 3266 reg = rtwn_read_4(sc, R92C_CR); 3267 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 3268 rtwn_write_4(sc, R92C_CR, reg); 3269 3270 rtwn_rxfilter_init(sc); 3271 3272 reg = rtwn_read_4(sc, R92C_RRSR); 3273 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_ALL); 3274 rtwn_write_4(sc, R92C_RRSR, reg); 3275 3276 /* Set short/long retry limits. */ 3277 rtwn_write_2(sc, R92C_RL, 3278 SM(R92C_RL_SRL, 0x07) | SM(R92C_RL_LRL, 0x07)); 3279 3280 /* Initialize EDCA parameters. */ 3281 rtwn_edca_init(sc); 3282 3283 /* Set data and response automatic rate fallback retry counts. */ 3284 rtwn_write_4(sc, R92C_DARFRC + 0, 0x01000000); 3285 rtwn_write_4(sc, R92C_DARFRC + 4, 0x07060504); 3286 rtwn_write_4(sc, R92C_RARFRC + 0, 0x01000000); 3287 rtwn_write_4(sc, R92C_RARFRC + 4, 0x07060504); 3288 3289 rtwn_write_2(sc, R92C_FWHW_TXQ_CTRL, 0x1f80); 3290 3291 /* Set ACK timeout. */ 3292 rtwn_write_1(sc, R92C_ACKTO, 0x40); 3293 3294 /* Initialize beacon parameters. */ 3295 rtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 3296 rtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 3297 rtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 3298 rtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 3299 3300 /* Setup AMPDU aggregation. */ 3301 rtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 3302 rtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 3303 3304 rtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 3305 rtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 3306 3307 rtwn_write_4(sc, R92C_PIFS, 0x1c); 3308 rtwn_write_4(sc, R92C_MCUTST_1, 0x0); 3309 3310 /* Load 8051 microcode. */ 3311 error = rtwn_load_firmware(sc); 3312 if (error != 0) 3313 goto fail; 3314 3315 /* Initialize MAC/BB/RF blocks. */ 3316 rtwn_mac_init(sc); 3317 rtwn_bb_init(sc); 3318 rtwn_rf_init(sc); 3319 3320 /* Turn CCK and OFDM blocks on. */ 3321 reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3322 reg |= R92C_RFMOD_CCK_EN; 3323 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3324 reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3325 reg |= R92C_RFMOD_OFDM_EN; 3326 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3327 3328 /* Clear per-station keys table. */ 3329 rtwn_cam_init(sc); 3330 3331 /* Enable hardware sequence numbering. */ 3332 rtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 3333 3334 /* Perform LO and IQ calibrations. */ 3335 rtwn_iq_calib(sc); 3336 /* Perform LC calibration. */ 3337 rtwn_lc_calib(sc); 3338 3339 rtwn_pa_bias_init(sc); 3340 3341 /* Initialize GPIO setting. */ 3342 rtwn_write_1(sc, R92C_GPIO_MUXCFG, 3343 rtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 3344 3345 /* Fix for lower temperature. */ 3346 rtwn_write_1(sc, 0x15, 0xe9); 3347 3348 /* CLear pending interrupts. */ 3349 rtwn_write_4(sc, R92C_HISR, 0xffffffff); 3350 3351 /* Enable interrupts. */ 3352 rtwn_write_4(sc, R92C_HIMR, RTWN_INT_ENABLE); 3353 3354 sc->sc_flags |= RTWN_RUNNING; 3355 3356 callout_reset(&sc->watchdog_to, hz, rtwn_watchdog, sc); 3357 return; 3358 3359 fail: 3360 rtwn_stop_locked(sc); 3361 } 3362 3363 static void 3364 rtwn_init(struct rtwn_softc *sc) 3365 { 3366 3367 RTWN_LOCK(sc); 3368 rtwn_init_locked(sc); 3369 RTWN_UNLOCK(sc); 3370 3371 if (sc->sc_flags & RTWN_RUNNING) 3372 ieee80211_start_all(&sc->sc_ic); 3373 } 3374 3375 static void 3376 rtwn_stop_locked(struct rtwn_softc *sc) 3377 { 3378 uint16_t reg; 3379 int i; 3380 3381 RTWN_LOCK_ASSERT(sc); 3382 3383 sc->sc_tx_timer = 0; 3384 callout_stop(&sc->watchdog_to); 3385 callout_stop(&sc->calib_to); 3386 sc->sc_flags &= ~RTWN_RUNNING; 3387 3388 /* Disable interrupts. */ 3389 rtwn_write_4(sc, R92C_HISR, 0x00000000); 3390 rtwn_write_4(sc, R92C_HIMR, 0x00000000); 3391 3392 /* Stop hardware. */ 3393 rtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3394 rtwn_write_1(sc, R92C_RF_CTRL, 0x00); 3395 reg = rtwn_read_1(sc, R92C_SYS_FUNC_EN); 3396 reg |= R92C_SYS_FUNC_EN_BB_GLB_RST; 3397 rtwn_write_1(sc, R92C_SYS_FUNC_EN, reg); 3398 reg &= ~R92C_SYS_FUNC_EN_BB_GLB_RST; 3399 rtwn_write_1(sc, R92C_SYS_FUNC_EN, reg); 3400 reg = rtwn_read_2(sc, R92C_CR); 3401 reg &= ~(R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3402 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3403 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3404 R92C_CR_ENSEC); 3405 rtwn_write_2(sc, R92C_CR, reg); 3406 if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) 3407 rtwn_fw_reset(sc); 3408 /* TODO: linux does additional btcoex stuff here */ 3409 rtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0x80); /* linux magic number */ 3410 rtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); /* ditto */ 3411 rtwn_write_1(sc, R92C_AFE_XTAL_CTRL, 0x0e); /* different with btcoex */ 3412 rtwn_write_1(sc, R92C_RSV_CTRL, 0x0e); 3413 rtwn_write_1(sc, R92C_APS_FSMCO, R92C_APS_FSMCO_PDN_EN); 3414 3415 for (i = 0; i < RTWN_NTXQUEUES; i++) 3416 rtwn_reset_tx_list(sc, i); 3417 rtwn_reset_rx_list(sc); 3418 } 3419 3420 static void 3421 rtwn_stop(struct rtwn_softc *sc) 3422 { 3423 RTWN_LOCK(sc); 3424 rtwn_stop_locked(sc); 3425 RTWN_UNLOCK(sc); 3426 } 3427 3428 static void 3429 rtwn_intr(void *arg) 3430 { 3431 struct rtwn_softc *sc = arg; 3432 uint32_t status; 3433 int i; 3434 3435 RTWN_LOCK(sc); 3436 status = rtwn_read_4(sc, R92C_HISR); 3437 if (status == 0 || status == 0xffffffff) { 3438 RTWN_UNLOCK(sc); 3439 return; 3440 } 3441 3442 /* Disable interrupts. */ 3443 rtwn_write_4(sc, R92C_HIMR, 0x00000000); 3444 3445 /* Ack interrupts. */ 3446 rtwn_write_4(sc, R92C_HISR, status); 3447 3448 /* Vendor driver treats RX errors like ROK... */ 3449 if (status & (R92C_IMR_ROK | R92C_IMR_RXFOVW | R92C_IMR_RDU)) { 3450 bus_dmamap_sync(sc->rx_ring.desc_dmat, sc->rx_ring.desc_map, 3451 BUS_DMASYNC_POSTREAD); 3452 3453 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 3454 struct r92c_rx_desc *rx_desc = &sc->rx_ring.desc[i]; 3455 struct rtwn_rx_data *rx_data = &sc->rx_ring.rx_data[i]; 3456 3457 if (le32toh(rx_desc->rxdw0) & R92C_RXDW0_OWN) 3458 continue; 3459 3460 rtwn_rx_frame(sc, rx_desc, rx_data, i); 3461 } 3462 } 3463 3464 if (status & R92C_IMR_BDOK) 3465 rtwn_tx_done(sc, RTWN_BEACON_QUEUE); 3466 if (status & R92C_IMR_HIGHDOK) 3467 rtwn_tx_done(sc, RTWN_HIGH_QUEUE); 3468 if (status & R92C_IMR_MGNTDOK) 3469 rtwn_tx_done(sc, RTWN_MGNT_QUEUE); 3470 if (status & R92C_IMR_BKDOK) 3471 rtwn_tx_done(sc, RTWN_BK_QUEUE); 3472 if (status & R92C_IMR_BEDOK) 3473 rtwn_tx_done(sc, RTWN_BE_QUEUE); 3474 if (status & R92C_IMR_VIDOK) 3475 rtwn_tx_done(sc, RTWN_VI_QUEUE); 3476 if (status & R92C_IMR_VODOK) 3477 rtwn_tx_done(sc, RTWN_VO_QUEUE); 3478 3479 /* Enable interrupts. */ 3480 rtwn_write_4(sc, R92C_HIMR, RTWN_INT_ENABLE); 3481 3482 RTWN_UNLOCK(sc); 3483 } 3484 3485 static void 3486 rtwn_hw_reset(void *arg0, int pending) 3487 { 3488 struct rtwn_softc *sc = arg0; 3489 struct ieee80211com *ic = &sc->sc_ic; 3490 3491 rtwn_stop(sc); 3492 rtwn_init(sc); 3493 ieee80211_notify_radio(ic, 1); 3494 } 3495