1 /* $OpenBSD: if_rtwn.c,v 1.6 2015/08/28 00:03:53 deraadt Exp $ */ 2 3 /*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * Copyright (c) 2015 Stefan Sperling <stsp@openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include <sys/cdefs.h> 21 __FBSDID("$FreeBSD$"); 22 23 /* 24 * Driver for Realtek RTL8188CE 25 */ 26 27 #include <sys/param.h> 28 #include <sys/sysctl.h> 29 #include <sys/sockio.h> 30 #include <sys/mbuf.h> 31 #include <sys/kernel.h> 32 #include <sys/socket.h> 33 #include <sys/systm.h> 34 #include <sys/malloc.h> 35 #include <sys/lock.h> 36 #include <sys/mutex.h> 37 #include <sys/module.h> 38 #include <sys/bus.h> 39 #include <sys/endian.h> 40 #include <sys/firmware.h> 41 42 #include <machine/bus.h> 43 #include <machine/resource.h> 44 #include <sys/rman.h> 45 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcivar.h> 48 49 #include <net/bpf.h> 50 #include <net/if.h> 51 #include <net/if_var.h> 52 #include <net/if_arp.h> 53 #include <net/ethernet.h> 54 #include <net/if_dl.h> 55 #include <net/if_media.h> 56 #include <net/if_types.h> 57 58 #include <net80211/ieee80211_var.h> 59 #include <net80211/ieee80211_radiotap.h> 60 #include <net80211/ieee80211_regdomain.h> 61 #include <net80211/ieee80211_ratectl.h> 62 63 #include <netinet/in.h> 64 #include <netinet/in_systm.h> 65 #include <netinet/in_var.h> 66 #include <netinet/ip.h> 67 #include <netinet/if_ether.h> 68 69 #include <dev/rtwn/if_rtwnreg.h> 70 71 #define RTWN_DEBUG 72 #ifdef RTWN_DEBUG 73 #define DPRINTF(x) do { if (sc->sc_debug > 0) printf x; } while (0) 74 #define DPRINTFN(n, x) do { if (sc->sc_debug >= (n)) printf x; } while (0) 75 #else 76 #define DPRINTF(x) 77 #define DPRINTFN(n, x) 78 #endif 79 80 /* 81 * PCI configuration space registers. 82 */ 83 #define RTWN_PCI_IOBA 0x10 /* i/o mapped base */ 84 #define RTWN_PCI_MMBA 0x18 /* memory mapped base */ 85 86 #define RTWN_INT_ENABLE (R92C_IMR_ROK | R92C_IMR_VODOK | R92C_IMR_VIDOK | \ 87 R92C_IMR_BEDOK | R92C_IMR_BKDOK | R92C_IMR_MGNTDOK | \ 88 R92C_IMR_HIGHDOK | R92C_IMR_BDOK | R92C_IMR_RDU | \ 89 R92C_IMR_RXFOVW) 90 91 struct rtwn_ident { 92 uint16_t vendor; 93 uint16_t device; 94 const char *name; 95 }; 96 97 98 static const struct rtwn_ident rtwn_ident_table[] = { 99 { 0x10ec, 0x8176, "Realtek RTL8188CE" }, 100 { 0, 0, NULL } 101 }; 102 103 104 static void rtwn_dma_map_addr(void *, bus_dma_segment_t *, int, int); 105 static void rtwn_setup_rx_desc(struct rtwn_softc *, struct r92c_rx_desc *, 106 bus_addr_t, size_t, int); 107 static int rtwn_alloc_rx_list(struct rtwn_softc *); 108 static void rtwn_reset_rx_list(struct rtwn_softc *); 109 static void rtwn_free_rx_list(struct rtwn_softc *); 110 static int rtwn_alloc_tx_list(struct rtwn_softc *, int); 111 static void rtwn_reset_tx_list(struct rtwn_softc *, int); 112 static void rtwn_free_tx_list(struct rtwn_softc *, int); 113 static struct ieee80211vap *rtwn_vap_create(struct ieee80211com *, 114 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 115 const uint8_t [IEEE80211_ADDR_LEN], 116 const uint8_t [IEEE80211_ADDR_LEN]); 117 static void rtwn_vap_delete(struct ieee80211vap *); 118 static void rtwn_write_1(struct rtwn_softc *, uint16_t, uint8_t); 119 static void rtwn_write_2(struct rtwn_softc *, uint16_t, uint16_t); 120 static void rtwn_write_4(struct rtwn_softc *, uint16_t, uint32_t); 121 static uint8_t rtwn_read_1(struct rtwn_softc *, uint16_t); 122 static uint16_t rtwn_read_2(struct rtwn_softc *, uint16_t); 123 static uint32_t rtwn_read_4(struct rtwn_softc *, uint16_t); 124 static int rtwn_fw_cmd(struct rtwn_softc *, uint8_t, const void *, int); 125 static void rtwn_rf_write(struct rtwn_softc *, int, uint8_t, uint32_t); 126 static uint32_t rtwn_rf_read(struct rtwn_softc *, int, uint8_t); 127 static int rtwn_llt_write(struct rtwn_softc *, uint32_t, uint32_t); 128 static uint8_t rtwn_efuse_read_1(struct rtwn_softc *, uint16_t); 129 static void rtwn_efuse_read(struct rtwn_softc *); 130 static int rtwn_read_chipid(struct rtwn_softc *); 131 static void rtwn_read_rom(struct rtwn_softc *); 132 static int rtwn_ra_init(struct rtwn_softc *); 133 static void rtwn_tsf_sync_enable(struct rtwn_softc *); 134 static void rtwn_set_led(struct rtwn_softc *, int, int); 135 static void rtwn_calib_to(void *); 136 static int rtwn_newstate(struct ieee80211vap *, enum ieee80211_state, int); 137 static int rtwn_updateedca(struct ieee80211com *); 138 static void rtwn_update_avgrssi(struct rtwn_softc *, int, int8_t); 139 static int8_t rtwn_get_rssi(struct rtwn_softc *, int, void *); 140 static void rtwn_rx_frame(struct rtwn_softc *, struct r92c_rx_desc *, 141 struct rtwn_rx_data *, int); 142 static int rtwn_tx(struct rtwn_softc *, struct mbuf *, 143 struct ieee80211_node *); 144 static void rtwn_tx_done(struct rtwn_softc *, int); 145 static int rtwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 146 const struct ieee80211_bpf_params *); 147 static int rtwn_transmit(struct ieee80211com *, struct mbuf *); 148 static void rtwn_parent(struct ieee80211com *); 149 static void rtwn_start(struct rtwn_softc *sc); 150 static void rtwn_watchdog(void *); 151 static int rtwn_power_on(struct rtwn_softc *); 152 static int rtwn_llt_init(struct rtwn_softc *); 153 static void rtwn_fw_reset(struct rtwn_softc *); 154 static void rtwn_fw_loadpage(struct rtwn_softc *, int, const uint8_t *, 155 int); 156 static int rtwn_load_firmware(struct rtwn_softc *); 157 static int rtwn_dma_init(struct rtwn_softc *); 158 static void rtwn_mac_init(struct rtwn_softc *); 159 static void rtwn_bb_init(struct rtwn_softc *); 160 static void rtwn_rf_init(struct rtwn_softc *); 161 static void rtwn_cam_init(struct rtwn_softc *); 162 static void rtwn_pa_bias_init(struct rtwn_softc *); 163 static void rtwn_rxfilter_init(struct rtwn_softc *); 164 static void rtwn_edca_init(struct rtwn_softc *); 165 static void rtwn_write_txpower(struct rtwn_softc *, int, uint16_t[]); 166 static void rtwn_get_txpower(struct rtwn_softc *, int, 167 struct ieee80211_channel *, struct ieee80211_channel *, 168 uint16_t[]); 169 static void rtwn_set_txpower(struct rtwn_softc *, 170 struct ieee80211_channel *, struct ieee80211_channel *); 171 static void rtwn_scan_start(struct ieee80211com *); 172 static void rtwn_scan_end(struct ieee80211com *); 173 static void rtwn_set_channel(struct ieee80211com *); 174 static void rtwn_update_mcast(struct ieee80211com *); 175 static void rtwn_set_chan(struct rtwn_softc *, 176 struct ieee80211_channel *, struct ieee80211_channel *); 177 static int rtwn_iq_calib_chain(struct rtwn_softc *, int, uint16_t[2], 178 uint16_t[2]); 179 static void rtwn_iq_calib_run(struct rtwn_softc *, int, uint16_t[2][2], 180 uint16_t[2][2]); 181 static int rtwn_iq_calib_compare_results(uint16_t[2][2], uint16_t[2][2], 182 uint16_t[2][2], uint16_t[2][2], int); 183 static void rtwn_iq_calib_write_results(struct rtwn_softc *, uint16_t[2], 184 uint16_t[2], int); 185 static void rtwn_iq_calib(struct rtwn_softc *); 186 static void rtwn_lc_calib(struct rtwn_softc *); 187 static void rtwn_temp_calib(struct rtwn_softc *); 188 static int rtwn_init(struct rtwn_softc *); 189 static void rtwn_stop_locked(struct rtwn_softc *); 190 static void rtwn_stop(struct rtwn_softc *); 191 static void rtwn_intr(void *); 192 193 /* Aliases. */ 194 #define rtwn_bb_write rtwn_write_4 195 #define rtwn_bb_read rtwn_read_4 196 197 static int rtwn_probe(device_t); 198 static int rtwn_attach(device_t); 199 static int rtwn_detach(device_t); 200 static int rtwn_shutdown(device_t); 201 static int rtwn_suspend(device_t); 202 static int rtwn_resume(device_t); 203 204 static device_method_t rtwn_methods[] = { 205 /* Device interface */ 206 DEVMETHOD(device_probe, rtwn_probe), 207 DEVMETHOD(device_attach, rtwn_attach), 208 DEVMETHOD(device_detach, rtwn_detach), 209 DEVMETHOD(device_shutdown, rtwn_shutdown), 210 DEVMETHOD(device_suspend, rtwn_suspend), 211 DEVMETHOD(device_resume, rtwn_resume), 212 213 DEVMETHOD_END 214 }; 215 216 static driver_t rtwn_driver = { 217 "rtwn", 218 rtwn_methods, 219 sizeof (struct rtwn_softc) 220 }; 221 static devclass_t rtwn_devclass; 222 223 DRIVER_MODULE(rtwn, pci, rtwn_driver, rtwn_devclass, NULL, NULL); 224 225 MODULE_VERSION(rtwn, 1); 226 227 MODULE_DEPEND(rtwn, pci, 1, 1, 1); 228 MODULE_DEPEND(rtwn, wlan, 1, 1, 1); 229 MODULE_DEPEND(rtwn, firmware, 1, 1, 1); 230 231 static int 232 rtwn_probe(device_t dev) 233 { 234 const struct rtwn_ident *ident; 235 236 for (ident = rtwn_ident_table; ident->name != NULL; ident++) { 237 if (pci_get_vendor(dev) == ident->vendor && 238 pci_get_device(dev) == ident->device) { 239 device_set_desc(dev, ident->name); 240 return (BUS_PROBE_DEFAULT); 241 } 242 } 243 return (ENXIO); 244 } 245 246 static int 247 rtwn_attach(device_t dev) 248 { 249 struct rtwn_softc *sc = device_get_softc(dev); 250 struct ieee80211com *ic = &sc->sc_ic; 251 uint32_t lcsr; 252 uint8_t bands[howmany(IEEE80211_MODE_MAX, 8)]; 253 int i, count, error, rid; 254 255 sc->sc_dev = dev; 256 sc->sc_debug = 0; 257 258 /* 259 * Get the offset of the PCI Express Capability Structure in PCI 260 * Configuration Space. 261 */ 262 error = pci_find_cap(dev, PCIY_EXPRESS, &sc->sc_cap_off); 263 if (error != 0) { 264 device_printf(dev, "PCIe capability structure not found!\n"); 265 return (error); 266 } 267 268 /* Enable bus-mastering. */ 269 pci_enable_busmaster(dev); 270 271 rid = PCIR_BAR(2); 272 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 273 RF_ACTIVE); 274 if (sc->mem == NULL) { 275 device_printf(dev, "can't map mem space\n"); 276 return (ENOMEM); 277 } 278 sc->sc_st = rman_get_bustag(sc->mem); 279 sc->sc_sh = rman_get_bushandle(sc->mem); 280 281 /* Install interrupt handler. */ 282 count = 1; 283 rid = 0; 284 if (pci_alloc_msi(dev, &count) == 0) 285 rid = 1; 286 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE | 287 (rid != 0 ? 0 : RF_SHAREABLE)); 288 if (sc->irq == NULL) { 289 device_printf(dev, "can't map interrupt\n"); 290 return (ENXIO); 291 } 292 293 RTWN_LOCK_INIT(sc); 294 callout_init_mtx(&sc->calib_to, &sc->sc_mtx, 0); 295 callout_init_mtx(&sc->watchdog_to, &sc->sc_mtx, 0); 296 mbufq_init(&sc->sc_snd, ifqmaxlen); 297 298 error = rtwn_read_chipid(sc); 299 if (error != 0) { 300 device_printf(dev, "unsupported test chip\n"); 301 goto fail; 302 } 303 304 /* Disable PCIe Active State Power Management (ASPM). */ 305 lcsr = pci_read_config(sc->sc_dev, sc->sc_cap_off + PCIER_LINK_CTL, 4); 306 lcsr &= ~PCIEM_LINK_CTL_ASPMC; 307 pci_write_config(sc->sc_dev, sc->sc_cap_off + PCIER_LINK_CTL, lcsr, 4); 308 309 /* Allocate Tx/Rx buffers. */ 310 error = rtwn_alloc_rx_list(sc); 311 if (error != 0) { 312 device_printf(dev, "could not allocate Rx buffers\n"); 313 goto fail; 314 } 315 for (i = 0; i < RTWN_NTXQUEUES; i++) { 316 error = rtwn_alloc_tx_list(sc, i); 317 if (error != 0) { 318 device_printf(dev, "could not allocate Tx buffers\n"); 319 goto fail; 320 } 321 } 322 323 /* Determine number of Tx/Rx chains. */ 324 if (sc->chip & RTWN_CHIP_92C) { 325 sc->ntxchains = (sc->chip & RTWN_CHIP_92C_1T2R) ? 1 : 2; 326 sc->nrxchains = 2; 327 } else { 328 sc->ntxchains = 1; 329 sc->nrxchains = 1; 330 } 331 rtwn_read_rom(sc); 332 333 device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n", 334 (sc->chip & RTWN_CHIP_92C) ? "8192CE" : "8188CE", 335 sc->ntxchains, sc->nrxchains); 336 337 ic->ic_softc = sc; 338 ic->ic_name = device_get_nameunit(dev); 339 ic->ic_opmode = IEEE80211_M_STA; 340 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 341 342 /* set device capabilities */ 343 ic->ic_caps = 344 IEEE80211_C_STA /* station mode */ 345 | IEEE80211_C_MONITOR /* monitor mode */ 346 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 347 | IEEE80211_C_SHSLOT /* short slot time supported */ 348 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 349 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 350 | IEEE80211_C_WME /* 802.11e */ 351 ; 352 353 memset(bands, 0, sizeof(bands)); 354 setbit(bands, IEEE80211_MODE_11B); 355 setbit(bands, IEEE80211_MODE_11G); 356 ieee80211_init_channels(ic, NULL, bands); 357 358 ieee80211_ifattach(ic); 359 360 ic->ic_wme.wme_update = rtwn_updateedca; 361 ic->ic_update_mcast = rtwn_update_mcast; 362 ic->ic_scan_start =rtwn_scan_start; 363 ic->ic_scan_end = rtwn_scan_end; 364 ic->ic_set_channel = rtwn_set_channel; 365 ic->ic_raw_xmit = rtwn_raw_xmit; 366 ic->ic_transmit = rtwn_transmit; 367 ic->ic_parent = rtwn_parent; 368 ic->ic_vap_create = rtwn_vap_create; 369 ic->ic_vap_delete = rtwn_vap_delete; 370 371 ieee80211_radiotap_attach(ic, 372 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 373 RTWN_TX_RADIOTAP_PRESENT, 374 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 375 RTWN_RX_RADIOTAP_PRESENT); 376 377 /* 378 * Hook our interrupt after all initialization is complete. 379 */ 380 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE, 381 NULL, rtwn_intr, sc, &sc->sc_ih); 382 if (error != 0) { 383 device_printf(dev, "can't establish interrupt, error %d\n", 384 error); 385 goto fail; 386 } 387 388 if (bootverbose) 389 ieee80211_announce(ic); 390 391 return (0); 392 393 fail: 394 rtwn_detach(dev); 395 return (error); 396 } 397 398 399 static int 400 rtwn_detach(device_t dev) 401 { 402 struct rtwn_softc *sc = device_get_softc(dev); 403 int i; 404 405 if (sc->sc_ic.ic_softc != NULL) { 406 rtwn_stop(sc); 407 408 callout_drain(&sc->calib_to); 409 callout_drain(&sc->watchdog_to); 410 ieee80211_ifdetach(&sc->sc_ic); 411 mbufq_drain(&sc->sc_snd); 412 } 413 414 /* Uninstall interrupt handler. */ 415 if (sc->irq != NULL) { 416 bus_teardown_intr(dev, sc->irq, sc->sc_ih); 417 bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq), 418 sc->irq); 419 pci_release_msi(dev); 420 } 421 422 /* Free Tx/Rx buffers. */ 423 for (i = 0; i < RTWN_NTXQUEUES; i++) 424 rtwn_free_tx_list(sc, i); 425 rtwn_free_rx_list(sc); 426 427 if (sc->mem != NULL) 428 bus_release_resource(dev, SYS_RES_MEMORY, 429 rman_get_rid(sc->mem), sc->mem); 430 431 RTWN_LOCK_DESTROY(sc); 432 return (0); 433 } 434 435 static int 436 rtwn_shutdown(device_t dev) 437 { 438 439 return (0); 440 } 441 442 static int 443 rtwn_suspend(device_t dev) 444 { 445 return (0); 446 } 447 448 static int 449 rtwn_resume(device_t dev) 450 { 451 452 return (0); 453 } 454 455 static void 456 rtwn_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 457 { 458 459 if (error != 0) 460 return; 461 KASSERT(nsegs == 1, ("too many DMA segments, %d should be 1", nsegs)); 462 *(bus_addr_t *)arg = segs[0].ds_addr; 463 } 464 465 static void 466 rtwn_setup_rx_desc(struct rtwn_softc *sc, struct r92c_rx_desc *desc, 467 bus_addr_t addr, size_t len, int idx) 468 { 469 470 memset(desc, 0, sizeof(*desc)); 471 desc->rxdw0 = htole32(SM(R92C_RXDW0_PKTLEN, len) | 472 ((idx == RTWN_RX_LIST_COUNT - 1) ? R92C_RXDW0_EOR : 0)); 473 desc->rxbufaddr = htole32(addr); 474 bus_space_barrier(sc->sc_st, sc->sc_sh, 0, sc->sc_mapsize, 475 BUS_SPACE_BARRIER_WRITE); 476 desc->rxdw0 |= htole32(R92C_RXDW0_OWN); 477 } 478 479 static int 480 rtwn_alloc_rx_list(struct rtwn_softc *sc) 481 { 482 struct rtwn_rx_ring *rx_ring = &sc->rx_ring; 483 struct rtwn_rx_data *rx_data; 484 bus_size_t size; 485 int i, error; 486 487 /* Allocate Rx descriptors. */ 488 size = sizeof(struct r92c_rx_desc) * RTWN_RX_LIST_COUNT; 489 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 490 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 491 size, 1, size, 0, NULL, NULL, &rx_ring->desc_dmat); 492 if (error != 0) { 493 device_printf(sc->sc_dev, "could not create rx desc DMA tag\n"); 494 goto fail; 495 } 496 497 error = bus_dmamem_alloc(rx_ring->desc_dmat, (void **)&rx_ring->desc, 498 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, 499 &rx_ring->desc_map); 500 if (error != 0) { 501 device_printf(sc->sc_dev, "could not allocate rx desc\n"); 502 goto fail; 503 } 504 error = bus_dmamap_load(rx_ring->desc_dmat, rx_ring->desc_map, 505 rx_ring->desc, size, rtwn_dma_map_addr, &rx_ring->paddr, 0); 506 if (error != 0) { 507 device_printf(sc->sc_dev, "could not load rx desc DMA map\n"); 508 goto fail; 509 } 510 bus_dmamap_sync(rx_ring->desc_dmat, rx_ring->desc_map, 511 BUS_DMASYNC_PREWRITE); 512 513 /* Create RX buffer DMA tag. */ 514 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 515 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 516 1, MCLBYTES, 0, NULL, NULL, &rx_ring->data_dmat); 517 if (error != 0) { 518 device_printf(sc->sc_dev, "could not create rx buf DMA tag\n"); 519 goto fail; 520 } 521 522 /* Allocate Rx buffers. */ 523 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 524 rx_data = &rx_ring->rx_data[i]; 525 error = bus_dmamap_create(rx_ring->data_dmat, 0, &rx_data->map); 526 if (error != 0) { 527 device_printf(sc->sc_dev, 528 "could not create rx buf DMA map\n"); 529 goto fail; 530 } 531 532 rx_data->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 533 if (rx_data->m == NULL) { 534 device_printf(sc->sc_dev, 535 "could not allocate rx mbuf\n"); 536 error = ENOMEM; 537 goto fail; 538 } 539 540 error = bus_dmamap_load(rx_ring->data_dmat, rx_data->map, 541 mtod(rx_data->m, void *), MCLBYTES, rtwn_dma_map_addr, 542 &rx_data->paddr, BUS_DMA_NOWAIT); 543 if (error != 0) { 544 device_printf(sc->sc_dev, 545 "could not load rx buf DMA map"); 546 goto fail; 547 } 548 549 rtwn_setup_rx_desc(sc, &rx_ring->desc[i], rx_data->paddr, 550 MCLBYTES, i); 551 } 552 return (0); 553 554 fail: 555 rtwn_free_rx_list(sc); 556 return (error); 557 } 558 559 static void 560 rtwn_reset_rx_list(struct rtwn_softc *sc) 561 { 562 struct rtwn_rx_ring *rx_ring = &sc->rx_ring; 563 struct rtwn_rx_data *rx_data; 564 int i; 565 566 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 567 rx_data = &rx_ring->rx_data[i]; 568 rtwn_setup_rx_desc(sc, &rx_ring->desc[i], rx_data->paddr, 569 MCLBYTES, i); 570 } 571 } 572 573 static void 574 rtwn_free_rx_list(struct rtwn_softc *sc) 575 { 576 struct rtwn_rx_ring *rx_ring = &sc->rx_ring; 577 struct rtwn_rx_data *rx_data; 578 int i; 579 580 if (rx_ring->desc_dmat != NULL) { 581 if (rx_ring->desc != NULL) { 582 bus_dmamap_unload(rx_ring->desc_dmat, 583 rx_ring->desc_map); 584 bus_dmamem_free(rx_ring->desc_dmat, rx_ring->desc, 585 rx_ring->desc_map); 586 rx_ring->desc = NULL; 587 } 588 bus_dma_tag_destroy(rx_ring->desc_dmat); 589 rx_ring->desc_dmat = NULL; 590 } 591 592 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 593 rx_data = &rx_ring->rx_data[i]; 594 595 if (rx_data->m != NULL) { 596 bus_dmamap_unload(rx_ring->data_dmat, rx_data->map); 597 m_freem(rx_data->m); 598 rx_data->m = NULL; 599 } 600 bus_dmamap_destroy(rx_ring->data_dmat, rx_data->map); 601 rx_data->map = NULL; 602 } 603 if (rx_ring->data_dmat != NULL) { 604 bus_dma_tag_destroy(rx_ring->data_dmat); 605 rx_ring->data_dmat = NULL; 606 } 607 } 608 609 static int 610 rtwn_alloc_tx_list(struct rtwn_softc *sc, int qid) 611 { 612 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 613 struct rtwn_tx_data *tx_data; 614 bus_size_t size; 615 int i, error; 616 617 size = sizeof(struct r92c_tx_desc) * RTWN_TX_LIST_COUNT; 618 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), PAGE_SIZE, 0, 619 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 620 size, 1, size, 0, NULL, NULL, &tx_ring->desc_dmat); 621 if (error != 0) { 622 device_printf(sc->sc_dev, "could not create tx ring DMA tag\n"); 623 goto fail; 624 } 625 626 error = bus_dmamem_alloc(tx_ring->desc_dmat, (void **)&tx_ring->desc, 627 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &tx_ring->desc_map); 628 if (error != 0) { 629 device_printf(sc->sc_dev, "can't map tx ring DMA memory\n"); 630 goto fail; 631 } 632 error = bus_dmamap_load(tx_ring->desc_dmat, tx_ring->desc_map, 633 tx_ring->desc, size, rtwn_dma_map_addr, &tx_ring->paddr, 634 BUS_DMA_NOWAIT); 635 if (error != 0) { 636 device_printf(sc->sc_dev, "could not load desc DMA map\n"); 637 goto fail; 638 } 639 640 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 641 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 642 1, MCLBYTES, 0, NULL, NULL, &tx_ring->data_dmat); 643 if (error != 0) { 644 device_printf(sc->sc_dev, "could not create tx buf DMA tag\n"); 645 goto fail; 646 } 647 648 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 649 struct r92c_tx_desc *desc = &tx_ring->desc[i]; 650 651 /* setup tx desc */ 652 desc->nextdescaddr = htole32(tx_ring->paddr + 653 + sizeof(struct r92c_tx_desc) 654 * ((i + 1) % RTWN_TX_LIST_COUNT)); 655 tx_data = &tx_ring->tx_data[i]; 656 error = bus_dmamap_create(tx_ring->data_dmat, 0, &tx_data->map); 657 if (error != 0) { 658 device_printf(sc->sc_dev, 659 "could not create tx buf DMA map\n"); 660 goto fail; 661 } 662 tx_data->m = NULL; 663 tx_data->ni = NULL; 664 } 665 return (0); 666 667 fail: 668 rtwn_free_tx_list(sc, qid); 669 return (error); 670 } 671 672 static void 673 rtwn_reset_tx_list(struct rtwn_softc *sc, int qid) 674 { 675 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 676 int i; 677 678 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 679 struct r92c_tx_desc *desc = &tx_ring->desc[i]; 680 struct rtwn_tx_data *tx_data = &tx_ring->tx_data[i]; 681 682 memset(desc, 0, sizeof(*desc) - 683 (sizeof(desc->reserved) + sizeof(desc->nextdescaddr64) + 684 sizeof(desc->nextdescaddr))); 685 686 if (tx_data->m != NULL) { 687 bus_dmamap_unload(tx_ring->data_dmat, tx_data->map); 688 m_freem(tx_data->m); 689 tx_data->m = NULL; 690 } 691 if (tx_data->ni != NULL) { 692 ieee80211_free_node(tx_data->ni); 693 tx_data->ni = NULL; 694 } 695 } 696 697 bus_dmamap_sync(tx_ring->desc_dmat, tx_ring->desc_map, 698 BUS_DMASYNC_POSTWRITE); 699 700 sc->qfullmsk &= ~(1 << qid); 701 tx_ring->queued = 0; 702 tx_ring->cur = 0; 703 } 704 705 static void 706 rtwn_free_tx_list(struct rtwn_softc *sc, int qid) 707 { 708 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 709 struct rtwn_tx_data *tx_data; 710 int i; 711 712 if (tx_ring->desc_dmat != NULL) { 713 if (tx_ring->desc != NULL) { 714 bus_dmamap_unload(tx_ring->desc_dmat, 715 tx_ring->desc_map); 716 bus_dmamem_free(tx_ring->desc_dmat, tx_ring->desc, 717 tx_ring->desc_map); 718 } 719 bus_dma_tag_destroy(tx_ring->desc_dmat); 720 } 721 722 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 723 tx_data = &tx_ring->tx_data[i]; 724 725 if (tx_data->m != NULL) { 726 bus_dmamap_unload(tx_ring->data_dmat, tx_data->map); 727 m_freem(tx_data->m); 728 tx_data->m = NULL; 729 } 730 } 731 if (tx_ring->data_dmat != NULL) { 732 bus_dma_tag_destroy(tx_ring->data_dmat); 733 tx_ring->data_dmat = NULL; 734 } 735 736 sc->qfullmsk &= ~(1 << qid); 737 tx_ring->queued = 0; 738 tx_ring->cur = 0; 739 } 740 741 742 static struct ieee80211vap * 743 rtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 744 enum ieee80211_opmode opmode, int flags, 745 const uint8_t bssid[IEEE80211_ADDR_LEN], 746 const uint8_t mac[IEEE80211_ADDR_LEN]) 747 { 748 struct rtwn_vap *rvp; 749 struct ieee80211vap *vap; 750 751 if (!TAILQ_EMPTY(&ic->ic_vaps)) 752 return (NULL); 753 754 rvp = malloc(sizeof(struct rtwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); 755 vap = &rvp->vap; 756 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 757 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 758 /* out of memory */ 759 free(rvp, M_80211_VAP); 760 return (NULL); 761 } 762 763 /* Override state transition machine. */ 764 rvp->newstate = vap->iv_newstate; 765 vap->iv_newstate = rtwn_newstate; 766 767 /* Complete setup. */ 768 ieee80211_vap_attach(vap, ieee80211_media_change, 769 ieee80211_media_status, mac); 770 ic->ic_opmode = opmode; 771 return (vap); 772 } 773 774 static void 775 rtwn_vap_delete(struct ieee80211vap *vap) 776 { 777 struct rtwn_vap *rvp = RTWN_VAP(vap); 778 779 ieee80211_vap_detach(vap); 780 free(rvp, M_80211_VAP); 781 } 782 783 static void 784 rtwn_write_1(struct rtwn_softc *sc, uint16_t addr, uint8_t val) 785 { 786 787 bus_space_write_1(sc->sc_st, sc->sc_sh, addr, val); 788 } 789 790 static void 791 rtwn_write_2(struct rtwn_softc *sc, uint16_t addr, uint16_t val) 792 { 793 794 val = htole16(val); 795 bus_space_write_2(sc->sc_st, sc->sc_sh, addr, val); 796 } 797 798 static void 799 rtwn_write_4(struct rtwn_softc *sc, uint16_t addr, uint32_t val) 800 { 801 802 val = htole32(val); 803 bus_space_write_4(sc->sc_st, sc->sc_sh, addr, val); 804 } 805 806 static uint8_t 807 rtwn_read_1(struct rtwn_softc *sc, uint16_t addr) 808 { 809 810 return (bus_space_read_1(sc->sc_st, sc->sc_sh, addr)); 811 } 812 813 static uint16_t 814 rtwn_read_2(struct rtwn_softc *sc, uint16_t addr) 815 { 816 817 return (bus_space_read_2(sc->sc_st, sc->sc_sh, addr)); 818 } 819 820 static uint32_t 821 rtwn_read_4(struct rtwn_softc *sc, uint16_t addr) 822 { 823 824 return (bus_space_read_4(sc->sc_st, sc->sc_sh, addr)); 825 } 826 827 static int 828 rtwn_fw_cmd(struct rtwn_softc *sc, uint8_t id, const void *buf, int len) 829 { 830 struct r92c_fw_cmd cmd; 831 int ntries; 832 833 /* Wait for current FW box to be empty. */ 834 for (ntries = 0; ntries < 100; ntries++) { 835 if (!(rtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur))) 836 break; 837 DELAY(1); 838 } 839 if (ntries == 100) { 840 device_printf(sc->sc_dev, 841 "could not send firmware command %d\n", id); 842 return (ETIMEDOUT); 843 } 844 memset(&cmd, 0, sizeof(cmd)); 845 cmd.id = id; 846 if (len > 3) 847 cmd.id |= R92C_CMD_FLAG_EXT; 848 KASSERT(len <= sizeof(cmd.msg), ("rtwn_fw_cmd\n")); 849 memcpy(cmd.msg, buf, len); 850 851 /* Write the first word last since that will trigger the FW. */ 852 rtwn_write_2(sc, R92C_HMEBOX_EXT(sc->fwcur), *((uint8_t *)&cmd + 4)); 853 rtwn_write_4(sc, R92C_HMEBOX(sc->fwcur), *((uint8_t *)&cmd + 0)); 854 855 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX; 856 857 /* Give firmware some time for processing. */ 858 DELAY(2000); 859 860 return (0); 861 } 862 863 static void 864 rtwn_rf_write(struct rtwn_softc *sc, int chain, uint8_t addr, uint32_t val) 865 { 866 rtwn_bb_write(sc, R92C_LSSI_PARAM(chain), 867 SM(R92C_LSSI_PARAM_ADDR, addr) | 868 SM(R92C_LSSI_PARAM_DATA, val)); 869 } 870 871 static uint32_t 872 rtwn_rf_read(struct rtwn_softc *sc, int chain, uint8_t addr) 873 { 874 uint32_t reg[R92C_MAX_CHAINS], val; 875 876 reg[0] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)); 877 if (chain != 0) 878 reg[chain] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(chain)); 879 880 rtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 881 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE); 882 DELAY(1000); 883 884 rtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), 885 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) | 886 R92C_HSSI_PARAM2_READ_EDGE); 887 DELAY(1000); 888 889 rtwn_bb_write(sc, R92C_HSSI_PARAM2(0), 890 reg[0] | R92C_HSSI_PARAM2_READ_EDGE); 891 DELAY(1000); 892 893 if (rtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI) 894 val = rtwn_bb_read(sc, R92C_HSPI_READBACK(chain)); 895 else 896 val = rtwn_bb_read(sc, R92C_LSSI_READBACK(chain)); 897 return (MS(val, R92C_LSSI_READBACK_DATA)); 898 } 899 900 static int 901 rtwn_llt_write(struct rtwn_softc *sc, uint32_t addr, uint32_t data) 902 { 903 int ntries; 904 905 rtwn_write_4(sc, R92C_LLT_INIT, 906 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) | 907 SM(R92C_LLT_INIT_ADDR, addr) | 908 SM(R92C_LLT_INIT_DATA, data)); 909 /* Wait for write operation to complete. */ 910 for (ntries = 0; ntries < 20; ntries++) { 911 if (MS(rtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) == 912 R92C_LLT_INIT_OP_NO_ACTIVE) 913 return (0); 914 DELAY(5); 915 } 916 return (ETIMEDOUT); 917 } 918 919 static uint8_t 920 rtwn_efuse_read_1(struct rtwn_softc *sc, uint16_t addr) 921 { 922 uint32_t reg; 923 int ntries; 924 925 reg = rtwn_read_4(sc, R92C_EFUSE_CTRL); 926 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr); 927 reg &= ~R92C_EFUSE_CTRL_VALID; 928 rtwn_write_4(sc, R92C_EFUSE_CTRL, reg); 929 /* Wait for read operation to complete. */ 930 for (ntries = 0; ntries < 100; ntries++) { 931 reg = rtwn_read_4(sc, R92C_EFUSE_CTRL); 932 if (reg & R92C_EFUSE_CTRL_VALID) 933 return (MS(reg, R92C_EFUSE_CTRL_DATA)); 934 DELAY(5); 935 } 936 device_printf(sc->sc_dev, 937 "could not read efuse byte at address 0x%x\n", addr); 938 return (0xff); 939 } 940 941 static void 942 rtwn_efuse_read(struct rtwn_softc *sc) 943 { 944 uint8_t *rom = (uint8_t *)&sc->rom; 945 uint16_t addr = 0; 946 uint32_t reg; 947 uint8_t off, msk; 948 int i; 949 950 reg = rtwn_read_2(sc, R92C_SYS_ISO_CTRL); 951 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) { 952 rtwn_write_2(sc, R92C_SYS_ISO_CTRL, 953 reg | R92C_SYS_ISO_CTRL_PWC_EV12V); 954 } 955 reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN); 956 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) { 957 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 958 reg | R92C_SYS_FUNC_EN_ELDR); 959 } 960 reg = rtwn_read_2(sc, R92C_SYS_CLKR); 961 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) != 962 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) { 963 rtwn_write_2(sc, R92C_SYS_CLKR, 964 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M); 965 } 966 memset(&sc->rom, 0xff, sizeof(sc->rom)); 967 while (addr < 512) { 968 reg = rtwn_efuse_read_1(sc, addr); 969 if (reg == 0xff) 970 break; 971 addr++; 972 off = reg >> 4; 973 msk = reg & 0xf; 974 for (i = 0; i < 4; i++) { 975 if (msk & (1 << i)) 976 continue; 977 rom[off * 8 + i * 2 + 0] = 978 rtwn_efuse_read_1(sc, addr); 979 addr++; 980 rom[off * 8 + i * 2 + 1] = 981 rtwn_efuse_read_1(sc, addr); 982 addr++; 983 } 984 } 985 #ifdef RTWN_DEBUG 986 if (sc->sc_debug >= 2) { 987 /* Dump ROM content. */ 988 printf("\n"); 989 for (i = 0; i < sizeof(sc->rom); i++) 990 printf("%02x:", rom[i]); 991 printf("\n"); 992 } 993 #endif 994 } 995 996 static int 997 rtwn_read_chipid(struct rtwn_softc *sc) 998 { 999 uint32_t reg; 1000 1001 reg = rtwn_read_4(sc, R92C_SYS_CFG); 1002 if (reg & R92C_SYS_CFG_TRP_VAUX_EN) 1003 /* Unsupported test chip. */ 1004 return (EIO); 1005 1006 if (reg & R92C_SYS_CFG_TYPE_92C) { 1007 sc->chip |= RTWN_CHIP_92C; 1008 /* Check if it is a castrated 8192C. */ 1009 if (MS(rtwn_read_4(sc, R92C_HPON_FSM), 1010 R92C_HPON_FSM_CHIP_BONDING_ID) == 1011 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R) 1012 sc->chip |= RTWN_CHIP_92C_1T2R; 1013 } 1014 if (reg & R92C_SYS_CFG_VENDOR_UMC) { 1015 sc->chip |= RTWN_CHIP_UMC; 1016 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0) 1017 sc->chip |= RTWN_CHIP_UMC_A_CUT; 1018 } 1019 return (0); 1020 } 1021 1022 static void 1023 rtwn_read_rom(struct rtwn_softc *sc) 1024 { 1025 struct r92c_rom *rom = &sc->rom; 1026 1027 /* Read full ROM image. */ 1028 rtwn_efuse_read(sc); 1029 1030 if (rom->id != 0x8129) 1031 device_printf(sc->sc_dev, "invalid EEPROM ID 0x%x\n", rom->id); 1032 1033 /* XXX Weird but this is what the vendor driver does. */ 1034 sc->pa_setting = rtwn_efuse_read_1(sc, 0x1fa); 1035 DPRINTF(("PA setting=0x%x\n", sc->pa_setting)); 1036 1037 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE); 1038 1039 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY); 1040 DPRINTF(("regulatory type=%d\n", sc->regulatory)); 1041 1042 IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr); 1043 } 1044 1045 /* 1046 * Initialize rate adaptation in firmware. 1047 */ 1048 static int 1049 rtwn_ra_init(struct rtwn_softc *sc) 1050 { 1051 static const uint8_t map[] = 1052 { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 }; 1053 struct ieee80211com *ic = &sc->sc_ic; 1054 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1055 struct ieee80211_node *ni = ieee80211_ref_node(vap->iv_bss); 1056 struct ieee80211_rateset *rs = &ni->ni_rates; 1057 struct r92c_fw_cmd_macid_cfg cmd; 1058 uint32_t rates, basicrates; 1059 uint8_t mode; 1060 int maxrate, maxbasicrate, error, i, j; 1061 1062 /* Get normal and basic rates mask. */ 1063 rates = basicrates = 0; 1064 maxrate = maxbasicrate = 0; 1065 for (i = 0; i < rs->rs_nrates; i++) { 1066 /* Convert 802.11 rate to HW rate index. */ 1067 for (j = 0; j < nitems(map); j++) 1068 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j]) 1069 break; 1070 if (j == nitems(map)) /* Unknown rate, skip. */ 1071 continue; 1072 rates |= 1 << j; 1073 if (j > maxrate) 1074 maxrate = j; 1075 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) { 1076 basicrates |= 1 << j; 1077 if (j > maxbasicrate) 1078 maxbasicrate = j; 1079 } 1080 } 1081 if (ic->ic_curmode == IEEE80211_MODE_11B) 1082 mode = R92C_RAID_11B; 1083 else 1084 mode = R92C_RAID_11BG; 1085 DPRINTF(("mode=0x%x rates=0x%08x, basicrates=0x%08x\n", 1086 mode, rates, basicrates)); 1087 1088 /* Set rates mask for group addressed frames. */ 1089 cmd.macid = RTWN_MACID_BC | RTWN_MACID_VALID; 1090 cmd.mask = htole32(mode << 28 | basicrates); 1091 error = rtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1092 if (error != 0) { 1093 device_printf(sc->sc_dev, 1094 "could not add broadcast station\n"); 1095 return (error); 1096 } 1097 /* Set initial MRR rate. */ 1098 DPRINTF(("maxbasicrate=%d\n", maxbasicrate)); 1099 rtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BC), 1100 maxbasicrate); 1101 1102 /* Set rates mask for unicast frames. */ 1103 cmd.macid = RTWN_MACID_BSS | RTWN_MACID_VALID; 1104 cmd.mask = htole32(mode << 28 | rates); 1105 error = rtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd)); 1106 if (error != 0) { 1107 device_printf(sc->sc_dev, "could not add BSS station\n"); 1108 return (error); 1109 } 1110 /* Set initial MRR rate. */ 1111 DPRINTF(("maxrate=%d\n", maxrate)); 1112 rtwn_write_1(sc, R92C_INIDATA_RATE_SEL(RTWN_MACID_BSS), 1113 maxrate); 1114 1115 /* Configure Automatic Rate Fallback Register. */ 1116 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1117 if (rates & 0x0c) 1118 rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0d)); 1119 else 1120 rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0f)); 1121 } else 1122 rtwn_write_4(sc, R92C_ARFR(0), htole32(rates & 0x0ff5)); 1123 1124 /* Indicate highest supported rate. */ 1125 ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1]; 1126 return (0); 1127 } 1128 1129 static void 1130 rtwn_tsf_sync_enable(struct rtwn_softc *sc) 1131 { 1132 struct ieee80211com *ic = &sc->sc_ic; 1133 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1134 struct ieee80211_node *ni = vap->iv_bss; 1135 uint64_t tsf; 1136 1137 /* Enable TSF synchronization. */ 1138 rtwn_write_1(sc, R92C_BCN_CTRL, 1139 rtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0); 1140 1141 rtwn_write_1(sc, R92C_BCN_CTRL, 1142 rtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN); 1143 1144 /* Set initial TSF. */ 1145 memcpy(&tsf, ni->ni_tstamp.data, 8); 1146 tsf = le64toh(tsf); 1147 tsf = tsf - (tsf % (vap->iv_bss->ni_intval * IEEE80211_DUR_TU)); 1148 tsf -= IEEE80211_DUR_TU; 1149 rtwn_write_4(sc, R92C_TSFTR + 0, tsf); 1150 rtwn_write_4(sc, R92C_TSFTR + 4, tsf >> 32); 1151 1152 rtwn_write_1(sc, R92C_BCN_CTRL, 1153 rtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN); 1154 } 1155 1156 static void 1157 rtwn_set_led(struct rtwn_softc *sc, int led, int on) 1158 { 1159 uint8_t reg; 1160 1161 if (led == RTWN_LED_LINK) { 1162 reg = rtwn_read_1(sc, R92C_LEDCFG2) & 0xf0; 1163 if (!on) 1164 reg |= R92C_LEDCFG2_DIS; 1165 else 1166 reg |= R92C_LEDCFG2_EN; 1167 rtwn_write_1(sc, R92C_LEDCFG2, reg); 1168 sc->ledlink = on; /* Save LED state. */ 1169 } 1170 } 1171 1172 static void 1173 rtwn_calib_to(void *arg) 1174 { 1175 struct rtwn_softc *sc = arg; 1176 struct r92c_fw_cmd_rssi cmd; 1177 1178 if (sc->avg_pwdb != -1) { 1179 /* Indicate Rx signal strength to FW for rate adaptation. */ 1180 memset(&cmd, 0, sizeof(cmd)); 1181 cmd.macid = 0; /* BSS. */ 1182 cmd.pwdb = sc->avg_pwdb; 1183 DPRINTFN(3, ("sending RSSI command avg=%d\n", sc->avg_pwdb)); 1184 rtwn_fw_cmd(sc, R92C_CMD_RSSI_SETTING, &cmd, sizeof(cmd)); 1185 } 1186 1187 /* Do temperature compensation. */ 1188 rtwn_temp_calib(sc); 1189 1190 callout_reset(&sc->calib_to, hz * 2, rtwn_calib_to, sc); 1191 } 1192 1193 static int 1194 rtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1195 { 1196 struct rtwn_vap *rvp = RTWN_VAP(vap); 1197 struct ieee80211com *ic = vap->iv_ic; 1198 struct ieee80211_node *ni = vap->iv_bss; 1199 struct rtwn_softc *sc = ic->ic_softc; 1200 uint32_t reg; 1201 1202 IEEE80211_UNLOCK(ic); 1203 RTWN_LOCK(sc); 1204 1205 if (vap->iv_state == IEEE80211_S_RUN) { 1206 /* Stop calibration. */ 1207 callout_stop(&sc->calib_to); 1208 1209 /* Turn link LED off. */ 1210 rtwn_set_led(sc, RTWN_LED_LINK, 0); 1211 1212 /* Set media status to 'No Link'. */ 1213 reg = rtwn_read_4(sc, R92C_CR); 1214 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_NOLINK); 1215 rtwn_write_4(sc, R92C_CR, reg); 1216 1217 /* Stop Rx of data frames. */ 1218 rtwn_write_2(sc, R92C_RXFLTMAP2, 0); 1219 1220 /* Rest TSF. */ 1221 rtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03); 1222 1223 /* Disable TSF synchronization. */ 1224 rtwn_write_1(sc, R92C_BCN_CTRL, 1225 rtwn_read_1(sc, R92C_BCN_CTRL) | 1226 R92C_BCN_CTRL_DIS_TSF_UDT0); 1227 1228 /* Reset EDCA parameters. */ 1229 rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217); 1230 rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317); 1231 rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320); 1232 rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444); 1233 } 1234 switch (nstate) { 1235 case IEEE80211_S_INIT: 1236 /* Turn link LED off. */ 1237 rtwn_set_led(sc, RTWN_LED_LINK, 0); 1238 break; 1239 case IEEE80211_S_SCAN: 1240 if (vap->iv_state != IEEE80211_S_SCAN) { 1241 /* Allow Rx from any BSSID. */ 1242 rtwn_write_4(sc, R92C_RCR, 1243 rtwn_read_4(sc, R92C_RCR) & 1244 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN)); 1245 1246 /* Set gain for scanning. */ 1247 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1248 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1249 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1250 1251 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1252 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20); 1253 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1254 } 1255 1256 /* Make link LED blink during scan. */ 1257 rtwn_set_led(sc, RTWN_LED_LINK, !sc->ledlink); 1258 1259 /* Pause AC Tx queues. */ 1260 rtwn_write_1(sc, R92C_TXPAUSE, 1261 rtwn_read_1(sc, R92C_TXPAUSE) | 0x0f); 1262 break; 1263 case IEEE80211_S_AUTH: 1264 /* Set initial gain under link. */ 1265 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)); 1266 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1267 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); 1268 1269 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)); 1270 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32); 1271 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); 1272 rtwn_set_chan(sc, ic->ic_curchan, NULL); 1273 break; 1274 case IEEE80211_S_RUN: 1275 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 1276 /* Enable Rx of data frames. */ 1277 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1278 1279 /* Turn link LED on. */ 1280 rtwn_set_led(sc, RTWN_LED_LINK, 1); 1281 break; 1282 } 1283 1284 /* Set media status to 'Associated'. */ 1285 reg = rtwn_read_4(sc, R92C_CR); 1286 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 1287 rtwn_write_4(sc, R92C_CR, reg); 1288 1289 /* Set BSSID. */ 1290 rtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0])); 1291 rtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4])); 1292 1293 if (ic->ic_curmode == IEEE80211_MODE_11B) 1294 rtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0); 1295 else /* 802.11b/g */ 1296 rtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3); 1297 1298 /* Enable Rx of data frames. */ 1299 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 1300 1301 /* Flush all AC queues. */ 1302 rtwn_write_1(sc, R92C_TXPAUSE, 0); 1303 1304 /* Set beacon interval. */ 1305 rtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval); 1306 1307 /* Allow Rx from our BSSID only. */ 1308 rtwn_write_4(sc, R92C_RCR, 1309 rtwn_read_4(sc, R92C_RCR) | 1310 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN); 1311 1312 /* Enable TSF synchronization. */ 1313 rtwn_tsf_sync_enable(sc); 1314 1315 rtwn_write_1(sc, R92C_SIFS_CCK + 1, 10); 1316 rtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10); 1317 rtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10); 1318 rtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10); 1319 rtwn_write_1(sc, R92C_R2T_SIFS + 1, 10); 1320 rtwn_write_1(sc, R92C_T2T_SIFS + 1, 10); 1321 1322 /* Intialize rate adaptation. */ 1323 rtwn_ra_init(sc); 1324 /* Turn link LED on. */ 1325 rtwn_set_led(sc, RTWN_LED_LINK, 1); 1326 1327 sc->avg_pwdb = -1; /* Reset average RSSI. */ 1328 /* Reset temperature calibration state machine. */ 1329 sc->thcal_state = 0; 1330 sc->thcal_lctemp = 0; 1331 /* Start periodic calibration. */ 1332 callout_reset(&sc->calib_to, hz * 2, rtwn_calib_to, sc); 1333 break; 1334 default: 1335 break; 1336 } 1337 RTWN_UNLOCK(sc); 1338 IEEE80211_LOCK(ic); 1339 return (rvp->newstate(vap, nstate, arg)); 1340 } 1341 1342 static int 1343 rtwn_updateedca(struct ieee80211com *ic) 1344 { 1345 struct rtwn_softc *sc = ic->ic_softc; 1346 const uint16_t aci2reg[WME_NUM_AC] = { 1347 R92C_EDCA_BE_PARAM, 1348 R92C_EDCA_BK_PARAM, 1349 R92C_EDCA_VI_PARAM, 1350 R92C_EDCA_VO_PARAM 1351 }; 1352 int aci, aifs, slottime; 1353 1354 IEEE80211_LOCK(ic); 1355 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 1356 for (aci = 0; aci < WME_NUM_AC; aci++) { 1357 const struct wmeParams *ac = 1358 &ic->ic_wme.wme_chanParams.cap_wmeParams[aci]; 1359 /* AIFS[AC] = AIFSN[AC] * aSlotTime + aSIFSTime. */ 1360 aifs = ac->wmep_aifsn * slottime + 10; 1361 rtwn_write_4(sc, aci2reg[aci], 1362 SM(R92C_EDCA_PARAM_TXOP, ac->wmep_txopLimit) | 1363 SM(R92C_EDCA_PARAM_ECWMIN, ac->wmep_logcwmin) | 1364 SM(R92C_EDCA_PARAM_ECWMAX, ac->wmep_logcwmax) | 1365 SM(R92C_EDCA_PARAM_AIFS, aifs)); 1366 } 1367 IEEE80211_UNLOCK(ic); 1368 return (0); 1369 } 1370 1371 static void 1372 rtwn_update_avgrssi(struct rtwn_softc *sc, int rate, int8_t rssi) 1373 { 1374 int pwdb; 1375 1376 /* Convert antenna signal to percentage. */ 1377 if (rssi <= -100 || rssi >= 20) 1378 pwdb = 0; 1379 else if (rssi >= 0) 1380 pwdb = 100; 1381 else 1382 pwdb = 100 + rssi; 1383 if (rate <= 3) { 1384 /* CCK gain is smaller than OFDM/MCS gain. */ 1385 pwdb += 6; 1386 if (pwdb > 100) 1387 pwdb = 100; 1388 if (pwdb <= 14) 1389 pwdb -= 4; 1390 else if (pwdb <= 26) 1391 pwdb -= 8; 1392 else if (pwdb <= 34) 1393 pwdb -= 6; 1394 else if (pwdb <= 42) 1395 pwdb -= 2; 1396 } 1397 if (sc->avg_pwdb == -1) /* Init. */ 1398 sc->avg_pwdb = pwdb; 1399 else if (sc->avg_pwdb < pwdb) 1400 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1; 1401 else 1402 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20); 1403 DPRINTFN(4, ("PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb)); 1404 } 1405 1406 static int8_t 1407 rtwn_get_rssi(struct rtwn_softc *sc, int rate, void *physt) 1408 { 1409 static const int8_t cckoff[] = { 16, -12, -26, -46 }; 1410 struct r92c_rx_phystat *phy; 1411 struct r92c_rx_cck *cck; 1412 uint8_t rpt; 1413 int8_t rssi; 1414 1415 if (rate <= 3) { 1416 cck = (struct r92c_rx_cck *)physt; 1417 if (sc->sc_flags & RTWN_FLAG_CCK_HIPWR) { 1418 rpt = (cck->agc_rpt >> 5) & 0x3; 1419 rssi = (cck->agc_rpt & 0x1f) << 1; 1420 } else { 1421 rpt = (cck->agc_rpt >> 6) & 0x3; 1422 rssi = cck->agc_rpt & 0x3e; 1423 } 1424 rssi = cckoff[rpt] - rssi; 1425 } else { /* OFDM/HT. */ 1426 phy = (struct r92c_rx_phystat *)physt; 1427 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110; 1428 } 1429 return (rssi); 1430 } 1431 1432 static void 1433 rtwn_rx_frame(struct rtwn_softc *sc, struct r92c_rx_desc *rx_desc, 1434 struct rtwn_rx_data *rx_data, int desc_idx) 1435 { 1436 struct ieee80211com *ic = &sc->sc_ic; 1437 struct ieee80211_frame_min *wh; 1438 struct ieee80211_node *ni; 1439 struct r92c_rx_phystat *phy = NULL; 1440 uint32_t rxdw0, rxdw3; 1441 struct mbuf *m, *m1; 1442 bus_dma_segment_t segs[1]; 1443 bus_addr_t physaddr; 1444 uint8_t rate; 1445 int8_t rssi = 0, nf; 1446 int infosz, nsegs, pktlen, shift, error; 1447 1448 rxdw0 = le32toh(rx_desc->rxdw0); 1449 rxdw3 = le32toh(rx_desc->rxdw3); 1450 1451 if (__predict_false(rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR))) { 1452 /* 1453 * This should not happen since we setup our Rx filter 1454 * to not receive these frames. 1455 */ 1456 counter_u64_add(ic->ic_ierrors, 1); 1457 return; 1458 } 1459 1460 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN); 1461 if (__predict_false(pktlen < sizeof(struct ieee80211_frame_ack) || 1462 pktlen > MCLBYTES)) { 1463 counter_u64_add(ic->ic_ierrors, 1); 1464 return; 1465 } 1466 1467 rate = MS(rxdw3, R92C_RXDW3_RATE); 1468 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8; 1469 if (infosz > sizeof(struct r92c_rx_phystat)) 1470 infosz = sizeof(struct r92c_rx_phystat); 1471 shift = MS(rxdw0, R92C_RXDW0_SHIFT); 1472 1473 /* Get RSSI from PHY status descriptor if present. */ 1474 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) { 1475 phy = mtod(rx_data->m, struct r92c_rx_phystat *); 1476 rssi = rtwn_get_rssi(sc, rate, phy); 1477 /* Update our average RSSI. */ 1478 rtwn_update_avgrssi(sc, rate, rssi); 1479 } 1480 1481 DPRINTFN(5, ("Rx frame len=%d rate=%d infosz=%d shift=%d rssi=%d\n", 1482 pktlen, rate, infosz, shift, rssi)); 1483 1484 m1 = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1485 if (m1 == NULL) { 1486 counter_u64_add(ic->ic_ierrors, 1); 1487 return; 1488 } 1489 bus_dmamap_unload(sc->rx_ring.data_dmat, rx_data->map); 1490 1491 error = bus_dmamap_load(sc->rx_ring.data_dmat, rx_data->map, 1492 mtod(m1, void *), MCLBYTES, rtwn_dma_map_addr, 1493 &physaddr, 0); 1494 if (error != 0) { 1495 m_freem(m1); 1496 1497 if (bus_dmamap_load_mbuf_sg(sc->rx_ring.data_dmat, 1498 rx_data->map, rx_data->m, segs, &nsegs, 0)) 1499 panic("%s: could not load old RX mbuf", 1500 device_get_name(sc->sc_dev)); 1501 1502 /* Physical address may have changed. */ 1503 rtwn_setup_rx_desc(sc, rx_desc, physaddr, MCLBYTES, desc_idx); 1504 counter_u64_add(ic->ic_ierrors, 1); 1505 return; 1506 } 1507 1508 /* Finalize mbuf. */ 1509 m = rx_data->m; 1510 rx_data->m = m1; 1511 m->m_pkthdr.len = m->m_len = pktlen + infosz + shift; 1512 1513 /* Update RX descriptor. */ 1514 rtwn_setup_rx_desc(sc, rx_desc, physaddr, MCLBYTES, desc_idx); 1515 1516 /* Get ieee80211 frame header. */ 1517 if (rxdw0 & R92C_RXDW0_PHYST) 1518 m_adj(m, infosz + shift); 1519 else 1520 m_adj(m, shift); 1521 1522 nf = -95; 1523 if (ieee80211_radiotap_active(ic)) { 1524 struct rtwn_rx_radiotap_header *tap = &sc->sc_rxtap; 1525 1526 tap->wr_flags = 0; 1527 if (!(rxdw3 & R92C_RXDW3_HT)) { 1528 switch (rate) { 1529 /* CCK. */ 1530 case 0: tap->wr_rate = 2; break; 1531 case 1: tap->wr_rate = 4; break; 1532 case 2: tap->wr_rate = 11; break; 1533 case 3: tap->wr_rate = 22; break; 1534 /* OFDM. */ 1535 case 4: tap->wr_rate = 12; break; 1536 case 5: tap->wr_rate = 18; break; 1537 case 6: tap->wr_rate = 24; break; 1538 case 7: tap->wr_rate = 36; break; 1539 case 8: tap->wr_rate = 48; break; 1540 case 9: tap->wr_rate = 72; break; 1541 case 10: tap->wr_rate = 96; break; 1542 case 11: tap->wr_rate = 108; break; 1543 } 1544 } else if (rate >= 12) { /* MCS0~15. */ 1545 /* Bit 7 set means HT MCS instead of rate. */ 1546 tap->wr_rate = 0x80 | (rate - 12); 1547 } 1548 tap->wr_dbm_antsignal = rssi; 1549 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 1550 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 1551 } 1552 1553 RTWN_UNLOCK(sc); 1554 wh = mtod(m, struct ieee80211_frame_min *); 1555 if (m->m_len >= sizeof(*wh)) 1556 ni = ieee80211_find_rxnode(ic, wh); 1557 else 1558 ni = NULL; 1559 1560 /* Send the frame to the 802.11 layer. */ 1561 if (ni != NULL) { 1562 (void)ieee80211_input(ni, m, rssi - nf, nf); 1563 /* Node is no longer needed. */ 1564 ieee80211_free_node(ni); 1565 } else 1566 (void)ieee80211_input_all(ic, m, rssi - nf, nf); 1567 1568 RTWN_LOCK(sc); 1569 } 1570 1571 static int 1572 rtwn_tx(struct rtwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni) 1573 { 1574 struct ieee80211com *ic = &sc->sc_ic; 1575 struct ieee80211vap *vap = ni->ni_vap; 1576 struct ieee80211_frame *wh; 1577 struct ieee80211_key *k = NULL; 1578 struct rtwn_tx_ring *tx_ring; 1579 struct rtwn_tx_data *data; 1580 struct r92c_tx_desc *txd; 1581 bus_dma_segment_t segs[1]; 1582 uint16_t qos; 1583 uint8_t raid, type, tid, qid; 1584 int nsegs, error; 1585 1586 wh = mtod(m, struct ieee80211_frame *); 1587 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1588 1589 /* Encrypt the frame if need be. */ 1590 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1591 k = ieee80211_crypto_encap(ni, m); 1592 if (k == NULL) { 1593 m_freem(m); 1594 return (ENOBUFS); 1595 } 1596 /* 802.11 header may have moved. */ 1597 wh = mtod(m, struct ieee80211_frame *); 1598 } 1599 1600 if (IEEE80211_QOS_HAS_SEQ(wh)) { 1601 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0]; 1602 tid = qos & IEEE80211_QOS_TID; 1603 } else { 1604 qos = 0; 1605 tid = 0; 1606 } 1607 1608 switch (type) { 1609 case IEEE80211_FC0_TYPE_CTL: 1610 case IEEE80211_FC0_TYPE_MGT: 1611 qid = RTWN_VO_QUEUE; 1612 break; 1613 default: 1614 qid = M_WME_GETAC(m); 1615 break; 1616 } 1617 1618 /* Grab a Tx buffer from the ring. */ 1619 tx_ring = &sc->tx_ring[qid]; 1620 data = &tx_ring->tx_data[tx_ring->cur]; 1621 if (data->m != NULL) { 1622 m_freem(m); 1623 return (ENOBUFS); 1624 } 1625 1626 /* Fill Tx descriptor. */ 1627 txd = &tx_ring->desc[tx_ring->cur]; 1628 if (htole32(txd->txdw0) & R92C_RXDW0_OWN) { 1629 m_freem(m); 1630 return (ENOBUFS); 1631 } 1632 txd->txdw0 = htole32( 1633 SM(R92C_TXDW0_PKTLEN, m->m_pkthdr.len) | 1634 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) | 1635 R92C_TXDW0_FSG | R92C_TXDW0_LSG); 1636 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1637 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST); 1638 1639 txd->txdw1 = 0; 1640 txd->txdw4 = 0; 1641 txd->txdw5 = 0; 1642 1643 /* XXX TODO: rate control; implement low-rate for EAPOL */ 1644 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 1645 type == IEEE80211_FC0_TYPE_DATA) { 1646 if (ic->ic_curmode == IEEE80211_MODE_11B) 1647 raid = R92C_RAID_11B; 1648 else 1649 raid = R92C_RAID_11BG; 1650 txd->txdw1 |= htole32( 1651 SM(R92C_TXDW1_MACID, RTWN_MACID_BSS) | 1652 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) | 1653 SM(R92C_TXDW1_RAID, raid) | 1654 R92C_TXDW1_AGGBK); 1655 1656 if (ic->ic_flags & IEEE80211_F_USEPROT) { 1657 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 1658 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF | 1659 R92C_TXDW4_HWRTSEN); 1660 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) { 1661 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN | 1662 R92C_TXDW4_HWRTSEN); 1663 } 1664 } 1665 1666 /* XXX TODO: implement rate control */ 1667 1668 /* Send RTS at OFDM24. */ 1669 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8)); 1670 txd->txdw5 |= htole32(SM(R92C_TXDW5_RTSRATE_FBLIMIT, 0xf)); 1671 /* Send data at OFDM54. */ 1672 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11)); 1673 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE_FBLIMIT, 0x1f)); 1674 1675 } else { 1676 txd->txdw1 |= htole32( 1677 SM(R92C_TXDW1_MACID, 0) | 1678 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) | 1679 SM(R92C_TXDW1_RAID, R92C_RAID_11B)); 1680 1681 /* Force CCK1. */ 1682 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE); 1683 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0)); 1684 } 1685 /* Set sequence number (already little endian). */ 1686 txd->txdseq = htole16(M_SEQNO_GET(m) % IEEE80211_SEQ_RANGE); 1687 1688 if (!qos) { 1689 /* Use HW sequence numbering for non-QoS frames. */ 1690 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ); 1691 txd->txdseq |= htole16(0x8000); 1692 } else 1693 txd->txdw4 |= htole32(R92C_TXDW4_QOS); 1694 1695 error = bus_dmamap_load_mbuf_sg(tx_ring->data_dmat, data->map, m, segs, 1696 &nsegs, BUS_DMA_NOWAIT); 1697 if (error != 0 && error != EFBIG) { 1698 device_printf(sc->sc_dev, "can't map mbuf (error %d)\n", error); 1699 m_freem(m); 1700 return (error); 1701 } 1702 if (error != 0) { 1703 struct mbuf *mnew; 1704 1705 mnew = m_defrag(m, M_NOWAIT); 1706 if (mnew == NULL) { 1707 device_printf(sc->sc_dev, 1708 "can't defragment mbuf\n"); 1709 m_freem(m); 1710 return (ENOBUFS); 1711 } 1712 m = mnew; 1713 1714 error = bus_dmamap_load_mbuf_sg(tx_ring->data_dmat, data->map, 1715 m, segs, &nsegs, BUS_DMA_NOWAIT); 1716 if (error != 0) { 1717 device_printf(sc->sc_dev, 1718 "can't map mbuf (error %d)\n", error); 1719 m_freem(m); 1720 return (error); 1721 } 1722 } 1723 1724 txd->txbufaddr = htole32(segs[0].ds_addr); 1725 txd->txbufsize = htole16(m->m_pkthdr.len); 1726 bus_space_barrier(sc->sc_st, sc->sc_sh, 0, sc->sc_mapsize, 1727 BUS_SPACE_BARRIER_WRITE); 1728 txd->txdw0 |= htole32(R92C_TXDW0_OWN); 1729 1730 bus_dmamap_sync(tx_ring->desc_dmat, tx_ring->desc_map, 1731 BUS_DMASYNC_POSTWRITE); 1732 bus_dmamap_sync(tx_ring->data_dmat, data->map, BUS_DMASYNC_POSTWRITE); 1733 1734 data->m = m; 1735 data->ni = ni; 1736 1737 if (ieee80211_radiotap_active_vap(vap)) { 1738 struct rtwn_tx_radiotap_header *tap = &sc->sc_txtap; 1739 1740 tap->wt_flags = 0; 1741 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1742 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1743 1744 ieee80211_radiotap_tx(vap, m); 1745 } 1746 1747 tx_ring->cur = (tx_ring->cur + 1) % RTWN_TX_LIST_COUNT; 1748 tx_ring->queued++; 1749 1750 if (tx_ring->queued >= (RTWN_TX_LIST_COUNT - 1)) 1751 sc->qfullmsk |= (1 << qid); 1752 1753 /* Kick TX. */ 1754 rtwn_write_2(sc, R92C_PCIE_CTRL_REG, (1 << qid)); 1755 return (0); 1756 } 1757 1758 static void 1759 rtwn_tx_done(struct rtwn_softc *sc, int qid) 1760 { 1761 struct rtwn_tx_ring *tx_ring = &sc->tx_ring[qid]; 1762 struct rtwn_tx_data *tx_data; 1763 struct r92c_tx_desc *tx_desc; 1764 int i; 1765 1766 bus_dmamap_sync(tx_ring->desc_dmat, tx_ring->desc_map, 1767 BUS_DMASYNC_POSTREAD); 1768 1769 for (i = 0; i < RTWN_TX_LIST_COUNT; i++) { 1770 tx_data = &tx_ring->tx_data[i]; 1771 if (tx_data->m == NULL) 1772 continue; 1773 1774 tx_desc = &tx_ring->desc[i]; 1775 if (le32toh(tx_desc->txdw0) & R92C_TXDW0_OWN) 1776 continue; 1777 1778 bus_dmamap_unload(tx_ring->desc_dmat, tx_ring->desc_map); 1779 1780 /* 1781 * XXX TODO: figure out whether the transmit succeeded or not. 1782 * .. and then notify rate control. 1783 */ 1784 ieee80211_tx_complete(tx_data->ni, tx_data->m, 0); 1785 tx_data->ni = NULL; 1786 tx_data->m = NULL; 1787 1788 sc->sc_tx_timer = 0; 1789 tx_ring->queued--; 1790 } 1791 1792 if (tx_ring->queued < (RTWN_TX_LIST_COUNT - 1)) 1793 sc->qfullmsk &= ~(1 << qid); 1794 rtwn_start(sc); 1795 } 1796 1797 static int 1798 rtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1799 const struct ieee80211_bpf_params *params) 1800 { 1801 struct ieee80211com *ic = ni->ni_ic; 1802 struct rtwn_softc *sc = ic->ic_softc; 1803 1804 RTWN_LOCK(sc); 1805 1806 /* Prevent management frames from being sent if we're not ready. */ 1807 if (!(sc->sc_flags & RTWN_RUNNING)) { 1808 RTWN_UNLOCK(sc); 1809 m_freem(m); 1810 return (ENETDOWN); 1811 } 1812 1813 if (rtwn_tx(sc, m, ni) != 0) { 1814 m_freem(m); 1815 RTWN_UNLOCK(sc); 1816 return (EIO); 1817 } 1818 sc->sc_tx_timer = 5; 1819 RTWN_UNLOCK(sc); 1820 return (0); 1821 } 1822 1823 static int 1824 rtwn_transmit(struct ieee80211com *ic, struct mbuf *m) 1825 { 1826 struct rtwn_softc *sc = ic->ic_softc; 1827 int error; 1828 1829 RTWN_LOCK(sc); 1830 if ((sc->sc_flags & RTWN_RUNNING) == 0) { 1831 RTWN_UNLOCK(sc); 1832 return (ENXIO); 1833 } 1834 error = mbufq_enqueue(&sc->sc_snd, m); 1835 if (error) { 1836 RTWN_UNLOCK(sc); 1837 return (error); 1838 } 1839 rtwn_start(sc); 1840 RTWN_UNLOCK(sc); 1841 return (0); 1842 } 1843 1844 static void 1845 rtwn_parent(struct ieee80211com *ic) 1846 { 1847 struct rtwn_softc *sc = ic->ic_softc; 1848 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1849 1850 if (ic->ic_nrunning > 0) { 1851 if (rtwn_init(sc) == 0) 1852 ieee80211_start_all(ic); 1853 else 1854 ieee80211_stop(vap); 1855 } else 1856 rtwn_stop(sc); 1857 } 1858 1859 static void 1860 rtwn_start(struct rtwn_softc *sc) 1861 { 1862 struct ieee80211_node *ni; 1863 struct mbuf *m; 1864 1865 RTWN_LOCK_ASSERT(sc); 1866 1867 if ((sc->sc_flags & RTWN_RUNNING) == 0) 1868 return; 1869 1870 while (sc->qfullmsk == 0 && (m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1871 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1872 if (rtwn_tx(sc, m, ni) != 0) { 1873 if_inc_counter(ni->ni_vap->iv_ifp, 1874 IFCOUNTER_OERRORS, 1); 1875 ieee80211_free_node(ni); 1876 continue; 1877 } 1878 sc->sc_tx_timer = 5; 1879 } 1880 } 1881 1882 static void 1883 rtwn_watchdog(void *arg) 1884 { 1885 struct rtwn_softc *sc = arg; 1886 struct ieee80211com *ic = &sc->sc_ic; 1887 1888 RTWN_LOCK_ASSERT(sc); 1889 1890 KASSERT(sc->sc_flags & RTWN_RUNNING, ("not running")); 1891 1892 if (sc->sc_tx_timer != 0 && --sc->sc_tx_timer == 0) { 1893 ic_printf(ic, "device timeout\n"); 1894 ieee80211_restart_all(ic); 1895 return; 1896 } 1897 callout_reset(&sc->watchdog_to, hz, rtwn_watchdog, sc); 1898 } 1899 1900 static int 1901 rtwn_power_on(struct rtwn_softc *sc) 1902 { 1903 uint32_t reg; 1904 int ntries; 1905 1906 /* Wait for autoload done bit. */ 1907 for (ntries = 0; ntries < 1000; ntries++) { 1908 if (rtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN) 1909 break; 1910 DELAY(5); 1911 } 1912 if (ntries == 1000) { 1913 device_printf(sc->sc_dev, 1914 "timeout waiting for chip autoload\n"); 1915 return (ETIMEDOUT); 1916 } 1917 1918 /* Unlock ISO/CLK/Power control register. */ 1919 rtwn_write_1(sc, R92C_RSV_CTRL, 0); 1920 1921 /* TODO: check if we need this for 8188CE */ 1922 if (sc->board_type != R92C_BOARD_TYPE_DONGLE) { 1923 /* bt coex */ 1924 reg = rtwn_read_4(sc, R92C_APS_FSMCO); 1925 reg |= (R92C_APS_FSMCO_SOP_ABG | 1926 R92C_APS_FSMCO_SOP_AMB | 1927 R92C_APS_FSMCO_XOP_BTCK); 1928 rtwn_write_4(sc, R92C_APS_FSMCO, reg); 1929 } 1930 1931 /* Move SPS into PWM mode. */ 1932 rtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b); 1933 1934 /* Set low byte to 0x0f, leave others unchanged. */ 1935 rtwn_write_4(sc, R92C_AFE_XTAL_CTRL, 1936 (rtwn_read_4(sc, R92C_AFE_XTAL_CTRL) & 0xffffff00) | 0x0f); 1937 1938 /* TODO: check if we need this for 8188CE */ 1939 if (sc->board_type != R92C_BOARD_TYPE_DONGLE) { 1940 /* bt coex */ 1941 reg = rtwn_read_4(sc, R92C_AFE_XTAL_CTRL); 1942 reg &= (~0x00024800); /* XXX magic from linux */ 1943 rtwn_write_4(sc, R92C_AFE_XTAL_CTRL, reg); 1944 } 1945 1946 rtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1947 (rtwn_read_2(sc, R92C_SYS_ISO_CTRL) & 0xff) | 1948 R92C_SYS_ISO_CTRL_PWC_EV12V | R92C_SYS_ISO_CTRL_DIOR); 1949 DELAY(200); 1950 1951 /* TODO: linux does additional btcoex stuff here */ 1952 1953 /* Auto enable WLAN. */ 1954 rtwn_write_2(sc, R92C_APS_FSMCO, 1955 rtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC); 1956 for (ntries = 0; ntries < 1000; ntries++) { 1957 if (!(rtwn_read_2(sc, R92C_APS_FSMCO) & 1958 R92C_APS_FSMCO_APFM_ONMAC)) 1959 break; 1960 DELAY(5); 1961 } 1962 if (ntries == 1000) { 1963 device_printf(sc->sc_dev, "timeout waiting for MAC auto ON\n"); 1964 return (ETIMEDOUT); 1965 } 1966 1967 /* Enable radio, GPIO and LED functions. */ 1968 rtwn_write_2(sc, R92C_APS_FSMCO, 1969 R92C_APS_FSMCO_AFSM_PCIE | 1970 R92C_APS_FSMCO_PDN_EN | 1971 R92C_APS_FSMCO_PFM_ALDN); 1972 /* Release RF digital isolation. */ 1973 rtwn_write_2(sc, R92C_SYS_ISO_CTRL, 1974 rtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR); 1975 1976 if (sc->chip & RTWN_CHIP_92C) 1977 rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 3, 0x77); 1978 else 1979 rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 3, 0x22); 1980 1981 rtwn_write_4(sc, R92C_INT_MIG, 0); 1982 1983 if (sc->board_type != R92C_BOARD_TYPE_DONGLE) { 1984 /* bt coex */ 1985 reg = rtwn_read_4(sc, R92C_AFE_XTAL_CTRL + 2); 1986 reg &= 0xfd; /* XXX magic from linux */ 1987 rtwn_write_4(sc, R92C_AFE_XTAL_CTRL + 2, reg); 1988 } 1989 1990 rtwn_write_1(sc, R92C_GPIO_MUXCFG, 1991 rtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_RFKILL); 1992 1993 reg = rtwn_read_1(sc, R92C_GPIO_IO_SEL); 1994 if (!(reg & R92C_GPIO_IO_SEL_RFKILL)) { 1995 device_printf(sc->sc_dev, 1996 "radio is disabled by hardware switch\n"); 1997 return (EPERM); 1998 } 1999 2000 /* Initialize MAC. */ 2001 reg = rtwn_read_1(sc, R92C_APSD_CTRL); 2002 rtwn_write_1(sc, R92C_APSD_CTRL, 2003 rtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF); 2004 for (ntries = 0; ntries < 200; ntries++) { 2005 if (!(rtwn_read_1(sc, R92C_APSD_CTRL) & 2006 R92C_APSD_CTRL_OFF_STATUS)) 2007 break; 2008 DELAY(500); 2009 } 2010 if (ntries == 200) { 2011 device_printf(sc->sc_dev, 2012 "timeout waiting for MAC initialization\n"); 2013 return (ETIMEDOUT); 2014 } 2015 2016 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */ 2017 reg = rtwn_read_2(sc, R92C_CR); 2018 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 2019 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 2020 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 2021 R92C_CR_ENSEC; 2022 rtwn_write_2(sc, R92C_CR, reg); 2023 2024 rtwn_write_1(sc, 0xfe10, 0x19); 2025 2026 return (0); 2027 } 2028 2029 static int 2030 rtwn_llt_init(struct rtwn_softc *sc) 2031 { 2032 int i, error; 2033 2034 /* Reserve pages [0; R92C_TX_PAGE_COUNT]. */ 2035 for (i = 0; i < R92C_TX_PAGE_COUNT; i++) { 2036 if ((error = rtwn_llt_write(sc, i, i + 1)) != 0) 2037 return (error); 2038 } 2039 /* NB: 0xff indicates end-of-list. */ 2040 if ((error = rtwn_llt_write(sc, i, 0xff)) != 0) 2041 return (error); 2042 /* 2043 * Use pages [R92C_TX_PAGE_COUNT + 1; R92C_TXPKTBUF_COUNT - 1] 2044 * as ring buffer. 2045 */ 2046 for (++i; i < R92C_TXPKTBUF_COUNT - 1; i++) { 2047 if ((error = rtwn_llt_write(sc, i, i + 1)) != 0) 2048 return (error); 2049 } 2050 /* Make the last page point to the beginning of the ring buffer. */ 2051 error = rtwn_llt_write(sc, i, R92C_TX_PAGE_COUNT + 1); 2052 return (error); 2053 } 2054 2055 static void 2056 rtwn_fw_reset(struct rtwn_softc *sc) 2057 { 2058 uint16_t reg; 2059 int ntries; 2060 2061 /* Tell 8051 to reset itself. */ 2062 rtwn_write_1(sc, R92C_HMETFR + 3, 0x20); 2063 2064 /* Wait until 8051 resets by itself. */ 2065 for (ntries = 0; ntries < 100; ntries++) { 2066 reg = rtwn_read_2(sc, R92C_SYS_FUNC_EN); 2067 if (!(reg & R92C_SYS_FUNC_EN_CPUEN)) 2068 goto sleep; 2069 DELAY(50); 2070 } 2071 /* Force 8051 reset. */ 2072 rtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN); 2073 sleep: 2074 /* 2075 * We must sleep for one second to let the firmware settle. 2076 * Accessing registers too early will hang the whole system. 2077 */ 2078 if (msleep(®, &sc->sc_mtx, 0, "rtwnrst", hz)) { 2079 device_printf(sc->sc_dev, "timeout waiting for firmware " 2080 "initialization to complete\n"); 2081 } 2082 } 2083 2084 static void 2085 rtwn_fw_loadpage(struct rtwn_softc *sc, int page, const uint8_t *buf, int len) 2086 { 2087 uint32_t reg; 2088 int off, mlen, i; 2089 2090 reg = rtwn_read_4(sc, R92C_MCUFWDL); 2091 reg = RW(reg, R92C_MCUFWDL_PAGE, page); 2092 rtwn_write_4(sc, R92C_MCUFWDL, reg); 2093 2094 DELAY(5); 2095 2096 off = R92C_FW_START_ADDR; 2097 while (len > 0) { 2098 if (len > 196) 2099 mlen = 196; 2100 else if (len > 4) 2101 mlen = 4; 2102 else 2103 mlen = 1; 2104 for (i = 0; i < mlen; i++) 2105 rtwn_write_1(sc, off++, buf[i]); 2106 buf += mlen; 2107 len -= mlen; 2108 } 2109 } 2110 2111 static int 2112 rtwn_load_firmware(struct rtwn_softc *sc) 2113 { 2114 const struct firmware *fw; 2115 const struct r92c_fw_hdr *hdr; 2116 const char *name; 2117 const u_char *ptr; 2118 size_t len; 2119 uint32_t reg; 2120 int mlen, ntries, page, error = 0; 2121 2122 /* Read firmware image from the filesystem. */ 2123 if ((sc->chip & (RTWN_CHIP_UMC_A_CUT | RTWN_CHIP_92C)) == 2124 RTWN_CHIP_UMC_A_CUT) 2125 name = "rtwn-rtl8192cfwU"; 2126 else 2127 name = "rtwn-rtl8192cfwU_B"; 2128 RTWN_UNLOCK(sc); 2129 fw = firmware_get(name); 2130 RTWN_LOCK(sc); 2131 if (fw == NULL) { 2132 device_printf(sc->sc_dev, 2133 "could not read firmware %s\n", name); 2134 return (ENOENT); 2135 } 2136 len = fw->datasize; 2137 if (len < sizeof(*hdr)) { 2138 device_printf(sc->sc_dev, "firmware too short\n"); 2139 error = EINVAL; 2140 goto fail; 2141 } 2142 ptr = fw->data; 2143 hdr = (const struct r92c_fw_hdr *)ptr; 2144 /* Check if there is a valid FW header and skip it. */ 2145 if ((le16toh(hdr->signature) >> 4) == 0x88c || 2146 (le16toh(hdr->signature) >> 4) == 0x92c) { 2147 DPRINTF(("FW V%d.%d %02d-%02d %02d:%02d\n", 2148 le16toh(hdr->version), le16toh(hdr->subversion), 2149 hdr->month, hdr->date, hdr->hour, hdr->minute)); 2150 ptr += sizeof(*hdr); 2151 len -= sizeof(*hdr); 2152 } 2153 2154 if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) 2155 rtwn_fw_reset(sc); 2156 2157 /* Enable FW download. */ 2158 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 2159 rtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2160 R92C_SYS_FUNC_EN_CPUEN); 2161 rtwn_write_1(sc, R92C_MCUFWDL, 2162 rtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN); 2163 rtwn_write_1(sc, R92C_MCUFWDL + 2, 2164 rtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08); 2165 2166 /* Reset the FWDL checksum. */ 2167 rtwn_write_1(sc, R92C_MCUFWDL, 2168 rtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_CHKSUM_RPT); 2169 2170 for (page = 0; len > 0; page++) { 2171 mlen = MIN(len, R92C_FW_PAGE_SIZE); 2172 rtwn_fw_loadpage(sc, page, ptr, mlen); 2173 ptr += mlen; 2174 len -= mlen; 2175 } 2176 2177 /* Disable FW download. */ 2178 rtwn_write_1(sc, R92C_MCUFWDL, 2179 rtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN); 2180 rtwn_write_1(sc, R92C_MCUFWDL + 1, 0); 2181 2182 /* Wait for checksum report. */ 2183 for (ntries = 0; ntries < 1000; ntries++) { 2184 if (rtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT) 2185 break; 2186 DELAY(5); 2187 } 2188 if (ntries == 1000) { 2189 device_printf(sc->sc_dev, 2190 "timeout waiting for checksum report\n"); 2191 error = ETIMEDOUT; 2192 goto fail; 2193 } 2194 2195 reg = rtwn_read_4(sc, R92C_MCUFWDL); 2196 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY; 2197 rtwn_write_4(sc, R92C_MCUFWDL, reg); 2198 /* Wait for firmware readiness. */ 2199 for (ntries = 0; ntries < 2000; ntries++) { 2200 if (rtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY) 2201 break; 2202 DELAY(50); 2203 } 2204 if (ntries == 1000) { 2205 device_printf(sc->sc_dev, 2206 "timeout waiting for firmware readiness\n"); 2207 error = ETIMEDOUT; 2208 goto fail; 2209 } 2210 fail: 2211 firmware_put(fw, FIRMWARE_UNLOAD); 2212 return (error); 2213 } 2214 2215 static int 2216 rtwn_dma_init(struct rtwn_softc *sc) 2217 { 2218 uint32_t reg; 2219 int error; 2220 2221 /* Initialize LLT table. */ 2222 error = rtwn_llt_init(sc); 2223 if (error != 0) 2224 return error; 2225 2226 /* Set number of pages for normal priority queue. */ 2227 rtwn_write_2(sc, R92C_RQPN_NPQ, 0); 2228 rtwn_write_4(sc, R92C_RQPN, 2229 /* Set number of pages for public queue. */ 2230 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) | 2231 /* Set number of pages for high priority queue. */ 2232 SM(R92C_RQPN_HPQ, R92C_HPQ_NPAGES) | 2233 /* Set number of pages for low priority queue. */ 2234 SM(R92C_RQPN_LPQ, R92C_LPQ_NPAGES) | 2235 /* Load values. */ 2236 R92C_RQPN_LD); 2237 2238 rtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2239 rtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY); 2240 rtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY); 2241 rtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY); 2242 rtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY); 2243 2244 reg = rtwn_read_2(sc, R92C_TRXDMA_CTRL); 2245 reg &= ~R92C_TRXDMA_CTRL_QMAP_M; 2246 reg |= 0xF771; 2247 rtwn_write_2(sc, R92C_TRXDMA_CTRL, reg); 2248 2249 rtwn_write_4(sc, R92C_TCR, R92C_TCR_CFENDFORM | (1 << 12) | (1 << 13)); 2250 2251 /* Configure Tx DMA. */ 2252 rtwn_write_4(sc, R92C_BKQ_DESA, sc->tx_ring[RTWN_BK_QUEUE].paddr); 2253 rtwn_write_4(sc, R92C_BEQ_DESA, sc->tx_ring[RTWN_BE_QUEUE].paddr); 2254 rtwn_write_4(sc, R92C_VIQ_DESA, sc->tx_ring[RTWN_VI_QUEUE].paddr); 2255 rtwn_write_4(sc, R92C_VOQ_DESA, sc->tx_ring[RTWN_VO_QUEUE].paddr); 2256 rtwn_write_4(sc, R92C_BCNQ_DESA, sc->tx_ring[RTWN_BEACON_QUEUE].paddr); 2257 rtwn_write_4(sc, R92C_MGQ_DESA, sc->tx_ring[RTWN_MGNT_QUEUE].paddr); 2258 rtwn_write_4(sc, R92C_HQ_DESA, sc->tx_ring[RTWN_HIGH_QUEUE].paddr); 2259 2260 /* Configure Rx DMA. */ 2261 rtwn_write_4(sc, R92C_RX_DESA, sc->rx_ring.paddr); 2262 2263 /* Set Tx/Rx transfer page boundary. */ 2264 rtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff); 2265 2266 /* Set Tx/Rx transfer page size. */ 2267 rtwn_write_1(sc, R92C_PBP, 2268 SM(R92C_PBP_PSRX, R92C_PBP_128) | 2269 SM(R92C_PBP_PSTX, R92C_PBP_128)); 2270 return (0); 2271 } 2272 2273 static void 2274 rtwn_mac_init(struct rtwn_softc *sc) 2275 { 2276 int i; 2277 2278 /* Write MAC initialization values. */ 2279 for (i = 0; i < nitems(rtl8192ce_mac); i++) 2280 rtwn_write_1(sc, rtl8192ce_mac[i].reg, rtl8192ce_mac[i].val); 2281 } 2282 2283 static void 2284 rtwn_bb_init(struct rtwn_softc *sc) 2285 { 2286 const struct rtwn_bb_prog *prog; 2287 uint32_t reg; 2288 int i; 2289 2290 /* Enable BB and RF. */ 2291 rtwn_write_2(sc, R92C_SYS_FUNC_EN, 2292 rtwn_read_2(sc, R92C_SYS_FUNC_EN) | 2293 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST | 2294 R92C_SYS_FUNC_EN_DIO_RF); 2295 2296 rtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83); 2297 2298 rtwn_write_1(sc, R92C_RF_CTRL, 2299 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB); 2300 2301 rtwn_write_1(sc, R92C_SYS_FUNC_EN, 2302 R92C_SYS_FUNC_EN_DIO_PCIE | R92C_SYS_FUNC_EN_PCIEA | 2303 R92C_SYS_FUNC_EN_PPLL | R92C_SYS_FUNC_EN_BB_GLB_RST | 2304 R92C_SYS_FUNC_EN_BBRSTB); 2305 2306 rtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80); 2307 2308 rtwn_write_4(sc, R92C_LEDCFG0, 2309 rtwn_read_4(sc, R92C_LEDCFG0) | 0x00800000); 2310 2311 /* Select BB programming. */ 2312 prog = (sc->chip & RTWN_CHIP_92C) ? 2313 &rtl8192ce_bb_prog_2t : &rtl8192ce_bb_prog_1t; 2314 2315 /* Write BB initialization values. */ 2316 for (i = 0; i < prog->count; i++) { 2317 rtwn_bb_write(sc, prog->regs[i], prog->vals[i]); 2318 DELAY(1); 2319 } 2320 2321 if (sc->chip & RTWN_CHIP_92C_1T2R) { 2322 /* 8192C 1T only configuration. */ 2323 reg = rtwn_bb_read(sc, R92C_FPGA0_TXINFO); 2324 reg = (reg & ~0x00000003) | 0x2; 2325 rtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); 2326 2327 reg = rtwn_bb_read(sc, R92C_FPGA1_TXINFO); 2328 reg = (reg & ~0x00300033) | 0x00200022; 2329 rtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); 2330 2331 reg = rtwn_bb_read(sc, R92C_CCK0_AFESETTING); 2332 reg = (reg & ~0xff000000) | 0x45 << 24; 2333 rtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); 2334 2335 reg = rtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2336 reg = (reg & ~0x000000ff) | 0x23; 2337 rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); 2338 2339 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1); 2340 reg = (reg & ~0x00000030) | 1 << 4; 2341 rtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); 2342 2343 reg = rtwn_bb_read(sc, 0xe74); 2344 reg = (reg & ~0x0c000000) | 2 << 26; 2345 rtwn_bb_write(sc, 0xe74, reg); 2346 reg = rtwn_bb_read(sc, 0xe78); 2347 reg = (reg & ~0x0c000000) | 2 << 26; 2348 rtwn_bb_write(sc, 0xe78, reg); 2349 reg = rtwn_bb_read(sc, 0xe7c); 2350 reg = (reg & ~0x0c000000) | 2 << 26; 2351 rtwn_bb_write(sc, 0xe7c, reg); 2352 reg = rtwn_bb_read(sc, 0xe80); 2353 reg = (reg & ~0x0c000000) | 2 << 26; 2354 rtwn_bb_write(sc, 0xe80, reg); 2355 reg = rtwn_bb_read(sc, 0xe88); 2356 reg = (reg & ~0x0c000000) | 2 << 26; 2357 rtwn_bb_write(sc, 0xe88, reg); 2358 } 2359 2360 /* Write AGC values. */ 2361 for (i = 0; i < prog->agccount; i++) { 2362 rtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, 2363 prog->agcvals[i]); 2364 DELAY(1); 2365 } 2366 2367 if (rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) & 2368 R92C_HSSI_PARAM2_CCK_HIPWR) 2369 sc->sc_flags |= RTWN_FLAG_CCK_HIPWR; 2370 } 2371 2372 static void 2373 rtwn_rf_init(struct rtwn_softc *sc) 2374 { 2375 const struct rtwn_rf_prog *prog; 2376 uint32_t reg, type; 2377 int i, j, idx, off; 2378 2379 /* Select RF programming based on board type. */ 2380 if (!(sc->chip & RTWN_CHIP_92C)) { 2381 if (sc->board_type == R92C_BOARD_TYPE_MINICARD) 2382 prog = rtl8188ce_rf_prog; 2383 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2384 prog = rtl8188ru_rf_prog; 2385 else 2386 prog = rtl8188cu_rf_prog; 2387 } else 2388 prog = rtl8192ce_rf_prog; 2389 2390 for (i = 0; i < sc->nrxchains; i++) { 2391 /* Save RF_ENV control type. */ 2392 idx = i / 2; 2393 off = (i % 2) * 16; 2394 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2395 type = (reg >> off) & 0x10; 2396 2397 /* Set RF_ENV enable. */ 2398 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2399 reg |= 0x100000; 2400 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2401 DELAY(1); 2402 /* Set RF_ENV output high. */ 2403 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i)); 2404 reg |= 0x10; 2405 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); 2406 DELAY(1); 2407 /* Set address and data lengths of RF registers. */ 2408 reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2409 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH; 2410 rtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2411 DELAY(1); 2412 reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i)); 2413 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH; 2414 rtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); 2415 DELAY(1); 2416 2417 /* Write RF initialization values for this chain. */ 2418 for (j = 0; j < prog[i].count; j++) { 2419 if (prog[i].regs[j] >= 0xf9 && 2420 prog[i].regs[j] <= 0xfe) { 2421 /* 2422 * These are fake RF registers offsets that 2423 * indicate a delay is required. 2424 */ 2425 DELAY(50); 2426 continue; 2427 } 2428 rtwn_rf_write(sc, i, prog[i].regs[j], 2429 prog[i].vals[j]); 2430 DELAY(1); 2431 } 2432 2433 /* Restore RF_ENV control type. */ 2434 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx)); 2435 reg &= ~(0x10 << off) | (type << off); 2436 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); 2437 2438 /* Cache RF register CHNLBW. */ 2439 sc->rf_chnlbw[i] = rtwn_rf_read(sc, i, R92C_RF_CHNLBW); 2440 } 2441 2442 if ((sc->chip & (RTWN_CHIP_UMC_A_CUT | RTWN_CHIP_92C)) == 2443 RTWN_CHIP_UMC_A_CUT) { 2444 rtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255); 2445 rtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00); 2446 } 2447 } 2448 2449 static void 2450 rtwn_cam_init(struct rtwn_softc *sc) 2451 { 2452 /* Invalidate all CAM entries. */ 2453 rtwn_write_4(sc, R92C_CAMCMD, 2454 R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR); 2455 } 2456 2457 static void 2458 rtwn_pa_bias_init(struct rtwn_softc *sc) 2459 { 2460 uint8_t reg; 2461 int i; 2462 2463 for (i = 0; i < sc->nrxchains; i++) { 2464 if (sc->pa_setting & (1 << i)) 2465 continue; 2466 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406); 2467 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406); 2468 rtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406); 2469 rtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406); 2470 } 2471 if (!(sc->pa_setting & 0x10)) { 2472 reg = rtwn_read_1(sc, 0x16); 2473 reg = (reg & ~0xf0) | 0x90; 2474 rtwn_write_1(sc, 0x16, reg); 2475 } 2476 } 2477 2478 static void 2479 rtwn_rxfilter_init(struct rtwn_softc *sc) 2480 { 2481 /* Initialize Rx filter. */ 2482 /* TODO: use better filter for monitor mode. */ 2483 rtwn_write_4(sc, R92C_RCR, 2484 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB | 2485 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL | 2486 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS); 2487 /* Accept all multicast frames. */ 2488 rtwn_write_4(sc, R92C_MAR + 0, 0xffffffff); 2489 rtwn_write_4(sc, R92C_MAR + 4, 0xffffffff); 2490 /* Accept all management frames. */ 2491 rtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff); 2492 /* Reject all control frames. */ 2493 rtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000); 2494 /* Accept all data frames. */ 2495 rtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff); 2496 } 2497 2498 static void 2499 rtwn_edca_init(struct rtwn_softc *sc) 2500 { 2501 2502 rtwn_write_2(sc, R92C_SPEC_SIFS, 0x1010); 2503 rtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x1010); 2504 rtwn_write_2(sc, R92C_SIFS_CCK, 0x1010); 2505 rtwn_write_2(sc, R92C_SIFS_OFDM, 0x0e0e); 2506 rtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b); 2507 rtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f); 2508 rtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4322); 2509 rtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3222); 2510 } 2511 2512 static void 2513 rtwn_write_txpower(struct rtwn_softc *sc, int chain, 2514 uint16_t power[RTWN_RIDX_COUNT]) 2515 { 2516 uint32_t reg; 2517 2518 /* Write per-CCK rate Tx power. */ 2519 if (chain == 0) { 2520 reg = rtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32); 2521 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]); 2522 rtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); 2523 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2524 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]); 2525 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]); 2526 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]); 2527 rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2528 } else { 2529 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32); 2530 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]); 2531 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]); 2532 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]); 2533 rtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); 2534 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11); 2535 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]); 2536 rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); 2537 } 2538 /* Write per-OFDM rate Tx power. */ 2539 rtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), 2540 SM(R92C_TXAGC_RATE06, power[ 4]) | 2541 SM(R92C_TXAGC_RATE09, power[ 5]) | 2542 SM(R92C_TXAGC_RATE12, power[ 6]) | 2543 SM(R92C_TXAGC_RATE18, power[ 7])); 2544 rtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), 2545 SM(R92C_TXAGC_RATE24, power[ 8]) | 2546 SM(R92C_TXAGC_RATE36, power[ 9]) | 2547 SM(R92C_TXAGC_RATE48, power[10]) | 2548 SM(R92C_TXAGC_RATE54, power[11])); 2549 /* Write per-MCS Tx power. */ 2550 rtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), 2551 SM(R92C_TXAGC_MCS00, power[12]) | 2552 SM(R92C_TXAGC_MCS01, power[13]) | 2553 SM(R92C_TXAGC_MCS02, power[14]) | 2554 SM(R92C_TXAGC_MCS03, power[15])); 2555 rtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), 2556 SM(R92C_TXAGC_MCS04, power[16]) | 2557 SM(R92C_TXAGC_MCS05, power[17]) | 2558 SM(R92C_TXAGC_MCS06, power[18]) | 2559 SM(R92C_TXAGC_MCS07, power[19])); 2560 rtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), 2561 SM(R92C_TXAGC_MCS08, power[20]) | 2562 SM(R92C_TXAGC_MCS09, power[21]) | 2563 SM(R92C_TXAGC_MCS10, power[22]) | 2564 SM(R92C_TXAGC_MCS11, power[23])); 2565 rtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), 2566 SM(R92C_TXAGC_MCS12, power[24]) | 2567 SM(R92C_TXAGC_MCS13, power[25]) | 2568 SM(R92C_TXAGC_MCS14, power[26]) | 2569 SM(R92C_TXAGC_MCS15, power[27])); 2570 } 2571 2572 static void 2573 rtwn_get_txpower(struct rtwn_softc *sc, int chain, 2574 struct ieee80211_channel *c, struct ieee80211_channel *extc, 2575 uint16_t power[RTWN_RIDX_COUNT]) 2576 { 2577 struct ieee80211com *ic = &sc->sc_ic; 2578 struct r92c_rom *rom = &sc->rom; 2579 uint16_t cckpow, ofdmpow, htpow, diff, max; 2580 const struct rtwn_txpwr *base; 2581 int ridx, chan, group; 2582 2583 /* Determine channel group. */ 2584 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2585 if (chan <= 3) 2586 group = 0; 2587 else if (chan <= 9) 2588 group = 1; 2589 else 2590 group = 2; 2591 2592 /* Get original Tx power based on board type and RF chain. */ 2593 if (!(sc->chip & RTWN_CHIP_92C)) { 2594 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA) 2595 base = &rtl8188ru_txagc[chain]; 2596 else 2597 base = &rtl8192cu_txagc[chain]; 2598 } else 2599 base = &rtl8192cu_txagc[chain]; 2600 2601 memset(power, 0, RTWN_RIDX_COUNT * sizeof(power[0])); 2602 if (sc->regulatory == 0) { 2603 for (ridx = 0; ridx <= 3; ridx++) 2604 power[ridx] = base->pwr[0][ridx]; 2605 } 2606 for (ridx = 4; ridx < RTWN_RIDX_COUNT; ridx++) { 2607 if (sc->regulatory == 3) { 2608 power[ridx] = base->pwr[0][ridx]; 2609 /* Apply vendor limits. */ 2610 if (extc != NULL) 2611 max = rom->ht40_max_pwr[group]; 2612 else 2613 max = rom->ht20_max_pwr[group]; 2614 max = (max >> (chain * 4)) & 0xf; 2615 if (power[ridx] > max) 2616 power[ridx] = max; 2617 } else if (sc->regulatory == 1) { 2618 if (extc == NULL) 2619 power[ridx] = base->pwr[group][ridx]; 2620 } else if (sc->regulatory != 2) 2621 power[ridx] = base->pwr[0][ridx]; 2622 } 2623 2624 /* Compute per-CCK rate Tx power. */ 2625 cckpow = rom->cck_tx_pwr[chain][group]; 2626 for (ridx = 0; ridx <= 3; ridx++) { 2627 power[ridx] += cckpow; 2628 if (power[ridx] > R92C_MAX_TX_PWR) 2629 power[ridx] = R92C_MAX_TX_PWR; 2630 } 2631 2632 htpow = rom->ht40_1s_tx_pwr[chain][group]; 2633 if (sc->ntxchains > 1) { 2634 /* Apply reduction for 2 spatial streams. */ 2635 diff = rom->ht40_2s_tx_pwr_diff[group]; 2636 diff = (diff >> (chain * 4)) & 0xf; 2637 htpow = (htpow > diff) ? htpow - diff : 0; 2638 } 2639 2640 /* Compute per-OFDM rate Tx power. */ 2641 diff = rom->ofdm_tx_pwr_diff[group]; 2642 diff = (diff >> (chain * 4)) & 0xf; 2643 ofdmpow = htpow + diff; /* HT->OFDM correction. */ 2644 for (ridx = 4; ridx <= 11; ridx++) { 2645 power[ridx] += ofdmpow; 2646 if (power[ridx] > R92C_MAX_TX_PWR) 2647 power[ridx] = R92C_MAX_TX_PWR; 2648 } 2649 2650 /* Compute per-MCS Tx power. */ 2651 if (extc == NULL) { 2652 diff = rom->ht20_tx_pwr_diff[group]; 2653 diff = (diff >> (chain * 4)) & 0xf; 2654 htpow += diff; /* HT40->HT20 correction. */ 2655 } 2656 for (ridx = 12; ridx <= 27; ridx++) { 2657 power[ridx] += htpow; 2658 if (power[ridx] > R92C_MAX_TX_PWR) 2659 power[ridx] = R92C_MAX_TX_PWR; 2660 } 2661 #ifdef RTWN_DEBUG 2662 if (sc->sc_debug >= 4) { 2663 /* Dump per-rate Tx power values. */ 2664 printf("Tx power for chain %d:\n", chain); 2665 for (ridx = 0; ridx < RTWN_RIDX_COUNT; ridx++) 2666 printf("Rate %d = %u\n", ridx, power[ridx]); 2667 } 2668 #endif 2669 } 2670 2671 static void 2672 rtwn_set_txpower(struct rtwn_softc *sc, struct ieee80211_channel *c, 2673 struct ieee80211_channel *extc) 2674 { 2675 uint16_t power[RTWN_RIDX_COUNT]; 2676 int i; 2677 2678 for (i = 0; i < sc->ntxchains; i++) { 2679 /* Compute per-rate Tx power values. */ 2680 rtwn_get_txpower(sc, i, c, extc, power); 2681 /* Write per-rate Tx power values to hardware. */ 2682 rtwn_write_txpower(sc, i, power); 2683 } 2684 } 2685 2686 static void 2687 rtwn_scan_start(struct ieee80211com *ic) 2688 { 2689 2690 /* XXX do nothing? */ 2691 } 2692 2693 static void 2694 rtwn_scan_end(struct ieee80211com *ic) 2695 { 2696 2697 /* XXX do nothing? */ 2698 } 2699 2700 static void 2701 rtwn_set_channel(struct ieee80211com *ic) 2702 { 2703 struct rtwn_softc *sc = ic->ic_softc; 2704 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2705 2706 RTWN_LOCK(sc); 2707 if (vap->iv_state == IEEE80211_S_SCAN) { 2708 /* Make link LED blink during scan. */ 2709 rtwn_set_led(sc, RTWN_LED_LINK, !sc->ledlink); 2710 } 2711 rtwn_set_chan(sc, ic->ic_curchan, NULL); 2712 RTWN_UNLOCK(sc); 2713 } 2714 2715 static void 2716 rtwn_update_mcast(struct ieee80211com *ic) 2717 { 2718 2719 /* XXX do nothing? */ 2720 } 2721 2722 static void 2723 rtwn_set_chan(struct rtwn_softc *sc, struct ieee80211_channel *c, 2724 struct ieee80211_channel *extc) 2725 { 2726 struct ieee80211com *ic = &sc->sc_ic; 2727 u_int chan; 2728 int i; 2729 2730 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */ 2731 if (chan == 0 || chan == IEEE80211_CHAN_ANY) { 2732 device_printf(sc->sc_dev, 2733 "%s: invalid channel %x\n", __func__, chan); 2734 return; 2735 } 2736 2737 /* Set Tx power for this new channel. */ 2738 rtwn_set_txpower(sc, c, extc); 2739 2740 for (i = 0; i < sc->nrxchains; i++) { 2741 rtwn_rf_write(sc, i, R92C_RF_CHNLBW, 2742 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan)); 2743 } 2744 #ifndef IEEE80211_NO_HT 2745 if (extc != NULL) { 2746 uint32_t reg; 2747 2748 /* Is secondary channel below or above primary? */ 2749 int prichlo = c->ic_freq < extc->ic_freq; 2750 2751 rtwn_write_1(sc, R92C_BWOPMODE, 2752 rtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ); 2753 2754 reg = rtwn_read_1(sc, R92C_RRSR + 2); 2755 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5; 2756 rtwn_write_1(sc, R92C_RRSR + 2, reg); 2757 2758 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, 2759 rtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ); 2760 rtwn_bb_write(sc, R92C_FPGA1_RFMOD, 2761 rtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ); 2762 2763 /* Set CCK side band. */ 2764 reg = rtwn_bb_read(sc, R92C_CCK0_SYSTEM); 2765 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4; 2766 rtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); 2767 2768 reg = rtwn_bb_read(sc, R92C_OFDM1_LSTF); 2769 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10; 2770 rtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); 2771 2772 rtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 2773 rtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) & 2774 ~R92C_FPGA0_ANAPARAM2_CBW20); 2775 2776 reg = rtwn_bb_read(sc, 0x818); 2777 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26; 2778 rtwn_bb_write(sc, 0x818, reg); 2779 2780 /* Select 40MHz bandwidth. */ 2781 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 2782 (sc->rf_chnlbw[0] & ~0xfff) | chan); 2783 } else 2784 #endif 2785 { 2786 rtwn_write_1(sc, R92C_BWOPMODE, 2787 rtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ); 2788 2789 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, 2790 rtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ); 2791 rtwn_bb_write(sc, R92C_FPGA1_RFMOD, 2792 rtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ); 2793 2794 rtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, 2795 rtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) | 2796 R92C_FPGA0_ANAPARAM2_CBW20); 2797 2798 /* Select 20MHz bandwidth. */ 2799 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 2800 (sc->rf_chnlbw[0] & ~0xfff) | R92C_RF_CHNLBW_BW20 | chan); 2801 } 2802 } 2803 2804 static int 2805 rtwn_iq_calib_chain(struct rtwn_softc *sc, int chain, uint16_t tx[2], 2806 uint16_t rx[2]) 2807 { 2808 uint32_t status; 2809 int offset = chain * 0x20; 2810 2811 if (chain == 0) { /* IQ calibration for chain 0. */ 2812 /* IQ calibration settings for chain 0. */ 2813 rtwn_bb_write(sc, 0xe30, 0x10008c1f); 2814 rtwn_bb_write(sc, 0xe34, 0x10008c1f); 2815 rtwn_bb_write(sc, 0xe38, 0x82140102); 2816 2817 if (sc->ntxchains > 1) { 2818 rtwn_bb_write(sc, 0xe3c, 0x28160202); /* 2T */ 2819 /* IQ calibration settings for chain 1. */ 2820 rtwn_bb_write(sc, 0xe50, 0x10008c22); 2821 rtwn_bb_write(sc, 0xe54, 0x10008c22); 2822 rtwn_bb_write(sc, 0xe58, 0x82140102); 2823 rtwn_bb_write(sc, 0xe5c, 0x28160202); 2824 } else 2825 rtwn_bb_write(sc, 0xe3c, 0x28160502); /* 1T */ 2826 2827 /* LO calibration settings. */ 2828 rtwn_bb_write(sc, 0xe4c, 0x001028d1); 2829 /* We're doing LO and IQ calibration in one shot. */ 2830 rtwn_bb_write(sc, 0xe48, 0xf9000000); 2831 rtwn_bb_write(sc, 0xe48, 0xf8000000); 2832 2833 } else { /* IQ calibration for chain 1. */ 2834 /* We're doing LO and IQ calibration in one shot. */ 2835 rtwn_bb_write(sc, 0xe60, 0x00000002); 2836 rtwn_bb_write(sc, 0xe60, 0x00000000); 2837 } 2838 2839 /* Give LO and IQ calibrations the time to complete. */ 2840 DELAY(1000); 2841 2842 /* Read IQ calibration status. */ 2843 status = rtwn_bb_read(sc, 0xeac); 2844 2845 if (status & (1 << (28 + chain * 3))) 2846 return (0); /* Tx failed. */ 2847 /* Read Tx IQ calibration results. */ 2848 tx[0] = (rtwn_bb_read(sc, 0xe94 + offset) >> 16) & 0x3ff; 2849 tx[1] = (rtwn_bb_read(sc, 0xe9c + offset) >> 16) & 0x3ff; 2850 if (tx[0] == 0x142 || tx[1] == 0x042) 2851 return (0); /* Tx failed. */ 2852 2853 if (status & (1 << (27 + chain * 3))) 2854 return (1); /* Rx failed. */ 2855 /* Read Rx IQ calibration results. */ 2856 rx[0] = (rtwn_bb_read(sc, 0xea4 + offset) >> 16) & 0x3ff; 2857 rx[1] = (rtwn_bb_read(sc, 0xeac + offset) >> 16) & 0x3ff; 2858 if (rx[0] == 0x132 || rx[1] == 0x036) 2859 return (1); /* Rx failed. */ 2860 2861 return (3); /* Both Tx and Rx succeeded. */ 2862 } 2863 2864 static void 2865 rtwn_iq_calib_run(struct rtwn_softc *sc, int n, uint16_t tx[2][2], 2866 uint16_t rx[2][2]) 2867 { 2868 /* Registers to save and restore during IQ calibration. */ 2869 struct iq_cal_regs { 2870 uint32_t adda[16]; 2871 uint8_t txpause; 2872 uint8_t bcn_ctrl; 2873 uint8_t ustime_tsf; 2874 uint32_t gpio_muxcfg; 2875 uint32_t ofdm0_trxpathena; 2876 uint32_t ofdm0_trmuxpar; 2877 uint32_t fpga0_rfifacesw1; 2878 } iq_cal_regs; 2879 static const uint16_t reg_adda[16] = { 2880 0x85c, 0xe6c, 0xe70, 0xe74, 2881 0xe78, 0xe7c, 0xe80, 0xe84, 2882 0xe88, 0xe8c, 0xed0, 0xed4, 2883 0xed8, 0xedc, 0xee0, 0xeec 2884 }; 2885 int i, chain; 2886 uint32_t hssi_param1; 2887 2888 if (n == 0) { 2889 for (i = 0; i < nitems(reg_adda); i++) 2890 iq_cal_regs.adda[i] = rtwn_bb_read(sc, reg_adda[i]); 2891 2892 iq_cal_regs.txpause = rtwn_read_1(sc, R92C_TXPAUSE); 2893 iq_cal_regs.bcn_ctrl = rtwn_read_1(sc, R92C_BCN_CTRL); 2894 iq_cal_regs.ustime_tsf = rtwn_read_1(sc, R92C_USTIME_TSF); 2895 iq_cal_regs.gpio_muxcfg = rtwn_read_4(sc, R92C_GPIO_MUXCFG); 2896 } 2897 2898 if (sc->ntxchains == 1) { 2899 rtwn_bb_write(sc, reg_adda[0], 0x0b1b25a0); 2900 for (i = 1; i < nitems(reg_adda); i++) 2901 rtwn_bb_write(sc, reg_adda[i], 0x0bdb25a0); 2902 } else { 2903 for (i = 0; i < nitems(reg_adda); i++) 2904 rtwn_bb_write(sc, reg_adda[i], 0x04db25a4); 2905 } 2906 2907 hssi_param1 = rtwn_bb_read(sc, R92C_HSSI_PARAM1(0)); 2908 if (!(hssi_param1 & R92C_HSSI_PARAM1_PI)) { 2909 rtwn_bb_write(sc, R92C_HSSI_PARAM1(0), 2910 hssi_param1 | R92C_HSSI_PARAM1_PI); 2911 rtwn_bb_write(sc, R92C_HSSI_PARAM1(1), 2912 hssi_param1 | R92C_HSSI_PARAM1_PI); 2913 } 2914 2915 if (n == 0) { 2916 iq_cal_regs.ofdm0_trxpathena = 2917 rtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA); 2918 iq_cal_regs.ofdm0_trmuxpar = 2919 rtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR); 2920 iq_cal_regs.fpga0_rfifacesw1 = 2921 rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1)); 2922 } 2923 2924 rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, 0x03a05600); 2925 rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, 0x000800e4); 2926 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), 0x22204000); 2927 if (sc->ntxchains > 1) { 2928 rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00010000); 2929 rtwn_bb_write(sc, R92C_LSSI_PARAM(1), 0x00010000); 2930 } 2931 2932 rtwn_write_1(sc, R92C_TXPAUSE, 0x3f); 2933 rtwn_write_1(sc, R92C_BCN_CTRL, iq_cal_regs.bcn_ctrl & ~(0x08)); 2934 rtwn_write_1(sc, R92C_USTIME_TSF, iq_cal_regs.ustime_tsf & ~(0x08)); 2935 rtwn_write_1(sc, R92C_GPIO_MUXCFG, 2936 iq_cal_regs.gpio_muxcfg & ~(0x20)); 2937 2938 rtwn_bb_write(sc, 0x0b68, 0x00080000); 2939 if (sc->ntxchains > 1) 2940 rtwn_bb_write(sc, 0x0b6c, 0x00080000); 2941 2942 rtwn_bb_write(sc, 0x0e28, 0x80800000); 2943 rtwn_bb_write(sc, 0x0e40, 0x01007c00); 2944 rtwn_bb_write(sc, 0x0e44, 0x01004800); 2945 2946 rtwn_bb_write(sc, 0x0b68, 0x00080000); 2947 2948 for (chain = 0; chain < sc->ntxchains; chain++) { 2949 if (chain > 0) { 2950 /* Put chain 0 on standby. */ 2951 rtwn_bb_write(sc, 0x0e28, 0x00); 2952 rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00010000); 2953 rtwn_bb_write(sc, 0x0e28, 0x80800000); 2954 2955 /* Enable chain 1. */ 2956 for (i = 0; i < nitems(reg_adda); i++) 2957 rtwn_bb_write(sc, reg_adda[i], 0x0b1b25a4); 2958 } 2959 2960 /* Run IQ calibration twice. */ 2961 for (i = 0; i < 2; i++) { 2962 int ret; 2963 2964 ret = rtwn_iq_calib_chain(sc, chain, 2965 tx[chain], rx[chain]); 2966 if (ret == 0) { 2967 DPRINTF(("%s: chain %d: Tx failed.\n", 2968 __func__, chain)); 2969 tx[chain][0] = 0xff; 2970 tx[chain][1] = 0xff; 2971 rx[chain][0] = 0xff; 2972 rx[chain][1] = 0xff; 2973 } else if (ret == 1) { 2974 DPRINTF(("%s: chain %d: Rx failed.\n", 2975 __func__, chain)); 2976 rx[chain][0] = 0xff; 2977 rx[chain][1] = 0xff; 2978 } else if (ret == 3) { 2979 DPRINTF(("%s: chain %d: Both Tx and Rx " 2980 "succeeded.\n", __func__, chain)); 2981 } 2982 } 2983 2984 DPRINTF(("%s: results for run %d chain %d: tx[0]=0x%x, " 2985 "tx[1]=0x%x rx[0]=0x%x rx[1]=0x%x\n", __func__, n, chain, 2986 tx[chain][0], tx[chain][1], rx[chain][0], rx[chain][1])); 2987 } 2988 2989 rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, 2990 iq_cal_regs.ofdm0_trxpathena); 2991 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), 2992 iq_cal_regs.fpga0_rfifacesw1); 2993 rtwn_bb_write(sc, R92C_OFDM0_TRMUXPAR, iq_cal_regs.ofdm0_trmuxpar); 2994 2995 rtwn_bb_write(sc, 0x0e28, 0x00); 2996 rtwn_bb_write(sc, R92C_LSSI_PARAM(0), 0x00032ed3); 2997 if (sc->ntxchains > 1) 2998 rtwn_bb_write(sc, R92C_LSSI_PARAM(1), 0x00032ed3); 2999 3000 if (n != 0) { 3001 if (!(hssi_param1 & R92C_HSSI_PARAM1_PI)) { 3002 rtwn_bb_write(sc, R92C_HSSI_PARAM1(0), hssi_param1); 3003 rtwn_bb_write(sc, R92C_HSSI_PARAM1(1), hssi_param1); 3004 } 3005 3006 for (i = 0; i < nitems(reg_adda); i++) 3007 rtwn_bb_write(sc, reg_adda[i], iq_cal_regs.adda[i]); 3008 3009 rtwn_write_1(sc, R92C_TXPAUSE, iq_cal_regs.txpause); 3010 rtwn_write_1(sc, R92C_BCN_CTRL, iq_cal_regs.bcn_ctrl); 3011 rtwn_write_1(sc, R92C_USTIME_TSF, iq_cal_regs.ustime_tsf); 3012 rtwn_write_4(sc, R92C_GPIO_MUXCFG, iq_cal_regs.gpio_muxcfg); 3013 } 3014 } 3015 3016 #define RTWN_IQ_CAL_MAX_TOLERANCE 5 3017 static int 3018 rtwn_iq_calib_compare_results(uint16_t tx1[2][2], uint16_t rx1[2][2], 3019 uint16_t tx2[2][2], uint16_t rx2[2][2], int ntxchains) 3020 { 3021 int chain, i, tx_ok[2], rx_ok[2]; 3022 3023 tx_ok[0] = tx_ok[1] = rx_ok[0] = rx_ok[1] = 0; 3024 for (chain = 0; chain < ntxchains; chain++) { 3025 for (i = 0; i < 2; i++) { 3026 if (tx1[chain][i] == 0xff || tx2[chain][i] == 0xff || 3027 rx1[chain][i] == 0xff || rx2[chain][i] == 0xff) 3028 continue; 3029 3030 tx_ok[chain] = (abs(tx1[chain][i] - tx2[chain][i]) <= 3031 RTWN_IQ_CAL_MAX_TOLERANCE); 3032 3033 rx_ok[chain] = (abs(rx1[chain][i] - rx2[chain][i]) <= 3034 RTWN_IQ_CAL_MAX_TOLERANCE); 3035 } 3036 } 3037 3038 if (ntxchains > 1) 3039 return (tx_ok[0] && tx_ok[1] && rx_ok[0] && rx_ok[1]); 3040 else 3041 return (tx_ok[0] && rx_ok[0]); 3042 } 3043 #undef RTWN_IQ_CAL_MAX_TOLERANCE 3044 3045 static void 3046 rtwn_iq_calib_write_results(struct rtwn_softc *sc, uint16_t tx[2], 3047 uint16_t rx[2], int chain) 3048 { 3049 uint32_t reg, val, x; 3050 long y, tx_c; 3051 3052 if (tx[0] == 0xff || tx[1] == 0xff) 3053 return; 3054 3055 reg = rtwn_bb_read(sc, R92C_OFDM0_TXIQIMBALANCE(chain)); 3056 val = ((reg >> 22) & 0x3ff); 3057 x = tx[0]; 3058 if (x & 0x0200) 3059 x |= 0xfc00; 3060 reg = (((x * val) >> 8) & 0x3ff); 3061 rtwn_bb_write(sc, R92C_OFDM0_TXIQIMBALANCE(chain), reg); 3062 3063 reg = rtwn_bb_read(sc, R92C_OFDM0_ECCATHRESHOLD); 3064 if (((x * val) >> 7) & 0x01) 3065 reg |= 0x80000000; 3066 else 3067 reg &= ~0x80000000; 3068 rtwn_bb_write(sc, R92C_OFDM0_ECCATHRESHOLD, reg); 3069 3070 y = tx[1]; 3071 if (y & 0x00000200) 3072 y |= 0xfffffc00; 3073 tx_c = (y * val) >> 8; 3074 reg = rtwn_bb_read(sc, R92C_OFDM0_TXAFE(chain)); 3075 reg |= ((((tx_c & 0x3c0) >> 6) << 24) & 0xf0000000); 3076 rtwn_bb_write(sc, R92C_OFDM0_TXAFE(chain), reg); 3077 3078 reg = rtwn_bb_read(sc, R92C_OFDM0_TXIQIMBALANCE(chain)); 3079 reg |= (((tx_c & 0x3f) << 16) & 0x003F0000); 3080 rtwn_bb_write(sc, R92C_OFDM0_TXIQIMBALANCE(chain), reg); 3081 3082 reg = rtwn_bb_read(sc, R92C_OFDM0_ECCATHRESHOLD); 3083 if (((y * val) >> 7) & 0x01) 3084 reg |= 0x20000000; 3085 else 3086 reg &= ~0x20000000; 3087 rtwn_bb_write(sc, R92C_OFDM0_ECCATHRESHOLD, reg); 3088 3089 if (rx[0] == 0xff || rx[1] == 0xff) 3090 return; 3091 3092 reg = rtwn_bb_read(sc, R92C_OFDM0_RXIQIMBALANCE(chain)); 3093 reg |= (rx[0] & 0x3ff); 3094 rtwn_bb_write(sc, R92C_OFDM0_RXIQIMBALANCE(chain), reg); 3095 reg |= (((rx[1] & 0x03f) << 8) & 0xFC00); 3096 rtwn_bb_write(sc, R92C_OFDM0_RXIQIMBALANCE(chain), reg); 3097 3098 if (chain == 0) { 3099 reg = rtwn_bb_read(sc, R92C_OFDM0_RXIQEXTANTA); 3100 reg |= (((rx[1] & 0xf) >> 6) & 0x000f); 3101 rtwn_bb_write(sc, R92C_OFDM0_RXIQEXTANTA, reg); 3102 } else { 3103 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCRSSITABLE); 3104 reg |= ((((rx[1] & 0xf) >> 6) << 12) & 0xf000); 3105 rtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, reg); 3106 } 3107 } 3108 3109 #define RTWN_IQ_CAL_NRUN 3 3110 static void 3111 rtwn_iq_calib(struct rtwn_softc *sc) 3112 { 3113 uint16_t tx[RTWN_IQ_CAL_NRUN][2][2], rx[RTWN_IQ_CAL_NRUN][2][2]; 3114 int n, valid; 3115 3116 valid = 0; 3117 for (n = 0; n < RTWN_IQ_CAL_NRUN; n++) { 3118 rtwn_iq_calib_run(sc, n, tx[n], rx[n]); 3119 3120 if (n == 0) 3121 continue; 3122 3123 /* Valid results remain stable after consecutive runs. */ 3124 valid = rtwn_iq_calib_compare_results(tx[n - 1], rx[n - 1], 3125 tx[n], rx[n], sc->ntxchains); 3126 if (valid) 3127 break; 3128 } 3129 3130 if (valid) { 3131 rtwn_iq_calib_write_results(sc, tx[n][0], rx[n][0], 0); 3132 if (sc->ntxchains > 1) 3133 rtwn_iq_calib_write_results(sc, tx[n][1], rx[n][1], 1); 3134 } 3135 } 3136 #undef RTWN_IQ_CAL_NRUN 3137 3138 static void 3139 rtwn_lc_calib(struct rtwn_softc *sc) 3140 { 3141 uint32_t rf_ac[2]; 3142 uint8_t txmode; 3143 int i; 3144 3145 txmode = rtwn_read_1(sc, R92C_OFDM1_LSTF + 3); 3146 if ((txmode & 0x70) != 0) { 3147 /* Disable all continuous Tx. */ 3148 rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70); 3149 3150 /* Set RF mode to standby mode. */ 3151 for (i = 0; i < sc->nrxchains; i++) { 3152 rf_ac[i] = rtwn_rf_read(sc, i, R92C_RF_AC); 3153 rtwn_rf_write(sc, i, R92C_RF_AC, 3154 RW(rf_ac[i], R92C_RF_AC_MODE, 3155 R92C_RF_AC_MODE_STANDBY)); 3156 } 3157 } else { 3158 /* Block all Tx queues. */ 3159 rtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3160 } 3161 /* Start calibration. */ 3162 rtwn_rf_write(sc, 0, R92C_RF_CHNLBW, 3163 rtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART); 3164 3165 /* Give calibration the time to complete. */ 3166 DELAY(100); 3167 3168 /* Restore configuration. */ 3169 if ((txmode & 0x70) != 0) { 3170 /* Restore Tx mode. */ 3171 rtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode); 3172 /* Restore RF mode. */ 3173 for (i = 0; i < sc->nrxchains; i++) 3174 rtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]); 3175 } else { 3176 /* Unblock all Tx queues. */ 3177 rtwn_write_1(sc, R92C_TXPAUSE, 0x00); 3178 } 3179 } 3180 3181 static void 3182 rtwn_temp_calib(struct rtwn_softc *sc) 3183 { 3184 int temp; 3185 3186 if (sc->thcal_state == 0) { 3187 /* Start measuring temperature. */ 3188 rtwn_rf_write(sc, 0, R92C_RF_T_METER, 0x60); 3189 sc->thcal_state = 1; 3190 return; 3191 } 3192 sc->thcal_state = 0; 3193 3194 /* Read measured temperature. */ 3195 temp = rtwn_rf_read(sc, 0, R92C_RF_T_METER) & 0x1f; 3196 if (temp == 0) /* Read failed, skip. */ 3197 return; 3198 DPRINTFN(2, ("temperature=%d\n", temp)); 3199 3200 /* 3201 * Redo IQ and LC calibration if temperature changed significantly 3202 * since last calibration. 3203 */ 3204 if (sc->thcal_lctemp == 0) { 3205 /* First calibration is performed in rtwn_init(). */ 3206 sc->thcal_lctemp = temp; 3207 } else if (abs(temp - sc->thcal_lctemp) > 1) { 3208 DPRINTF(("IQ/LC calib triggered by temp: %d -> %d\n", 3209 sc->thcal_lctemp, temp)); 3210 rtwn_iq_calib(sc); 3211 rtwn_lc_calib(sc); 3212 /* Record temperature of last calibration. */ 3213 sc->thcal_lctemp = temp; 3214 } 3215 } 3216 3217 static int 3218 rtwn_init(struct rtwn_softc *sc) 3219 { 3220 struct ieee80211com *ic = &sc->sc_ic; 3221 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 3222 uint32_t reg; 3223 uint8_t macaddr[IEEE80211_ADDR_LEN]; 3224 int i, error; 3225 3226 RTWN_LOCK(sc); 3227 3228 if (sc->sc_flags & RTWN_RUNNING) { 3229 RTWN_UNLOCK(sc); 3230 return 0; 3231 } 3232 sc->sc_flags |= RTWN_RUNNING; 3233 3234 /* Init firmware commands ring. */ 3235 sc->fwcur = 0; 3236 3237 /* Power on adapter. */ 3238 error = rtwn_power_on(sc); 3239 if (error != 0) { 3240 device_printf(sc->sc_dev, "could not power on adapter\n"); 3241 goto fail; 3242 } 3243 3244 /* Initialize DMA. */ 3245 error = rtwn_dma_init(sc); 3246 if (error != 0) { 3247 device_printf(sc->sc_dev, "could not initialize DMA\n"); 3248 goto fail; 3249 } 3250 3251 /* Set info size in Rx descriptors (in 64-bit words). */ 3252 rtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4); 3253 3254 /* Disable interrupts. */ 3255 rtwn_write_4(sc, R92C_HISR, 0x00000000); 3256 rtwn_write_4(sc, R92C_HIMR, 0x00000000); 3257 3258 /* Set MAC address. */ 3259 IEEE80211_ADDR_COPY(macaddr, vap ? vap->iv_myaddr : ic->ic_macaddr); 3260 for (i = 0; i < IEEE80211_ADDR_LEN; i++) 3261 rtwn_write_1(sc, R92C_MACID + i, macaddr[i]); 3262 3263 /* Set initial network type. */ 3264 reg = rtwn_read_4(sc, R92C_CR); 3265 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA); 3266 rtwn_write_4(sc, R92C_CR, reg); 3267 3268 rtwn_rxfilter_init(sc); 3269 3270 reg = rtwn_read_4(sc, R92C_RRSR); 3271 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_ALL); 3272 rtwn_write_4(sc, R92C_RRSR, reg); 3273 3274 /* Set short/long retry limits. */ 3275 rtwn_write_2(sc, R92C_RL, 3276 SM(R92C_RL_SRL, 0x07) | SM(R92C_RL_LRL, 0x07)); 3277 3278 /* Initialize EDCA parameters. */ 3279 rtwn_edca_init(sc); 3280 3281 /* Set data and response automatic rate fallback retry counts. */ 3282 rtwn_write_4(sc, R92C_DARFRC + 0, 0x01000000); 3283 rtwn_write_4(sc, R92C_DARFRC + 4, 0x07060504); 3284 rtwn_write_4(sc, R92C_RARFRC + 0, 0x01000000); 3285 rtwn_write_4(sc, R92C_RARFRC + 4, 0x07060504); 3286 3287 rtwn_write_2(sc, R92C_FWHW_TXQ_CTRL, 0x1f80); 3288 3289 /* Set ACK timeout. */ 3290 rtwn_write_1(sc, R92C_ACKTO, 0x40); 3291 3292 /* Initialize beacon parameters. */ 3293 rtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404); 3294 rtwn_write_1(sc, R92C_DRVERLYINT, 0x05); 3295 rtwn_write_1(sc, R92C_BCNDMATIM, 0x02); 3296 rtwn_write_2(sc, R92C_BCNTCFG, 0x660f); 3297 3298 /* Setup AMPDU aggregation. */ 3299 rtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */ 3300 rtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16); 3301 3302 rtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff); 3303 rtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0); 3304 3305 rtwn_write_4(sc, R92C_PIFS, 0x1c); 3306 rtwn_write_4(sc, R92C_MCUTST_1, 0x0); 3307 3308 /* Load 8051 microcode. */ 3309 error = rtwn_load_firmware(sc); 3310 if (error != 0) 3311 goto fail; 3312 3313 /* Initialize MAC/BB/RF blocks. */ 3314 rtwn_mac_init(sc); 3315 rtwn_bb_init(sc); 3316 rtwn_rf_init(sc); 3317 3318 /* Turn CCK and OFDM blocks on. */ 3319 reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3320 reg |= R92C_RFMOD_CCK_EN; 3321 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3322 reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD); 3323 reg |= R92C_RFMOD_OFDM_EN; 3324 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); 3325 3326 /* Clear per-station keys table. */ 3327 rtwn_cam_init(sc); 3328 3329 /* Enable hardware sequence numbering. */ 3330 rtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff); 3331 3332 /* Perform LO and IQ calibrations. */ 3333 rtwn_iq_calib(sc); 3334 /* Perform LC calibration. */ 3335 rtwn_lc_calib(sc); 3336 3337 rtwn_pa_bias_init(sc); 3338 3339 /* Initialize GPIO setting. */ 3340 rtwn_write_1(sc, R92C_GPIO_MUXCFG, 3341 rtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT); 3342 3343 /* Fix for lower temperature. */ 3344 rtwn_write_1(sc, 0x15, 0xe9); 3345 3346 /* CLear pending interrupts. */ 3347 rtwn_write_4(sc, R92C_HISR, 0xffffffff); 3348 3349 /* Enable interrupts. */ 3350 rtwn_write_4(sc, R92C_HIMR, RTWN_INT_ENABLE); 3351 3352 callout_reset(&sc->watchdog_to, hz, rtwn_watchdog, sc); 3353 3354 fail: 3355 if (error != 0) 3356 rtwn_stop_locked(sc); 3357 3358 RTWN_UNLOCK(sc); 3359 3360 return error; 3361 } 3362 3363 static void 3364 rtwn_stop_locked(struct rtwn_softc *sc) 3365 { 3366 uint16_t reg; 3367 int i; 3368 3369 RTWN_LOCK_ASSERT(sc); 3370 3371 if (!(sc->sc_flags & RTWN_RUNNING)) 3372 return; 3373 3374 sc->sc_tx_timer = 0; 3375 callout_stop(&sc->watchdog_to); 3376 callout_stop(&sc->calib_to); 3377 sc->sc_flags &= ~RTWN_RUNNING; 3378 3379 /* Disable interrupts. */ 3380 rtwn_write_4(sc, R92C_HISR, 0x00000000); 3381 rtwn_write_4(sc, R92C_HIMR, 0x00000000); 3382 3383 /* Stop hardware. */ 3384 rtwn_write_1(sc, R92C_TXPAUSE, 0xff); 3385 rtwn_write_1(sc, R92C_RF_CTRL, 0x00); 3386 reg = rtwn_read_1(sc, R92C_SYS_FUNC_EN); 3387 reg |= R92C_SYS_FUNC_EN_BB_GLB_RST; 3388 rtwn_write_1(sc, R92C_SYS_FUNC_EN, reg); 3389 reg &= ~R92C_SYS_FUNC_EN_BB_GLB_RST; 3390 rtwn_write_1(sc, R92C_SYS_FUNC_EN, reg); 3391 reg = rtwn_read_2(sc, R92C_CR); 3392 reg &= ~(R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN | 3393 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN | 3394 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN | 3395 R92C_CR_ENSEC); 3396 rtwn_write_2(sc, R92C_CR, reg); 3397 if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RAM_DL_SEL) 3398 rtwn_fw_reset(sc); 3399 /* TODO: linux does additional btcoex stuff here */ 3400 rtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0x80); /* linux magic number */ 3401 rtwn_write_1(sc, R92C_SPS0_CTRL, 0x23); /* ditto */ 3402 rtwn_write_1(sc, R92C_AFE_XTAL_CTRL, 0x0e); /* different with btcoex */ 3403 rtwn_write_1(sc, R92C_RSV_CTRL, 0x0e); 3404 rtwn_write_1(sc, R92C_APS_FSMCO, R92C_APS_FSMCO_PDN_EN); 3405 3406 for (i = 0; i < RTWN_NTXQUEUES; i++) 3407 rtwn_reset_tx_list(sc, i); 3408 rtwn_reset_rx_list(sc); 3409 } 3410 3411 static void 3412 rtwn_stop(struct rtwn_softc *sc) 3413 { 3414 RTWN_LOCK(sc); 3415 rtwn_stop_locked(sc); 3416 RTWN_UNLOCK(sc); 3417 } 3418 3419 static void 3420 rtwn_intr(void *arg) 3421 { 3422 struct rtwn_softc *sc = arg; 3423 uint32_t status; 3424 int i; 3425 3426 RTWN_LOCK(sc); 3427 status = rtwn_read_4(sc, R92C_HISR); 3428 if (status == 0 || status == 0xffffffff) { 3429 RTWN_UNLOCK(sc); 3430 return; 3431 } 3432 3433 /* Disable interrupts. */ 3434 rtwn_write_4(sc, R92C_HIMR, 0x00000000); 3435 3436 /* Ack interrupts. */ 3437 rtwn_write_4(sc, R92C_HISR, status); 3438 3439 /* Vendor driver treats RX errors like ROK... */ 3440 if (status & (R92C_IMR_ROK | R92C_IMR_RXFOVW | R92C_IMR_RDU)) { 3441 bus_dmamap_sync(sc->rx_ring.desc_dmat, sc->rx_ring.desc_map, 3442 BUS_DMASYNC_POSTREAD); 3443 3444 for (i = 0; i < RTWN_RX_LIST_COUNT; i++) { 3445 struct r92c_rx_desc *rx_desc = &sc->rx_ring.desc[i]; 3446 struct rtwn_rx_data *rx_data = &sc->rx_ring.rx_data[i]; 3447 3448 if (le32toh(rx_desc->rxdw0) & R92C_RXDW0_OWN) 3449 continue; 3450 3451 rtwn_rx_frame(sc, rx_desc, rx_data, i); 3452 } 3453 } 3454 3455 if (status & R92C_IMR_BDOK) 3456 rtwn_tx_done(sc, RTWN_BEACON_QUEUE); 3457 if (status & R92C_IMR_HIGHDOK) 3458 rtwn_tx_done(sc, RTWN_HIGH_QUEUE); 3459 if (status & R92C_IMR_MGNTDOK) 3460 rtwn_tx_done(sc, RTWN_MGNT_QUEUE); 3461 if (status & R92C_IMR_BKDOK) 3462 rtwn_tx_done(sc, RTWN_BK_QUEUE); 3463 if (status & R92C_IMR_BEDOK) 3464 rtwn_tx_done(sc, RTWN_BE_QUEUE); 3465 if (status & R92C_IMR_VIDOK) 3466 rtwn_tx_done(sc, RTWN_VI_QUEUE); 3467 if (status & R92C_IMR_VODOK) 3468 rtwn_tx_done(sc, RTWN_VO_QUEUE); 3469 3470 /* Enable interrupts. */ 3471 rtwn_write_4(sc, R92C_HIMR, RTWN_INT_ENABLE); 3472 3473 RTWN_UNLOCK(sc); 3474 } 3475