1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 5 * Copyright (c) 2012 Stefan Sperling <stsp@openbsd.org> 6 * Copyright (c) 2020 Henri Hennebert <hlh@restart.be> 7 * All rights reserved. 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef _RTSXREG_H_ 29 #define _RTSXREG_H_ 30 31 /* Host command buffer control register. */ 32 #define RTSX_HCBAR 0x00 33 #define RTSX_HCBCTLR 0x04 34 #define RTSX_START_CMD (1U << 31) 35 #define RTSX_HW_AUTO_RSP (1U << 30) 36 #define RTSX_STOP_CMD (1U << 28) 37 38 /* Host data buffer control register. */ 39 #define RTSX_HDBAR 0x08 40 #define RTSX_HDBCTLR 0x0C 41 #define RTSX_TRIG_DMA (1U << 31) 42 #define RTSX_DMA_READ (1U << 29) 43 #define RTSX_STOP_DMA (1U << 28) 44 #define RTSX_ADMA_MODE (2U << 26) 45 46 /* Interrupt pending register. */ 47 #define RTSX_BIPR 0x14 48 #define RTSX_CMD_DONE_INT (1U << 31) 49 #define RTSX_DATA_DONE_INT (1U << 30) 50 #define RTSX_TRANS_OK_INT (1U << 29) 51 #define RTSX_TRANS_FAIL_INT (1U << 28) 52 #define RTSX_XD_INT (1U << 27) 53 #define RTSX_MS_INT (1U << 26) 54 #define RTSX_SD_INT (1U << 25) 55 #define RTSX_DELINK_INT (1U << 24) 56 #define RTSX_SD_WRITE_PROTECT (1U << 19) 57 #define RTSX_XD_EXIST (1U << 18) 58 #define RTSX_MS_EXIST (1U << 17) 59 #define RTSX_SD_EXIST (1U << 16) 60 #define RTSX_CARD_EXIST (RTSX_XD_EXIST|RTSX_MS_EXIST|RTSX_SD_EXIST) 61 #define RTSX_CARD_INT (RTSX_XD_INT|RTSX_MS_INT|RTSX_SD_INT) 62 63 /* Chip register access. */ 64 #define RTSX_HAIMR 0x10 65 #define RTSX_HAIMR_WRITE 0x40000000 66 #define RTSX_HAIMR_BUSY 0x80000000 67 68 /* Interrupt enable register. */ 69 #define RTSX_BIER 0x18 70 #define RTSX_CMD_DONE_INT_EN (1U << 31) 71 #define RTSX_DATA_DONE_INT_EN (1U << 30) 72 #define RTSX_TRANS_OK_INT_EN (1U << 29) 73 #define RTSX_TRANS_FAIL_INT_EN (1U << 28) 74 #define RTSX_XD_INT_EN (1U << 27) 75 #define RTSX_MS_INT_EN (1U << 26) 76 #define RTSX_SD_INT_EN (1U << 25) 77 #define RTSX_GPIO0_INT_EN (1U << 24) 78 #define RTSX_MS_OC_INT_EN (1U << 23) 79 #define RTSX_SD_OC_INT_EN (1U << 22) 80 81 /* Power on/off. */ 82 #define RTSX_FPDCTL 0xFC00 83 #define RTSX_SSC_POWER_DOWN 0x01 84 #define RTSX_SD_OC_POWER_DOWN 0x02 85 #define RTSX_MS_OC_POWER_DOWN 0x04 86 #define RTSX_ALL_POWER_DOWN 0x07 87 #define RTSX_OC_POWER_DOWN 0x06 88 89 /* Card power control register. */ 90 #define RTSX_CARD_PWR_CTL 0xFD50 91 #define RTSX_SD_PWR_ON 0x00 92 #define RTSX_SD_PARTIAL_PWR_ON 0x01 93 #define RTSX_SD_PWR_OFF 0x03 94 #define RTSX_SD_PWR_MASK 0x03 95 96 #define RTSX_PMOS_STRG_MASK 0x10 97 #define RTSX_PMOS_STRG_400mA 0x00 98 #define RTSX_PMOS_STRG_800mA 0x10 99 100 #define RTSX_BPP_POWER_MASK 0x0F 101 #define RTSX_BPP_POWER_OFF 0x0F 102 #define RTSX_BPP_POWER_5_PERCENT_ON 0x0E 103 #define RTSX_BPP_POWER_10_PERCENT_ON 0x0C 104 #define RTSX_BPP_POWER_15_PERCENT_ON 0x08 105 #define RTSX_BPP_POWER_ON 0x00 106 107 #define RTSX_MS_PWR_OFF 0x0C 108 #define RTSX_MS_PWR_ON 0x00 109 #define RTSX_MS_PARTIAL_PWR_ON 0x04 110 111 #define RTSX_RTL8411B_PACKAGE 0xFD51 112 #define RTSX_RTL8411B_QFN48 0x02 113 114 #define RTSX_CARD_SHARE_MODE 0xFD52 115 #define RTSX_CARD_SHARE_MASK 0x0F 116 #define RTSX_CARD_SHARE_48_XD 0x02 117 #define RTSX_CARD_SHARE_48_SD 0x04 118 #define RTSX_CARD_SHARE_48_MS 0x08 119 120 #define RTSX_CARD_DRIVE_SEL 0xFD53 121 #define RTSX_MS_DRIVE_8mA (0x01 << 6) 122 #define RTSX_MMC_DRIVE_8mA (0x01 << 4) 123 #define RTSX_XD_DRIVE_8mA (0x01 << 2) 124 #define RTSX_GPIO_DRIVE_8mA 0x01 125 #define RTSX_CARD_DRIVE_DEFAULT (RTSX_MS_DRIVE_8mA | RTSX_GPIO_DRIVE_8mA) 126 #define RTSX_RTS5209_CARD_DRIVE_DEFAULT (RTSX_MS_DRIVE_8mA | RTSX_MMC_DRIVE_8mA | \ 127 RTSX_XD_DRIVE_8mA | RTSX_GPIO_DRIVE_8mA) 128 #define RTSX_RTL8411_CARD_DRIVE_DEFAULT (RTSX_MS_DRIVE_8mA | RTSX_MMC_DRIVE_8mA | \ 129 RTSX_XD_DRIVE_8mA) 130 131 #define RTSX_CARD_STOP 0xFD54 132 #define RTSX_SPI_STOP 0x01 133 #define RTSX_XD_STOP 0x02 134 #define RTSX_SD_STOP 0x04 135 #define RTSX_MS_STOP 0x08 136 #define RTSX_SPI_CLR_ERR 0x10 137 #define RTSX_XD_CLR_ERR 0x20 138 #define RTSX_SD_CLR_ERR 0x40 139 #define RTSX_MS_CLR_ERR 0x80 140 #define RTSX_ALL_STOP 0x0F 141 #define RTSX_ALL_CLR_ERR 0xF0 142 143 #define RTSX_CARD_OE 0xFD55 144 #define RTSX_XD_OUTPUT_EN 0x02 145 #define RTSX_SD_OUTPUT_EN 0x04 146 #define RTSX_MS_OUTPUT_EN 0x08 147 #define RTSX_SPI_OUTPUT_EN 0x10 148 #define RTSX_CARD_OUTPUT_EN (RTSX_XD_OUTPUT_EN|RTSX_SD_OUTPUT_EN|\ 149 RTSX_MS_OUTPUT_EN) 150 151 #define RTSX_CARD_GPIO_DIR 0xFD57 152 #define RTSX_CARD_GPIO 0xFD58 153 #define RTSX_CARD_GPIO_LED_OFF 0x01 154 155 #define RTSX_SD30_CLK_DRIVE_SEL 0xFD5A 156 #define RTSX_DRIVER_TYPE_A 0x05 157 #define RTSX_DRIVER_TYPE_B 0x03 158 #define RTSX_DRIVER_TYPE_C 0x02 159 #define RTSX_DRIVER_TYPE_D 0x01 160 161 #define RTSX_CARD_DATA_SOURCE 0xFD5B 162 #define RTSX_RING_BUFFER 0x00 163 #define RTSX_PINGPONG_BUFFER 0x01 164 165 #define RTSX_CARD_SELECT 0xFD5C 166 #define RTSX_XD_MOD_SEL 0x01 167 #define RTSX_SD_MOD_SEL 0x02 168 #define RTSX_MS_MOD_SEL 0x03 169 #define RTSX_SPI_MOD_SEL 0x04 170 171 #define RTSX_SD30_CMD_DRIVE_SEL 0xFD5E /* was 0xFE5E in OpenBSD */ 172 #define RTSX_CFG_DRIVER_TYPE_A 0x02 173 #define RTSX_CFG_DRIVER_TYPE_B 0x03 174 #define RTSX_CFG_DRIVER_TYPE_C 0x01 175 #define RTSX_CFG_DRIVER_TYPE_D 0x00 176 #define RTSX_SD30_DRIVE_SEL_MASK 0x07 177 178 #define RTSX_SD30_DAT_DRIVE_SEL 0xFD5F 179 180 /* Card clock. */ 181 #define RTSX_CARD_CLK_EN 0xFD69 182 #define RTSX_XD_CLK_EN 0x02 183 #define RTSX_SD_CLK_EN 0x04 184 #define RTSX_MS_CLK_EN 0x08 185 #define RTSX_SPI_CLK_EN 0x10 186 #define RTSX_CARD_CLK_EN_ALL (RTSX_XD_CLK_EN|RTSX_SD_CLK_EN|\ 187 RTSX_MS_CLK_EN|RTSX_SPI_CLK_EN) 188 189 #define RTSX_SDIO_CTRL 0xFD6B 190 #define RTSX_SDIO_BUS_CTRL 0x01 191 #define RTSX_SDIO_CD_CTRL 0x02 192 193 #define RTSX_CARD_PAD_CTL 0xFD73 194 #define RTSX_CD_DISABLE_MASK 0x07 195 #define RTSX_CD_AUTO_DISABLE 0x40 196 #define RTSX_CD_ENABLE 0x00 197 198 /* Internal clock. */ 199 #define RTSX_CLK_CTL 0xFC02 200 #define RTSX_CHANGE_CLK 0x01 201 #define RTSX_CLK_LOW_FREQ 0x01 202 203 /* Internal clock divisor values. */ 204 #define RTSX_CLK_DIV 0xFC03 205 #define RTSX_CLK_DIV_1 0x01 206 #define RTSX_CLK_DIV_2 0x02 207 #define RTSX_CLK_DIV_4 0x03 208 #define RTSX_CLK_DIV_8 0x04 209 210 /* Internal clock selection. */ 211 #define RTSX_CLK_SEL 0xFC04 212 #define RTSX_SSC_80 0 213 #define RTSX_SSC_100 1 214 #define RTSX_SSC_120 2 215 #define RTSX_SSC_150 3 216 #define RTSX_SSC_200 4 217 218 #define RTSX_SSC_DIV_N_0 0xFC0F 219 220 #define RTSX_SSC_CTL1 0xFC11 221 #define RTSX_RSTB 0x80 222 #define RTSX_SSC_8X_EN 0x40 223 #define RTSX_SSC_FIX_FRAC 0x20 224 #define RTSX_SSC_SEL_1M 0x00 225 #define RTSX_SSC_SEL_2M 0x08 226 #define RTSX_SSC_SEL_2M 0x08 227 #define RTSX_SSC_SEL_4M 0x10 228 #define RTSX_SSC_SEL_8M 0x18 229 230 #define RTSX_SSC_CTL2 0xFC12 231 #define RTSX_SSC_DEPTH_MASK 0x07 232 #define RTSX_SSC_DEPTH_4M 0x01 233 #define RTSX_SSC_DEPTH_2M 0x02 234 #define RTSX_SSC_DEPTH_1M 0x03 235 #define RTSX_SSC_DEPTH_500K 0x04 236 #define RTSX_SSC_DEPTH_250K 0x05 237 238 /* RC oscillator, default is 2M */ 239 #define RTSX_RCCTL 0xFC14 240 #define RTSX_RCCTL_F_400K 0x00 241 #define RTSX_RCCTL_F_2M 0x01 242 243 /* RTS5229-only. */ 244 #define RTSX_OLT_LED_CTL 0xFC1E 245 #define RTSX_OLT_LED_PERIOD 0x02 246 #define RTSX_OLT_LED_AUTOBLINK 0x08 247 248 #define RTSX_LDO_CTL 0xFC1E 249 #define RTSX_BPP_ASIC_3V3 0x07 250 #define RTSX_BPP_ASIC_MASK 0x07 251 #define RTSX_BPP_PAD_3V3 0x04 252 #define RTSX_BPP_PAD_1V8 0x00 253 #define RTSX_BPP_PAD_MASK 0x04 254 #define RTSX_BPP_LDO_POWB 0x03 255 #define RTSX_BPP_LDO_ON 0x00 256 #define RTSX_BPP_LDO_SUSPEND 0x02 257 #define RTSX_BPP_LDO_OFF 0x03 258 #define RTSX_BPP_SHIFT_8402 5 259 #define RTSX_BPP_SHIFT_8411 4 260 261 #define RTSX_GPIO_CTL 0xFC1F 262 #define RTSX_GPIO_LED_ON 0x02 263 264 #define RTSX_SD_VPCLK0_CTL 0xFC2A 265 #define RTSX_SD_VPCLK1_CTL 0xFC2B 266 #define RTSX_PHASE_SELECT_MASK 0x1F 267 #define RTSX_PHASE_NOT_RESET 0x40 268 269 /* Host controller commands. */ 270 #define RTSX_READ_REG_CMD 0 271 #define RTSX_WRITE_REG_CMD 1 272 #define RTSX_CHECK_REG_CMD 2 273 274 #define RTSX_OCPCTL 0xFC15 275 #define RTSX_OCPSTAT 0xFC16 276 #define RTSX_OCPGLITCH 0xFC17 277 #define RTSX_OCPPARA1 0xFC18 278 #define RTSX_OCPPARA2 0xFC19 279 280 /* FPGA */ 281 #define RTSX_FPGA_PULL_CTL 0xFC1D 282 #define RTSX_FPGA_MS_PULL_CTL_BIT 0x10 283 #define RTSX_FPGA_SD_PULL_CTL_BIT 0x08 284 285 /* Clock source configuration register. */ 286 #define RTSX_CARD_CLK_SOURCE 0xFC2E 287 #define RTSX_CRC_FIX_CLK (0x00 << 0) 288 #define RTSX_CRC_VAR_CLK0 (0x01 << 0) 289 #define RTSX_CRC_VAR_CLK1 (0x02 << 0) 290 #define RTSX_SD30_FIX_CLK (0x00 << 2) 291 #define RTSX_SD30_VAR_CLK0 (0x01 << 2) 292 #define RTSX_SD30_VAR_CLK1 (0x02 << 2) 293 #define RTSX_SAMPLE_FIX_CLK (0x00 << 4) 294 #define RTSX_SAMPLE_VAR_CLK0 (0x01 << 4) 295 #define RTSX_SAMPLE_VAR_CLK1 (0x02 << 4) 296 297 298 /* ASIC */ 299 #define RTSX_CARD_PULL_CTL1 0xFD60 300 #define RTSX_CARD_PULL_CTL2 0xFD61 301 #define RTSX_CARD_PULL_CTL3 0xFD62 302 #define RTSX_CARD_PULL_CTL4 0xFD63 303 #define RTSX_CARD_PULL_CTL5 0xFD64 304 #define RTSX_CARD_PULL_CTL6 0xFD65 305 306 #define RTSX_PULL_CTL_DISABLE12 0x55 307 #define RTSX_PULL_CTL_DISABLE3 0xD5 308 #define RTSX_PULL_CTL_DISABLE3_TYPE_C 0xE5 309 #define RTSX_PULL_CTL_ENABLE12 0xAA 310 #define RTSX_PULL_CTL_ENABLE3 0xE9 311 #define RTSX_PULL_CTL_ENABLE3_TYPE_C 0xD9 312 313 /* SD configuration register 1 (clock divider, bus mode and width). */ 314 #define RTSX_SD_CFG1 0xFDA0 315 #define RTSX_CLK_DIVIDE_0 0x00 316 #define RTSX_CLK_DIVIDE_128 0x80 317 #define RTSX_CLK_DIVIDE_256 0xC0 318 #define RTSX_CLK_DIVIDE_MASK 0xC0 319 #define RTSX_SD20_MODE 0x00 320 #define RTSX_SDDDR_MODE 0x04 321 #define RTSX_SD30_MODE 0x08 322 #define RTSX_SD_MODE_MASK 0x0C 323 #define RTSX_BUS_WIDTH_1 0x00 324 #define RTSX_BUS_WIDTH_4 0x01 325 #define RTSX_BUS_WIDTH_8 0x02 326 #define RTSX_SD_ASYNC_FIFO_NOT_RST 0x10 327 #define RTSX_BUS_WIDTH_MASK 0x03 328 329 /* SD configuration register 2 (SD command response flags). */ 330 #define RTSX_SD_CFG2 0xFDA1 331 #define RTSX_SD_CALCULATE_CRC7 0x00 332 #define RTSX_SD_NO_CALCULATE_CRC7 0x80 333 #define RTSX_SD_CHECK_CRC16 0x00 334 #define RTSX_SD_NO_CHECK_CRC16 0x40 335 #define RTSX_SD_NO_CHECK_WAIT_CRC_TO 0x20 336 #define RTSX_SD_WAIT_BUSY_END 0x08 337 #define RTSX_SD_NO_WAIT_BUSY_END 0x00 338 #define RTSX_SD_CHECK_CRC7 0x00 339 #define RTSX_SD_NO_CHECK_CRC7 0x04 340 #define RTSX_SD_RSP_LEN_0 0x00 341 #define RTSX_SD_RSP_LEN_6 0x01 342 #define RTSX_SD_RSP_LEN_17 0x02 343 /* SD command response types. */ 344 #define RTSX_SD_RSP_TYPE_R0 0x04 345 #define RTSX_SD_RSP_TYPE_R1 0x01 346 #define RTSX_SD_RSP_TYPE_R1B 0x09 347 #define RTSX_SD_RSP_TYPE_R2 0x02 348 #define RTSX_SD_RSP_TYPE_R3 0x05 349 #define RTSX_SD_RSP_TYPE_R4 0x05 350 #define RTSX_SD_RSP_TYPE_R5 0x01 351 #define RTSX_SD_RSP_TYPE_R6 0x01 352 #define RTSX_SD_RSP_TYPE_R7 0x01 353 354 #define RTSX_SD_CFG3 0xFDA2 355 #define RTSX_SD30_CLK_END_EN 0x10 356 #define RTSX_SD_RSP_80CLK_TIMEOUT_EN 0x01 357 358 #define RTSX_SD_STAT1 0xFDA3 359 #define RTSX_SD_CRC7_ERR 0x80 360 #define RTSX_SD_CRC16_ERR 0x40 361 #define RTSX_SD_CRC_WRITE_ERR 0x20 362 #define RTSX_SD_CRC_WRITE_ERR_MASK 0x1C 363 #define RTSX_GET_CRC_TIME_OUT 0x02 364 #define RTSX_SD_TUNING_COMPARE_ERR 0x01 365 366 #define RTSX_SD_STAT2 0xFDA4 367 #define RTSX_SD_RSP_80CLK_TIMEOUT 0x01 368 369 #define RTSX_SD_CRC_ERR (RTSX_SD_CRC7_ERR|RTSX_SD_CRC16_ERR|RTSX_SD_CRC_WRITE_ERR) 370 371 /* SD bus status register. */ 372 #define RTSX_SD_BUS_STAT 0xFDA5 373 #define RTSX_SD_CLK_TOGGLE_EN 0x80 374 #define RTSX_SD_CLK_FORCE_STOP 0x40 375 #define RTSX_SD_DAT3_STATUS 0x10 376 #define RTSX_SD_DAT2_STATUS 0x08 377 #define RTSX_SD_DAT1_STATUS 0x04 378 #define RTSX_SD_DAT0_STATUS 0x02 379 #define RTSX_SD_CMD_STATUS 0x01 380 381 #define RTSX_SD_PAD_CTL 0xFDA6 382 #define RTSX_SD_IO_USING_1V8 0x80 383 384 /* Sample point control register. */ 385 #define RTSX_SD_SAMPLE_POINT_CTL 0xFDA7 386 #define RTSX_DDR_FIX_RX_DAT 0x00 387 #define RTSX_DDR_VAR_RX_DAT 0x80 388 #define RTSX_DDR_FIX_RX_DAT_EDGE 0x00 389 #define RTSX_DDR_FIX_RX_DAT_14_DELAY 0x40 390 #define RTSX_DDR_FIX_RX_CMD 0x00 391 #define RTSX_DDR_VAR_RX_CMD 0x20 392 #define RTSX_DDR_FIX_RX_CMD_POS_EDGE 0x00 393 #define RTSX_DDR_FIX_RX_CMD_14_DELAY 0x10 394 #define RTSX_SD20_RX_POS_EDGE 0x00 395 #define RTSX_SD20_RX_14_DELAY 0x08 396 #define RTSX_SD20_RX_SEL_MASK 0x08 397 398 #define RTSX_SD_PUSH_POINT_CTL 0xFDA8 399 #define RTSX_SD20_TX_NEG_EDGE 0x00 400 #define RTSX_SD20_TX_SEL_MASK 0x10 401 #define RTSX_SD20_TX_14_AHEAD 0x10 402 403 #define RTSX_SD_CMD0 0xFDA9 404 #define RTSX_SD_CMD_START 0x40 405 #define RTSX_SD_CMD1 0xFDAA 406 #define RTSX_SD_CMD2 0xFDAB 407 #define RTSX_SD_CMD3 0xFDAC 408 #define RTSX_SD_CMD4 0xFDAD 409 410 #define RTSX_SD_CMD5 0xFDAE 411 #define RTSX_SD_BYTE_CNT_L 0xFDAF 412 #define RTSX_SD_BYTE_CNT_H 0xFDB0 413 #define RTSX_SD_BLOCK_CNT_L 0xFDB1 414 #define RTSX_SD_BLOCK_CNT_H 0xFDB2 415 416 /* 417 * Transfer modes. 418 */ 419 #define RTSX_SD_TRANSFER 0xFDB3 420 421 /* Write one or two bytes from SD_CMD2 and SD_CMD3 to the card. */ 422 #define RTSX_TM_NORMAL_WRITE 0x00 423 424 /* Write (SD_BYTE_CNT * SD_BLOCK_COUNTS) bytes from ring buffer to card. */ 425 #define RTSX_TM_AUTO_WRITE3 0x01 426 427 /* Like AUTO_WRITE3, plus automatically send CMD 12 when done. 428 * The response to CMD 12 is written to SD_CMD{0,1,2,3,4}. */ 429 #define RTSX_TM_AUTO_WRITE4 0x02 430 431 /* Read (SD_BYTE_CNT * SD_BLOCK_CNT) bytes from card into ring buffer. */ 432 #define RTSX_TM_AUTO_READ3 0x05 433 434 /* Like AUTO_READ3, plus automatically send CMD 12 when done. 435 * The response to CMD 12 is written to SD_CMD{0,1,2,3,4}. */ 436 #define RTSX_TM_AUTO_READ4 0x06 437 438 /* Send an SD command described in SD_CMD{0,1,2,3,4} to the card and put 439 * the response into SD_CMD{0,1,2,3,4}. Long responses (17 byte) are put 440 * into ping-pong buffer 2 instead. */ 441 #define RTSX_TM_CMD_RSP 0x08 442 443 /* Send write command, get response from the card, write data from ring 444 * buffer to card, and send CMD 12 when done. 445 * The response to CMD 12 is written to SD_CMD{0,1,2,3,4}. */ 446 #define RTSX_TM_AUTO_WRITE1 0x09 447 448 /* Like AUTO_WRITE1 except no CMD 12 is sent. */ 449 #define RTSX_TM_AUTO_WRITE2 0x0A 450 451 /* Send read command, read up to 512 bytes (SD_BYTE_CNT * SD_BLOCK_CNT) 452 * from the card into the ring buffer or ping-pong buffer 2. */ 453 #define RTSX_TM_NORMAL_READ 0x0C 454 455 /* Same as WRITE1, except data is read from the card to the ring buffer. */ 456 #define RTSX_TM_AUTO_READ1 0x0D 457 458 /* Same as WRITE2, except data is read from the card to the ring buffer. */ 459 #define RTSX_TM_AUTO_READ2 0x0E 460 461 /* Send CMD 19 and receive response and tuning pattern from card and 462 * report the result. */ 463 #define RTSX_TM_AUTO_TUNING 0x0F 464 465 /* transfer control */ 466 #define RTSX_SD_TRANSFER_START 0x80 467 #define RTSX_SD_TRANSFER_END 0x40 468 #define RTSX_SD_STAT_IDLE 0x20 469 #define RTSX_SD_TRANSFER_ERR 0x10 470 471 #define RTSX_SD_CMD_STATE 0xFDB5 472 #define RTSX_SD_CMD_IDLE 0x80 473 474 #define RTSX_SD_DATA_STATE 0xFDB6 475 #define RTSX_SD_DATA_IDLE 0x80 476 477 #define RTSX_REG_SD_STOP_SDCLK_CFG 0xFDB8 478 #define RTSX_SD30_CLK_STOP_CFG_EN 0x04 479 #define RTSX_SD30_CLK_STOP_CFG0 0x01 480 #define RTSX_SD30_CLK_STOP_CFG1 0x02 481 482 #define RTSX_REG_PRE_RW_MODE 0xFD70 483 #define RTSX_EN_INFINITE_MODE 0x01 484 485 /* ping-pong buffer 2 */ 486 #define RTSX_PPBUF_BASE2 0xFA00 487 #define RTSX_PPBUF_SIZE 256 488 489 #define RTSX_SUPPORTED_VOLTAGE (MMC_OCR_300_310|MMC_OCR_310_320|\ 490 MMC_OCR_320_330|MMC_OCR_330_340) 491 492 #define RTSX_CFG_PCI 0x1C 493 #define RTSX_CFG_ASIC 0x10 494 495 #define RTSX_IRQEN0 0xFE20 496 #define RTSX_LINK_DOWN_INT_EN 0x10 497 #define RTSX_LINK_READY_INT_EN 0x20 498 #define RTSX_SUSPEND_INT_EN 0x40 499 #define RTSX_DMA_DONE_INT_EN 0x80 500 501 #define RTSX_IRQSTAT0 0xFE21 502 #define RTSX_LINK_DOWN_INT 0x10 503 #define RTSX_LINK_READY_INT 0x20 504 #define RTSX_SUSPEND_INT 0x40 505 #define RTSX_DMA_DONE_INT 0x80 506 507 #define RTSX_DMATC0 0xFE28 508 #define RTSX_DMATC1 0xFE29 509 #define RTSX_DMATC2 0xFE2A 510 #define RTSX_DMATC3 0xFE2B 511 512 #define RTSX_DMACTL 0xFE2C 513 #define RTSX_DMA_EN 0x01 514 #define RTSX_DMA_DIR 0x02 515 #define RTSX_DMA_DIR_TO_CARD 0x00 516 #define RTSX_DMA_DIR_FROM_CARD 0x02 517 #define RTSX_DMA_BUSY 0x04 518 #define RTSX_DMA_RST 0x80 519 #define RTSX_DMA_128 (0 << 4) 520 #define RTSX_DMA_256 (1 << 4) 521 #define RTSX_DMA_512 (2 << 4) 522 #define RTSX_DMA_1024 (3 << 4) 523 #define RTSX_DMA_PACK_SIZE_MASK 0x30 524 525 #define RTSX_RBCTL 0xFE34 526 #define RTSX_RB_FLUSH 0x80 527 #define RTSX_U_AUTO_DMA_EN_MASK 0x20 528 #define RTSX_U_AUTO_DMA_DISABLE 0x00 529 530 #define RTSX_CFGADDR0 0xFE35 531 #define RTSX_CFGADDR1 0xFE36 532 #define RTSX_CFGDATA0 0xFE37 533 #define RTSX_CFGDATA1 0xFE38 534 #define RTSX_CFGDATA2 0xFE39 535 #define RTSX_CFGDATA3 0xFE3A 536 #define RTSX_CFGRWCTL 0xFE3B 537 #define RTSX_CFG_WRITE_DATA0 0x01 538 #define RTSX_CFG_WRITE_DATA1 0x02 539 #define RTSX_CFG_WRITE_DATA2 0x04 540 #define RTSX_CFG_WRITE_DATA3 0x08 541 #define RTSX_CFG_BUSY 0x80 542 543 #define RTSX_LTR_CTL 0xFE4A 544 545 #define RTSX_OBFF_CFG 0xFE4C 546 #define RTSX_OBFF_EN_MASK 0x03 547 #define RTSX_OBFF_DISABLE 0x00 548 #define RTSX_OBFF_ENABLE 0x03 549 550 #define RTSX_SDIOCFG_REG 0x724 551 #define RTSX_SDIOCFG_NO_BYPASS_SDIO 0x02 552 #define RTSX_SDIOCFG_HAVE_SDIO 0x04 553 #define RTSX_SDIOCFG_SINGLE_LUN 0x08 554 #define RTSX_SDIOCFG_SDIO_ONLY 0x80 555 556 #define RTSX_HOST_SLEEP_STATE 0xFE60 557 #define RTSX_HOST_ENTER_S1 0x01 558 #define RTSX_HOST_ENTER_S3 0x02 559 560 #define RTSX_SDIO_CFG 0xFE70 561 #define RTSX_SDIO_BUS_AUTO_SWITCH 0x10 562 563 #define RTSX_NFTS_TX_CTRL 0xFE72 564 #define RTSX_INT_READ_CLR 0x02 565 566 #define RTSX_PWR_GATE_CTRL 0xFE75 567 #define RTSX_PWR_GATE_EN 0x01 568 #define RTSX_LDO3318_PWR_MASK 0x06 569 #define RTSX_LDO3318_ON 0x00 570 #define RTSX_LDO3318_SUSPEND 0x04 571 #define RTSX_LDO3318_OFF 0x06 572 #define RTSX_LDO3318_VCC1 0x02 573 #define RTSX_LDO3318_VCC2 0x04 574 #define RTSX_PWD_SUSPEND_EN 0xFE76 575 #define RTSX_LDO_PWR_SEL 0xFE78 576 #define RTSX_LDO_PWR_SEL_3V3 0x01 577 #define RTSX_LDO_PWR_SEL_DV33 0x03 578 579 #define RTSX_PHY_RWCTL 0xFE3C 580 #define RTSX_PHY_READ 0x00 581 #define RTSX_PHY_WRITE 0x01 582 #define RTSX_PHY_BUSY 0x80 583 #define RTSX_PHY_DATA0 0xFE3D 584 #define RTSX_PHY_DATA1 0xFE3E 585 #define RTSX_PHY_ADDR 0xFE3F 586 587 #define RTSX_PHY_PCR 0x00 588 #define RTSX_PHY_PCR_FORCE_CODE 0xB000 589 #define RTSX_PHY_PCR_OOBS_CALI_50 0x0800 590 #define RTSX_PHY_PCR_OOBS_VCM_08 0x0200 591 #define RTSX_PHY_PCR_OOBS_SEN_90 0x0040 592 #define RTSX_PHY_PCR_RSSI_EN 0x0002 593 #define RTSX_PHY_PCR_RX10K 0x0001 594 595 #define RTSX_PHY_RCR1 0x02 596 #define RTSX_PHY_RCR1_ADP_TIME_4 0x0400 597 #define RTSX_PHY_RCR1_VCO_COARSE 0x001F 598 #define RTSX_PHY_RCR1_INIT_27S 0x0A1F 599 600 #define RTSX_PHY_RCR2 0x03 601 #define RTSX_PHY_RCR2_EMPHASE_EN 0x8000 602 #define RTSX_PHY_RCR2_NADJR 0x4000 603 #define RTSX_PHY_RCR2_CDR_SR_2 0x0100 604 #define RTSX_PHY_RCR2_FREQSEL_12 0x0040 605 #define RTSX_PHY_RCR2_CDR_SC_12P 0x0010 606 #define RTSX_PHY_RCR2_CALIB_LATE 0x0002 607 #define RTSX_PHY_RCR2_INIT_27S 0xC152 608 609 #define RTSX__PHY_ANA03 0x03 610 #define RTSX__PHY_ANA03_TIMER_MAX 0x2700 611 #define RTSX__PHY_ANA03_OOBS_DEB_EN 0x0040 612 #define RTSX__PHY_CMU_DEBUG_EN 0x0008 613 614 #define RTSX_PHY_RDR 0x05 615 #define RTSX_PHY_RDR_RXDSEL_1_9 0x4000 616 #define RTSX_PHY_SSC_AUTO_PWD 0x0600 617 618 #define RTSX_PHY_TUNE 0x08 619 #define RTSX_PHY_TUNE_TUNEREF_1_0 0x4000 620 #define RTSX_PHY_TUNE_VBGSEL_1252 0x0C00 621 #define RTSX_PHY_TUNE_SDBUS_33 0x0200 622 #define RTSX_PHY_TUNE_TUNED18 0x01C0 623 #define RTSX_PHY_TUNE_TUNED12 0X0020 624 #define RTSX_PHY_TUNE_TUNEA12 0x0004 625 #define RTSX_PHY_TUNE_VOLTAGE_MASK 0xFC3F 626 #define RTSX_PHY_TUNE_VOLTAGE_3V3 0x03C0 627 #define RTSX_PHY_TUNE_D18_1V8 0x0100 628 #define RTSX_PHY_TUNE_D18_1V7 0x0080 629 630 #define RTSX_PHY_BPCR 0x0A 631 #define RTSX_PHY_BPCR_IBRXSEL 0x0400 632 #define RTSX_PHY_BPCR_IBTXSEL 0x0100 633 #define RTSX_PHY_BPCR_IB_FILTER 0x0080 634 #define RTSX_PHY_BPCR_CMIRROR_EN 0x0040 635 636 #define RTSX_PHY_REV 0x19 637 #define RTSX_PHY_REV_RESV 0xE000 638 #define RTSX_PHY_REV_RXIDLE_LATCHED 0x1000 639 #define RTSX_PHY_REV_P1_EN 0x0800 640 #define RTSX_PHY_REV_RXIDLE_EN 0x0400 641 #define RTSX_PHY_REV_CLKREQ_TX_EN 0x0200 642 #define RTSX_PHY_REV_CLKREQ_RX_EN 0x0100 643 #define RTSX_PHY_REV_CLKREQ_DT_1_0 0x0040 644 #define RTSX_PHY_REV_STOP_CLKRD 0x0020 645 #define RTSX_PHY_REV_RX_PWST 0x0008 646 #define RTSX_PHY_REV_STOP_CLKWR 0x0004 647 648 649 #define RTSX__PHY_REV0 0x19 650 #define RTSX__PHY_REV0_FILTER_OUT 0x3800 651 #define RTSX__PHY_REV0_CDR_BYPASS_PFD 0x0100 652 #define RTSX__PHY_REV0_CDR_RX_IDLE_BYPASS 0x0002 653 654 #define RTSX_PHY_FLD0 0x1A 655 #define RTSX_PHY_FLD0_INIT_27S 0x2546 656 657 #define RTSX_PHY_FLD3 0x1D 658 #define RTSX_PHY_FLD3_TIMER_4 0x0800 659 #define RTSX_PHY_FLD3_TIMER_6 0x0020 660 #define RTSX_PHY_FLD3_RXDELINK 0x0004 661 #define RTSX_PHY_FLD3_INIT_27S 0x0004 662 663 #define RTSX__PHY_FLD0 0x1D 664 #define RTSX__PHY_FLD0_CLK_REQ_20C 0x8000 665 #define RTSX__PHY_FLD0_RX_IDLE_EN 0x1000 666 #define RTSX__PHY_FLD0_BIT_ERR_RSTN 0x0800 667 #define RTSX__PHY_FLD0_BER_COUNT 0x01E0 668 #define RTSX__PHY_FLD0_BER_TIMER 0x001E 669 #define RTSX__PHY_FLD0_CHECK_EN 0x0001 670 671 #define RTSX_PHY_FLD4 0x1E 672 #define RTSX_PHY_FLD4_FLDEN_SEL 0x4000 673 #define RTSX_PHY_FLD4_REQ_REF 0x2000 674 #define RTSX_PHY_FLD4_RXAMP_OFF 0x1000 675 #define RTSX_PHY_FLD4_REQ_ADDA 0x0800 676 #define RTSX_PHY_FLD4_BER_COUNT 0x00E0 677 #define RTSX_PHY_FLD4_BER_TIMER 0x000A 678 #define RTSX_PHY_FLD4_BER_CHK_EN 0x0001 679 #define RTSX_PHY_FLD4_INIT_27S 0x5C7F 680 681 #define RTSX_CARD_AUTO_BLINK 0xFD56 682 #define RTSX_LED_BLINK_EN 0x08 683 #define RTSX_LED_BLINK_SPEED 0x05 684 685 #define RTSX_PCLK_CTL 0xFE55 686 #define RTSX_PCLK_MODE_SEL 0x20 687 688 #define RTSX_PME_FORCE_CTL 0xFE56 689 690 #define RTSX_ASPM_FORCE_CTL 0xFE57 691 #define RTSX_ASPM_FORCE_MASK 0x3F 692 #define RTSX_FORCE_ASPM_NO_ASPM 0x00 693 694 #define RTSX_PM_CLK_FORCE_CTL 0xFE58 695 #define RTSX_CLK_PM_EN 0x01 696 697 #define RTSX_FUNC_FORCE_CTL 0xFE59 698 #define RTSX_FUNC_FORCE_UPME_XMT_DBG 0x02 699 700 #define RTSX_CHANGE_LINK_STATE 0xFE5B 701 #define RTSX_CD_RST_CORE_EN 0x01 702 #define RTSX_FORCE_RST_CORE_EN 0x02 703 #define RTSX_NON_STICKY_RST_N_DBG 0x08 704 #define RTSX_MAC_PHY_RST_N_DBG 0x10 705 706 #define RTSX_PERST_GLITCH_WIDTH 0xFE5C 707 708 #define RTSX_EFUSE_CONTENT 0xFE5F 709 710 #define RTSX_PM_EVENT_DEBUG 0xFE71 711 #define RTSX_PME_DEBUG_0 0x08 712 713 #define RTSX_L1SUB_CONFIG1 0xFE8D 714 #define RTSX_AUX_CLK_ACTIVE_SEL_MASK 0x01 715 #define RTSX_MAC_CKSW_DONE 0x00 716 717 #define RTSX_L1SUB_CONFIG2 0xFE8E 718 #define RTSX_L1SUB_AUTO_CFG 0x02 719 720 #define RTSX_L1SUB_CONFIG3 0xFE8F 721 722 #define RTSX_DUMMY_REG 0xFE90 723 724 #define RTSX_REG_VREF 0xFE97 725 #define RTSX_PWD_SUSPND_EN 0x10 726 727 #define RTSX_RTS5260_DMA_RST_CTL_0 0xFEBF 728 #define RTSX_RTS5260_DMA_RST 0x80 729 #define RTSX_RTS5260_ADMA3_RST 0x40 730 731 #define RTSX_PETXCFG 0xFF03 /* was 0xFE49 in OpenBSD */ 732 #define RTSX_FORCE_CLKREQ_DELINK_MASK 0x80 733 #define RTSX_FORCE_CLKREQ_LOW 0x80 734 735 #define RTSX_RREF_CFG 0xFF6C 736 #define RTSX_RREF_VBGSEL_MASK 0x38 737 #define RTSX_RREF_VBGSEL_1V25 0x28 738 739 #define RTSX_PM_CTRL3 0xFF46 740 #define RTSX_RTS522A_PM_CTRL3 0xFF7E 741 #define RTSX_D3_DELINK_MODE_EN 0x10 742 #define RTSX_PM_WAKE_EN 0x01 743 744 #define RTSX_OOBS_CONFIG 0xFF6E 745 #define RTSX_OOBS_AUTOK_DIS 0x80 746 #define RTSX_OOBS_VAL_MASK 0x1F 747 748 #define RTSX_LDO_DV18_CFG 0xFF70 749 #define RTSX_DV331812_MASK 0x70 750 #define RTSX_DV331812_33 0x70 751 752 #define RTSX_LDO_CONFIG2 0xFF71 753 #define RTSX_LDO_D3318_MASK 0x07 754 #define RTSX_LDO_D3318_33V 0x07 755 #define RTSX_LDO_D3318_18V 0x02 756 #define RTSX_DV331812_VDD1 0x04 757 #define RTSX_DV331812_POWERON 0x08 758 #define RTSX_DV331812_POWEROFF 0x00 759 760 #define RTSX_LDO_VCC_CFG0 0xFF72 761 #define RTSX_LDO_VCC_LMTVTH_MASK 0x30 762 #define RTSX_LDO_VCC_LMTVTH_2A 0x10 763 #define RTSX_RTS5260_DVCC_TUNE_MASK 0x70 764 #define RTSX_RTS5260_DVCC_33 0x70 765 766 #define RTSX_LDO_VCC_CFG1 0xFF73 767 #define RTSX_LDO_VCC_REF_TUNE_MASK 0x30 768 #define RTSX_LDO_VCC_REF_1V2 0x20 769 #define RTSX_LDO_VCC_TUNE_MASK 0x07 770 #define RTSX_LDO_VCC_1V8 0x04 771 #define RTSX_LDO_VCC_3V3 0x07 772 #define RTSX_LDO_VCC_LMT_EN 0x08 773 /*RTS5260*/ 774 #define RTSX_LDO_POW_SDVDD1_MASK 0x08 775 #define RTSX_LDO_POW_SDVDD1_ON 0x08 776 #define RTSX_LDO_POW_SDVDD1_OFF 0x00 777 778 #define RTSX_RTS5260_DVCC_CTRL 0xFF73 779 #define RTSX_RTS5260_DVCC_OCP_EN (0x01 << 7) 780 #define RTSX_RTS5260_DVCC_OCP_THD_MASK (0x07 << 4) 781 #define RTSX_RTS5260_DVCC_POWERON (0x01 << 3) 782 #define RTSX_RTS5260_DVCC_OCP_CL_EN (0x01 << 2) 783 784 #define RTSX_LDO_VIO_CFG 0xFF75 785 #define RTSX_LDO_VIO_TUNE_MASK 0x07 786 #define RTSX_LDO_VIO_1V7 0x03 787 788 #define RTSX_LDO_DV12S_CFG 0xFF76 789 #define RTSX_LDO_D12_TUNE_MASK 0x07 790 #define RTSX_LDO_D12_TUNE_DF 0x04 791 792 #define RTSX_LDO_AV12S_CFG 0xFF77 793 #define RTSX_LDO_AV12S_TUNE_MASK 0x07 794 #define RTSX_LDO_AV12S_TUNE_DF 0x04 795 796 #define RTSX_SG_INT 0x04 797 #define RTSX_SG_END 0x02 798 #define RTSX_SG_VALID 0x01 799 800 #define RTSX_SG_NO_OP 0x00 801 #define RTSX_SG_TRANS_DATA (0x02 << 4) 802 #define RTSX_SG_LINK_DESC (0x03 << 4) 803 804 #define RTSX_IC_VERSION_A 0x00 805 #define RTSX_IC_VERSION_B 0x01 806 #define RTSX_IC_VERSION_C 0x02 807 #define RTSX_IC_VERSION_D 0x03 808 809 #define RTSX_RTS5260_AUTOLOAD_CFG4 0xFF7F 810 #define RTSX_RTS5260_MIMO_DISABLE 0x8A 811 812 #define RTSX_PCR_SETTING_REG1 0x724 813 #define RTSX_PCR_SETTING_REG2 0x814 814 #define RTSX_PCR_SETTING_REG3 0x747 815 816 #define RTSX_RX_PHASE_MAX 32 817 #define RTSX_RX_TUNING_CNT 3 818 #endif 819