1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 5 * Copyright (c) 2012 Stefan Sperling <stsp@openbsd.org> 6 * Copyright (c) 2020 Henri Hennebert <hlh@restart.be> 7 * All rights reserved. 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef _RTSXREG_H_ 29 #define _RTSXREG_H_ 30 31 #if __FreeBSD_version < 1200000 32 #define IO_SEND_OP_COND 5 33 #endif 34 35 /* Host command buffer control register. */ 36 #define RTSX_HCBAR 0x00 37 #define RTSX_HCBCTLR 0x04 38 #define RTSX_START_CMD (1U << 31) 39 #define RTSX_HW_AUTO_RSP (1U << 30) 40 #define RTSX_STOP_CMD (1U << 28) 41 42 /* Host data buffer control register. */ 43 #define RTSX_HDBAR 0x08 44 #define RTSX_HDBCTLR 0x0C 45 #define RTSX_TRIG_DMA (1U << 31) 46 #define RTSX_DMA_READ (1U << 29) 47 #define RTSX_STOP_DMA (1U << 28) 48 #define RTSX_ADMA_MODE (2U << 26) 49 50 /* Interrupt pending register. */ 51 #define RTSX_BIPR 0x14 52 #define RTSX_CMD_DONE_INT (1U << 31) 53 #define RTSX_DATA_DONE_INT (1U << 30) 54 #define RTSX_TRANS_OK_INT (1U << 29) 55 #define RTSX_TRANS_FAIL_INT (1U << 28) 56 #define RTSX_XD_INT (1U << 27) 57 #define RTSX_MS_INT (1U << 26) 58 #define RTSX_SD_INT (1U << 25) 59 #define RTSX_DELINK_INT (1U << 24) 60 #define RTSX_SD_WRITE_PROTECT (1U << 19) 61 #define RTSX_XD_EXIST (1U << 18) 62 #define RTSX_MS_EXIST (1U << 17) 63 #define RTSX_SD_EXIST (1U << 16) 64 #define RTSX_CARD_EXIST (RTSX_XD_EXIST|RTSX_MS_EXIST|RTSX_SD_EXIST) 65 #define RTSX_CARD_INT (RTSX_XD_INT|RTSX_MS_INT|RTSX_SD_INT) 66 67 /* Chip register access. */ 68 #define RTSX_HAIMR 0x10 69 #define RTSX_HAIMR_WRITE 0x40000000 70 #define RTSX_HAIMR_BUSY 0x80000000 71 72 /* Interrupt enable register. */ 73 #define RTSX_BIER 0x18 74 #define RTSX_CMD_DONE_INT_EN (1U << 31) 75 #define RTSX_DATA_DONE_INT_EN (1U << 30) 76 #define RTSX_TRANS_OK_INT_EN (1U << 29) 77 #define RTSX_TRANS_FAIL_INT_EN (1U << 28) 78 #define RTSX_XD_INT_EN (1U << 27) 79 #define RTSX_MS_INT_EN (1U << 26) 80 #define RTSX_SD_INT_EN (1U << 25) 81 #define RTSX_GPIO0_INT_EN (1U << 24) 82 #define RTSX_MS_OC_INT_EN (1U << 23) 83 #define RTSX_SD_OC_INT_EN (1U << 22) 84 85 /* Power on/off. */ 86 #define RTSX_FPDCTL 0xFC00 87 #define RTSX_SSC_POWER_DOWN 0x01 88 #define RTSX_SD_OC_POWER_DOWN 0x02 89 #define RTSX_MS_OC_POWER_DOWN 0x04 90 #define RTSX_ALL_POWER_DOWN 0x07 91 #define RTSX_OC_POWER_DOWN 0x06 92 93 /* Card power control register. */ 94 #define RTSX_CARD_PWR_CTL 0xFD50 95 #define RTSX_SD_PWR_ON 0x00 96 #define RTSX_SD_PARTIAL_PWR_ON 0x01 97 #define RTSX_SD_PWR_OFF 0x03 98 #define RTSX_SD_PWR_MASK 0x03 99 100 #define RTSX_PMOS_STRG_MASK 0x10 101 #define RTSX_PMOS_STRG_400mA 0x00 102 #define RTSX_PMOS_STRG_800mA 0x10 103 104 #define RTSX_BPP_POWER_MASK 0x0F 105 #define RTSX_BPP_POWER_OFF 0x0F 106 #define RTSX_BPP_POWER_5_PERCENT_ON 0x0E 107 #define RTSX_BPP_POWER_10_PERCENT_ON 0x0C 108 #define RTSX_BPP_POWER_15_PERCENT_ON 0x08 109 #define RTSX_BPP_POWER_ON 0x00 110 111 #define RTSX_MS_PWR_OFF 0x0C 112 #define RTSX_MS_PWR_ON 0x00 113 #define RTSX_MS_PARTIAL_PWR_ON 0x04 114 115 #define RTSX_RTL8411B_PACKAGE 0xFD51 116 #define RTSX_RTL8411B_QFN48 0x02 117 118 #define RTSX_CARD_SHARE_MODE 0xFD52 119 #define RTSX_CARD_SHARE_MASK 0x0F 120 #define RTSX_CARD_SHARE_48_XD 0x02 121 #define RTSX_CARD_SHARE_48_SD 0x04 122 #define RTSX_CARD_SHARE_48_MS 0x08 123 124 #define RTSX_CARD_DRIVE_SEL 0xFD53 125 #define RTSX_MS_DRIVE_8mA (0x01 << 6) 126 #define RTSX_MMC_DRIVE_8mA (0x01 << 4) 127 #define RTSX_XD_DRIVE_8mA (0x01 << 2) 128 #define RTSX_GPIO_DRIVE_8mA 0x01 129 #define RTSX_CARD_DRIVE_DEFAULT (RTSX_MS_DRIVE_8mA | RTSX_GPIO_DRIVE_8mA) 130 #define RTSX_RTS5209_CARD_DRIVE_DEFAULT (RTSX_MS_DRIVE_8mA | RTSX_MMC_DRIVE_8mA | \ 131 RTSX_XD_DRIVE_8mA | RTSX_GPIO_DRIVE_8mA) 132 #define RTSX_RTL8411_CARD_DRIVE_DEFAULT (RTSX_MS_DRIVE_8mA | RTSX_MMC_DRIVE_8mA | \ 133 RTSX_XD_DRIVE_8mA) 134 135 #define RTSX_CARD_STOP 0xFD54 136 #define RTSX_SPI_STOP 0x01 137 #define RTSX_XD_STOP 0x02 138 #define RTSX_SD_STOP 0x04 139 #define RTSX_MS_STOP 0x08 140 #define RTSX_SPI_CLR_ERR 0x10 141 #define RTSX_XD_CLR_ERR 0x20 142 #define RTSX_SD_CLR_ERR 0x40 143 #define RTSX_MS_CLR_ERR 0x80 144 #define RTSX_ALL_STOP 0x0F 145 #define RTSX_ALL_CLR_ERR 0xF0 146 147 #define RTSX_CARD_OE 0xFD55 148 #define RTSX_XD_OUTPUT_EN 0x02 149 #define RTSX_SD_OUTPUT_EN 0x04 150 #define RTSX_MS_OUTPUT_EN 0x08 151 #define RTSX_SPI_OUTPUT_EN 0x10 152 #define RTSX_CARD_OUTPUT_EN (RTSX_XD_OUTPUT_EN|RTSX_SD_OUTPUT_EN|\ 153 RTSX_MS_OUTPUT_EN) 154 155 #define RTSX_CARD_GPIO_DIR 0xFD57 156 #define RTSX_CARD_GPIO 0xFD58 157 #define RTSX_CARD_GPIO_LED_OFF 0x01 158 159 #define RTSX_SD30_CLK_DRIVE_SEL 0xFD5A 160 #define RTSX_DRIVER_TYPE_A 0x05 161 #define RTSX_DRIVER_TYPE_B 0x03 162 #define RTSX_DRIVER_TYPE_C 0x02 163 #define RTSX_DRIVER_TYPE_D 0x01 164 165 #define RTSX_CARD_DATA_SOURCE 0xFD5B 166 #define RTSX_RING_BUFFER 0x00 167 #define RTSX_PINGPONG_BUFFER 0x01 168 169 #define RTSX_CARD_SELECT 0xFD5C 170 #define RTSX_XD_MOD_SEL 0x01 171 #define RTSX_SD_MOD_SEL 0x02 172 #define RTSX_MS_MOD_SEL 0x03 173 #define RTSX_SPI_MOD_SEL 0x04 174 175 #define RTSX_SD30_CMD_DRIVE_SEL 0xFD5E /* was 0xFE5E in OpenBSD */ 176 #define RTSX_CFG_DRIVER_TYPE_A 0x02 177 #define RTSX_CFG_DRIVER_TYPE_B 0x03 178 #define RTSX_CFG_DRIVER_TYPE_C 0x01 179 #define RTSX_CFG_DRIVER_TYPE_D 0x00 180 #define RTSX_SD30_DRIVE_SEL_MASK 0x07 181 182 #define RTSX_SD30_DAT_DRIVE_SEL 0xFD5F 183 184 /* Card clock. */ 185 #define RTSX_CARD_CLK_EN 0xFD69 186 #define RTSX_XD_CLK_EN 0x02 187 #define RTSX_SD_CLK_EN 0x04 188 #define RTSX_MS_CLK_EN 0x08 189 #define RTSX_SPI_CLK_EN 0x10 190 #define RTSX_CARD_CLK_EN_ALL (RTSX_XD_CLK_EN|RTSX_SD_CLK_EN|\ 191 RTSX_MS_CLK_EN|RTSX_SPI_CLK_EN) 192 193 #define RTSX_SDIO_CTRL 0xFD6B 194 #define RTSX_SDIO_BUS_CTRL 0x01 195 #define RTSX_SDIO_CD_CTRL 0x02 196 197 #define RTSX_CARD_PAD_CTL 0xFD73 198 #define RTSX_CD_DISABLE_MASK 0x07 199 #define RTSX_CD_AUTO_DISABLE 0x40 200 #define RTSX_CD_ENABLE 0x00 201 202 /* Internal clock. */ 203 #define RTSX_CLK_CTL 0xFC02 204 #define RTSX_CHANGE_CLK 0x01 205 #define RTSX_CLK_LOW_FREQ 0x01 206 207 /* Internal clock divisor values. */ 208 #define RTSX_CLK_DIV 0xFC03 209 #define RTSX_CLK_DIV_1 0x01 210 #define RTSX_CLK_DIV_2 0x02 211 #define RTSX_CLK_DIV_4 0x03 212 #define RTSX_CLK_DIV_8 0x04 213 214 /* Internal clock selection. */ 215 #define RTSX_CLK_SEL 0xFC04 216 #define RTSX_SSC_80 0 217 #define RTSX_SSC_100 1 218 #define RTSX_SSC_120 2 219 #define RTSX_SSC_150 3 220 #define RTSX_SSC_200 4 221 222 #define RTSX_SSC_DIV_N_0 0xFC0F 223 224 #define RTSX_SSC_CTL1 0xFC11 225 #define RTSX_RSTB 0x80 226 #define RTSX_SSC_8X_EN 0x40 227 #define RTSX_SSC_FIX_FRAC 0x20 228 #define RTSX_SSC_SEL_1M 0x00 229 #define RTSX_SSC_SEL_2M 0x08 230 #define RTSX_SSC_SEL_2M 0x08 231 #define RTSX_SSC_SEL_4M 0x10 232 #define RTSX_SSC_SEL_8M 0x18 233 234 #define RTSX_SSC_CTL2 0xFC12 235 #define RTSX_SSC_DEPTH_MASK 0x07 236 #define RTSX_SSC_DEPTH_4M 0x01 237 #define RTSX_SSC_DEPTH_2M 0x02 238 #define RTSX_SSC_DEPTH_1M 0x03 239 #define RTSX_SSC_DEPTH_500K 0x04 240 #define RTSX_SSC_DEPTH_250K 0x05 241 242 /* RC oscillator, default is 2M */ 243 #define RTSX_RCCTL 0xFC14 244 #define RTSX_RCCTL_F_400K 0x00 245 #define RTSX_RCCTL_F_2M 0x01 246 247 /* RTS5229-only. */ 248 #define RTSX_OLT_LED_CTL 0xFC1E 249 #define RTSX_OLT_LED_PERIOD 0x02 250 #define RTSX_OLT_LED_AUTOBLINK 0x08 251 252 #define RTSX_LDO_CTL 0xFC1E 253 #define RTSX_BPP_ASIC_3V3 0x07 254 #define RTSX_BPP_ASIC_MASK 0x07 255 #define RTSX_BPP_PAD_3V3 0x04 256 #define RTSX_BPP_PAD_1V8 0x00 257 #define RTSX_BPP_PAD_MASK 0x04 258 #define RTSX_BPP_LDO_POWB 0x03 259 #define RTSX_BPP_LDO_ON 0x00 260 #define RTSX_BPP_LDO_SUSPEND 0x02 261 #define RTSX_BPP_LDO_OFF 0x03 262 #define RTSX_BPP_SHIFT_8402 5 263 #define RTSX_BPP_SHIFT_8411 4 264 265 #define RTSX_GPIO_CTL 0xFC1F 266 #define RTSX_GPIO_LED_ON 0x02 267 268 #define RTSX_SD_VPCLK0_CTL 0xFC2A 269 #define RTSX_SD_VPCLK1_CTL 0xFC2B 270 #define RTSX_PHASE_SELECT_MASK 0x1F 271 #define RTSX_PHASE_NOT_RESET 0x40 272 273 /* Host controller commands. */ 274 #define RTSX_READ_REG_CMD 0 275 #define RTSX_WRITE_REG_CMD 1 276 #define RTSX_CHECK_REG_CMD 2 277 278 #define RTSX_OCPCTL 0xFC15 279 #define RTSX_OCPSTAT 0xFC16 280 #define RTSX_OCPGLITCH 0xFC17 281 #define RTSX_OCPPARA1 0xFC18 282 #define RTSX_OCPPARA2 0xFC19 283 284 /* FPGA */ 285 #define RTSX_FPGA_PULL_CTL 0xFC1D 286 #define RTSX_FPGA_MS_PULL_CTL_BIT 0x10 287 #define RTSX_FPGA_SD_PULL_CTL_BIT 0x08 288 289 /* Clock source configuration register. */ 290 #define RTSX_CARD_CLK_SOURCE 0xFC2E 291 #define RTSX_CRC_FIX_CLK (0x00 << 0) 292 #define RTSX_CRC_VAR_CLK0 (0x01 << 0) 293 #define RTSX_CRC_VAR_CLK1 (0x02 << 0) 294 #define RTSX_SD30_FIX_CLK (0x00 << 2) 295 #define RTSX_SD30_VAR_CLK0 (0x01 << 2) 296 #define RTSX_SD30_VAR_CLK1 (0x02 << 2) 297 #define RTSX_SAMPLE_FIX_CLK (0x00 << 4) 298 #define RTSX_SAMPLE_VAR_CLK0 (0x01 << 4) 299 #define RTSX_SAMPLE_VAR_CLK1 (0x02 << 4) 300 301 302 /* ASIC */ 303 #define RTSX_CARD_PULL_CTL1 0xFD60 304 #define RTSX_CARD_PULL_CTL2 0xFD61 305 #define RTSX_CARD_PULL_CTL3 0xFD62 306 #define RTSX_CARD_PULL_CTL4 0xFD63 307 #define RTSX_CARD_PULL_CTL5 0xFD64 308 #define RTSX_CARD_PULL_CTL6 0xFD65 309 310 #define RTSX_PULL_CTL_DISABLE12 0x55 311 #define RTSX_PULL_CTL_DISABLE3 0xD5 312 #define RTSX_PULL_CTL_DISABLE3_TYPE_C 0xE5 313 #define RTSX_PULL_CTL_ENABLE12 0xAA 314 #define RTSX_PULL_CTL_ENABLE3 0xE9 315 #define RTSX_PULL_CTL_ENABLE3_TYPE_C 0xD9 316 317 /* SD configuration register 1 (clock divider, bus mode and width). */ 318 #define RTSX_SD_CFG1 0xFDA0 319 #define RTSX_CLK_DIVIDE_0 0x00 320 #define RTSX_CLK_DIVIDE_128 0x80 321 #define RTSX_CLK_DIVIDE_256 0xC0 322 #define RTSX_CLK_DIVIDE_MASK 0xC0 323 #define RTSX_SD20_MODE 0x00 324 #define RTSX_SDDDR_MODE 0x04 325 #define RTSX_SD30_MODE 0x08 326 #define RTSX_SD_MODE_MASK 0x0C 327 #define RTSX_BUS_WIDTH_1 0x00 328 #define RTSX_BUS_WIDTH_4 0x01 329 #define RTSX_BUS_WIDTH_8 0x02 330 #define RTSX_SD_ASYNC_FIFO_NOT_RST 0x10 331 #define RTSX_BUS_WIDTH_MASK 0x03 332 333 /* SD configuration register 2 (SD command response flags). */ 334 #define RTSX_SD_CFG2 0xFDA1 335 #define RTSX_SD_CALCULATE_CRC7 0x00 336 #define RTSX_SD_NO_CALCULATE_CRC7 0x80 337 #define RTSX_SD_CHECK_CRC16 0x00 338 #define RTSX_SD_NO_CHECK_CRC16 0x40 339 #define RTSX_SD_NO_CHECK_WAIT_CRC_TO 0x20 340 #define RTSX_SD_WAIT_BUSY_END 0x08 341 #define RTSX_SD_NO_WAIT_BUSY_END 0x00 342 #define RTSX_SD_CHECK_CRC7 0x00 343 #define RTSX_SD_NO_CHECK_CRC7 0x04 344 #define RTSX_SD_RSP_LEN_0 0x00 345 #define RTSX_SD_RSP_LEN_6 0x01 346 #define RTSX_SD_RSP_LEN_17 0x02 347 /* SD command response types. */ 348 #define RTSX_SD_RSP_TYPE_R0 0x04 349 #define RTSX_SD_RSP_TYPE_R1 0x01 350 #define RTSX_SD_RSP_TYPE_R1B 0x09 351 #define RTSX_SD_RSP_TYPE_R2 0x02 352 #define RTSX_SD_RSP_TYPE_R3 0x05 353 #define RTSX_SD_RSP_TYPE_R4 0x05 354 #define RTSX_SD_RSP_TYPE_R5 0x01 355 #define RTSX_SD_RSP_TYPE_R6 0x01 356 #define RTSX_SD_RSP_TYPE_R7 0x01 357 358 #define RTSX_SD_CFG3 0xFDA2 359 #define RTSX_SD30_CLK_END_EN 0x10 360 #define RTSX_SD_RSP_80CLK_TIMEOUT_EN 0x01 361 362 #define RTSX_SD_STAT1 0xFDA3 363 #define RTSX_SD_CRC7_ERR 0x80 364 #define RTSX_SD_CRC16_ERR 0x40 365 #define RTSX_SD_CRC_WRITE_ERR 0x20 366 #define RTSX_SD_CRC_WRITE_ERR_MASK 0x1C 367 #define RTSX_GET_CRC_TIME_OUT 0x02 368 #define RTSX_SD_TUNING_COMPARE_ERR 0x01 369 370 #define RTSX_SD_STAT2 0xFDA4 371 #define RTSX_SD_RSP_80CLK_TIMEOUT 0x01 372 373 #define RTSX_SD_CRC_ERR (RTSX_SD_CRC7_ERR|RTSX_SD_CRC16_ERR|RTSX_SD_CRC_WRITE_ERR) 374 375 /* SD bus status register. */ 376 #define RTSX_SD_BUS_STAT 0xFDA5 377 #define RTSX_SD_CLK_TOGGLE_EN 0x80 378 #define RTSX_SD_CLK_FORCE_STOP 0x40 379 #define RTSX_SD_DAT3_STATUS 0x10 380 #define RTSX_SD_DAT2_STATUS 0x08 381 #define RTSX_SD_DAT1_STATUS 0x04 382 #define RTSX_SD_DAT0_STATUS 0x02 383 #define RTSX_SD_CMD_STATUS 0x01 384 385 #define RTSX_SD_PAD_CTL 0xFDA6 386 #define RTSX_SD_IO_USING_1V8 0x80 387 388 /* Sample point control register. */ 389 #define RTSX_SD_SAMPLE_POINT_CTL 0xFDA7 390 #define RTSX_DDR_FIX_RX_DAT 0x00 391 #define RTSX_DDR_VAR_RX_DAT 0x80 392 #define RTSX_DDR_FIX_RX_DAT_EDGE 0x00 393 #define RTSX_DDR_FIX_RX_DAT_14_DELAY 0x40 394 #define RTSX_DDR_FIX_RX_CMD 0x00 395 #define RTSX_DDR_VAR_RX_CMD 0x20 396 #define RTSX_DDR_FIX_RX_CMD_POS_EDGE 0x00 397 #define RTSX_DDR_FIX_RX_CMD_14_DELAY 0x10 398 #define RTSX_SD20_RX_POS_EDGE 0x00 399 #define RTSX_SD20_RX_14_DELAY 0x08 400 #define RTSX_SD20_RX_SEL_MASK 0x08 401 402 #define RTSX_SD_PUSH_POINT_CTL 0xFDA8 403 #define RTSX_SD20_TX_NEG_EDGE 0x00 404 #define RTSX_SD20_TX_SEL_MASK 0x10 405 #define RTSX_SD20_TX_14_AHEAD 0x10 406 407 #define RTSX_SD_CMD0 0xFDA9 408 #define RTSX_SD_CMD_START 0x40 409 #define RTSX_SD_CMD1 0xFDAA 410 #define RTSX_SD_CMD2 0xFDAB 411 #define RTSX_SD_CMD3 0xFDAC 412 #define RTSX_SD_CMD4 0xFDAD 413 414 #define RTSX_SD_CMD5 0xFDAE 415 #define RTSX_SD_BYTE_CNT_L 0xFDAF 416 #define RTSX_SD_BYTE_CNT_H 0xFDB0 417 #define RTSX_SD_BLOCK_CNT_L 0xFDB1 418 #define RTSX_SD_BLOCK_CNT_H 0xFDB2 419 420 /* 421 * Transfer modes. 422 */ 423 #define RTSX_SD_TRANSFER 0xFDB3 424 425 /* Write one or two bytes from SD_CMD2 and SD_CMD3 to the card. */ 426 #define RTSX_TM_NORMAL_WRITE 0x00 427 428 /* Write (SD_BYTE_CNT * SD_BLOCK_COUNTS) bytes from ring buffer to card. */ 429 #define RTSX_TM_AUTO_WRITE3 0x01 430 431 /* Like AUTO_WRITE3, plus automatically send CMD 12 when done. 432 * The response to CMD 12 is written to SD_CMD{0,1,2,3,4}. */ 433 #define RTSX_TM_AUTO_WRITE4 0x02 434 435 /* Read (SD_BYTE_CNT * SD_BLOCK_CNT) bytes from card into ring buffer. */ 436 #define RTSX_TM_AUTO_READ3 0x05 437 438 /* Like AUTO_READ3, plus automatically send CMD 12 when done. 439 * The response to CMD 12 is written to SD_CMD{0,1,2,3,4}. */ 440 #define RTSX_TM_AUTO_READ4 0x06 441 442 /* Send an SD command described in SD_CMD{0,1,2,3,4} to the card and put 443 * the response into SD_CMD{0,1,2,3,4}. Long responses (17 byte) are put 444 * into ping-pong buffer 2 instead. */ 445 #define RTSX_TM_CMD_RSP 0x08 446 447 /* Send write command, get response from the card, write data from ring 448 * buffer to card, and send CMD 12 when done. 449 * The response to CMD 12 is written to SD_CMD{0,1,2,3,4}. */ 450 #define RTSX_TM_AUTO_WRITE1 0x09 451 452 /* Like AUTO_WRITE1 except no CMD 12 is sent. */ 453 #define RTSX_TM_AUTO_WRITE2 0x0A 454 455 /* Send read command, read up to 512 bytes (SD_BYTE_CNT * SD_BLOCK_CNT) 456 * from the card into the ring buffer or ping-pong buffer 2. */ 457 #define RTSX_TM_NORMAL_READ 0x0C 458 459 /* Same as WRITE1, except data is read from the card to the ring buffer. */ 460 #define RTSX_TM_AUTO_READ1 0x0D 461 462 /* Same as WRITE2, except data is read from the card to the ring buffer. */ 463 #define RTSX_TM_AUTO_READ2 0x0E 464 465 /* Send CMD 19 and receive response and tuning pattern from card and 466 * report the result. */ 467 #define RTSX_TM_AUTO_TUNING 0x0F 468 469 /* transfer control */ 470 #define RTSX_SD_TRANSFER_START 0x80 471 #define RTSX_SD_TRANSFER_END 0x40 472 #define RTSX_SD_STAT_IDLE 0x20 473 #define RTSX_SD_TRANSFER_ERR 0x10 474 475 #define RTSX_SD_CMD_STATE 0xFDB5 476 #define RTSX_SD_CMD_IDLE 0x80 477 478 #define RTSX_SD_DATA_STATE 0xFDB6 479 #define RTSX_SD_DATA_IDLE 0x80 480 481 #define RTSX_REG_SD_STOP_SDCLK_CFG 0xFDB8 482 #define RTSX_SD30_CLK_STOP_CFG_EN 0x04 483 #define RTSX_SD30_CLK_STOP_CFG0 0x01 484 #define RTSX_SD30_CLK_STOP_CFG1 0x02 485 486 #define RTSX_REG_PRE_RW_MODE 0xFD70 487 #define RTSX_EN_INFINITE_MODE 0x01 488 489 /* ping-pong buffer 2 */ 490 #define RTSX_PPBUF_BASE2 0xFA00 491 #define RTSX_PPBUF_SIZE 256 492 493 #define RTSX_SUPPORTED_VOLTAGE (MMC_OCR_300_310|MMC_OCR_310_320|\ 494 MMC_OCR_320_330|MMC_OCR_330_340) 495 496 #define RTSX_CFG_PCI 0x1C 497 #define RTSX_CFG_ASIC 0x10 498 499 #define RTSX_IRQEN0 0xFE20 500 #define RTSX_LINK_DOWN_INT_EN 0x10 501 #define RTSX_LINK_READY_INT_EN 0x20 502 #define RTSX_SUSPEND_INT_EN 0x40 503 #define RTSX_DMA_DONE_INT_EN 0x80 504 505 #define RTSX_IRQSTAT0 0xFE21 506 #define RTSX_LINK_DOWN_INT 0x10 507 #define RTSX_LINK_READY_INT 0x20 508 #define RTSX_SUSPEND_INT 0x40 509 #define RTSX_DMA_DONE_INT 0x80 510 511 #define RTSX_DMATC0 0xFE28 512 #define RTSX_DMATC1 0xFE29 513 #define RTSX_DMATC2 0xFE2A 514 #define RTSX_DMATC3 0xFE2B 515 516 #define RTSX_DMACTL 0xFE2C 517 #define RTSX_DMA_EN 0x01 518 #define RTSX_DMA_DIR 0x02 519 #define RTSX_DMA_DIR_TO_CARD 0x00 520 #define RTSX_DMA_DIR_FROM_CARD 0x02 521 #define RTSX_DMA_BUSY 0x04 522 #define RTSX_DMA_RST 0x80 523 #define RTSX_DMA_128 (0 << 4) 524 #define RTSX_DMA_256 (1 << 4) 525 #define RTSX_DMA_512 (2 << 4) 526 #define RTSX_DMA_1024 (3 << 4) 527 #define RTSX_DMA_PACK_SIZE_MASK 0x30 528 529 #define RTSX_RBCTL 0xFE34 530 #define RTSX_RB_FLUSH 0x80 531 #define RTSX_U_AUTO_DMA_EN_MASK 0x20 532 #define RTSX_U_AUTO_DMA_DISABLE 0x00 533 534 #define RTSX_CFGADDR0 0xFE35 535 #define RTSX_CFGADDR1 0xFE36 536 #define RTSX_CFGDATA0 0xFE37 537 #define RTSX_CFGDATA1 0xFE38 538 #define RTSX_CFGDATA2 0xFE39 539 #define RTSX_CFGDATA3 0xFE3A 540 #define RTSX_CFGRWCTL 0xFE3B 541 #define RTSX_CFG_WRITE_DATA0 0x01 542 #define RTSX_CFG_WRITE_DATA1 0x02 543 #define RTSX_CFG_WRITE_DATA2 0x04 544 #define RTSX_CFG_WRITE_DATA3 0x08 545 #define RTSX_CFG_BUSY 0x80 546 547 #define RTSX_LTR_CTL 0xFE4A 548 549 #define RTSX_OBFF_CFG 0xFE4C 550 #define RTSX_OBFF_EN_MASK 0x03 551 #define RTSX_OBFF_DISABLE 0x00 552 #define RTSX_OBFF_ENABLE 0x03 553 554 #define RTSX_SDIOCFG_REG 0x724 555 #define RTSX_SDIOCFG_NO_BYPASS_SDIO 0x02 556 #define RTSX_SDIOCFG_HAVE_SDIO 0x04 557 #define RTSX_SDIOCFG_SINGLE_LUN 0x08 558 #define RTSX_SDIOCFG_SDIO_ONLY 0x80 559 560 #define RTSX_HOST_SLEEP_STATE 0xFE60 561 #define RTSX_HOST_ENTER_S1 0x01 562 #define RTSX_HOST_ENTER_S3 0x02 563 564 #define RTSX_SDIO_CFG 0xFE70 565 #define RTSX_SDIO_BUS_AUTO_SWITCH 0x10 566 567 #define RTSX_NFTS_TX_CTRL 0xFE72 568 #define RTSX_INT_READ_CLR 0x02 569 570 #define RTSX_PWR_GATE_CTRL 0xFE75 571 #define RTSX_PWR_GATE_EN 0x01 572 #define RTSX_LDO3318_PWR_MASK 0x06 573 #define RTSX_LDO3318_ON 0x00 574 #define RTSX_LDO3318_SUSPEND 0x04 575 #define RTSX_LDO3318_OFF 0x06 576 #define RTSX_LDO3318_VCC1 0x02 577 #define RTSX_LDO3318_VCC2 0x04 578 #define RTSX_PWD_SUSPEND_EN 0xFE76 579 #define RTSX_LDO_PWR_SEL 0xFE78 580 #define RTSX_LDO_PWR_SEL_3V3 0x01 581 #define RTSX_LDO_PWR_SEL_DV33 0x03 582 583 #define RTSX_PHY_RWCTL 0xFE3C 584 #define RTSX_PHY_READ 0x00 585 #define RTSX_PHY_WRITE 0x01 586 #define RTSX_PHY_BUSY 0x80 587 #define RTSX_PHY_DATA0 0xFE3D 588 #define RTSX_PHY_DATA1 0xFE3E 589 #define RTSX_PHY_ADDR 0xFE3F 590 591 #define RTSX_PHY_PCR 0x00 592 #define RTSX_PHY_PCR_FORCE_CODE 0xB000 593 #define RTSX_PHY_PCR_OOBS_CALI_50 0x0800 594 #define RTSX_PHY_PCR_OOBS_VCM_08 0x0200 595 #define RTSX_PHY_PCR_OOBS_SEN_90 0x0040 596 #define RTSX_PHY_PCR_RSSI_EN 0x0002 597 #define RTSX_PHY_PCR_RX10K 0x0001 598 599 #define RTSX_PHY_RCR1 0x02 600 #define RTSX_PHY_RCR1_ADP_TIME_4 0x0400 601 #define RTSX_PHY_RCR1_VCO_COARSE 0x001F 602 #define RTSX_PHY_RCR1_INIT_27S 0x0A1F 603 604 #define RTSX_PHY_RCR2 0x03 605 #define RTSX_PHY_RCR2_EMPHASE_EN 0x8000 606 #define RTSX_PHY_RCR2_NADJR 0x4000 607 #define RTSX_PHY_RCR2_CDR_SR_2 0x0100 608 #define RTSX_PHY_RCR2_FREQSEL_12 0x0040 609 #define RTSX_PHY_RCR2_CDR_SC_12P 0x0010 610 #define RTSX_PHY_RCR2_CALIB_LATE 0x0002 611 #define RTSX_PHY_RCR2_INIT_27S 0xC152 612 613 #define RTSX__PHY_ANA03 0x03 614 #define RTSX__PHY_ANA03_TIMER_MAX 0x2700 615 #define RTSX__PHY_ANA03_OOBS_DEB_EN 0x0040 616 #define RTSX__PHY_CMU_DEBUG_EN 0x0008 617 618 #define RTSX_PHY_RDR 0x05 619 #define RTSX_PHY_RDR_RXDSEL_1_9 0x4000 620 #define RTSX_PHY_SSC_AUTO_PWD 0x0600 621 622 #define RTSX_PHY_TUNE 0x08 623 #define RTSX_PHY_TUNE_TUNEREF_1_0 0x4000 624 #define RTSX_PHY_TUNE_VBGSEL_1252 0x0C00 625 #define RTSX_PHY_TUNE_SDBUS_33 0x0200 626 #define RTSX_PHY_TUNE_TUNED18 0x01C0 627 #define RTSX_PHY_TUNE_TUNED12 0X0020 628 #define RTSX_PHY_TUNE_TUNEA12 0x0004 629 #define RTSX_PHY_TUNE_VOLTAGE_MASK 0xFC3F 630 #define RTSX_PHY_TUNE_VOLTAGE_3V3 0x03C0 631 #define RTSX_PHY_TUNE_D18_1V8 0x0100 632 #define RTSX_PHY_TUNE_D18_1V7 0x0080 633 634 #define RTSX_PHY_BPCR 0x0A 635 #define RTSX_PHY_BPCR_IBRXSEL 0x0400 636 #define RTSX_PHY_BPCR_IBTXSEL 0x0100 637 #define RTSX_PHY_BPCR_IB_FILTER 0x0080 638 #define RTSX_PHY_BPCR_CMIRROR_EN 0x0040 639 640 #define RTSX_PHY_REV 0x19 641 #define RTSX_PHY_REV_RESV 0xE000 642 #define RTSX_PHY_REV_RXIDLE_LATCHED 0x1000 643 #define RTSX_PHY_REV_P1_EN 0x0800 644 #define RTSX_PHY_REV_RXIDLE_EN 0x0400 645 #define RTSX_PHY_REV_CLKREQ_TX_EN 0x0200 646 #define RTSX_PHY_REV_CLKREQ_RX_EN 0x0100 647 #define RTSX_PHY_REV_CLKREQ_DT_1_0 0x0040 648 #define RTSX_PHY_REV_STOP_CLKRD 0x0020 649 #define RTSX_PHY_REV_RX_PWST 0x0008 650 #define RTSX_PHY_REV_STOP_CLKWR 0x0004 651 652 653 #define RTSX__PHY_REV0 0x19 654 #define RTSX__PHY_REV0_FILTER_OUT 0x3800 655 #define RTSX__PHY_REV0_CDR_BYPASS_PFD 0x0100 656 #define RTSX__PHY_REV0_CDR_RX_IDLE_BYPASS 0x0002 657 658 #define RTSX_PHY_FLD0 0x1A 659 #define RTSX_PHY_FLD0_INIT_27S 0x2546 660 661 #define RTSX_PHY_FLD3 0x1D 662 #define RTSX_PHY_FLD3_TIMER_4 0x0800 663 #define RTSX_PHY_FLD3_TIMER_6 0x0020 664 #define RTSX_PHY_FLD3_RXDELINK 0x0004 665 #define RTSX_PHY_FLD3_INIT_27S 0x0004 666 667 #define RTSX__PHY_FLD0 0x1D 668 #define RTSX__PHY_FLD0_CLK_REQ_20C 0x8000 669 #define RTSX__PHY_FLD0_RX_IDLE_EN 0x1000 670 #define RTSX__PHY_FLD0_BIT_ERR_RSTN 0x0800 671 #define RTSX__PHY_FLD0_BER_COUNT 0x01E0 672 #define RTSX__PHY_FLD0_BER_TIMER 0x001E 673 #define RTSX__PHY_FLD0_CHECK_EN 0x0001 674 675 #define RTSX_PHY_FLD4 0x1E 676 #define RTSX_PHY_FLD4_FLDEN_SEL 0x4000 677 #define RTSX_PHY_FLD4_REQ_REF 0x2000 678 #define RTSX_PHY_FLD4_RXAMP_OFF 0x1000 679 #define RTSX_PHY_FLD4_REQ_ADDA 0x0800 680 #define RTSX_PHY_FLD4_BER_COUNT 0x00E0 681 #define RTSX_PHY_FLD4_BER_TIMER 0x000A 682 #define RTSX_PHY_FLD4_BER_CHK_EN 0x0001 683 #define RTSX_PHY_FLD4_INIT_27S 0x5C7F 684 685 #define RTSX_CARD_AUTO_BLINK 0xFD56 686 #define RTSX_LED_BLINK_EN 0x08 687 #define RTSX_LED_BLINK_SPEED 0x05 688 689 #define RTSX_PCLK_CTL 0xFE55 690 #define RTSX_PCLK_MODE_SEL 0x20 691 692 #define RTSX_PME_FORCE_CTL 0xFE56 693 694 #define RTSX_ASPM_FORCE_CTL 0xFE57 695 #define RTSX_ASPM_FORCE_MASK 0x3F 696 #define RTSX_FORCE_ASPM_NO_ASPM 0x00 697 698 #define RTSX_PM_CLK_FORCE_CTL 0xFE58 699 #define RTSX_CLK_PM_EN 0x01 700 701 #define RTSX_FUNC_FORCE_CTL 0xFE59 702 #define RTSX_FUNC_FORCE_UPME_XMT_DBG 0x02 703 704 #define RTSX_CHANGE_LINK_STATE 0xFE5B 705 #define RTSX_CD_RST_CORE_EN 0x01 706 #define RTSX_FORCE_RST_CORE_EN 0x02 707 #define RTSX_NON_STICKY_RST_N_DBG 0x08 708 #define RTSX_MAC_PHY_RST_N_DBG 0x10 709 710 #define RTSX_PERST_GLITCH_WIDTH 0xFE5C 711 712 #define RTSX_EFUSE_CONTENT 0xFE5F 713 714 #define RTSX_PM_EVENT_DEBUG 0xFE71 715 #define RTSX_PME_DEBUG_0 0x08 716 717 #define RTSX_L1SUB_CONFIG1 0xFE8D 718 #define RTSX_AUX_CLK_ACTIVE_SEL_MASK 0x01 719 #define RTSX_MAC_CKSW_DONE 0x00 720 721 #define RTSX_L1SUB_CONFIG2 0xFE8E 722 #define RTSX_L1SUB_AUTO_CFG 0x02 723 724 #define RTSX_L1SUB_CONFIG3 0xFE8F 725 726 #define RTSX_DUMMY_REG 0xFE90 727 728 #define RTSX_REG_VREF 0xFE97 729 #define RTSX_PWD_SUSPND_EN 0x10 730 731 #define RTSX_RTS5260_DMA_RST_CTL_0 0xFEBF 732 #define RTSX_RTS5260_DMA_RST 0x80 733 #define RTSX_RTS5260_ADMA3_RST 0x40 734 735 #define RTSX_PETXCFG 0xFF03 /* was 0xFE49 in OpenBSD */ 736 #define RTSX_FORCE_CLKREQ_DELINK_MASK 0x80 737 #define RTSX_FORCE_CLKREQ_LOW 0x80 738 739 #define RTSX_RREF_CFG 0xFF6C 740 #define RTSX_RREF_VBGSEL_MASK 0x38 741 #define RTSX_RREF_VBGSEL_1V25 0x28 742 743 #define RTSX_PM_CTRL3 0xFF46 744 #define RTSX_RTS522A_PM_CTRL3 0xFF7E 745 #define RTSX_D3_DELINK_MODE_EN 0x10 746 #define RTSX_PM_WAKE_EN 0x01 747 748 #define RTSX_OOBS_CONFIG 0xFF6E 749 #define RTSX_OOBS_AUTOK_DIS 0x80 750 #define RTSX_OOBS_VAL_MASK 0x1F 751 752 #define RTSX_LDO_DV18_CFG 0xFF70 753 #define RTSX_DV331812_MASK 0x70 754 #define RTSX_DV331812_33 0x70 755 756 #define RTSX_LDO_CONFIG2 0xFF71 757 #define RTSX_LDO_D3318_MASK 0x07 758 #define RTSX_LDO_D3318_33V 0x07 759 #define RTSX_LDO_D3318_18V 0x02 760 #define RTSX_DV331812_VDD1 0x04 761 #define RTSX_DV331812_POWERON 0x08 762 #define RTSX_DV331812_POWEROFF 0x00 763 764 #define RTSX_LDO_VCC_CFG0 0xFF72 765 #define RTSX_LDO_VCC_LMTVTH_MASK 0x30 766 #define RTSX_LDO_VCC_LMTVTH_2A 0x10 767 #define RTSX_RTS5260_DVCC_TUNE_MASK 0x70 768 #define RTSX_RTS5260_DVCC_33 0x70 769 770 #define RTSX_LDO_VCC_CFG1 0xFF73 771 #define RTSX_LDO_VCC_REF_TUNE_MASK 0x30 772 #define RTSX_LDO_VCC_REF_1V2 0x20 773 #define RTSX_LDO_VCC_TUNE_MASK 0x07 774 #define RTSX_LDO_VCC_1V8 0x04 775 #define RTSX_LDO_VCC_3V3 0x07 776 #define RTSX_LDO_VCC_LMT_EN 0x08 777 /*RTS5260*/ 778 #define RTSX_LDO_POW_SDVDD1_MASK 0x08 779 #define RTSX_LDO_POW_SDVDD1_ON 0x08 780 #define RTSX_LDO_POW_SDVDD1_OFF 0x00 781 782 #define RTSX_RTS5260_DVCC_CTRL 0xFF73 783 #define RTSX_RTS5260_DVCC_OCP_EN (0x01 << 7) 784 #define RTSX_RTS5260_DVCC_OCP_THD_MASK (0x07 << 4) 785 #define RTSX_RTS5260_DVCC_POWERON (0x01 << 3) 786 #define RTSX_RTS5260_DVCC_OCP_CL_EN (0x01 << 2) 787 788 #define RTSX_LDO_VIO_CFG 0xFF75 789 #define RTSX_LDO_VIO_TUNE_MASK 0x07 790 #define RTSX_LDO_VIO_1V7 0x03 791 792 #define RTSX_LDO_DV12S_CFG 0xFF76 793 #define RTSX_LDO_D12_TUNE_MASK 0x07 794 #define RTSX_LDO_D12_TUNE_DF 0x04 795 796 #define RTSX_LDO_AV12S_CFG 0xFF77 797 #define RTSX_LDO_AV12S_TUNE_MASK 0x07 798 #define RTSX_LDO_AV12S_TUNE_DF 0x04 799 800 #define RTSX_SG_INT 0x04 801 #define RTSX_SG_END 0x02 802 #define RTSX_SG_VALID 0x01 803 804 #define RTSX_SG_NO_OP 0x00 805 #define RTSX_SG_TRANS_DATA (0x02 << 4) 806 #define RTSX_SG_LINK_DESC (0x03 << 4) 807 808 #define RTSX_IC_VERSION_A 0x00 809 #define RTSX_IC_VERSION_B 0x01 810 #define RTSX_IC_VERSION_C 0x02 811 #define RTSX_IC_VERSION_D 0x03 812 813 #define RTSX_RTS5260_AUTOLOAD_CFG4 0xFF7F 814 #define RTSX_RTS5260_MIMO_DISABLE 0x8A 815 816 #define RTSX_PCR_SETTING_REG1 0x724 817 #define RTSX_PCR_SETTING_REG2 0x814 818 #define RTSX_PCR_SETTING_REG3 0x747 819 820 #define RTSX_RX_PHASE_MAX 32 821 #define RTSX_RX_TUNING_CNT 3 822 #endif 823