1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 5 * Copyright (c) 2012 Stefan Sperling <stsp@openbsd.org> 6 * Copyright (c) 2020 Henri Hennebert <hlh@restart.be> 7 * Copyright (c) 2020 Gary Jennejohn <gj@freebsd.org> 8 * Copyright (c) 2020 Jesper Schmitz Mouridsen <jsm@FreeBSD.org> 9 * All rights reserved. 10 * 11 * Patch from: 12 * - Lutz Bichler <Lutz.Bichler@gmail.com> 13 * 14 * Base on OpenBSD /sys/dev/pci/rtsx_pci.c & /dev/ic/rtsx.c 15 * on Linux /drivers/mmc/host/rtsx_pci_sdmmc.c, 16 * /include/linux/rtsx_pci.h & 17 * /drivers/misc/cardreader/rtsx_pcr.c 18 * on NetBSD /sys/dev/ic/rtsx.c 19 * 20 * Permission to use, copy, modify, and distribute this software for any 21 * purpose with or without fee is hereby granted, provided that the above 22 * copyright notice and this permission notice appear in all copies. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 __FBSDID("$FreeBSD$"); 39 40 #include <sys/param.h> 41 #include <sys/module.h> 42 #include <sys/systm.h> /* For FreeBSD 11 */ 43 #include <sys/types.h> /* For FreeBSD 11 */ 44 #include <sys/errno.h> 45 #include <sys/kernel.h> 46 #include <sys/bus.h> 47 #include <sys/endian.h> 48 #include <machine/bus.h> 49 #include <sys/mutex.h> 50 #include <sys/malloc.h> 51 #include <sys/rman.h> 52 #include <sys/queue.h> 53 #include <sys/taskqueue.h> 54 #include <sys/sysctl.h> 55 #include <dev/pci/pcivar.h> 56 #include <dev/pci/pcireg.h> 57 #include <dev/mmc/bridge.h> 58 #include <dev/mmc/mmcreg.h> 59 #include <dev/mmc/mmcbrvar.h> 60 #include <machine/_inttypes.h> 61 62 #include "opt_mmccam.h" 63 64 #ifdef MMCCAM 65 #include <cam/cam.h> 66 #include <cam/cam_ccb.h> 67 #include <cam/cam_debug.h> 68 #include <cam/cam_sim.h> 69 #include <cam/cam_xpt_sim.h> 70 #include <cam/mmc/mmc_sim.h> 71 #include "mmc_sim_if.h" 72 #endif /* MMCCAM */ 73 74 #include "rtsxreg.h" 75 76 /* The softc holds our per-instance data. */ 77 struct rtsx_softc { 78 struct mtx rtsx_mtx; /* device mutex */ 79 device_t rtsx_dev; /* device */ 80 uint16_t rtsx_flags; /* device flags */ 81 uint16_t rtsx_device_id; /* device ID */ 82 device_t rtsx_mmc_dev; /* device of mmc bus */ 83 uint32_t rtsx_intr_enabled; /* enabled interrupts */ 84 uint32_t rtsx_intr_status; /* soft interrupt status */ 85 int rtsx_irq_res_id; /* bus IRQ resource id */ 86 struct resource *rtsx_irq_res; /* bus IRQ resource */ 87 void *rtsx_irq_cookie; /* bus IRQ resource cookie */ 88 struct callout rtsx_timeout_callout; /* callout for timeout */ 89 int rtsx_timeout_cmd; /* interrupt timeout for setup commands */ 90 int rtsx_timeout_io; /* interrupt timeout for I/O commands */ 91 void (*rtsx_intr_trans_ok)(struct rtsx_softc *sc); 92 /* function to call if transfer succeed */ 93 void (*rtsx_intr_trans_ko)(struct rtsx_softc *sc); 94 /* function to call if transfer fail */ 95 96 struct timeout_task 97 rtsx_card_insert_task; /* card insert delayed task */ 98 struct task rtsx_card_remove_task; /* card remove task */ 99 100 int rtsx_mem_res_id; /* bus memory resource id */ 101 struct resource *rtsx_mem_res; /* bus memory resource */ 102 bus_space_tag_t rtsx_mem_btag; /* host register set tag */ 103 bus_space_handle_t rtsx_mem_bhandle; /* host register set handle */ 104 105 bus_dma_tag_t rtsx_cmd_dma_tag; /* DMA tag for command transfer */ 106 bus_dmamap_t rtsx_cmd_dmamap; /* DMA map for command transfer */ 107 void *rtsx_cmd_dmamem; /* DMA mem for command transfer */ 108 bus_addr_t rtsx_cmd_buffer; /* device visible address of the DMA segment */ 109 int rtsx_cmd_index; /* index in rtsx_cmd_buffer */ 110 111 bus_dma_tag_t rtsx_data_dma_tag; /* DMA tag for data transfer */ 112 bus_dmamap_t rtsx_data_dmamap; /* DMA map for data transfer */ 113 void *rtsx_data_dmamem; /* DMA mem for data transfer */ 114 bus_addr_t rtsx_data_buffer; /* device visible address of the DMA segment */ 115 116 #ifdef MMCCAM 117 union ccb *rtsx_ccb; /* CAM control block */ 118 struct mmc_sim rtsx_mmc_sim; /* CAM generic sim */ 119 struct mmc_request rtsx_cam_req; /* CAM MMC request */ 120 #endif /* MMCCAM */ 121 122 struct mmc_request *rtsx_req; /* MMC request */ 123 struct mmc_host rtsx_host; /* host parameters */ 124 int rtsx_pcie_cap; /* PCIe capability offset */ 125 int8_t rtsx_bus_busy; /* bus busy status */ 126 int8_t rtsx_ios_bus_width; /* current host.ios.bus_width */ 127 int32_t rtsx_ios_clock; /* current host.ios.clock */ 128 int8_t rtsx_ios_power_mode; /* current host.ios.power mode */ 129 int8_t rtsx_ios_timing; /* current host.ios.timing */ 130 int8_t rtsx_ios_vccq; /* current host.ios.vccq */ 131 uint8_t rtsx_read_only; /* card read only status */ 132 uint8_t rtsx_inversion; /* inversion of card detection and read only status */ 133 uint8_t rtsx_force_timing; /* force bus_timing_uhs_sdr50 */ 134 uint8_t rtsx_debug_mask; /* debugging mask */ 135 #define RTSX_DEBUG_BASIC 0x01 /* debug basic flow */ 136 #define RTSX_TRACE_SD_CMD 0x02 /* trace SD commands */ 137 #define RTSX_DEBUG_TUNING 0x04 /* debug tuning */ 138 #ifdef MMCCAM 139 uint8_t rtsx_cam_status; /* CAM status - 1 if card in use */ 140 #endif /* MMCCAM */ 141 uint64_t rtsx_read_count; /* count of read operations */ 142 uint64_t rtsx_write_count; /* count of write operations */ 143 bool rtsx_discovery_mode; /* are we in discovery mode? */ 144 bool rtsx_tuning_mode; /* are we tuning */ 145 bool rtsx_double_clk; /* double clock freqency */ 146 bool rtsx_vpclk; /* voltage at Pulse-width Modulation(PWM) clock? */ 147 uint8_t rtsx_ssc_depth; /* Spread spectrum clocking depth */ 148 uint8_t rtsx_card_drive_sel; /* value for RTSX_CARD_DRIVE_SEL */ 149 uint8_t rtsx_sd30_drive_sel_3v3;/* value for RTSX_SD30_DRIVE_SEL */ 150 }; 151 152 /* rtsx_flags values */ 153 #define RTSX_F_DEFAULT 0x0000 154 #define RTSX_F_CARD_PRESENT 0x0001 155 #define RTSX_F_SDIO_SUPPORT 0x0002 156 #define RTSX_F_VERSION_A 0x0004 157 #define RTSX_F_VERSION_B 0x0008 158 #define RTSX_F_VERSION_C 0x0010 159 #define RTSX_F_VERSION_D 0x0020 160 #define RTSX_F_8411B_QFN48 0x0040 161 #define RTSX_F_REVERSE_SOCKET 0x0080 162 163 #define RTSX_REALTEK 0x10ec 164 #define RTSX_RTS5209 0x5209 165 #define RTSX_RTS5227 0x5227 166 #define RTSX_RTS5229 0x5229 167 #define RTSX_RTS522A 0x522a 168 #define RTSX_RTS525A 0x525a 169 #define RTSX_RTS5249 0x5249 170 #define RTSX_RTS5260 0x5260 171 #define RTSX_RTL8402 0x5286 172 #define RTSX_RTL8411 0x5289 173 #define RTSX_RTL8411B 0x5287 174 175 #define RTSX_VERSION "2.1g" 176 177 static const struct rtsx_pciids { 178 uint16_t device_id; 179 const char *desc; 180 } rtsx_ids[] = { 181 { RTSX_RTS5209, RTSX_VERSION " Realtek RTS5209 PCIe SD Card Reader" }, 182 { RTSX_RTS5227, RTSX_VERSION " Realtek RTS5227 PCIe SD Card Reader" }, 183 { RTSX_RTS5229, RTSX_VERSION " Realtek RTS5229 PCIe SD Card Reader" }, 184 { RTSX_RTS522A, RTSX_VERSION " Realtek RTS522A PCIe SD Card Reader" }, 185 { RTSX_RTS525A, RTSX_VERSION " Realtek RTS525A PCIe SD Card Reader" }, 186 { RTSX_RTS5249, RTSX_VERSION " Realtek RTS5249 PCIe SD Card Reader" }, 187 { RTSX_RTS5260, RTSX_VERSION " Realtek RTS5260 PCIe SD Card Reader" }, 188 { RTSX_RTL8402, RTSX_VERSION " Realtek RTL8402 PCIe SD Card Reader" }, 189 { RTSX_RTL8411, RTSX_VERSION " Realtek RTL8411 PCIe SD Card Reader" }, 190 { RTSX_RTL8411B, RTSX_VERSION " Realtek RTL8411B PCIe SD Card Reader" }, 191 }; 192 193 /* See `kenv | grep smbios.system` */ 194 static const struct rtsx_inversion_model { 195 char *maker; 196 char *family; 197 char *product; 198 } rtsx_inversion_models[] = { 199 { "LENOVO", "ThinkPad T470p", "20J7S0PM00"}, 200 { "LENOVO", "ThinkPad X13 Gen 1", "20UF000QRT"}, 201 { NULL, NULL, NULL} 202 }; 203 204 static int rtsx_dma_alloc(struct rtsx_softc *sc); 205 static void rtsx_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 206 static void rtsx_dma_free(struct rtsx_softc *sc); 207 static void rtsx_intr(void *arg); 208 static void rtsx_handle_card_present(struct rtsx_softc *sc); 209 static void rtsx_card_task(void *arg, int pending __unused); 210 static bool rtsx_is_card_present(struct rtsx_softc *sc); 211 static int rtsx_init(struct rtsx_softc *sc); 212 static int rtsx_map_sd_drive(int index); 213 static int rtsx_rts5227_fill_driving(struct rtsx_softc *sc); 214 static int rtsx_rts5249_fill_driving(struct rtsx_softc *sc); 215 static int rtsx_rts5260_fill_driving(struct rtsx_softc *sc); 216 static int rtsx_read(struct rtsx_softc *, uint16_t, uint8_t *); 217 static int rtsx_read_cfg(struct rtsx_softc *sc, uint8_t func, uint16_t addr, uint32_t *val); 218 static int rtsx_write(struct rtsx_softc *sc, uint16_t addr, uint8_t mask, uint8_t val); 219 static int rtsx_read_phy(struct rtsx_softc *sc, uint8_t addr, uint16_t *val); 220 static int rtsx_write_phy(struct rtsx_softc *sc, uint8_t addr, uint16_t val); 221 static int rtsx_bus_power_off(struct rtsx_softc *sc); 222 static int rtsx_bus_power_on(struct rtsx_softc *sc); 223 static int rtsx_set_bus_width(struct rtsx_softc *sc, enum mmc_bus_width width); 224 static int rtsx_set_sd_timing(struct rtsx_softc *sc, enum mmc_bus_timing timing); 225 static int rtsx_set_sd_clock(struct rtsx_softc *sc, uint32_t freq); 226 static int rtsx_stop_sd_clock(struct rtsx_softc *sc); 227 static int rtsx_switch_sd_clock(struct rtsx_softc *sc, uint8_t clk, uint8_t n, uint8_t div, uint8_t mcu); 228 #ifndef MMCCAM 229 static void rtsx_sd_change_tx_phase(struct rtsx_softc *sc, uint8_t sample_point); 230 static void rtsx_sd_change_rx_phase(struct rtsx_softc *sc, uint8_t sample_point); 231 static void rtsx_sd_tuning_rx_phase(struct rtsx_softc *sc, uint32_t *phase_map); 232 static int rtsx_sd_tuning_rx_cmd(struct rtsx_softc *sc, uint8_t sample_point); 233 static int rtsx_sd_tuning_rx_cmd_wait(struct rtsx_softc *sc, struct mmc_command *cmd); 234 static void rtsx_sd_tuning_rx_cmd_wakeup(struct rtsx_softc *sc); 235 static void rtsx_sd_wait_data_idle(struct rtsx_softc *sc); 236 static uint8_t rtsx_sd_search_final_rx_phase(struct rtsx_softc *sc, uint32_t phase_map); 237 static int rtsx_sd_get_rx_phase_len(uint32_t phase_map, int start_bit); 238 #endif /* !MMCCAM */ 239 #if 0 /* For led */ 240 static int rtsx_led_enable(struct rtsx_softc *sc); 241 static int rtsx_led_disable(struct rtsx_softc *sc); 242 #endif /* For led */ 243 static uint8_t rtsx_response_type(uint16_t mmc_rsp); 244 static void rtsx_init_cmd(struct rtsx_softc *sc, struct mmc_command *cmd); 245 static void rtsx_push_cmd(struct rtsx_softc *sc, uint8_t cmd, uint16_t reg, 246 uint8_t mask, uint8_t data); 247 static void rtsx_set_cmd_data_len(struct rtsx_softc *sc, uint16_t block_cnt, uint16_t byte_cnt); 248 static void rtsx_send_cmd(struct rtsx_softc *sc); 249 static void rtsx_ret_resp(struct rtsx_softc *sc); 250 static void rtsx_set_resp(struct rtsx_softc *sc, struct mmc_command *cmd); 251 static void rtsx_stop_cmd(struct rtsx_softc *sc); 252 static void rtsx_clear_error(struct rtsx_softc *sc); 253 static void rtsx_req_done(struct rtsx_softc *sc); 254 static int rtsx_send_req(struct rtsx_softc *sc, struct mmc_command *cmd); 255 static int rtsx_xfer_short(struct rtsx_softc *sc, struct mmc_command *cmd); 256 static void rtsx_ask_ppbuf_part1(struct rtsx_softc *sc); 257 static void rtsx_get_ppbuf_part1(struct rtsx_softc *sc); 258 static void rtsx_get_ppbuf_part2(struct rtsx_softc *sc); 259 static void rtsx_put_ppbuf_part1(struct rtsx_softc *sc); 260 static void rtsx_put_ppbuf_part2(struct rtsx_softc *sc); 261 static void rtsx_write_ppbuf(struct rtsx_softc *sc); 262 static int rtsx_xfer(struct rtsx_softc *sc, struct mmc_command *cmd); 263 static void rtsx_xfer_begin(struct rtsx_softc *sc); 264 static void rtsx_xfer_start(struct rtsx_softc *sc); 265 static void rtsx_xfer_finish(struct rtsx_softc *sc); 266 static void rtsx_timeout(void *arg); 267 268 #ifdef MMCCAM 269 static int rtsx_get_tran_settings(device_t dev, struct ccb_trans_settings_mmc *cts); 270 static int rtsx_set_tran_settings(device_t dev, struct ccb_trans_settings_mmc *cts); 271 static int rtsx_cam_request(device_t dev, union ccb *ccb); 272 #endif /* MMCCAM */ 273 274 static int rtsx_read_ivar(device_t bus, device_t child, int which, uintptr_t *result); 275 static int rtsx_write_ivar(device_t bus, device_t child, int which, uintptr_t value); 276 277 static int rtsx_mmcbr_update_ios(device_t bus, device_t child __unused); 278 static int rtsx_mmcbr_switch_vccq(device_t bus, device_t child __unused); 279 static int rtsx_mmcbr_request(device_t bus, device_t child __unused, struct mmc_request *req); 280 #ifndef MMCCAM 281 static int rtsx_mmcbr_tune(device_t bus, device_t child __unused, bool hs400 __unused); 282 static int rtsx_mmcbr_retune(device_t bus, device_t child __unused, bool reset __unused); 283 static int rtsx_mmcbr_get_ro(device_t bus, device_t child __unused); 284 static int rtsx_mmcbr_acquire_host(device_t bus, device_t child __unused); 285 static int rtsx_mmcbr_release_host(device_t bus, device_t child __unused); 286 #endif /* !MMCCAM */ 287 288 static int rtsx_probe(device_t dev); 289 static int rtsx_attach(device_t dev); 290 static int rtsx_detach(device_t dev); 291 static int rtsx_shutdown(device_t dev); 292 static int rtsx_suspend(device_t dev); 293 static int rtsx_resume(device_t dev); 294 295 #define RTSX_LOCK_INIT(_sc) mtx_init(&(_sc)->rtsx_mtx, \ 296 device_get_nameunit(sc->rtsx_dev), "rtsx", MTX_DEF) 297 #define RTSX_LOCK(_sc) mtx_lock(&(_sc)->rtsx_mtx) 298 #define RTSX_UNLOCK(_sc) mtx_unlock(&(_sc)->rtsx_mtx) 299 #define RTSX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rtsx_mtx) 300 301 #define RTSX_SDCLK_OFF 0 302 #define RTSX_SDCLK_250KHZ 250000 303 #define RTSX_SDCLK_400KHZ 400000 304 #define RTSX_SDCLK_25MHZ 25000000 305 #define RTSX_SDCLK_50MHZ 50000000 306 #define RTSX_SDCLK_100MHZ 100000000 307 #define RTSX_SDCLK_208MHZ 208000000 308 309 #define RTSX_MIN_DIV_N 80 310 #define RTSX_MAX_DIV_N 208 311 312 #define RTSX_MAX_DATA_BLKLEN 512 313 314 #define RTSX_DMA_ALIGN 4 315 #define RTSX_HOSTCMD_MAX 256 316 #define RTSX_DMA_CMD_BIFSIZE (sizeof(uint32_t) * RTSX_HOSTCMD_MAX) 317 #define RTSX_DMA_DATA_BUFSIZE MAXPHYS 318 319 #define ISSET(t, f) ((t) & (f)) 320 321 #define READ4(sc, reg) \ 322 (bus_space_read_4((sc)->rtsx_mem_btag, (sc)->rtsx_mem_bhandle, (reg))) 323 #define WRITE4(sc, reg, val) \ 324 (bus_space_write_4((sc)->rtsx_mem_btag, (sc)->rtsx_mem_bhandle, (reg), (val))) 325 326 #define RTSX_READ(sc, reg, val) \ 327 do { \ 328 int err = rtsx_read((sc), (reg), (val)); \ 329 if (err) \ 330 return (err); \ 331 } while (0) 332 333 #define RTSX_WRITE(sc, reg, val) \ 334 do { \ 335 int err = rtsx_write((sc), (reg), 0xff, (val)); \ 336 if (err) \ 337 return (err); \ 338 } while (0) 339 #define RTSX_CLR(sc, reg, bits) \ 340 do { \ 341 int err = rtsx_write((sc), (reg), (bits), 0); \ 342 if (err) \ 343 return (err); \ 344 } while (0) 345 346 #define RTSX_SET(sc, reg, bits) \ 347 do { \ 348 int err = rtsx_write((sc), (reg), (bits), 0xff);\ 349 if (err) \ 350 return (err); \ 351 } while (0) 352 353 #define RTSX_BITOP(sc, reg, mask, bits) \ 354 do { \ 355 int err = rtsx_write((sc), (reg), (mask), (bits)); \ 356 if (err) \ 357 return (err); \ 358 } while (0) 359 360 /* 361 * We use two DMA buffers: a command buffer and a data buffer. 362 * 363 * The command buffer contains a command queue for the host controller, 364 * which describes SD/MMC commands to run, and other parameters. The chip 365 * runs the command queue when a special bit in the RTSX_HCBAR register is 366 * set and signals completion with the RTSX_TRANS_OK_INT interrupt. 367 * Each command is encoded as a 4 byte sequence containing command number 368 * (read, write, or check a host controller register), a register address, 369 * and a data bit-mask and value. 370 * SD/MMC commands which do not transfer any data from/to the card only use 371 * the command buffer. 372 * 373 * The data buffer is used for transfer longer than 512. Data transfer is 374 * controlled via the RTSX_HDBAR register and completion is signalled by 375 * the RTSX_TRANS_OK_INT interrupt. 376 * 377 * The chip is unable to perform DMA above 4GB. 378 */ 379 380 /* 381 * Main commands in the usual seqence used: 382 * 383 * CMD0 Go idle state 384 * CMD8 Send interface condition 385 * CMD55 Application Command for next ACMD 386 * ACMD41 Send Operation Conditions Register (OCR: voltage profile of the card) 387 * CMD2 Send Card Identification (CID) Register 388 * CMD3 Send relative address 389 * CMD9 Send Card Specific Data (CSD) 390 * CMD13 Send status (32 bits - bit 25: card password protected) 391 * CMD7 Select card (before Get card SCR) 392 * ACMD51 Send SCR (SD CARD Configuration Register - [51:48]: Bus widths supported) 393 * CMD6 SD switch function 394 * ACMD13 Send SD status (512 bits) 395 * ACMD42 Set/Clear card detect 396 * ACMD6 Set bus width 397 * CMD19 Send tuning block 398 * CMD12 Stop transmission 399 * 400 * CMD17 Read single block (<=512) 401 * CMD18 Read multiple blocks (>512) 402 * CMD24 Write single block (<=512) 403 * CMD25 Write multiple blocks (>512) 404 * 405 * CMD52 IO R/W direct 406 * CMD5 Send Operation Conditions 407 */ 408 409 static int 410 rtsx_dma_alloc(struct rtsx_softc *sc) 411 { 412 int error = 0; 413 414 error = bus_dma_tag_create(bus_get_dma_tag(sc->rtsx_dev), /* inherit from parent */ 415 RTSX_DMA_ALIGN, 0, /* alignment, boundary */ 416 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 417 BUS_SPACE_MAXADDR, /* highaddr */ 418 NULL, NULL, /* filter, filterarg */ 419 RTSX_DMA_CMD_BIFSIZE, 1, /* maxsize, nsegments */ 420 RTSX_DMA_CMD_BIFSIZE, /* maxsegsize */ 421 0, /* flags */ 422 NULL, NULL, /* lockfunc, lockarg */ 423 &sc->rtsx_cmd_dma_tag); 424 if (error) { 425 device_printf(sc->rtsx_dev, 426 "Can't create cmd parent DMA tag\n"); 427 return (error); 428 } 429 error = bus_dmamem_alloc(sc->rtsx_cmd_dma_tag, /* DMA tag */ 430 &sc->rtsx_cmd_dmamem, /* will hold the KVA pointer */ 431 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, /* flags */ 432 &sc->rtsx_cmd_dmamap); /* DMA map */ 433 if (error) { 434 device_printf(sc->rtsx_dev, 435 "Can't create DMA map for command transfer\n"); 436 goto destroy_cmd_dma_tag; 437 438 } 439 error = bus_dmamap_load(sc->rtsx_cmd_dma_tag, /* DMA tag */ 440 sc->rtsx_cmd_dmamap, /* DMA map */ 441 sc->rtsx_cmd_dmamem, /* KVA pointer to be mapped */ 442 RTSX_DMA_CMD_BIFSIZE, /* size of buffer */ 443 rtsx_dmamap_cb, /* callback */ 444 &sc->rtsx_cmd_buffer, /* first arg of callback */ 445 0); /* flags */ 446 if (error || sc->rtsx_cmd_buffer == 0) { 447 device_printf(sc->rtsx_dev, 448 "Can't load DMA memory for command transfer\n"); 449 error = (error) ? error : EFAULT; 450 goto destroy_cmd_dmamem_alloc; 451 } 452 453 error = bus_dma_tag_create(bus_get_dma_tag(sc->rtsx_dev), /* inherit from parent */ 454 RTSX_DMA_DATA_BUFSIZE, 0, /* alignment, boundary */ 455 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 456 BUS_SPACE_MAXADDR, /* highaddr */ 457 NULL, NULL, /* filter, filterarg */ 458 RTSX_DMA_DATA_BUFSIZE, 1, /* maxsize, nsegments */ 459 RTSX_DMA_DATA_BUFSIZE, /* maxsegsize */ 460 0, /* flags */ 461 NULL, NULL, /* lockfunc, lockarg */ 462 &sc->rtsx_data_dma_tag); 463 if (error) { 464 device_printf(sc->rtsx_dev, 465 "Can't create data parent DMA tag\n"); 466 goto destroy_cmd_dmamap_load; 467 } 468 error = bus_dmamem_alloc(sc->rtsx_data_dma_tag, /* DMA tag */ 469 &sc->rtsx_data_dmamem, /* will hold the KVA pointer */ 470 BUS_DMA_WAITOK | BUS_DMA_ZERO, /* flags */ 471 &sc->rtsx_data_dmamap); /* DMA map */ 472 if (error) { 473 device_printf(sc->rtsx_dev, 474 "Can't create DMA map for data transfer\n"); 475 goto destroy_data_dma_tag; 476 } 477 error = bus_dmamap_load(sc->rtsx_data_dma_tag, /* DMA tag */ 478 sc->rtsx_data_dmamap, /* DMA map */ 479 sc->rtsx_data_dmamem, /* KVA pointer to be mapped */ 480 RTSX_DMA_DATA_BUFSIZE, /* size of buffer */ 481 rtsx_dmamap_cb, /* callback */ 482 &sc->rtsx_data_buffer, /* first arg of callback */ 483 0); /* flags */ 484 if (error || sc->rtsx_data_buffer == 0) { 485 device_printf(sc->rtsx_dev, 486 "Can't load DMA memory for data transfer\n"); 487 error = (error) ? error : EFAULT; 488 goto destroy_data_dmamem_alloc; 489 } 490 return (error); 491 492 destroy_data_dmamem_alloc: 493 bus_dmamem_free(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamem, sc->rtsx_data_dmamap); 494 destroy_data_dma_tag: 495 bus_dma_tag_destroy(sc->rtsx_data_dma_tag); 496 destroy_cmd_dmamap_load: 497 bus_dmamap_unload(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap); 498 destroy_cmd_dmamem_alloc: 499 bus_dmamem_free(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamem, sc->rtsx_cmd_dmamap); 500 destroy_cmd_dma_tag: 501 bus_dma_tag_destroy(sc->rtsx_cmd_dma_tag); 502 503 return (error); 504 } 505 506 static void 507 rtsx_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 508 { 509 if (error) { 510 printf("rtsx_dmamap_cb: error %d\n", error); 511 return; 512 } 513 *(bus_addr_t *)arg = segs[0].ds_addr; 514 } 515 516 static void 517 rtsx_dma_free(struct rtsx_softc *sc) 518 { 519 if (sc->rtsx_cmd_dma_tag != NULL) { 520 if (sc->rtsx_cmd_dmamap != NULL) 521 bus_dmamap_unload(sc->rtsx_cmd_dma_tag, 522 sc->rtsx_cmd_dmamap); 523 if (sc->rtsx_cmd_dmamem != NULL) 524 bus_dmamem_free(sc->rtsx_cmd_dma_tag, 525 sc->rtsx_cmd_dmamem, 526 sc->rtsx_cmd_dmamap); 527 sc->rtsx_cmd_dmamap = NULL; 528 sc->rtsx_cmd_dmamem = NULL; 529 sc->rtsx_cmd_buffer = 0; 530 bus_dma_tag_destroy(sc->rtsx_cmd_dma_tag); 531 sc->rtsx_cmd_dma_tag = NULL; 532 } 533 if (sc->rtsx_data_dma_tag != NULL) { 534 if (sc->rtsx_data_dmamap != NULL) 535 bus_dmamap_unload(sc->rtsx_data_dma_tag, 536 sc->rtsx_data_dmamap); 537 if (sc->rtsx_data_dmamem != NULL) 538 bus_dmamem_free(sc->rtsx_data_dma_tag, 539 sc->rtsx_data_dmamem, 540 sc->rtsx_data_dmamap); 541 sc->rtsx_data_dmamap = NULL; 542 sc->rtsx_data_dmamem = NULL; 543 sc->rtsx_data_buffer = 0; 544 bus_dma_tag_destroy(sc->rtsx_data_dma_tag); 545 sc->rtsx_data_dma_tag = NULL; 546 } 547 } 548 549 static void 550 rtsx_intr(void *arg) 551 { 552 struct rtsx_softc *sc = arg; 553 uint32_t enabled; 554 uint32_t status; 555 556 RTSX_LOCK(sc); 557 558 enabled = sc->rtsx_intr_enabled; 559 status = READ4(sc, RTSX_BIPR); /* read Bus Interrupt Pending Register */ 560 sc->rtsx_intr_status = status; 561 562 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 563 device_printf(sc->rtsx_dev, "Interrupt handler - enabled: 0x%08x, status: 0x%08x\n", enabled, status); 564 565 /* Ack interrupts. */ 566 WRITE4(sc, RTSX_BIPR, status); 567 568 if (((enabled & status) == 0) || status == 0xffffffff) { 569 device_printf(sc->rtsx_dev, "Spurious interrupt - enabled: 0x%08x, status: 0x%08x\n", enabled, status); 570 RTSX_UNLOCK(sc); 571 return; 572 } 573 574 /* Detect write protect. */ 575 if (status & RTSX_SD_WRITE_PROTECT) 576 sc->rtsx_read_only = 1; 577 else 578 sc->rtsx_read_only = 0; 579 580 /* Start task to handle SD card status change (from dwmmc.c). */ 581 if (status & RTSX_SD_INT) { 582 device_printf(sc->rtsx_dev, "Interrupt card inserted/removed\n"); 583 rtsx_handle_card_present(sc); 584 } 585 586 if (sc->rtsx_req == NULL) { 587 RTSX_UNLOCK(sc); 588 return; 589 } 590 591 if (status & RTSX_TRANS_OK_INT) { 592 sc->rtsx_req->cmd->error = MMC_ERR_NONE; 593 if (sc->rtsx_intr_trans_ok != NULL) 594 sc->rtsx_intr_trans_ok(sc); 595 } else if (status & RTSX_TRANS_FAIL_INT) { 596 uint8_t stat1; 597 sc->rtsx_req->cmd->error = MMC_ERR_FAILED; 598 if (rtsx_read(sc, RTSX_SD_STAT1, &stat1) == 0 && 599 (stat1 & RTSX_SD_CRC_ERR)) { 600 device_printf(sc->rtsx_dev, "CRC error\n"); 601 sc->rtsx_req->cmd->error = MMC_ERR_BADCRC; 602 } 603 if (!sc->rtsx_tuning_mode) 604 device_printf(sc->rtsx_dev, "Transfer fail - status: 0x%08x\n", status); 605 rtsx_stop_cmd(sc); 606 if (sc->rtsx_intr_trans_ko != NULL) 607 sc->rtsx_intr_trans_ko(sc); 608 } 609 610 RTSX_UNLOCK(sc); 611 } 612 613 /* 614 * Function called from the IRQ handler (from dwmmc.c). 615 */ 616 static void 617 rtsx_handle_card_present(struct rtsx_softc *sc) 618 { 619 bool was_present; 620 bool is_present; 621 622 #ifdef MMCCAM 623 was_present = sc->rtsx_cam_status; 624 #else /* !MMCCAM */ 625 was_present = sc->rtsx_mmc_dev != NULL; 626 #endif /* MMCCAM */ 627 is_present = rtsx_is_card_present(sc); 628 if (is_present) 629 device_printf(sc->rtsx_dev, "Card present\n"); 630 else 631 device_printf(sc->rtsx_dev, "Card absent\n"); 632 633 if (!was_present && is_present) { 634 /* 635 * The delay is to debounce the card insert 636 * (sometimes the card detect pin stabilizes 637 * before the other pins have made good contact). 638 */ 639 taskqueue_enqueue_timeout(taskqueue_swi_giant, 640 &sc->rtsx_card_insert_task, -hz); 641 } else if (was_present && !is_present) { 642 taskqueue_enqueue(taskqueue_swi_giant, &sc->rtsx_card_remove_task); 643 } 644 } 645 646 /* 647 * This function is called at startup. 648 */ 649 static void 650 rtsx_card_task(void *arg, int pending __unused) 651 { 652 struct rtsx_softc *sc = arg; 653 654 if (rtsx_is_card_present(sc)) { 655 sc->rtsx_flags |= RTSX_F_CARD_PRESENT; 656 /* Card is present, attach if necessary. */ 657 #ifdef MMCCAM 658 if (sc->rtsx_cam_status == 0) { 659 #else /* !MMCCAM */ 660 if (sc->rtsx_mmc_dev == NULL) { 661 #endif /* MMCCAM */ 662 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 663 device_printf(sc->rtsx_dev, "Card inserted\n"); 664 665 sc->rtsx_read_count = sc->rtsx_write_count = 0; 666 #ifdef MMCCAM 667 sc->rtsx_cam_status = 1; 668 mmc_cam_sim_discover(&sc->rtsx_mmc_sim); 669 #else /* !MMCCAM */ 670 RTSX_LOCK(sc); 671 sc->rtsx_mmc_dev = device_add_child(sc->rtsx_dev, "mmc", -1); 672 RTSX_UNLOCK(sc); 673 if (sc->rtsx_mmc_dev == NULL) { 674 device_printf(sc->rtsx_dev, "Adding MMC bus failed\n"); 675 } else { 676 device_set_ivars(sc->rtsx_mmc_dev, sc); 677 device_probe_and_attach(sc->rtsx_mmc_dev); 678 } 679 #endif /* MMCCAM */ 680 } 681 } else { 682 sc->rtsx_flags &= ~RTSX_F_CARD_PRESENT; 683 /* Card isn't present, detach if necessary. */ 684 #ifdef MMCCAM 685 if (sc->rtsx_cam_status != 0) { 686 #else /* !MMCCAM */ 687 if (sc->rtsx_mmc_dev != NULL) { 688 #endif /* MMCCAM */ 689 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 690 device_printf(sc->rtsx_dev, "Card removed\n"); 691 692 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 693 device_printf(sc->rtsx_dev, "Read count: %" PRIu64 ", write count: %" PRIu64 "\n", 694 sc->rtsx_read_count, sc->rtsx_write_count); 695 #ifdef MMCCAM 696 sc->rtsx_cam_status = 0; 697 mmc_cam_sim_discover(&sc->rtsx_mmc_sim); 698 #else /* !MMCCAM */ 699 if (device_delete_child(sc->rtsx_dev, sc->rtsx_mmc_dev)) 700 device_printf(sc->rtsx_dev, "Detaching MMC bus failed\n"); 701 sc->rtsx_mmc_dev = NULL; 702 #endif /* MMCCAM */ 703 } 704 } 705 } 706 707 static bool 708 rtsx_is_card_present(struct rtsx_softc *sc) 709 { 710 uint32_t status; 711 712 status = READ4(sc, RTSX_BIPR); 713 if (sc->rtsx_inversion == 0) 714 return (status & RTSX_SD_EXIST); 715 else 716 return !(status & RTSX_SD_EXIST); 717 } 718 719 static int 720 rtsx_init(struct rtsx_softc *sc) 721 { 722 uint8_t version; 723 uint8_t val; 724 int error; 725 726 sc->rtsx_host.host_ocr = RTSX_SUPPORTED_VOLTAGE; 727 sc->rtsx_host.f_min = RTSX_SDCLK_250KHZ; 728 sc->rtsx_host.f_max = RTSX_SDCLK_208MHZ; 729 sc->rtsx_host.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_HSPEED | 730 MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 731 732 sc->rtsx_host.caps |= MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104; 733 if (sc->rtsx_device_id == RTSX_RTS5209) 734 sc->rtsx_host.caps |= MMC_CAP_8_BIT_DATA; 735 pci_find_cap(sc->rtsx_dev, PCIY_EXPRESS, &(sc->rtsx_pcie_cap)); 736 737 /* 738 * Check IC version. 739 */ 740 switch (sc->rtsx_device_id) { 741 case RTSX_RTS5229: 742 /* Read IC version from dummy register. */ 743 RTSX_READ(sc, RTSX_DUMMY_REG, &version); 744 if ((version & 0x0F) == RTSX_IC_VERSION_C) 745 sc->rtsx_flags |= RTSX_F_VERSION_C; 746 break; 747 case RTSX_RTS522A: 748 /* Read IC version from dummy register. */ 749 RTSX_READ(sc, RTSX_DUMMY_REG, &version); 750 if ((version & 0x0F) == RTSX_IC_VERSION_A) 751 sc->rtsx_flags |= RTSX_F_VERSION_A; 752 break; 753 case RTSX_RTS525A: 754 /* Read IC version from dummy register. */ 755 RTSX_READ(sc, RTSX_DUMMY_REG, &version); 756 if ((version & 0x0F) == RTSX_IC_VERSION_A) 757 sc->rtsx_flags |= RTSX_F_VERSION_A; 758 break; 759 case RTSX_RTL8411B: 760 RTSX_READ(sc, RTSX_RTL8411B_PACKAGE, &version); 761 if (version & RTSX_RTL8411B_QFN48) 762 sc->rtsx_flags |= RTSX_F_8411B_QFN48; 763 break; 764 } 765 766 /* 767 * Fetch vendor settings. 768 */ 769 /* 770 * Normally OEMs will set vendor setting to the config space 771 * of Realtek card reader in BIOS stage. This statement reads 772 * the setting and configure the internal registers according 773 * to it, to improve card reader's compatibility condition. 774 */ 775 sc->rtsx_card_drive_sel = RTSX_CARD_DRIVE_DEFAULT; 776 switch (sc->rtsx_device_id) { 777 uint32_t reg; 778 uint32_t reg1; 779 uint8_t reg3; 780 case RTSX_RTS5209: 781 sc->rtsx_card_drive_sel = RTSX_RTS5209_CARD_DRIVE_DEFAULT; 782 sc->rtsx_sd30_drive_sel_3v3 = RTSX_DRIVER_TYPE_D; 783 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG2, 4); 784 if (!(reg & 0x80)) { 785 sc->rtsx_card_drive_sel = (reg >> 8) & 0x3F; 786 sc->rtsx_sd30_drive_sel_3v3 = reg & 0x07; 787 } else if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) { 788 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg); 789 } 790 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 791 device_printf(sc->rtsx_dev, "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x\n", 792 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3); 793 break; 794 case RTSX_RTS5227: 795 case RTSX_RTS522A: 796 sc->rtsx_sd30_drive_sel_3v3 = RTSX_CFG_DRIVER_TYPE_B; 797 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4); 798 if (!(reg & 0x1000000)) { 799 sc->rtsx_card_drive_sel &= 0x3F; 800 sc->rtsx_card_drive_sel |= ((reg >> 25) & 0x01) << 6; 801 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG2, 4); 802 sc->rtsx_sd30_drive_sel_3v3 = (reg >> 5) & 0x03; 803 if (reg & 0x4000) 804 sc->rtsx_flags |= RTSX_F_REVERSE_SOCKET; 805 } else if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) { 806 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg); 807 } 808 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 809 device_printf(sc->rtsx_dev, 810 "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x, reverse_socket is %s\n", 811 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3, 812 (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) ? "true" : "false"); 813 break; 814 case RTSX_RTS5229: 815 sc->rtsx_sd30_drive_sel_3v3 = RTSX_DRIVER_TYPE_D; 816 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4); 817 if (!(reg & 0x1000000)) { 818 sc->rtsx_card_drive_sel &= 0x3F; 819 sc->rtsx_card_drive_sel |= ((reg >> 25) & 0x01) << 6; 820 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG2, 4); 821 sc->rtsx_sd30_drive_sel_3v3 = rtsx_map_sd_drive((reg >> 5) & 0x03); 822 } else if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) { 823 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg); 824 } 825 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 826 device_printf(sc->rtsx_dev, "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x\n", 827 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3); 828 break; 829 case RTSX_RTS525A: 830 case RTSX_RTS5249: 831 case RTSX_RTS5260: 832 sc->rtsx_sd30_drive_sel_3v3 = RTSX_CFG_DRIVER_TYPE_B; 833 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4); 834 if ((reg & 0x1000000)) { 835 sc->rtsx_card_drive_sel &= 0x3F; 836 sc->rtsx_card_drive_sel |= ((reg >> 25) & 0x01) << 6; 837 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG2, 4); 838 sc->rtsx_sd30_drive_sel_3v3 = (reg >> 5) & 0x03; 839 if (reg & 0x4000) 840 sc->rtsx_flags |= RTSX_F_REVERSE_SOCKET; 841 } else if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) { 842 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg); 843 } 844 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 845 device_printf(sc->rtsx_dev, 846 "card_drive_sel = 0x%02x, sd30_drive_sel_3v3: 0x%02x, reverse_socket is %s\n", 847 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3, 848 (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) ? "true" : "false"); 849 break; 850 case RTSX_RTL8402: 851 case RTSX_RTL8411: 852 sc->rtsx_card_drive_sel = RTSX_RTL8411_CARD_DRIVE_DEFAULT; 853 sc->rtsx_sd30_drive_sel_3v3 = RTSX_DRIVER_TYPE_D; 854 reg1 = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4); 855 if (reg1 & 0x1000000) { 856 sc->rtsx_card_drive_sel &= 0x3F; 857 sc->rtsx_card_drive_sel |= ((reg1 >> 25) & 0x01) << 6; 858 reg3 = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG3, 1); 859 sc->rtsx_sd30_drive_sel_3v3 = (reg3 >> 5) & 0x07; 860 } else if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) { 861 device_printf(sc->rtsx_dev, "pci_read_config() error - reg1: 0x%08x\n", reg1); 862 } 863 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 864 device_printf(sc->rtsx_dev, 865 "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x\n", 866 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3); 867 break; 868 case RTSX_RTL8411B: 869 sc->rtsx_card_drive_sel = RTSX_RTL8411_CARD_DRIVE_DEFAULT; 870 sc->rtsx_sd30_drive_sel_3v3 = RTSX_DRIVER_TYPE_D; 871 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4); 872 if (!(reg & 0x1000000)) { 873 sc->rtsx_sd30_drive_sel_3v3 = rtsx_map_sd_drive(reg & 0x03); 874 } else if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) { 875 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg); 876 } 877 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 878 device_printf(sc->rtsx_dev, 879 "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x\n", 880 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3); 881 break; 882 } 883 884 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 885 device_printf(sc->rtsx_dev, "rtsx_init() rtsx_flags: 0x%04x\n", sc->rtsx_flags); 886 887 /* Enable interrupts. */ 888 sc->rtsx_intr_enabled = RTSX_TRANS_OK_INT_EN | RTSX_TRANS_FAIL_INT_EN | RTSX_SD_INT_EN; 889 WRITE4(sc, RTSX_BIER, sc->rtsx_intr_enabled); 890 891 /* Power on SSC clock. */ 892 RTSX_CLR(sc, RTSX_FPDCTL, RTSX_SSC_POWER_DOWN); 893 /* Wait SSC power stable. */ 894 DELAY(200); 895 896 /* Disable ASPM */ 897 val = pci_read_config(sc->rtsx_dev, sc->rtsx_pcie_cap + PCIER_LINK_CTL, 1); 898 pci_write_config(sc->rtsx_dev, sc->rtsx_pcie_cap + PCIER_LINK_CTL, val & 0xfc, 1); 899 900 /* 901 * Optimize phy. 902 */ 903 switch (sc->rtsx_device_id) { 904 case RTSX_RTS5209: 905 /* Some magic numbers from Linux driver. */ 906 if ((error = rtsx_write_phy(sc, 0x00, 0xB966))) 907 return (error); 908 break; 909 case RTSX_RTS5227: 910 RTSX_CLR(sc, RTSX_PM_CTRL3, RTSX_D3_DELINK_MODE_EN); 911 912 /* Optimize RX sensitivity. */ 913 if ((error = rtsx_write_phy(sc, 0x00, 0xBA42))) 914 return (error); 915 break; 916 case RTSX_RTS5229: 917 /* Optimize RX sensitivity. */ 918 if ((error = rtsx_write_phy(sc, 0x00, 0xBA42))) 919 return (error); 920 break; 921 case RTSX_RTS522A: 922 RTSX_CLR(sc, RTSX_RTS522A_PM_CTRL3, RTSX_D3_DELINK_MODE_EN); 923 if (sc->rtsx_flags & RTSX_F_VERSION_A) { 924 if ((error = rtsx_write_phy(sc, RTSX_PHY_RCR2, RTSX_PHY_RCR2_INIT_27S))) 925 return (error); 926 } 927 if ((error = rtsx_write_phy(sc, RTSX_PHY_RCR1, RTSX_PHY_RCR1_INIT_27S))) 928 return (error); 929 if ((error = rtsx_write_phy(sc, RTSX_PHY_FLD0, RTSX_PHY_FLD0_INIT_27S))) 930 return (error); 931 if ((error = rtsx_write_phy(sc, RTSX_PHY_FLD3, RTSX_PHY_FLD3_INIT_27S))) 932 return (error); 933 if ((error = rtsx_write_phy(sc, RTSX_PHY_FLD4, RTSX_PHY_FLD4_INIT_27S))) 934 return (error); 935 break; 936 case RTSX_RTS525A: 937 if ((error = rtsx_write_phy(sc, RTSX__PHY_FLD0, 938 RTSX__PHY_FLD0_CLK_REQ_20C | RTSX__PHY_FLD0_RX_IDLE_EN | 939 RTSX__PHY_FLD0_BIT_ERR_RSTN | RTSX__PHY_FLD0_BER_COUNT | 940 RTSX__PHY_FLD0_BER_TIMER | RTSX__PHY_FLD0_CHECK_EN))) 941 return (error); 942 if ((error = rtsx_write_phy(sc, RTSX__PHY_ANA03, 943 RTSX__PHY_ANA03_TIMER_MAX | RTSX__PHY_ANA03_OOBS_DEB_EN | 944 RTSX__PHY_CMU_DEBUG_EN))) 945 return (error); 946 if (sc->rtsx_flags & RTSX_F_VERSION_A) 947 if ((error = rtsx_write_phy(sc, RTSX__PHY_REV0, 948 RTSX__PHY_REV0_FILTER_OUT | RTSX__PHY_REV0_CDR_BYPASS_PFD | 949 RTSX__PHY_REV0_CDR_RX_IDLE_BYPASS))) 950 return (error); 951 break; 952 case RTSX_RTS5249: 953 RTSX_CLR(sc, RTSX_PM_CTRL3, RTSX_D3_DELINK_MODE_EN); 954 if ((error = rtsx_write_phy(sc, RTSX_PHY_REV, 955 RTSX_PHY_REV_RESV | RTSX_PHY_REV_RXIDLE_LATCHED | 956 RTSX_PHY_REV_P1_EN | RTSX_PHY_REV_RXIDLE_EN | 957 RTSX_PHY_REV_CLKREQ_TX_EN | RTSX_PHY_REV_RX_PWST | 958 RTSX_PHY_REV_CLKREQ_DT_1_0 | RTSX_PHY_REV_STOP_CLKRD | 959 RTSX_PHY_REV_STOP_CLKWR))) 960 return (error); 961 DELAY(1000); 962 if ((error = rtsx_write_phy(sc, RTSX_PHY_BPCR, 963 RTSX_PHY_BPCR_IBRXSEL | RTSX_PHY_BPCR_IBTXSEL | 964 RTSX_PHY_BPCR_IB_FILTER | RTSX_PHY_BPCR_CMIRROR_EN))) 965 return (error); 966 if ((error = rtsx_write_phy(sc, RTSX_PHY_PCR, 967 RTSX_PHY_PCR_FORCE_CODE | RTSX_PHY_PCR_OOBS_CALI_50 | 968 RTSX_PHY_PCR_OOBS_VCM_08 | RTSX_PHY_PCR_OOBS_SEN_90 | 969 RTSX_PHY_PCR_RSSI_EN | RTSX_PHY_PCR_RX10K))) 970 return (error); 971 if ((error = rtsx_write_phy(sc, RTSX_PHY_RCR2, 972 RTSX_PHY_RCR2_EMPHASE_EN | RTSX_PHY_RCR2_NADJR | 973 RTSX_PHY_RCR2_CDR_SR_2 | RTSX_PHY_RCR2_FREQSEL_12 | 974 RTSX_PHY_RCR2_CDR_SC_12P | RTSX_PHY_RCR2_CALIB_LATE))) 975 return (error); 976 if ((error = rtsx_write_phy(sc, RTSX_PHY_FLD4, 977 RTSX_PHY_FLD4_FLDEN_SEL | RTSX_PHY_FLD4_REQ_REF | 978 RTSX_PHY_FLD4_RXAMP_OFF | RTSX_PHY_FLD4_REQ_ADDA | 979 RTSX_PHY_FLD4_BER_COUNT | RTSX_PHY_FLD4_BER_TIMER | 980 RTSX_PHY_FLD4_BER_CHK_EN))) 981 return (error); 982 if ((error = rtsx_write_phy(sc, RTSX_PHY_RDR, 983 RTSX_PHY_RDR_RXDSEL_1_9 | RTSX_PHY_SSC_AUTO_PWD))) 984 return (error); 985 if ((error = rtsx_write_phy(sc, RTSX_PHY_RCR1, 986 RTSX_PHY_RCR1_ADP_TIME_4 | RTSX_PHY_RCR1_VCO_COARSE))) 987 return (error); 988 if ((error = rtsx_write_phy(sc, RTSX_PHY_FLD3, 989 RTSX_PHY_FLD3_TIMER_4 | RTSX_PHY_FLD3_TIMER_6 | 990 RTSX_PHY_FLD3_RXDELINK))) 991 return (error); 992 if ((error = rtsx_write_phy(sc, RTSX_PHY_TUNE, 993 RTSX_PHY_TUNE_TUNEREF_1_0 | RTSX_PHY_TUNE_VBGSEL_1252 | 994 RTSX_PHY_TUNE_SDBUS_33 | RTSX_PHY_TUNE_TUNED18 | 995 RTSX_PHY_TUNE_TUNED12 | RTSX_PHY_TUNE_TUNEA12))) 996 return (error); 997 break; 998 } 999 1000 /* Set mcu_cnt to 7 to ensure data can be sampled properly. */ 1001 RTSX_BITOP(sc, RTSX_CLK_DIV, 0x07, 0x07); 1002 1003 /* Disable sleep mode. */ 1004 RTSX_CLR(sc, RTSX_HOST_SLEEP_STATE, 1005 RTSX_HOST_ENTER_S1 | RTSX_HOST_ENTER_S3); 1006 1007 /* Disable card clock. */ 1008 RTSX_CLR(sc, RTSX_CARD_CLK_EN, RTSX_CARD_CLK_EN_ALL); 1009 1010 /* Reset delink mode. */ 1011 RTSX_CLR(sc, RTSX_CHANGE_LINK_STATE, 1012 RTSX_FORCE_RST_CORE_EN | RTSX_NON_STICKY_RST_N_DBG); 1013 1014 /* Card driving select. */ 1015 RTSX_WRITE(sc, RTSX_CARD_DRIVE_SEL, sc->rtsx_card_drive_sel); 1016 1017 /* Enable SSC clock. */ 1018 RTSX_WRITE(sc, RTSX_SSC_CTL1, RTSX_SSC_8X_EN | RTSX_SSC_SEL_4M); 1019 RTSX_WRITE(sc, RTSX_SSC_CTL2, 0x12); 1020 1021 /* Disable cd_pwr_save. */ 1022 RTSX_BITOP(sc, RTSX_CHANGE_LINK_STATE, 0x16, RTSX_MAC_PHY_RST_N_DBG); 1023 1024 /* Clear Link Ready Interrupt. */ 1025 RTSX_BITOP(sc, RTSX_IRQSTAT0, RTSX_LINK_READY_INT, RTSX_LINK_READY_INT); 1026 1027 /* Enlarge the estimation window of PERST# glitch 1028 * to reduce the chance of invalid card interrupt. */ 1029 RTSX_WRITE(sc, RTSX_PERST_GLITCH_WIDTH, 0x80); 1030 1031 /* Set RC oscillator to 400K. */ 1032 RTSX_CLR(sc, RTSX_RCCTL, RTSX_RCCTL_F_2M); 1033 1034 /* Enable interrupt write-clear (default is read-clear). */ 1035 RTSX_CLR(sc, RTSX_NFTS_TX_CTRL, RTSX_INT_READ_CLR); 1036 1037 switch (sc->rtsx_device_id) { 1038 case RTSX_RTS525A: 1039 case RTSX_RTS5260: 1040 RTSX_BITOP(sc, RTSX_PM_CLK_FORCE_CTL, 1, 1); 1041 break; 1042 } 1043 1044 /* OC power down. */ 1045 RTSX_BITOP(sc, RTSX_FPDCTL, RTSX_SD_OC_POWER_DOWN, RTSX_SD_OC_POWER_DOWN); 1046 1047 /* Enable clk_request_n to enable clock power management */ 1048 pci_write_config(sc->rtsx_dev, sc->rtsx_pcie_cap + PCIER_LINK_CTL + 1, 1, 1); 1049 1050 /* Enter L1 when host tx idle */ 1051 pci_write_config(sc->rtsx_dev, 0x70F, 0x5B, 1); 1052 1053 /* 1054 * Specific extra init. 1055 */ 1056 switch (sc->rtsx_device_id) { 1057 uint16_t cap; 1058 case RTSX_RTS5209: 1059 /* Turn off LED. */ 1060 RTSX_WRITE(sc, RTSX_CARD_GPIO, 0x03); 1061 /* Reset ASPM state to default value. */ 1062 RTSX_CLR(sc, RTSX_ASPM_FORCE_CTL, RTSX_ASPM_FORCE_MASK); 1063 /* Force CLKREQ# PIN to drive 0 to request clock. */ 1064 RTSX_BITOP(sc, RTSX_PETXCFG, 0x08, 0x08); 1065 /* Configure GPIO as output. */ 1066 RTSX_WRITE(sc, RTSX_CARD_GPIO_DIR, 0x03); 1067 /* Configure driving. */ 1068 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, sc->rtsx_sd30_drive_sel_3v3); 1069 break; 1070 case RTSX_RTS5227: 1071 /* Configure GPIO as output. */ 1072 RTSX_BITOP(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON, RTSX_GPIO_LED_ON); 1073 /* Reset ASPM state to default value. */ 1074 RTSX_BITOP(sc, RTSX_ASPM_FORCE_CTL, RTSX_ASPM_FORCE_MASK, RTSX_FORCE_ASPM_NO_ASPM); 1075 /* Switch LDO3318 source from DV33 to 3V3. */ 1076 RTSX_CLR(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33); 1077 RTSX_BITOP(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33, RTSX_LDO_PWR_SEL_3V3); 1078 /* Set default OLT blink period. */ 1079 RTSX_BITOP(sc, RTSX_OLT_LED_CTL, 0x0F, RTSX_OLT_LED_PERIOD); 1080 /* Configure LTR. */ 1081 cap = pci_read_config(sc->rtsx_dev, sc->rtsx_pcie_cap + PCIER_DEVICE_CTL2, 2); 1082 if (cap & PCIEM_CTL2_LTR_ENABLE) 1083 RTSX_WRITE(sc, RTSX_LTR_CTL, 0xa3); 1084 /* Configure OBFF. */ 1085 RTSX_BITOP(sc, RTSX_OBFF_CFG, RTSX_OBFF_EN_MASK, RTSX_OBFF_ENABLE); 1086 /* Configure driving. */ 1087 if ((error = rtsx_rts5227_fill_driving(sc))) 1088 return (error); 1089 /* Configure force_clock_req. */ 1090 if (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) 1091 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB8, 0xB8); 1092 else 1093 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB8, 0x88); 1094 RTSX_CLR(sc, RTSX_PM_CTRL3, RTSX_D3_DELINK_MODE_EN); 1095 /*!!! Added for reboot after Windows. */ 1096 RTSX_BITOP(sc, RTSX_PM_CTRL3, RTSX_PM_WAKE_EN, RTSX_PM_WAKE_EN); 1097 break; 1098 case RTSX_RTS5229: 1099 /* Configure GPIO as output. */ 1100 RTSX_BITOP(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON, RTSX_GPIO_LED_ON); 1101 /* Reset ASPM state to default value. */ 1102 /* With this reset: dd if=/dev/random of=/dev/mmcsd0 encounter a timeout. */ 1103 //!!! RTSX_BITOP(sc, RTSX_ASPM_FORCE_CTL, RTSX_ASPM_FORCE_MASK, RTSX_FORCE_ASPM_NO_ASPM); 1104 /* Force CLKREQ# PIN to drive 0 to request clock. */ 1105 RTSX_BITOP(sc, RTSX_PETXCFG, 0x08, 0x08); 1106 /* Switch LDO3318 source from DV33 to card_3v3. */ 1107 RTSX_CLR(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33); 1108 RTSX_BITOP(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33, RTSX_LDO_PWR_SEL_3V3); 1109 /* Set default OLT blink period. */ 1110 RTSX_BITOP(sc, RTSX_OLT_LED_CTL, 0x0F, RTSX_OLT_LED_PERIOD); 1111 /* Configure driving. */ 1112 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, sc->rtsx_sd30_drive_sel_3v3); 1113 break; 1114 case RTSX_RTS522A: 1115 /* Add specific init from RTS5227. */ 1116 /* Configure GPIO as output. */ 1117 RTSX_BITOP(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON, RTSX_GPIO_LED_ON); 1118 /* Reset ASPM state to default value. */ 1119 RTSX_BITOP(sc, RTSX_ASPM_FORCE_CTL, RTSX_ASPM_FORCE_MASK, RTSX_FORCE_ASPM_NO_ASPM); 1120 /* Switch LDO3318 source from DV33 to 3V3. */ 1121 RTSX_CLR(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33); 1122 RTSX_BITOP(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33, RTSX_LDO_PWR_SEL_3V3); 1123 /* Set default OLT blink period. */ 1124 RTSX_BITOP(sc, RTSX_OLT_LED_CTL, 0x0F, RTSX_OLT_LED_PERIOD); 1125 /* Configure LTR. */ 1126 cap = pci_read_config(sc->rtsx_dev, sc->rtsx_pcie_cap + PCIER_DEVICE_CTL2, 2); 1127 if (cap & PCIEM_CTL2_LTR_ENABLE) 1128 RTSX_WRITE(sc, RTSX_LTR_CTL, 0xa3); 1129 /* Configure OBFF. */ 1130 RTSX_BITOP(sc, RTSX_OBFF_CFG, RTSX_OBFF_EN_MASK, RTSX_OBFF_ENABLE); 1131 /* Configure driving. */ 1132 if ((error = rtsx_rts5227_fill_driving(sc))) 1133 return (error); 1134 /* Configure force_clock_req. */ 1135 if (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) 1136 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB8, 0xB8); 1137 else 1138 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB8, 0x88); 1139 RTSX_CLR(sc, RTSX_RTS522A_PM_CTRL3, 0x10); 1140 1141 /* specific for RTS522A. */ 1142 RTSX_BITOP(sc, RTSX_FUNC_FORCE_CTL, 1143 RTSX_FUNC_FORCE_UPME_XMT_DBG, RTSX_FUNC_FORCE_UPME_XMT_DBG); 1144 RTSX_BITOP(sc, RTSX_PCLK_CTL, 0x04, 0x04); 1145 RTSX_BITOP(sc, RTSX_PM_EVENT_DEBUG, 1146 RTSX_PME_DEBUG_0, RTSX_PME_DEBUG_0); 1147 RTSX_WRITE(sc, RTSX_PM_CLK_FORCE_CTL, 0x11); 1148 break; 1149 case RTSX_RTS525A: 1150 /* Add specific init from RTS5249. */ 1151 /* Rest L1SUB Config. */ 1152 RTSX_CLR(sc, RTSX_L1SUB_CONFIG3, 0xff); 1153 /* Configure GPIO as output. */ 1154 RTSX_BITOP(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON, RTSX_GPIO_LED_ON); 1155 /* Reset ASPM state to default value. */ 1156 RTSX_BITOP(sc, RTSX_ASPM_FORCE_CTL, RTSX_ASPM_FORCE_MASK, RTSX_FORCE_ASPM_NO_ASPM); 1157 /* Switch LDO3318 source from DV33 to 3V3. */ 1158 RTSX_CLR(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33); 1159 RTSX_BITOP(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33, RTSX_LDO_PWR_SEL_3V3); 1160 /* Set default OLT blink period. */ 1161 RTSX_BITOP(sc, RTSX_OLT_LED_CTL, 0x0F, RTSX_OLT_LED_PERIOD); 1162 /* Configure driving. */ 1163 if ((error = rtsx_rts5249_fill_driving(sc))) 1164 return (error); 1165 /* Configure force_clock_req. */ 1166 if (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) 1167 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0xB0); 1168 else 1169 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0x80); 1170 1171 /* Specifc for RTS525A. */ 1172 RTSX_BITOP(sc, RTSX_PCLK_CTL, RTSX_PCLK_MODE_SEL, RTSX_PCLK_MODE_SEL); 1173 if (sc->rtsx_flags & RTSX_F_VERSION_A) { 1174 RTSX_WRITE(sc, RTSX_L1SUB_CONFIG2, RTSX_L1SUB_AUTO_CFG); 1175 RTSX_BITOP(sc, RTSX_RREF_CFG, 1176 RTSX_RREF_VBGSEL_MASK, RTSX_RREF_VBGSEL_1V25); 1177 RTSX_BITOP(sc, RTSX_LDO_VIO_CFG, 1178 RTSX_LDO_VIO_TUNE_MASK, RTSX_LDO_VIO_1V7); 1179 RTSX_BITOP(sc, RTSX_LDO_DV12S_CFG, 1180 RTSX_LDO_D12_TUNE_MASK, RTSX_LDO_D12_TUNE_DF); 1181 RTSX_BITOP(sc, RTSX_LDO_AV12S_CFG, 1182 RTSX_LDO_AV12S_TUNE_MASK, RTSX_LDO_AV12S_TUNE_DF); 1183 RTSX_BITOP(sc, RTSX_LDO_VCC_CFG0, 1184 RTSX_LDO_VCC_LMTVTH_MASK, RTSX_LDO_VCC_LMTVTH_2A); 1185 RTSX_BITOP(sc, RTSX_OOBS_CONFIG, 1186 RTSX_OOBS_AUTOK_DIS | RTSX_OOBS_VAL_MASK, 0x89); 1187 } 1188 break; 1189 case RTSX_RTS5249: 1190 /* Rest L1SUB Config. */ 1191 RTSX_CLR(sc, RTSX_L1SUB_CONFIG3, 0xff); 1192 /* Configure GPIO as output. */ 1193 RTSX_BITOP(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON, RTSX_GPIO_LED_ON); 1194 /* Reset ASPM state to default value. */ 1195 RTSX_BITOP(sc, RTSX_ASPM_FORCE_CTL, RTSX_ASPM_FORCE_MASK, RTSX_FORCE_ASPM_NO_ASPM); 1196 /* Switch LDO3318 source from DV33 to 3V3. */ 1197 RTSX_CLR(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33); 1198 RTSX_BITOP(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33, RTSX_LDO_PWR_SEL_3V3); 1199 /* Set default OLT blink period. */ 1200 RTSX_BITOP(sc, RTSX_OLT_LED_CTL, 0x0F, RTSX_OLT_LED_PERIOD); 1201 /* Configure driving. */ 1202 if ((error = rtsx_rts5249_fill_driving(sc))) 1203 return (error); 1204 /* Configure force_clock_req. */ 1205 if (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) 1206 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0xB0); 1207 else 1208 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0x80); 1209 break; 1210 case RTSX_RTS5260: 1211 /* Set mcu_cnt to 7 to ensure data can be sampled properly. */ 1212 RTSX_BITOP(sc, RTSX_CLK_DIV, 0x07, 0x07); 1213 RTSX_WRITE(sc, RTSX_SSC_DIV_N_0, 0x5D); 1214 /* Force no MDIO */ 1215 RTSX_WRITE(sc, RTSX_RTS5260_AUTOLOAD_CFG4, RTSX_RTS5260_MIMO_DISABLE); 1216 /* Modify SDVCC Tune Default Parameters! */ 1217 RTSX_BITOP(sc, RTSX_LDO_VCC_CFG0, RTSX_RTS5260_DVCC_TUNE_MASK, RTSX_RTS5260_DVCC_33); 1218 1219 RTSX_BITOP(sc, RTSX_PCLK_CTL, RTSX_PCLK_MODE_SEL, RTSX_PCLK_MODE_SEL); 1220 1221 RTSX_BITOP(sc, RTSX_L1SUB_CONFIG1, RTSX_AUX_CLK_ACTIVE_SEL_MASK, RTSX_MAC_CKSW_DONE); 1222 /* Rest L1SUB Config */ 1223 RTSX_CLR(sc, RTSX_L1SUB_CONFIG3, 0xFF); 1224 RTSX_BITOP(sc, RTSX_PM_CLK_FORCE_CTL, RTSX_CLK_PM_EN, RTSX_CLK_PM_EN); 1225 RTSX_WRITE(sc, RTSX_PWD_SUSPEND_EN, 0xFF); 1226 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_PWR_GATE_EN, RTSX_PWR_GATE_EN); 1227 RTSX_BITOP(sc, RTSX_REG_VREF, RTSX_PWD_SUSPND_EN, RTSX_PWD_SUSPND_EN); 1228 RTSX_BITOP(sc, RTSX_RBCTL, RTSX_U_AUTO_DMA_EN_MASK, RTSX_U_AUTO_DMA_DISABLE); 1229 if (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) 1230 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0xB0); 1231 else 1232 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0x80); 1233 RTSX_BITOP(sc, RTSX_OBFF_CFG, RTSX_OBFF_EN_MASK, RTSX_OBFF_DISABLE); 1234 1235 RTSX_CLR(sc, RTSX_RTS5260_DVCC_CTRL, RTSX_RTS5260_DVCC_OCP_EN | RTSX_RTS5260_DVCC_OCP_CL_EN); 1236 1237 /* CLKREQ# PIN will be forced to drive low. */ 1238 RTSX_BITOP(sc, RTSX_PETXCFG, RTSX_FORCE_CLKREQ_DELINK_MASK, RTSX_FORCE_CLKREQ_LOW); 1239 1240 RTSX_CLR(sc, RTSX_RTS522A_PM_CTRL3, 0x10); 1241 break; 1242 case RTSX_RTL8402: 1243 case RTSX_RTL8411: 1244 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, sc->rtsx_sd30_drive_sel_3v3); 1245 RTSX_BITOP(sc, RTSX_CARD_PAD_CTL, RTSX_CD_DISABLE_MASK | RTSX_CD_AUTO_DISABLE, 1246 RTSX_CD_ENABLE); 1247 break; 1248 case RTSX_RTL8411B: 1249 if (sc->rtsx_flags & RTSX_F_8411B_QFN48) 1250 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xf5); 1251 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, sc->rtsx_sd30_drive_sel_3v3); 1252 /* Enable SD interrupt. */ 1253 RTSX_BITOP(sc, RTSX_CARD_PAD_CTL, RTSX_CD_DISABLE_MASK | RTSX_CD_AUTO_DISABLE, 1254 RTSX_CD_ENABLE); 1255 /* Clear hw_pfm_en to disable hardware PFM mode. */ 1256 RTSX_BITOP(sc, RTSX_FUNC_FORCE_CTL, 0x06, 0x00); 1257 break; 1258 } 1259 1260 /*!!! Added for reboot after Windows. */ 1261 rtsx_bus_power_off(sc); 1262 rtsx_set_sd_timing(sc, bus_timing_normal); 1263 rtsx_set_sd_clock(sc, 0); 1264 /*!!! Added for reboot after Windows. */ 1265 1266 return (0); 1267 } 1268 1269 static int 1270 rtsx_map_sd_drive(int index) 1271 { 1272 uint8_t sd_drive[4] = 1273 { 1274 0x01, /* Type D */ 1275 0x02, /* Type C */ 1276 0x05, /* Type A */ 1277 0x03 /* Type B */ 1278 }; 1279 return (sd_drive[index]); 1280 } 1281 1282 /* For voltage 3v3. */ 1283 static int 1284 rtsx_rts5227_fill_driving(struct rtsx_softc *sc) 1285 { 1286 u_char driving_3v3[4][3] = { 1287 {0x13, 0x13, 0x13}, 1288 {0x96, 0x96, 0x96}, 1289 {0x7F, 0x7F, 0x7F}, 1290 {0x96, 0x96, 0x96}, 1291 }; 1292 RTSX_WRITE(sc, RTSX_SD30_CLK_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][0]); 1293 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][1]); 1294 RTSX_WRITE(sc, RTSX_SD30_DAT_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][2]); 1295 1296 return (0); 1297 } 1298 1299 /* For voltage 3v3. */ 1300 static int 1301 rtsx_rts5249_fill_driving(struct rtsx_softc *sc) 1302 { 1303 u_char driving_3v3[4][3] = { 1304 {0x11, 0x11, 0x18}, 1305 {0x55, 0x55, 0x5C}, 1306 {0xFF, 0xFF, 0xFF}, 1307 {0x96, 0x96, 0x96}, 1308 }; 1309 RTSX_WRITE(sc, RTSX_SD30_CLK_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][0]); 1310 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][1]); 1311 RTSX_WRITE(sc, RTSX_SD30_DAT_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][2]); 1312 1313 return (0); 1314 } 1315 1316 static int 1317 rtsx_rts5260_fill_driving(struct rtsx_softc *sc) 1318 { 1319 u_char driving_3v3[4][3] = { 1320 {0x11, 0x11, 0x11}, 1321 {0x22, 0x22, 0x22}, 1322 {0x55, 0x55, 0x55}, 1323 {0x33, 0x33, 0x33}, 1324 }; 1325 RTSX_WRITE(sc, RTSX_SD30_CLK_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][0]); 1326 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][1]); 1327 RTSX_WRITE(sc, RTSX_SD30_DAT_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][2]); 1328 1329 return (0); 1330 } 1331 1332 static int 1333 rtsx_read(struct rtsx_softc *sc, uint16_t addr, uint8_t *val) 1334 { 1335 int tries = 1024; 1336 uint32_t arg; 1337 uint32_t reg; 1338 1339 arg = RTSX_HAIMR_BUSY | (uint32_t)((addr & 0x3FFF) << 16); 1340 WRITE4(sc, RTSX_HAIMR, arg); 1341 1342 while (tries--) { 1343 reg = READ4(sc, RTSX_HAIMR); 1344 if (!(reg & RTSX_HAIMR_BUSY)) 1345 break; 1346 } 1347 *val = (reg & 0xff); 1348 1349 if (tries > 0) { 1350 return (0); 1351 } else { 1352 device_printf(sc->rtsx_dev, "rtsx_read(0x%x) timeout\n", arg); 1353 return (ETIMEDOUT); 1354 } 1355 } 1356 1357 static int 1358 rtsx_read_cfg(struct rtsx_softc *sc, uint8_t func, uint16_t addr, uint32_t *val) 1359 { 1360 int tries = 1024; 1361 uint8_t data0, data1, data2, data3, rwctl; 1362 1363 RTSX_WRITE(sc, RTSX_CFGADDR0, addr); 1364 RTSX_WRITE(sc, RTSX_CFGADDR1, addr >> 8); 1365 RTSX_WRITE(sc, RTSX_CFGRWCTL, RTSX_CFG_BUSY | (func & 0x03 << 4)); 1366 1367 while (tries--) { 1368 RTSX_READ(sc, RTSX_CFGRWCTL, &rwctl); 1369 if (!(rwctl & RTSX_CFG_BUSY)) 1370 break; 1371 } 1372 1373 if (tries == 0) 1374 return (ETIMEDOUT); 1375 1376 RTSX_READ(sc, RTSX_CFGDATA0, &data0); 1377 RTSX_READ(sc, RTSX_CFGDATA1, &data1); 1378 RTSX_READ(sc, RTSX_CFGDATA2, &data2); 1379 RTSX_READ(sc, RTSX_CFGDATA3, &data3); 1380 1381 *val = (data3 << 24) | (data2 << 16) | (data1 << 8) | data0; 1382 1383 return (0); 1384 } 1385 1386 static int 1387 rtsx_write(struct rtsx_softc *sc, uint16_t addr, uint8_t mask, uint8_t val) 1388 { 1389 int tries = 1024; 1390 uint32_t arg; 1391 uint32_t reg; 1392 1393 arg = RTSX_HAIMR_BUSY | RTSX_HAIMR_WRITE | 1394 (uint32_t)(((addr & 0x3FFF) << 16) | 1395 (mask << 8) | val); 1396 WRITE4(sc, RTSX_HAIMR, arg); 1397 1398 while (tries--) { 1399 reg = READ4(sc, RTSX_HAIMR); 1400 if (!(reg & RTSX_HAIMR_BUSY)) { 1401 if (val != (reg & 0xff)) { 1402 device_printf(sc->rtsx_dev, "rtsx_write(0x%x) error reg=0x%x\n", arg, reg); 1403 return (EIO); 1404 } 1405 return (0); 1406 } 1407 } 1408 device_printf(sc->rtsx_dev, "rtsx_write(0x%x) timeout\n", arg); 1409 1410 return (ETIMEDOUT); 1411 } 1412 1413 static int 1414 rtsx_read_phy(struct rtsx_softc *sc, uint8_t addr, uint16_t *val) 1415 { 1416 int tries = 100000; 1417 uint8_t data0, data1, rwctl; 1418 1419 RTSX_WRITE(sc, RTSX_PHY_ADDR, addr); 1420 RTSX_WRITE(sc, RTSX_PHY_RWCTL, RTSX_PHY_BUSY | RTSX_PHY_READ); 1421 1422 while (tries--) { 1423 RTSX_READ(sc, RTSX_PHY_RWCTL, &rwctl); 1424 if (!(rwctl & RTSX_PHY_BUSY)) 1425 break; 1426 } 1427 if (tries == 0) 1428 return (ETIMEDOUT); 1429 1430 RTSX_READ(sc, RTSX_PHY_DATA0, &data0); 1431 RTSX_READ(sc, RTSX_PHY_DATA1, &data1); 1432 *val = data1 << 8 | data0; 1433 1434 return (0); 1435 } 1436 1437 static int 1438 rtsx_write_phy(struct rtsx_softc *sc, uint8_t addr, uint16_t val) 1439 { 1440 int tries = 100000; 1441 uint8_t rwctl; 1442 1443 RTSX_WRITE(sc, RTSX_PHY_DATA0, val); 1444 RTSX_WRITE(sc, RTSX_PHY_DATA1, val >> 8); 1445 RTSX_WRITE(sc, RTSX_PHY_ADDR, addr); 1446 RTSX_WRITE(sc, RTSX_PHY_RWCTL, RTSX_PHY_BUSY | RTSX_PHY_WRITE); 1447 1448 while (tries--) { 1449 RTSX_READ(sc, RTSX_PHY_RWCTL, &rwctl); 1450 if (!(rwctl & RTSX_PHY_BUSY)) 1451 break; 1452 } 1453 1454 return ((tries == 0) ? ETIMEDOUT : 0); 1455 } 1456 1457 /* 1458 * Notice that the meaning of RTSX_PWR_GATE_CTRL changes between RTS5209 and 1459 * RTS5229. In RTS5209 it is a mask of disabled power gates, while in RTS5229 1460 * it is a mask of *enabled* gates. 1461 */ 1462 static int 1463 rtsx_bus_power_off(struct rtsx_softc *sc) 1464 { 1465 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 1466 device_printf(sc->rtsx_dev, "rtsx_bus_power_off()\n"); 1467 1468 /* Disable SD clock. */ 1469 RTSX_CLR(sc, RTSX_CARD_CLK_EN, RTSX_SD_CLK_EN); 1470 1471 /* Disable SD output. */ 1472 RTSX_CLR(sc, RTSX_CARD_OE, RTSX_SD_OUTPUT_EN); 1473 1474 /* Turn off power. */ 1475 switch (sc->rtsx_device_id) { 1476 case RTSX_RTS5209: 1477 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK | RTSX_PMOS_STRG_MASK, 1478 RTSX_SD_PWR_OFF | RTSX_PMOS_STRG_400mA); 1479 RTSX_SET(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_OFF); 1480 break; 1481 case RTSX_RTS5227: 1482 case RTSX_RTS5229: 1483 case RTSX_RTS522A: 1484 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK | RTSX_PMOS_STRG_MASK, 1485 RTSX_SD_PWR_OFF | RTSX_PMOS_STRG_400mA); 1486 RTSX_CLR(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK); 1487 break; 1488 case RTSX_RTS5260: 1489 rtsx_stop_cmd(sc); 1490 /* Switch vccq to 330 */ 1491 RTSX_BITOP(sc, RTSX_LDO_CONFIG2, RTSX_DV331812_VDD1, RTSX_DV331812_VDD1); 1492 RTSX_BITOP(sc, RTSX_LDO_DV18_CFG, RTSX_DV331812_MASK, RTSX_DV331812_33); 1493 RTSX_CLR(sc, RTSX_SD_PAD_CTL, RTSX_SD_IO_USING_1V8); 1494 rtsx_rts5260_fill_driving(sc); 1495 1496 RTSX_BITOP(sc, RTSX_LDO_VCC_CFG1, RTSX_LDO_POW_SDVDD1_MASK, RTSX_LDO_POW_SDVDD1_OFF); 1497 RTSX_BITOP(sc, RTSX_LDO_CONFIG2, RTSX_DV331812_POWERON, RTSX_DV331812_POWEROFF); 1498 break; 1499 case RTSX_RTL8402: 1500 case RTSX_RTL8411: 1501 case RTSX_RTL8411B: 1502 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK, 1503 RTSX_BPP_POWER_OFF); 1504 RTSX_BITOP(sc, RTSX_LDO_CTL, RTSX_BPP_LDO_POWB, 1505 RTSX_BPP_LDO_SUSPEND); 1506 break; 1507 default: 1508 RTSX_CLR(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK); 1509 RTSX_SET(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_OFF); 1510 RTSX_CLR(sc, RTSX_CARD_PWR_CTL, RTSX_PMOS_STRG_800mA); 1511 break; 1512 } 1513 1514 /* Disable pull control. */ 1515 switch (sc->rtsx_device_id) { 1516 case RTSX_RTS5209: 1517 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, RTSX_PULL_CTL_DISABLE12); 1518 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_DISABLE12); 1519 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_DISABLE3); 1520 break; 1521 case RTSX_RTS5227: 1522 case RTSX_RTS522A: 1523 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_DISABLE12); 1524 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_DISABLE3); 1525 break; 1526 case RTSX_RTS5229: 1527 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_DISABLE12); 1528 if (sc->rtsx_flags & RTSX_F_VERSION_C) 1529 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_DISABLE3_TYPE_C); 1530 else 1531 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_DISABLE3); 1532 break; 1533 case RTSX_RTS525A: 1534 case RTSX_RTS5249: 1535 case RTSX_RTS5260: 1536 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0x66); 1537 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_DISABLE12); 1538 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_DISABLE3); 1539 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x55); 1540 break; 1541 case RTSX_RTL8402: 1542 case RTSX_RTL8411: 1543 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0x65); 1544 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0x55); 1545 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0x95); 1546 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x09); 1547 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL5, 0x05); 1548 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x04); 1549 break; 1550 case RTSX_RTL8411B: 1551 if (sc->rtsx_flags & RTSX_F_8411B_QFN48) { 1552 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0x55); 1553 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xf5); 1554 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x15); 1555 } else { 1556 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0x65); 1557 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0x55); 1558 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xd5); 1559 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x59); 1560 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL5, 0x55); 1561 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x15); 1562 } 1563 break; 1564 } 1565 1566 return (0); 1567 } 1568 1569 static int 1570 rtsx_bus_power_on(struct rtsx_softc *sc) 1571 { 1572 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 1573 device_printf(sc->rtsx_dev, "rtsx_bus_power_on()\n"); 1574 1575 /* Select SD card. */ 1576 RTSX_BITOP(sc, RTSX_CARD_SELECT, 0x07, RTSX_SD_MOD_SEL); 1577 RTSX_BITOP(sc, RTSX_CARD_SHARE_MODE, RTSX_CARD_SHARE_MASK, RTSX_CARD_SHARE_48_SD); 1578 1579 /* Enable SD clock. */ 1580 RTSX_BITOP(sc, RTSX_CARD_CLK_EN, RTSX_SD_CLK_EN, RTSX_SD_CLK_EN); 1581 1582 /* Enable pull control. */ 1583 switch (sc->rtsx_device_id) { 1584 case RTSX_RTS5209: 1585 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, RTSX_PULL_CTL_ENABLE12); 1586 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_ENABLE12); 1587 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_ENABLE3); 1588 break; 1589 case RTSX_RTS5227: 1590 case RTSX_RTS522A: 1591 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_ENABLE12); 1592 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_ENABLE3); 1593 break; 1594 case RTSX_RTS5229: 1595 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_ENABLE12); 1596 if (sc->rtsx_flags & RTSX_F_VERSION_C) 1597 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_ENABLE3_TYPE_C); 1598 else 1599 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_ENABLE3); 1600 break; 1601 case RTSX_RTS525A: 1602 case RTSX_RTS5249: 1603 case RTSX_RTS5260: 1604 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0x66); 1605 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_ENABLE12); 1606 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_ENABLE3); 1607 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0xaa); 1608 break; 1609 case RTSX_RTL8402: 1610 case RTSX_RTL8411: 1611 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0xaa); 1612 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0xaa); 1613 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xa9); 1614 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x09); 1615 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL5, 0x09); 1616 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x04); 1617 break; 1618 case RTSX_RTL8411B: 1619 if (sc->rtsx_flags & RTSX_F_8411B_QFN48) { 1620 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0xaa); 1621 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xf9); 1622 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x19); 1623 } else { 1624 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0xaa); 1625 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0xaa); 1626 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xd9); 1627 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x59); 1628 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL5, 0x55); 1629 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x15); 1630 } 1631 break; 1632 } 1633 1634 /* 1635 * To avoid a current peak, enable card power in two phases 1636 * with a delay in between. 1637 */ 1638 switch (sc->rtsx_device_id) { 1639 case RTSX_RTS5209: 1640 /* Partial power. */ 1641 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PARTIAL_PWR_ON); 1642 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, RTSX_LDO3318_VCC2); 1643 1644 DELAY(200); 1645 1646 /* Full power. */ 1647 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PWR_ON); 1648 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, RTSX_LDO3318_ON); 1649 break; 1650 case RTSX_RTS5227: 1651 case RTSX_RTS522A: 1652 /* Partial power. */ 1653 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PARTIAL_PWR_ON); 1654 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, RTSX_LDO3318_VCC1); 1655 1656 DELAY(20000); 1657 1658 /* Full power. */ 1659 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PWR_ON); 1660 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, 1661 RTSX_LDO3318_VCC1 | RTSX_LDO3318_VCC2); 1662 RTSX_BITOP(sc, RTSX_CARD_OE, RTSX_SD_OUTPUT_EN, RTSX_SD_OUTPUT_EN); 1663 RTSX_BITOP(sc, RTSX_CARD_OE, RTSX_MS_OUTPUT_EN, RTSX_MS_OUTPUT_EN); 1664 break; 1665 case RTSX_RTS5229: 1666 /* Partial power. */ 1667 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PARTIAL_PWR_ON); 1668 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, RTSX_LDO3318_VCC1); 1669 1670 DELAY(200); 1671 1672 /* Full power. */ 1673 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PWR_ON); 1674 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, 1675 RTSX_LDO3318_VCC1 | RTSX_LDO3318_VCC2); 1676 break; 1677 case RTSX_RTS525A: 1678 RTSX_BITOP(sc, RTSX_LDO_VCC_CFG1, RTSX_LDO_VCC_TUNE_MASK, RTSX_LDO_VCC_3V3); 1679 case RTSX_RTS5249: 1680 /* Partial power. */ 1681 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PARTIAL_PWR_ON); 1682 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, RTSX_LDO3318_VCC1); 1683 1684 DELAY(5000); 1685 1686 /* Full power. */ 1687 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PWR_ON); 1688 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, 1689 RTSX_LDO3318_VCC1 | RTSX_LDO3318_VCC2); 1690 break; 1691 case RTSX_RTS5260: 1692 RTSX_BITOP(sc, RTSX_LDO_CONFIG2, RTSX_DV331812_VDD1, RTSX_DV331812_VDD1); 1693 RTSX_BITOP(sc, RTSX_LDO_VCC_CFG0, RTSX_RTS5260_DVCC_TUNE_MASK, RTSX_RTS5260_DVCC_33); 1694 RTSX_BITOP(sc, RTSX_LDO_VCC_CFG1, RTSX_LDO_POW_SDVDD1_MASK, RTSX_LDO_POW_SDVDD1_ON); 1695 RTSX_BITOP(sc, RTSX_LDO_CONFIG2, RTSX_DV331812_POWERON, RTSX_DV331812_POWERON); 1696 1697 DELAY(20000); 1698 1699 RTSX_BITOP(sc, RTSX_SD_CFG1, RTSX_SD_MODE_MASK | RTSX_SD_ASYNC_FIFO_NOT_RST, 1700 RTSX_SD30_MODE | RTSX_SD_ASYNC_FIFO_NOT_RST); 1701 RTSX_BITOP(sc, RTSX_CLK_CTL, RTSX_CHANGE_CLK, RTSX_CLK_LOW_FREQ); 1702 RTSX_WRITE(sc, RTSX_CARD_CLK_SOURCE, 1703 RTSX_CRC_VAR_CLK0 | RTSX_SD30_FIX_CLK | RTSX_SAMPLE_VAR_CLK1); 1704 RTSX_CLR(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ); 1705 1706 /* Initialize SD_CFG1 register */ 1707 RTSX_WRITE(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_128 | RTSX_SD20_MODE); 1708 RTSX_WRITE(sc, RTSX_SD_SAMPLE_POINT_CTL, RTSX_SD20_RX_POS_EDGE); 1709 RTSX_CLR(sc, RTSX_SD_PUSH_POINT_CTL, 0xff); 1710 RTSX_BITOP(sc, RTSX_CARD_STOP, RTSX_SD_STOP | RTSX_SD_CLR_ERR, 1711 RTSX_SD_STOP | RTSX_SD_CLR_ERR); 1712 /* Reset SD_CFG3 register */ 1713 RTSX_CLR(sc, RTSX_SD_CFG3, RTSX_SD30_CLK_END_EN); 1714 RTSX_CLR(sc, RTSX_REG_SD_STOP_SDCLK_CFG, 1715 RTSX_SD30_CLK_STOP_CFG_EN | RTSX_SD30_CLK_STOP_CFG0 | RTSX_SD30_CLK_STOP_CFG1); 1716 RTSX_CLR(sc, RTSX_REG_PRE_RW_MODE, RTSX_EN_INFINITE_MODE); 1717 break; 1718 case RTSX_RTL8402: 1719 case RTSX_RTL8411: 1720 case RTSX_RTL8411B: 1721 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK, 1722 RTSX_BPP_POWER_5_PERCENT_ON); 1723 RTSX_BITOP(sc, RTSX_LDO_CTL, RTSX_BPP_LDO_POWB, 1724 RTSX_BPP_LDO_SUSPEND); 1725 DELAY(150); 1726 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK, 1727 RTSX_BPP_POWER_10_PERCENT_ON); 1728 DELAY(150); 1729 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK, 1730 RTSX_BPP_POWER_15_PERCENT_ON); 1731 DELAY(150); 1732 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK, 1733 RTSX_BPP_POWER_ON); 1734 RTSX_BITOP(sc, RTSX_LDO_CTL, RTSX_BPP_LDO_POWB, 1735 RTSX_BPP_LDO_ON); 1736 break; 1737 } 1738 1739 /* Enable SD card output. */ 1740 RTSX_WRITE(sc, RTSX_CARD_OE, RTSX_SD_OUTPUT_EN); 1741 1742 DELAY(200); 1743 1744 return (0); 1745 } 1746 1747 /* 1748 * Set but width. 1749 */ 1750 static int 1751 rtsx_set_bus_width(struct rtsx_softc *sc, enum mmc_bus_width width) 1752 { 1753 uint32_t bus_width; 1754 1755 switch (width) { 1756 case bus_width_1: 1757 bus_width = RTSX_BUS_WIDTH_1; 1758 break; 1759 case bus_width_4: 1760 bus_width = RTSX_BUS_WIDTH_4; 1761 break; 1762 case bus_width_8: 1763 bus_width = RTSX_BUS_WIDTH_8; 1764 break; 1765 default: 1766 return (MMC_ERR_INVALID); 1767 } 1768 RTSX_BITOP(sc, RTSX_SD_CFG1, RTSX_BUS_WIDTH_MASK, bus_width); 1769 1770 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) { 1771 char *busw[] = { 1772 "1 bit", 1773 "4 bits", 1774 "8 bits" 1775 }; 1776 device_printf(sc->rtsx_dev, "Setting bus width to %s\n", busw[bus_width]); 1777 } 1778 return (0); 1779 } 1780 1781 static int 1782 rtsx_set_sd_timing(struct rtsx_softc *sc, enum mmc_bus_timing timing) 1783 { 1784 if (timing == bus_timing_hs && sc->rtsx_force_timing) { 1785 timing = bus_timing_uhs_sdr50; 1786 sc->rtsx_ios_timing = timing; 1787 } 1788 1789 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 1790 device_printf(sc->rtsx_dev, "rtsx_set_sd_timing(%u)\n", timing); 1791 1792 switch (timing) { 1793 case bus_timing_uhs_sdr50: 1794 case bus_timing_uhs_sdr104: 1795 sc->rtsx_double_clk = false; 1796 sc->rtsx_vpclk = true; 1797 RTSX_BITOP(sc, RTSX_SD_CFG1, 0x0c | RTSX_SD_ASYNC_FIFO_NOT_RST, 1798 RTSX_SD30_MODE | RTSX_SD_ASYNC_FIFO_NOT_RST); 1799 RTSX_BITOP(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ, RTSX_CLK_LOW_FREQ); 1800 RTSX_WRITE(sc, RTSX_CARD_CLK_SOURCE, 1801 RTSX_CRC_VAR_CLK0 | RTSX_SD30_FIX_CLK | RTSX_SAMPLE_VAR_CLK1); 1802 RTSX_CLR(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ); 1803 break; 1804 case bus_timing_hs: 1805 RTSX_BITOP(sc, RTSX_SD_CFG1, RTSX_SD_MODE_MASK, RTSX_SD20_MODE); 1806 RTSX_BITOP(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ, RTSX_CLK_LOW_FREQ); 1807 RTSX_WRITE(sc, RTSX_CARD_CLK_SOURCE, 1808 RTSX_CRC_FIX_CLK | RTSX_SD30_VAR_CLK0 | RTSX_SAMPLE_VAR_CLK1); 1809 RTSX_CLR(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ); 1810 1811 RTSX_BITOP(sc, RTSX_SD_PUSH_POINT_CTL, 1812 RTSX_SD20_TX_SEL_MASK, RTSX_SD20_TX_14_AHEAD); 1813 RTSX_BITOP(sc, RTSX_SD_SAMPLE_POINT_CTL, 1814 RTSX_SD20_RX_SEL_MASK, RTSX_SD20_RX_14_DELAY); 1815 break; 1816 default: 1817 RTSX_BITOP(sc, RTSX_SD_CFG1, RTSX_SD_MODE_MASK, RTSX_SD20_MODE); 1818 RTSX_BITOP(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ, RTSX_CLK_LOW_FREQ); 1819 RTSX_WRITE(sc, RTSX_CARD_CLK_SOURCE, 1820 RTSX_CRC_FIX_CLK | RTSX_SD30_VAR_CLK0 | RTSX_SAMPLE_VAR_CLK1); 1821 RTSX_CLR(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ); 1822 1823 RTSX_WRITE(sc, RTSX_SD_PUSH_POINT_CTL, RTSX_SD20_TX_NEG_EDGE); 1824 RTSX_BITOP(sc, RTSX_SD_SAMPLE_POINT_CTL, 1825 RTSX_SD20_RX_SEL_MASK, RTSX_SD20_RX_POS_EDGE); 1826 break; 1827 } 1828 1829 return (0); 1830 } 1831 1832 /* 1833 * Set or change SDCLK frequency or disable the SD clock. 1834 * Return zero on success. 1835 */ 1836 static int 1837 rtsx_set_sd_clock(struct rtsx_softc *sc, uint32_t freq) 1838 { 1839 uint8_t clk; 1840 uint8_t clk_divider, n, div, mcu; 1841 int error = 0; 1842 1843 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 1844 device_printf(sc->rtsx_dev, "rtsx_set_sd_clock(%u)\n", freq); 1845 1846 if (freq == RTSX_SDCLK_OFF) { 1847 error = rtsx_stop_sd_clock(sc); 1848 return error; 1849 } 1850 1851 sc->rtsx_ssc_depth = RTSX_SSC_DEPTH_500K; 1852 sc->rtsx_discovery_mode = (freq <= 1000000) ? true : false; 1853 1854 if (sc->rtsx_discovery_mode) { 1855 /* We use 250k(around) here, in discovery stage. */ 1856 clk_divider = RTSX_CLK_DIVIDE_128; 1857 freq = 30000000; 1858 } else { 1859 clk_divider = RTSX_CLK_DIVIDE_0; 1860 } 1861 RTSX_BITOP(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK, clk_divider); 1862 1863 freq /= 1000000; 1864 if (sc->rtsx_discovery_mode || !sc->rtsx_double_clk) 1865 clk = freq; 1866 else 1867 clk = freq * 2; 1868 1869 switch (sc->rtsx_device_id) { 1870 case RTSX_RTL8402: 1871 case RTSX_RTL8411: 1872 case RTSX_RTL8411B: 1873 n = clk * 4 / 5 - 2; 1874 break; 1875 default: 1876 n = clk - 2; 1877 break; 1878 } 1879 if ((clk <= 2) || (n > RTSX_MAX_DIV_N)) 1880 return (MMC_ERR_INVALID); 1881 1882 mcu = 125 / clk + 3; 1883 if (mcu > 15) 1884 mcu = 15; 1885 1886 /* Make sure that the SSC clock div_n is not less than RTSX_MIN_DIV_N. */ 1887 div = RTSX_CLK_DIV_1; 1888 while ((n < RTSX_MIN_DIV_N) && (div < RTSX_CLK_DIV_8)) { 1889 switch (sc->rtsx_device_id) { 1890 case RTSX_RTL8402: 1891 case RTSX_RTL8411: 1892 case RTSX_RTL8411B: 1893 n = (((n + 2) * 5 / 4) * 2) * 4 / 5 - 2; 1894 break; 1895 default: 1896 n = (n + 2) * 2 - 2; 1897 break; 1898 } 1899 div++; 1900 } 1901 1902 if (sc->rtsx_double_clk && sc->rtsx_ssc_depth > 1) 1903 sc->rtsx_ssc_depth -= 1; 1904 1905 if (div > RTSX_CLK_DIV_1) { 1906 if (sc->rtsx_ssc_depth > (div - 1)) 1907 sc->rtsx_ssc_depth -= (div - 1); 1908 else 1909 sc->rtsx_ssc_depth = RTSX_SSC_DEPTH_4M; 1910 } 1911 1912 /* Enable SD clock. */ 1913 error = rtsx_switch_sd_clock(sc, clk, n, div, mcu); 1914 1915 return (error); 1916 } 1917 1918 static int 1919 rtsx_stop_sd_clock(struct rtsx_softc *sc) 1920 { 1921 RTSX_CLR(sc, RTSX_CARD_CLK_EN, RTSX_CARD_CLK_EN_ALL); 1922 RTSX_SET(sc, RTSX_SD_BUS_STAT, RTSX_SD_CLK_FORCE_STOP); 1923 1924 return (0); 1925 } 1926 1927 static int 1928 rtsx_switch_sd_clock(struct rtsx_softc *sc, uint8_t clk, uint8_t n, uint8_t div, uint8_t mcu) 1929 { 1930 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) { 1931 device_printf(sc->rtsx_dev, "rtsx_switch_sd_clock() - discovery-mode is %s, ssc_depth: %d\n", 1932 (sc->rtsx_discovery_mode) ? "true" : "false", sc->rtsx_ssc_depth); 1933 device_printf(sc->rtsx_dev, "rtsx_switch_sd_clock() - clk: %d, n: %d, div: %d, mcu: %d\n", 1934 clk, n, div, mcu); 1935 } 1936 1937 RTSX_BITOP(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ, RTSX_CLK_LOW_FREQ); 1938 RTSX_WRITE(sc, RTSX_CLK_DIV, (div << 4) | mcu); 1939 RTSX_CLR(sc, RTSX_SSC_CTL1, RTSX_RSTB); 1940 RTSX_BITOP(sc, RTSX_SSC_CTL2, RTSX_SSC_DEPTH_MASK, sc->rtsx_ssc_depth); 1941 RTSX_WRITE(sc, RTSX_SSC_DIV_N_0, n); 1942 RTSX_BITOP(sc, RTSX_SSC_CTL1, RTSX_RSTB, RTSX_RSTB); 1943 if (sc->rtsx_vpclk) { 1944 RTSX_CLR(sc, RTSX_SD_VPCLK0_CTL, RTSX_PHASE_NOT_RESET); 1945 RTSX_BITOP(sc, RTSX_SD_VPCLK0_CTL, RTSX_PHASE_NOT_RESET, RTSX_PHASE_NOT_RESET); 1946 } 1947 1948 /* Wait SSC clock stable. */ 1949 DELAY(200); 1950 1951 RTSX_CLR(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ); 1952 1953 return (0); 1954 } 1955 1956 #ifndef MMCCAM 1957 static void 1958 rtsx_sd_change_tx_phase(struct rtsx_softc *sc, uint8_t sample_point) 1959 { 1960 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 1961 device_printf(sc->rtsx_dev, "rtsx_sd_change_tx_phase() - sample_point: %d\n", sample_point); 1962 1963 rtsx_write(sc, RTSX_CLK_CTL, RTSX_CHANGE_CLK, RTSX_CHANGE_CLK); 1964 rtsx_write(sc, RTSX_SD_VPCLK0_CTL, RTSX_PHASE_SELECT_MASK, sample_point); 1965 rtsx_write(sc, RTSX_SD_VPCLK0_CTL, RTSX_PHASE_NOT_RESET, 0); 1966 rtsx_write(sc, RTSX_SD_VPCLK0_CTL, RTSX_PHASE_NOT_RESET, RTSX_PHASE_NOT_RESET); 1967 rtsx_write(sc, RTSX_CLK_CTL, RTSX_CHANGE_CLK, 0); 1968 rtsx_write(sc, RTSX_SD_CFG1, RTSX_SD_ASYNC_FIFO_NOT_RST, 0); 1969 } 1970 1971 static void 1972 rtsx_sd_change_rx_phase(struct rtsx_softc *sc, uint8_t sample_point) 1973 { 1974 if (sc->rtsx_debug_mask & RTSX_DEBUG_TUNING) 1975 device_printf(sc->rtsx_dev, "rtsx_sd_change_rx_phase() - sample_point: %d\n", sample_point); 1976 1977 rtsx_write(sc, RTSX_CLK_CTL, RTSX_CHANGE_CLK, RTSX_CHANGE_CLK); 1978 rtsx_write(sc, RTSX_SD_VPCLK1_CTL, RTSX_PHASE_SELECT_MASK, sample_point); 1979 rtsx_write(sc, RTSX_SD_VPCLK1_CTL, RTSX_PHASE_NOT_RESET, 0); 1980 rtsx_write(sc, RTSX_SD_VPCLK1_CTL, RTSX_PHASE_NOT_RESET, RTSX_PHASE_NOT_RESET); 1981 rtsx_write(sc, RTSX_CLK_CTL, RTSX_CHANGE_CLK, 0); 1982 rtsx_write(sc, RTSX_SD_CFG1, RTSX_SD_ASYNC_FIFO_NOT_RST, 0); 1983 } 1984 1985 static void 1986 rtsx_sd_tuning_rx_phase(struct rtsx_softc *sc, uint32_t *phase_map) 1987 { 1988 uint32_t raw_phase_map = 0; 1989 int i; 1990 int error; 1991 1992 for (i = 0; i < RTSX_RX_PHASE_MAX; i++) { 1993 error = rtsx_sd_tuning_rx_cmd(sc, (uint8_t)i); 1994 if (error == 0) 1995 raw_phase_map |= 1 << i; 1996 } 1997 if (phase_map != NULL) 1998 *phase_map = raw_phase_map; 1999 } 2000 2001 static int 2002 rtsx_sd_tuning_rx_cmd(struct rtsx_softc *sc, uint8_t sample_point) 2003 { 2004 struct mmc_request req = {}; 2005 struct mmc_command cmd = {}; 2006 int error = 0; 2007 2008 cmd.opcode = MMC_SEND_TUNING_BLOCK; 2009 cmd.arg = 0; 2010 req.cmd = &cmd; 2011 2012 RTSX_LOCK(sc); 2013 2014 sc->rtsx_req = &req; 2015 2016 rtsx_sd_change_rx_phase(sc, sample_point); 2017 2018 rtsx_write(sc, RTSX_SD_CFG3, RTSX_SD_RSP_80CLK_TIMEOUT_EN, 2019 RTSX_SD_RSP_80CLK_TIMEOUT_EN); 2020 2021 rtsx_init_cmd(sc, &cmd); 2022 rtsx_set_cmd_data_len(sc, 1, 0x40); 2023 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 0xff, 2024 RTSX_SD_CALCULATE_CRC7 | RTSX_SD_CHECK_CRC16 | 2025 RTSX_SD_NO_WAIT_BUSY_END | RTSX_SD_CHECK_CRC7 | RTSX_SD_RSP_LEN_6); 2026 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 2027 0xff, RTSX_TM_AUTO_TUNING | RTSX_SD_TRANSFER_START); 2028 rtsx_push_cmd(sc, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, 2029 RTSX_SD_TRANSFER_END, RTSX_SD_TRANSFER_END); 2030 2031 /* Set interrupt post processing */ 2032 sc->rtsx_intr_trans_ok = rtsx_sd_tuning_rx_cmd_wakeup; 2033 sc->rtsx_intr_trans_ko = rtsx_sd_tuning_rx_cmd_wakeup; 2034 2035 /* Run the command queue. */ 2036 rtsx_send_cmd(sc); 2037 2038 error = rtsx_sd_tuning_rx_cmd_wait(sc, &cmd); 2039 2040 if (error) { 2041 if (sc->rtsx_debug_mask & RTSX_DEBUG_TUNING) 2042 device_printf(sc->rtsx_dev, "rtsx_sd_tuning_rx_cmd() - error: %d\n", error); 2043 rtsx_sd_wait_data_idle(sc); 2044 rtsx_clear_error(sc); 2045 } 2046 rtsx_write(sc, RTSX_SD_CFG3, RTSX_SD_RSP_80CLK_TIMEOUT_EN, 0); 2047 2048 sc->rtsx_req = NULL; 2049 2050 RTSX_UNLOCK(sc); 2051 2052 return (error); 2053 } 2054 2055 static int 2056 rtsx_sd_tuning_rx_cmd_wait(struct rtsx_softc *sc, struct mmc_command *cmd) 2057 { 2058 int status; 2059 int mask = RTSX_TRANS_OK_INT | RTSX_TRANS_FAIL_INT; 2060 2061 status = sc->rtsx_intr_status & mask; 2062 while (status == 0) { 2063 if (msleep(&sc->rtsx_intr_status, &sc->rtsx_mtx, 0, "rtsxintr", sc->rtsx_timeout_cmd) == EWOULDBLOCK) { 2064 cmd->error = MMC_ERR_TIMEOUT; 2065 return (MMC_ERR_TIMEOUT); 2066 } 2067 status = sc->rtsx_intr_status & mask; 2068 } 2069 return (cmd->error); 2070 } 2071 2072 static void 2073 rtsx_sd_tuning_rx_cmd_wakeup(struct rtsx_softc *sc) 2074 { 2075 wakeup(&sc->rtsx_intr_status); 2076 } 2077 2078 static void 2079 rtsx_sd_wait_data_idle(struct rtsx_softc *sc) 2080 { 2081 int i; 2082 uint8_t val; 2083 2084 for (i = 0; i < 100; i++) { 2085 rtsx_read(sc, RTSX_SD_DATA_STATE, &val); 2086 if (val & RTSX_SD_DATA_IDLE) 2087 return; 2088 DELAY(100); 2089 } 2090 } 2091 2092 static uint8_t 2093 rtsx_sd_search_final_rx_phase(struct rtsx_softc *sc, uint32_t phase_map) 2094 { 2095 int start = 0, len = 0; 2096 int start_final = 0, len_final = 0; 2097 uint8_t final_phase = 0xff; 2098 2099 while (start < RTSX_RX_PHASE_MAX) { 2100 len = rtsx_sd_get_rx_phase_len(phase_map, start); 2101 if (len_final < len) { 2102 start_final = start; 2103 len_final = len; 2104 } 2105 start += len ? len : 1; 2106 } 2107 2108 final_phase = (start_final + len_final / 2) % RTSX_RX_PHASE_MAX; 2109 2110 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 2111 device_printf(sc->rtsx_dev, 2112 "rtsx_sd_search_final_rx_phase() - phase_map: %x, start_final: %d, len_final: %d, final_phase: %d\n", 2113 phase_map, start_final, len_final, final_phase); 2114 2115 return final_phase; 2116 } 2117 2118 static int 2119 rtsx_sd_get_rx_phase_len(uint32_t phase_map, int start_bit) 2120 { 2121 int i; 2122 2123 for (i = 0; i < RTSX_RX_PHASE_MAX; i++) { 2124 if ((phase_map & (1 << (start_bit + i) % RTSX_RX_PHASE_MAX)) == 0) 2125 return i; 2126 } 2127 return RTSX_RX_PHASE_MAX; 2128 } 2129 #endif /* !MMCCAM */ 2130 2131 #if 0 /* For led */ 2132 static int 2133 rtsx_led_enable(struct rtsx_softc *sc) 2134 { 2135 switch (sc->rtsx_device_id) { 2136 case RTSX_RTS5209: 2137 RTSX_CLR(sc, RTSX_CARD_GPIO, RTSX_CARD_GPIO_LED_OFF); 2138 RTSX_WRITE(sc, RTSX_CARD_AUTO_BLINK, 2139 RTSX_LED_BLINK_EN | RTSX_LED_BLINK_SPEED); 2140 break; 2141 case RTSX_RTL8411B: 2142 RTSX_CLR(sc, RTSX_GPIO_CTL, 0x01); 2143 RTSX_WRITE(sc, RTSX_CARD_AUTO_BLINK, 2144 RTSX_LED_BLINK_EN | RTSX_LED_BLINK_SPEED); 2145 break; 2146 default: 2147 RTSX_SET(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON); 2148 RTSX_SET(sc, RTSX_OLT_LED_CTL, RTSX_OLT_LED_AUTOBLINK); 2149 break; 2150 } 2151 2152 return (0); 2153 } 2154 2155 static int 2156 rtsx_led_disable(struct rtsx_softc *sc) 2157 { 2158 switch (sc->rtsx_device_id) { 2159 case RTSX_RTS5209: 2160 RTSX_CLR(sc, RTSX_CARD_AUTO_BLINK, RTSX_LED_BLINK_EN); 2161 RTSX_WRITE(sc, RTSX_CARD_GPIO, RTSX_CARD_GPIO_LED_OFF); 2162 break; 2163 case RTSX_RTL8411B: 2164 RTSX_CLR(sc, RTSX_CARD_AUTO_BLINK, RTSX_LED_BLINK_EN); 2165 RTSX_SET(sc, RTSX_GPIO_CTL, 0x01); 2166 break; 2167 default: 2168 RTSX_CLR(sc, RTSX_OLT_LED_CTL, RTSX_OLT_LED_AUTOBLINK); 2169 RTSX_CLR(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON); 2170 break; 2171 } 2172 2173 return (0); 2174 } 2175 #endif /* For led */ 2176 2177 static uint8_t 2178 rtsx_response_type(uint16_t mmc_rsp) 2179 { 2180 int i; 2181 struct rsp_type { 2182 uint16_t mmc_rsp; 2183 uint8_t rtsx_rsp; 2184 } rsp_types[] = { 2185 { MMC_RSP_NONE, RTSX_SD_RSP_TYPE_R0 }, 2186 { MMC_RSP_R1, RTSX_SD_RSP_TYPE_R1 }, 2187 { MMC_RSP_R1B, RTSX_SD_RSP_TYPE_R1B }, 2188 { MMC_RSP_R2, RTSX_SD_RSP_TYPE_R2 }, 2189 { MMC_RSP_R3, RTSX_SD_RSP_TYPE_R3 }, 2190 { MMC_RSP_R4, RTSX_SD_RSP_TYPE_R4 }, 2191 { MMC_RSP_R5, RTSX_SD_RSP_TYPE_R5 }, 2192 { MMC_RSP_R6, RTSX_SD_RSP_TYPE_R6 }, 2193 { MMC_RSP_R7, RTSX_SD_RSP_TYPE_R7 } 2194 }; 2195 2196 for (i = 0; i < nitems(rsp_types); i++) { 2197 if (mmc_rsp == rsp_types[i].mmc_rsp) 2198 return (rsp_types[i].rtsx_rsp); 2199 } 2200 2201 return (0); 2202 } 2203 2204 /* 2205 * Init command buffer with SD command index and argument. 2206 */ 2207 static void 2208 rtsx_init_cmd(struct rtsx_softc *sc, struct mmc_command *cmd) 2209 { 2210 sc->rtsx_cmd_index = 0; 2211 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CMD0, 2212 0xff, RTSX_SD_CMD_START | cmd->opcode); 2213 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CMD1, 2214 0xff, cmd->arg >> 24); 2215 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CMD2, 2216 0xff, cmd->arg >> 16); 2217 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CMD3, 2218 0xff, cmd->arg >> 8); 2219 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CMD4, 2220 0xff, cmd->arg); 2221 } 2222 2223 /* 2224 * Append a properly encoded host command to the host command buffer. 2225 */ 2226 static void 2227 rtsx_push_cmd(struct rtsx_softc *sc, uint8_t cmd, uint16_t reg, 2228 uint8_t mask, uint8_t data) 2229 { 2230 KASSERT(sc->rtsx_cmd_index < RTSX_HOSTCMD_MAX, 2231 ("rtsx: Too many host commands (%d)\n", sc->rtsx_cmd_index)); 2232 2233 uint32_t *cmd_buffer = (uint32_t *)(sc->rtsx_cmd_dmamem); 2234 cmd_buffer[sc->rtsx_cmd_index++] = 2235 htole32((uint32_t)(cmd & 0x3) << 30) | 2236 ((uint32_t)(reg & 0x3fff) << 16) | 2237 ((uint32_t)(mask) << 8) | 2238 ((uint32_t)data); 2239 } 2240 2241 /* 2242 * Queue commands to configure data transfer size. 2243 */ 2244 static void 2245 rtsx_set_cmd_data_len(struct rtsx_softc *sc, uint16_t block_cnt, uint16_t byte_cnt) 2246 { 2247 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BLOCK_CNT_L, 2248 0xff, block_cnt & 0xff); 2249 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BLOCK_CNT_H, 2250 0xff, block_cnt >> 8); 2251 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BYTE_CNT_L, 2252 0xff, byte_cnt & 0xff); 2253 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BYTE_CNT_H, 2254 0xff, byte_cnt >> 8); 2255 } 2256 2257 /* 2258 * Run the command queue. 2259 */ 2260 static void 2261 rtsx_send_cmd(struct rtsx_softc *sc) 2262 { 2263 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 2264 device_printf(sc->rtsx_dev, "rtsx_send_cmd()\n"); 2265 2266 sc->rtsx_intr_status = 0; 2267 2268 /* Sync command DMA buffer. */ 2269 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_PREREAD); 2270 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_PREWRITE); 2271 2272 /* Tell the chip where the command buffer is and run the commands. */ 2273 WRITE4(sc, RTSX_HCBAR, (uint32_t)sc->rtsx_cmd_buffer); 2274 WRITE4(sc, RTSX_HCBCTLR, 2275 ((sc->rtsx_cmd_index * 4) & 0x00ffffff) | RTSX_START_CMD | RTSX_HW_AUTO_RSP); 2276 } 2277 2278 /* 2279 * Stop previous command. 2280 */ 2281 static void 2282 rtsx_stop_cmd(struct rtsx_softc *sc) 2283 { 2284 /* Stop command transfer. */ 2285 WRITE4(sc, RTSX_HCBCTLR, RTSX_STOP_CMD); 2286 2287 /* Stop DMA transfer. */ 2288 WRITE4(sc, RTSX_HDBCTLR, RTSX_STOP_DMA); 2289 2290 switch (sc->rtsx_device_id) { 2291 case RTSX_RTS5260: 2292 rtsx_write(sc, RTSX_RTS5260_DMA_RST_CTL_0, 2293 RTSX_RTS5260_DMA_RST | RTSX_RTS5260_ADMA3_RST, 2294 RTSX_RTS5260_DMA_RST | RTSX_RTS5260_ADMA3_RST); 2295 rtsx_write(sc, RTSX_RBCTL, RTSX_RB_FLUSH, RTSX_RB_FLUSH); 2296 break; 2297 default: 2298 rtsx_write(sc, RTSX_DMACTL, RTSX_DMA_RST, RTSX_DMA_RST); 2299 2300 rtsx_write(sc, RTSX_RBCTL, RTSX_RB_FLUSH, RTSX_RB_FLUSH); 2301 break; 2302 } 2303 } 2304 2305 /* 2306 * Clear error. 2307 */ 2308 static void 2309 rtsx_clear_error(struct rtsx_softc *sc) 2310 { 2311 /* Clear error. */ 2312 rtsx_write(sc, RTSX_CARD_STOP, RTSX_SD_STOP | RTSX_SD_CLR_ERR, 2313 RTSX_SD_STOP | RTSX_SD_CLR_ERR); 2314 } 2315 2316 /* 2317 * Signal end of request to mmc/mmcsd. 2318 */ 2319 static void 2320 rtsx_req_done(struct rtsx_softc *sc) 2321 { 2322 #ifdef MMCCAM 2323 union ccb *ccb; 2324 #endif /* MMCCAM */ 2325 struct mmc_request *req; 2326 2327 req = sc->rtsx_req; 2328 if (req->cmd->error == MMC_ERR_NONE) { 2329 if (req->cmd->opcode == MMC_READ_SINGLE_BLOCK || 2330 req->cmd->opcode == MMC_READ_MULTIPLE_BLOCK) 2331 sc->rtsx_read_count++; 2332 else if (req->cmd->opcode == MMC_WRITE_BLOCK || 2333 req->cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK) 2334 sc->rtsx_write_count++; 2335 } else { 2336 rtsx_clear_error(sc); 2337 } 2338 callout_stop(&sc->rtsx_timeout_callout); 2339 sc->rtsx_req = NULL; 2340 #ifdef MMCCAM 2341 ccb = sc->rtsx_ccb; 2342 sc->rtsx_ccb = NULL; 2343 ccb->ccb_h.status = (req->cmd->error == 0 ? CAM_REQ_CMP : CAM_REQ_CMP_ERR); 2344 xpt_done(ccb); 2345 #else /* !MMCCAM */ 2346 req->done(req); 2347 #endif /* MMCCAM */ 2348 } 2349 2350 /* 2351 * Send request. 2352 */ 2353 static int 2354 rtsx_send_req(struct rtsx_softc *sc, struct mmc_command *cmd) 2355 { 2356 uint8_t rsp_type; 2357 uint16_t reg; 2358 2359 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 2360 device_printf(sc->rtsx_dev, "rtsx_send_req() - CMD%d\n", cmd->opcode); 2361 2362 /* Convert response type. */ 2363 rsp_type = rtsx_response_type(cmd->flags & MMC_RSP_MASK); 2364 if (rsp_type == 0) { 2365 device_printf(sc->rtsx_dev, "Unknown rsp_type: 0x%lx\n", (cmd->flags & MMC_RSP_MASK)); 2366 cmd->error = MMC_ERR_INVALID; 2367 return (MMC_ERR_INVALID); 2368 } 2369 2370 rtsx_init_cmd(sc, cmd); 2371 2372 /* Queue command to set response type. */ 2373 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 0xff, rsp_type); 2374 2375 /* Use the ping-pong buffer (cmd buffer) for commands which do not transfer data. */ 2376 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_CARD_DATA_SOURCE, 2377 0x01, RTSX_PINGPONG_BUFFER); 2378 2379 /* Queue commands to perform SD transfer. */ 2380 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 2381 0xff, RTSX_TM_CMD_RSP | RTSX_SD_TRANSFER_START); 2382 rtsx_push_cmd(sc, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, 2383 RTSX_SD_TRANSFER_END|RTSX_SD_STAT_IDLE, 2384 RTSX_SD_TRANSFER_END|RTSX_SD_STAT_IDLE); 2385 2386 /* If needed queue commands to read back card status response. */ 2387 if (rsp_type == RTSX_SD_RSP_TYPE_R2) { 2388 /* Read data from ping-pong buffer. */ 2389 for (reg = RTSX_PPBUF_BASE2; reg < RTSX_PPBUF_BASE2 + 16; reg++) 2390 rtsx_push_cmd(sc, RTSX_READ_REG_CMD, reg, 0, 0); 2391 } else if (rsp_type != RTSX_SD_RSP_TYPE_R0) { 2392 /* Read data from SD_CMDx registers. */ 2393 for (reg = RTSX_SD_CMD0; reg <= RTSX_SD_CMD4; reg++) 2394 rtsx_push_cmd(sc, RTSX_READ_REG_CMD, reg, 0, 0); 2395 } 2396 rtsx_push_cmd(sc, RTSX_READ_REG_CMD, RTSX_SD_STAT1, 0, 0); 2397 2398 /* Set transfer OK function. */ 2399 if (sc->rtsx_intr_trans_ok == NULL) 2400 sc->rtsx_intr_trans_ok = rtsx_ret_resp; 2401 2402 /* Run the command queue. */ 2403 rtsx_send_cmd(sc); 2404 2405 return (0); 2406 } 2407 2408 /* 2409 * Return response of previous command (case cmd->data == NULL) and complete resquest. 2410 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2411 */ 2412 static void 2413 rtsx_ret_resp(struct rtsx_softc *sc) 2414 { 2415 struct mmc_command *cmd; 2416 2417 cmd = sc->rtsx_req->cmd; 2418 rtsx_set_resp(sc, cmd); 2419 rtsx_req_done(sc); 2420 } 2421 2422 /* 2423 * Set response of previous command. 2424 */ 2425 static void 2426 rtsx_set_resp(struct rtsx_softc *sc, struct mmc_command *cmd) 2427 { 2428 uint8_t rsp_type; 2429 2430 rsp_type = rtsx_response_type(cmd->flags & MMC_RSP_MASK); 2431 2432 /* Sync command DMA buffer. */ 2433 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTREAD); 2434 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTWRITE); 2435 2436 /* Copy card response into mmc response buffer. */ 2437 if (ISSET(cmd->flags, MMC_RSP_PRESENT)) { 2438 uint32_t *cmd_buffer = (uint32_t *)(sc->rtsx_cmd_dmamem); 2439 2440 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) { 2441 device_printf(sc->rtsx_dev, "cmd_buffer: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", 2442 cmd_buffer[0], cmd_buffer[1], cmd_buffer[2], cmd_buffer[3], cmd_buffer[4]); 2443 } 2444 2445 if (rsp_type == RTSX_SD_RSP_TYPE_R2) { 2446 /* First byte is CHECK_REG_CMD return value, skip it. */ 2447 unsigned char *ptr = (unsigned char *)cmd_buffer + 1; 2448 int i; 2449 2450 /* 2451 * The controller offloads the last byte {CRC-7, end bit 1} 2452 * of response type R2. Assign dummy CRC, 0, and end bit to this 2453 * byte (ptr[16], goes into the LSB of resp[3] later). 2454 */ 2455 ptr[16] = 0x01; 2456 /* The second byte is the status of response, skip it. */ 2457 for (i = 0; i < 4; i++) 2458 cmd->resp[i] = be32dec(ptr + 1 + i * 4); 2459 } else { 2460 /* 2461 * First byte is CHECK_REG_CMD return value, second 2462 * one is the command op code -- we skip those. 2463 */ 2464 cmd->resp[0] = 2465 ((be32toh(cmd_buffer[0]) & 0x0000ffff) << 16) | 2466 ((be32toh(cmd_buffer[1]) & 0xffff0000) >> 16); 2467 } 2468 2469 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 2470 device_printf(sc->rtsx_dev, "cmd->resp: 0x%08x 0x%08x 0x%08x 0x%08x\n", 2471 cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); 2472 } 2473 } 2474 2475 /* 2476 * Use the ping-pong buffer (cmd buffer) for transfer <= 512 bytes. 2477 */ 2478 static int 2479 rtsx_xfer_short(struct rtsx_softc *sc, struct mmc_command *cmd) 2480 { 2481 int read; 2482 2483 if (cmd->data == NULL || cmd->data->len == 0) { 2484 cmd->error = MMC_ERR_INVALID; 2485 return (MMC_ERR_INVALID); 2486 } 2487 cmd->data->xfer_len = (cmd->data->len > RTSX_MAX_DATA_BLKLEN) ? 2488 RTSX_MAX_DATA_BLKLEN : cmd->data->len; 2489 2490 read = ISSET(cmd->data->flags, MMC_DATA_READ); 2491 2492 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 2493 device_printf(sc->rtsx_dev, "rtsx_xfer_short() - %s xfer: %ld bytes with block size %ld\n", 2494 read ? "Read" : "Write", 2495 (unsigned long)cmd->data->len, (unsigned long)cmd->data->xfer_len); 2496 2497 if (cmd->data->len > 512) { 2498 device_printf(sc->rtsx_dev, "rtsx_xfer_short() - length too large: %ld > 512\n", 2499 (unsigned long)cmd->data->len); 2500 cmd->error = MMC_ERR_INVALID; 2501 return (MMC_ERR_INVALID); 2502 } 2503 2504 if (read) { 2505 if (sc->rtsx_discovery_mode) 2506 rtsx_write(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK, RTSX_CLK_DIVIDE_0); 2507 2508 rtsx_init_cmd(sc, cmd); 2509 2510 /* Queue commands to configure data transfer size. */ 2511 rtsx_set_cmd_data_len(sc, cmd->data->len / cmd->data->xfer_len, cmd->data->xfer_len); 2512 2513 /* From Linux: rtsx_pci_sdmmc.c sd_read_data(). */ 2514 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 0xff, 2515 RTSX_SD_CALCULATE_CRC7 | RTSX_SD_CHECK_CRC16 | 2516 RTSX_SD_NO_WAIT_BUSY_END | RTSX_SD_CHECK_CRC7 | RTSX_SD_RSP_LEN_6); 2517 2518 /* Use the ping-pong buffer (cmd buffer). */ 2519 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_CARD_DATA_SOURCE, 2520 0x01, RTSX_PINGPONG_BUFFER); 2521 2522 /* Queue commands to perform SD transfer. */ 2523 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 2524 0xff, RTSX_TM_NORMAL_READ | RTSX_SD_TRANSFER_START); 2525 rtsx_push_cmd(sc, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, 2526 RTSX_SD_TRANSFER_END, RTSX_SD_TRANSFER_END); 2527 2528 /* Set transfer OK function. */ 2529 sc->rtsx_intr_trans_ok = rtsx_ask_ppbuf_part1; 2530 2531 /* Run the command queue. */ 2532 rtsx_send_cmd(sc); 2533 } else { 2534 /* Set transfer OK function. */ 2535 sc->rtsx_intr_trans_ok = rtsx_put_ppbuf_part1; 2536 2537 /* Run the command queue. */ 2538 rtsx_send_req(sc, cmd); 2539 } 2540 2541 return (0); 2542 } 2543 2544 /* 2545 * Use the ping-pong buffer (cmd buffer) for the transfer - first part <= 256 bytes. 2546 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2547 */ 2548 static void 2549 rtsx_ask_ppbuf_part1(struct rtsx_softc *sc) 2550 { 2551 struct mmc_command *cmd; 2552 uint16_t reg = RTSX_PPBUF_BASE2; 2553 int len; 2554 int i; 2555 2556 cmd = sc->rtsx_req->cmd; 2557 len = (cmd->data->len > RTSX_HOSTCMD_MAX) ? RTSX_HOSTCMD_MAX : cmd->data->len; 2558 2559 sc->rtsx_cmd_index = 0; 2560 for (i = 0; i < len; i++) { 2561 rtsx_push_cmd(sc, RTSX_READ_REG_CMD, reg++, 0, 0); 2562 } 2563 2564 /* Set transfer OK function. */ 2565 sc->rtsx_intr_trans_ok = rtsx_get_ppbuf_part1; 2566 2567 /* Run the command queue. */ 2568 rtsx_send_cmd(sc); 2569 } 2570 2571 /* 2572 * Get the data from the ping-pong buffer (cmd buffer) - first part <= 256 bytes. 2573 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2574 */ 2575 static void 2576 rtsx_get_ppbuf_part1(struct rtsx_softc *sc) 2577 { 2578 struct mmc_command *cmd; 2579 uint8_t *ptr; 2580 int len; 2581 2582 cmd = sc->rtsx_req->cmd; 2583 ptr = cmd->data->data; 2584 len = (cmd->data->len > RTSX_HOSTCMD_MAX) ? RTSX_HOSTCMD_MAX : cmd->data->len; 2585 2586 /* Sync command DMA buffer. */ 2587 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTREAD); 2588 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTWRITE); 2589 2590 memcpy(ptr, sc->rtsx_cmd_dmamem, len); 2591 2592 len = (cmd->data->len > RTSX_HOSTCMD_MAX) ? cmd->data->len - RTSX_HOSTCMD_MAX : 0; 2593 2594 /* Use the ping-pong buffer (cmd buffer) for the transfer - second part > 256 bytes. */ 2595 if (len > 0) { 2596 uint16_t reg = RTSX_PPBUF_BASE2 + RTSX_HOSTCMD_MAX; 2597 int i; 2598 2599 sc->rtsx_cmd_index = 0; 2600 for (i = 0; i < len; i++) { 2601 rtsx_push_cmd(sc, RTSX_READ_REG_CMD, reg++, 0, 0); 2602 } 2603 2604 /* Set transfer OK function. */ 2605 sc->rtsx_intr_trans_ok = rtsx_get_ppbuf_part2; 2606 2607 /* Run the command queue. */ 2608 rtsx_send_cmd(sc); 2609 } else { 2610 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD && cmd->opcode == ACMD_SEND_SCR) { 2611 uint8_t *ptr = cmd->data->data; 2612 device_printf(sc->rtsx_dev, "SCR: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n", 2613 ptr[0], ptr[1], ptr[2], ptr[3], 2614 ptr[4], ptr[5], ptr[6], ptr[7]); 2615 } 2616 2617 if (sc->rtsx_discovery_mode) 2618 rtsx_write(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK, RTSX_CLK_DIVIDE_128); 2619 2620 rtsx_req_done(sc); 2621 } 2622 } 2623 2624 /* 2625 * Get the data from the ping-pong buffer (cmd buffer) - second part > 256 bytes. 2626 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2627 */ 2628 static void 2629 rtsx_get_ppbuf_part2(struct rtsx_softc *sc) 2630 { 2631 struct mmc_command *cmd; 2632 uint8_t *ptr; 2633 int len; 2634 2635 cmd = sc->rtsx_req->cmd; 2636 ptr = cmd->data->data; 2637 ptr += RTSX_HOSTCMD_MAX; 2638 len = cmd->data->len - RTSX_HOSTCMD_MAX; 2639 2640 /* Sync command DMA buffer. */ 2641 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTREAD); 2642 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTWRITE); 2643 2644 memcpy(ptr, sc->rtsx_cmd_dmamem, len); 2645 2646 if (sc->rtsx_discovery_mode) 2647 rtsx_write(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK, RTSX_CLK_DIVIDE_128); 2648 2649 rtsx_req_done(sc); 2650 } 2651 2652 /* 2653 * Use the ping-pong buffer (cmd buffer) for transfer - first part <= 256 bytes. 2654 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2655 */ 2656 static void 2657 rtsx_put_ppbuf_part1(struct rtsx_softc *sc) 2658 { 2659 struct mmc_command *cmd; 2660 uint16_t reg = RTSX_PPBUF_BASE2; 2661 uint8_t *ptr; 2662 int len; 2663 int i; 2664 2665 cmd = sc->rtsx_req->cmd; 2666 ptr = cmd->data->data; 2667 len = (cmd->data->len > RTSX_HOSTCMD_MAX) ? RTSX_HOSTCMD_MAX : cmd->data->len; 2668 2669 rtsx_set_resp(sc, cmd); 2670 2671 sc->rtsx_cmd_index = 0; 2672 for (i = 0; i < len; i++) { 2673 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, reg++, 0xff, *ptr); 2674 ptr++; 2675 } 2676 2677 /* Set transfer OK function. */ 2678 if (cmd->data->len > RTSX_HOSTCMD_MAX) 2679 sc->rtsx_intr_trans_ok = rtsx_put_ppbuf_part2; 2680 else 2681 sc->rtsx_intr_trans_ok = rtsx_write_ppbuf; 2682 2683 /* Run the command queue. */ 2684 rtsx_send_cmd(sc); 2685 } 2686 2687 /* 2688 * Use the ping-pong buffer (cmd buffer) for transfer - second part > 256 bytes. 2689 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2690 */ 2691 static void 2692 rtsx_put_ppbuf_part2(struct rtsx_softc *sc) 2693 { 2694 struct mmc_command *cmd; 2695 uint16_t reg = RTSX_PPBUF_BASE2 + RTSX_HOSTCMD_MAX; 2696 uint8_t *ptr; 2697 int len; 2698 int i; 2699 2700 cmd = sc->rtsx_req->cmd; 2701 ptr = cmd->data->data; 2702 ptr += RTSX_HOSTCMD_MAX; 2703 len = cmd->data->len - RTSX_HOSTCMD_MAX; 2704 2705 sc->rtsx_cmd_index = 0; 2706 for (i = 0; i < len; i++) { 2707 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, reg++, 0xff, *ptr); 2708 ptr++; 2709 } 2710 2711 /* Set transfer OK function. */ 2712 sc->rtsx_intr_trans_ok = rtsx_write_ppbuf; 2713 2714 /* Run the command queue. */ 2715 rtsx_send_cmd(sc); 2716 } 2717 2718 /* 2719 * Write the data previously given via the ping-pong buffer on the card. 2720 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2721 */ 2722 static void 2723 rtsx_write_ppbuf(struct rtsx_softc *sc) 2724 { 2725 struct mmc_command *cmd; 2726 2727 cmd = sc->rtsx_req->cmd; 2728 2729 sc->rtsx_cmd_index = 0; 2730 2731 /* Queue commands to configure data transfer size. */ 2732 rtsx_set_cmd_data_len(sc, cmd->data->len / cmd->data->xfer_len, cmd->data->xfer_len); 2733 2734 /* From Linux: rtsx_pci_sdmmc.c sd_write_data(). */ 2735 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 0xff, 2736 RTSX_SD_CALCULATE_CRC7 | RTSX_SD_CHECK_CRC16 | 2737 RTSX_SD_NO_WAIT_BUSY_END | RTSX_SD_CHECK_CRC7 | RTSX_SD_RSP_LEN_0); 2738 2739 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 0xff, 2740 RTSX_TM_AUTO_WRITE3 | RTSX_SD_TRANSFER_START); 2741 rtsx_push_cmd(sc, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, 2742 RTSX_SD_TRANSFER_END, RTSX_SD_TRANSFER_END); 2743 2744 /* Set transfer OK function. */ 2745 sc->rtsx_intr_trans_ok = rtsx_req_done; 2746 2747 /* Run the command queue. */ 2748 rtsx_send_cmd(sc); 2749 } 2750 2751 /* 2752 * Use the data buffer for transfer > 512 bytes. 2753 */ 2754 static int 2755 rtsx_xfer(struct rtsx_softc *sc, struct mmc_command *cmd) 2756 { 2757 int read = ISSET(cmd->data->flags, MMC_DATA_READ); 2758 2759 cmd->data->xfer_len = (cmd->data->len > RTSX_MAX_DATA_BLKLEN) ? 2760 RTSX_MAX_DATA_BLKLEN : cmd->data->len; 2761 2762 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 2763 device_printf(sc->rtsx_dev, "rtsx_xfer() - %s xfer: %ld bytes with block size %ld\n", 2764 read ? "Read" : "Write", 2765 (unsigned long)cmd->data->len, (unsigned long)cmd->data->xfer_len); 2766 2767 if (cmd->data->len > RTSX_DMA_DATA_BUFSIZE) { 2768 device_printf(sc->rtsx_dev, "rtsx_xfer() length too large: %ld > %d\n", 2769 (unsigned long)cmd->data->len, RTSX_DMA_DATA_BUFSIZE); 2770 cmd->error = MMC_ERR_INVALID; 2771 return (MMC_ERR_INVALID); 2772 } 2773 2774 if (!read) { 2775 /* Set transfer OK function. */ 2776 sc->rtsx_intr_trans_ok = rtsx_xfer_begin; 2777 2778 /* Run the command queue. */ 2779 rtsx_send_req(sc, cmd); 2780 } else { 2781 rtsx_xfer_start(sc); 2782 } 2783 2784 return (0); 2785 } 2786 2787 /* 2788 * Get request response and start dma data transfer (write command). 2789 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2790 */ 2791 static void 2792 rtsx_xfer_begin(struct rtsx_softc *sc) 2793 { 2794 struct mmc_command *cmd; 2795 2796 cmd = sc->rtsx_req->cmd; 2797 2798 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 2799 device_printf(sc->rtsx_dev, "rtsx_xfer_begin() - CMD%d\n", cmd->opcode); 2800 2801 rtsx_set_resp(sc, cmd); 2802 rtsx_xfer_start(sc); 2803 } 2804 2805 /* 2806 * Start dma data transfer. 2807 */ 2808 static void 2809 rtsx_xfer_start(struct rtsx_softc *sc) 2810 { 2811 struct mmc_command *cmd; 2812 int read; 2813 uint8_t cfg2; 2814 int dma_dir; 2815 int tmode; 2816 2817 cmd = sc->rtsx_req->cmd; 2818 read = ISSET(cmd->data->flags, MMC_DATA_READ); 2819 2820 /* Configure DMA transfer mode parameters. */ 2821 if (cmd->opcode == MMC_READ_MULTIPLE_BLOCK) 2822 cfg2 = RTSX_SD_CHECK_CRC16 | RTSX_SD_NO_WAIT_BUSY_END | RTSX_SD_RSP_LEN_6; 2823 else 2824 cfg2 = RTSX_SD_CHECK_CRC16 | RTSX_SD_NO_WAIT_BUSY_END | RTSX_SD_RSP_LEN_0; 2825 if (read) { 2826 dma_dir = RTSX_DMA_DIR_FROM_CARD; 2827 /* 2828 * Use transfer mode AUTO_READ1, which assume we not 2829 * already send the read command and don't need to send 2830 * CMD 12 manually after read. 2831 */ 2832 tmode = RTSX_TM_AUTO_READ1; 2833 cfg2 |= RTSX_SD_CALCULATE_CRC7 | RTSX_SD_CHECK_CRC7; 2834 2835 rtsx_init_cmd(sc, cmd); 2836 } else { 2837 dma_dir = RTSX_DMA_DIR_TO_CARD; 2838 /* 2839 * Use transfer mode AUTO_WRITE3, wich assumes we've already 2840 * sent the write command and gotten the response, and will 2841 * send CMD 12 manually after writing. 2842 */ 2843 tmode = RTSX_TM_AUTO_WRITE3; 2844 cfg2 |= RTSX_SD_NO_CALCULATE_CRC7 | RTSX_SD_NO_CHECK_CRC7; 2845 2846 sc->rtsx_cmd_index = 0; 2847 } 2848 2849 /* Queue commands to configure data transfer size. */ 2850 rtsx_set_cmd_data_len(sc, cmd->data->len / cmd->data->xfer_len, cmd->data->xfer_len); 2851 2852 /* Configure DMA controller. */ 2853 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_IRQSTAT0, 2854 RTSX_DMA_DONE_INT, RTSX_DMA_DONE_INT); 2855 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMATC3, 2856 0xff, cmd->data->len >> 24); 2857 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMATC2, 2858 0xff, cmd->data->len >> 16); 2859 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMATC1, 2860 0xff, cmd->data->len >> 8); 2861 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMATC0, 2862 0xff, cmd->data->len); 2863 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMACTL, 2864 RTSX_DMA_EN | RTSX_DMA_DIR | RTSX_DMA_PACK_SIZE_MASK, 2865 RTSX_DMA_EN | dma_dir | RTSX_DMA_512); 2866 2867 /* Use the DMA ring buffer for commands which transfer data. */ 2868 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_CARD_DATA_SOURCE, 2869 0x01, RTSX_RING_BUFFER); 2870 2871 /* Queue command to set response type. */ 2872 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 0xff, cfg2); 2873 2874 /* Queue commands to perform SD transfer. */ 2875 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 2876 0xff, tmode | RTSX_SD_TRANSFER_START); 2877 rtsx_push_cmd(sc, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, 2878 RTSX_SD_TRANSFER_END, RTSX_SD_TRANSFER_END); 2879 2880 /* Run the command queue. */ 2881 rtsx_send_cmd(sc); 2882 2883 if (!read) 2884 memcpy(sc->rtsx_data_dmamem, cmd->data->data, cmd->data->len); 2885 2886 /* Sync data DMA buffer. */ 2887 bus_dmamap_sync(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamap, BUS_DMASYNC_PREREAD); 2888 bus_dmamap_sync(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamap, BUS_DMASYNC_PREWRITE); 2889 2890 /* Set transfer OK function. */ 2891 sc->rtsx_intr_trans_ok = rtsx_xfer_finish; 2892 2893 /* Tell the chip where the data buffer is and run the transfer. */ 2894 WRITE4(sc, RTSX_HDBAR, sc->rtsx_data_buffer); 2895 WRITE4(sc, RTSX_HDBCTLR, RTSX_TRIG_DMA | (read ? RTSX_DMA_READ : 0) | 2896 (cmd->data->len & 0x00ffffff)); 2897 } 2898 2899 /* 2900 * Finish dma data transfer. 2901 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2902 */ 2903 static void 2904 rtsx_xfer_finish(struct rtsx_softc *sc) 2905 { 2906 struct mmc_command *cmd; 2907 int read; 2908 2909 cmd = sc->rtsx_req->cmd; 2910 2911 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 2912 device_printf(sc->rtsx_dev, "rtsx_xfer_finish() - CMD%d\n", cmd->opcode); 2913 2914 read = ISSET(cmd->data->flags, MMC_DATA_READ); 2915 2916 /* Sync data DMA buffer. */ 2917 bus_dmamap_sync(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamap, BUS_DMASYNC_POSTREAD); 2918 bus_dmamap_sync(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamap, BUS_DMASYNC_POSTWRITE); 2919 2920 if (read) { 2921 memcpy(cmd->data->data, sc->rtsx_data_dmamem, cmd->data->len); 2922 rtsx_req_done(sc); 2923 } else { 2924 /* Send CMD12 after AUTO_WRITE3 (see mmcsd_rw() in mmcsd.c) */ 2925 /* and complete request. */ 2926 sc->rtsx_intr_trans_ok = NULL; 2927 rtsx_send_req(sc, sc->rtsx_req->stop); 2928 } 2929 } 2930 2931 /* 2932 * Manage request timeout. 2933 */ 2934 static void 2935 rtsx_timeout(void *arg) 2936 { 2937 struct rtsx_softc *sc; 2938 2939 sc = (struct rtsx_softc *)arg; 2940 if (sc->rtsx_req != NULL) { 2941 device_printf(sc->rtsx_dev, "Controller timeout for CMD%u\n", 2942 sc->rtsx_req->cmd->opcode); 2943 sc->rtsx_req->cmd->error = MMC_ERR_TIMEOUT; 2944 rtsx_stop_cmd(sc); 2945 rtsx_req_done(sc); 2946 } else { 2947 device_printf(sc->rtsx_dev, "Controller timeout!\n"); 2948 } 2949 } 2950 2951 #ifdef MMCCAM 2952 static int 2953 rtsx_get_tran_settings(device_t dev, struct ccb_trans_settings_mmc *cts) 2954 { 2955 struct rtsx_softc *sc; 2956 2957 sc = device_get_softc(dev); 2958 2959 cts->host_ocr = sc->rtsx_host.host_ocr; 2960 cts->host_f_min = sc->rtsx_host.f_min; 2961 cts->host_f_max = sc->rtsx_host.f_max; 2962 cts->host_caps = sc->rtsx_host.caps; 2963 cts->host_max_data = RTSX_DMA_DATA_BUFSIZE / MMC_SECTOR_SIZE; 2964 memcpy(&cts->ios, &sc->rtsx_host.ios, sizeof(struct mmc_ios)); 2965 2966 return (0); 2967 } 2968 2969 /* 2970 * Apply settings and return status accordingly. 2971 */ 2972 static int 2973 rtsx_set_tran_settings(device_t dev, struct ccb_trans_settings_mmc *cts) 2974 { 2975 struct rtsx_softc *sc; 2976 struct mmc_ios *ios; 2977 struct mmc_ios *new_ios; 2978 2979 sc = device_get_softc(dev); 2980 2981 ios = &sc->rtsx_host.ios; 2982 new_ios = &cts->ios; 2983 2984 /* Update only requested fields */ 2985 if (cts->ios_valid & MMC_CLK) { 2986 ios->clock = new_ios->clock; 2987 sc->rtsx_ios_clock = -1; /* To be updated by rtsx_mmcbr_update_ios(). */ 2988 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 2989 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - clock: %u\n", ios->clock); 2990 } 2991 if (cts->ios_valid & MMC_VDD) { 2992 ios->vdd = new_ios->vdd; 2993 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 2994 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - vdd: %d\n", ios->vdd); 2995 } 2996 if (cts->ios_valid & MMC_CS) { 2997 ios->chip_select = new_ios->chip_select; 2998 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 2999 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - chip_select: %d\n", ios->chip_select); 3000 } 3001 if (cts->ios_valid & MMC_BW) { 3002 ios->bus_width = new_ios->bus_width; 3003 sc->rtsx_ios_bus_width = -1; /* To be updated by rtsx_mmcbr_update_ios(). */ 3004 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 3005 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - bus width: %d\n", ios->bus_width); 3006 } 3007 if (cts->ios_valid & MMC_PM) { 3008 ios->power_mode = new_ios->power_mode; 3009 sc->rtsx_ios_power_mode = -1; /* To be updated by rtsx_mmcbr_update_ios(). */ 3010 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 3011 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - power mode: %d\n", ios->power_mode); 3012 } 3013 if (cts->ios_valid & MMC_BT) { 3014 ios->timing = new_ios->timing; 3015 sc->rtsx_ios_timing = -1; /* To be updated by rtsx_mmcbr_update_ios(). */ 3016 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 3017 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - timing: %d\n", ios->timing); 3018 } 3019 if (cts->ios_valid & MMC_BM) { 3020 ios->bus_mode = new_ios->bus_mode; 3021 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 3022 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - bus mode: %d\n", ios->bus_mode); 3023 } 3024 #if __FreeBSD_version >= 1300000 3025 if (cts->ios_valid & MMC_VCCQ) { 3026 ios->vccq = new_ios->vccq; 3027 sc->rtsx_ios_vccq = -1; /* To be updated by rtsx_mmcbr_update_ios(). */ 3028 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 3029 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - vccq: %d\n", ios->vccq); 3030 } 3031 #endif /* __FreeBSD_version >= 1300000 */ 3032 if (rtsx_mmcbr_update_ios(sc->rtsx_dev, NULL) == 0) 3033 return (CAM_REQ_CMP); 3034 else 3035 return (CAM_REQ_CMP_ERR); 3036 } 3037 3038 /* 3039 * Build a request and run it. 3040 */ 3041 static int 3042 rtsx_cam_request(device_t dev, union ccb *ccb) 3043 { 3044 struct rtsx_softc *sc; 3045 3046 sc = device_get_softc(dev); 3047 3048 RTSX_LOCK(sc); 3049 if (sc->rtsx_ccb != NULL) { 3050 RTSX_UNLOCK(sc); 3051 return (CAM_BUSY); 3052 } 3053 sc->rtsx_ccb = ccb; 3054 sc->rtsx_cam_req.cmd = &ccb->mmcio.cmd; 3055 sc->rtsx_cam_req.stop = &ccb->mmcio.stop; 3056 RTSX_UNLOCK(sc); 3057 3058 rtsx_mmcbr_request(sc->rtsx_dev, NULL, &sc->rtsx_cam_req); 3059 return (0); 3060 } 3061 #endif /* MMCCAM */ 3062 3063 static int 3064 rtsx_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) 3065 { 3066 struct rtsx_softc *sc; 3067 3068 sc = device_get_softc(bus); 3069 switch (which) { 3070 case MMCBR_IVAR_BUS_MODE: /* ivar 0 - 1 = opendrain, 2 = pushpull */ 3071 *result = sc->rtsx_host.ios.bus_mode; 3072 break; 3073 case MMCBR_IVAR_BUS_WIDTH: /* ivar 1 - 0 = 1b 2 = 4b, 3 = 8b */ 3074 *result = sc->rtsx_host.ios.bus_width; 3075 break; 3076 case MMCBR_IVAR_CHIP_SELECT: /* ivar 2 - O = dontcare, 1 = cs_high, 2 = cs_low */ 3077 *result = sc->rtsx_host.ios.chip_select; 3078 break; 3079 case MMCBR_IVAR_CLOCK: /* ivar 3 - clock in Hz */ 3080 *result = sc->rtsx_host.ios.clock; 3081 break; 3082 case MMCBR_IVAR_F_MIN: /* ivar 4 */ 3083 *result = sc->rtsx_host.f_min; 3084 break; 3085 case MMCBR_IVAR_F_MAX: /* ivar 5 */ 3086 *result = sc->rtsx_host.f_max; 3087 break; 3088 case MMCBR_IVAR_HOST_OCR: /* ivar 6 - host operation conditions register */ 3089 *result = sc->rtsx_host.host_ocr; 3090 break; 3091 case MMCBR_IVAR_MODE: /* ivar 7 - 0 = mode_mmc, 1 = mode_sd */ 3092 *result = sc->rtsx_host.mode; 3093 break; 3094 case MMCBR_IVAR_OCR: /* ivar 8 - operation conditions register */ 3095 *result = sc->rtsx_host.ocr; 3096 break; 3097 case MMCBR_IVAR_POWER_MODE: /* ivar 9 - 0 = off, 1 = up, 2 = on */ 3098 *result = sc->rtsx_host.ios.power_mode; 3099 break; 3100 case MMCBR_IVAR_VDD: /* ivar 11 - voltage power pin */ 3101 *result = sc->rtsx_host.ios.vdd; 3102 break; 3103 case MMCBR_IVAR_VCCQ: /* ivar 12 - signaling: 0 = 1.20V, 1 = 1.80V, 2 = 3.30V */ 3104 *result = sc->rtsx_host.ios.vccq; 3105 break; 3106 case MMCBR_IVAR_CAPS: /* ivar 13 */ 3107 *result = sc->rtsx_host.caps; 3108 break; 3109 case MMCBR_IVAR_TIMING: /* ivar 14 - 0 = normal, 1 = timing_hs, ... */ 3110 *result = sc->rtsx_host.ios.timing; 3111 break; 3112 case MMCBR_IVAR_MAX_DATA: /* ivar 15 */ 3113 *result = RTSX_DMA_DATA_BUFSIZE / MMC_SECTOR_SIZE; 3114 break; 3115 case MMCBR_IVAR_RETUNE_REQ: /* ivar 10 */ 3116 case MMCBR_IVAR_MAX_BUSY_TIMEOUT: /* ivar 16 */ 3117 default: 3118 return (EINVAL); 3119 } 3120 3121 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 3122 device_printf(bus, "Read ivar #%d, value %#x / #%d\n", 3123 which, *(int *)result, *(int *)result); 3124 3125 return (0); 3126 } 3127 3128 static int 3129 rtsx_write_ivar(device_t bus, device_t child, int which, uintptr_t value) 3130 { 3131 struct rtsx_softc *sc; 3132 3133 sc = device_get_softc(bus); 3134 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 3135 device_printf(bus, "Write ivar #%d, value %#x / #%d\n", 3136 which, (int)value, (int)value); 3137 3138 switch (which) { 3139 case MMCBR_IVAR_BUS_MODE: /* ivar 0 - 1 = opendrain, 2 = pushpull */ 3140 sc->rtsx_host.ios.bus_mode = value; 3141 break; 3142 case MMCBR_IVAR_BUS_WIDTH: /* ivar 1 - 0 = 1b 2 = 4b, 3 = 8b */ 3143 sc->rtsx_host.ios.bus_width = value; 3144 sc->rtsx_ios_bus_width = -1; /* To be updated on next rtsx_mmcbr_update_ios(). */ 3145 break; 3146 case MMCBR_IVAR_CHIP_SELECT: /* ivar 2 - O = dontcare, 1 = cs_high, 2 = cs_low */ 3147 sc->rtsx_host.ios.chip_select = value; 3148 break; 3149 case MMCBR_IVAR_CLOCK: /* ivar 3 - clock in Hz */ 3150 sc->rtsx_host.ios.clock = value; 3151 sc->rtsx_ios_clock = -1; /* To be updated on next rtsx_mmcbr_update_ios(). */ 3152 break; 3153 case MMCBR_IVAR_MODE: /* ivar 7 - 0 = mode_mmc, 1 = mode_sd */ 3154 sc->rtsx_host.mode = value; 3155 break; 3156 case MMCBR_IVAR_OCR: /* ivar 8 - operation conditions register */ 3157 sc->rtsx_host.ocr = value; 3158 break; 3159 case MMCBR_IVAR_POWER_MODE: /* ivar 9 - 0 = off, 1 = up, 2 = on */ 3160 sc->rtsx_host.ios.power_mode = value; 3161 sc->rtsx_ios_power_mode = -1; /* To be updated on next rtsx_mmcbr_update_ios(). */ 3162 break; 3163 case MMCBR_IVAR_VDD: /* ivar 11 - voltage power pin */ 3164 sc->rtsx_host.ios.vdd = value; 3165 break; 3166 case MMCBR_IVAR_VCCQ: /* ivar 12 - signaling: 0 = 1.20V, 1 = 1.80V, 2 = 3.30V */ 3167 sc->rtsx_host.ios.vccq = value; 3168 sc->rtsx_ios_vccq = value; /* rtsx_mmcbr_switch_vccq() will be called by mmc.c (MMCCAM undef). */ 3169 break; 3170 case MMCBR_IVAR_TIMING: /* ivar 14 - 0 = normal, 1 = timing_hs, ... */ 3171 sc->rtsx_host.ios.timing = value; 3172 sc->rtsx_ios_timing = -1; /* To be updated on next rtsx_mmcbr_update_ios(). */ 3173 break; 3174 /* These are read-only. */ 3175 case MMCBR_IVAR_F_MIN: /* ivar 4 */ 3176 case MMCBR_IVAR_F_MAX: /* ivar 5 */ 3177 case MMCBR_IVAR_HOST_OCR: /* ivar 6 - host operation conditions register */ 3178 case MMCBR_IVAR_RETUNE_REQ: /* ivar 10 */ 3179 case MMCBR_IVAR_CAPS: /* ivar 13 */ 3180 case MMCBR_IVAR_MAX_DATA: /* ivar 15 */ 3181 case MMCBR_IVAR_MAX_BUSY_TIMEOUT: /* ivar 16 */ 3182 default: 3183 return (EINVAL); 3184 } 3185 3186 return (0); 3187 } 3188 3189 static int 3190 rtsx_mmcbr_update_ios(device_t bus, device_t child__unused) 3191 { 3192 struct rtsx_softc *sc; 3193 struct mmc_ios *ios; 3194 int error; 3195 3196 sc = device_get_softc(bus); 3197 ios = &sc->rtsx_host.ios; 3198 3199 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 3200 device_printf(bus, "rtsx_mmcbr_update_ios()\n"); 3201 3202 /* if MMCBR_IVAR_BUS_WIDTH updated. */ 3203 if (sc->rtsx_ios_bus_width < 0) { 3204 sc->rtsx_ios_bus_width = ios->bus_width; 3205 if ((error = rtsx_set_bus_width(sc, ios->bus_width))) 3206 return (error); 3207 } 3208 3209 /* if MMCBR_IVAR_POWER_MODE updated. */ 3210 if (sc->rtsx_ios_power_mode < 0) { 3211 sc->rtsx_ios_power_mode = ios->power_mode; 3212 switch (ios->power_mode) { 3213 case power_off: 3214 if ((error = rtsx_bus_power_off(sc))) 3215 return (error); 3216 break; 3217 case power_up: 3218 if ((error = rtsx_bus_power_on(sc))) 3219 return (error); 3220 break; 3221 case power_on: 3222 if ((error = rtsx_bus_power_on(sc))) 3223 return (error); 3224 break; 3225 } 3226 } 3227 3228 sc->rtsx_double_clk = true; 3229 sc->rtsx_vpclk = false; 3230 3231 /* if MMCBR_IVAR_TIMING updated. */ 3232 if (sc->rtsx_ios_timing < 0) { 3233 sc->rtsx_ios_timing = ios->timing; 3234 if ((error = rtsx_set_sd_timing(sc, ios->timing))) 3235 return (error); 3236 } 3237 3238 /* if MMCBR_IVAR_CLOCK updated, must be after rtsx_set_sd_timing() */ 3239 if (sc->rtsx_ios_clock < 0) { 3240 sc->rtsx_ios_clock = ios->clock; 3241 if ((error = rtsx_set_sd_clock(sc, ios->clock))) 3242 return (error); 3243 } 3244 3245 /* if MMCCAM and vccq updated */ 3246 if (sc->rtsx_ios_vccq < 0) { 3247 sc->rtsx_ios_vccq = ios->vccq; 3248 if ((error = rtsx_mmcbr_switch_vccq(sc->rtsx_dev, NULL))) 3249 return (error); 3250 } 3251 3252 return (0); 3253 } 3254 3255 /* 3256 * Set output stage logic power voltage. 3257 */ 3258 static int 3259 rtsx_mmcbr_switch_vccq(device_t bus, device_t child __unused) 3260 { 3261 struct rtsx_softc *sc; 3262 int vccq = 0; 3263 int error; 3264 3265 sc = device_get_softc(bus); 3266 3267 switch (sc->rtsx_host.ios.vccq) { 3268 case vccq_120: 3269 vccq = 120; 3270 break; 3271 case vccq_180: 3272 vccq = 180; 3273 break; 3274 case vccq_330: 3275 vccq = 330; 3276 break; 3277 }; 3278 /* It seems it is always vccq_330. */ 3279 if (vccq == 330) { 3280 switch (sc->rtsx_device_id) { 3281 uint16_t val; 3282 case RTSX_RTS5227: 3283 if ((error = rtsx_write_phy(sc, 0x08, 0x4FE4))) 3284 return (error); 3285 if ((error = rtsx_rts5227_fill_driving(sc))) 3286 return (error); 3287 break; 3288 case RTSX_RTS5209: 3289 case RTSX_RTS5229: 3290 RTSX_BITOP(sc, RTSX_SD30_CMD_DRIVE_SEL, RTSX_SD30_DRIVE_SEL_MASK, sc->rtsx_sd30_drive_sel_3v3); 3291 if ((error = rtsx_write_phy(sc, 0x08, 0x4FE4))) 3292 return (error); 3293 break; 3294 case RTSX_RTS522A: 3295 if ((error = rtsx_write_phy(sc, 0x08, 0x57E4))) 3296 return (error); 3297 if ((error = rtsx_rts5227_fill_driving(sc))) 3298 return (error); 3299 break; 3300 case RTSX_RTS525A: 3301 RTSX_BITOP(sc, RTSX_LDO_CONFIG2, RTSX_LDO_D3318_MASK, RTSX_LDO_D3318_33V); 3302 RTSX_BITOP(sc, RTSX_SD_PAD_CTL, RTSX_SD_IO_USING_1V8, 0); 3303 if ((error = rtsx_rts5249_fill_driving(sc))) 3304 return (error); 3305 break; 3306 case RTSX_RTS5249: 3307 if ((error = rtsx_read_phy(sc, RTSX_PHY_TUNE, &val))) 3308 return (error); 3309 if ((error = rtsx_write_phy(sc, RTSX_PHY_TUNE, 3310 (val & RTSX_PHY_TUNE_VOLTAGE_MASK) | RTSX_PHY_TUNE_VOLTAGE_3V3))) 3311 return (error); 3312 if ((error = rtsx_rts5249_fill_driving(sc))) 3313 return (error); 3314 break; 3315 case RTSX_RTS5260: 3316 RTSX_BITOP(sc, RTSX_LDO_CONFIG2, RTSX_DV331812_VDD1, RTSX_DV331812_VDD1); 3317 RTSX_BITOP(sc, RTSX_LDO_DV18_CFG, RTSX_DV331812_MASK, RTSX_DV331812_33); 3318 RTSX_CLR(sc, RTSX_SD_PAD_CTL, RTSX_SD_IO_USING_1V8); 3319 if ((error = rtsx_rts5260_fill_driving(sc))) 3320 return (error); 3321 break; 3322 case RTSX_RTL8402: 3323 RTSX_BITOP(sc, RTSX_SD30_CMD_DRIVE_SEL, RTSX_SD30_DRIVE_SEL_MASK, sc->rtsx_sd30_drive_sel_3v3); 3324 RTSX_BITOP(sc, RTSX_LDO_CTL, 3325 (RTSX_BPP_ASIC_MASK << RTSX_BPP_SHIFT_8402) | RTSX_BPP_PAD_MASK, 3326 (RTSX_BPP_ASIC_3V3 << RTSX_BPP_SHIFT_8402) | RTSX_BPP_PAD_3V3); 3327 break; 3328 case RTSX_RTL8411: 3329 case RTSX_RTL8411B: 3330 RTSX_BITOP(sc, RTSX_SD30_CMD_DRIVE_SEL, RTSX_SD30_DRIVE_SEL_MASK, sc->rtsx_sd30_drive_sel_3v3); 3331 RTSX_BITOP(sc, RTSX_LDO_CTL, 3332 (RTSX_BPP_ASIC_MASK << RTSX_BPP_SHIFT_8411) | RTSX_BPP_PAD_MASK, 3333 (RTSX_BPP_ASIC_3V3 << RTSX_BPP_SHIFT_8411) | RTSX_BPP_PAD_3V3); 3334 break; 3335 } 3336 DELAY(300); 3337 } 3338 3339 if (sc->rtsx_debug_mask & (RTSX_DEBUG_BASIC | RTSX_TRACE_SD_CMD)) 3340 device_printf(sc->rtsx_dev, "rtsx_mmcbr_switch_vccq(%d)\n", vccq); 3341 3342 return (0); 3343 } 3344 3345 #ifndef MMCCAM 3346 /* 3347 * Tune card if bus_timing_uhs_sdr50. 3348 */ 3349 static int 3350 rtsx_mmcbr_tune(device_t bus, device_t child __unused, bool hs400) 3351 { 3352 struct rtsx_softc *sc; 3353 uint32_t raw_phase_map[RTSX_RX_TUNING_CNT] = {0}; 3354 uint32_t phase_map; 3355 uint8_t final_phase; 3356 int i; 3357 3358 sc = device_get_softc(bus); 3359 3360 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 3361 device_printf(sc->rtsx_dev, "rtsx_mmcbr_tune() - hs400 is %s\n", 3362 (hs400) ? "true" : "false"); 3363 3364 if (sc->rtsx_ios_timing != bus_timing_uhs_sdr50) 3365 return (0); 3366 3367 sc->rtsx_tuning_mode = true; 3368 3369 switch (sc->rtsx_device_id) { 3370 case RTSX_RTS5209: 3371 case RTSX_RTS5227: 3372 rtsx_sd_change_tx_phase(sc, 27); 3373 break; 3374 case RTSX_RTS522A: 3375 rtsx_sd_change_tx_phase(sc, 20); 3376 break; 3377 case RTSX_RTS5229: 3378 rtsx_sd_change_tx_phase(sc, 27); 3379 break; 3380 case RTSX_RTS525A: 3381 case RTSX_RTS5249: 3382 rtsx_sd_change_tx_phase(sc, 29); 3383 break; 3384 case RTSX_RTL8402: 3385 case RTSX_RTL8411: 3386 case RTSX_RTL8411B: 3387 rtsx_sd_change_tx_phase(sc, 7); 3388 break; 3389 } 3390 3391 /* trying rx tuning for bus_timing_uhs_sdr50. */ 3392 for (i = 0; i < RTSX_RX_TUNING_CNT; i++) { 3393 rtsx_sd_tuning_rx_phase(sc, &(raw_phase_map[i])); 3394 if (raw_phase_map[i] == 0) 3395 break; 3396 } 3397 3398 phase_map = 0xffffffff; 3399 for (i = 0; i < RTSX_RX_TUNING_CNT; i++) { 3400 if (sc->rtsx_debug_mask & (RTSX_DEBUG_BASIC | RTSX_DEBUG_TUNING)) 3401 device_printf(sc->rtsx_dev, "rtsx_mmcbr_tune() - RX raw_phase_map[%d]: 0x%08x\n", 3402 i, raw_phase_map[i]); 3403 phase_map &= raw_phase_map[i]; 3404 } 3405 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 3406 device_printf(sc->rtsx_dev, "rtsx_mmcbr_tune() - RX phase_map: 0x%08x\n", phase_map); 3407 3408 if (phase_map) { 3409 final_phase = rtsx_sd_search_final_rx_phase(sc, phase_map); 3410 if (final_phase != 0xff) { 3411 rtsx_sd_change_rx_phase(sc, final_phase); 3412 } 3413 } 3414 3415 sc->rtsx_tuning_mode = false; 3416 3417 return (0); 3418 } 3419 3420 static int 3421 rtsx_mmcbr_retune(device_t bus, device_t child __unused, bool reset __unused) 3422 { 3423 struct rtsx_softc *sc; 3424 3425 sc = device_get_softc(bus); 3426 3427 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 3428 device_printf(sc->rtsx_dev, "rtsx_mmcbr_retune()\n"); 3429 3430 return (0); 3431 } 3432 #endif /* !MMCCAM */ 3433 3434 static int 3435 rtsx_mmcbr_request(device_t bus, device_t child __unused, struct mmc_request *req) 3436 { 3437 struct rtsx_softc *sc; 3438 struct mmc_command *cmd; 3439 int timeout; 3440 int error; 3441 3442 sc = device_get_softc(bus); 3443 3444 RTSX_LOCK(sc); 3445 if (sc->rtsx_req != NULL) { 3446 RTSX_UNLOCK(sc); 3447 return (EBUSY); 3448 } 3449 sc->rtsx_req = req; 3450 cmd = req->cmd; 3451 cmd->error = error = MMC_ERR_NONE; 3452 sc->rtsx_intr_status = 0; 3453 sc->rtsx_intr_trans_ok = NULL; 3454 sc->rtsx_intr_trans_ko = rtsx_req_done; 3455 3456 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 3457 device_printf(sc->rtsx_dev, "rtsx_mmcbr_request(CMD%u arg %#x, flags %#x, dlen %u, dflags %#x)\n", 3458 cmd->opcode, cmd->arg, cmd->flags, 3459 cmd->data != NULL ? (unsigned int)cmd->data->len : 0, 3460 cmd->data != NULL ? cmd->data->flags : 0); 3461 3462 /* Check if card present. */ 3463 if (!ISSET(sc->rtsx_flags, RTSX_F_CARD_PRESENT)) { 3464 cmd->error = error = MMC_ERR_FAILED; 3465 goto end; 3466 } 3467 3468 /* Refuse SDIO probe if the chip doesn't support SDIO. */ 3469 if (cmd->opcode == IO_SEND_OP_COND && 3470 !ISSET(sc->rtsx_flags, RTSX_F_SDIO_SUPPORT)) { 3471 cmd->error = error = MMC_ERR_INVALID; 3472 goto end; 3473 } 3474 3475 /* Return MMC_ERR_TIMEOUT for SD_IO_RW_DIRECT and IO_SEND_OP_COND. */ 3476 if (cmd->opcode == SD_IO_RW_DIRECT || cmd->opcode == IO_SEND_OP_COND) { 3477 cmd->error = error = MMC_ERR_TIMEOUT; 3478 goto end; 3479 } 3480 3481 /* Select SD card. */ 3482 RTSX_BITOP(sc, RTSX_CARD_SELECT, 0x07, RTSX_SD_MOD_SEL); 3483 RTSX_BITOP(sc, RTSX_CARD_SHARE_MODE, RTSX_CARD_SHARE_MASK, RTSX_CARD_SHARE_48_SD); 3484 3485 if (cmd->data == NULL) { 3486 DELAY(200); 3487 timeout = sc->rtsx_timeout_cmd; 3488 error = rtsx_send_req(sc, cmd); 3489 } else if (cmd->data->len <= 512) { 3490 timeout = sc->rtsx_timeout_io; 3491 error = rtsx_xfer_short(sc, cmd); 3492 } else { 3493 timeout = sc->rtsx_timeout_io; 3494 error = rtsx_xfer(sc, cmd); 3495 } 3496 end: 3497 if (error == MMC_ERR_NONE) { 3498 callout_reset(&sc->rtsx_timeout_callout, timeout * hz, rtsx_timeout, sc); 3499 } else { 3500 rtsx_req_done(sc); 3501 } 3502 RTSX_UNLOCK(sc); 3503 3504 return (error); 3505 } 3506 3507 #ifndef MMCCAM 3508 static int 3509 rtsx_mmcbr_get_ro(device_t bus, device_t child __unused) 3510 { 3511 struct rtsx_softc *sc; 3512 3513 sc = device_get_softc(bus); 3514 3515 if (sc->rtsx_inversion == 0) 3516 return (sc->rtsx_read_only); 3517 else 3518 return !(sc->rtsx_read_only); 3519 } 3520 3521 static int 3522 rtsx_mmcbr_acquire_host(device_t bus, device_t child __unused) 3523 { 3524 struct rtsx_softc *sc; 3525 3526 sc = device_get_softc(bus); 3527 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 3528 device_printf(bus, "rtsx_mmcbr_acquire_host()\n"); 3529 3530 RTSX_LOCK(sc); 3531 while (sc->rtsx_bus_busy) 3532 msleep(&sc->rtsx_bus_busy, &sc->rtsx_mtx, 0, "rtsxah", 0); 3533 sc->rtsx_bus_busy++; 3534 RTSX_UNLOCK(sc); 3535 3536 return (0); 3537 } 3538 3539 static int 3540 rtsx_mmcbr_release_host(device_t bus, device_t child __unused) 3541 { 3542 struct rtsx_softc *sc; 3543 3544 sc = device_get_softc(bus); 3545 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 3546 device_printf(bus, "rtsx_mmcbr_release_host()\n"); 3547 3548 RTSX_LOCK(sc); 3549 sc->rtsx_bus_busy--; 3550 wakeup(&sc->rtsx_bus_busy); 3551 RTSX_UNLOCK(sc); 3552 3553 return (0); 3554 } 3555 #endif /* !MMCCAM */ 3556 3557 /* 3558 * 3559 * PCI Support Functions 3560 * 3561 */ 3562 3563 /* 3564 * Compare the device ID (chip) of this device against the IDs that this driver 3565 * supports. If there is a match, set the description and return success. 3566 */ 3567 static int 3568 rtsx_probe(device_t dev) 3569 { 3570 uint16_t vendor_id; 3571 uint16_t device_id; 3572 int i; 3573 3574 vendor_id = pci_get_vendor(dev); 3575 device_id = pci_get_device(dev); 3576 3577 if (vendor_id != RTSX_REALTEK) 3578 return (ENXIO); 3579 for (i = 0; i < nitems(rtsx_ids); i++) { 3580 if (rtsx_ids[i].device_id == device_id) { 3581 device_set_desc(dev, rtsx_ids[i].desc); 3582 return (BUS_PROBE_DEFAULT); 3583 } 3584 } 3585 return (ENXIO); 3586 } 3587 3588 /* 3589 * Attach function is only called if the probe is successful. 3590 */ 3591 static int 3592 rtsx_attach(device_t dev) 3593 { 3594 struct rtsx_softc *sc = device_get_softc(dev); 3595 uint16_t vendor_id; 3596 uint16_t device_id; 3597 struct sysctl_ctx_list *ctx; 3598 struct sysctl_oid_list *tree; 3599 int msi_count = 1; 3600 uint32_t sdio_cfg; 3601 int error; 3602 char *maker; 3603 char *family; 3604 char *product; 3605 int i; 3606 3607 vendor_id = pci_get_vendor(dev); 3608 device_id = pci_get_device(dev); 3609 if (bootverbose) 3610 device_printf(dev, "Attach - Vendor ID: 0x%x - Device ID: 0x%x\n", 3611 vendor_id, device_id); 3612 3613 sc->rtsx_dev = dev; 3614 sc->rtsx_device_id = device_id; 3615 sc->rtsx_req = NULL; 3616 sc->rtsx_timeout_cmd = 1; 3617 sc->rtsx_timeout_io = 10; 3618 sc->rtsx_read_only = 0; 3619 sc->rtsx_inversion = 0; 3620 sc->rtsx_force_timing = 0; 3621 sc->rtsx_debug_mask = 0; 3622 sc->rtsx_read_count = 0; 3623 sc->rtsx_write_count = 0; 3624 3625 maker = kern_getenv("smbios.system.maker"); 3626 family = kern_getenv("smbios.system.family"); 3627 product = kern_getenv("smbios.system.product"); 3628 for (i = 0; rtsx_inversion_models[i].maker != NULL; i++) { 3629 if (strcmp(rtsx_inversion_models[i].maker, maker) == 0 && 3630 strcmp(rtsx_inversion_models[i].family, family) == 0 && 3631 strcmp(rtsx_inversion_models[i].product, product) == 0) { 3632 device_printf(dev, "Inversion activated for %s/%s/%s, see BUG in rtsx(4)\n", maker, family, product); 3633 device_printf(dev, "If a card is detected without an SD card present," 3634 " add dev.rtsx.0.inversion=0 in loader.conf(5)\n"); 3635 sc->rtsx_inversion = 1; 3636 } 3637 } 3638 3639 RTSX_LOCK_INIT(sc); 3640 3641 ctx = device_get_sysctl_ctx(dev); 3642 tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 3643 SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "timeout_io", CTLFLAG_RW, 3644 &sc->rtsx_timeout_io, 0, "Request timeout for I/O commands in seconds"); 3645 SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "timeout_cmd", CTLFLAG_RW, 3646 &sc->rtsx_timeout_cmd, 0, "Request timeout for setup commands in seconds"); 3647 SYSCTL_ADD_U8(ctx, tree, OID_AUTO, "read_only", CTLFLAG_RD, 3648 &sc->rtsx_read_only, 0, "Card is write protected"); 3649 SYSCTL_ADD_U8(ctx, tree, OID_AUTO, "inversion", CTLFLAG_RWTUN, 3650 &sc->rtsx_inversion, 0, "Inversion of card detection and read only status"); 3651 SYSCTL_ADD_U8(ctx, tree, OID_AUTO, "force_timing", CTLFLAG_RW, 3652 &sc->rtsx_force_timing, 0, "Force bus_timing_uhs_sdr50"); 3653 SYSCTL_ADD_U8(ctx, tree, OID_AUTO, "debug_mask", CTLFLAG_RWTUN, 3654 &sc->rtsx_debug_mask, 0, "debugging mask, see rtsx(4)"); 3655 SYSCTL_ADD_U64(ctx, tree, OID_AUTO, "read_count", CTLFLAG_RD | CTLFLAG_STATS, 3656 &sc->rtsx_read_count, 0, "Count of read operations"); 3657 SYSCTL_ADD_U64(ctx, tree, OID_AUTO, "write_count", CTLFLAG_RD | CTLFLAG_STATS, 3658 &sc->rtsx_write_count, 0, "Count of write operations"); 3659 3660 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 3661 device_printf(dev, "We are running with inversion: %d\n", sc->rtsx_inversion); 3662 3663 /* Allocate IRQ. */ 3664 sc->rtsx_irq_res_id = 0; 3665 if (pci_alloc_msi(dev, &msi_count) == 0) 3666 sc->rtsx_irq_res_id = 1; 3667 sc->rtsx_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->rtsx_irq_res_id, 3668 RF_ACTIVE | (sc->rtsx_irq_res_id != 0 ? 0 : RF_SHAREABLE)); 3669 if (sc->rtsx_irq_res == NULL) { 3670 device_printf(dev, "Can't allocate IRQ resources for %d\n", sc->rtsx_irq_res_id); 3671 pci_release_msi(dev); 3672 return (ENXIO); 3673 } 3674 3675 callout_init_mtx(&sc->rtsx_timeout_callout, &sc->rtsx_mtx, 0); 3676 3677 /* Allocate memory resource. */ 3678 if (sc->rtsx_device_id == RTSX_RTS525A) 3679 sc->rtsx_mem_res_id = PCIR_BAR(1); 3680 else 3681 sc->rtsx_mem_res_id = PCIR_BAR(0); 3682 sc->rtsx_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->rtsx_mem_res_id, RF_ACTIVE); 3683 if (sc->rtsx_mem_res == NULL) { 3684 device_printf(dev, "Can't allocate memory resource for %d\n", sc->rtsx_mem_res_id); 3685 goto destroy_rtsx_irq_res; 3686 } 3687 3688 if (bootverbose) 3689 device_printf(dev, "rtsx_irq_res_id: %d, rtsx_mem_res_id: %d\n", 3690 sc->rtsx_irq_res_id, sc->rtsx_mem_res_id); 3691 3692 sc->rtsx_mem_btag = rman_get_bustag(sc->rtsx_mem_res); 3693 sc->rtsx_mem_bhandle = rman_get_bushandle(sc->rtsx_mem_res); 3694 3695 TIMEOUT_TASK_INIT(taskqueue_swi_giant, &sc->rtsx_card_insert_task, 0, 3696 rtsx_card_task, sc); 3697 TASK_INIT(&sc->rtsx_card_remove_task, 0, rtsx_card_task, sc); 3698 3699 /* Allocate two DMA buffers: a command buffer and a data buffer. */ 3700 error = rtsx_dma_alloc(sc); 3701 if (error) 3702 goto destroy_rtsx_irq_res; 3703 3704 /* Activate the interrupt. */ 3705 error = bus_setup_intr(dev, sc->rtsx_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 3706 NULL, rtsx_intr, sc, &sc->rtsx_irq_cookie); 3707 if (error) { 3708 device_printf(dev, "Can't set up irq [0x%x]!\n", error); 3709 goto destroy_rtsx_mem_res; 3710 } 3711 pci_enable_busmaster(dev); 3712 3713 if (rtsx_read_cfg(sc, 0, RTSX_SDIOCFG_REG, &sdio_cfg) == 0) { 3714 if ((sdio_cfg & RTSX_SDIOCFG_SDIO_ONLY) || 3715 (sdio_cfg & RTSX_SDIOCFG_HAVE_SDIO)) 3716 sc->rtsx_flags |= RTSX_F_SDIO_SUPPORT; 3717 } 3718 3719 #ifdef MMCCAM 3720 sc->rtsx_ccb = NULL; 3721 sc->rtsx_cam_status = 0; 3722 3723 SYSCTL_ADD_U8(ctx, tree, OID_AUTO, "cam_status", CTLFLAG_RD, 3724 &sc->rtsx_cam_status, 0, "driver cam card present"); 3725 3726 if (mmc_cam_sim_alloc(dev, "rtsx_mmc", &sc->rtsx_mmc_sim) != 0) { 3727 device_printf(dev, "Can't allocate CAM SIM\n"); 3728 goto destroy_rtsx_irq; 3729 } 3730 #endif /* MMCCAM */ 3731 3732 /* Initialize device. */ 3733 error = rtsx_init(sc); 3734 if (error) { 3735 device_printf(dev, "Error %d during rtsx_init()\n", error); 3736 goto destroy_rtsx_irq; 3737 } 3738 3739 /* 3740 * Schedule a card detection as we won't get an interrupt 3741 * if the card is inserted when we attach. We wait a quarter 3742 * of a second to allow for a "spontaneous" interrupt which may 3743 * change the card presence state. This delay avoid a panic 3744 * on some configuration (e.g. Lenovo T540p). 3745 */ 3746 DELAY(250000); 3747 if (rtsx_is_card_present(sc)) 3748 device_printf(sc->rtsx_dev, "A card is detected\n"); 3749 else 3750 device_printf(sc->rtsx_dev, "No card is detected\n"); 3751 rtsx_card_task(sc, 0); 3752 3753 if (bootverbose) 3754 device_printf(dev, "Device attached\n"); 3755 3756 return (0); 3757 3758 destroy_rtsx_irq: 3759 bus_teardown_intr(dev, sc->rtsx_irq_res, sc->rtsx_irq_cookie); 3760 destroy_rtsx_mem_res: 3761 bus_release_resource(dev, SYS_RES_MEMORY, sc->rtsx_mem_res_id, 3762 sc->rtsx_mem_res); 3763 rtsx_dma_free(sc); 3764 destroy_rtsx_irq_res: 3765 callout_drain(&sc->rtsx_timeout_callout); 3766 bus_release_resource(dev, SYS_RES_IRQ, sc->rtsx_irq_res_id, 3767 sc->rtsx_irq_res); 3768 pci_release_msi(dev); 3769 RTSX_LOCK_DESTROY(sc); 3770 3771 return (ENXIO); 3772 } 3773 3774 static int 3775 rtsx_detach(device_t dev) 3776 { 3777 struct rtsx_softc *sc = device_get_softc(dev); 3778 int error; 3779 3780 if (bootverbose) 3781 device_printf(dev, "Detach - Vendor ID: 0x%x - Device ID: 0x%x\n", 3782 pci_get_vendor(dev), sc->rtsx_device_id); 3783 3784 /* Disable interrupts. */ 3785 sc->rtsx_intr_enabled = 0; 3786 WRITE4(sc, RTSX_BIER, sc->rtsx_intr_enabled); 3787 3788 /* Stop device. */ 3789 error = device_delete_children(sc->rtsx_dev); 3790 sc->rtsx_mmc_dev = NULL; 3791 if (error) 3792 return (error); 3793 3794 taskqueue_drain_timeout(taskqueue_swi_giant, &sc->rtsx_card_insert_task); 3795 taskqueue_drain(taskqueue_swi_giant, &sc->rtsx_card_remove_task); 3796 3797 /* Teardown the state in our softc created in our attach routine. */ 3798 rtsx_dma_free(sc); 3799 if (sc->rtsx_mem_res != NULL) 3800 bus_release_resource(dev, SYS_RES_MEMORY, sc->rtsx_mem_res_id, 3801 sc->rtsx_mem_res); 3802 if (sc->rtsx_irq_cookie != NULL) 3803 bus_teardown_intr(dev, sc->rtsx_irq_res, sc->rtsx_irq_cookie); 3804 if (sc->rtsx_irq_res != NULL) { 3805 callout_drain(&sc->rtsx_timeout_callout); 3806 bus_release_resource(dev, SYS_RES_IRQ, sc->rtsx_irq_res_id, 3807 sc->rtsx_irq_res); 3808 pci_release_msi(dev); 3809 } 3810 RTSX_LOCK_DESTROY(sc); 3811 #ifdef MMCCAM 3812 mmc_cam_sim_free(&sc->rtsx_mmc_sim); 3813 #endif /* MMCCAM */ 3814 3815 return (0); 3816 } 3817 3818 static int 3819 rtsx_shutdown(device_t dev) 3820 { 3821 if (bootverbose) 3822 device_printf(dev, "Shutdown\n"); 3823 3824 return (0); 3825 } 3826 3827 /* 3828 * Device suspend routine. 3829 */ 3830 static int 3831 rtsx_suspend(device_t dev) 3832 { 3833 struct rtsx_softc *sc = device_get_softc(dev); 3834 3835 device_printf(dev, "Suspend\n"); 3836 3837 #ifdef MMCCAM 3838 if (sc->rtsx_ccb != NULL) { 3839 device_printf(dev, "Request in progress: CMD%u, rtsr_intr_status: 0x%08x\n", 3840 sc->rtsx_ccb->mmcio.cmd.opcode, sc->rtsx_intr_status); 3841 } 3842 #else /* !MMCCAM */ 3843 if (sc->rtsx_req != NULL) { 3844 device_printf(dev, "Request in progress: CMD%u, rtsr_intr_status: 0x%08x\n", 3845 sc->rtsx_req->cmd->opcode, sc->rtsx_intr_status); 3846 } 3847 #endif /* MMCCAM */ 3848 3849 bus_generic_suspend(dev); 3850 3851 return (0); 3852 } 3853 3854 /* 3855 * Device resume routine. 3856 */ 3857 static int 3858 rtsx_resume(device_t dev) 3859 { 3860 device_printf(dev, "Resume\n"); 3861 3862 rtsx_init(device_get_softc(dev)); 3863 3864 bus_generic_resume(dev); 3865 3866 return (0); 3867 } 3868 3869 static device_method_t rtsx_methods[] = { 3870 /* Device interface */ 3871 DEVMETHOD(device_probe, rtsx_probe), 3872 DEVMETHOD(device_attach, rtsx_attach), 3873 DEVMETHOD(device_detach, rtsx_detach), 3874 DEVMETHOD(device_shutdown, rtsx_shutdown), 3875 DEVMETHOD(device_suspend, rtsx_suspend), 3876 DEVMETHOD(device_resume, rtsx_resume), 3877 3878 /* Bus interface */ 3879 DEVMETHOD(bus_read_ivar, rtsx_read_ivar), 3880 DEVMETHOD(bus_write_ivar, rtsx_write_ivar), 3881 3882 #ifndef MMCCAM 3883 /* MMC bridge interface */ 3884 DEVMETHOD(mmcbr_update_ios, rtsx_mmcbr_update_ios), 3885 DEVMETHOD(mmcbr_switch_vccq, rtsx_mmcbr_switch_vccq), 3886 DEVMETHOD(mmcbr_tune, rtsx_mmcbr_tune), 3887 DEVMETHOD(mmcbr_retune, rtsx_mmcbr_retune), 3888 DEVMETHOD(mmcbr_request, rtsx_mmcbr_request), 3889 DEVMETHOD(mmcbr_get_ro, rtsx_mmcbr_get_ro), 3890 DEVMETHOD(mmcbr_acquire_host, rtsx_mmcbr_acquire_host), 3891 DEVMETHOD(mmcbr_release_host, rtsx_mmcbr_release_host), 3892 #endif /* !MMCCAM */ 3893 3894 #ifdef MMCCAM 3895 /* MMCCAM interface */ 3896 DEVMETHOD(mmc_sim_get_tran_settings, rtsx_get_tran_settings), 3897 DEVMETHOD(mmc_sim_set_tran_settings, rtsx_set_tran_settings), 3898 DEVMETHOD(mmc_sim_cam_request, rtsx_cam_request), 3899 #endif /* MMCCAM */ 3900 3901 DEVMETHOD_END 3902 }; 3903 3904 DEFINE_CLASS_0(rtsx, rtsx_driver, rtsx_methods, sizeof(struct rtsx_softc)); 3905 DRIVER_MODULE(rtsx, pci, rtsx_driver, NULL, NULL); 3906 3907 /* For Plug and Play */ 3908 MODULE_PNP_INFO("U16:device;D:#;T:vendor=0x10ec", pci, rtsx, 3909 rtsx_ids, nitems(rtsx_ids)); 3910 3911 #ifndef MMCCAM 3912 MMC_DECLARE_BRIDGE(rtsx); 3913 #endif /* !MMCCAM */ 3914