1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 5 * Copyright (c) 2012 Stefan Sperling <stsp@openbsd.org> 6 * Copyright (c) 2020 Henri Hennebert <hlh@restart.be> 7 * Copyright (c) 2020 Gary Jennejohn <gj@freebsd.org> 8 * Copyright (c) 2020 Jesper Schmitz Mouridsen <jsm@FreeBSD.org> 9 * All rights reserved. 10 * 11 * Patch from: 12 * - Lutz Bichler <Lutz.Bichler@gmail.com> 13 * 14 * Base on OpenBSD /sys/dev/pci/rtsx_pci.c & /dev/ic/rtsx.c 15 * on Linux /drivers/mmc/host/rtsx_pci_sdmmc.c, 16 * /include/linux/rtsx_pci.h & 17 * /drivers/misc/cardreader/rtsx_pcr.c 18 * on NetBSD /sys/dev/ic/rtsx.c 19 * 20 * Permission to use, copy, modify, and distribute this software for any 21 * purpose with or without fee is hereby granted, provided that the above 22 * copyright notice and this permission notice appear in all copies. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 __FBSDID("$FreeBSD$"); 39 40 #include <sys/param.h> 41 #include <sys/module.h> 42 #include <sys/systm.h> /* For FreeBSD 11 */ 43 #include <sys/types.h> /* For FreeBSD 11 */ 44 #include <sys/errno.h> 45 #include <sys/kernel.h> 46 #include <sys/bus.h> 47 #include <sys/endian.h> 48 #include <machine/bus.h> 49 #include <sys/mutex.h> 50 #include <sys/malloc.h> 51 #include <sys/rman.h> 52 #include <sys/queue.h> 53 #include <sys/taskqueue.h> 54 #include <sys/sysctl.h> 55 #include <dev/pci/pcivar.h> 56 #include <dev/pci/pcireg.h> 57 #include <dev/mmc/bridge.h> 58 #include <dev/mmc/mmcreg.h> 59 #include <dev/mmc/mmcbrvar.h> 60 #include <machine/_inttypes.h> 61 62 #include "opt_mmccam.h" 63 64 #ifdef MMCCAM 65 #include <cam/cam.h> 66 #include <cam/cam_ccb.h> 67 #include <cam/cam_debug.h> 68 #include <cam/cam_sim.h> 69 #include <cam/cam_xpt_sim.h> 70 #endif /* MMCCAM */ 71 72 #include "rtsxreg.h" 73 74 /* The softc holds our per-instance data. */ 75 struct rtsx_softc { 76 struct mtx rtsx_mtx; /* device mutex */ 77 device_t rtsx_dev; /* device */ 78 uint16_t rtsx_flags; /* device flags */ 79 uint16_t rtsx_device_id; /* device ID */ 80 device_t rtsx_mmc_dev; /* device of mmc bus */ 81 uint32_t rtsx_intr_enabled; /* enabled interrupts */ 82 uint32_t rtsx_intr_status; /* soft interrupt status */ 83 int rtsx_irq_res_id; /* bus IRQ resource id */ 84 struct resource *rtsx_irq_res; /* bus IRQ resource */ 85 void *rtsx_irq_cookie; /* bus IRQ resource cookie */ 86 struct callout rtsx_timeout_callout; /* callout for timeout */ 87 int rtsx_timeout_cmd; /* interrupt timeout for setup commands */ 88 int rtsx_timeout_io; /* interrupt timeout for I/O commands */ 89 void (*rtsx_intr_trans_ok)(struct rtsx_softc *sc); 90 /* function to call if transfer succeed */ 91 void (*rtsx_intr_trans_ko)(struct rtsx_softc *sc); 92 /* function to call if transfer fail */ 93 94 struct timeout_task 95 rtsx_card_insert_task; /* card insert delayed task */ 96 struct task rtsx_card_remove_task; /* card remove task */ 97 98 int rtsx_res_id; /* bus memory resource id */ 99 struct resource *rtsx_res; /* bus memory resource */ 100 int rtsx_res_type; /* bus memory resource type */ 101 bus_space_tag_t rtsx_btag; /* host register set tag */ 102 bus_space_handle_t rtsx_bhandle; /* host register set handle */ 103 104 bus_dma_tag_t rtsx_cmd_dma_tag; /* DMA tag for command transfer */ 105 bus_dmamap_t rtsx_cmd_dmamap; /* DMA map for command transfer */ 106 void *rtsx_cmd_dmamem; /* DMA mem for command transfer */ 107 bus_addr_t rtsx_cmd_buffer; /* device visible address of the DMA segment */ 108 int rtsx_cmd_index; /* index in rtsx_cmd_buffer */ 109 110 bus_dma_tag_t rtsx_data_dma_tag; /* DMA tag for data transfer */ 111 bus_dmamap_t rtsx_data_dmamap; /* DMA map for data transfer */ 112 void *rtsx_data_dmamem; /* DMA mem for data transfer */ 113 bus_addr_t rtsx_data_buffer; /* device visible address of the DMA segment */ 114 115 #ifdef MMCCAM 116 struct cam_devq *rtsx_devq; /* CAM queue of requests */ 117 struct cam_sim *rtsx_sim; /* descriptor of our SCSI Interface Modules (SIM) */ 118 struct mtx rtsx_sim_mtx; /* SIM mutex */ 119 union ccb *rtsx_ccb; /* CAM control block */ 120 struct mmc_request rtsx_cam_req; /* CAM MMC request */ 121 #endif /* MMCCAM */ 122 123 struct mmc_request *rtsx_req; /* MMC request */ 124 struct mmc_host rtsx_host; /* host parameters */ 125 int rtsx_pcie_cap; /* PCIe capability offset */ 126 int8_t rtsx_bus_busy; /* bus busy status */ 127 int8_t rtsx_ios_bus_width; /* current host.ios.bus_width */ 128 int32_t rtsx_ios_clock; /* current host.ios.clock */ 129 int8_t rtsx_ios_power_mode; /* current host.ios.power mode */ 130 int8_t rtsx_ios_timing; /* current host.ios.timing */ 131 int8_t rtsx_ios_vccq; /* current host.ios.vccq */ 132 uint8_t rtsx_read_only; /* card read only status */ 133 uint8_t rtsx_inversion; /* inversion of card detection and read only status */ 134 uint8_t rtsx_force_timing; /* force bus_timing_uhs_sdr50 */ 135 uint8_t rtsx_debug; /* print debugging */ 136 #ifdef MMCCAM 137 uint8_t rtsx_cam_status; /* CAM status - 1 if card in use */ 138 #endif /* MMCCAM */ 139 uint64_t rtsx_read_count; /* count of read operations */ 140 uint64_t rtsx_write_count; /* count of write operations */ 141 bool rtsx_discovery_mode; /* are we in discovery mode? */ 142 bool rtsx_tuning_mode; /* are we tuning */ 143 bool rtsx_double_clk; /* double clock freqency */ 144 bool rtsx_vpclk; /* voltage at Pulse-width Modulation(PWM) clock? */ 145 uint8_t rtsx_ssc_depth; /* Spread spectrum clocking depth */ 146 uint8_t rtsx_card_drive_sel; /* value for RTSX_CARD_DRIVE_SEL */ 147 uint8_t rtsx_sd30_drive_sel_3v3;/* value for RTSX_SD30_DRIVE_SEL */ 148 }; 149 150 /* rtsx_flags values */ 151 #define RTSX_F_DEFAULT 0x0000 152 #define RTSX_F_CARD_PRESENT 0x0001 153 #define RTSX_F_SDIO_SUPPORT 0x0002 154 #define RTSX_F_VERSION_A 0x0004 155 #define RTSX_F_VERSION_B 0x0008 156 #define RTSX_F_VERSION_C 0x0010 157 #define RTSX_F_VERSION_D 0x0020 158 #define RTSX_F_8411B_QFN48 0x0040 159 #define RTSX_F_REVERSE_SOCKET 0x0080 160 161 #define RTSX_REALTEK 0x10ec 162 #define RTSX_RTS5209 0x5209 163 #define RTSX_RTS5227 0x5227 164 #define RTSX_RTS5229 0x5229 165 #define RTSX_RTS522A 0x522a 166 #define RTSX_RTS525A 0x525a 167 #define RTSX_RTS5249 0x5249 168 #define RTSX_RTL8402 0x5286 169 #define RTSX_RTL8411 0x5289 170 #define RTSX_RTL8411B 0x5287 171 172 #define RTSX_VERSION "2.0i" 173 174 static const struct rtsx_device { 175 uint16_t vendor_id; 176 uint16_t device_id; 177 const char *desc; 178 } rtsx_devices[] = { 179 { RTSX_REALTEK, RTSX_RTS5209, RTSX_VERSION " Realtek RTS5209 PCIe MMC/SD Card Reader"}, 180 { RTSX_REALTEK, RTSX_RTS5227, RTSX_VERSION " Realtek RTS5227 PCIe MMC/SD Card Reader"}, 181 { RTSX_REALTEK, RTSX_RTS5229, RTSX_VERSION " Realtek RTS5229 PCIe MMC/SD Card Reader"}, 182 { RTSX_REALTEK, RTSX_RTS522A, RTSX_VERSION " Realtek RTS522A PCIe MMC/SD Card Reader"}, 183 { RTSX_REALTEK, RTSX_RTS525A, RTSX_VERSION " Realtek RTS525A PCIe MMC/SD Card Reader"}, 184 { RTSX_REALTEK, RTSX_RTS5249, RTSX_VERSION " Realtek RTS5249 PCIe MMC/SD Card Reader"}, 185 { RTSX_REALTEK, RTSX_RTL8402, RTSX_VERSION " Realtek RTL8402 PCIe MMC/SD Card Reader"}, 186 { RTSX_REALTEK, RTSX_RTL8411, RTSX_VERSION " Realtek RTL8411 PCIe MMC/SD Card Reader"}, 187 { RTSX_REALTEK, RTSX_RTL8411B, RTSX_VERSION " Realtek RTL8411B PCIe MMC/SD Card Reader"}, 188 { 0, 0, NULL} 189 }; 190 191 /* See `kenv | grep smbios.system` */ 192 static const struct rtsx_inversion_model { 193 char *maker; 194 char *family; 195 char *product; 196 } rtsx_inversion_models[] = { 197 { "LENOVO", "ThinkPad T470p", "20J7S0PM00"}, 198 { NULL, NULL, NULL} 199 }; 200 201 static int rtsx_dma_alloc(struct rtsx_softc *sc); 202 static void rtsx_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 203 static void rtsx_dma_free(struct rtsx_softc *sc); 204 static void rtsx_intr(void *arg); 205 static void rtsx_handle_card_present(struct rtsx_softc *sc); 206 static void rtsx_card_task(void *arg, int pending __unused); 207 static bool rtsx_is_card_present(struct rtsx_softc *sc); 208 static int rtsx_init(struct rtsx_softc *sc); 209 static int rtsx_map_sd_drive(int index); 210 static int rtsx_rts5227_fill_driving(struct rtsx_softc *sc); 211 static int rtsx_rts5249_fill_driving(struct rtsx_softc *sc); 212 static int rtsx_read(struct rtsx_softc *, uint16_t, uint8_t *); 213 static int rtsx_read_cfg(struct rtsx_softc *sc, uint8_t func, uint16_t addr, uint32_t *val); 214 static int rtsx_write(struct rtsx_softc *sc, uint16_t addr, uint8_t mask, uint8_t val); 215 static int rtsx_read_phy(struct rtsx_softc *sc, uint8_t addr, uint16_t *val); 216 static int rtsx_write_phy(struct rtsx_softc *sc, uint8_t addr, uint16_t val); 217 static int rtsx_bus_power_off(struct rtsx_softc *sc); 218 static int rtsx_bus_power_on(struct rtsx_softc *sc); 219 static int rtsx_set_bus_width(struct rtsx_softc *sc, enum mmc_bus_width width); 220 static int rtsx_set_sd_timing(struct rtsx_softc *sc, enum mmc_bus_timing timing); 221 static int rtsx_set_sd_clock(struct rtsx_softc *sc, uint32_t freq); 222 static int rtsx_stop_sd_clock(struct rtsx_softc *sc); 223 static int rtsx_switch_sd_clock(struct rtsx_softc *sc, uint8_t clk, uint8_t n, uint8_t div, uint8_t mcu); 224 static void rtsx_sd_change_tx_phase(struct rtsx_softc *sc, uint8_t sample_point); 225 static void rtsx_sd_change_rx_phase(struct rtsx_softc *sc, uint8_t sample_point); 226 static void rtsx_sd_tuning_rx_phase(struct rtsx_softc *sc, uint32_t *phase_map); 227 static int rtsx_sd_tuning_rx_cmd(struct rtsx_softc *sc, uint8_t sample_point); 228 static int rtsx_sd_tuning_rx_cmd_wait(struct rtsx_softc *sc, struct mmc_command *cmd); 229 static void rtsx_sd_tuning_rx_cmd_wakeup(struct rtsx_softc *sc); 230 static void rtsx_sd_wait_data_idle(struct rtsx_softc *sc); 231 static uint8_t rtsx_sd_search_final_rx_phase(struct rtsx_softc *sc, uint32_t phase_map); 232 static int rtsx_sd_get_rx_phase_len(uint32_t phase_map, int start_bit); 233 #if 0 /* For led */ 234 static int rtsx_led_enable(struct rtsx_softc *sc); 235 static int rtsx_led_disable(struct rtsx_softc *sc); 236 #endif /* For led */ 237 static uint8_t rtsx_response_type(uint16_t mmc_rsp); 238 static void rtsx_init_cmd(struct rtsx_softc *sc, struct mmc_command *cmd); 239 static void rtsx_push_cmd(struct rtsx_softc *sc, uint8_t cmd, uint16_t reg, 240 uint8_t mask, uint8_t data); 241 static void rtsx_set_cmd_data_len(struct rtsx_softc *sc, uint16_t block_cnt, uint16_t byte_cnt); 242 static void rtsx_send_cmd(struct rtsx_softc *sc); 243 static void rtsx_ret_resp(struct rtsx_softc *sc); 244 static void rtsx_set_resp(struct rtsx_softc *sc, struct mmc_command *cmd); 245 static void rtsx_stop_cmd(struct rtsx_softc *sc); 246 static void rtsx_clear_error(struct rtsx_softc *sc); 247 static void rtsx_req_done(struct rtsx_softc *sc); 248 static int rtsx_send_req(struct rtsx_softc *sc, struct mmc_command *cmd); 249 static int rtsx_xfer_short(struct rtsx_softc *sc, struct mmc_command *cmd); 250 static void rtsx_ask_ppbuf_part1(struct rtsx_softc *sc); 251 static void rtsx_get_ppbuf_part1(struct rtsx_softc *sc); 252 static void rtsx_get_ppbuf_part2(struct rtsx_softc *sc); 253 static void rtsx_put_ppbuf_part1(struct rtsx_softc *sc); 254 static void rtsx_put_ppbuf_part2(struct rtsx_softc *sc); 255 static void rtsx_write_ppbuf(struct rtsx_softc *sc); 256 static int rtsx_xfer(struct rtsx_softc *sc, struct mmc_command *cmd); 257 static void rtsx_xfer_begin(struct rtsx_softc *sc); 258 static void rtsx_xfer_start(struct rtsx_softc *sc); 259 static void rtsx_xfer_finish(struct rtsx_softc *sc); 260 static void rtsx_timeout(void *arg); 261 262 #ifdef MMCCAM 263 static void rtsx_cam_action(struct cam_sim *sim, union ccb *ccb); 264 static void rtsx_cam_poll(struct cam_sim *sim); 265 static void rtsx_cam_set_tran_settings(struct rtsx_softc *sc, union ccb *ccb); 266 static void rtsx_cam_request(struct rtsx_softc *sc, union ccb *ccb); 267 #endif /* MMCCAM */ 268 269 static int rtsx_read_ivar(device_t bus, device_t child, int which, uintptr_t *result); 270 static int rtsx_write_ivar(device_t bus, device_t child, int which, uintptr_t value); 271 272 static int rtsx_mmcbr_update_ios(device_t bus, device_t child __unused); 273 static int rtsx_mmcbr_switch_vccq(device_t bus, device_t child __unused); 274 static int rtsx_mmcbr_tune(device_t bus, device_t child __unused, bool hs400 __unused); 275 static int rtsx_mmcbr_retune(device_t bus, device_t child __unused, bool reset __unused); 276 static int rtsx_mmcbr_request(device_t bus, device_t child __unused, struct mmc_request *req); 277 static int rtsx_mmcbr_get_ro(device_t bus, device_t child __unused); 278 static int rtsx_mmcbr_acquire_host(device_t bus, device_t child __unused); 279 static int rtsx_mmcbr_release_host(device_t bus, device_t child __unused); 280 281 static int rtsx_probe(device_t dev); 282 static int rtsx_attach(device_t dev); 283 static int rtsx_detach(device_t dev); 284 static int rtsx_shutdown(device_t dev); 285 static int rtsx_suspend(device_t dev); 286 static int rtsx_resume(device_t dev); 287 288 #define RTSX_LOCK_INIT(_sc) mtx_init(&(_sc)->rtsx_mtx, \ 289 device_get_nameunit(sc->rtsx_dev), "rtsx", MTX_DEF) 290 #define RTSX_LOCK(_sc) mtx_lock(&(_sc)->rtsx_mtx) 291 #define RTSX_UNLOCK(_sc) mtx_unlock(&(_sc)->rtsx_mtx) 292 #define RTSX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rtsx_mtx) 293 294 #define RTSX_SDCLK_OFF 0 295 #define RTSX_SDCLK_250KHZ 250000 296 #define RTSX_SDCLK_400KHZ 400000 297 #define RTSX_SDCLK_25MHZ 25000000 298 #define RTSX_SDCLK_50MHZ 50000000 299 #define RTSX_SDCLK_100MHZ 100000000 300 #define RTSX_SDCLK_208MHZ 208000000 301 302 #define RTSX_MIN_DIV_N 80 303 #define RTSX_MAX_DIV_N 208 304 305 #define RTSX_MAX_DATA_BLKLEN 512 306 307 #define RTSX_DMA_ALIGN 4 308 #define RTSX_HOSTCMD_MAX 256 309 #define RTSX_DMA_CMD_BIFSIZE (sizeof(uint32_t) * RTSX_HOSTCMD_MAX) 310 #define RTSX_DMA_DATA_BUFSIZE MAXPHYS 311 312 #define ISSET(t, f) ((t) & (f)) 313 314 #define READ4(sc, reg) \ 315 (bus_space_read_4((sc)->rtsx_btag, (sc)->rtsx_bhandle, (reg))) 316 #define WRITE4(sc, reg, val) \ 317 (bus_space_write_4((sc)->rtsx_btag, (sc)->rtsx_bhandle, (reg), (val))) 318 319 #define RTSX_READ(sc, reg, val) \ 320 do { \ 321 int err = rtsx_read((sc), (reg), (val)); \ 322 if (err) \ 323 return (err); \ 324 } while (0) 325 326 #define RTSX_WRITE(sc, reg, val) \ 327 do { \ 328 int err = rtsx_write((sc), (reg), 0xff, (val)); \ 329 if (err) \ 330 return (err); \ 331 } while (0) 332 #define RTSX_CLR(sc, reg, bits) \ 333 do { \ 334 int err = rtsx_write((sc), (reg), (bits), 0); \ 335 if (err) \ 336 return (err); \ 337 } while (0) 338 339 #define RTSX_SET(sc, reg, bits) \ 340 do { \ 341 int err = rtsx_write((sc), (reg), (bits), 0xff);\ 342 if (err) \ 343 return (err); \ 344 } while (0) 345 346 #define RTSX_BITOP(sc, reg, mask, bits) \ 347 do { \ 348 int err = rtsx_write((sc), (reg), (mask), (bits)); \ 349 if (err) \ 350 return (err); \ 351 } while (0) 352 353 /* 354 * We use two DMA buffers: a command buffer and a data buffer. 355 * 356 * The command buffer contains a command queue for the host controller, 357 * which describes SD/MMC commands to run, and other parameters. The chip 358 * runs the command queue when a special bit in the RTSX_HCBAR register is 359 * set and signals completion with the RTSX_TRANS_OK_INT interrupt. 360 * Each command is encoded as a 4 byte sequence containing command number 361 * (read, write, or check a host controller register), a register address, 362 * and a data bit-mask and value. 363 * SD/MMC commands which do not transfer any data from/to the card only use 364 * the command buffer. 365 * 366 * The data buffer is used for transfer longer than 512. Data transfer is 367 * controlled via the RTSX_HDBAR register and completion is signalled by 368 * the RTSX_TRANS_OK_INT interrupt. 369 * 370 * The chip is unable to perform DMA above 4GB. 371 */ 372 373 /* 374 * Main commands in the usual seqence used: 375 * 376 * CMD0 Go idle state 377 * CMD8 Send interface condition 378 * CMD55 Application Command for next ACMD 379 * ACMD41 Send Operation Conditions Register (OCR: voltage profile of the card) 380 * CMD2 Send Card Identification (CID) Register 381 * CMD3 Send relative address 382 * CMD9 Send Card Specific Data (CSD) 383 * CMD13 Send status (32 bits - bit 25: card password protected) 384 * CMD7 Select card (before Get card SCR) 385 * ACMD51 Send SCR (SD CARD Configuration Register - [51:48]: Bus widths supported) 386 * CMD6 SD switch function 387 * ACMD13 Send SD status (512 bits) 388 * ACMD42 Set/Clear card detect 389 * ACMD6 Set bus width 390 * CMD19 Send tuning block 391 * CMD12 Stop transmission 392 * 393 * CMD17 Read single block (<=512) 394 * CMD18 Read multiple blocks (>512) 395 * CMD24 Write single block (<=512) 396 * CMD25 Write multiple blocks (>512) 397 * 398 * CMD52 IO R/W direct 399 * CMD5 Send Operation Conditions 400 */ 401 402 static int 403 rtsx_dma_alloc(struct rtsx_softc *sc) 404 { 405 int error = 0; 406 407 error = bus_dma_tag_create(bus_get_dma_tag(sc->rtsx_dev), /* inherit from parent */ 408 RTSX_DMA_ALIGN, 0, /* alignment, boundary */ 409 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 410 BUS_SPACE_MAXADDR, /* highaddr */ 411 NULL, NULL, /* filter, filterarg */ 412 RTSX_DMA_CMD_BIFSIZE, 1, /* maxsize, nsegments */ 413 RTSX_DMA_CMD_BIFSIZE, /* maxsegsize */ 414 0, /* flags */ 415 NULL, NULL, /* lockfunc, lockarg */ 416 &sc->rtsx_cmd_dma_tag); 417 if (error) { 418 device_printf(sc->rtsx_dev, 419 "Can't create cmd parent DMA tag\n"); 420 return (error); 421 } 422 error = bus_dmamem_alloc(sc->rtsx_cmd_dma_tag, /* DMA tag */ 423 &sc->rtsx_cmd_dmamem, /* will hold the KVA pointer */ 424 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, /* flags */ 425 &sc->rtsx_cmd_dmamap); /* DMA map */ 426 if (error) { 427 device_printf(sc->rtsx_dev, 428 "Can't create DMA map for command transfer\n"); 429 goto destroy_cmd_dma_tag; 430 431 } 432 error = bus_dmamap_load(sc->rtsx_cmd_dma_tag, /* DMA tag */ 433 sc->rtsx_cmd_dmamap, /* DMA map */ 434 sc->rtsx_cmd_dmamem, /* KVA pointer to be mapped */ 435 RTSX_DMA_CMD_BIFSIZE, /* size of buffer */ 436 rtsx_dmamap_cb, /* callback */ 437 &sc->rtsx_cmd_buffer, /* first arg of callback */ 438 0); /* flags */ 439 if (error || sc->rtsx_cmd_buffer == 0) { 440 device_printf(sc->rtsx_dev, 441 "Can't load DMA memory for command transfer\n"); 442 error = (error) ? error : EFAULT; 443 goto destroy_cmd_dmamem_alloc; 444 } 445 446 error = bus_dma_tag_create(bus_get_dma_tag(sc->rtsx_dev), /* inherit from parent */ 447 RTSX_DMA_DATA_BUFSIZE, 0, /* alignment, boundary */ 448 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 449 BUS_SPACE_MAXADDR, /* highaddr */ 450 NULL, NULL, /* filter, filterarg */ 451 RTSX_DMA_DATA_BUFSIZE, 1, /* maxsize, nsegments */ 452 RTSX_DMA_DATA_BUFSIZE, /* maxsegsize */ 453 0, /* flags */ 454 NULL, NULL, /* lockfunc, lockarg */ 455 &sc->rtsx_data_dma_tag); 456 if (error) { 457 device_printf(sc->rtsx_dev, 458 "Can't create data parent DMA tag\n"); 459 goto destroy_cmd_dmamap_load; 460 } 461 error = bus_dmamem_alloc(sc->rtsx_data_dma_tag, /* DMA tag */ 462 &sc->rtsx_data_dmamem, /* will hold the KVA pointer */ 463 BUS_DMA_WAITOK | BUS_DMA_ZERO, /* flags */ 464 &sc->rtsx_data_dmamap); /* DMA map */ 465 if (error) { 466 device_printf(sc->rtsx_dev, 467 "Can't create DMA map for data transfer\n"); 468 goto destroy_data_dma_tag; 469 } 470 error = bus_dmamap_load(sc->rtsx_data_dma_tag, /* DMA tag */ 471 sc->rtsx_data_dmamap, /* DMA map */ 472 sc->rtsx_data_dmamem, /* KVA pointer to be mapped */ 473 RTSX_DMA_DATA_BUFSIZE, /* size of buffer */ 474 rtsx_dmamap_cb, /* callback */ 475 &sc->rtsx_data_buffer, /* first arg of callback */ 476 0); /* flags */ 477 if (error || sc->rtsx_data_buffer == 0) { 478 device_printf(sc->rtsx_dev, 479 "Can't load DMA memory for data transfer\n"); 480 error = (error) ? error : EFAULT; 481 goto destroy_data_dmamem_alloc; 482 } 483 return (error); 484 485 destroy_data_dmamem_alloc: 486 bus_dmamem_free(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamem, sc->rtsx_data_dmamap); 487 destroy_data_dma_tag: 488 bus_dma_tag_destroy(sc->rtsx_data_dma_tag); 489 destroy_cmd_dmamap_load: 490 bus_dmamap_unload(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap); 491 destroy_cmd_dmamem_alloc: 492 bus_dmamem_free(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamem, sc->rtsx_cmd_dmamap); 493 destroy_cmd_dma_tag: 494 bus_dma_tag_destroy(sc->rtsx_cmd_dma_tag); 495 496 return (error); 497 } 498 499 static void 500 rtsx_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 501 { 502 if (error) { 503 printf("rtsx_dmamap_cb: error %d\n", error); 504 return; 505 } 506 *(bus_addr_t *)arg = segs[0].ds_addr; 507 } 508 509 static void 510 rtsx_dma_free(struct rtsx_softc *sc) 511 { 512 if (sc->rtsx_cmd_dma_tag != NULL) { 513 if (sc->rtsx_cmd_dmamap != NULL) 514 bus_dmamap_unload(sc->rtsx_cmd_dma_tag, 515 sc->rtsx_cmd_dmamap); 516 if (sc->rtsx_cmd_dmamem != NULL) 517 bus_dmamem_free(sc->rtsx_cmd_dma_tag, 518 sc->rtsx_cmd_dmamem, 519 sc->rtsx_cmd_dmamap); 520 sc->rtsx_cmd_dmamap = NULL; 521 sc->rtsx_cmd_dmamem = NULL; 522 sc->rtsx_cmd_buffer = 0; 523 bus_dma_tag_destroy(sc->rtsx_cmd_dma_tag); 524 sc->rtsx_cmd_dma_tag = NULL; 525 } 526 if (sc->rtsx_data_dma_tag != NULL) { 527 if (sc->rtsx_data_dmamap != NULL) 528 bus_dmamap_unload(sc->rtsx_data_dma_tag, 529 sc->rtsx_data_dmamap); 530 if (sc->rtsx_data_dmamem != NULL) 531 bus_dmamem_free(sc->rtsx_data_dma_tag, 532 sc->rtsx_data_dmamem, 533 sc->rtsx_data_dmamap); 534 sc->rtsx_data_dmamap = NULL; 535 sc->rtsx_data_dmamem = NULL; 536 sc->rtsx_data_buffer = 0; 537 bus_dma_tag_destroy(sc->rtsx_data_dma_tag); 538 sc->rtsx_data_dma_tag = NULL; 539 } 540 } 541 542 static void 543 rtsx_intr(void *arg) 544 { 545 struct rtsx_softc *sc = arg; 546 uint32_t enabled; 547 uint32_t status; 548 549 RTSX_LOCK(sc); 550 551 enabled = sc->rtsx_intr_enabled; 552 status = READ4(sc, RTSX_BIPR); /* read Bus Interrupt Pending Register */ 553 sc->rtsx_intr_status = status; 554 555 if (bootverbose) 556 device_printf(sc->rtsx_dev, "Interrupt handler - enabled: 0x%08x, status: 0x%08x\n", enabled, status); 557 558 /* Ack interrupts. */ 559 WRITE4(sc, RTSX_BIPR, status); 560 561 if (((enabled & status) == 0) || status == 0xffffffff) { 562 device_printf(sc->rtsx_dev, "Spurious interrupt - enabled: 0x%08x, status: 0x%08x\n", enabled, status); 563 RTSX_UNLOCK(sc); 564 return; 565 } 566 567 /* Detect write protect. */ 568 if (status & RTSX_SD_WRITE_PROTECT) 569 sc->rtsx_read_only = 1; 570 else 571 sc->rtsx_read_only = 0; 572 573 /* Start task to handle SD card status change (from dwmmc.c). */ 574 if (status & RTSX_SD_INT) { 575 device_printf(sc->rtsx_dev, "Interrupt card inserted/removed\n"); 576 rtsx_handle_card_present(sc); 577 } 578 579 if (sc->rtsx_req == NULL) { 580 RTSX_UNLOCK(sc); 581 return; 582 } 583 584 if (status & RTSX_TRANS_OK_INT) { 585 sc->rtsx_req->cmd->error = MMC_ERR_NONE; 586 if (sc->rtsx_intr_trans_ok != NULL) 587 sc->rtsx_intr_trans_ok(sc); 588 } else if (status & RTSX_TRANS_FAIL_INT) { 589 uint8_t stat1; 590 sc->rtsx_req->cmd->error = MMC_ERR_FAILED; 591 if (rtsx_read(sc, RTSX_SD_STAT1, &stat1) == 0 && 592 (stat1 & RTSX_SD_CRC_ERR)) { 593 device_printf(sc->rtsx_dev, "CRC error\n"); 594 sc->rtsx_req->cmd->error = MMC_ERR_BADCRC; 595 } 596 if (!sc->rtsx_tuning_mode) 597 device_printf(sc->rtsx_dev, "Transfer fail - status: 0x%08x\n", status); 598 rtsx_stop_cmd(sc); 599 if (sc->rtsx_intr_trans_ko != NULL) 600 sc->rtsx_intr_trans_ko(sc); 601 } 602 603 RTSX_UNLOCK(sc); 604 } 605 606 /* 607 * Function called from the IRQ handler (from dwmmc.c). 608 */ 609 static void 610 rtsx_handle_card_present(struct rtsx_softc *sc) 611 { 612 bool was_present; 613 bool is_present; 614 615 #ifdef MMCCAM 616 was_present = sc->rtsx_cam_status; 617 #else /* !MMCCAM */ 618 was_present = sc->rtsx_mmc_dev != NULL; 619 #endif /* MMCCAM */ 620 is_present = rtsx_is_card_present(sc); 621 if (is_present) 622 device_printf(sc->rtsx_dev, "Card present\n"); 623 else 624 device_printf(sc->rtsx_dev, "Card absent\n"); 625 626 if (!was_present && is_present) { 627 /* 628 * The delay is to debounce the card insert 629 * (sometimes the card detect pin stabilizes 630 * before the other pins have made good contact). 631 */ 632 taskqueue_enqueue_timeout(taskqueue_swi_giant, 633 &sc->rtsx_card_insert_task, -hz); 634 } else if (was_present && !is_present) { 635 taskqueue_enqueue(taskqueue_swi_giant, &sc->rtsx_card_remove_task); 636 } 637 } 638 639 /* 640 * This function is called at startup. 641 */ 642 static void 643 rtsx_card_task(void *arg, int pending __unused) 644 { 645 struct rtsx_softc *sc = arg; 646 647 RTSX_LOCK(sc); 648 649 if (rtsx_is_card_present(sc)) { 650 sc->rtsx_flags |= RTSX_F_CARD_PRESENT; 651 /* Card is present, attach if necessary. */ 652 #ifdef MMCCAM 653 if (sc->rtsx_cam_status == 0) { 654 union ccb *ccb; 655 uint32_t pathid; 656 #else /* !MMCCAM */ 657 if (sc->rtsx_mmc_dev == NULL) { 658 #endif /* MMCCAM */ 659 if (bootverbose) 660 device_printf(sc->rtsx_dev, "Card inserted\n"); 661 662 sc->rtsx_read_count = sc->rtsx_write_count = 0; 663 #ifdef MMCCAM 664 sc->rtsx_cam_status = 1; 665 pathid = cam_sim_path(sc->rtsx_sim); 666 ccb = xpt_alloc_ccb_nowait(); 667 if (ccb == NULL) { 668 device_printf(sc->rtsx_dev, "Unable to alloc CCB for rescan\n"); 669 RTSX_UNLOCK(sc); 670 return; 671 } 672 /* 673 * We create a rescan request for BUS:0:0, since the card 674 * will be at lun 0. 675 */ 676 if (xpt_create_path(&ccb->ccb_h.path, NULL, pathid, 677 /* target */ 0, /* lun */ 0) != CAM_REQ_CMP) { 678 device_printf(sc->rtsx_dev, "Unable to create path for rescan\n"); 679 RTSX_UNLOCK(sc); 680 xpt_free_ccb(ccb); 681 return; 682 } 683 RTSX_UNLOCK(sc); 684 xpt_rescan(ccb); 685 #else /* !MMCCAM */ 686 sc->rtsx_mmc_dev = device_add_child(sc->rtsx_dev, "mmc", -1); 687 RTSX_UNLOCK(sc); 688 if (sc->rtsx_mmc_dev == NULL) { 689 device_printf(sc->rtsx_dev, "Adding MMC bus failed\n"); 690 } else { 691 device_set_ivars(sc->rtsx_mmc_dev, sc); 692 device_probe_and_attach(sc->rtsx_mmc_dev); 693 } 694 #endif /* MMCCAM */ 695 } else 696 RTSX_UNLOCK(sc); 697 } else { 698 sc->rtsx_flags &= ~RTSX_F_CARD_PRESENT; 699 /* Card isn't present, detach if necessary. */ 700 #ifdef MMCCAM 701 if (sc->rtsx_cam_status != 0) { 702 union ccb *ccb; 703 uint32_t pathid; 704 #else /* !MMCCAM */ 705 if (sc->rtsx_mmc_dev != NULL) { 706 #endif /* MMCCAM */ 707 if (bootverbose) 708 device_printf(sc->rtsx_dev, "Card removed\n"); 709 710 if (sc->rtsx_debug) 711 device_printf(sc->rtsx_dev, "Read count: %" PRIu64 ", write count: %" PRIu64 "\n", 712 sc->rtsx_read_count, sc->rtsx_write_count); 713 #ifdef MMCCAM 714 sc->rtsx_cam_status = 0; 715 pathid = cam_sim_path(sc->rtsx_sim); 716 ccb = xpt_alloc_ccb_nowait(); 717 if (ccb == NULL) { 718 device_printf(sc->rtsx_dev, "Unable to alloc CCB for rescan\n"); 719 RTSX_UNLOCK(sc); 720 return; 721 } 722 /* 723 * We create a rescan request for BUS:0:0, since the card 724 * will be at lun 0. 725 */ 726 if (xpt_create_path(&ccb->ccb_h.path, NULL, pathid, 727 /* target */ 0, /* lun */ 0) != CAM_REQ_CMP) { 728 device_printf(sc->rtsx_dev, "Unable to create path for rescan\n"); 729 RTSX_UNLOCK(sc); 730 xpt_free_ccb(ccb); 731 return; 732 } 733 RTSX_UNLOCK(sc); 734 xpt_rescan(ccb); 735 #else /* !MMCCAM */ 736 RTSX_UNLOCK(sc); 737 if (device_delete_child(sc->rtsx_dev, sc->rtsx_mmc_dev)) 738 device_printf(sc->rtsx_dev, "Detaching MMC bus failed\n"); 739 sc->rtsx_mmc_dev = NULL; 740 #endif /* MMCCAM */ 741 } else 742 RTSX_UNLOCK(sc); 743 } 744 } 745 746 static bool 747 rtsx_is_card_present(struct rtsx_softc *sc) 748 { 749 uint32_t status; 750 751 status = READ4(sc, RTSX_BIPR); 752 if (sc->rtsx_inversion == 0) 753 return (status & RTSX_SD_EXIST); 754 else 755 return !(status & RTSX_SD_EXIST); 756 } 757 758 static int 759 rtsx_init(struct rtsx_softc *sc) 760 { 761 bool rtsx_init_debug = false; 762 uint8_t version; 763 uint8_t val; 764 int error; 765 766 sc->rtsx_host.host_ocr = RTSX_SUPPORTED_VOLTAGE; 767 sc->rtsx_host.f_min = RTSX_SDCLK_250KHZ; 768 sc->rtsx_host.f_max = RTSX_SDCLK_208MHZ; 769 sc->rtsx_host.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_HSPEED | 770 MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 771 772 sc->rtsx_host.caps |= MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104; 773 if (sc->rtsx_device_id == RTSX_RTS5209) 774 sc->rtsx_host.caps |= MMC_CAP_8_BIT_DATA; 775 pci_find_cap(sc->rtsx_dev, PCIY_EXPRESS, &(sc->rtsx_pcie_cap)); 776 777 /* 778 * Check IC version. 779 */ 780 switch (sc->rtsx_device_id) { 781 case RTSX_RTS5229: 782 /* Read IC version from dummy register. */ 783 RTSX_READ(sc, RTSX_DUMMY_REG, &version); 784 if ((version & 0x0F) == RTSX_IC_VERSION_C) 785 sc->rtsx_flags |= RTSX_F_VERSION_C; 786 break; 787 case RTSX_RTS522A: 788 /* Read IC version from dummy register. */ 789 RTSX_READ(sc, RTSX_DUMMY_REG, &version); 790 if ((version & 0x0F) == RTSX_IC_VERSION_A) 791 sc->rtsx_flags |= RTSX_F_VERSION_A; 792 break; 793 case RTSX_RTS525A: 794 /* Read IC version from dummy register. */ 795 RTSX_READ(sc, RTSX_DUMMY_REG, &version); 796 if ((version & 0x0F) == RTSX_IC_VERSION_A) 797 sc->rtsx_flags |= RTSX_F_VERSION_A; 798 break; 799 case RTSX_RTL8411B: 800 RTSX_READ(sc, RTSX_RTL8411B_PACKAGE, &version); 801 if (version & RTSX_RTL8411B_QFN48) 802 sc->rtsx_flags |= RTSX_F_8411B_QFN48; 803 break; 804 } 805 806 /* 807 * Fetch vendor settings. 808 */ 809 /* 810 * Normally OEMs will set vendor setting to the config space 811 * of Realtek card reader in BIOS stage. This statement reads 812 * the setting and configure the internal registers according 813 * to it, to improve card reader's compatibility condition. 814 */ 815 sc->rtsx_card_drive_sel = RTSX_CARD_DRIVE_DEFAULT; 816 switch (sc->rtsx_device_id) { 817 uint32_t reg; 818 uint32_t reg1; 819 uint8_t reg3; 820 case RTSX_RTS5209: 821 sc->rtsx_card_drive_sel = RTSX_RTS5209_CARD_DRIVE_DEFAULT; 822 sc->rtsx_sd30_drive_sel_3v3 = RTSX_DRIVER_TYPE_D; 823 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG2, 4); 824 if (!(reg & 0x80)) { 825 sc->rtsx_card_drive_sel = (reg >> 8) & 0x3F; 826 sc->rtsx_sd30_drive_sel_3v3 = reg & 0x07; 827 } else { 828 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg); 829 } 830 if (bootverbose || rtsx_init_debug) 831 device_printf(sc->rtsx_dev, "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x\n", 832 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3); 833 break; 834 case RTSX_RTS5227: 835 case RTSX_RTS522A: 836 sc->rtsx_sd30_drive_sel_3v3 = RTSX_CFG_DRIVER_TYPE_B; 837 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4); 838 if (!(reg & 0x1000000)) { 839 sc->rtsx_card_drive_sel &= 0x3F; 840 sc->rtsx_card_drive_sel |= ((reg >> 25) & 0x01) << 6; 841 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG2, 4); 842 sc->rtsx_sd30_drive_sel_3v3 = (reg >> 5) & 0x03; 843 if (reg & 0x4000) 844 sc->rtsx_flags |= RTSX_F_REVERSE_SOCKET; 845 } else { 846 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg); 847 } 848 if (bootverbose || rtsx_init_debug) 849 device_printf(sc->rtsx_dev, 850 "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x, reverse_socket is %s\n", 851 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3, 852 (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) ? "true" : "false"); 853 break; 854 case RTSX_RTS5229: 855 sc->rtsx_sd30_drive_sel_3v3 = RTSX_DRIVER_TYPE_D; 856 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4); 857 if (!(reg & 0x1000000)) { 858 sc->rtsx_card_drive_sel &= 0x3F; 859 sc->rtsx_card_drive_sel |= ((reg >> 25) & 0x01) << 6; 860 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG2, 4); 861 sc->rtsx_sd30_drive_sel_3v3 = rtsx_map_sd_drive((reg >> 5) & 0x03); 862 } else { 863 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg); 864 } 865 if (bootverbose || rtsx_init_debug) 866 device_printf(sc->rtsx_dev, "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x\n", 867 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3); 868 break; 869 case RTSX_RTS525A: 870 case RTSX_RTS5249: 871 sc->rtsx_sd30_drive_sel_3v3 = RTSX_CFG_DRIVER_TYPE_B; 872 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4); 873 if ((reg & 0x1000000)) { 874 sc->rtsx_card_drive_sel &= 0x3F; 875 sc->rtsx_card_drive_sel |= ((reg >> 25) & 0x01) << 6; 876 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG2, 4); 877 sc->rtsx_sd30_drive_sel_3v3 = (reg >> 5) & 0x03; 878 if (reg & 0x4000) 879 sc->rtsx_flags |= RTSX_F_REVERSE_SOCKET; 880 } else { 881 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg); 882 } 883 if (bootverbose || rtsx_init_debug) 884 device_printf(sc->rtsx_dev, 885 "card_drive_sel = 0x%02x, sd30_drive_sel_3v3: 0x%02x, reverse_socket is %s\n", 886 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3, 887 (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) ? "true" : "false"); 888 break; 889 case RTSX_RTL8402: 890 case RTSX_RTL8411: 891 sc->rtsx_card_drive_sel = RTSX_RTL8411_CARD_DRIVE_DEFAULT; 892 sc->rtsx_sd30_drive_sel_3v3 = RTSX_DRIVER_TYPE_D; 893 reg1 = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4); 894 if (reg1 & 0x1000000) { 895 sc->rtsx_card_drive_sel &= 0x3F; 896 sc->rtsx_card_drive_sel |= ((reg1 >> 25) & 0x01) << 6; 897 reg3 = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG3, 1); 898 sc->rtsx_sd30_drive_sel_3v3 = (reg3 >> 5) & 0x07; 899 } else { 900 device_printf(sc->rtsx_dev, "pci_read_config() error - reg1: 0x%08x\n", reg1); 901 } 902 if (bootverbose || rtsx_init_debug) 903 device_printf(sc->rtsx_dev, 904 "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x\n", 905 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3); 906 break; 907 case RTSX_RTL8411B: 908 sc->rtsx_card_drive_sel = RTSX_RTL8411_CARD_DRIVE_DEFAULT; 909 sc->rtsx_sd30_drive_sel_3v3 = RTSX_DRIVER_TYPE_D; 910 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4); 911 if (!(reg & 0x1000000)) { 912 sc->rtsx_sd30_drive_sel_3v3 = rtsx_map_sd_drive(reg & 0x03); 913 } else { 914 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg); 915 } 916 if (bootverbose || rtsx_init_debug) 917 device_printf(sc->rtsx_dev, 918 "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x\n", 919 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3); 920 break; 921 } 922 923 if (bootverbose || rtsx_init_debug) 924 device_printf(sc->rtsx_dev, "rtsx_init() rtsx_flags: 0x%04x\n", sc->rtsx_flags); 925 926 /* Enable interrupts. */ 927 sc->rtsx_intr_enabled = RTSX_TRANS_OK_INT_EN | RTSX_TRANS_FAIL_INT_EN | RTSX_SD_INT_EN | RTSX_MS_INT_EN; 928 WRITE4(sc, RTSX_BIER, sc->rtsx_intr_enabled); 929 930 /* Power on SSC clock. */ 931 RTSX_CLR(sc, RTSX_FPDCTL, RTSX_SSC_POWER_DOWN); 932 /* Wait SSC power stable. */ 933 DELAY(200); 934 935 /* Disable ASPM */ 936 val = pci_read_config(sc->rtsx_dev, sc->rtsx_pcie_cap + PCIER_LINK_CTL, 1); 937 pci_write_config(sc->rtsx_dev, sc->rtsx_pcie_cap + PCIER_LINK_CTL, val & 0xfc, 1); 938 939 /* 940 * Optimize phy. 941 */ 942 switch (sc->rtsx_device_id) { 943 case RTSX_RTS5209: 944 /* Some magic numbers from Linux driver. */ 945 if ((error = rtsx_write_phy(sc, 0x00, 0xB966))) 946 return (error); 947 break; 948 case RTSX_RTS5227: 949 RTSX_CLR(sc, RTSX_PM_CTRL3, RTSX_D3_DELINK_MODE_EN); 950 951 /* Optimize RX sensitivity. */ 952 if ((error = rtsx_write_phy(sc, 0x00, 0xBA42))) 953 return (error); 954 break; 955 case RTSX_RTS5229: 956 /* Optimize RX sensitivity. */ 957 if ((error = rtsx_write_phy(sc, 0x00, 0xBA42))) 958 return (error); 959 break; 960 case RTSX_RTS522A: 961 RTSX_CLR(sc, RTSX_RTS522A_PM_CTRL3, RTSX_D3_DELINK_MODE_EN); 962 if (sc->rtsx_flags & RTSX_F_VERSION_A) { 963 if ((error = rtsx_write_phy(sc, RTSX_PHY_RCR2, RTSX_PHY_RCR2_INIT_27S))) 964 return (error); 965 } 966 if ((error = rtsx_write_phy(sc, RTSX_PHY_RCR1, RTSX_PHY_RCR1_INIT_27S))) 967 return (error); 968 if ((error = rtsx_write_phy(sc, RTSX_PHY_FLD0, RTSX_PHY_FLD0_INIT_27S))) 969 return (error); 970 if ((error = rtsx_write_phy(sc, RTSX_PHY_FLD3, RTSX_PHY_FLD3_INIT_27S))) 971 return (error); 972 if ((error = rtsx_write_phy(sc, RTSX_PHY_FLD4, RTSX_PHY_FLD4_INIT_27S))) 973 return (error); 974 break; 975 case RTSX_RTS525A: 976 if ((error = rtsx_write_phy(sc, RTSX__PHY_FLD0, 977 RTSX__PHY_FLD0_CLK_REQ_20C | RTSX__PHY_FLD0_RX_IDLE_EN | 978 RTSX__PHY_FLD0_BIT_ERR_RSTN | RTSX__PHY_FLD0_BER_COUNT | 979 RTSX__PHY_FLD0_BER_TIMER | RTSX__PHY_FLD0_CHECK_EN))) 980 return (error); 981 if ((error = rtsx_write_phy(sc, RTSX__PHY_ANA03, 982 RTSX__PHY_ANA03_TIMER_MAX | RTSX__PHY_ANA03_OOBS_DEB_EN | 983 RTSX__PHY_CMU_DEBUG_EN))) 984 return (error); 985 if (sc->rtsx_flags & RTSX_F_VERSION_A) 986 if ((error = rtsx_write_phy(sc, RTSX__PHY_REV0, 987 RTSX__PHY_REV0_FILTER_OUT | RTSX__PHY_REV0_CDR_BYPASS_PFD | 988 RTSX__PHY_REV0_CDR_RX_IDLE_BYPASS))) 989 return (error); 990 break; 991 case RTSX_RTS5249: 992 RTSX_CLR(sc, RTSX_PM_CTRL3, RTSX_D3_DELINK_MODE_EN); 993 if ((error = rtsx_write_phy(sc, RTSX_PHY_REV, 994 RTSX_PHY_REV_RESV | RTSX_PHY_REV_RXIDLE_LATCHED | 995 RTSX_PHY_REV_P1_EN | RTSX_PHY_REV_RXIDLE_EN | 996 RTSX_PHY_REV_CLKREQ_TX_EN | RTSX_PHY_REV_RX_PWST | 997 RTSX_PHY_REV_CLKREQ_DT_1_0 | RTSX_PHY_REV_STOP_CLKRD | 998 RTSX_PHY_REV_STOP_CLKWR))) 999 return (error); 1000 DELAY(1000); 1001 if ((error = rtsx_write_phy(sc, RTSX_PHY_BPCR, 1002 RTSX_PHY_BPCR_IBRXSEL | RTSX_PHY_BPCR_IBTXSEL | 1003 RTSX_PHY_BPCR_IB_FILTER | RTSX_PHY_BPCR_CMIRROR_EN))) 1004 return (error); 1005 if ((error = rtsx_write_phy(sc, RTSX_PHY_PCR, 1006 RTSX_PHY_PCR_FORCE_CODE | RTSX_PHY_PCR_OOBS_CALI_50 | 1007 RTSX_PHY_PCR_OOBS_VCM_08 | RTSX_PHY_PCR_OOBS_SEN_90 | 1008 RTSX_PHY_PCR_RSSI_EN | RTSX_PHY_PCR_RX10K))) 1009 return (error); 1010 if ((error = rtsx_write_phy(sc, RTSX_PHY_RCR2, 1011 RTSX_PHY_RCR2_EMPHASE_EN | RTSX_PHY_RCR2_NADJR | 1012 RTSX_PHY_RCR2_CDR_SR_2 | RTSX_PHY_RCR2_FREQSEL_12 | 1013 RTSX_PHY_RCR2_CDR_SC_12P | RTSX_PHY_RCR2_CALIB_LATE))) 1014 return (error); 1015 if ((error = rtsx_write_phy(sc, RTSX_PHY_FLD4, 1016 RTSX_PHY_FLD4_FLDEN_SEL | RTSX_PHY_FLD4_REQ_REF | 1017 RTSX_PHY_FLD4_RXAMP_OFF | RTSX_PHY_FLD4_REQ_ADDA | 1018 RTSX_PHY_FLD4_BER_COUNT | RTSX_PHY_FLD4_BER_TIMER | 1019 RTSX_PHY_FLD4_BER_CHK_EN))) 1020 return (error); 1021 if ((error = rtsx_write_phy(sc, RTSX_PHY_RDR, 1022 RTSX_PHY_RDR_RXDSEL_1_9 | RTSX_PHY_SSC_AUTO_PWD))) 1023 return (error); 1024 if ((error = rtsx_write_phy(sc, RTSX_PHY_RCR1, 1025 RTSX_PHY_RCR1_ADP_TIME_4 | RTSX_PHY_RCR1_VCO_COARSE))) 1026 return (error); 1027 if ((error = rtsx_write_phy(sc, RTSX_PHY_FLD3, 1028 RTSX_PHY_FLD3_TIMER_4 | RTSX_PHY_FLD3_TIMER_6 | 1029 RTSX_PHY_FLD3_RXDELINK))) 1030 return (error); 1031 if ((error = rtsx_write_phy(sc, RTSX_PHY_TUNE, 1032 RTSX_PHY_TUNE_TUNEREF_1_0 | RTSX_PHY_TUNE_VBGSEL_1252 | 1033 RTSX_PHY_TUNE_SDBUS_33 | RTSX_PHY_TUNE_TUNED18 | 1034 RTSX_PHY_TUNE_TUNED12 | RTSX_PHY_TUNE_TUNEA12))) 1035 return (error); 1036 break; 1037 } 1038 1039 /* Set mcu_cnt to 7 to ensure data can be sampled properly. */ 1040 RTSX_BITOP(sc, RTSX_CLK_DIV, 0x07, 0x07); 1041 1042 /* Disable sleep mode. */ 1043 RTSX_CLR(sc, RTSX_HOST_SLEEP_STATE, 1044 RTSX_HOST_ENTER_S1 | RTSX_HOST_ENTER_S3); 1045 1046 /* Disable card clock. */ 1047 RTSX_CLR(sc, RTSX_CARD_CLK_EN, RTSX_CARD_CLK_EN_ALL); 1048 1049 /* Reset delink mode. */ 1050 RTSX_CLR(sc, RTSX_CHANGE_LINK_STATE, 1051 RTSX_FORCE_RST_CORE_EN | RTSX_NON_STICKY_RST_N_DBG); 1052 1053 /* Card driving select. */ 1054 RTSX_WRITE(sc, RTSX_CARD_DRIVE_SEL, sc->rtsx_card_drive_sel); 1055 1056 /* Enable SSC clock. */ 1057 RTSX_WRITE(sc, RTSX_SSC_CTL1, RTSX_SSC_8X_EN | RTSX_SSC_SEL_4M); 1058 RTSX_WRITE(sc, RTSX_SSC_CTL2, 0x12); 1059 1060 /* Disable cd_pwr_save. */ 1061 RTSX_BITOP(sc, RTSX_CHANGE_LINK_STATE, 0x16, RTSX_MAC_PHY_RST_N_DBG); 1062 1063 /* Clear Link Ready Interrupt. */ 1064 RTSX_BITOP(sc, RTSX_IRQSTAT0, RTSX_LINK_READY_INT, RTSX_LINK_READY_INT); 1065 1066 /* Enlarge the estimation window of PERST# glitch 1067 * to reduce the chance of invalid card interrupt. */ 1068 RTSX_WRITE(sc, RTSX_PERST_GLITCH_WIDTH, 0x80); 1069 1070 /* Set RC oscillator to 400K. */ 1071 RTSX_CLR(sc, RTSX_RCCTL, RTSX_RCCTL_F_2M); 1072 1073 /* Enable interrupt write-clear (default is read-clear). */ 1074 RTSX_CLR(sc, RTSX_NFTS_TX_CTRL, RTSX_INT_READ_CLR); 1075 1076 if (sc->rtsx_device_id == RTSX_RTS525A) 1077 RTSX_BITOP(sc, RTSX_PM_CLK_FORCE_CTL, 1, 1); 1078 1079 /* OC power down. */ 1080 RTSX_BITOP(sc, RTSX_FPDCTL, RTSX_SD_OC_POWER_DOWN, RTSX_SD_OC_POWER_DOWN); 1081 1082 /* Enable clk_request_n to enable clock power management */ 1083 pci_write_config(sc->rtsx_dev, sc->rtsx_pcie_cap + PCIER_LINK_CTL + 1, 1, 1); 1084 1085 /* Enter L1 when host tx idle */ 1086 pci_write_config(sc->rtsx_dev, 0x70F, 0x5B, 1); 1087 1088 /* 1089 * Specific extra init. 1090 */ 1091 switch (sc->rtsx_device_id) { 1092 uint16_t cap; 1093 case RTSX_RTS5209: 1094 /* Turn off LED. */ 1095 RTSX_WRITE(sc, RTSX_CARD_GPIO, 0x03); 1096 /* Reset ASPM state to default value. */ 1097 RTSX_CLR(sc, RTSX_ASPM_FORCE_CTL, RTSX_ASPM_FORCE_MASK); 1098 /* Force CLKREQ# PIN to drive 0 to request clock. */ 1099 RTSX_BITOP(sc, RTSX_PETXCFG, 0x08, 0x08); 1100 /* Configure GPIO as output. */ 1101 RTSX_WRITE(sc, RTSX_CARD_GPIO_DIR, 0x03); 1102 /* Configure driving. */ 1103 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, sc->rtsx_sd30_drive_sel_3v3); 1104 break; 1105 case RTSX_RTS5227: 1106 /* Configure GPIO as output. */ 1107 RTSX_BITOP(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON, RTSX_GPIO_LED_ON); 1108 /* Reset ASPM state to default value. */ 1109 RTSX_BITOP(sc, RTSX_ASPM_FORCE_CTL, RTSX_ASPM_FORCE_MASK, RTSX_FORCE_ASPM_NO_ASPM); 1110 /* Switch LDO3318 source from DV33 to 3V3. */ 1111 RTSX_CLR(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33); 1112 RTSX_BITOP(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33, RTSX_LDO_PWR_SEL_3V3); 1113 /* Set default OLT blink period. */ 1114 RTSX_BITOP(sc, RTSX_OLT_LED_CTL, 0x0F, RTSX_OLT_LED_PERIOD); 1115 /* Configure LTR. */ 1116 cap = pci_read_config(sc->rtsx_dev, sc->rtsx_pcie_cap + PCIER_DEVICE_CTL2, 2); 1117 if (cap & PCIEM_CTL2_LTR_ENABLE) 1118 RTSX_WRITE(sc, RTSX_LTR_CTL, 0xa3); 1119 /* Configure OBFF. */ 1120 RTSX_BITOP(sc, RTSX_OBFF_CFG, RTSX_OBFF_EN_MASK, RTSX_OBFF_ENABLE); 1121 /* Configure driving. */ 1122 if ((error = rtsx_rts5227_fill_driving(sc))) 1123 return (error); 1124 /* Configure force_clock_req. */ 1125 if (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) 1126 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB8, 0xB8); 1127 else 1128 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB8, 0x88); 1129 RTSX_CLR(sc, RTSX_PM_CTRL3, RTSX_D3_DELINK_MODE_EN); 1130 /*!!! Added for reboot after Windows. */ 1131 RTSX_BITOP(sc, RTSX_PM_CTRL3, RTSX_PM_WAKE_EN, RTSX_PM_WAKE_EN); 1132 break; 1133 case RTSX_RTS5229: 1134 /* Configure GPIO as output. */ 1135 RTSX_BITOP(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON, RTSX_GPIO_LED_ON); 1136 /* Reset ASPM state to default value. */ 1137 /* With this reset: dd if=/dev/random of=/dev/mmcsd0 encounter a timeout. */ 1138 //!!! RTSX_BITOP(sc, RTSX_ASPM_FORCE_CTL, RTSX_ASPM_FORCE_MASK, RTSX_FORCE_ASPM_NO_ASPM); 1139 /* Force CLKREQ# PIN to drive 0 to request clock. */ 1140 RTSX_BITOP(sc, RTSX_PETXCFG, 0x08, 0x08); 1141 /* Switch LDO3318 source from DV33 to card_3v3. */ 1142 RTSX_CLR(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33); 1143 RTSX_BITOP(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33, RTSX_LDO_PWR_SEL_3V3); 1144 /* Set default OLT blink period. */ 1145 RTSX_BITOP(sc, RTSX_OLT_LED_CTL, 0x0F, RTSX_OLT_LED_PERIOD); 1146 /* Configure driving. */ 1147 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, sc->rtsx_sd30_drive_sel_3v3); 1148 break; 1149 case RTSX_RTS522A: 1150 /* Add specific init from RTS5227. */ 1151 /* Configure GPIO as output. */ 1152 RTSX_BITOP(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON, RTSX_GPIO_LED_ON); 1153 /* Reset ASPM state to default value. */ 1154 RTSX_BITOP(sc, RTSX_ASPM_FORCE_CTL, RTSX_ASPM_FORCE_MASK, RTSX_FORCE_ASPM_NO_ASPM); 1155 /* Switch LDO3318 source from DV33 to 3V3. */ 1156 RTSX_CLR(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33); 1157 RTSX_BITOP(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33, RTSX_LDO_PWR_SEL_3V3); 1158 /* Set default OLT blink period. */ 1159 RTSX_BITOP(sc, RTSX_OLT_LED_CTL, 0x0F, RTSX_OLT_LED_PERIOD); 1160 /* Configure LTR. */ 1161 cap = pci_read_config(sc->rtsx_dev, sc->rtsx_pcie_cap + PCIER_DEVICE_CTL2, 2); 1162 if (cap & PCIEM_CTL2_LTR_ENABLE) 1163 RTSX_WRITE(sc, RTSX_LTR_CTL, 0xa3); 1164 /* Configure OBFF. */ 1165 RTSX_BITOP(sc, RTSX_OBFF_CFG, RTSX_OBFF_EN_MASK, RTSX_OBFF_ENABLE); 1166 /* Configure driving. */ 1167 if ((error = rtsx_rts5227_fill_driving(sc))) 1168 return (error); 1169 /* Configure force_clock_req. */ 1170 if (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) 1171 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB8, 0xB8); 1172 else 1173 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB8, 0x88); 1174 RTSX_CLR(sc, RTSX_RTS522A_PM_CTRL3, 0x10); 1175 1176 /* specific for RTS522A. */ 1177 RTSX_BITOP(sc, RTSX_FUNC_FORCE_CTL, 1178 RTSX_FUNC_FORCE_UPME_XMT_DBG, RTSX_FUNC_FORCE_UPME_XMT_DBG); 1179 RTSX_BITOP(sc, RTSX_PCLK_CTL, 0x04, 0x04); 1180 RTSX_BITOP(sc, RTSX_PM_EVENT_DEBUG, 1181 RTSX_PME_DEBUG_0, RTSX_PME_DEBUG_0); 1182 RTSX_WRITE(sc, RTSX_PM_CLK_FORCE_CTL, 0x11); 1183 break; 1184 case RTSX_RTS525A: 1185 /* Add specific init from RTS5249. */ 1186 /* Rest L1SUB Config. */ 1187 RTSX_CLR(sc, RTSX_L1SUB_CONFIG3, 0xff); 1188 /* Configure GPIO as output. */ 1189 RTSX_BITOP(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON, RTSX_GPIO_LED_ON); 1190 /* Reset ASPM state to default value. */ 1191 RTSX_BITOP(sc, RTSX_ASPM_FORCE_CTL, RTSX_ASPM_FORCE_MASK, RTSX_FORCE_ASPM_NO_ASPM); 1192 /* Switch LDO3318 source from DV33 to 3V3. */ 1193 RTSX_CLR(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33); 1194 RTSX_BITOP(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33, RTSX_LDO_PWR_SEL_3V3); 1195 /* Set default OLT blink period. */ 1196 RTSX_BITOP(sc, RTSX_OLT_LED_CTL, 0x0F, RTSX_OLT_LED_PERIOD); 1197 /* Configure driving. */ 1198 if ((error = rtsx_rts5249_fill_driving(sc))) 1199 return (error); 1200 /* Configure force_clock_req. */ 1201 if (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) 1202 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0xB0); 1203 else 1204 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0x80); 1205 1206 /* Specifc for RTS525A. */ 1207 RTSX_BITOP(sc, RTSX_PCLK_CTL, RTSX_PCLK_MODE_SEL, RTSX_PCLK_MODE_SEL); 1208 if (sc->rtsx_flags & RTSX_F_VERSION_A) { 1209 RTSX_WRITE(sc, RTSX_L1SUB_CONFIG2, RTSX_L1SUB_AUTO_CFG); 1210 RTSX_BITOP(sc, RTSX_RREF_CFG, 1211 RTSX_RREF_VBGSEL_MASK, RTSX_RREF_VBGSEL_1V25); 1212 RTSX_BITOP(sc, RTSX_LDO_VIO_CFG, 1213 RTSX_LDO_VIO_TUNE_MASK, RTSX_LDO_VIO_1V7); 1214 RTSX_BITOP(sc, RTSX_LDO_DV12S_CFG, 1215 RTSX_LDO_D12_TUNE_MASK, RTSX_LDO_D12_TUNE_DF); 1216 RTSX_BITOP(sc, RTSX_LDO_AV12S_CFG, 1217 RTSX_LDO_AV12S_TUNE_MASK, RTSX_LDO_AV12S_TUNE_DF); 1218 RTSX_BITOP(sc, RTSX_LDO_VCC_CFG0, 1219 RTSX_LDO_VCC_LMTVTH_MASK, RTSX_LDO_VCC_LMTVTH_2A); 1220 RTSX_BITOP(sc, RTSX_OOBS_CONFIG, 1221 RTSX_OOBS_AUTOK_DIS | RTSX_OOBS_VAL_MASK, 0x89); 1222 } 1223 break; 1224 case RTSX_RTS5249: 1225 /* Rest L1SUB Config. */ 1226 RTSX_CLR(sc, RTSX_L1SUB_CONFIG3, 0xff); 1227 /* Configure GPIO as output. */ 1228 RTSX_BITOP(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON, RTSX_GPIO_LED_ON); 1229 /* Reset ASPM state to default value. */ 1230 RTSX_BITOP(sc, RTSX_ASPM_FORCE_CTL, RTSX_ASPM_FORCE_MASK, RTSX_FORCE_ASPM_NO_ASPM); 1231 /* Switch LDO3318 source from DV33 to 3V3. */ 1232 RTSX_CLR(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33); 1233 RTSX_BITOP(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33, RTSX_LDO_PWR_SEL_3V3); 1234 /* Set default OLT blink period. */ 1235 RTSX_BITOP(sc, RTSX_OLT_LED_CTL, 0x0F, RTSX_OLT_LED_PERIOD); 1236 /* Configure driving. */ 1237 if ((error = rtsx_rts5249_fill_driving(sc))) 1238 return (error); 1239 /* Configure force_clock_req. */ 1240 if (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) 1241 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0xB0); 1242 else 1243 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0x80); 1244 break; 1245 case RTSX_RTL8402: 1246 case RTSX_RTL8411: 1247 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, sc->rtsx_sd30_drive_sel_3v3); 1248 RTSX_BITOP(sc, RTSX_CARD_PAD_CTL, RTSX_CD_DISABLE_MASK | RTSX_CD_AUTO_DISABLE, 1249 RTSX_CD_ENABLE); 1250 break; 1251 case RTSX_RTL8411B: 1252 if (sc->rtsx_flags & RTSX_F_8411B_QFN48) 1253 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xf5); 1254 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, sc->rtsx_sd30_drive_sel_3v3); 1255 /* Enable SD interrupt. */ 1256 RTSX_BITOP(sc, RTSX_CARD_PAD_CTL, RTSX_CD_DISABLE_MASK | RTSX_CD_AUTO_DISABLE, 1257 RTSX_CD_ENABLE); 1258 /* Clear hw_pfm_en to disable hardware PFM mode. */ 1259 RTSX_BITOP(sc, RTSX_FUNC_FORCE_CTL, 0x06, 0x00); 1260 break; 1261 } 1262 1263 /*!!! Added for reboot after Windows. */ 1264 rtsx_bus_power_off(sc); 1265 rtsx_set_sd_timing(sc, bus_timing_normal); 1266 rtsx_set_sd_clock(sc, 0); 1267 /*!!! Added for reboot after Windows. */ 1268 1269 return (0); 1270 } 1271 1272 static int 1273 rtsx_map_sd_drive(int index) 1274 { 1275 uint8_t sd_drive[4] = 1276 { 1277 0x01, /* Type D */ 1278 0x02, /* Type C */ 1279 0x05, /* Type A */ 1280 0x03 /* Type B */ 1281 }; 1282 return (sd_drive[index]); 1283 } 1284 1285 /* For voltage 3v3. */ 1286 static int 1287 rtsx_rts5227_fill_driving(struct rtsx_softc *sc) 1288 { 1289 u_char driving_3v3[4][3] = { 1290 {0x13, 0x13, 0x13}, 1291 {0x96, 0x96, 0x96}, 1292 {0x7F, 0x7F, 0x7F}, 1293 {0x96, 0x96, 0x96}, 1294 }; 1295 RTSX_WRITE(sc, RTSX_SD30_CLK_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][0]); 1296 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][1]); 1297 RTSX_WRITE(sc, RTSX_SD30_DAT_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][2]); 1298 1299 return (0); 1300 } 1301 1302 /* For voltage 3v3. */ 1303 static int 1304 rtsx_rts5249_fill_driving(struct rtsx_softc *sc) 1305 { 1306 u_char driving_3v3[4][3] = { 1307 {0x11, 0x11, 0x18}, 1308 {0x55, 0x55, 0x5C}, 1309 {0xFF, 0xFF, 0xFF}, 1310 {0x96, 0x96, 0x96}, 1311 }; 1312 RTSX_WRITE(sc, RTSX_SD30_CLK_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][0]); 1313 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][1]); 1314 RTSX_WRITE(sc, RTSX_SD30_DAT_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][2]); 1315 1316 return (0); 1317 } 1318 1319 static int 1320 rtsx_read(struct rtsx_softc *sc, uint16_t addr, uint8_t *val) 1321 { 1322 int tries = 1024; 1323 uint32_t reg; 1324 1325 WRITE4(sc, RTSX_HAIMR, RTSX_HAIMR_BUSY | 1326 (uint32_t)((addr & 0x3FFF) << 16)); 1327 1328 while (tries--) { 1329 reg = READ4(sc, RTSX_HAIMR); 1330 if (!(reg & RTSX_HAIMR_BUSY)) 1331 break; 1332 } 1333 *val = (reg & 0xff); 1334 1335 return ((tries == 0) ? ETIMEDOUT : 0); 1336 } 1337 1338 static int 1339 rtsx_read_cfg(struct rtsx_softc *sc, uint8_t func, uint16_t addr, uint32_t *val) 1340 { 1341 int tries = 1024; 1342 uint8_t data0, data1, data2, data3, rwctl; 1343 1344 RTSX_WRITE(sc, RTSX_CFGADDR0, addr); 1345 RTSX_WRITE(sc, RTSX_CFGADDR1, addr >> 8); 1346 RTSX_WRITE(sc, RTSX_CFGRWCTL, RTSX_CFG_BUSY | (func & 0x03 << 4)); 1347 1348 while (tries--) { 1349 RTSX_READ(sc, RTSX_CFGRWCTL, &rwctl); 1350 if (!(rwctl & RTSX_CFG_BUSY)) 1351 break; 1352 } 1353 1354 if (tries == 0) 1355 return (ETIMEDOUT); 1356 1357 RTSX_READ(sc, RTSX_CFGDATA0, &data0); 1358 RTSX_READ(sc, RTSX_CFGDATA1, &data1); 1359 RTSX_READ(sc, RTSX_CFGDATA2, &data2); 1360 RTSX_READ(sc, RTSX_CFGDATA3, &data3); 1361 1362 *val = (data3 << 24) | (data2 << 16) | (data1 << 8) | data0; 1363 1364 return (0); 1365 } 1366 1367 static int 1368 rtsx_write(struct rtsx_softc *sc, uint16_t addr, uint8_t mask, uint8_t val) 1369 { 1370 int tries = 1024; 1371 uint32_t reg; 1372 1373 WRITE4(sc, RTSX_HAIMR, 1374 RTSX_HAIMR_BUSY | RTSX_HAIMR_WRITE | 1375 (uint32_t)(((addr & 0x3FFF) << 16) | 1376 (mask << 8) | val)); 1377 1378 while (tries--) { 1379 reg = READ4(sc, RTSX_HAIMR); 1380 if (!(reg & RTSX_HAIMR_BUSY)) { 1381 if (val != (reg & 0xff)) 1382 return (EIO); 1383 return (0); 1384 } 1385 } 1386 1387 return (ETIMEDOUT); 1388 } 1389 1390 static int 1391 rtsx_read_phy(struct rtsx_softc *sc, uint8_t addr, uint16_t *val) 1392 { 1393 int tries = 100000; 1394 uint8_t data0, data1, rwctl; 1395 1396 RTSX_WRITE(sc, RTSX_PHY_ADDR, addr); 1397 RTSX_WRITE(sc, RTSX_PHY_RWCTL, RTSX_PHY_BUSY | RTSX_PHY_READ); 1398 1399 while (tries--) { 1400 RTSX_READ(sc, RTSX_PHY_RWCTL, &rwctl); 1401 if (!(rwctl & RTSX_PHY_BUSY)) 1402 break; 1403 } 1404 if (tries == 0) 1405 return (ETIMEDOUT); 1406 1407 RTSX_READ(sc, RTSX_PHY_DATA0, &data0); 1408 RTSX_READ(sc, RTSX_PHY_DATA1, &data1); 1409 *val = data1 << 8 | data0; 1410 1411 return (0); 1412 } 1413 1414 static int 1415 rtsx_write_phy(struct rtsx_softc *sc, uint8_t addr, uint16_t val) 1416 { 1417 int tries = 100000; 1418 uint8_t rwctl; 1419 1420 RTSX_WRITE(sc, RTSX_PHY_DATA0, val); 1421 RTSX_WRITE(sc, RTSX_PHY_DATA1, val >> 8); 1422 RTSX_WRITE(sc, RTSX_PHY_ADDR, addr); 1423 RTSX_WRITE(sc, RTSX_PHY_RWCTL, RTSX_PHY_BUSY | RTSX_PHY_WRITE); 1424 1425 while (tries--) { 1426 RTSX_READ(sc, RTSX_PHY_RWCTL, &rwctl); 1427 if (!(rwctl & RTSX_PHY_BUSY)) 1428 break; 1429 } 1430 1431 return ((tries == 0) ? ETIMEDOUT : 0); 1432 } 1433 1434 /* 1435 * Notice that the meaning of RTSX_PWR_GATE_CTRL changes between RTS5209 and 1436 * RTS5229. In RTS5209 it is a mask of disabled power gates, while in RTS5229 1437 * it is a mask of *enabled* gates. 1438 */ 1439 static int 1440 rtsx_bus_power_off(struct rtsx_softc *sc) 1441 { 1442 if (bootverbose || sc->rtsx_debug) 1443 device_printf(sc->rtsx_dev, "rtsx_bus_power_off()\n"); 1444 1445 /* Disable SD clock. */ 1446 RTSX_CLR(sc, RTSX_CARD_CLK_EN, RTSX_SD_CLK_EN); 1447 1448 /* Disable SD output. */ 1449 RTSX_CLR(sc, RTSX_CARD_OE, RTSX_SD_OUTPUT_EN); 1450 1451 /* Turn off power. */ 1452 switch (sc->rtsx_device_id) { 1453 case RTSX_RTS5209: 1454 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK | RTSX_PMOS_STRG_MASK, 1455 RTSX_SD_PWR_OFF | RTSX_PMOS_STRG_400mA); 1456 RTSX_SET(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_OFF); 1457 break; 1458 case RTSX_RTS5227: 1459 case RTSX_RTS5229: 1460 case RTSX_RTS522A: 1461 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK | RTSX_PMOS_STRG_MASK, 1462 RTSX_SD_PWR_OFF | RTSX_PMOS_STRG_400mA); 1463 RTSX_CLR(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK); 1464 break; 1465 case RTSX_RTL8402: 1466 case RTSX_RTL8411: 1467 case RTSX_RTL8411B: 1468 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK, 1469 RTSX_BPP_POWER_OFF); 1470 RTSX_BITOP(sc, RTSX_LDO_CTL, RTSX_BPP_LDO_POWB, 1471 RTSX_BPP_LDO_SUSPEND); 1472 break; 1473 default: 1474 RTSX_CLR(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK); 1475 RTSX_SET(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_OFF); 1476 RTSX_CLR(sc, RTSX_CARD_PWR_CTL, RTSX_PMOS_STRG_800mA); 1477 break; 1478 } 1479 1480 /* Disable pull control. */ 1481 switch (sc->rtsx_device_id) { 1482 case RTSX_RTS5209: 1483 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, RTSX_PULL_CTL_DISABLE12); 1484 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_DISABLE12); 1485 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_DISABLE3); 1486 break; 1487 case RTSX_RTS5227: 1488 case RTSX_RTS522A: 1489 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_DISABLE12); 1490 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_DISABLE3); 1491 break; 1492 case RTSX_RTS5229: 1493 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_DISABLE12); 1494 if (sc->rtsx_flags & RTSX_F_VERSION_C) 1495 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_DISABLE3_TYPE_C); 1496 else 1497 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_DISABLE3); 1498 break; 1499 case RTSX_RTS525A: 1500 case RTSX_RTS5249: 1501 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0x66); 1502 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_DISABLE12); 1503 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_DISABLE3); 1504 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x55); 1505 break; 1506 case RTSX_RTL8402: 1507 case RTSX_RTL8411: 1508 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0x65); 1509 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0x55); 1510 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0x95); 1511 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x09); 1512 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL5, 0x05); 1513 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x04); 1514 break; 1515 case RTSX_RTL8411B: 1516 if (sc->rtsx_flags & RTSX_F_8411B_QFN48) { 1517 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0x55); 1518 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xf5); 1519 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x15); 1520 } else { 1521 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0x65); 1522 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0x55); 1523 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xd5); 1524 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x59); 1525 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL5, 0x55); 1526 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x15); 1527 } 1528 break; 1529 } 1530 1531 return (0); 1532 } 1533 1534 static int 1535 rtsx_bus_power_on(struct rtsx_softc *sc) 1536 { 1537 if (bootverbose || sc->rtsx_debug) 1538 device_printf(sc->rtsx_dev, "rtsx_bus_power_on()\n"); 1539 1540 /* Select SD card. */ 1541 RTSX_BITOP(sc, RTSX_CARD_SELECT, 0x07, RTSX_SD_MOD_SEL); 1542 RTSX_BITOP(sc, RTSX_CARD_SHARE_MODE, RTSX_CARD_SHARE_MASK, RTSX_CARD_SHARE_48_SD); 1543 1544 /* Enable SD clock. */ 1545 RTSX_BITOP(sc, RTSX_CARD_CLK_EN, RTSX_SD_CLK_EN, RTSX_SD_CLK_EN); 1546 1547 /* Enable pull control. */ 1548 switch (sc->rtsx_device_id) { 1549 case RTSX_RTS5209: 1550 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, RTSX_PULL_CTL_ENABLE12); 1551 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_ENABLE12); 1552 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_ENABLE3); 1553 break; 1554 case RTSX_RTS5227: 1555 case RTSX_RTS522A: 1556 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_ENABLE12); 1557 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_ENABLE3); 1558 break; 1559 case RTSX_RTS5229: 1560 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_ENABLE12); 1561 if (sc->rtsx_flags & RTSX_F_VERSION_C) 1562 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_ENABLE3_TYPE_C); 1563 else 1564 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_ENABLE3); 1565 break; 1566 case RTSX_RTS525A: 1567 case RTSX_RTS5249: 1568 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0x66); 1569 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_ENABLE12); 1570 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_ENABLE3); 1571 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0xaa); 1572 break; 1573 case RTSX_RTL8402: 1574 case RTSX_RTL8411: 1575 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0xaa); 1576 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0xaa); 1577 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xa9); 1578 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x09); 1579 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL5, 0x09); 1580 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x04); 1581 break; 1582 case RTSX_RTL8411B: 1583 if (sc->rtsx_flags & RTSX_F_8411B_QFN48) { 1584 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0xaa); 1585 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xf9); 1586 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x19); 1587 } else { 1588 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0xaa); 1589 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0xaa); 1590 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xd9); 1591 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x59); 1592 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL5, 0x55); 1593 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x15); 1594 } 1595 break; 1596 } 1597 1598 /* 1599 * To avoid a current peak, enable card power in two phases 1600 * with a delay in between. 1601 */ 1602 switch (sc->rtsx_device_id) { 1603 case RTSX_RTS5209: 1604 /* Partial power. */ 1605 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PARTIAL_PWR_ON); 1606 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, RTSX_LDO3318_VCC2); 1607 1608 DELAY(200); 1609 1610 /* Full power. */ 1611 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PWR_ON); 1612 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, RTSX_LDO3318_ON); 1613 break; 1614 case RTSX_RTS5227: 1615 case RTSX_RTS522A: 1616 /* Partial power. */ 1617 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PARTIAL_PWR_ON); 1618 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, RTSX_LDO3318_VCC1); 1619 1620 DELAY(20000); 1621 1622 /* Full power. */ 1623 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PWR_ON); 1624 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, 1625 RTSX_LDO3318_VCC1 | RTSX_LDO3318_VCC2); 1626 RTSX_BITOP(sc, RTSX_CARD_OE, RTSX_SD_OUTPUT_EN, RTSX_SD_OUTPUT_EN); 1627 RTSX_BITOP(sc, RTSX_CARD_OE, RTSX_MS_OUTPUT_EN, RTSX_MS_OUTPUT_EN); 1628 break; 1629 case RTSX_RTS5229: 1630 /* Partial power. */ 1631 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PARTIAL_PWR_ON); 1632 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, RTSX_LDO3318_VCC1); 1633 1634 DELAY(200); 1635 1636 /* Full power. */ 1637 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PWR_ON); 1638 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, 1639 RTSX_LDO3318_VCC1 | RTSX_LDO3318_VCC2); 1640 break; 1641 case RTSX_RTS525A: 1642 RTSX_BITOP(sc, RTSX_LDO_VCC_CFG1, RTSX_LDO_VCC_TUNE_MASK, RTSX_LDO_VCC_3V3); 1643 case RTSX_RTS5249: 1644 /* Partial power. */ 1645 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PARTIAL_PWR_ON); 1646 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, RTSX_LDO3318_VCC1); 1647 1648 DELAY(5000); 1649 1650 /* Full power. */ 1651 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PWR_ON); 1652 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, 1653 RTSX_LDO3318_VCC1 | RTSX_LDO3318_VCC2); 1654 break; 1655 case RTSX_RTL8402: 1656 case RTSX_RTL8411: 1657 case RTSX_RTL8411B: 1658 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK, 1659 RTSX_BPP_POWER_5_PERCENT_ON); 1660 RTSX_BITOP(sc, RTSX_LDO_CTL, RTSX_BPP_LDO_POWB, 1661 RTSX_BPP_LDO_SUSPEND); 1662 DELAY(150); 1663 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK, 1664 RTSX_BPP_POWER_10_PERCENT_ON); 1665 DELAY(150); 1666 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK, 1667 RTSX_BPP_POWER_15_PERCENT_ON); 1668 DELAY(150); 1669 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK, 1670 RTSX_BPP_POWER_ON); 1671 RTSX_BITOP(sc, RTSX_LDO_CTL, RTSX_BPP_LDO_POWB, 1672 RTSX_BPP_LDO_ON); 1673 break; 1674 } 1675 1676 /* Enable SD card output. */ 1677 RTSX_WRITE(sc, RTSX_CARD_OE, RTSX_SD_OUTPUT_EN); 1678 1679 DELAY(200); 1680 1681 return (0); 1682 } 1683 1684 /* 1685 * Set but width. 1686 */ 1687 static int 1688 rtsx_set_bus_width(struct rtsx_softc *sc, enum mmc_bus_width width) 1689 { 1690 uint32_t bus_width; 1691 1692 switch (width) { 1693 case bus_width_1: 1694 bus_width = RTSX_BUS_WIDTH_1; 1695 break; 1696 case bus_width_4: 1697 bus_width = RTSX_BUS_WIDTH_4; 1698 break; 1699 case bus_width_8: 1700 bus_width = RTSX_BUS_WIDTH_8; 1701 break; 1702 default: 1703 return (MMC_ERR_INVALID); 1704 } 1705 RTSX_BITOP(sc, RTSX_SD_CFG1, RTSX_BUS_WIDTH_MASK, bus_width); 1706 1707 if (bootverbose || sc->rtsx_debug) { 1708 char *busw[] = { 1709 "1 bit", 1710 "4 bits", 1711 "8 bits" 1712 }; 1713 device_printf(sc->rtsx_dev, "Setting bus width to %s\n", busw[bus_width]); 1714 } 1715 return (0); 1716 } 1717 1718 static int 1719 rtsx_set_sd_timing(struct rtsx_softc *sc, enum mmc_bus_timing timing) 1720 { 1721 if (timing == bus_timing_hs && sc->rtsx_force_timing) { 1722 timing = bus_timing_uhs_sdr50; 1723 sc->rtsx_ios_timing = timing; 1724 } 1725 1726 if (bootverbose || sc->rtsx_debug) 1727 device_printf(sc->rtsx_dev, "rtsx_set_sd_timing(%u)\n", timing); 1728 1729 switch (timing) { 1730 case bus_timing_uhs_sdr50: 1731 case bus_timing_uhs_sdr104: 1732 sc->rtsx_double_clk = false; 1733 sc->rtsx_vpclk = true; 1734 RTSX_BITOP(sc, RTSX_SD_CFG1, 0x0c | RTSX_SD_ASYNC_FIFO_NOT_RST, 1735 RTSX_SD30_MODE | RTSX_SD_ASYNC_FIFO_NOT_RST); 1736 RTSX_BITOP(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ, RTSX_CLK_LOW_FREQ); 1737 RTSX_WRITE(sc, RTSX_CARD_CLK_SOURCE, 1738 RTSX_CRC_VAR_CLK0 | RTSX_SD30_FIX_CLK | RTSX_SAMPLE_VAR_CLK1); 1739 RTSX_CLR(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ); 1740 break; 1741 case bus_timing_hs: 1742 RTSX_BITOP(sc, RTSX_SD_CFG1, RTSX_SD_MODE_MASK, RTSX_SD20_MODE); 1743 RTSX_BITOP(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ, RTSX_CLK_LOW_FREQ); 1744 RTSX_WRITE(sc, RTSX_CARD_CLK_SOURCE, 1745 RTSX_CRC_FIX_CLK | RTSX_SD30_VAR_CLK0 | RTSX_SAMPLE_VAR_CLK1); 1746 RTSX_CLR(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ); 1747 1748 RTSX_BITOP(sc, RTSX_SD_PUSH_POINT_CTL, 1749 RTSX_SD20_TX_SEL_MASK, RTSX_SD20_TX_14_AHEAD); 1750 RTSX_BITOP(sc, RTSX_SD_SAMPLE_POINT_CTL, 1751 RTSX_SD20_RX_SEL_MASK, RTSX_SD20_RX_14_DELAY); 1752 break; 1753 default: 1754 RTSX_BITOP(sc, RTSX_SD_CFG1, RTSX_SD_MODE_MASK, RTSX_SD20_MODE); 1755 RTSX_BITOP(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ, RTSX_CLK_LOW_FREQ); 1756 RTSX_WRITE(sc, RTSX_CARD_CLK_SOURCE, 1757 RTSX_CRC_FIX_CLK | RTSX_SD30_VAR_CLK0 | RTSX_SAMPLE_VAR_CLK1); 1758 RTSX_CLR(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ); 1759 1760 RTSX_WRITE(sc, RTSX_SD_PUSH_POINT_CTL, RTSX_SD20_TX_NEG_EDGE); 1761 RTSX_BITOP(sc, RTSX_SD_SAMPLE_POINT_CTL, 1762 RTSX_SD20_RX_SEL_MASK, RTSX_SD20_RX_POS_EDGE); 1763 break; 1764 } 1765 1766 return (0); 1767 } 1768 1769 /* 1770 * Set or change SDCLK frequency or disable the SD clock. 1771 * Return zero on success. 1772 */ 1773 static int 1774 rtsx_set_sd_clock(struct rtsx_softc *sc, uint32_t freq) 1775 { 1776 uint8_t clk; 1777 uint8_t clk_divider, n, div, mcu; 1778 int error = 0; 1779 1780 if (bootverbose || sc->rtsx_debug) 1781 device_printf(sc->rtsx_dev, "rtsx_set_sd_clock(%u)\n", freq); 1782 1783 if (freq == RTSX_SDCLK_OFF) { 1784 error = rtsx_stop_sd_clock(sc); 1785 return error; 1786 } 1787 1788 sc->rtsx_ssc_depth = RTSX_SSC_DEPTH_500K; 1789 sc->rtsx_discovery_mode = (freq <= 1000000) ? true : false; 1790 1791 if (sc->rtsx_discovery_mode) { 1792 /* We use 250k(around) here, in discovery stage. */ 1793 clk_divider = RTSX_CLK_DIVIDE_128; 1794 freq = 30000000; 1795 } else { 1796 clk_divider = RTSX_CLK_DIVIDE_0; 1797 } 1798 RTSX_BITOP(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK, clk_divider); 1799 1800 freq /= 1000000; 1801 if (sc->rtsx_discovery_mode || !sc->rtsx_double_clk) 1802 clk = freq; 1803 else 1804 clk = freq * 2; 1805 1806 switch (sc->rtsx_device_id) { 1807 case RTSX_RTL8402: 1808 case RTSX_RTL8411: 1809 case RTSX_RTL8411B: 1810 n = clk * 4 / 5 - 2; 1811 break; 1812 default: 1813 n = clk - 2; 1814 break; 1815 } 1816 if ((clk <= 2) || (n > RTSX_MAX_DIV_N)) 1817 return (MMC_ERR_INVALID); 1818 1819 mcu = 125 / clk + 3; 1820 if (mcu > 15) 1821 mcu = 15; 1822 1823 /* Make sure that the SSC clock div_n is not less than RTSX_MIN_DIV_N. */ 1824 div = RTSX_CLK_DIV_1; 1825 while ((n < RTSX_MIN_DIV_N) && (div < RTSX_CLK_DIV_8)) { 1826 switch (sc->rtsx_device_id) { 1827 case RTSX_RTL8402: 1828 case RTSX_RTL8411: 1829 case RTSX_RTL8411B: 1830 n = (((n + 2) * 5 / 4) * 2) * 4 / 5 - 2; 1831 break; 1832 default: 1833 n = (n + 2) * 2 - 2; 1834 break; 1835 } 1836 div++; 1837 } 1838 1839 if (sc->rtsx_double_clk && sc->rtsx_ssc_depth > 1) 1840 sc->rtsx_ssc_depth -= 1; 1841 1842 if (div > RTSX_CLK_DIV_1) { 1843 if (sc->rtsx_ssc_depth > (div - 1)) 1844 sc->rtsx_ssc_depth -= (div - 1); 1845 else 1846 sc->rtsx_ssc_depth = RTSX_SSC_DEPTH_4M; 1847 } 1848 1849 /* Enable SD clock. */ 1850 error = rtsx_switch_sd_clock(sc, clk, n, div, mcu); 1851 1852 return (error); 1853 } 1854 1855 static int 1856 rtsx_stop_sd_clock(struct rtsx_softc *sc) 1857 { 1858 RTSX_CLR(sc, RTSX_CARD_CLK_EN, RTSX_CARD_CLK_EN_ALL); 1859 RTSX_SET(sc, RTSX_SD_BUS_STAT, RTSX_SD_CLK_FORCE_STOP); 1860 1861 return (0); 1862 } 1863 1864 static int 1865 rtsx_switch_sd_clock(struct rtsx_softc *sc, uint8_t clk, uint8_t n, uint8_t div, uint8_t mcu) 1866 { 1867 if (bootverbose || sc->rtsx_debug) { 1868 device_printf(sc->rtsx_dev, "rtsx_switch_sd_clock() - discovery-mode is %s, ssc_depth: %d\n", 1869 (sc->rtsx_discovery_mode) ? "true" : "false", sc->rtsx_ssc_depth); 1870 device_printf(sc->rtsx_dev, "rtsx_switch_sd_clock() - clk: %d, n: %d, div: %d, mcu: %d\n", 1871 clk, n, div, mcu); 1872 } 1873 1874 RTSX_BITOP(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ, RTSX_CLK_LOW_FREQ); 1875 RTSX_WRITE(sc, RTSX_CLK_DIV, (div << 4) | mcu); 1876 RTSX_CLR(sc, RTSX_SSC_CTL1, RTSX_RSTB); 1877 RTSX_BITOP(sc, RTSX_SSC_CTL2, RTSX_SSC_DEPTH_MASK, sc->rtsx_ssc_depth); 1878 RTSX_WRITE(sc, RTSX_SSC_DIV_N_0, n); 1879 RTSX_BITOP(sc, RTSX_SSC_CTL1, RTSX_RSTB, RTSX_RSTB); 1880 if (sc->rtsx_vpclk) { 1881 RTSX_CLR(sc, RTSX_SD_VPCLK0_CTL, RTSX_PHASE_NOT_RESET); 1882 RTSX_BITOP(sc, RTSX_SD_VPCLK0_CTL, RTSX_PHASE_NOT_RESET, RTSX_PHASE_NOT_RESET); 1883 } 1884 1885 /* Wait SSC clock stable. */ 1886 DELAY(200); 1887 1888 RTSX_CLR(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ); 1889 1890 return (0); 1891 } 1892 1893 static void 1894 rtsx_sd_change_tx_phase(struct rtsx_softc *sc, uint8_t sample_point) 1895 { 1896 if (bootverbose || sc->rtsx_debug) 1897 device_printf(sc->rtsx_dev, "rtsx_sd_change_tx_phase() - sample_point: %d\n", sample_point); 1898 1899 rtsx_write(sc, RTSX_CLK_CTL, RTSX_CHANGE_CLK, RTSX_CHANGE_CLK); 1900 rtsx_write(sc, RTSX_SD_VPCLK0_CTL, RTSX_PHASE_SELECT_MASK, sample_point); 1901 rtsx_write(sc, RTSX_SD_VPCLK0_CTL, RTSX_PHASE_NOT_RESET, 0); 1902 rtsx_write(sc, RTSX_SD_VPCLK0_CTL, RTSX_PHASE_NOT_RESET, RTSX_PHASE_NOT_RESET); 1903 rtsx_write(sc, RTSX_CLK_CTL, RTSX_CHANGE_CLK, 0); 1904 rtsx_write(sc, RTSX_SD_CFG1, RTSX_SD_ASYNC_FIFO_NOT_RST, 0); 1905 } 1906 1907 static void 1908 rtsx_sd_change_rx_phase(struct rtsx_softc *sc, uint8_t sample_point) 1909 { 1910 if (bootverbose || sc->rtsx_debug == 2) 1911 device_printf(sc->rtsx_dev, "rtsx_sd_change_rx_phase() - sample_point: %d\n", sample_point); 1912 1913 rtsx_write(sc, RTSX_CLK_CTL, RTSX_CHANGE_CLK, RTSX_CHANGE_CLK); 1914 rtsx_write(sc, RTSX_SD_VPCLK1_CTL, RTSX_PHASE_SELECT_MASK, sample_point); 1915 rtsx_write(sc, RTSX_SD_VPCLK1_CTL, RTSX_PHASE_NOT_RESET, 0); 1916 rtsx_write(sc, RTSX_SD_VPCLK1_CTL, RTSX_PHASE_NOT_RESET, RTSX_PHASE_NOT_RESET); 1917 rtsx_write(sc, RTSX_CLK_CTL, RTSX_CHANGE_CLK, 0); 1918 rtsx_write(sc, RTSX_SD_CFG1, RTSX_SD_ASYNC_FIFO_NOT_RST, 0); 1919 } 1920 1921 static void 1922 rtsx_sd_tuning_rx_phase(struct rtsx_softc *sc, uint32_t *phase_map) 1923 { 1924 uint32_t raw_phase_map = 0; 1925 int i; 1926 int error; 1927 1928 for (i = 0; i < RTSX_RX_PHASE_MAX; i++) { 1929 error = rtsx_sd_tuning_rx_cmd(sc, (uint8_t)i); 1930 if (error == 0) 1931 raw_phase_map |= 1 << i; 1932 } 1933 if (phase_map != NULL) 1934 *phase_map = raw_phase_map; 1935 } 1936 1937 static int 1938 rtsx_sd_tuning_rx_cmd(struct rtsx_softc *sc, uint8_t sample_point) 1939 { 1940 struct mmc_request req = {}; 1941 struct mmc_command cmd = {}; 1942 int error = 0; 1943 1944 cmd.opcode = MMC_SEND_TUNING_BLOCK; 1945 cmd.arg = 0; 1946 req.cmd = &cmd; 1947 1948 RTSX_LOCK(sc); 1949 1950 sc->rtsx_req = &req; 1951 1952 rtsx_sd_change_rx_phase(sc, sample_point); 1953 1954 rtsx_write(sc, RTSX_SD_CFG3, RTSX_SD_RSP_80CLK_TIMEOUT_EN, 1955 RTSX_SD_RSP_80CLK_TIMEOUT_EN); 1956 1957 rtsx_init_cmd(sc, &cmd); 1958 rtsx_set_cmd_data_len(sc, 1, 0x40); 1959 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 0xff, 1960 RTSX_SD_CALCULATE_CRC7 | RTSX_SD_CHECK_CRC16 | 1961 RTSX_SD_NO_WAIT_BUSY_END | RTSX_SD_CHECK_CRC7 | RTSX_SD_RSP_LEN_6); 1962 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 1963 0xff, RTSX_TM_AUTO_TUNING | RTSX_SD_TRANSFER_START); 1964 rtsx_push_cmd(sc, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, 1965 RTSX_SD_TRANSFER_END, RTSX_SD_TRANSFER_END); 1966 1967 /* Set interrupt post processing */ 1968 sc->rtsx_intr_trans_ok = rtsx_sd_tuning_rx_cmd_wakeup; 1969 sc->rtsx_intr_trans_ko = rtsx_sd_tuning_rx_cmd_wakeup; 1970 1971 /* Run the command queue. */ 1972 rtsx_send_cmd(sc); 1973 1974 error = rtsx_sd_tuning_rx_cmd_wait(sc, &cmd); 1975 1976 if (error) { 1977 if (bootverbose || sc->rtsx_debug == 2) 1978 device_printf(sc->rtsx_dev, "rtsx_sd_tuning_rx_cmd() - error: %d\n", error); 1979 rtsx_sd_wait_data_idle(sc); 1980 rtsx_clear_error(sc); 1981 } 1982 rtsx_write(sc, RTSX_SD_CFG3, RTSX_SD_RSP_80CLK_TIMEOUT_EN, 0); 1983 1984 sc->rtsx_req = NULL; 1985 1986 RTSX_UNLOCK(sc); 1987 1988 return (error); 1989 } 1990 1991 static int 1992 rtsx_sd_tuning_rx_cmd_wait(struct rtsx_softc *sc, struct mmc_command *cmd) 1993 { 1994 int status; 1995 int mask = RTSX_TRANS_OK_INT | RTSX_TRANS_FAIL_INT; 1996 1997 status = sc->rtsx_intr_status & mask; 1998 while (status == 0) { 1999 if (msleep(&sc->rtsx_intr_status, &sc->rtsx_mtx, 0, "rtsxintr", sc->rtsx_timeout_cmd) == EWOULDBLOCK) { 2000 cmd->error = MMC_ERR_TIMEOUT; 2001 return (MMC_ERR_TIMEOUT); 2002 } 2003 status = sc->rtsx_intr_status & mask; 2004 } 2005 return (cmd->error); 2006 } 2007 2008 static void 2009 rtsx_sd_tuning_rx_cmd_wakeup(struct rtsx_softc *sc) 2010 { 2011 wakeup(&sc->rtsx_intr_status); 2012 } 2013 2014 static void 2015 rtsx_sd_wait_data_idle(struct rtsx_softc *sc) 2016 { 2017 int i; 2018 uint8_t val; 2019 2020 for (i = 0; i < 100; i++) { 2021 rtsx_read(sc, RTSX_SD_DATA_STATE, &val); 2022 if (val & RTSX_SD_DATA_IDLE) 2023 return; 2024 DELAY(100); 2025 } 2026 } 2027 2028 static uint8_t 2029 rtsx_sd_search_final_rx_phase(struct rtsx_softc *sc, uint32_t phase_map) 2030 { 2031 int start = 0, len = 0; 2032 int start_final = 0, len_final = 0; 2033 uint8_t final_phase = 0xff; 2034 2035 while (start < RTSX_RX_PHASE_MAX) { 2036 len = rtsx_sd_get_rx_phase_len(phase_map, start); 2037 if (len_final < len) { 2038 start_final = start; 2039 len_final = len; 2040 } 2041 start += len ? len : 1; 2042 } 2043 2044 final_phase = (start_final + len_final / 2) % RTSX_RX_PHASE_MAX; 2045 2046 if (bootverbose || sc->rtsx_debug) 2047 device_printf(sc->rtsx_dev, 2048 "rtsx_sd_search_final_rx_phase() - phase_map: %x, start_final: %d, len_final: %d, final_phase: %d\n", 2049 phase_map, start_final, len_final, final_phase); 2050 2051 return final_phase; 2052 } 2053 2054 static int 2055 rtsx_sd_get_rx_phase_len(uint32_t phase_map, int start_bit) 2056 { 2057 int i; 2058 2059 for (i = 0; i < RTSX_RX_PHASE_MAX; i++) { 2060 if ((phase_map & (1 << (start_bit + i) % RTSX_RX_PHASE_MAX)) == 0) 2061 return i; 2062 } 2063 return RTSX_RX_PHASE_MAX; 2064 } 2065 2066 #if 0 /* For led */ 2067 static int 2068 rtsx_led_enable(struct rtsx_softc *sc) 2069 { 2070 switch (sc->rtsx_device_id) { 2071 case RTSX_RTS5209: 2072 RTSX_CLR(sc, RTSX_CARD_GPIO, RTSX_CARD_GPIO_LED_OFF); 2073 RTSX_WRITE(sc, RTSX_CARD_AUTO_BLINK, 2074 RTSX_LED_BLINK_EN | RTSX_LED_BLINK_SPEED); 2075 break; 2076 case RTSX_RTL8411B: 2077 RTSX_CLR(sc, RTSX_GPIO_CTL, 0x01); 2078 RTSX_WRITE(sc, RTSX_CARD_AUTO_BLINK, 2079 RTSX_LED_BLINK_EN | RTSX_LED_BLINK_SPEED); 2080 break; 2081 default: 2082 RTSX_SET(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON); 2083 RTSX_SET(sc, RTSX_OLT_LED_CTL, RTSX_OLT_LED_AUTOBLINK); 2084 break; 2085 } 2086 2087 return (0); 2088 } 2089 2090 static int 2091 rtsx_led_disable(struct rtsx_softc *sc) 2092 { 2093 switch (sc->rtsx_device_id) { 2094 case RTSX_RTS5209: 2095 RTSX_CLR(sc, RTSX_CARD_AUTO_BLINK, RTSX_LED_BLINK_EN); 2096 RTSX_WRITE(sc, RTSX_CARD_GPIO, RTSX_CARD_GPIO_LED_OFF); 2097 break; 2098 case RTSX_RTL8411B: 2099 RTSX_CLR(sc, RTSX_CARD_AUTO_BLINK, RTSX_LED_BLINK_EN); 2100 RTSX_SET(sc, RTSX_GPIO_CTL, 0x01); 2101 break; 2102 default: 2103 RTSX_CLR(sc, RTSX_OLT_LED_CTL, RTSX_OLT_LED_AUTOBLINK); 2104 RTSX_CLR(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON); 2105 break; 2106 } 2107 2108 return (0); 2109 } 2110 #endif /* For led */ 2111 2112 static uint8_t 2113 rtsx_response_type(uint16_t mmc_rsp) 2114 { 2115 int i; 2116 struct rsp_type { 2117 uint16_t mmc_rsp; 2118 uint8_t rtsx_rsp; 2119 } rsp_types[] = { 2120 { MMC_RSP_NONE, RTSX_SD_RSP_TYPE_R0 }, 2121 { MMC_RSP_R1, RTSX_SD_RSP_TYPE_R1 }, 2122 { MMC_RSP_R1B, RTSX_SD_RSP_TYPE_R1B }, 2123 { MMC_RSP_R2, RTSX_SD_RSP_TYPE_R2 }, 2124 { MMC_RSP_R3, RTSX_SD_RSP_TYPE_R3 }, 2125 { MMC_RSP_R4, RTSX_SD_RSP_TYPE_R4 }, 2126 { MMC_RSP_R5, RTSX_SD_RSP_TYPE_R5 }, 2127 { MMC_RSP_R6, RTSX_SD_RSP_TYPE_R6 }, 2128 { MMC_RSP_R7, RTSX_SD_RSP_TYPE_R7 } 2129 }; 2130 2131 for (i = 0; i < nitems(rsp_types); i++) { 2132 if (mmc_rsp == rsp_types[i].mmc_rsp) 2133 return (rsp_types[i].rtsx_rsp); 2134 } 2135 2136 return (0); 2137 } 2138 2139 /* 2140 * Init command buffer with SD command index and argument. 2141 */ 2142 static void 2143 rtsx_init_cmd(struct rtsx_softc *sc, struct mmc_command *cmd) 2144 { 2145 sc->rtsx_cmd_index = 0; 2146 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CMD0, 2147 0xff, RTSX_SD_CMD_START | cmd->opcode); 2148 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CMD1, 2149 0xff, cmd->arg >> 24); 2150 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CMD2, 2151 0xff, cmd->arg >> 16); 2152 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CMD3, 2153 0xff, cmd->arg >> 8); 2154 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CMD4, 2155 0xff, cmd->arg); 2156 } 2157 2158 /* 2159 * Append a properly encoded host command to the host command buffer. 2160 */ 2161 static void 2162 rtsx_push_cmd(struct rtsx_softc *sc, uint8_t cmd, uint16_t reg, 2163 uint8_t mask, uint8_t data) 2164 { 2165 KASSERT(sc->rtsx_cmd_index < RTSX_HOSTCMD_MAX, 2166 ("rtsx: Too many host commands (%d)\n", sc->rtsx_cmd_index)); 2167 2168 uint32_t *cmd_buffer = (uint32_t *)(sc->rtsx_cmd_dmamem); 2169 cmd_buffer[sc->rtsx_cmd_index++] = 2170 htole32((uint32_t)(cmd & 0x3) << 30) | 2171 ((uint32_t)(reg & 0x3fff) << 16) | 2172 ((uint32_t)(mask) << 8) | 2173 ((uint32_t)data); 2174 } 2175 2176 /* 2177 * Queue commands to configure data transfer size. 2178 */ 2179 static void 2180 rtsx_set_cmd_data_len(struct rtsx_softc *sc, uint16_t block_cnt, uint16_t byte_cnt) 2181 { 2182 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BLOCK_CNT_L, 2183 0xff, block_cnt & 0xff); 2184 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BLOCK_CNT_H, 2185 0xff, block_cnt >> 8); 2186 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BYTE_CNT_L, 2187 0xff, byte_cnt & 0xff); 2188 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BYTE_CNT_H, 2189 0xff, byte_cnt >> 8); 2190 } 2191 2192 /* 2193 * Run the command queue. 2194 */ 2195 static void 2196 rtsx_send_cmd(struct rtsx_softc *sc) 2197 { 2198 if (bootverbose) 2199 device_printf(sc->rtsx_dev, "rtsx_send_cmd()\n"); 2200 2201 sc->rtsx_intr_status = 0; 2202 2203 /* Sync command DMA buffer. */ 2204 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_PREREAD); 2205 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_PREWRITE); 2206 2207 /* Tell the chip where the command buffer is and run the commands. */ 2208 WRITE4(sc, RTSX_HCBAR, (uint32_t)sc->rtsx_cmd_buffer); 2209 WRITE4(sc, RTSX_HCBCTLR, 2210 ((sc->rtsx_cmd_index * 4) & 0x00ffffff) | RTSX_START_CMD | RTSX_HW_AUTO_RSP); 2211 } 2212 2213 /* 2214 * Stop previous command. 2215 */ 2216 static void 2217 rtsx_stop_cmd(struct rtsx_softc *sc) 2218 { 2219 /* Stop command transfer. */ 2220 WRITE4(sc, RTSX_HCBCTLR, RTSX_STOP_CMD); 2221 2222 /* Stop DMA transfer. */ 2223 WRITE4(sc, RTSX_HDBCTLR, RTSX_STOP_DMA); 2224 2225 rtsx_write(sc, RTSX_DMACTL, RTSX_DMA_RST, RTSX_DMA_RST); 2226 2227 rtsx_write(sc, RTSX_RBCTL, RTSX_RB_FLUSH, RTSX_RB_FLUSH); 2228 } 2229 2230 /* 2231 * Clear error. 2232 */ 2233 static void 2234 rtsx_clear_error(struct rtsx_softc *sc) 2235 { 2236 /* Clear error. */ 2237 rtsx_write(sc, RTSX_CARD_STOP, RTSX_SD_STOP | RTSX_SD_CLR_ERR, 2238 RTSX_SD_STOP | RTSX_SD_CLR_ERR); 2239 } 2240 2241 /* 2242 * Signal end of request to mmc/mmcsd. 2243 */ 2244 static void 2245 rtsx_req_done(struct rtsx_softc *sc) 2246 { 2247 #ifdef MMCCAM 2248 union ccb *ccb; 2249 #endif /* MMCCAM */ 2250 struct mmc_request *req; 2251 2252 req = sc->rtsx_req; 2253 if (req->cmd->error == MMC_ERR_NONE) { 2254 if (req->cmd->opcode == MMC_READ_SINGLE_BLOCK || 2255 req->cmd->opcode == MMC_READ_MULTIPLE_BLOCK) 2256 sc->rtsx_read_count++; 2257 else if (req->cmd->opcode == MMC_WRITE_BLOCK || 2258 req->cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK) 2259 sc->rtsx_write_count++; 2260 } else { 2261 rtsx_clear_error(sc); 2262 } 2263 callout_stop(&sc->rtsx_timeout_callout); 2264 sc->rtsx_req = NULL; 2265 #ifdef MMCCAM 2266 ccb = sc->rtsx_ccb; 2267 sc->rtsx_ccb = NULL; 2268 ccb->ccb_h.status = (req->cmd->error == 0 ? CAM_REQ_CMP : CAM_REQ_CMP_ERR); 2269 xpt_done(ccb); 2270 #else /* !MMCCAM */ 2271 req->done(req); 2272 #endif /* MMCCAM */ 2273 } 2274 2275 /* 2276 * Send request. 2277 */ 2278 static int 2279 rtsx_send_req(struct rtsx_softc *sc, struct mmc_command *cmd) 2280 { 2281 uint8_t rsp_type; 2282 uint16_t reg; 2283 2284 if (bootverbose) 2285 device_printf(sc->rtsx_dev, "rtsx_send_req() - CMD%d\n", cmd->opcode); 2286 2287 /* Convert response type. */ 2288 rsp_type = rtsx_response_type(cmd->flags & MMC_RSP_MASK); 2289 if (rsp_type == 0) { 2290 device_printf(sc->rtsx_dev, "Unknown rsp_type: 0x%lx\n", (cmd->flags & MMC_RSP_MASK)); 2291 cmd->error = MMC_ERR_INVALID; 2292 return (MMC_ERR_INVALID); 2293 } 2294 2295 rtsx_init_cmd(sc, cmd); 2296 2297 /* Queue command to set response type. */ 2298 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 0xff, rsp_type); 2299 2300 /* Use the ping-pong buffer (cmd buffer) for commands which do not transfer data. */ 2301 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_CARD_DATA_SOURCE, 2302 0x01, RTSX_PINGPONG_BUFFER); 2303 2304 /* Queue commands to perform SD transfer. */ 2305 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 2306 0xff, RTSX_TM_CMD_RSP | RTSX_SD_TRANSFER_START); 2307 rtsx_push_cmd(sc, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, 2308 RTSX_SD_TRANSFER_END|RTSX_SD_STAT_IDLE, 2309 RTSX_SD_TRANSFER_END|RTSX_SD_STAT_IDLE); 2310 2311 /* If needed queue commands to read back card status response. */ 2312 if (rsp_type == RTSX_SD_RSP_TYPE_R2) { 2313 /* Read data from ping-pong buffer. */ 2314 for (reg = RTSX_PPBUF_BASE2; reg < RTSX_PPBUF_BASE2 + 16; reg++) 2315 rtsx_push_cmd(sc, RTSX_READ_REG_CMD, reg, 0, 0); 2316 } else if (rsp_type != RTSX_SD_RSP_TYPE_R0) { 2317 /* Read data from SD_CMDx registers. */ 2318 for (reg = RTSX_SD_CMD0; reg <= RTSX_SD_CMD4; reg++) 2319 rtsx_push_cmd(sc, RTSX_READ_REG_CMD, reg, 0, 0); 2320 } 2321 rtsx_push_cmd(sc, RTSX_READ_REG_CMD, RTSX_SD_STAT1, 0, 0); 2322 2323 /* Set transfer OK function. */ 2324 if (sc->rtsx_intr_trans_ok == NULL) 2325 sc->rtsx_intr_trans_ok = rtsx_ret_resp; 2326 2327 /* Run the command queue. */ 2328 rtsx_send_cmd(sc); 2329 2330 return (0); 2331 } 2332 2333 /* 2334 * Return response of previous command (case cmd->data == NULL) and complete resquest. 2335 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2336 */ 2337 static void 2338 rtsx_ret_resp(struct rtsx_softc *sc) 2339 { 2340 struct mmc_command *cmd; 2341 2342 cmd = sc->rtsx_req->cmd; 2343 rtsx_set_resp(sc, cmd); 2344 rtsx_req_done(sc); 2345 } 2346 2347 /* 2348 * Set response of previous command. 2349 */ 2350 static void 2351 rtsx_set_resp(struct rtsx_softc *sc, struct mmc_command *cmd) 2352 { 2353 uint8_t rsp_type; 2354 2355 rsp_type = rtsx_response_type(cmd->flags & MMC_RSP_MASK); 2356 2357 /* Sync command DMA buffer. */ 2358 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTREAD); 2359 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTWRITE); 2360 2361 /* Copy card response into mmc response buffer. */ 2362 if (ISSET(cmd->flags, MMC_RSP_PRESENT)) { 2363 uint32_t *cmd_buffer = (uint32_t *)(sc->rtsx_cmd_dmamem); 2364 2365 if (bootverbose) { 2366 device_printf(sc->rtsx_dev, "cmd_buffer: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", 2367 cmd_buffer[0], cmd_buffer[1], cmd_buffer[2], cmd_buffer[3], cmd_buffer[4]); 2368 } 2369 2370 if (rsp_type == RTSX_SD_RSP_TYPE_R2) { 2371 /* First byte is CHECK_REG_CMD return value, skip it. */ 2372 unsigned char *ptr = (unsigned char *)cmd_buffer + 1; 2373 int i; 2374 2375 /* 2376 * The controller offloads the last byte {CRC-7, end bit 1} 2377 * of response type R2. Assign dummy CRC, 0, and end bit to this 2378 * byte (ptr[16], goes into the LSB of resp[3] later). 2379 */ 2380 ptr[16] = 0x01; 2381 /* The second byte is the status of response, skip it. */ 2382 for (i = 0; i < 4; i++) 2383 cmd->resp[i] = be32dec(ptr + 1 + i * 4); 2384 } else { 2385 /* 2386 * First byte is CHECK_REG_CMD return value, second 2387 * one is the command op code -- we skip those. 2388 */ 2389 cmd->resp[0] = 2390 ((be32toh(cmd_buffer[0]) & 0x0000ffff) << 16) | 2391 ((be32toh(cmd_buffer[1]) & 0xffff0000) >> 16); 2392 } 2393 2394 if (bootverbose) 2395 device_printf(sc->rtsx_dev, "cmd->resp: 0x%08x 0x%08x 0x%08x 0x%08x\n", 2396 cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); 2397 } 2398 } 2399 2400 /* 2401 * Use the ping-pong buffer (cmd buffer) for transfer <= 512 bytes. 2402 */ 2403 static int 2404 rtsx_xfer_short(struct rtsx_softc *sc, struct mmc_command *cmd) 2405 { 2406 int read; 2407 2408 if (cmd->data == NULL || cmd->data->len == 0) { 2409 cmd->error = MMC_ERR_INVALID; 2410 return (MMC_ERR_INVALID); 2411 } 2412 cmd->data->xfer_len = (cmd->data->len > RTSX_MAX_DATA_BLKLEN) ? 2413 RTSX_MAX_DATA_BLKLEN : cmd->data->len; 2414 2415 read = ISSET(cmd->data->flags, MMC_DATA_READ); 2416 2417 if (bootverbose) 2418 device_printf(sc->rtsx_dev, "rtsx_xfer_short() - %s xfer: %ld bytes with block size %ld\n", 2419 read ? "Read" : "Write", 2420 (unsigned long)cmd->data->len, (unsigned long)cmd->data->xfer_len); 2421 2422 if (cmd->data->len > 512) { 2423 device_printf(sc->rtsx_dev, "rtsx_xfer_short() - length too large: %ld > 512\n", 2424 (unsigned long)cmd->data->len); 2425 cmd->error = MMC_ERR_INVALID; 2426 return (MMC_ERR_INVALID); 2427 } 2428 2429 if (read) { 2430 if (sc->rtsx_discovery_mode) 2431 rtsx_write(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK, RTSX_CLK_DIVIDE_0); 2432 2433 rtsx_init_cmd(sc, cmd); 2434 2435 /* Queue commands to configure data transfer size. */ 2436 rtsx_set_cmd_data_len(sc, cmd->data->len / cmd->data->xfer_len, cmd->data->xfer_len); 2437 2438 /* From Linux: rtsx_pci_sdmmc.c sd_read_data(). */ 2439 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 0xff, 2440 RTSX_SD_CALCULATE_CRC7 | RTSX_SD_CHECK_CRC16 | 2441 RTSX_SD_NO_WAIT_BUSY_END | RTSX_SD_CHECK_CRC7 | RTSX_SD_RSP_LEN_6); 2442 2443 /* Use the ping-pong buffer (cmd buffer). */ 2444 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_CARD_DATA_SOURCE, 2445 0x01, RTSX_PINGPONG_BUFFER); 2446 2447 /* Queue commands to perform SD transfer. */ 2448 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 2449 0xff, RTSX_TM_NORMAL_READ | RTSX_SD_TRANSFER_START); 2450 rtsx_push_cmd(sc, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, 2451 RTSX_SD_TRANSFER_END, RTSX_SD_TRANSFER_END); 2452 2453 /* Set transfer OK function. */ 2454 sc->rtsx_intr_trans_ok = rtsx_ask_ppbuf_part1; 2455 2456 /* Run the command queue. */ 2457 rtsx_send_cmd(sc); 2458 } else { 2459 /* Set transfer OK function. */ 2460 sc->rtsx_intr_trans_ok = rtsx_put_ppbuf_part1; 2461 2462 /* Run the command queue. */ 2463 rtsx_send_req(sc, cmd); 2464 } 2465 2466 return (0); 2467 } 2468 2469 /* 2470 * Use the ping-pong buffer (cmd buffer) for the transfer - first part <= 256 bytes. 2471 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2472 */ 2473 static void 2474 rtsx_ask_ppbuf_part1(struct rtsx_softc *sc) 2475 { 2476 struct mmc_command *cmd; 2477 uint16_t reg = RTSX_PPBUF_BASE2; 2478 int len; 2479 int i; 2480 2481 cmd = sc->rtsx_req->cmd; 2482 len = (cmd->data->len > RTSX_HOSTCMD_MAX) ? RTSX_HOSTCMD_MAX : cmd->data->len; 2483 2484 sc->rtsx_cmd_index = 0; 2485 for (i = 0; i < len; i++) { 2486 rtsx_push_cmd(sc, RTSX_READ_REG_CMD, reg++, 0, 0); 2487 } 2488 2489 /* Set transfer OK function. */ 2490 sc->rtsx_intr_trans_ok = rtsx_get_ppbuf_part1; 2491 2492 /* Run the command queue. */ 2493 rtsx_send_cmd(sc); 2494 } 2495 2496 /* 2497 * Get the data from the ping-pong buffer (cmd buffer) - first part <= 256 bytes. 2498 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2499 */ 2500 static void 2501 rtsx_get_ppbuf_part1(struct rtsx_softc *sc) 2502 { 2503 struct mmc_command *cmd; 2504 uint8_t *ptr; 2505 int len; 2506 2507 cmd = sc->rtsx_req->cmd; 2508 ptr = cmd->data->data; 2509 len = (cmd->data->len > RTSX_HOSTCMD_MAX) ? RTSX_HOSTCMD_MAX : cmd->data->len; 2510 2511 /* Sync command DMA buffer. */ 2512 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTREAD); 2513 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTWRITE); 2514 2515 memcpy(ptr, sc->rtsx_cmd_dmamem, len); 2516 2517 len = (cmd->data->len > RTSX_HOSTCMD_MAX) ? cmd->data->len - RTSX_HOSTCMD_MAX : 0; 2518 2519 /* Use the ping-pong buffer (cmd buffer) for the transfer - second part > 256 bytes. */ 2520 if (len > 0) { 2521 uint16_t reg = RTSX_PPBUF_BASE2 + RTSX_HOSTCMD_MAX; 2522 int i; 2523 2524 sc->rtsx_cmd_index = 0; 2525 for (i = 0; i < len; i++) { 2526 rtsx_push_cmd(sc, RTSX_READ_REG_CMD, reg++, 0, 0); 2527 } 2528 2529 /* Set transfer OK function. */ 2530 sc->rtsx_intr_trans_ok = rtsx_get_ppbuf_part2; 2531 2532 /* Run the command queue. */ 2533 rtsx_send_cmd(sc); 2534 } else { 2535 if (bootverbose && cmd->opcode == ACMD_SEND_SCR) { 2536 uint8_t *ptr = cmd->data->data; 2537 device_printf(sc->rtsx_dev, "SCR: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n", 2538 ptr[0], ptr[1], ptr[2], ptr[3], 2539 ptr[4], ptr[5], ptr[6], ptr[7]); 2540 } 2541 2542 if (sc->rtsx_discovery_mode) 2543 rtsx_write(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK, RTSX_CLK_DIVIDE_128); 2544 2545 rtsx_req_done(sc); 2546 } 2547 } 2548 2549 /* 2550 * Get the data from the ping-pong buffer (cmd buffer) - second part > 256 bytes. 2551 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2552 */ 2553 static void 2554 rtsx_get_ppbuf_part2(struct rtsx_softc *sc) 2555 { 2556 struct mmc_command *cmd; 2557 uint8_t *ptr; 2558 int len; 2559 2560 cmd = sc->rtsx_req->cmd; 2561 ptr = cmd->data->data; 2562 ptr += RTSX_HOSTCMD_MAX; 2563 len = cmd->data->len - RTSX_HOSTCMD_MAX; 2564 2565 /* Sync command DMA buffer. */ 2566 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTREAD); 2567 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTWRITE); 2568 2569 memcpy(ptr, sc->rtsx_cmd_dmamem, len); 2570 2571 if (sc->rtsx_discovery_mode) 2572 rtsx_write(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK, RTSX_CLK_DIVIDE_128); 2573 2574 rtsx_req_done(sc); 2575 } 2576 2577 /* 2578 * Use the ping-pong buffer (cmd buffer) for transfer - first part <= 256 bytes. 2579 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2580 */ 2581 static void 2582 rtsx_put_ppbuf_part1(struct rtsx_softc *sc) 2583 { 2584 struct mmc_command *cmd; 2585 uint16_t reg = RTSX_PPBUF_BASE2; 2586 uint8_t *ptr; 2587 int len; 2588 int i; 2589 2590 cmd = sc->rtsx_req->cmd; 2591 ptr = cmd->data->data; 2592 len = (cmd->data->len > RTSX_HOSTCMD_MAX) ? RTSX_HOSTCMD_MAX : cmd->data->len; 2593 2594 rtsx_set_resp(sc, cmd); 2595 2596 sc->rtsx_cmd_index = 0; 2597 for (i = 0; i < len; i++) { 2598 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, reg++, 0xff, *ptr); 2599 ptr++; 2600 } 2601 2602 /* Set transfer OK function. */ 2603 if (cmd->data->len > RTSX_HOSTCMD_MAX) 2604 sc->rtsx_intr_trans_ok = rtsx_put_ppbuf_part2; 2605 else 2606 sc->rtsx_intr_trans_ok = rtsx_write_ppbuf; 2607 2608 /* Run the command queue. */ 2609 rtsx_send_cmd(sc); 2610 } 2611 2612 /* 2613 * Use the ping-pong buffer (cmd buffer) for transfer - second part > 256 bytes. 2614 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2615 */ 2616 static void 2617 rtsx_put_ppbuf_part2(struct rtsx_softc *sc) 2618 { 2619 struct mmc_command *cmd; 2620 uint16_t reg = RTSX_PPBUF_BASE2 + RTSX_HOSTCMD_MAX; 2621 uint8_t *ptr; 2622 int len; 2623 int i; 2624 2625 cmd = sc->rtsx_req->cmd; 2626 ptr = cmd->data->data; 2627 ptr += RTSX_HOSTCMD_MAX; 2628 len = cmd->data->len - RTSX_HOSTCMD_MAX; 2629 2630 sc->rtsx_cmd_index = 0; 2631 for (i = 0; i < len; i++) { 2632 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, reg++, 0xff, *ptr); 2633 ptr++; 2634 } 2635 2636 /* Set transfer OK function. */ 2637 sc->rtsx_intr_trans_ok = rtsx_write_ppbuf; 2638 2639 /* Run the command queue. */ 2640 rtsx_send_cmd(sc); 2641 } 2642 2643 /* 2644 * Write the data previously given via the ping-pong buffer on the card. 2645 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2646 */ 2647 static void 2648 rtsx_write_ppbuf(struct rtsx_softc *sc) 2649 { 2650 struct mmc_command *cmd; 2651 2652 cmd = sc->rtsx_req->cmd; 2653 2654 sc->rtsx_cmd_index = 0; 2655 2656 /* Queue commands to configure data transfer size. */ 2657 rtsx_set_cmd_data_len(sc, cmd->data->len / cmd->data->xfer_len, cmd->data->xfer_len); 2658 2659 /* From Linux: rtsx_pci_sdmmc.c sd_write_data(). */ 2660 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 0xff, 2661 RTSX_SD_CALCULATE_CRC7 | RTSX_SD_CHECK_CRC16 | 2662 RTSX_SD_NO_WAIT_BUSY_END | RTSX_SD_CHECK_CRC7 | RTSX_SD_RSP_LEN_0); 2663 2664 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 0xff, 2665 RTSX_TM_AUTO_WRITE3 | RTSX_SD_TRANSFER_START); 2666 rtsx_push_cmd(sc, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, 2667 RTSX_SD_TRANSFER_END, RTSX_SD_TRANSFER_END); 2668 2669 /* Set transfer OK function. */ 2670 sc->rtsx_intr_trans_ok = rtsx_req_done; 2671 2672 /* Run the command queue. */ 2673 rtsx_send_cmd(sc); 2674 } 2675 2676 /* 2677 * Use the data buffer for transfer > 512 bytes. 2678 */ 2679 static int 2680 rtsx_xfer(struct rtsx_softc *sc, struct mmc_command *cmd) 2681 { 2682 int read = ISSET(cmd->data->flags, MMC_DATA_READ); 2683 2684 cmd->data->xfer_len = (cmd->data->len > RTSX_MAX_DATA_BLKLEN) ? 2685 RTSX_MAX_DATA_BLKLEN : cmd->data->len; 2686 2687 if (bootverbose) 2688 device_printf(sc->rtsx_dev, "rtsx_xfer() - %s xfer: %ld bytes with block size %ld\n", 2689 read ? "Read" : "Write", 2690 (unsigned long)cmd->data->len, (unsigned long)cmd->data->xfer_len); 2691 2692 if (cmd->data->len > RTSX_DMA_DATA_BUFSIZE) { 2693 device_printf(sc->rtsx_dev, "rtsx_xfer() length too large: %ld > %d\n", 2694 (unsigned long)cmd->data->len, RTSX_DMA_DATA_BUFSIZE); 2695 cmd->error = MMC_ERR_INVALID; 2696 return (MMC_ERR_INVALID); 2697 } 2698 2699 if (!read) { 2700 /* Set transfer OK function. */ 2701 sc->rtsx_intr_trans_ok = rtsx_xfer_begin; 2702 2703 /* Run the command queue. */ 2704 rtsx_send_req(sc, cmd); 2705 } else { 2706 rtsx_xfer_start(sc); 2707 } 2708 2709 return (0); 2710 } 2711 2712 /* 2713 * Get request response and start dma data transfer (write command). 2714 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2715 */ 2716 static void 2717 rtsx_xfer_begin(struct rtsx_softc *sc) 2718 { 2719 struct mmc_command *cmd; 2720 2721 cmd = sc->rtsx_req->cmd; 2722 2723 if (bootverbose) 2724 device_printf(sc->rtsx_dev, "rtsx_xfer_begin() - CMD%d\n", cmd->opcode); 2725 2726 rtsx_set_resp(sc, cmd); 2727 rtsx_xfer_start(sc); 2728 } 2729 2730 /* 2731 * Start dma data transfer. 2732 */ 2733 static void 2734 rtsx_xfer_start(struct rtsx_softc *sc) 2735 { 2736 struct mmc_command *cmd; 2737 int read; 2738 uint8_t cfg2; 2739 int dma_dir; 2740 int tmode; 2741 2742 cmd = sc->rtsx_req->cmd; 2743 read = ISSET(cmd->data->flags, MMC_DATA_READ); 2744 2745 /* Configure DMA transfer mode parameters. */ 2746 if (cmd->opcode == MMC_READ_MULTIPLE_BLOCK) 2747 cfg2 = RTSX_SD_CHECK_CRC16 | RTSX_SD_NO_WAIT_BUSY_END | RTSX_SD_RSP_LEN_6; 2748 else 2749 cfg2 = RTSX_SD_CHECK_CRC16 | RTSX_SD_NO_WAIT_BUSY_END | RTSX_SD_RSP_LEN_0; 2750 if (read) { 2751 dma_dir = RTSX_DMA_DIR_FROM_CARD; 2752 /* 2753 * Use transfer mode AUTO_READ1, which assume we not 2754 * already send the read command and don't need to send 2755 * CMD 12 manually after read. 2756 */ 2757 tmode = RTSX_TM_AUTO_READ1; 2758 cfg2 |= RTSX_SD_CALCULATE_CRC7 | RTSX_SD_CHECK_CRC7; 2759 2760 rtsx_init_cmd(sc, cmd); 2761 } else { 2762 dma_dir = RTSX_DMA_DIR_TO_CARD; 2763 /* 2764 * Use transfer mode AUTO_WRITE3, wich assumes we've already 2765 * sent the write command and gotten the response, and will 2766 * send CMD 12 manually after writing. 2767 */ 2768 tmode = RTSX_TM_AUTO_WRITE3; 2769 cfg2 |= RTSX_SD_NO_CALCULATE_CRC7 | RTSX_SD_NO_CHECK_CRC7; 2770 2771 sc->rtsx_cmd_index = 0; 2772 } 2773 2774 /* Queue commands to configure data transfer size. */ 2775 rtsx_set_cmd_data_len(sc, cmd->data->len / cmd->data->xfer_len, cmd->data->xfer_len); 2776 2777 /* Configure DMA controller. */ 2778 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_IRQSTAT0, 2779 RTSX_DMA_DONE_INT, RTSX_DMA_DONE_INT); 2780 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMATC3, 2781 0xff, cmd->data->len >> 24); 2782 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMATC2, 2783 0xff, cmd->data->len >> 16); 2784 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMATC1, 2785 0xff, cmd->data->len >> 8); 2786 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMATC0, 2787 0xff, cmd->data->len); 2788 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMACTL, 2789 RTSX_DMA_EN | RTSX_DMA_DIR | RTSX_DMA_PACK_SIZE_MASK, 2790 RTSX_DMA_EN | dma_dir | RTSX_DMA_512); 2791 2792 /* Use the DMA ring buffer for commands which transfer data. */ 2793 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_CARD_DATA_SOURCE, 2794 0x01, RTSX_RING_BUFFER); 2795 2796 /* Queue command to set response type. */ 2797 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 0xff, cfg2); 2798 2799 /* Queue commands to perform SD transfer. */ 2800 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 2801 0xff, tmode | RTSX_SD_TRANSFER_START); 2802 rtsx_push_cmd(sc, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, 2803 RTSX_SD_TRANSFER_END, RTSX_SD_TRANSFER_END); 2804 2805 /* Run the command queue. */ 2806 rtsx_send_cmd(sc); 2807 2808 if (!read) 2809 memcpy(sc->rtsx_data_dmamem, cmd->data->data, cmd->data->len); 2810 2811 /* Sync data DMA buffer. */ 2812 bus_dmamap_sync(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamap, BUS_DMASYNC_PREREAD); 2813 bus_dmamap_sync(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamap, BUS_DMASYNC_PREWRITE); 2814 2815 /* Set transfer OK function. */ 2816 sc->rtsx_intr_trans_ok = rtsx_xfer_finish; 2817 2818 /* Tell the chip where the data buffer is and run the transfer. */ 2819 WRITE4(sc, RTSX_HDBAR, sc->rtsx_data_buffer); 2820 WRITE4(sc, RTSX_HDBCTLR, RTSX_TRIG_DMA | (read ? RTSX_DMA_READ : 0) | 2821 (cmd->data->len & 0x00ffffff)); 2822 } 2823 2824 /* 2825 * Finish dma data transfer. 2826 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2827 */ 2828 static void 2829 rtsx_xfer_finish(struct rtsx_softc *sc) 2830 { 2831 struct mmc_command *cmd; 2832 int read; 2833 2834 cmd = sc->rtsx_req->cmd; 2835 2836 if (bootverbose) 2837 device_printf(sc->rtsx_dev, "rtsx_xfer_finish() - CMD%d\n", cmd->opcode); 2838 2839 read = ISSET(cmd->data->flags, MMC_DATA_READ); 2840 2841 /* Sync data DMA buffer. */ 2842 bus_dmamap_sync(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamap, BUS_DMASYNC_POSTREAD); 2843 bus_dmamap_sync(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamap, BUS_DMASYNC_POSTWRITE); 2844 2845 if (read) { 2846 memcpy(cmd->data->data, sc->rtsx_data_dmamem, cmd->data->len); 2847 rtsx_req_done(sc); 2848 } else { 2849 /* Send CMD12 after AUTO_WRITE3 (see mmcsd_rw() in mmcsd.c) */ 2850 /* and complete request. */ 2851 sc->rtsx_intr_trans_ok = NULL; 2852 rtsx_send_req(sc, sc->rtsx_req->stop); 2853 } 2854 } 2855 2856 /* 2857 * Manage request timeout. 2858 */ 2859 static void 2860 rtsx_timeout(void *arg) 2861 { 2862 struct rtsx_softc *sc; 2863 2864 sc = (struct rtsx_softc *)arg; 2865 if (sc->rtsx_req != NULL) { 2866 device_printf(sc->rtsx_dev, "Controller timeout for CMD%u\n", 2867 sc->rtsx_req->cmd->opcode); 2868 sc->rtsx_req->cmd->error = MMC_ERR_TIMEOUT; 2869 rtsx_stop_cmd(sc); 2870 rtsx_req_done(sc); 2871 } else { 2872 device_printf(sc->rtsx_dev, "Controller timeout!\n"); 2873 } 2874 } 2875 2876 #ifdef MMCCAM 2877 static void 2878 rtsx_cam_action(struct cam_sim *sim, union ccb *ccb) 2879 { 2880 struct rtsx_softc *sc; 2881 2882 sc = cam_sim_softc(sim); 2883 if (sc == NULL) { 2884 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2885 xpt_done(ccb); 2886 return; 2887 } 2888 switch (ccb->ccb_h.func_code) { 2889 case XPT_PATH_INQ: 2890 { 2891 struct ccb_pathinq *cpi = &ccb->cpi; 2892 2893 cpi->version_num = 1; /* SIM driver version number - now all drivers use 1 */ 2894 cpi->hba_inquiry = 0; /* bitmask of features supported by the controller */ 2895 cpi->target_sprt = 0; /* flags for target mode support */ 2896 cpi->hba_misc = PIM_NOBUSRESET | PIM_SEQSCAN; 2897 cpi->hba_eng_cnt = 0; /* HBA engine count - always set to 0 */ 2898 cpi->max_target = 0; /* maximal supported target ID */ 2899 cpi->max_lun = 0; /* maximal supported LUN ID */ 2900 cpi->initiator_id = 1; /* the SCSI ID of the controller itself */ 2901 cpi->maxio = RTSX_DMA_DATA_BUFSIZE; /* maximum io size */ 2902 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); /* vendor ID of the SIM */ 2903 strncpy(cpi->hba_vid, "Realtek", HBA_IDLEN); /* vendor ID of the HBA */ 2904 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); /* device name for SIM */ 2905 cpi->unit_number = cam_sim_unit(sim); /* controller unit number */ 2906 cpi->bus_id = cam_sim_bus(sim); /* bus number */ 2907 cpi->protocol = PROTO_MMCSD; 2908 cpi->protocol_version = SCSI_REV_0; 2909 cpi->transport = XPORT_MMCSD; 2910 cpi->transport_version = 1; 2911 2912 cpi->ccb_h.status = CAM_REQ_CMP; 2913 break; 2914 } 2915 case XPT_MMC_GET_TRAN_SETTINGS: 2916 case XPT_GET_TRAN_SETTINGS: 2917 { 2918 struct ccb_trans_settings *cts = &ccb->cts; 2919 2920 if (bootverbose || sc->rtsx_debug) 2921 device_printf(sc->rtsx_dev, "rtsx_cam_action() - got XPT_GET_TRAN_SETTINGS\n"); 2922 2923 cts->protocol = PROTO_MMCSD; 2924 cts->protocol_version = 1; 2925 cts->transport = XPORT_MMCSD; 2926 cts->transport_version = 1; 2927 cts->xport_specific.valid = 0; 2928 cts->proto_specific.mmc.host_ocr = sc->rtsx_host.host_ocr; 2929 cts->proto_specific.mmc.host_f_min = sc->rtsx_host.f_min; 2930 cts->proto_specific.mmc.host_f_max = sc->rtsx_host.f_max; 2931 cts->proto_specific.mmc.host_caps = sc->rtsx_host.caps; 2932 #if __FreeBSD__ > 12 2933 cts->proto_specific.mmc.host_max_data = RTSX_DMA_DATA_BUFSIZE / MMC_SECTOR_SIZE; 2934 #endif 2935 memcpy(&cts->proto_specific.mmc.ios, &sc->rtsx_host.ios, sizeof(struct mmc_ios)); 2936 2937 ccb->ccb_h.status = CAM_REQ_CMP; 2938 break; 2939 } 2940 case XPT_MMC_SET_TRAN_SETTINGS: 2941 case XPT_SET_TRAN_SETTINGS: 2942 if (bootverbose || sc->rtsx_debug) 2943 device_printf(sc->rtsx_dev, "rtsx_cam_action() - got XPT_SET_TRAN_SETTINGS\n"); 2944 2945 /* Apply settings and set ccb->ccb_h.status accordingly. */ 2946 rtsx_cam_set_tran_settings(sc, ccb); 2947 break; 2948 case XPT_RESET_BUS: 2949 if (bootverbose || sc->rtsx_debug) 2950 device_printf(sc->rtsx_dev, "got XPT_RESET_BUS, ACK it...\n"); 2951 2952 ccb->ccb_h.status = CAM_REQ_CMP; 2953 break; 2954 case XPT_MMC_IO: 2955 /* 2956 * Here is the HW-dependent part of sending 2957 * the command to the underlying h/w. 2958 * At some point in the future an interrupt comes 2959 * and the request will be marked as completed. 2960 */ 2961 ccb->ccb_h.status = CAM_REQ_INPROG; 2962 2963 rtsx_cam_request(sc, ccb); 2964 return; 2965 default: 2966 ccb->ccb_h.status = CAM_REQ_INVALID; 2967 break; 2968 } 2969 xpt_done(ccb); 2970 return; 2971 } 2972 2973 static void 2974 rtsx_cam_poll(struct cam_sim *sim) 2975 { 2976 return; 2977 } 2978 2979 /* 2980 * Apply settings and set ccb->ccb_h.status accordingly. 2981 */ 2982 static void 2983 rtsx_cam_set_tran_settings(struct rtsx_softc *sc, union ccb *ccb) 2984 { 2985 struct mmc_ios *ios; 2986 struct mmc_ios *new_ios; 2987 struct ccb_trans_settings_mmc *cts; 2988 2989 ios = &sc->rtsx_host.ios; 2990 cts = &ccb->cts.proto_specific.mmc; 2991 new_ios = &cts->ios; 2992 2993 /* Update only requested fields */ 2994 if (cts->ios_valid & MMC_CLK) { 2995 ios->clock = new_ios->clock; 2996 sc->rtsx_ios_clock = -1; /* To be updated by rtsx_mmcbr_update_ios(). */ 2997 if (bootverbose || sc->rtsx_debug) 2998 device_printf(sc->rtsx_dev, "rtsx_cam_set_tran_settings() - clock: %u\n", ios->clock); 2999 } 3000 if (cts->ios_valid & MMC_VDD) { 3001 ios->vdd = new_ios->vdd; 3002 if (bootverbose || sc->rtsx_debug) 3003 device_printf(sc->rtsx_dev, "rtsx_cam_set_tran_settings() - vdd: %d\n", ios->vdd); 3004 } 3005 if (cts->ios_valid & MMC_CS) { 3006 ios->chip_select = new_ios->chip_select; 3007 if (bootverbose || sc->rtsx_debug) 3008 device_printf(sc->rtsx_dev, "rtsx_cam_set_tran_settings() - chip_select: %d\n", ios->chip_select); 3009 } 3010 if (cts->ios_valid & MMC_BW) { 3011 ios->bus_width = new_ios->bus_width; 3012 sc->rtsx_ios_bus_width = -1; /* To be updated by rtsx_mmcbr_update_ios(). */ 3013 if (bootverbose || sc->rtsx_debug) 3014 device_printf(sc->rtsx_dev, "rtsx_cam_set_tran_settings() - bus width: %d\n", ios->bus_width); 3015 } 3016 if (cts->ios_valid & MMC_PM) { 3017 ios->power_mode = new_ios->power_mode; 3018 sc->rtsx_ios_power_mode = -1; /* To be updated by rtsx_mmcbr_update_ios(). */ 3019 if (bootverbose || sc->rtsx_debug) 3020 device_printf(sc->rtsx_dev, "rtsx_cam_set_tran_settings() - power mode: %d\n", ios->power_mode); 3021 } 3022 if (cts->ios_valid & MMC_BT) { 3023 ios->timing = new_ios->timing; 3024 sc->rtsx_ios_timing = -1; /* To be updated by rtsx_mmcbr_update_ios(). */ 3025 if (bootverbose || sc->rtsx_debug) 3026 device_printf(sc->rtsx_dev, "rtsx_cam_set_tran_settings() - timing: %d\n", ios->timing); 3027 } 3028 if (cts->ios_valid & MMC_BM) { 3029 ios->bus_mode = new_ios->bus_mode; 3030 if (bootverbose || sc->rtsx_debug) 3031 device_printf(sc->rtsx_dev, "rtsx_cam_set_tran_settings() - bus mode: %d\n", ios->bus_mode); 3032 } 3033 #if __FreeBSD__ > 12 3034 if (cts->ios_valid & MMC_VCCQ) { 3035 ios->vccq = new_ios->vccq; 3036 sc->rtsx_ios_vccq = -1; /* To be updated by rtsx_mmcbr_update_ios(). */ 3037 if (bootverbose || sc->rtsx_debug) 3038 device_printf(sc->rtsx_dev, "rtsx_cam_set_tran_settings() - vccq: %d\n", ios->vccq); 3039 } 3040 #endif /* __FreeBSD__ > 12 */ 3041 if (rtsx_mmcbr_update_ios(sc->rtsx_dev, NULL) == 0) 3042 ccb->ccb_h.status = CAM_REQ_CMP; 3043 else 3044 ccb->ccb_h.status = CAM_REQ_CMP_ERR; 3045 3046 return; 3047 } 3048 3049 /* 3050 * Build a request and run it. 3051 */ 3052 static void 3053 rtsx_cam_request(struct rtsx_softc *sc, union ccb *ccb) 3054 { 3055 RTSX_LOCK(sc); 3056 if (sc->rtsx_ccb != NULL) { 3057 RTSX_UNLOCK(sc); 3058 ccb->ccb_h.status = CAM_BUSY; /* i.e. CAM_REQ_CMP | CAM_REQ_CMP_ERR */ 3059 return; 3060 } 3061 sc->rtsx_ccb = ccb; 3062 sc->rtsx_cam_req.cmd = &ccb->mmcio.cmd; 3063 sc->rtsx_cam_req.stop = &ccb->mmcio.stop; 3064 RTSX_UNLOCK(sc); 3065 3066 rtsx_mmcbr_request(sc->rtsx_dev, NULL, &sc->rtsx_cam_req); 3067 return; 3068 } 3069 #endif /* MMCCAM */ 3070 3071 static int 3072 rtsx_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) 3073 { 3074 struct rtsx_softc *sc; 3075 3076 sc = device_get_softc(bus); 3077 switch (which) { 3078 case MMCBR_IVAR_BUS_MODE: /* ivar 0 - 1 = opendrain, 2 = pushpull */ 3079 *result = sc->rtsx_host.ios.bus_mode; 3080 break; 3081 case MMCBR_IVAR_BUS_WIDTH: /* ivar 1 - 0 = 1b 2 = 4b, 3 = 8b */ 3082 *result = sc->rtsx_host.ios.bus_width; 3083 break; 3084 case MMCBR_IVAR_CHIP_SELECT: /* ivar 2 - O = dontcare, 1 = cs_high, 2 = cs_low */ 3085 *result = sc->rtsx_host.ios.chip_select; 3086 break; 3087 case MMCBR_IVAR_CLOCK: /* ivar 3 - clock in Hz */ 3088 *result = sc->rtsx_host.ios.clock; 3089 break; 3090 case MMCBR_IVAR_F_MIN: /* ivar 4 */ 3091 *result = sc->rtsx_host.f_min; 3092 break; 3093 case MMCBR_IVAR_F_MAX: /* ivar 5 */ 3094 *result = sc->rtsx_host.f_max; 3095 break; 3096 case MMCBR_IVAR_HOST_OCR: /* ivar 6 - host operation conditions register */ 3097 *result = sc->rtsx_host.host_ocr; 3098 break; 3099 case MMCBR_IVAR_MODE: /* ivar 7 - 0 = mode_mmc, 1 = mode_sd */ 3100 *result = sc->rtsx_host.mode; 3101 break; 3102 case MMCBR_IVAR_OCR: /* ivar 8 - operation conditions register */ 3103 *result = sc->rtsx_host.ocr; 3104 break; 3105 case MMCBR_IVAR_POWER_MODE: /* ivar 9 - 0 = off, 1 = up, 2 = on */ 3106 *result = sc->rtsx_host.ios.power_mode; 3107 break; 3108 case MMCBR_IVAR_VDD: /* ivar 11 - voltage power pin */ 3109 *result = sc->rtsx_host.ios.vdd; 3110 break; 3111 case MMCBR_IVAR_VCCQ: /* ivar 12 - signaling: 0 = 1.20V, 1 = 1.80V, 2 = 3.30V */ 3112 *result = sc->rtsx_host.ios.vccq; 3113 break; 3114 case MMCBR_IVAR_CAPS: /* ivar 13 */ 3115 *result = sc->rtsx_host.caps; 3116 break; 3117 case MMCBR_IVAR_TIMING: /* ivar 14 - 0 = normal, 1 = timing_hs, ... */ 3118 *result = sc->rtsx_host.ios.timing; 3119 break; 3120 case MMCBR_IVAR_MAX_DATA: /* ivar 15 */ 3121 *result = RTSX_DMA_DATA_BUFSIZE / MMC_SECTOR_SIZE; 3122 break; 3123 case MMCBR_IVAR_RETUNE_REQ: /* ivar 10 */ 3124 case MMCBR_IVAR_MAX_BUSY_TIMEOUT: /* ivar 16 */ 3125 default: 3126 return (EINVAL); 3127 } 3128 3129 if (bootverbose) 3130 device_printf(bus, "Read ivar #%d, value %#x / #%d\n", 3131 which, *(int *)result, *(int *)result); 3132 3133 return (0); 3134 } 3135 3136 static int 3137 rtsx_write_ivar(device_t bus, device_t child, int which, uintptr_t value) 3138 { 3139 struct rtsx_softc *sc; 3140 3141 if (bootverbose) 3142 device_printf(bus, "Write ivar #%d, value %#x / #%d\n", 3143 which, (int)value, (int)value); 3144 3145 sc = device_get_softc(bus); 3146 switch (which) { 3147 case MMCBR_IVAR_BUS_MODE: /* ivar 0 - 1 = opendrain, 2 = pushpull */ 3148 sc->rtsx_host.ios.bus_mode = value; 3149 break; 3150 case MMCBR_IVAR_BUS_WIDTH: /* ivar 1 - 0 = 1b 2 = 4b, 3 = 8b */ 3151 sc->rtsx_host.ios.bus_width = value; 3152 sc->rtsx_ios_bus_width = -1; /* To be updated on next rtsx_mmcbr_update_ios(). */ 3153 break; 3154 case MMCBR_IVAR_CHIP_SELECT: /* ivar 2 - O = dontcare, 1 = cs_high, 2 = cs_low */ 3155 sc->rtsx_host.ios.chip_select = value; 3156 break; 3157 case MMCBR_IVAR_CLOCK: /* ivar 3 - clock in Hz */ 3158 sc->rtsx_host.ios.clock = value; 3159 sc->rtsx_ios_clock = -1; /* To be updated on next rtsx_mmcbr_update_ios(). */ 3160 break; 3161 case MMCBR_IVAR_MODE: /* ivar 7 - 0 = mode_mmc, 1 = mode_sd */ 3162 sc->rtsx_host.mode = value; 3163 break; 3164 case MMCBR_IVAR_OCR: /* ivar 8 - operation conditions register */ 3165 sc->rtsx_host.ocr = value; 3166 break; 3167 case MMCBR_IVAR_POWER_MODE: /* ivar 9 - 0 = off, 1 = up, 2 = on */ 3168 sc->rtsx_host.ios.power_mode = value; 3169 sc->rtsx_ios_power_mode = -1; /* To be updated on next rtsx_mmcbr_update_ios(). */ 3170 break; 3171 case MMCBR_IVAR_VDD: /* ivar 11 - voltage power pin */ 3172 sc->rtsx_host.ios.vdd = value; 3173 break; 3174 case MMCBR_IVAR_VCCQ: /* ivar 12 - signaling: 0 = 1.20V, 1 = 1.80V, 2 = 3.30V */ 3175 sc->rtsx_host.ios.vccq = value; 3176 sc->rtsx_ios_vccq = value; /* rtsx_mmcbr_switch_vccq() will be called by mmc.c (MMCCAM undef). */ 3177 break; 3178 case MMCBR_IVAR_TIMING: /* ivar 14 - 0 = normal, 1 = timing_hs, ... */ 3179 sc->rtsx_host.ios.timing = value; 3180 sc->rtsx_ios_timing = -1; /* To be updated on next rtsx_mmcbr_update_ios(). */ 3181 break; 3182 /* These are read-only. */ 3183 case MMCBR_IVAR_F_MIN: /* ivar 4 */ 3184 case MMCBR_IVAR_F_MAX: /* ivar 5 */ 3185 case MMCBR_IVAR_HOST_OCR: /* ivar 6 - host operation conditions register */ 3186 case MMCBR_IVAR_RETUNE_REQ: /* ivar 10 */ 3187 case MMCBR_IVAR_CAPS: /* ivar 13 */ 3188 case MMCBR_IVAR_MAX_DATA: /* ivar 15 */ 3189 case MMCBR_IVAR_MAX_BUSY_TIMEOUT: /* ivar 16 */ 3190 default: 3191 return (EINVAL); 3192 } 3193 3194 return (0); 3195 } 3196 3197 static int 3198 rtsx_mmcbr_update_ios(device_t bus, device_t child__unused) 3199 { 3200 struct rtsx_softc *sc; 3201 struct mmc_ios *ios; 3202 int error; 3203 3204 sc = device_get_softc(bus); 3205 ios = &sc->rtsx_host.ios; 3206 3207 if (bootverbose) 3208 device_printf(bus, "rtsx_mmcbr_update_ios()\n"); 3209 3210 /* if MMCBR_IVAR_BUS_WIDTH updated. */ 3211 if (sc->rtsx_ios_bus_width < 0) { 3212 sc->rtsx_ios_bus_width = ios->bus_width; 3213 if ((error = rtsx_set_bus_width(sc, ios->bus_width))) 3214 return (error); 3215 } 3216 3217 /* if MMCBR_IVAR_POWER_MODE updated. */ 3218 if (sc->rtsx_ios_power_mode < 0) { 3219 sc->rtsx_ios_power_mode = ios->power_mode; 3220 switch (ios->power_mode) { 3221 case power_off: 3222 if ((error = rtsx_bus_power_off(sc))) 3223 return (error); 3224 break; 3225 case power_up: 3226 if ((error = rtsx_bus_power_on(sc))) 3227 return (error); 3228 break; 3229 case power_on: 3230 if ((error = rtsx_bus_power_on(sc))) 3231 return (error); 3232 break; 3233 } 3234 } 3235 3236 sc->rtsx_double_clk = true; 3237 sc->rtsx_vpclk = false; 3238 3239 /* if MMCBR_IVAR_TIMING updated. */ 3240 if (sc->rtsx_ios_timing < 0) { 3241 sc->rtsx_ios_timing = ios->timing; 3242 if ((error = rtsx_set_sd_timing(sc, ios->timing))) 3243 return (error); 3244 } 3245 3246 /* if MMCBR_IVAR_CLOCK updated, must be after rtsx_set_sd_timing() */ 3247 if (sc->rtsx_ios_clock < 0) { 3248 sc->rtsx_ios_clock = ios->clock; 3249 if ((error = rtsx_set_sd_clock(sc, ios->clock))) 3250 return (error); 3251 } 3252 3253 /* if MMCCAM and vccq updated */ 3254 if (sc->rtsx_ios_vccq < 0) { 3255 sc->rtsx_ios_vccq = ios->vccq; 3256 if ((error = rtsx_mmcbr_switch_vccq(sc->rtsx_dev, NULL))) 3257 return (error); 3258 } 3259 3260 return (0); 3261 } 3262 3263 /* 3264 * Set output stage logic power voltage. 3265 */ 3266 static int 3267 rtsx_mmcbr_switch_vccq(device_t bus, device_t child __unused) 3268 { 3269 struct rtsx_softc *sc; 3270 int vccq = 0; 3271 int error; 3272 3273 sc = device_get_softc(bus); 3274 3275 switch (sc->rtsx_host.ios.vccq) { 3276 case vccq_120: 3277 vccq = 120; 3278 break; 3279 case vccq_180: 3280 vccq = 180; 3281 break; 3282 case vccq_330: 3283 vccq = 330; 3284 break; 3285 }; 3286 /* It seems it is always vccq_330. */ 3287 if (vccq == 330) { 3288 switch (sc->rtsx_device_id) { 3289 uint16_t val; 3290 case RTSX_RTS5227: 3291 if ((error = rtsx_write_phy(sc, 0x08, 0x4FE4))) 3292 return (error); 3293 if ((error = rtsx_rts5227_fill_driving(sc))) 3294 return (error); 3295 break; 3296 case RTSX_RTS5209: 3297 case RTSX_RTS5229: 3298 RTSX_BITOP(sc, RTSX_SD30_CMD_DRIVE_SEL, RTSX_SD30_DRIVE_SEL_MASK, sc->rtsx_sd30_drive_sel_3v3); 3299 if ((error = rtsx_write_phy(sc, 0x08, 0x4FE4))) 3300 return (error); 3301 break; 3302 case RTSX_RTS522A: 3303 if ((error = rtsx_write_phy(sc, 0x08, 0x57E4))) 3304 return (error); 3305 if ((error = rtsx_rts5227_fill_driving(sc))) 3306 return (error); 3307 break; 3308 case RTSX_RTS525A: 3309 RTSX_BITOP(sc, RTSX_LDO_CONFIG2, RTSX_LDO_D3318_MASK, RTSX_LDO_D3318_33V); 3310 RTSX_BITOP(sc, RTSX_SD_PAD_CTL, RTSX_SD_IO_USING_1V8, 0); 3311 if ((error = rtsx_rts5249_fill_driving(sc))) 3312 return (error); 3313 break; 3314 case RTSX_RTS5249: 3315 if ((error = rtsx_read_phy(sc, RTSX_PHY_TUNE, &val))) 3316 return (error); 3317 if ((error = rtsx_write_phy(sc, RTSX_PHY_TUNE, 3318 (val & RTSX_PHY_TUNE_VOLTAGE_MASK) | RTSX_PHY_TUNE_VOLTAGE_3V3))) 3319 return (error); 3320 if ((error = rtsx_rts5249_fill_driving(sc))) 3321 return (error); 3322 break; 3323 case RTSX_RTL8402: 3324 RTSX_BITOP(sc, RTSX_SD30_CMD_DRIVE_SEL, RTSX_SD30_DRIVE_SEL_MASK, sc->rtsx_sd30_drive_sel_3v3); 3325 RTSX_BITOP(sc, RTSX_LDO_CTL, 3326 (RTSX_BPP_ASIC_MASK << RTSX_BPP_SHIFT_8402) | RTSX_BPP_PAD_MASK, 3327 (RTSX_BPP_ASIC_3V3 << RTSX_BPP_SHIFT_8402) | RTSX_BPP_PAD_3V3); 3328 break; 3329 case RTSX_RTL8411: 3330 case RTSX_RTL8411B: 3331 RTSX_BITOP(sc, RTSX_SD30_CMD_DRIVE_SEL, RTSX_SD30_DRIVE_SEL_MASK, sc->rtsx_sd30_drive_sel_3v3); 3332 RTSX_BITOP(sc, RTSX_LDO_CTL, 3333 (RTSX_BPP_ASIC_MASK << RTSX_BPP_SHIFT_8411) | RTSX_BPP_PAD_MASK, 3334 (RTSX_BPP_ASIC_3V3 << RTSX_BPP_SHIFT_8411) | RTSX_BPP_PAD_3V3); 3335 break; 3336 } 3337 DELAY(300); 3338 } 3339 3340 if (bootverbose || sc->rtsx_debug) 3341 device_printf(sc->rtsx_dev, "rtsx_mmcbr_switch_vccq(%d)\n", vccq); 3342 3343 return (0); 3344 } 3345 3346 /* 3347 * Tune card if bus_timing_uhs_sdr50. 3348 */ 3349 static int 3350 rtsx_mmcbr_tune(device_t bus, device_t child __unused, bool hs400) 3351 { 3352 struct rtsx_softc *sc; 3353 uint32_t raw_phase_map[RTSX_RX_TUNING_CNT] = {0}; 3354 uint32_t phase_map; 3355 uint8_t final_phase; 3356 int i; 3357 3358 sc = device_get_softc(bus); 3359 3360 if (bootverbose || sc->rtsx_debug) 3361 device_printf(sc->rtsx_dev, "rtsx_mmcbr_tune() - hs400 is %s\n", 3362 (hs400) ? "true" : "false"); 3363 3364 if (sc->rtsx_ios_timing != bus_timing_uhs_sdr50) 3365 return (0); 3366 3367 sc->rtsx_tuning_mode = true; 3368 3369 switch (sc->rtsx_device_id) { 3370 case RTSX_RTS5209: 3371 case RTSX_RTS5227: 3372 rtsx_sd_change_tx_phase(sc, 27); 3373 break; 3374 case RTSX_RTS522A: 3375 rtsx_sd_change_tx_phase(sc, 20); 3376 break; 3377 case RTSX_RTS5229: 3378 rtsx_sd_change_tx_phase(sc, 27); 3379 break; 3380 case RTSX_RTS525A: 3381 case RTSX_RTS5249: 3382 rtsx_sd_change_tx_phase(sc, 29); 3383 break; 3384 case RTSX_RTL8402: 3385 case RTSX_RTL8411: 3386 case RTSX_RTL8411B: 3387 rtsx_sd_change_tx_phase(sc, 7); 3388 break; 3389 } 3390 3391 /* trying rx tuning for bus_timing_uhs_sdr50. */ 3392 for (i = 0; i < RTSX_RX_TUNING_CNT; i++) { 3393 rtsx_sd_tuning_rx_phase(sc, &(raw_phase_map[i])); 3394 if (raw_phase_map[i] == 0) 3395 break; 3396 } 3397 3398 phase_map = 0xffffffff; 3399 for (i = 0; i < RTSX_RX_TUNING_CNT; i++) { 3400 if (bootverbose || sc->rtsx_debug) 3401 device_printf(sc->rtsx_dev, "rtsx_mmcbr_tune() - RX raw_phase_map[%d]: 0x%08x\n", 3402 i, raw_phase_map[i]); 3403 phase_map &= raw_phase_map[i]; 3404 } 3405 if (bootverbose || sc->rtsx_debug) 3406 device_printf(sc->rtsx_dev, "rtsx_mmcbr_tune() - RX phase_map: 0x%08x\n", phase_map); 3407 3408 if (phase_map) { 3409 final_phase = rtsx_sd_search_final_rx_phase(sc, phase_map); 3410 if (final_phase != 0xff) { 3411 if (sc->rtsx_debug == 1) { 3412 sc->rtsx_debug = 2; 3413 rtsx_sd_change_rx_phase(sc, final_phase); 3414 sc->rtsx_debug = 1; 3415 } else { 3416 rtsx_sd_change_rx_phase(sc, final_phase); 3417 } 3418 } 3419 } 3420 3421 sc->rtsx_tuning_mode = false; 3422 3423 return (0); 3424 } 3425 3426 static int 3427 rtsx_mmcbr_retune(device_t bus, device_t child __unused, bool reset __unused) 3428 { 3429 struct rtsx_softc *sc; 3430 3431 sc = device_get_softc(bus); 3432 3433 if (bootverbose) 3434 device_printf(sc->rtsx_dev, "rtsx_mmcbr_retune()\n"); 3435 3436 return (0); 3437 } 3438 3439 static int 3440 rtsx_mmcbr_request(device_t bus, device_t child __unused, struct mmc_request *req) 3441 { 3442 struct rtsx_softc *sc; 3443 struct mmc_command *cmd; 3444 int timeout; 3445 int error; 3446 3447 sc = device_get_softc(bus); 3448 3449 RTSX_LOCK(sc); 3450 if (sc->rtsx_req != NULL) { 3451 RTSX_UNLOCK(sc); 3452 return (EBUSY); 3453 } 3454 sc->rtsx_req = req; 3455 cmd = req->cmd; 3456 cmd->error = error = MMC_ERR_NONE; 3457 sc->rtsx_intr_status = 0; 3458 sc->rtsx_intr_trans_ok = NULL; 3459 sc->rtsx_intr_trans_ko = rtsx_req_done; 3460 3461 if (bootverbose) 3462 device_printf(sc->rtsx_dev, "rtsx_mmcbr_request(CMD%u arg %#x, flags %#x, dlen %u, dflags %#x)\n", 3463 cmd->opcode, cmd->arg, cmd->flags, 3464 cmd->data != NULL ? (unsigned int)cmd->data->len : 0, 3465 cmd->data != NULL ? cmd->data->flags : 0); 3466 3467 /* Check if card present. */ 3468 if (!ISSET(sc->rtsx_flags, RTSX_F_CARD_PRESENT)) { 3469 cmd->error = error = MMC_ERR_FAILED; 3470 goto end; 3471 } 3472 3473 /* Refuse SDIO probe if the chip doesn't support SDIO. */ 3474 if (cmd->opcode == IO_SEND_OP_COND && 3475 !ISSET(sc->rtsx_flags, RTSX_F_SDIO_SUPPORT)) { 3476 cmd->error = error = MMC_ERR_INVALID; 3477 goto end; 3478 } 3479 3480 /* Return MMC_ERR_TIMEOUT for SD_IO_RW_DIRECT and IO_SEND_OP_COND. */ 3481 if (cmd->opcode == SD_IO_RW_DIRECT || cmd->opcode == IO_SEND_OP_COND) { 3482 cmd->error = error = MMC_ERR_TIMEOUT; 3483 goto end; 3484 } 3485 3486 /* Select SD card. */ 3487 RTSX_BITOP(sc, RTSX_CARD_SELECT, 0x07, RTSX_SD_MOD_SEL); 3488 RTSX_BITOP(sc, RTSX_CARD_SHARE_MODE, RTSX_CARD_SHARE_MASK, RTSX_CARD_SHARE_48_SD); 3489 3490 if (cmd->data == NULL) { 3491 DELAY(200); 3492 timeout = sc->rtsx_timeout_cmd; 3493 error = rtsx_send_req(sc, cmd); 3494 } else if (cmd->data->len <= 512) { 3495 timeout = sc->rtsx_timeout_io; 3496 error = rtsx_xfer_short(sc, cmd); 3497 } else { 3498 timeout = sc->rtsx_timeout_io; 3499 error = rtsx_xfer(sc, cmd); 3500 } 3501 end: 3502 if (error == MMC_ERR_NONE) { 3503 callout_reset(&sc->rtsx_timeout_callout, timeout * hz, rtsx_timeout, sc); 3504 } else { 3505 rtsx_req_done(sc); 3506 } 3507 RTSX_UNLOCK(sc); 3508 3509 return (error); 3510 } 3511 3512 static int 3513 rtsx_mmcbr_get_ro(device_t bus, device_t child __unused) 3514 { 3515 struct rtsx_softc *sc; 3516 3517 sc = device_get_softc(bus); 3518 3519 if (sc->rtsx_inversion == 0) 3520 return (sc->rtsx_read_only); 3521 else 3522 return !(sc->rtsx_read_only); 3523 } 3524 3525 static int 3526 rtsx_mmcbr_acquire_host(device_t bus, device_t child __unused) 3527 { 3528 struct rtsx_softc *sc; 3529 3530 if (bootverbose) 3531 device_printf(bus, "rtsx_mmcbr_acquire_host()\n"); 3532 3533 sc = device_get_softc(bus); 3534 RTSX_LOCK(sc); 3535 while (sc->rtsx_bus_busy) 3536 msleep(&sc->rtsx_bus_busy, &sc->rtsx_mtx, 0, "rtsxah", 0); 3537 sc->rtsx_bus_busy++; 3538 RTSX_UNLOCK(sc); 3539 3540 return (0); 3541 } 3542 3543 static int 3544 rtsx_mmcbr_release_host(device_t bus, device_t child __unused) 3545 { 3546 struct rtsx_softc *sc; 3547 3548 if (bootverbose) 3549 device_printf(bus, "rtsx_mmcbr_release_host()\n"); 3550 3551 sc = device_get_softc(bus); 3552 RTSX_LOCK(sc); 3553 sc->rtsx_bus_busy--; 3554 wakeup(&sc->rtsx_bus_busy); 3555 RTSX_UNLOCK(sc); 3556 3557 return (0); 3558 } 3559 3560 /* 3561 * 3562 * PCI Support Functions 3563 * 3564 */ 3565 3566 /* 3567 * Compare the device ID (chip) of this device against the IDs that this driver 3568 * supports. If there is a match, set the description and return success. 3569 */ 3570 static int 3571 rtsx_probe(device_t dev) 3572 { 3573 struct rtsx_softc *sc; 3574 uint16_t vendor_id; 3575 uint16_t device_id; 3576 int i; 3577 int result; 3578 3579 vendor_id = pci_get_vendor(dev); 3580 device_id = pci_get_device(dev); 3581 3582 result = ENXIO; 3583 for (i = 0; rtsx_devices[i].vendor_id != 0; i++) { 3584 if (rtsx_devices[i].vendor_id == vendor_id && 3585 rtsx_devices[i].device_id == device_id) { 3586 device_set_desc(dev, rtsx_devices[i].desc); 3587 sc = device_get_softc(dev); 3588 sc->rtsx_device_id = device_id; 3589 result = BUS_PROBE_DEFAULT; 3590 break; 3591 } 3592 } 3593 3594 return (result); 3595 } 3596 3597 /* 3598 * Attach function is only called if the probe is successful. 3599 */ 3600 static int 3601 rtsx_attach(device_t dev) 3602 { 3603 struct rtsx_softc *sc = device_get_softc(dev); 3604 struct sysctl_ctx_list *ctx; 3605 struct sysctl_oid_list *tree; 3606 int msi_count = 1; 3607 uint32_t sdio_cfg; 3608 int error; 3609 char *maker; 3610 char *family; 3611 char *product; 3612 int i; 3613 3614 if (bootverbose) 3615 device_printf(dev, "Attach - Vendor ID: 0x%x - Device ID: 0x%x\n", 3616 pci_get_vendor(dev), pci_get_device(dev)); 3617 3618 sc->rtsx_dev = dev; 3619 sc->rtsx_req = NULL; 3620 sc->rtsx_timeout_cmd = 1; 3621 sc->rtsx_timeout_io = 10; 3622 sc->rtsx_read_only = 0; 3623 sc->rtsx_inversion = 0; 3624 sc->rtsx_force_timing = 0; 3625 sc->rtsx_debug = 0; 3626 sc->rtsx_read_count = 0; 3627 sc->rtsx_write_count = 0; 3628 3629 maker = kern_getenv("smbios.system.maker"); 3630 family = kern_getenv("smbios.system.family"); 3631 product = kern_getenv("smbios.system.product"); 3632 for (i = 0; rtsx_inversion_models[i].maker != NULL; i++) { 3633 if (strcmp(rtsx_inversion_models[i].maker, maker) == 0 && 3634 strcmp(rtsx_inversion_models[i].family, family) == 0 && 3635 strcmp(rtsx_inversion_models[i].product, product) == 0) { 3636 device_printf(dev, "Inversion activated for %s/%s/%s, see BUG in rtsx(4)\n", maker, family, product); 3637 device_printf(dev, "If a card is detected without an SD card present," 3638 " add dev.rtsx.0.inversion=0 in loader.conf(5)\n"); 3639 sc->rtsx_inversion = 1; 3640 } 3641 } 3642 3643 RTSX_LOCK_INIT(sc); 3644 3645 ctx = device_get_sysctl_ctx(dev); 3646 tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 3647 SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "timeout_io", CTLFLAG_RW, 3648 &sc->rtsx_timeout_io, 0, "Request timeout for I/O commands in seconds"); 3649 SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "timeout_cmd", CTLFLAG_RW, 3650 &sc->rtsx_timeout_cmd, 0, "Request timeout for setup commands in seconds"); 3651 SYSCTL_ADD_U8(ctx, tree, OID_AUTO, "read_only", CTLFLAG_RD, 3652 &sc->rtsx_read_only, 0, "Card is write protected"); 3653 SYSCTL_ADD_U8(ctx, tree, OID_AUTO, "inversion", CTLFLAG_RWTUN, 3654 &sc->rtsx_inversion, 0, "Inversion of card detection and read only status"); 3655 SYSCTL_ADD_U8(ctx, tree, OID_AUTO, "force_timing", CTLFLAG_RW, 3656 &sc->rtsx_force_timing, 0, "Force bus_timing_uhs_sdr50"); 3657 SYSCTL_ADD_U8(ctx, tree, OID_AUTO, "debug", CTLFLAG_RWTUN, 3658 &sc->rtsx_debug, 0, "Debugging flag"); 3659 SYSCTL_ADD_U64(ctx, tree, OID_AUTO, "read_count", CTLFLAG_RD, 3660 &sc->rtsx_read_count, 0, "Count of read operations"); 3661 SYSCTL_ADD_U64(ctx, tree, OID_AUTO, "write_count", CTLFLAG_RD, 3662 &sc->rtsx_write_count, 0, "Count of write operations"); 3663 3664 if (bootverbose || sc->rtsx_debug) 3665 device_printf(dev, "We are running with inversion: %d\n", sc->rtsx_inversion); 3666 3667 /* Allocate IRQ. */ 3668 sc->rtsx_irq_res_id = 0; 3669 if (pci_alloc_msi(dev, &msi_count) == 0) 3670 sc->rtsx_irq_res_id = 1; 3671 sc->rtsx_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->rtsx_irq_res_id, 3672 RF_ACTIVE | (sc->rtsx_irq_res_id != 0 ? 0 : RF_SHAREABLE)); 3673 if (sc->rtsx_irq_res == NULL) { 3674 device_printf(dev, "Can't allocate IRQ resources for %d\n", sc->rtsx_irq_res_id); 3675 pci_release_msi(dev); 3676 return (ENXIO); 3677 } 3678 3679 callout_init_mtx(&sc->rtsx_timeout_callout, &sc->rtsx_mtx, 0); 3680 3681 /* Allocate memory resource. */ 3682 if (sc->rtsx_device_id == RTSX_RTS525A) 3683 sc->rtsx_res_id = PCIR_BAR(1); 3684 else 3685 sc->rtsx_res_id = PCIR_BAR(0); 3686 sc->rtsx_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->rtsx_res_id, RF_ACTIVE); 3687 if (sc->rtsx_res == NULL) { 3688 device_printf(dev, "Can't allocate memory resource for %d\n", sc->rtsx_res_id); 3689 goto destroy_rtsx_irq_res; 3690 } 3691 3692 if (bootverbose) 3693 device_printf(dev, "rtsx_irq_res_id: %d, rtsx_res_id: %d\n", 3694 sc->rtsx_irq_res_id, sc->rtsx_res_id); 3695 3696 sc->rtsx_btag = rman_get_bustag(sc->rtsx_res); 3697 sc->rtsx_bhandle = rman_get_bushandle(sc->rtsx_res); 3698 3699 TIMEOUT_TASK_INIT(taskqueue_swi_giant, &sc->rtsx_card_insert_task, 0, 3700 rtsx_card_task, sc); 3701 TASK_INIT(&sc->rtsx_card_remove_task, 0, rtsx_card_task, sc); 3702 3703 /* Allocate two DMA buffers: a command buffer and a data buffer. */ 3704 error = rtsx_dma_alloc(sc); 3705 if (error) 3706 goto destroy_rtsx_irq_res; 3707 3708 /* Activate the interrupt. */ 3709 error = bus_setup_intr(dev, sc->rtsx_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 3710 NULL, rtsx_intr, sc, &sc->rtsx_irq_cookie); 3711 if (error) { 3712 device_printf(dev, "Can't set up irq [0x%x]!\n", error); 3713 goto destroy_rtsx_res; 3714 } 3715 pci_enable_busmaster(dev); 3716 3717 if (rtsx_read_cfg(sc, 0, RTSX_SDIOCFG_REG, &sdio_cfg) == 0) { 3718 if ((sdio_cfg & RTSX_SDIOCFG_SDIO_ONLY) || 3719 (sdio_cfg & RTSX_SDIOCFG_HAVE_SDIO)) 3720 sc->rtsx_flags |= RTSX_F_SDIO_SUPPORT; 3721 } 3722 3723 #ifdef MMCCAM 3724 sc->rtsx_ccb = NULL; 3725 sc->rtsx_cam_status = 0; 3726 3727 SYSCTL_ADD_U8(ctx, tree, OID_AUTO, "cam_status", CTLFLAG_RD, 3728 &sc->rtsx_cam_status, 0, "driver cam card present"); 3729 if ((sc->rtsx_devq = cam_simq_alloc(1)) == NULL) { 3730 device_printf(dev, "Error during CAM queue allocation\n"); 3731 goto destroy_rtsx_irq; 3732 } 3733 mtx_init(&sc->rtsx_sim_mtx, "rtsxsim", NULL, MTX_DEF); 3734 sc->rtsx_sim = cam_sim_alloc(rtsx_cam_action, rtsx_cam_poll, 3735 "rtsx", sc, device_get_unit(dev), 3736 &sc->rtsx_sim_mtx, 1, 1, sc->rtsx_devq); 3737 if (sc->rtsx_sim == NULL) { 3738 device_printf(dev, "Can't allocate CAM SIM\n"); 3739 goto destroy_rtsx_irq; 3740 } 3741 mtx_lock(&sc->rtsx_sim_mtx); 3742 if (xpt_bus_register(sc->rtsx_sim, dev, 0) != 0) { 3743 device_printf(dev, "Can't register SCSI pass-through bus\n"); 3744 mtx_unlock(&sc->rtsx_sim_mtx); 3745 goto destroy_rtsx_irq; 3746 } 3747 mtx_unlock(&sc->rtsx_sim_mtx); 3748 #endif /* MMCCAM */ 3749 3750 /* Initialize device. */ 3751 if (rtsx_init(sc)) { 3752 device_printf(dev, "Error during rtsx_init()\n"); 3753 goto destroy_rtsx_irq; 3754 } 3755 3756 /* 3757 * Schedule a card detection as we won't get an interrupt 3758 * if the card is inserted when we attach. We wait a quarter 3759 * of a second to allow for a "spontaneous" interrupt which may 3760 * change the card presence state. This delay avoid a panic 3761 * on some configuration (e.g. Lenovo T540p). 3762 */ 3763 DELAY(250000); 3764 if (rtsx_is_card_present(sc)) 3765 device_printf(sc->rtsx_dev, "A card is detected\n"); 3766 else 3767 device_printf(sc->rtsx_dev, "No card is detected\n"); 3768 rtsx_card_task(sc, 0); 3769 3770 if (bootverbose) 3771 device_printf(dev, "Device attached\n"); 3772 3773 return (0); 3774 3775 destroy_rtsx_irq: 3776 bus_teardown_intr(dev, sc->rtsx_irq_res, sc->rtsx_irq_cookie); 3777 destroy_rtsx_res: 3778 bus_release_resource(dev, SYS_RES_MEMORY, sc->rtsx_res_id, 3779 sc->rtsx_res); 3780 rtsx_dma_free(sc); 3781 destroy_rtsx_irq_res: 3782 callout_drain(&sc->rtsx_timeout_callout); 3783 bus_release_resource(dev, SYS_RES_IRQ, sc->rtsx_irq_res_id, 3784 sc->rtsx_irq_res); 3785 pci_release_msi(dev); 3786 RTSX_LOCK_DESTROY(sc); 3787 #ifdef MMCCAM 3788 if (sc->rtsx_sim != NULL) { 3789 mtx_lock(&sc->rtsx_sim_mtx); 3790 xpt_bus_deregister(cam_sim_path(sc->rtsx_sim)); 3791 cam_sim_free(sc->rtsx_sim, FALSE); 3792 mtx_unlock(&sc->rtsx_sim_mtx); 3793 } 3794 if (sc->rtsx_devq != NULL) { 3795 mtx_destroy(&sc->rtsx_sim_mtx); 3796 cam_simq_free(sc->rtsx_devq); 3797 } 3798 #endif /* MMCCAM */ 3799 3800 return (ENXIO); 3801 } 3802 3803 static int 3804 rtsx_detach(device_t dev) 3805 { 3806 struct rtsx_softc *sc = device_get_softc(dev); 3807 int error; 3808 3809 if (bootverbose) 3810 device_printf(dev, "Detach - Vendor ID: 0x%x - Device ID: 0x%x\n", 3811 pci_get_vendor(dev), pci_get_device(dev)); 3812 3813 /* Disable interrupts. */ 3814 sc->rtsx_intr_enabled = 0; 3815 WRITE4(sc, RTSX_BIER, sc->rtsx_intr_enabled); 3816 3817 /* Stop device. */ 3818 error = device_delete_children(sc->rtsx_dev); 3819 sc->rtsx_mmc_dev = NULL; 3820 if (error) 3821 return (error); 3822 3823 taskqueue_drain_timeout(taskqueue_swi_giant, &sc->rtsx_card_insert_task); 3824 taskqueue_drain(taskqueue_swi_giant, &sc->rtsx_card_remove_task); 3825 3826 /* Teardown the state in our softc created in our attach routine. */ 3827 rtsx_dma_free(sc); 3828 if (sc->rtsx_res != NULL) 3829 bus_release_resource(dev, SYS_RES_MEMORY, sc->rtsx_res_id, 3830 sc->rtsx_res); 3831 if (sc->rtsx_irq_cookie != NULL) 3832 bus_teardown_intr(dev, sc->rtsx_irq_res, sc->rtsx_irq_cookie); 3833 if (sc->rtsx_irq_res != NULL) { 3834 callout_drain(&sc->rtsx_timeout_callout); 3835 bus_release_resource(dev, SYS_RES_IRQ, sc->rtsx_irq_res_id, 3836 sc->rtsx_irq_res); 3837 pci_release_msi(dev); 3838 } 3839 RTSX_LOCK_DESTROY(sc); 3840 #ifdef MMCCAM 3841 if (sc->rtsx_sim != NULL) { 3842 mtx_lock(&sc->rtsx_sim_mtx); 3843 xpt_bus_deregister(cam_sim_path(sc->rtsx_sim)); 3844 cam_sim_free(sc->rtsx_sim, FALSE); 3845 mtx_unlock(&sc->rtsx_sim_mtx); 3846 } 3847 if (sc->rtsx_devq != NULL) { 3848 mtx_destroy(&sc->rtsx_sim_mtx); 3849 cam_simq_free(sc->rtsx_devq); 3850 } 3851 #endif /* MMCCAM */ 3852 3853 return (0); 3854 } 3855 3856 static int 3857 rtsx_shutdown(device_t dev) 3858 { 3859 if (bootverbose) 3860 device_printf(dev, "Shutdown\n"); 3861 3862 rtsx_detach(dev); 3863 3864 return (0); 3865 } 3866 3867 /* 3868 * Device suspend routine. 3869 */ 3870 static int 3871 rtsx_suspend(device_t dev) 3872 { 3873 struct rtsx_softc *sc = device_get_softc(dev); 3874 3875 device_printf(dev, "Suspend\n"); 3876 3877 #ifdef MMCCAM 3878 if (sc->rtsx_ccb != NULL) { 3879 device_printf(dev, "Request in progress: CMD%u, rtsr_intr_status: 0x%08x\n", 3880 sc->rtsx_ccb->mmcio.cmd.opcode, sc->rtsx_intr_status); 3881 } 3882 #else /* !MMCCAM */ 3883 if (sc->rtsx_req != NULL) { 3884 device_printf(dev, "Request in progress: CMD%u, rtsr_intr_status: 0x%08x\n", 3885 sc->rtsx_req->cmd->opcode, sc->rtsx_intr_status); 3886 } 3887 #endif /* MMCCAM */ 3888 3889 bus_generic_suspend(dev); 3890 3891 return (0); 3892 } 3893 3894 /* 3895 * Device resume routine. 3896 */ 3897 static int 3898 rtsx_resume(device_t dev) 3899 { 3900 device_printf(dev, "Resume\n"); 3901 3902 bus_generic_resume(dev); 3903 3904 return (0); 3905 } 3906 3907 static device_method_t rtsx_methods[] = { 3908 /* Device interface */ 3909 DEVMETHOD(device_probe, rtsx_probe), 3910 DEVMETHOD(device_attach, rtsx_attach), 3911 DEVMETHOD(device_detach, rtsx_detach), 3912 DEVMETHOD(device_shutdown, rtsx_shutdown), 3913 DEVMETHOD(device_suspend, rtsx_suspend), 3914 DEVMETHOD(device_resume, rtsx_resume), 3915 3916 /* Bus interface */ 3917 DEVMETHOD(bus_read_ivar, rtsx_read_ivar), 3918 DEVMETHOD(bus_write_ivar, rtsx_write_ivar), 3919 3920 /* MMC bridge interface */ 3921 DEVMETHOD(mmcbr_update_ios, rtsx_mmcbr_update_ios), 3922 DEVMETHOD(mmcbr_switch_vccq, rtsx_mmcbr_switch_vccq), 3923 DEVMETHOD(mmcbr_tune, rtsx_mmcbr_tune), 3924 DEVMETHOD(mmcbr_retune, rtsx_mmcbr_retune), 3925 DEVMETHOD(mmcbr_request, rtsx_mmcbr_request), 3926 DEVMETHOD(mmcbr_get_ro, rtsx_mmcbr_get_ro), 3927 DEVMETHOD(mmcbr_acquire_host, rtsx_mmcbr_acquire_host), 3928 DEVMETHOD(mmcbr_release_host, rtsx_mmcbr_release_host), 3929 3930 DEVMETHOD_END 3931 }; 3932 3933 static devclass_t rtsx_devclass; 3934 3935 DEFINE_CLASS_0(rtsx, rtsx_driver, rtsx_methods, sizeof(struct rtsx_softc)); 3936 DRIVER_MODULE(rtsx, pci, rtsx_driver, rtsx_devclass, NULL, NULL); 3937 #ifndef MMCCAM 3938 MMC_DECLARE_BRIDGE(rtsx); 3939 #endif /* MMCCAM */ 3940