1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 5 * Copyright (c) 2012 Stefan Sperling <stsp@openbsd.org> 6 * Copyright (c) 2020 Henri Hennebert <hlh@restart.be> 7 * Copyright (c) 2020 Gary Jennejohn <gj@freebsd.org> 8 * Copyright (c) 2020 Jesper Schmitz Mouridsen <jsm@FreeBSD.org> 9 * All rights reserved. 10 * 11 * Patch from: 12 * - Lutz Bichler <Lutz.Bichler@gmail.com> 13 * 14 * Base on OpenBSD /sys/dev/pci/rtsx_pci.c & /dev/ic/rtsx.c 15 * on Linux /drivers/mmc/host/rtsx_pci_sdmmc.c, 16 * /include/linux/rtsx_pci.h & 17 * /drivers/misc/cardreader/rtsx_pcr.c 18 * on NetBSD /sys/dev/ic/rtsx.c 19 * 20 * Permission to use, copy, modify, and distribute this software for any 21 * purpose with or without fee is hereby granted, provided that the above 22 * copyright notice and this permission notice appear in all copies. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 __FBSDID("$FreeBSD$"); 39 40 #include <sys/param.h> 41 #include <sys/module.h> 42 #include <sys/systm.h> /* For FreeBSD 11 */ 43 #include <sys/types.h> /* For FreeBSD 11 */ 44 #include <sys/errno.h> 45 #include <sys/kernel.h> 46 #include <sys/bus.h> 47 #include <sys/endian.h> 48 #include <machine/bus.h> 49 #include <sys/mutex.h> 50 #include <sys/malloc.h> 51 #include <sys/rman.h> 52 #include <sys/queue.h> 53 #include <sys/taskqueue.h> 54 #include <sys/sysctl.h> 55 #include <dev/pci/pcivar.h> 56 #include <dev/pci/pcireg.h> 57 #include <dev/mmc/bridge.h> 58 #include <dev/mmc/mmcreg.h> 59 #include <dev/mmc/mmcbrvar.h> 60 #include <machine/_inttypes.h> 61 62 #include "opt_mmccam.h" 63 64 #ifdef MMCCAM 65 #include <cam/cam.h> 66 #include <cam/cam_ccb.h> 67 #include <cam/cam_debug.h> 68 #include <cam/cam_sim.h> 69 #include <cam/cam_xpt_sim.h> 70 #include <cam/mmc/mmc_sim.h> 71 #include "mmc_sim_if.h" 72 #endif /* MMCCAM */ 73 74 #include "rtsxreg.h" 75 76 /* The softc holds our per-instance data. */ 77 struct rtsx_softc { 78 struct mtx rtsx_mtx; /* device mutex */ 79 device_t rtsx_dev; /* device */ 80 uint16_t rtsx_flags; /* device flags */ 81 uint16_t rtsx_device_id; /* device ID */ 82 device_t rtsx_mmc_dev; /* device of mmc bus */ 83 uint32_t rtsx_intr_enabled; /* enabled interrupts */ 84 uint32_t rtsx_intr_status; /* soft interrupt status */ 85 int rtsx_irq_res_id; /* bus IRQ resource id */ 86 struct resource *rtsx_irq_res; /* bus IRQ resource */ 87 void *rtsx_irq_cookie; /* bus IRQ resource cookie */ 88 struct callout rtsx_timeout_callout; /* callout for timeout */ 89 int rtsx_timeout_cmd; /* interrupt timeout for setup commands */ 90 int rtsx_timeout_io; /* interrupt timeout for I/O commands */ 91 void (*rtsx_intr_trans_ok)(struct rtsx_softc *sc); 92 /* function to call if transfer succeed */ 93 void (*rtsx_intr_trans_ko)(struct rtsx_softc *sc); 94 /* function to call if transfer fail */ 95 96 struct timeout_task 97 rtsx_card_insert_task; /* card insert delayed task */ 98 struct task rtsx_card_remove_task; /* card remove task */ 99 100 int rtsx_mem_res_id; /* bus memory resource id */ 101 struct resource *rtsx_mem_res; /* bus memory resource */ 102 bus_space_tag_t rtsx_mem_btag; /* host register set tag */ 103 bus_space_handle_t rtsx_mem_bhandle; /* host register set handle */ 104 105 bus_dma_tag_t rtsx_cmd_dma_tag; /* DMA tag for command transfer */ 106 bus_dmamap_t rtsx_cmd_dmamap; /* DMA map for command transfer */ 107 void *rtsx_cmd_dmamem; /* DMA mem for command transfer */ 108 bus_addr_t rtsx_cmd_buffer; /* device visible address of the DMA segment */ 109 int rtsx_cmd_index; /* index in rtsx_cmd_buffer */ 110 111 bus_dma_tag_t rtsx_data_dma_tag; /* DMA tag for data transfer */ 112 bus_dmamap_t rtsx_data_dmamap; /* DMA map for data transfer */ 113 void *rtsx_data_dmamem; /* DMA mem for data transfer */ 114 bus_addr_t rtsx_data_buffer; /* device visible address of the DMA segment */ 115 116 #ifdef MMCCAM 117 union ccb *rtsx_ccb; /* CAM control block */ 118 struct mmc_sim rtsx_mmc_sim; /* CAM generic sim */ 119 struct mmc_request rtsx_cam_req; /* CAM MMC request */ 120 #endif /* MMCCAM */ 121 122 struct mmc_request *rtsx_req; /* MMC request */ 123 struct mmc_host rtsx_host; /* host parameters */ 124 int rtsx_pcie_cap; /* PCIe capability offset */ 125 int8_t rtsx_bus_busy; /* bus busy status */ 126 int8_t rtsx_ios_bus_width; /* current host.ios.bus_width */ 127 int32_t rtsx_ios_clock; /* current host.ios.clock */ 128 int8_t rtsx_ios_power_mode; /* current host.ios.power mode */ 129 int8_t rtsx_ios_timing; /* current host.ios.timing */ 130 int8_t rtsx_ios_vccq; /* current host.ios.vccq */ 131 uint8_t rtsx_read_only; /* card read only status */ 132 uint8_t rtsx_inversion; /* inversion of card detection and read only status */ 133 uint8_t rtsx_force_timing; /* force bus_timing_uhs_sdr50 */ 134 uint8_t rtsx_debug_mask; /* debugging mask */ 135 #define RTSX_DEBUG_BASIC 0x01 /* debug basic flow */ 136 #define RTSX_TRACE_SD_CMD 0x02 /* trace SD commands */ 137 #define RTSX_DEBUG_TUNING 0x04 /* debug tuning */ 138 #ifdef MMCCAM 139 uint8_t rtsx_cam_status; /* CAM status - 1 if card in use */ 140 #endif /* MMCCAM */ 141 uint64_t rtsx_read_count; /* count of read operations */ 142 uint64_t rtsx_write_count; /* count of write operations */ 143 bool rtsx_discovery_mode; /* are we in discovery mode? */ 144 bool rtsx_tuning_mode; /* are we tuning */ 145 bool rtsx_double_clk; /* double clock freqency */ 146 bool rtsx_vpclk; /* voltage at Pulse-width Modulation(PWM) clock? */ 147 uint8_t rtsx_ssc_depth; /* Spread spectrum clocking depth */ 148 uint8_t rtsx_card_drive_sel; /* value for RTSX_CARD_DRIVE_SEL */ 149 uint8_t rtsx_sd30_drive_sel_3v3;/* value for RTSX_SD30_DRIVE_SEL */ 150 }; 151 152 /* rtsx_flags values */ 153 #define RTSX_F_DEFAULT 0x0000 154 #define RTSX_F_CARD_PRESENT 0x0001 155 #define RTSX_F_SDIO_SUPPORT 0x0002 156 #define RTSX_F_VERSION_A 0x0004 157 #define RTSX_F_VERSION_B 0x0008 158 #define RTSX_F_VERSION_C 0x0010 159 #define RTSX_F_VERSION_D 0x0020 160 #define RTSX_F_8411B_QFN48 0x0040 161 #define RTSX_F_REVERSE_SOCKET 0x0080 162 163 #define RTSX_REALTEK 0x10ec 164 #define RTSX_RTS5209 0x5209 165 #define RTSX_RTS5227 0x5227 166 #define RTSX_RTS5229 0x5229 167 #define RTSX_RTS522A 0x522a 168 #define RTSX_RTS525A 0x525a 169 #define RTSX_RTS5249 0x5249 170 #define RTSX_RTS5260 0x5260 171 #define RTSX_RTL8402 0x5286 172 #define RTSX_RTL8411 0x5289 173 #define RTSX_RTL8411B 0x5287 174 175 #define RTSX_VERSION "2.1f-1" 176 177 static const struct rtsx_device { 178 uint16_t vendor_id; 179 uint16_t device_id; 180 const char *desc; 181 } rtsx_devices[] = { 182 { RTSX_REALTEK, RTSX_RTS5209, RTSX_VERSION " Realtek RTS5209 PCIe MMC/SD Card Reader"}, 183 { RTSX_REALTEK, RTSX_RTS5227, RTSX_VERSION " Realtek RTS5227 PCIe MMC/SD Card Reader"}, 184 { RTSX_REALTEK, RTSX_RTS5229, RTSX_VERSION " Realtek RTS5229 PCIe MMC/SD Card Reader"}, 185 { RTSX_REALTEK, RTSX_RTS522A, RTSX_VERSION " Realtek RTS522A PCIe MMC/SD Card Reader"}, 186 { RTSX_REALTEK, RTSX_RTS525A, RTSX_VERSION " Realtek RTS525A PCIe MMC/SD Card Reader"}, 187 { RTSX_REALTEK, RTSX_RTS5249, RTSX_VERSION " Realtek RTS5249 PCIe MMC/SD Card Reader"}, 188 { RTSX_REALTEK, RTSX_RTS5260, RTSX_VERSION " Realtek RTS5260 PCIe MMC/SD Card Reader"}, 189 { RTSX_REALTEK, RTSX_RTL8402, RTSX_VERSION " Realtek RTL8402 PCIe MMC/SD Card Reader"}, 190 { RTSX_REALTEK, RTSX_RTL8411, RTSX_VERSION " Realtek RTL8411 PCIe MMC/SD Card Reader"}, 191 { RTSX_REALTEK, RTSX_RTL8411B, RTSX_VERSION " Realtek RTL8411B PCIe MMC/SD Card Reader"}, 192 { 0, 0, NULL} 193 }; 194 195 /* See `kenv | grep smbios.system` */ 196 static const struct rtsx_inversion_model { 197 char *maker; 198 char *family; 199 char *product; 200 } rtsx_inversion_models[] = { 201 { "LENOVO", "ThinkPad T470p", "20J7S0PM00"}, 202 { NULL, NULL, NULL} 203 }; 204 205 static int rtsx_dma_alloc(struct rtsx_softc *sc); 206 static void rtsx_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 207 static void rtsx_dma_free(struct rtsx_softc *sc); 208 static void rtsx_intr(void *arg); 209 static void rtsx_handle_card_present(struct rtsx_softc *sc); 210 static void rtsx_card_task(void *arg, int pending __unused); 211 static bool rtsx_is_card_present(struct rtsx_softc *sc); 212 static int rtsx_init(struct rtsx_softc *sc); 213 static int rtsx_map_sd_drive(int index); 214 static int rtsx_rts5227_fill_driving(struct rtsx_softc *sc); 215 static int rtsx_rts5249_fill_driving(struct rtsx_softc *sc); 216 static int rtsx_rts5260_fill_driving(struct rtsx_softc *sc); 217 static int rtsx_read(struct rtsx_softc *, uint16_t, uint8_t *); 218 static int rtsx_read_cfg(struct rtsx_softc *sc, uint8_t func, uint16_t addr, uint32_t *val); 219 static int rtsx_write(struct rtsx_softc *sc, uint16_t addr, uint8_t mask, uint8_t val); 220 static int rtsx_read_phy(struct rtsx_softc *sc, uint8_t addr, uint16_t *val); 221 static int rtsx_write_phy(struct rtsx_softc *sc, uint8_t addr, uint16_t val); 222 static int rtsx_bus_power_off(struct rtsx_softc *sc); 223 static int rtsx_bus_power_on(struct rtsx_softc *sc); 224 static int rtsx_set_bus_width(struct rtsx_softc *sc, enum mmc_bus_width width); 225 static int rtsx_set_sd_timing(struct rtsx_softc *sc, enum mmc_bus_timing timing); 226 static int rtsx_set_sd_clock(struct rtsx_softc *sc, uint32_t freq); 227 static int rtsx_stop_sd_clock(struct rtsx_softc *sc); 228 static int rtsx_switch_sd_clock(struct rtsx_softc *sc, uint8_t clk, uint8_t n, uint8_t div, uint8_t mcu); 229 #ifndef MMCCAM 230 static void rtsx_sd_change_tx_phase(struct rtsx_softc *sc, uint8_t sample_point); 231 static void rtsx_sd_change_rx_phase(struct rtsx_softc *sc, uint8_t sample_point); 232 static void rtsx_sd_tuning_rx_phase(struct rtsx_softc *sc, uint32_t *phase_map); 233 static int rtsx_sd_tuning_rx_cmd(struct rtsx_softc *sc, uint8_t sample_point); 234 static int rtsx_sd_tuning_rx_cmd_wait(struct rtsx_softc *sc, struct mmc_command *cmd); 235 static void rtsx_sd_tuning_rx_cmd_wakeup(struct rtsx_softc *sc); 236 static void rtsx_sd_wait_data_idle(struct rtsx_softc *sc); 237 static uint8_t rtsx_sd_search_final_rx_phase(struct rtsx_softc *sc, uint32_t phase_map); 238 static int rtsx_sd_get_rx_phase_len(uint32_t phase_map, int start_bit); 239 #endif /* !MMCCAM */ 240 #if 0 /* For led */ 241 static int rtsx_led_enable(struct rtsx_softc *sc); 242 static int rtsx_led_disable(struct rtsx_softc *sc); 243 #endif /* For led */ 244 static uint8_t rtsx_response_type(uint16_t mmc_rsp); 245 static void rtsx_init_cmd(struct rtsx_softc *sc, struct mmc_command *cmd); 246 static void rtsx_push_cmd(struct rtsx_softc *sc, uint8_t cmd, uint16_t reg, 247 uint8_t mask, uint8_t data); 248 static void rtsx_set_cmd_data_len(struct rtsx_softc *sc, uint16_t block_cnt, uint16_t byte_cnt); 249 static void rtsx_send_cmd(struct rtsx_softc *sc); 250 static void rtsx_ret_resp(struct rtsx_softc *sc); 251 static void rtsx_set_resp(struct rtsx_softc *sc, struct mmc_command *cmd); 252 static void rtsx_stop_cmd(struct rtsx_softc *sc); 253 static void rtsx_clear_error(struct rtsx_softc *sc); 254 static void rtsx_req_done(struct rtsx_softc *sc); 255 static int rtsx_send_req(struct rtsx_softc *sc, struct mmc_command *cmd); 256 static int rtsx_xfer_short(struct rtsx_softc *sc, struct mmc_command *cmd); 257 static void rtsx_ask_ppbuf_part1(struct rtsx_softc *sc); 258 static void rtsx_get_ppbuf_part1(struct rtsx_softc *sc); 259 static void rtsx_get_ppbuf_part2(struct rtsx_softc *sc); 260 static void rtsx_put_ppbuf_part1(struct rtsx_softc *sc); 261 static void rtsx_put_ppbuf_part2(struct rtsx_softc *sc); 262 static void rtsx_write_ppbuf(struct rtsx_softc *sc); 263 static int rtsx_xfer(struct rtsx_softc *sc, struct mmc_command *cmd); 264 static void rtsx_xfer_begin(struct rtsx_softc *sc); 265 static void rtsx_xfer_start(struct rtsx_softc *sc); 266 static void rtsx_xfer_finish(struct rtsx_softc *sc); 267 static void rtsx_timeout(void *arg); 268 269 #ifdef MMCCAM 270 static int rtsx_get_tran_settings(device_t dev, struct ccb_trans_settings_mmc *cts); 271 static int rtsx_set_tran_settings(device_t dev, struct ccb_trans_settings_mmc *cts); 272 static int rtsx_cam_request(device_t dev, union ccb *ccb); 273 #endif /* MMCCAM */ 274 275 static int rtsx_read_ivar(device_t bus, device_t child, int which, uintptr_t *result); 276 static int rtsx_write_ivar(device_t bus, device_t child, int which, uintptr_t value); 277 278 static int rtsx_mmcbr_update_ios(device_t bus, device_t child __unused); 279 static int rtsx_mmcbr_switch_vccq(device_t bus, device_t child __unused); 280 static int rtsx_mmcbr_request(device_t bus, device_t child __unused, struct mmc_request *req); 281 #ifndef MMCCAM 282 static int rtsx_mmcbr_tune(device_t bus, device_t child __unused, bool hs400 __unused); 283 static int rtsx_mmcbr_retune(device_t bus, device_t child __unused, bool reset __unused); 284 static int rtsx_mmcbr_get_ro(device_t bus, device_t child __unused); 285 static int rtsx_mmcbr_acquire_host(device_t bus, device_t child __unused); 286 static int rtsx_mmcbr_release_host(device_t bus, device_t child __unused); 287 #endif /* !MMCCAM */ 288 289 static int rtsx_probe(device_t dev); 290 static int rtsx_attach(device_t dev); 291 static int rtsx_detach(device_t dev); 292 static int rtsx_shutdown(device_t dev); 293 static int rtsx_suspend(device_t dev); 294 static int rtsx_resume(device_t dev); 295 296 #define RTSX_LOCK_INIT(_sc) mtx_init(&(_sc)->rtsx_mtx, \ 297 device_get_nameunit(sc->rtsx_dev), "rtsx", MTX_DEF) 298 #define RTSX_LOCK(_sc) mtx_lock(&(_sc)->rtsx_mtx) 299 #define RTSX_UNLOCK(_sc) mtx_unlock(&(_sc)->rtsx_mtx) 300 #define RTSX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rtsx_mtx) 301 302 #define RTSX_SDCLK_OFF 0 303 #define RTSX_SDCLK_250KHZ 250000 304 #define RTSX_SDCLK_400KHZ 400000 305 #define RTSX_SDCLK_25MHZ 25000000 306 #define RTSX_SDCLK_50MHZ 50000000 307 #define RTSX_SDCLK_100MHZ 100000000 308 #define RTSX_SDCLK_208MHZ 208000000 309 310 #define RTSX_MIN_DIV_N 80 311 #define RTSX_MAX_DIV_N 208 312 313 #define RTSX_MAX_DATA_BLKLEN 512 314 315 #define RTSX_DMA_ALIGN 4 316 #define RTSX_HOSTCMD_MAX 256 317 #define RTSX_DMA_CMD_BIFSIZE (sizeof(uint32_t) * RTSX_HOSTCMD_MAX) 318 #define RTSX_DMA_DATA_BUFSIZE MAXPHYS 319 320 #define ISSET(t, f) ((t) & (f)) 321 322 #define READ4(sc, reg) \ 323 (bus_space_read_4((sc)->rtsx_mem_btag, (sc)->rtsx_mem_bhandle, (reg))) 324 #define WRITE4(sc, reg, val) \ 325 (bus_space_write_4((sc)->rtsx_mem_btag, (sc)->rtsx_mem_bhandle, (reg), (val))) 326 327 #define RTSX_READ(sc, reg, val) \ 328 do { \ 329 int err = rtsx_read((sc), (reg), (val)); \ 330 if (err) \ 331 return (err); \ 332 } while (0) 333 334 #define RTSX_WRITE(sc, reg, val) \ 335 do { \ 336 int err = rtsx_write((sc), (reg), 0xff, (val)); \ 337 if (err) \ 338 return (err); \ 339 } while (0) 340 #define RTSX_CLR(sc, reg, bits) \ 341 do { \ 342 int err = rtsx_write((sc), (reg), (bits), 0); \ 343 if (err) \ 344 return (err); \ 345 } while (0) 346 347 #define RTSX_SET(sc, reg, bits) \ 348 do { \ 349 int err = rtsx_write((sc), (reg), (bits), 0xff);\ 350 if (err) \ 351 return (err); \ 352 } while (0) 353 354 #define RTSX_BITOP(sc, reg, mask, bits) \ 355 do { \ 356 int err = rtsx_write((sc), (reg), (mask), (bits)); \ 357 if (err) \ 358 return (err); \ 359 } while (0) 360 361 /* 362 * We use two DMA buffers: a command buffer and a data buffer. 363 * 364 * The command buffer contains a command queue for the host controller, 365 * which describes SD/MMC commands to run, and other parameters. The chip 366 * runs the command queue when a special bit in the RTSX_HCBAR register is 367 * set and signals completion with the RTSX_TRANS_OK_INT interrupt. 368 * Each command is encoded as a 4 byte sequence containing command number 369 * (read, write, or check a host controller register), a register address, 370 * and a data bit-mask and value. 371 * SD/MMC commands which do not transfer any data from/to the card only use 372 * the command buffer. 373 * 374 * The data buffer is used for transfer longer than 512. Data transfer is 375 * controlled via the RTSX_HDBAR register and completion is signalled by 376 * the RTSX_TRANS_OK_INT interrupt. 377 * 378 * The chip is unable to perform DMA above 4GB. 379 */ 380 381 /* 382 * Main commands in the usual seqence used: 383 * 384 * CMD0 Go idle state 385 * CMD8 Send interface condition 386 * CMD55 Application Command for next ACMD 387 * ACMD41 Send Operation Conditions Register (OCR: voltage profile of the card) 388 * CMD2 Send Card Identification (CID) Register 389 * CMD3 Send relative address 390 * CMD9 Send Card Specific Data (CSD) 391 * CMD13 Send status (32 bits - bit 25: card password protected) 392 * CMD7 Select card (before Get card SCR) 393 * ACMD51 Send SCR (SD CARD Configuration Register - [51:48]: Bus widths supported) 394 * CMD6 SD switch function 395 * ACMD13 Send SD status (512 bits) 396 * ACMD42 Set/Clear card detect 397 * ACMD6 Set bus width 398 * CMD19 Send tuning block 399 * CMD12 Stop transmission 400 * 401 * CMD17 Read single block (<=512) 402 * CMD18 Read multiple blocks (>512) 403 * CMD24 Write single block (<=512) 404 * CMD25 Write multiple blocks (>512) 405 * 406 * CMD52 IO R/W direct 407 * CMD5 Send Operation Conditions 408 */ 409 410 static int 411 rtsx_dma_alloc(struct rtsx_softc *sc) 412 { 413 int error = 0; 414 415 error = bus_dma_tag_create(bus_get_dma_tag(sc->rtsx_dev), /* inherit from parent */ 416 RTSX_DMA_ALIGN, 0, /* alignment, boundary */ 417 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 418 BUS_SPACE_MAXADDR, /* highaddr */ 419 NULL, NULL, /* filter, filterarg */ 420 RTSX_DMA_CMD_BIFSIZE, 1, /* maxsize, nsegments */ 421 RTSX_DMA_CMD_BIFSIZE, /* maxsegsize */ 422 0, /* flags */ 423 NULL, NULL, /* lockfunc, lockarg */ 424 &sc->rtsx_cmd_dma_tag); 425 if (error) { 426 device_printf(sc->rtsx_dev, 427 "Can't create cmd parent DMA tag\n"); 428 return (error); 429 } 430 error = bus_dmamem_alloc(sc->rtsx_cmd_dma_tag, /* DMA tag */ 431 &sc->rtsx_cmd_dmamem, /* will hold the KVA pointer */ 432 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, /* flags */ 433 &sc->rtsx_cmd_dmamap); /* DMA map */ 434 if (error) { 435 device_printf(sc->rtsx_dev, 436 "Can't create DMA map for command transfer\n"); 437 goto destroy_cmd_dma_tag; 438 439 } 440 error = bus_dmamap_load(sc->rtsx_cmd_dma_tag, /* DMA tag */ 441 sc->rtsx_cmd_dmamap, /* DMA map */ 442 sc->rtsx_cmd_dmamem, /* KVA pointer to be mapped */ 443 RTSX_DMA_CMD_BIFSIZE, /* size of buffer */ 444 rtsx_dmamap_cb, /* callback */ 445 &sc->rtsx_cmd_buffer, /* first arg of callback */ 446 0); /* flags */ 447 if (error || sc->rtsx_cmd_buffer == 0) { 448 device_printf(sc->rtsx_dev, 449 "Can't load DMA memory for command transfer\n"); 450 error = (error) ? error : EFAULT; 451 goto destroy_cmd_dmamem_alloc; 452 } 453 454 error = bus_dma_tag_create(bus_get_dma_tag(sc->rtsx_dev), /* inherit from parent */ 455 RTSX_DMA_DATA_BUFSIZE, 0, /* alignment, boundary */ 456 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 457 BUS_SPACE_MAXADDR, /* highaddr */ 458 NULL, NULL, /* filter, filterarg */ 459 RTSX_DMA_DATA_BUFSIZE, 1, /* maxsize, nsegments */ 460 RTSX_DMA_DATA_BUFSIZE, /* maxsegsize */ 461 0, /* flags */ 462 NULL, NULL, /* lockfunc, lockarg */ 463 &sc->rtsx_data_dma_tag); 464 if (error) { 465 device_printf(sc->rtsx_dev, 466 "Can't create data parent DMA tag\n"); 467 goto destroy_cmd_dmamap_load; 468 } 469 error = bus_dmamem_alloc(sc->rtsx_data_dma_tag, /* DMA tag */ 470 &sc->rtsx_data_dmamem, /* will hold the KVA pointer */ 471 BUS_DMA_WAITOK | BUS_DMA_ZERO, /* flags */ 472 &sc->rtsx_data_dmamap); /* DMA map */ 473 if (error) { 474 device_printf(sc->rtsx_dev, 475 "Can't create DMA map for data transfer\n"); 476 goto destroy_data_dma_tag; 477 } 478 error = bus_dmamap_load(sc->rtsx_data_dma_tag, /* DMA tag */ 479 sc->rtsx_data_dmamap, /* DMA map */ 480 sc->rtsx_data_dmamem, /* KVA pointer to be mapped */ 481 RTSX_DMA_DATA_BUFSIZE, /* size of buffer */ 482 rtsx_dmamap_cb, /* callback */ 483 &sc->rtsx_data_buffer, /* first arg of callback */ 484 0); /* flags */ 485 if (error || sc->rtsx_data_buffer == 0) { 486 device_printf(sc->rtsx_dev, 487 "Can't load DMA memory for data transfer\n"); 488 error = (error) ? error : EFAULT; 489 goto destroy_data_dmamem_alloc; 490 } 491 return (error); 492 493 destroy_data_dmamem_alloc: 494 bus_dmamem_free(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamem, sc->rtsx_data_dmamap); 495 destroy_data_dma_tag: 496 bus_dma_tag_destroy(sc->rtsx_data_dma_tag); 497 destroy_cmd_dmamap_load: 498 bus_dmamap_unload(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap); 499 destroy_cmd_dmamem_alloc: 500 bus_dmamem_free(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamem, sc->rtsx_cmd_dmamap); 501 destroy_cmd_dma_tag: 502 bus_dma_tag_destroy(sc->rtsx_cmd_dma_tag); 503 504 return (error); 505 } 506 507 static void 508 rtsx_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 509 { 510 if (error) { 511 printf("rtsx_dmamap_cb: error %d\n", error); 512 return; 513 } 514 *(bus_addr_t *)arg = segs[0].ds_addr; 515 } 516 517 static void 518 rtsx_dma_free(struct rtsx_softc *sc) 519 { 520 if (sc->rtsx_cmd_dma_tag != NULL) { 521 if (sc->rtsx_cmd_dmamap != NULL) 522 bus_dmamap_unload(sc->rtsx_cmd_dma_tag, 523 sc->rtsx_cmd_dmamap); 524 if (sc->rtsx_cmd_dmamem != NULL) 525 bus_dmamem_free(sc->rtsx_cmd_dma_tag, 526 sc->rtsx_cmd_dmamem, 527 sc->rtsx_cmd_dmamap); 528 sc->rtsx_cmd_dmamap = NULL; 529 sc->rtsx_cmd_dmamem = NULL; 530 sc->rtsx_cmd_buffer = 0; 531 bus_dma_tag_destroy(sc->rtsx_cmd_dma_tag); 532 sc->rtsx_cmd_dma_tag = NULL; 533 } 534 if (sc->rtsx_data_dma_tag != NULL) { 535 if (sc->rtsx_data_dmamap != NULL) 536 bus_dmamap_unload(sc->rtsx_data_dma_tag, 537 sc->rtsx_data_dmamap); 538 if (sc->rtsx_data_dmamem != NULL) 539 bus_dmamem_free(sc->rtsx_data_dma_tag, 540 sc->rtsx_data_dmamem, 541 sc->rtsx_data_dmamap); 542 sc->rtsx_data_dmamap = NULL; 543 sc->rtsx_data_dmamem = NULL; 544 sc->rtsx_data_buffer = 0; 545 bus_dma_tag_destroy(sc->rtsx_data_dma_tag); 546 sc->rtsx_data_dma_tag = NULL; 547 } 548 } 549 550 static void 551 rtsx_intr(void *arg) 552 { 553 struct rtsx_softc *sc = arg; 554 uint32_t enabled; 555 uint32_t status; 556 557 RTSX_LOCK(sc); 558 559 enabled = sc->rtsx_intr_enabled; 560 status = READ4(sc, RTSX_BIPR); /* read Bus Interrupt Pending Register */ 561 sc->rtsx_intr_status = status; 562 563 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 564 device_printf(sc->rtsx_dev, "Interrupt handler - enabled: 0x%08x, status: 0x%08x\n", enabled, status); 565 566 /* Ack interrupts. */ 567 WRITE4(sc, RTSX_BIPR, status); 568 569 if (((enabled & status) == 0) || status == 0xffffffff) { 570 device_printf(sc->rtsx_dev, "Spurious interrupt - enabled: 0x%08x, status: 0x%08x\n", enabled, status); 571 RTSX_UNLOCK(sc); 572 return; 573 } 574 575 /* Detect write protect. */ 576 if (status & RTSX_SD_WRITE_PROTECT) 577 sc->rtsx_read_only = 1; 578 else 579 sc->rtsx_read_only = 0; 580 581 /* Start task to handle SD card status change (from dwmmc.c). */ 582 if (status & RTSX_SD_INT) { 583 device_printf(sc->rtsx_dev, "Interrupt card inserted/removed\n"); 584 rtsx_handle_card_present(sc); 585 } 586 587 if (sc->rtsx_req == NULL) { 588 RTSX_UNLOCK(sc); 589 return; 590 } 591 592 if (status & RTSX_TRANS_OK_INT) { 593 sc->rtsx_req->cmd->error = MMC_ERR_NONE; 594 if (sc->rtsx_intr_trans_ok != NULL) 595 sc->rtsx_intr_trans_ok(sc); 596 } else if (status & RTSX_TRANS_FAIL_INT) { 597 uint8_t stat1; 598 sc->rtsx_req->cmd->error = MMC_ERR_FAILED; 599 if (rtsx_read(sc, RTSX_SD_STAT1, &stat1) == 0 && 600 (stat1 & RTSX_SD_CRC_ERR)) { 601 device_printf(sc->rtsx_dev, "CRC error\n"); 602 sc->rtsx_req->cmd->error = MMC_ERR_BADCRC; 603 } 604 if (!sc->rtsx_tuning_mode) 605 device_printf(sc->rtsx_dev, "Transfer fail - status: 0x%08x\n", status); 606 rtsx_stop_cmd(sc); 607 if (sc->rtsx_intr_trans_ko != NULL) 608 sc->rtsx_intr_trans_ko(sc); 609 } 610 611 RTSX_UNLOCK(sc); 612 } 613 614 /* 615 * Function called from the IRQ handler (from dwmmc.c). 616 */ 617 static void 618 rtsx_handle_card_present(struct rtsx_softc *sc) 619 { 620 bool was_present; 621 bool is_present; 622 623 #ifdef MMCCAM 624 was_present = sc->rtsx_cam_status; 625 #else /* !MMCCAM */ 626 was_present = sc->rtsx_mmc_dev != NULL; 627 #endif /* MMCCAM */ 628 is_present = rtsx_is_card_present(sc); 629 if (is_present) 630 device_printf(sc->rtsx_dev, "Card present\n"); 631 else 632 device_printf(sc->rtsx_dev, "Card absent\n"); 633 634 if (!was_present && is_present) { 635 /* 636 * The delay is to debounce the card insert 637 * (sometimes the card detect pin stabilizes 638 * before the other pins have made good contact). 639 */ 640 taskqueue_enqueue_timeout(taskqueue_swi_giant, 641 &sc->rtsx_card_insert_task, -hz); 642 } else if (was_present && !is_present) { 643 taskqueue_enqueue(taskqueue_swi_giant, &sc->rtsx_card_remove_task); 644 } 645 } 646 647 /* 648 * This function is called at startup. 649 */ 650 static void 651 rtsx_card_task(void *arg, int pending __unused) 652 { 653 struct rtsx_softc *sc = arg; 654 655 if (rtsx_is_card_present(sc)) { 656 sc->rtsx_flags |= RTSX_F_CARD_PRESENT; 657 /* Card is present, attach if necessary. */ 658 #ifdef MMCCAM 659 if (sc->rtsx_cam_status == 0) { 660 #else /* !MMCCAM */ 661 if (sc->rtsx_mmc_dev == NULL) { 662 #endif /* MMCCAM */ 663 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 664 device_printf(sc->rtsx_dev, "Card inserted\n"); 665 666 sc->rtsx_read_count = sc->rtsx_write_count = 0; 667 #ifdef MMCCAM 668 sc->rtsx_cam_status = 1; 669 mmc_cam_sim_discover(&sc->rtsx_mmc_sim); 670 #else /* !MMCCAM */ 671 RTSX_LOCK(sc); 672 sc->rtsx_mmc_dev = device_add_child(sc->rtsx_dev, "mmc", -1); 673 RTSX_UNLOCK(sc); 674 if (sc->rtsx_mmc_dev == NULL) { 675 device_printf(sc->rtsx_dev, "Adding MMC bus failed\n"); 676 } else { 677 device_set_ivars(sc->rtsx_mmc_dev, sc); 678 device_probe_and_attach(sc->rtsx_mmc_dev); 679 } 680 #endif /* MMCCAM */ 681 } 682 } else { 683 sc->rtsx_flags &= ~RTSX_F_CARD_PRESENT; 684 /* Card isn't present, detach if necessary. */ 685 #ifdef MMCCAM 686 if (sc->rtsx_cam_status != 0) { 687 #else /* !MMCCAM */ 688 if (sc->rtsx_mmc_dev != NULL) { 689 #endif /* MMCCAM */ 690 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 691 device_printf(sc->rtsx_dev, "Card removed\n"); 692 693 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 694 device_printf(sc->rtsx_dev, "Read count: %" PRIu64 ", write count: %" PRIu64 "\n", 695 sc->rtsx_read_count, sc->rtsx_write_count); 696 #ifdef MMCCAM 697 sc->rtsx_cam_status = 0; 698 mmc_cam_sim_discover(&sc->rtsx_mmc_sim); 699 #else /* !MMCCAM */ 700 if (device_delete_child(sc->rtsx_dev, sc->rtsx_mmc_dev)) 701 device_printf(sc->rtsx_dev, "Detaching MMC bus failed\n"); 702 sc->rtsx_mmc_dev = NULL; 703 #endif /* MMCCAM */ 704 } 705 } 706 } 707 708 static bool 709 rtsx_is_card_present(struct rtsx_softc *sc) 710 { 711 uint32_t status; 712 713 status = READ4(sc, RTSX_BIPR); 714 if (sc->rtsx_inversion == 0) 715 return (status & RTSX_SD_EXIST); 716 else 717 return !(status & RTSX_SD_EXIST); 718 } 719 720 static int 721 rtsx_init(struct rtsx_softc *sc) 722 { 723 uint8_t version; 724 uint8_t val; 725 int error; 726 727 sc->rtsx_host.host_ocr = RTSX_SUPPORTED_VOLTAGE; 728 sc->rtsx_host.f_min = RTSX_SDCLK_250KHZ; 729 sc->rtsx_host.f_max = RTSX_SDCLK_208MHZ; 730 sc->rtsx_host.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_HSPEED | 731 MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 732 733 sc->rtsx_host.caps |= MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104; 734 if (sc->rtsx_device_id == RTSX_RTS5209) 735 sc->rtsx_host.caps |= MMC_CAP_8_BIT_DATA; 736 pci_find_cap(sc->rtsx_dev, PCIY_EXPRESS, &(sc->rtsx_pcie_cap)); 737 738 /* 739 * Check IC version. 740 */ 741 switch (sc->rtsx_device_id) { 742 case RTSX_RTS5229: 743 /* Read IC version from dummy register. */ 744 RTSX_READ(sc, RTSX_DUMMY_REG, &version); 745 if ((version & 0x0F) == RTSX_IC_VERSION_C) 746 sc->rtsx_flags |= RTSX_F_VERSION_C; 747 break; 748 case RTSX_RTS522A: 749 /* Read IC version from dummy register. */ 750 RTSX_READ(sc, RTSX_DUMMY_REG, &version); 751 if ((version & 0x0F) == RTSX_IC_VERSION_A) 752 sc->rtsx_flags |= RTSX_F_VERSION_A; 753 break; 754 case RTSX_RTS525A: 755 /* Read IC version from dummy register. */ 756 RTSX_READ(sc, RTSX_DUMMY_REG, &version); 757 if ((version & 0x0F) == RTSX_IC_VERSION_A) 758 sc->rtsx_flags |= RTSX_F_VERSION_A; 759 break; 760 case RTSX_RTL8411B: 761 RTSX_READ(sc, RTSX_RTL8411B_PACKAGE, &version); 762 if (version & RTSX_RTL8411B_QFN48) 763 sc->rtsx_flags |= RTSX_F_8411B_QFN48; 764 break; 765 } 766 767 /* 768 * Fetch vendor settings. 769 */ 770 /* 771 * Normally OEMs will set vendor setting to the config space 772 * of Realtek card reader in BIOS stage. This statement reads 773 * the setting and configure the internal registers according 774 * to it, to improve card reader's compatibility condition. 775 */ 776 sc->rtsx_card_drive_sel = RTSX_CARD_DRIVE_DEFAULT; 777 switch (sc->rtsx_device_id) { 778 uint32_t reg; 779 uint32_t reg1; 780 uint8_t reg3; 781 case RTSX_RTS5209: 782 sc->rtsx_card_drive_sel = RTSX_RTS5209_CARD_DRIVE_DEFAULT; 783 sc->rtsx_sd30_drive_sel_3v3 = RTSX_DRIVER_TYPE_D; 784 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG2, 4); 785 if (!(reg & 0x80)) { 786 sc->rtsx_card_drive_sel = (reg >> 8) & 0x3F; 787 sc->rtsx_sd30_drive_sel_3v3 = reg & 0x07; 788 } else if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) { 789 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg); 790 } 791 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 792 device_printf(sc->rtsx_dev, "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x\n", 793 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3); 794 break; 795 case RTSX_RTS5227: 796 case RTSX_RTS522A: 797 sc->rtsx_sd30_drive_sel_3v3 = RTSX_CFG_DRIVER_TYPE_B; 798 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4); 799 if (!(reg & 0x1000000)) { 800 sc->rtsx_card_drive_sel &= 0x3F; 801 sc->rtsx_card_drive_sel |= ((reg >> 25) & 0x01) << 6; 802 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG2, 4); 803 sc->rtsx_sd30_drive_sel_3v3 = (reg >> 5) & 0x03; 804 if (reg & 0x4000) 805 sc->rtsx_flags |= RTSX_F_REVERSE_SOCKET; 806 } else if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) { 807 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg); 808 } 809 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 810 device_printf(sc->rtsx_dev, 811 "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x, reverse_socket is %s\n", 812 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3, 813 (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) ? "true" : "false"); 814 break; 815 case RTSX_RTS5229: 816 sc->rtsx_sd30_drive_sel_3v3 = RTSX_DRIVER_TYPE_D; 817 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4); 818 if (!(reg & 0x1000000)) { 819 sc->rtsx_card_drive_sel &= 0x3F; 820 sc->rtsx_card_drive_sel |= ((reg >> 25) & 0x01) << 6; 821 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG2, 4); 822 sc->rtsx_sd30_drive_sel_3v3 = rtsx_map_sd_drive((reg >> 5) & 0x03); 823 } else if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) { 824 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg); 825 } 826 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 827 device_printf(sc->rtsx_dev, "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x\n", 828 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3); 829 break; 830 case RTSX_RTS525A: 831 case RTSX_RTS5249: 832 case RTSX_RTS5260: 833 sc->rtsx_sd30_drive_sel_3v3 = RTSX_CFG_DRIVER_TYPE_B; 834 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4); 835 if ((reg & 0x1000000)) { 836 sc->rtsx_card_drive_sel &= 0x3F; 837 sc->rtsx_card_drive_sel |= ((reg >> 25) & 0x01) << 6; 838 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG2, 4); 839 sc->rtsx_sd30_drive_sel_3v3 = (reg >> 5) & 0x03; 840 if (reg & 0x4000) 841 sc->rtsx_flags |= RTSX_F_REVERSE_SOCKET; 842 } else if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) { 843 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg); 844 } 845 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 846 device_printf(sc->rtsx_dev, 847 "card_drive_sel = 0x%02x, sd30_drive_sel_3v3: 0x%02x, reverse_socket is %s\n", 848 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3, 849 (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) ? "true" : "false"); 850 break; 851 case RTSX_RTL8402: 852 case RTSX_RTL8411: 853 sc->rtsx_card_drive_sel = RTSX_RTL8411_CARD_DRIVE_DEFAULT; 854 sc->rtsx_sd30_drive_sel_3v3 = RTSX_DRIVER_TYPE_D; 855 reg1 = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4); 856 if (reg1 & 0x1000000) { 857 sc->rtsx_card_drive_sel &= 0x3F; 858 sc->rtsx_card_drive_sel |= ((reg1 >> 25) & 0x01) << 6; 859 reg3 = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG3, 1); 860 sc->rtsx_sd30_drive_sel_3v3 = (reg3 >> 5) & 0x07; 861 } else if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) { 862 device_printf(sc->rtsx_dev, "pci_read_config() error - reg1: 0x%08x\n", reg1); 863 } 864 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 865 device_printf(sc->rtsx_dev, 866 "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x\n", 867 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3); 868 break; 869 case RTSX_RTL8411B: 870 sc->rtsx_card_drive_sel = RTSX_RTL8411_CARD_DRIVE_DEFAULT; 871 sc->rtsx_sd30_drive_sel_3v3 = RTSX_DRIVER_TYPE_D; 872 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4); 873 if (!(reg & 0x1000000)) { 874 sc->rtsx_sd30_drive_sel_3v3 = rtsx_map_sd_drive(reg & 0x03); 875 } else if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) { 876 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg); 877 } 878 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 879 device_printf(sc->rtsx_dev, 880 "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x\n", 881 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3); 882 break; 883 } 884 885 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 886 device_printf(sc->rtsx_dev, "rtsx_init() rtsx_flags: 0x%04x\n", sc->rtsx_flags); 887 888 /* Enable interrupts. */ 889 sc->rtsx_intr_enabled = RTSX_TRANS_OK_INT_EN | RTSX_TRANS_FAIL_INT_EN | RTSX_SD_INT_EN | RTSX_MS_INT_EN; 890 WRITE4(sc, RTSX_BIER, sc->rtsx_intr_enabled); 891 892 /* Power on SSC clock. */ 893 RTSX_CLR(sc, RTSX_FPDCTL, RTSX_SSC_POWER_DOWN); 894 /* Wait SSC power stable. */ 895 DELAY(200); 896 897 /* Disable ASPM */ 898 val = pci_read_config(sc->rtsx_dev, sc->rtsx_pcie_cap + PCIER_LINK_CTL, 1); 899 pci_write_config(sc->rtsx_dev, sc->rtsx_pcie_cap + PCIER_LINK_CTL, val & 0xfc, 1); 900 901 /* 902 * Optimize phy. 903 */ 904 switch (sc->rtsx_device_id) { 905 case RTSX_RTS5209: 906 /* Some magic numbers from Linux driver. */ 907 if ((error = rtsx_write_phy(sc, 0x00, 0xB966))) 908 return (error); 909 break; 910 case RTSX_RTS5227: 911 RTSX_CLR(sc, RTSX_PM_CTRL3, RTSX_D3_DELINK_MODE_EN); 912 913 /* Optimize RX sensitivity. */ 914 if ((error = rtsx_write_phy(sc, 0x00, 0xBA42))) 915 return (error); 916 break; 917 case RTSX_RTS5229: 918 /* Optimize RX sensitivity. */ 919 if ((error = rtsx_write_phy(sc, 0x00, 0xBA42))) 920 return (error); 921 break; 922 case RTSX_RTS522A: 923 RTSX_CLR(sc, RTSX_RTS522A_PM_CTRL3, RTSX_D3_DELINK_MODE_EN); 924 if (sc->rtsx_flags & RTSX_F_VERSION_A) { 925 if ((error = rtsx_write_phy(sc, RTSX_PHY_RCR2, RTSX_PHY_RCR2_INIT_27S))) 926 return (error); 927 } 928 if ((error = rtsx_write_phy(sc, RTSX_PHY_RCR1, RTSX_PHY_RCR1_INIT_27S))) 929 return (error); 930 if ((error = rtsx_write_phy(sc, RTSX_PHY_FLD0, RTSX_PHY_FLD0_INIT_27S))) 931 return (error); 932 if ((error = rtsx_write_phy(sc, RTSX_PHY_FLD3, RTSX_PHY_FLD3_INIT_27S))) 933 return (error); 934 if ((error = rtsx_write_phy(sc, RTSX_PHY_FLD4, RTSX_PHY_FLD4_INIT_27S))) 935 return (error); 936 break; 937 case RTSX_RTS525A: 938 if ((error = rtsx_write_phy(sc, RTSX__PHY_FLD0, 939 RTSX__PHY_FLD0_CLK_REQ_20C | RTSX__PHY_FLD0_RX_IDLE_EN | 940 RTSX__PHY_FLD0_BIT_ERR_RSTN | RTSX__PHY_FLD0_BER_COUNT | 941 RTSX__PHY_FLD0_BER_TIMER | RTSX__PHY_FLD0_CHECK_EN))) 942 return (error); 943 if ((error = rtsx_write_phy(sc, RTSX__PHY_ANA03, 944 RTSX__PHY_ANA03_TIMER_MAX | RTSX__PHY_ANA03_OOBS_DEB_EN | 945 RTSX__PHY_CMU_DEBUG_EN))) 946 return (error); 947 if (sc->rtsx_flags & RTSX_F_VERSION_A) 948 if ((error = rtsx_write_phy(sc, RTSX__PHY_REV0, 949 RTSX__PHY_REV0_FILTER_OUT | RTSX__PHY_REV0_CDR_BYPASS_PFD | 950 RTSX__PHY_REV0_CDR_RX_IDLE_BYPASS))) 951 return (error); 952 break; 953 case RTSX_RTS5249: 954 RTSX_CLR(sc, RTSX_PM_CTRL3, RTSX_D3_DELINK_MODE_EN); 955 if ((error = rtsx_write_phy(sc, RTSX_PHY_REV, 956 RTSX_PHY_REV_RESV | RTSX_PHY_REV_RXIDLE_LATCHED | 957 RTSX_PHY_REV_P1_EN | RTSX_PHY_REV_RXIDLE_EN | 958 RTSX_PHY_REV_CLKREQ_TX_EN | RTSX_PHY_REV_RX_PWST | 959 RTSX_PHY_REV_CLKREQ_DT_1_0 | RTSX_PHY_REV_STOP_CLKRD | 960 RTSX_PHY_REV_STOP_CLKWR))) 961 return (error); 962 DELAY(1000); 963 if ((error = rtsx_write_phy(sc, RTSX_PHY_BPCR, 964 RTSX_PHY_BPCR_IBRXSEL | RTSX_PHY_BPCR_IBTXSEL | 965 RTSX_PHY_BPCR_IB_FILTER | RTSX_PHY_BPCR_CMIRROR_EN))) 966 return (error); 967 if ((error = rtsx_write_phy(sc, RTSX_PHY_PCR, 968 RTSX_PHY_PCR_FORCE_CODE | RTSX_PHY_PCR_OOBS_CALI_50 | 969 RTSX_PHY_PCR_OOBS_VCM_08 | RTSX_PHY_PCR_OOBS_SEN_90 | 970 RTSX_PHY_PCR_RSSI_EN | RTSX_PHY_PCR_RX10K))) 971 return (error); 972 if ((error = rtsx_write_phy(sc, RTSX_PHY_RCR2, 973 RTSX_PHY_RCR2_EMPHASE_EN | RTSX_PHY_RCR2_NADJR | 974 RTSX_PHY_RCR2_CDR_SR_2 | RTSX_PHY_RCR2_FREQSEL_12 | 975 RTSX_PHY_RCR2_CDR_SC_12P | RTSX_PHY_RCR2_CALIB_LATE))) 976 return (error); 977 if ((error = rtsx_write_phy(sc, RTSX_PHY_FLD4, 978 RTSX_PHY_FLD4_FLDEN_SEL | RTSX_PHY_FLD4_REQ_REF | 979 RTSX_PHY_FLD4_RXAMP_OFF | RTSX_PHY_FLD4_REQ_ADDA | 980 RTSX_PHY_FLD4_BER_COUNT | RTSX_PHY_FLD4_BER_TIMER | 981 RTSX_PHY_FLD4_BER_CHK_EN))) 982 return (error); 983 if ((error = rtsx_write_phy(sc, RTSX_PHY_RDR, 984 RTSX_PHY_RDR_RXDSEL_1_9 | RTSX_PHY_SSC_AUTO_PWD))) 985 return (error); 986 if ((error = rtsx_write_phy(sc, RTSX_PHY_RCR1, 987 RTSX_PHY_RCR1_ADP_TIME_4 | RTSX_PHY_RCR1_VCO_COARSE))) 988 return (error); 989 if ((error = rtsx_write_phy(sc, RTSX_PHY_FLD3, 990 RTSX_PHY_FLD3_TIMER_4 | RTSX_PHY_FLD3_TIMER_6 | 991 RTSX_PHY_FLD3_RXDELINK))) 992 return (error); 993 if ((error = rtsx_write_phy(sc, RTSX_PHY_TUNE, 994 RTSX_PHY_TUNE_TUNEREF_1_0 | RTSX_PHY_TUNE_VBGSEL_1252 | 995 RTSX_PHY_TUNE_SDBUS_33 | RTSX_PHY_TUNE_TUNED18 | 996 RTSX_PHY_TUNE_TUNED12 | RTSX_PHY_TUNE_TUNEA12))) 997 return (error); 998 break; 999 } 1000 1001 /* Set mcu_cnt to 7 to ensure data can be sampled properly. */ 1002 RTSX_BITOP(sc, RTSX_CLK_DIV, 0x07, 0x07); 1003 1004 /* Disable sleep mode. */ 1005 RTSX_CLR(sc, RTSX_HOST_SLEEP_STATE, 1006 RTSX_HOST_ENTER_S1 | RTSX_HOST_ENTER_S3); 1007 1008 /* Disable card clock. */ 1009 RTSX_CLR(sc, RTSX_CARD_CLK_EN, RTSX_CARD_CLK_EN_ALL); 1010 1011 /* Reset delink mode. */ 1012 RTSX_CLR(sc, RTSX_CHANGE_LINK_STATE, 1013 RTSX_FORCE_RST_CORE_EN | RTSX_NON_STICKY_RST_N_DBG); 1014 1015 /* Card driving select. */ 1016 RTSX_WRITE(sc, RTSX_CARD_DRIVE_SEL, sc->rtsx_card_drive_sel); 1017 1018 /* Enable SSC clock. */ 1019 RTSX_WRITE(sc, RTSX_SSC_CTL1, RTSX_SSC_8X_EN | RTSX_SSC_SEL_4M); 1020 RTSX_WRITE(sc, RTSX_SSC_CTL2, 0x12); 1021 1022 /* Disable cd_pwr_save. */ 1023 RTSX_BITOP(sc, RTSX_CHANGE_LINK_STATE, 0x16, RTSX_MAC_PHY_RST_N_DBG); 1024 1025 /* Clear Link Ready Interrupt. */ 1026 RTSX_BITOP(sc, RTSX_IRQSTAT0, RTSX_LINK_READY_INT, RTSX_LINK_READY_INT); 1027 1028 /* Enlarge the estimation window of PERST# glitch 1029 * to reduce the chance of invalid card interrupt. */ 1030 RTSX_WRITE(sc, RTSX_PERST_GLITCH_WIDTH, 0x80); 1031 1032 /* Set RC oscillator to 400K. */ 1033 RTSX_CLR(sc, RTSX_RCCTL, RTSX_RCCTL_F_2M); 1034 1035 /* Enable interrupt write-clear (default is read-clear). */ 1036 RTSX_CLR(sc, RTSX_NFTS_TX_CTRL, RTSX_INT_READ_CLR); 1037 1038 if (sc->rtsx_device_id == RTSX_RTS525A) 1039 RTSX_BITOP(sc, RTSX_PM_CLK_FORCE_CTL, 1, 1); 1040 1041 /* OC power down. */ 1042 RTSX_BITOP(sc, RTSX_FPDCTL, RTSX_SD_OC_POWER_DOWN, RTSX_SD_OC_POWER_DOWN); 1043 1044 /* Enable clk_request_n to enable clock power management */ 1045 pci_write_config(sc->rtsx_dev, sc->rtsx_pcie_cap + PCIER_LINK_CTL + 1, 1, 1); 1046 1047 /* Enter L1 when host tx idle */ 1048 pci_write_config(sc->rtsx_dev, 0x70F, 0x5B, 1); 1049 1050 /* 1051 * Specific extra init. 1052 */ 1053 switch (sc->rtsx_device_id) { 1054 uint16_t cap; 1055 case RTSX_RTS5209: 1056 /* Turn off LED. */ 1057 RTSX_WRITE(sc, RTSX_CARD_GPIO, 0x03); 1058 /* Reset ASPM state to default value. */ 1059 RTSX_CLR(sc, RTSX_ASPM_FORCE_CTL, RTSX_ASPM_FORCE_MASK); 1060 /* Force CLKREQ# PIN to drive 0 to request clock. */ 1061 RTSX_BITOP(sc, RTSX_PETXCFG, 0x08, 0x08); 1062 /* Configure GPIO as output. */ 1063 RTSX_WRITE(sc, RTSX_CARD_GPIO_DIR, 0x03); 1064 /* Configure driving. */ 1065 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, sc->rtsx_sd30_drive_sel_3v3); 1066 break; 1067 case RTSX_RTS5227: 1068 /* Configure GPIO as output. */ 1069 RTSX_BITOP(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON, RTSX_GPIO_LED_ON); 1070 /* Reset ASPM state to default value. */ 1071 RTSX_BITOP(sc, RTSX_ASPM_FORCE_CTL, RTSX_ASPM_FORCE_MASK, RTSX_FORCE_ASPM_NO_ASPM); 1072 /* Switch LDO3318 source from DV33 to 3V3. */ 1073 RTSX_CLR(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33); 1074 RTSX_BITOP(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33, RTSX_LDO_PWR_SEL_3V3); 1075 /* Set default OLT blink period. */ 1076 RTSX_BITOP(sc, RTSX_OLT_LED_CTL, 0x0F, RTSX_OLT_LED_PERIOD); 1077 /* Configure LTR. */ 1078 cap = pci_read_config(sc->rtsx_dev, sc->rtsx_pcie_cap + PCIER_DEVICE_CTL2, 2); 1079 if (cap & PCIEM_CTL2_LTR_ENABLE) 1080 RTSX_WRITE(sc, RTSX_LTR_CTL, 0xa3); 1081 /* Configure OBFF. */ 1082 RTSX_BITOP(sc, RTSX_OBFF_CFG, RTSX_OBFF_EN_MASK, RTSX_OBFF_ENABLE); 1083 /* Configure driving. */ 1084 if ((error = rtsx_rts5227_fill_driving(sc))) 1085 return (error); 1086 /* Configure force_clock_req. */ 1087 if (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) 1088 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB8, 0xB8); 1089 else 1090 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB8, 0x88); 1091 RTSX_CLR(sc, RTSX_PM_CTRL3, RTSX_D3_DELINK_MODE_EN); 1092 /*!!! Added for reboot after Windows. */ 1093 RTSX_BITOP(sc, RTSX_PM_CTRL3, RTSX_PM_WAKE_EN, RTSX_PM_WAKE_EN); 1094 break; 1095 case RTSX_RTS5229: 1096 /* Configure GPIO as output. */ 1097 RTSX_BITOP(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON, RTSX_GPIO_LED_ON); 1098 /* Reset ASPM state to default value. */ 1099 /* With this reset: dd if=/dev/random of=/dev/mmcsd0 encounter a timeout. */ 1100 //!!! RTSX_BITOP(sc, RTSX_ASPM_FORCE_CTL, RTSX_ASPM_FORCE_MASK, RTSX_FORCE_ASPM_NO_ASPM); 1101 /* Force CLKREQ# PIN to drive 0 to request clock. */ 1102 RTSX_BITOP(sc, RTSX_PETXCFG, 0x08, 0x08); 1103 /* Switch LDO3318 source from DV33 to card_3v3. */ 1104 RTSX_CLR(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33); 1105 RTSX_BITOP(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33, RTSX_LDO_PWR_SEL_3V3); 1106 /* Set default OLT blink period. */ 1107 RTSX_BITOP(sc, RTSX_OLT_LED_CTL, 0x0F, RTSX_OLT_LED_PERIOD); 1108 /* Configure driving. */ 1109 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, sc->rtsx_sd30_drive_sel_3v3); 1110 break; 1111 case RTSX_RTS522A: 1112 /* Add specific init from RTS5227. */ 1113 /* Configure GPIO as output. */ 1114 RTSX_BITOP(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON, RTSX_GPIO_LED_ON); 1115 /* Reset ASPM state to default value. */ 1116 RTSX_BITOP(sc, RTSX_ASPM_FORCE_CTL, RTSX_ASPM_FORCE_MASK, RTSX_FORCE_ASPM_NO_ASPM); 1117 /* Switch LDO3318 source from DV33 to 3V3. */ 1118 RTSX_CLR(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33); 1119 RTSX_BITOP(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33, RTSX_LDO_PWR_SEL_3V3); 1120 /* Set default OLT blink period. */ 1121 RTSX_BITOP(sc, RTSX_OLT_LED_CTL, 0x0F, RTSX_OLT_LED_PERIOD); 1122 /* Configure LTR. */ 1123 cap = pci_read_config(sc->rtsx_dev, sc->rtsx_pcie_cap + PCIER_DEVICE_CTL2, 2); 1124 if (cap & PCIEM_CTL2_LTR_ENABLE) 1125 RTSX_WRITE(sc, RTSX_LTR_CTL, 0xa3); 1126 /* Configure OBFF. */ 1127 RTSX_BITOP(sc, RTSX_OBFF_CFG, RTSX_OBFF_EN_MASK, RTSX_OBFF_ENABLE); 1128 /* Configure driving. */ 1129 if ((error = rtsx_rts5227_fill_driving(sc))) 1130 return (error); 1131 /* Configure force_clock_req. */ 1132 if (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) 1133 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB8, 0xB8); 1134 else 1135 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB8, 0x88); 1136 RTSX_CLR(sc, RTSX_RTS522A_PM_CTRL3, 0x10); 1137 1138 /* specific for RTS522A. */ 1139 RTSX_BITOP(sc, RTSX_FUNC_FORCE_CTL, 1140 RTSX_FUNC_FORCE_UPME_XMT_DBG, RTSX_FUNC_FORCE_UPME_XMT_DBG); 1141 RTSX_BITOP(sc, RTSX_PCLK_CTL, 0x04, 0x04); 1142 RTSX_BITOP(sc, RTSX_PM_EVENT_DEBUG, 1143 RTSX_PME_DEBUG_0, RTSX_PME_DEBUG_0); 1144 RTSX_WRITE(sc, RTSX_PM_CLK_FORCE_CTL, 0x11); 1145 break; 1146 case RTSX_RTS525A: 1147 /* Add specific init from RTS5249. */ 1148 /* Rest L1SUB Config. */ 1149 RTSX_CLR(sc, RTSX_L1SUB_CONFIG3, 0xff); 1150 /* Configure GPIO as output. */ 1151 RTSX_BITOP(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON, RTSX_GPIO_LED_ON); 1152 /* Reset ASPM state to default value. */ 1153 RTSX_BITOP(sc, RTSX_ASPM_FORCE_CTL, RTSX_ASPM_FORCE_MASK, RTSX_FORCE_ASPM_NO_ASPM); 1154 /* Switch LDO3318 source from DV33 to 3V3. */ 1155 RTSX_CLR(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33); 1156 RTSX_BITOP(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33, RTSX_LDO_PWR_SEL_3V3); 1157 /* Set default OLT blink period. */ 1158 RTSX_BITOP(sc, RTSX_OLT_LED_CTL, 0x0F, RTSX_OLT_LED_PERIOD); 1159 /* Configure driving. */ 1160 if ((error = rtsx_rts5249_fill_driving(sc))) 1161 return (error); 1162 /* Configure force_clock_req. */ 1163 if (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) 1164 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0xB0); 1165 else 1166 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0x80); 1167 1168 /* Specifc for RTS525A. */ 1169 RTSX_BITOP(sc, RTSX_PCLK_CTL, RTSX_PCLK_MODE_SEL, RTSX_PCLK_MODE_SEL); 1170 if (sc->rtsx_flags & RTSX_F_VERSION_A) { 1171 RTSX_WRITE(sc, RTSX_L1SUB_CONFIG2, RTSX_L1SUB_AUTO_CFG); 1172 RTSX_BITOP(sc, RTSX_RREF_CFG, 1173 RTSX_RREF_VBGSEL_MASK, RTSX_RREF_VBGSEL_1V25); 1174 RTSX_BITOP(sc, RTSX_LDO_VIO_CFG, 1175 RTSX_LDO_VIO_TUNE_MASK, RTSX_LDO_VIO_1V7); 1176 RTSX_BITOP(sc, RTSX_LDO_DV12S_CFG, 1177 RTSX_LDO_D12_TUNE_MASK, RTSX_LDO_D12_TUNE_DF); 1178 RTSX_BITOP(sc, RTSX_LDO_AV12S_CFG, 1179 RTSX_LDO_AV12S_TUNE_MASK, RTSX_LDO_AV12S_TUNE_DF); 1180 RTSX_BITOP(sc, RTSX_LDO_VCC_CFG0, 1181 RTSX_LDO_VCC_LMTVTH_MASK, RTSX_LDO_VCC_LMTVTH_2A); 1182 RTSX_BITOP(sc, RTSX_OOBS_CONFIG, 1183 RTSX_OOBS_AUTOK_DIS | RTSX_OOBS_VAL_MASK, 0x89); 1184 } 1185 break; 1186 case RTSX_RTS5249: 1187 /* Rest L1SUB Config. */ 1188 RTSX_CLR(sc, RTSX_L1SUB_CONFIG3, 0xff); 1189 /* Configure GPIO as output. */ 1190 RTSX_BITOP(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON, RTSX_GPIO_LED_ON); 1191 /* Reset ASPM state to default value. */ 1192 RTSX_BITOP(sc, RTSX_ASPM_FORCE_CTL, RTSX_ASPM_FORCE_MASK, RTSX_FORCE_ASPM_NO_ASPM); 1193 /* Switch LDO3318 source from DV33 to 3V3. */ 1194 RTSX_CLR(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33); 1195 RTSX_BITOP(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33, RTSX_LDO_PWR_SEL_3V3); 1196 /* Set default OLT blink period. */ 1197 RTSX_BITOP(sc, RTSX_OLT_LED_CTL, 0x0F, RTSX_OLT_LED_PERIOD); 1198 /* Configure driving. */ 1199 if ((error = rtsx_rts5249_fill_driving(sc))) 1200 return (error); 1201 /* Configure force_clock_req. */ 1202 if (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) 1203 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0xB0); 1204 else 1205 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0x80); 1206 break; 1207 case RTSX_RTS5260: 1208 /* Set mcu_cnt to 7 to ensure data can be sampled properly. */ 1209 RTSX_BITOP(sc, RTSX_CLK_DIV, 0x07, 0x07); 1210 RTSX_WRITE(sc, RTSX_SSC_DIV_N_0, 0x5D); 1211 /* force no MDIO*/ 1212 RTSX_WRITE(sc, RTSX_RTS5260_AUTOLOAD_CFG4, RTSX_RTS5260_MIMO_DISABLE); 1213 /*Modify SDVCC Tune Default Parameters!*/ 1214 RTSX_BITOP(sc, RTSX_LDO_VCC_CFG0, RTSX_RTS5260_DVCC_TUNE_MASK, RTSX_RTS5260_DVCC_33); 1215 RTSX_BITOP(sc, RTSX_PCLK_CTL, RTSX_PCLK_MODE_SEL, RTSX_PCLK_MODE_SEL); 1216 RTSX_BITOP(sc, RTSX_L1SUB_CONFIG1, RTSX_AUX_CLK_ACTIVE_SEL_MASK, RTSX_MAC_CKSW_DONE); 1217 /* Rest L1SUB Config */ 1218 RTSX_CLR(sc, RTSX_L1SUB_CONFIG3, 0xFF); 1219 RTSX_BITOP(sc, RTSX_PM_CLK_FORCE_CTL, RTSX_CLK_PM_EN, RTSX_CLK_PM_EN); 1220 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_PWR_GATE_EN, RTSX_PWR_GATE_EN); 1221 RTSX_BITOP(sc, RTSX_RB_FLUSH, RTSX_U_AUTO_DMA_EN_MASK, RTSX_U_AUTO_DMA_DISABLE); 1222 if (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) 1223 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0xB0); 1224 else 1225 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0x80); 1226 RTSX_BITOP(sc, RTSX_OBFF_CFG, RTSX_OBFF_EN_MASK, RTSX_OBFF_DISABLE); 1227 break; 1228 case RTSX_RTL8402: 1229 case RTSX_RTL8411: 1230 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, sc->rtsx_sd30_drive_sel_3v3); 1231 RTSX_BITOP(sc, RTSX_CARD_PAD_CTL, RTSX_CD_DISABLE_MASK | RTSX_CD_AUTO_DISABLE, 1232 RTSX_CD_ENABLE); 1233 break; 1234 case RTSX_RTL8411B: 1235 if (sc->rtsx_flags & RTSX_F_8411B_QFN48) 1236 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xf5); 1237 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, sc->rtsx_sd30_drive_sel_3v3); 1238 /* Enable SD interrupt. */ 1239 RTSX_BITOP(sc, RTSX_CARD_PAD_CTL, RTSX_CD_DISABLE_MASK | RTSX_CD_AUTO_DISABLE, 1240 RTSX_CD_ENABLE); 1241 /* Clear hw_pfm_en to disable hardware PFM mode. */ 1242 RTSX_BITOP(sc, RTSX_FUNC_FORCE_CTL, 0x06, 0x00); 1243 break; 1244 } 1245 1246 /*!!! Added for reboot after Windows. */ 1247 rtsx_bus_power_off(sc); 1248 rtsx_set_sd_timing(sc, bus_timing_normal); 1249 rtsx_set_sd_clock(sc, 0); 1250 /*!!! Added for reboot after Windows. */ 1251 1252 return (0); 1253 } 1254 1255 static int 1256 rtsx_map_sd_drive(int index) 1257 { 1258 uint8_t sd_drive[4] = 1259 { 1260 0x01, /* Type D */ 1261 0x02, /* Type C */ 1262 0x05, /* Type A */ 1263 0x03 /* Type B */ 1264 }; 1265 return (sd_drive[index]); 1266 } 1267 1268 /* For voltage 3v3. */ 1269 static int 1270 rtsx_rts5227_fill_driving(struct rtsx_softc *sc) 1271 { 1272 u_char driving_3v3[4][3] = { 1273 {0x13, 0x13, 0x13}, 1274 {0x96, 0x96, 0x96}, 1275 {0x7F, 0x7F, 0x7F}, 1276 {0x96, 0x96, 0x96}, 1277 }; 1278 RTSX_WRITE(sc, RTSX_SD30_CLK_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][0]); 1279 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][1]); 1280 RTSX_WRITE(sc, RTSX_SD30_DAT_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][2]); 1281 1282 return (0); 1283 } 1284 1285 /* For voltage 3v3. */ 1286 static int 1287 rtsx_rts5249_fill_driving(struct rtsx_softc *sc) 1288 { 1289 u_char driving_3v3[4][3] = { 1290 {0x11, 0x11, 0x18}, 1291 {0x55, 0x55, 0x5C}, 1292 {0xFF, 0xFF, 0xFF}, 1293 {0x96, 0x96, 0x96}, 1294 }; 1295 RTSX_WRITE(sc, RTSX_SD30_CLK_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][0]); 1296 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][1]); 1297 RTSX_WRITE(sc, RTSX_SD30_DAT_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][2]); 1298 1299 return (0); 1300 } 1301 1302 static int 1303 rtsx_rts5260_fill_driving(struct rtsx_softc *sc) 1304 { 1305 u_char driving_3v3[4][3] = { 1306 {0x11, 0x11, 0x11}, 1307 {0x22, 0x22, 0x22}, 1308 {0x55, 0x55, 0x55}, 1309 {0x33, 0x33, 0x33}, 1310 }; 1311 RTSX_WRITE(sc, RTSX_SD30_CLK_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][0]); 1312 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][1]); 1313 RTSX_WRITE(sc, RTSX_SD30_DAT_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][2]); 1314 1315 return (0); 1316 } 1317 1318 static int 1319 rtsx_read(struct rtsx_softc *sc, uint16_t addr, uint8_t *val) 1320 { 1321 int tries = 1024; 1322 uint32_t arg; 1323 uint32_t reg; 1324 1325 arg = RTSX_HAIMR_BUSY | (uint32_t)((addr & 0x3FFF) << 16); 1326 WRITE4(sc, RTSX_HAIMR, arg); 1327 1328 while (tries--) { 1329 reg = READ4(sc, RTSX_HAIMR); 1330 if (!(reg & RTSX_HAIMR_BUSY)) 1331 break; 1332 } 1333 *val = (reg & 0xff); 1334 1335 if (tries > 0) { 1336 return (0); 1337 } else { 1338 device_printf(sc->rtsx_dev, "rtsx_read(0x%x) timeout\n", arg); 1339 return (ETIMEDOUT); 1340 } 1341 } 1342 1343 static int 1344 rtsx_read_cfg(struct rtsx_softc *sc, uint8_t func, uint16_t addr, uint32_t *val) 1345 { 1346 int tries = 1024; 1347 uint8_t data0, data1, data2, data3, rwctl; 1348 1349 RTSX_WRITE(sc, RTSX_CFGADDR0, addr); 1350 RTSX_WRITE(sc, RTSX_CFGADDR1, addr >> 8); 1351 RTSX_WRITE(sc, RTSX_CFGRWCTL, RTSX_CFG_BUSY | (func & 0x03 << 4)); 1352 1353 while (tries--) { 1354 RTSX_READ(sc, RTSX_CFGRWCTL, &rwctl); 1355 if (!(rwctl & RTSX_CFG_BUSY)) 1356 break; 1357 } 1358 1359 if (tries == 0) 1360 return (ETIMEDOUT); 1361 1362 RTSX_READ(sc, RTSX_CFGDATA0, &data0); 1363 RTSX_READ(sc, RTSX_CFGDATA1, &data1); 1364 RTSX_READ(sc, RTSX_CFGDATA2, &data2); 1365 RTSX_READ(sc, RTSX_CFGDATA3, &data3); 1366 1367 *val = (data3 << 24) | (data2 << 16) | (data1 << 8) | data0; 1368 1369 return (0); 1370 } 1371 1372 static int 1373 rtsx_write(struct rtsx_softc *sc, uint16_t addr, uint8_t mask, uint8_t val) 1374 { 1375 int tries = 1024; 1376 uint32_t arg; 1377 uint32_t reg; 1378 1379 arg = RTSX_HAIMR_BUSY | RTSX_HAIMR_WRITE | 1380 (uint32_t)(((addr & 0x3FFF) << 16) | 1381 (mask << 8) | val); 1382 WRITE4(sc, RTSX_HAIMR, arg); 1383 1384 while (tries--) { 1385 reg = READ4(sc, RTSX_HAIMR); 1386 if (!(reg & RTSX_HAIMR_BUSY)) { 1387 if (val != (reg & 0xff)) { 1388 device_printf(sc->rtsx_dev, "rtsx_write(0x%x) error reg=0x%x\n", arg, reg); 1389 return (EIO); 1390 } 1391 return (0); 1392 } 1393 } 1394 device_printf(sc->rtsx_dev, "rtsx_write(0x%x) timeout\n", arg); 1395 1396 return (ETIMEDOUT); 1397 } 1398 1399 static int 1400 rtsx_read_phy(struct rtsx_softc *sc, uint8_t addr, uint16_t *val) 1401 { 1402 int tries = 100000; 1403 uint8_t data0, data1, rwctl; 1404 1405 RTSX_WRITE(sc, RTSX_PHY_ADDR, addr); 1406 RTSX_WRITE(sc, RTSX_PHY_RWCTL, RTSX_PHY_BUSY | RTSX_PHY_READ); 1407 1408 while (tries--) { 1409 RTSX_READ(sc, RTSX_PHY_RWCTL, &rwctl); 1410 if (!(rwctl & RTSX_PHY_BUSY)) 1411 break; 1412 } 1413 if (tries == 0) 1414 return (ETIMEDOUT); 1415 1416 RTSX_READ(sc, RTSX_PHY_DATA0, &data0); 1417 RTSX_READ(sc, RTSX_PHY_DATA1, &data1); 1418 *val = data1 << 8 | data0; 1419 1420 return (0); 1421 } 1422 1423 static int 1424 rtsx_write_phy(struct rtsx_softc *sc, uint8_t addr, uint16_t val) 1425 { 1426 int tries = 100000; 1427 uint8_t rwctl; 1428 1429 RTSX_WRITE(sc, RTSX_PHY_DATA0, val); 1430 RTSX_WRITE(sc, RTSX_PHY_DATA1, val >> 8); 1431 RTSX_WRITE(sc, RTSX_PHY_ADDR, addr); 1432 RTSX_WRITE(sc, RTSX_PHY_RWCTL, RTSX_PHY_BUSY | RTSX_PHY_WRITE); 1433 1434 while (tries--) { 1435 RTSX_READ(sc, RTSX_PHY_RWCTL, &rwctl); 1436 if (!(rwctl & RTSX_PHY_BUSY)) 1437 break; 1438 } 1439 1440 return ((tries == 0) ? ETIMEDOUT : 0); 1441 } 1442 1443 /* 1444 * Notice that the meaning of RTSX_PWR_GATE_CTRL changes between RTS5209 and 1445 * RTS5229. In RTS5209 it is a mask of disabled power gates, while in RTS5229 1446 * it is a mask of *enabled* gates. 1447 */ 1448 static int 1449 rtsx_bus_power_off(struct rtsx_softc *sc) 1450 { 1451 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 1452 device_printf(sc->rtsx_dev, "rtsx_bus_power_off()\n"); 1453 1454 /* Disable SD clock. */ 1455 RTSX_CLR(sc, RTSX_CARD_CLK_EN, RTSX_SD_CLK_EN); 1456 1457 /* Disable SD output. */ 1458 RTSX_CLR(sc, RTSX_CARD_OE, RTSX_SD_OUTPUT_EN); 1459 1460 /* Turn off power. */ 1461 switch (sc->rtsx_device_id) { 1462 case RTSX_RTS5209: 1463 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK | RTSX_PMOS_STRG_MASK, 1464 RTSX_SD_PWR_OFF | RTSX_PMOS_STRG_400mA); 1465 RTSX_SET(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_OFF); 1466 break; 1467 case RTSX_RTS5227: 1468 case RTSX_RTS5229: 1469 case RTSX_RTS522A: 1470 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK | RTSX_PMOS_STRG_MASK, 1471 RTSX_SD_PWR_OFF | RTSX_PMOS_STRG_400mA); 1472 RTSX_CLR(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK); 1473 break; 1474 case RTSX_RTS5260: 1475 RTSX_BITOP(sc, RTSX_LDO_VCC_CFG1, RTSX_LDO_POW_SDVDD1_MASK, RTSX_LDO_POW_SDVDD1_OFF); 1476 RTSX_BITOP(sc, RTSX_LDO_CONFIG2, RTSX_DV331812_POWERON, RTSX_DV331812_POWEROFF); 1477 break; 1478 case RTSX_RTL8402: 1479 case RTSX_RTL8411: 1480 case RTSX_RTL8411B: 1481 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK, 1482 RTSX_BPP_POWER_OFF); 1483 RTSX_BITOP(sc, RTSX_LDO_CTL, RTSX_BPP_LDO_POWB, 1484 RTSX_BPP_LDO_SUSPEND); 1485 break; 1486 default: 1487 RTSX_CLR(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK); 1488 RTSX_SET(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_OFF); 1489 RTSX_CLR(sc, RTSX_CARD_PWR_CTL, RTSX_PMOS_STRG_800mA); 1490 break; 1491 } 1492 1493 /* Disable pull control. */ 1494 switch (sc->rtsx_device_id) { 1495 case RTSX_RTS5209: 1496 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, RTSX_PULL_CTL_DISABLE12); 1497 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_DISABLE12); 1498 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_DISABLE3); 1499 break; 1500 case RTSX_RTS5227: 1501 case RTSX_RTS522A: 1502 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_DISABLE12); 1503 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_DISABLE3); 1504 break; 1505 case RTSX_RTS5229: 1506 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_DISABLE12); 1507 if (sc->rtsx_flags & RTSX_F_VERSION_C) 1508 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_DISABLE3_TYPE_C); 1509 else 1510 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_DISABLE3); 1511 break; 1512 case RTSX_RTS525A: 1513 case RTSX_RTS5249: 1514 case RTSX_RTS5260: 1515 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0x66); 1516 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_DISABLE12); 1517 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_DISABLE3); 1518 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x55); 1519 break; 1520 case RTSX_RTL8402: 1521 case RTSX_RTL8411: 1522 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0x65); 1523 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0x55); 1524 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0x95); 1525 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x09); 1526 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL5, 0x05); 1527 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x04); 1528 break; 1529 case RTSX_RTL8411B: 1530 if (sc->rtsx_flags & RTSX_F_8411B_QFN48) { 1531 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0x55); 1532 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xf5); 1533 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x15); 1534 } else { 1535 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0x65); 1536 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0x55); 1537 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xd5); 1538 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x59); 1539 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL5, 0x55); 1540 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x15); 1541 } 1542 break; 1543 } 1544 1545 return (0); 1546 } 1547 1548 static int 1549 rtsx_bus_power_on(struct rtsx_softc *sc) 1550 { 1551 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 1552 device_printf(sc->rtsx_dev, "rtsx_bus_power_on()\n"); 1553 1554 /* Select SD card. */ 1555 RTSX_BITOP(sc, RTSX_CARD_SELECT, 0x07, RTSX_SD_MOD_SEL); 1556 RTSX_BITOP(sc, RTSX_CARD_SHARE_MODE, RTSX_CARD_SHARE_MASK, RTSX_CARD_SHARE_48_SD); 1557 1558 /* Enable SD clock. */ 1559 RTSX_BITOP(sc, RTSX_CARD_CLK_EN, RTSX_SD_CLK_EN, RTSX_SD_CLK_EN); 1560 1561 /* Enable pull control. */ 1562 switch (sc->rtsx_device_id) { 1563 case RTSX_RTS5209: 1564 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, RTSX_PULL_CTL_ENABLE12); 1565 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_ENABLE12); 1566 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_ENABLE3); 1567 break; 1568 case RTSX_RTS5227: 1569 case RTSX_RTS522A: 1570 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_ENABLE12); 1571 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_ENABLE3); 1572 break; 1573 case RTSX_RTS5229: 1574 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_ENABLE12); 1575 if (sc->rtsx_flags & RTSX_F_VERSION_C) 1576 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_ENABLE3_TYPE_C); 1577 else 1578 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_ENABLE3); 1579 break; 1580 case RTSX_RTS525A: 1581 case RTSX_RTS5249: 1582 case RTSX_RTS5260: 1583 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0x66); 1584 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_ENABLE12); 1585 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_ENABLE3); 1586 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0xaa); 1587 break; 1588 case RTSX_RTL8402: 1589 case RTSX_RTL8411: 1590 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0xaa); 1591 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0xaa); 1592 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xa9); 1593 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x09); 1594 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL5, 0x09); 1595 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x04); 1596 break; 1597 case RTSX_RTL8411B: 1598 if (sc->rtsx_flags & RTSX_F_8411B_QFN48) { 1599 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0xaa); 1600 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xf9); 1601 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x19); 1602 } else { 1603 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0xaa); 1604 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0xaa); 1605 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xd9); 1606 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x59); 1607 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL5, 0x55); 1608 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x15); 1609 } 1610 break; 1611 } 1612 1613 /* 1614 * To avoid a current peak, enable card power in two phases 1615 * with a delay in between. 1616 */ 1617 switch (sc->rtsx_device_id) { 1618 case RTSX_RTS5209: 1619 /* Partial power. */ 1620 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PARTIAL_PWR_ON); 1621 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, RTSX_LDO3318_VCC2); 1622 1623 DELAY(200); 1624 1625 /* Full power. */ 1626 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PWR_ON); 1627 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, RTSX_LDO3318_ON); 1628 break; 1629 case RTSX_RTS5227: 1630 case RTSX_RTS522A: 1631 /* Partial power. */ 1632 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PARTIAL_PWR_ON); 1633 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, RTSX_LDO3318_VCC1); 1634 1635 DELAY(20000); 1636 1637 /* Full power. */ 1638 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PWR_ON); 1639 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, 1640 RTSX_LDO3318_VCC1 | RTSX_LDO3318_VCC2); 1641 RTSX_BITOP(sc, RTSX_CARD_OE, RTSX_SD_OUTPUT_EN, RTSX_SD_OUTPUT_EN); 1642 RTSX_BITOP(sc, RTSX_CARD_OE, RTSX_MS_OUTPUT_EN, RTSX_MS_OUTPUT_EN); 1643 break; 1644 case RTSX_RTS5229: 1645 /* Partial power. */ 1646 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PARTIAL_PWR_ON); 1647 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, RTSX_LDO3318_VCC1); 1648 1649 DELAY(200); 1650 1651 /* Full power. */ 1652 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PWR_ON); 1653 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, 1654 RTSX_LDO3318_VCC1 | RTSX_LDO3318_VCC2); 1655 break; 1656 case RTSX_RTS525A: 1657 RTSX_BITOP(sc, RTSX_LDO_VCC_CFG1, RTSX_LDO_VCC_TUNE_MASK, RTSX_LDO_VCC_3V3); 1658 case RTSX_RTS5249: 1659 /* Partial power. */ 1660 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PARTIAL_PWR_ON); 1661 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, RTSX_LDO3318_VCC1); 1662 1663 DELAY(5000); 1664 1665 /* Full power. */ 1666 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PWR_ON); 1667 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, 1668 RTSX_LDO3318_VCC1 | RTSX_LDO3318_VCC2); 1669 break; 1670 case RTSX_RTS5260: 1671 RTSX_BITOP(sc, RTSX_LDO_CONFIG2, RTSX_DV331812_VDD1, RTSX_DV331812_VDD1); 1672 RTSX_BITOP(sc, RTSX_LDO_VCC_CFG0, RTSX_RTS5260_DVCC_TUNE_MASK, RTSX_RTS5260_DVCC_33); 1673 RTSX_BITOP(sc, RTSX_LDO_VCC_CFG1, RTSX_LDO_POW_SDVDD1_MASK, RTSX_LDO_POW_SDVDD1_ON); 1674 RTSX_BITOP(sc, RTSX_LDO_CONFIG2, RTSX_DV331812_POWERON, RTSX_DV331812_POWERON); 1675 1676 DELAY(20000); 1677 1678 /* Initialize SD_CFG1 register */ 1679 RTSX_WRITE(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_128 | RTSX_SD20_MODE); 1680 RTSX_WRITE(sc, RTSX_SD_SAMPLE_POINT_CTL, RTSX_SD20_RX_POS_EDGE); 1681 RTSX_CLR(sc, RTSX_SD_PUSH_POINT_CTL, 0xff); 1682 RTSX_BITOP(sc, RTSX_CARD_STOP, RTSX_MS_STOP | RTSX_SD_CLR_ERR, 1683 RTSX_MS_STOP | RTSX_SD_CLR_ERR); 1684 /* Reset SD_CFG3 register */ 1685 RTSX_CLR(sc, RTSX_SD_CFG3, RTSX_SD30_CLK_END_EN); 1686 RTSX_CLR(sc, RTSX_REG_SD_STOP_SDCLK_CFG, 1687 RTSX_SD30_CLK_STOP_CFG_EN | RTSX_SD30_CLK_STOP_CFG0 | RTSX_SD30_CLK_STOP_CFG1); 1688 RTSX_CLR(sc, RTSX_REG_PRE_RW_MODE, RTSX_EN_INFINITE_MODE); 1689 break; 1690 case RTSX_RTL8402: 1691 case RTSX_RTL8411: 1692 case RTSX_RTL8411B: 1693 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK, 1694 RTSX_BPP_POWER_5_PERCENT_ON); 1695 RTSX_BITOP(sc, RTSX_LDO_CTL, RTSX_BPP_LDO_POWB, 1696 RTSX_BPP_LDO_SUSPEND); 1697 DELAY(150); 1698 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK, 1699 RTSX_BPP_POWER_10_PERCENT_ON); 1700 DELAY(150); 1701 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK, 1702 RTSX_BPP_POWER_15_PERCENT_ON); 1703 DELAY(150); 1704 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK, 1705 RTSX_BPP_POWER_ON); 1706 RTSX_BITOP(sc, RTSX_LDO_CTL, RTSX_BPP_LDO_POWB, 1707 RTSX_BPP_LDO_ON); 1708 break; 1709 } 1710 1711 /* Enable SD card output. */ 1712 RTSX_WRITE(sc, RTSX_CARD_OE, RTSX_SD_OUTPUT_EN); 1713 1714 DELAY(200); 1715 1716 return (0); 1717 } 1718 1719 /* 1720 * Set but width. 1721 */ 1722 static int 1723 rtsx_set_bus_width(struct rtsx_softc *sc, enum mmc_bus_width width) 1724 { 1725 uint32_t bus_width; 1726 1727 switch (width) { 1728 case bus_width_1: 1729 bus_width = RTSX_BUS_WIDTH_1; 1730 break; 1731 case bus_width_4: 1732 bus_width = RTSX_BUS_WIDTH_4; 1733 break; 1734 case bus_width_8: 1735 bus_width = RTSX_BUS_WIDTH_8; 1736 break; 1737 default: 1738 return (MMC_ERR_INVALID); 1739 } 1740 RTSX_BITOP(sc, RTSX_SD_CFG1, RTSX_BUS_WIDTH_MASK, bus_width); 1741 1742 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) { 1743 char *busw[] = { 1744 "1 bit", 1745 "4 bits", 1746 "8 bits" 1747 }; 1748 device_printf(sc->rtsx_dev, "Setting bus width to %s\n", busw[bus_width]); 1749 } 1750 return (0); 1751 } 1752 1753 static int 1754 rtsx_set_sd_timing(struct rtsx_softc *sc, enum mmc_bus_timing timing) 1755 { 1756 if (timing == bus_timing_hs && sc->rtsx_force_timing) { 1757 timing = bus_timing_uhs_sdr50; 1758 sc->rtsx_ios_timing = timing; 1759 } 1760 1761 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 1762 device_printf(sc->rtsx_dev, "rtsx_set_sd_timing(%u)\n", timing); 1763 1764 switch (timing) { 1765 case bus_timing_uhs_sdr50: 1766 case bus_timing_uhs_sdr104: 1767 sc->rtsx_double_clk = false; 1768 sc->rtsx_vpclk = true; 1769 RTSX_BITOP(sc, RTSX_SD_CFG1, 0x0c | RTSX_SD_ASYNC_FIFO_NOT_RST, 1770 RTSX_SD30_MODE | RTSX_SD_ASYNC_FIFO_NOT_RST); 1771 RTSX_BITOP(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ, RTSX_CLK_LOW_FREQ); 1772 RTSX_WRITE(sc, RTSX_CARD_CLK_SOURCE, 1773 RTSX_CRC_VAR_CLK0 | RTSX_SD30_FIX_CLK | RTSX_SAMPLE_VAR_CLK1); 1774 RTSX_CLR(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ); 1775 break; 1776 case bus_timing_hs: 1777 RTSX_BITOP(sc, RTSX_SD_CFG1, RTSX_SD_MODE_MASK, RTSX_SD20_MODE); 1778 RTSX_BITOP(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ, RTSX_CLK_LOW_FREQ); 1779 RTSX_WRITE(sc, RTSX_CARD_CLK_SOURCE, 1780 RTSX_CRC_FIX_CLK | RTSX_SD30_VAR_CLK0 | RTSX_SAMPLE_VAR_CLK1); 1781 RTSX_CLR(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ); 1782 1783 RTSX_BITOP(sc, RTSX_SD_PUSH_POINT_CTL, 1784 RTSX_SD20_TX_SEL_MASK, RTSX_SD20_TX_14_AHEAD); 1785 RTSX_BITOP(sc, RTSX_SD_SAMPLE_POINT_CTL, 1786 RTSX_SD20_RX_SEL_MASK, RTSX_SD20_RX_14_DELAY); 1787 break; 1788 default: 1789 RTSX_BITOP(sc, RTSX_SD_CFG1, RTSX_SD_MODE_MASK, RTSX_SD20_MODE); 1790 RTSX_BITOP(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ, RTSX_CLK_LOW_FREQ); 1791 RTSX_WRITE(sc, RTSX_CARD_CLK_SOURCE, 1792 RTSX_CRC_FIX_CLK | RTSX_SD30_VAR_CLK0 | RTSX_SAMPLE_VAR_CLK1); 1793 RTSX_CLR(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ); 1794 1795 RTSX_WRITE(sc, RTSX_SD_PUSH_POINT_CTL, RTSX_SD20_TX_NEG_EDGE); 1796 RTSX_BITOP(sc, RTSX_SD_SAMPLE_POINT_CTL, 1797 RTSX_SD20_RX_SEL_MASK, RTSX_SD20_RX_POS_EDGE); 1798 break; 1799 } 1800 1801 return (0); 1802 } 1803 1804 /* 1805 * Set or change SDCLK frequency or disable the SD clock. 1806 * Return zero on success. 1807 */ 1808 static int 1809 rtsx_set_sd_clock(struct rtsx_softc *sc, uint32_t freq) 1810 { 1811 uint8_t clk; 1812 uint8_t clk_divider, n, div, mcu; 1813 int error = 0; 1814 1815 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 1816 device_printf(sc->rtsx_dev, "rtsx_set_sd_clock(%u)\n", freq); 1817 1818 if (freq == RTSX_SDCLK_OFF) { 1819 error = rtsx_stop_sd_clock(sc); 1820 return error; 1821 } 1822 1823 sc->rtsx_ssc_depth = RTSX_SSC_DEPTH_500K; 1824 sc->rtsx_discovery_mode = (freq <= 1000000) ? true : false; 1825 1826 if (sc->rtsx_discovery_mode) { 1827 /* We use 250k(around) here, in discovery stage. */ 1828 clk_divider = RTSX_CLK_DIVIDE_128; 1829 freq = 30000000; 1830 } else { 1831 clk_divider = RTSX_CLK_DIVIDE_0; 1832 } 1833 RTSX_BITOP(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK, clk_divider); 1834 1835 freq /= 1000000; 1836 if (sc->rtsx_discovery_mode || !sc->rtsx_double_clk) 1837 clk = freq; 1838 else 1839 clk = freq * 2; 1840 1841 switch (sc->rtsx_device_id) { 1842 case RTSX_RTL8402: 1843 case RTSX_RTL8411: 1844 case RTSX_RTL8411B: 1845 n = clk * 4 / 5 - 2; 1846 break; 1847 default: 1848 n = clk - 2; 1849 break; 1850 } 1851 if ((clk <= 2) || (n > RTSX_MAX_DIV_N)) 1852 return (MMC_ERR_INVALID); 1853 1854 mcu = 125 / clk + 3; 1855 if (mcu > 15) 1856 mcu = 15; 1857 1858 /* Make sure that the SSC clock div_n is not less than RTSX_MIN_DIV_N. */ 1859 div = RTSX_CLK_DIV_1; 1860 while ((n < RTSX_MIN_DIV_N) && (div < RTSX_CLK_DIV_8)) { 1861 switch (sc->rtsx_device_id) { 1862 case RTSX_RTL8402: 1863 case RTSX_RTL8411: 1864 case RTSX_RTL8411B: 1865 n = (((n + 2) * 5 / 4) * 2) * 4 / 5 - 2; 1866 break; 1867 default: 1868 n = (n + 2) * 2 - 2; 1869 break; 1870 } 1871 div++; 1872 } 1873 1874 if (sc->rtsx_double_clk && sc->rtsx_ssc_depth > 1) 1875 sc->rtsx_ssc_depth -= 1; 1876 1877 if (div > RTSX_CLK_DIV_1) { 1878 if (sc->rtsx_ssc_depth > (div - 1)) 1879 sc->rtsx_ssc_depth -= (div - 1); 1880 else 1881 sc->rtsx_ssc_depth = RTSX_SSC_DEPTH_4M; 1882 } 1883 1884 /* Enable SD clock. */ 1885 error = rtsx_switch_sd_clock(sc, clk, n, div, mcu); 1886 1887 return (error); 1888 } 1889 1890 static int 1891 rtsx_stop_sd_clock(struct rtsx_softc *sc) 1892 { 1893 RTSX_CLR(sc, RTSX_CARD_CLK_EN, RTSX_CARD_CLK_EN_ALL); 1894 RTSX_SET(sc, RTSX_SD_BUS_STAT, RTSX_SD_CLK_FORCE_STOP); 1895 1896 return (0); 1897 } 1898 1899 static int 1900 rtsx_switch_sd_clock(struct rtsx_softc *sc, uint8_t clk, uint8_t n, uint8_t div, uint8_t mcu) 1901 { 1902 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) { 1903 device_printf(sc->rtsx_dev, "rtsx_switch_sd_clock() - discovery-mode is %s, ssc_depth: %d\n", 1904 (sc->rtsx_discovery_mode) ? "true" : "false", sc->rtsx_ssc_depth); 1905 device_printf(sc->rtsx_dev, "rtsx_switch_sd_clock() - clk: %d, n: %d, div: %d, mcu: %d\n", 1906 clk, n, div, mcu); 1907 } 1908 1909 RTSX_BITOP(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ, RTSX_CLK_LOW_FREQ); 1910 RTSX_WRITE(sc, RTSX_CLK_DIV, (div << 4) | mcu); 1911 RTSX_CLR(sc, RTSX_SSC_CTL1, RTSX_RSTB); 1912 RTSX_BITOP(sc, RTSX_SSC_CTL2, RTSX_SSC_DEPTH_MASK, sc->rtsx_ssc_depth); 1913 RTSX_WRITE(sc, RTSX_SSC_DIV_N_0, n); 1914 RTSX_BITOP(sc, RTSX_SSC_CTL1, RTSX_RSTB, RTSX_RSTB); 1915 if (sc->rtsx_vpclk) { 1916 RTSX_CLR(sc, RTSX_SD_VPCLK0_CTL, RTSX_PHASE_NOT_RESET); 1917 RTSX_BITOP(sc, RTSX_SD_VPCLK0_CTL, RTSX_PHASE_NOT_RESET, RTSX_PHASE_NOT_RESET); 1918 } 1919 1920 /* Wait SSC clock stable. */ 1921 DELAY(200); 1922 1923 RTSX_CLR(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ); 1924 1925 return (0); 1926 } 1927 1928 #ifndef MMCCAM 1929 static void 1930 rtsx_sd_change_tx_phase(struct rtsx_softc *sc, uint8_t sample_point) 1931 { 1932 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 1933 device_printf(sc->rtsx_dev, "rtsx_sd_change_tx_phase() - sample_point: %d\n", sample_point); 1934 1935 rtsx_write(sc, RTSX_CLK_CTL, RTSX_CHANGE_CLK, RTSX_CHANGE_CLK); 1936 rtsx_write(sc, RTSX_SD_VPCLK0_CTL, RTSX_PHASE_SELECT_MASK, sample_point); 1937 rtsx_write(sc, RTSX_SD_VPCLK0_CTL, RTSX_PHASE_NOT_RESET, 0); 1938 rtsx_write(sc, RTSX_SD_VPCLK0_CTL, RTSX_PHASE_NOT_RESET, RTSX_PHASE_NOT_RESET); 1939 rtsx_write(sc, RTSX_CLK_CTL, RTSX_CHANGE_CLK, 0); 1940 rtsx_write(sc, RTSX_SD_CFG1, RTSX_SD_ASYNC_FIFO_NOT_RST, 0); 1941 } 1942 1943 static void 1944 rtsx_sd_change_rx_phase(struct rtsx_softc *sc, uint8_t sample_point) 1945 { 1946 if (sc->rtsx_debug_mask & RTSX_DEBUG_TUNING) 1947 device_printf(sc->rtsx_dev, "rtsx_sd_change_rx_phase() - sample_point: %d\n", sample_point); 1948 1949 rtsx_write(sc, RTSX_CLK_CTL, RTSX_CHANGE_CLK, RTSX_CHANGE_CLK); 1950 rtsx_write(sc, RTSX_SD_VPCLK1_CTL, RTSX_PHASE_SELECT_MASK, sample_point); 1951 rtsx_write(sc, RTSX_SD_VPCLK1_CTL, RTSX_PHASE_NOT_RESET, 0); 1952 rtsx_write(sc, RTSX_SD_VPCLK1_CTL, RTSX_PHASE_NOT_RESET, RTSX_PHASE_NOT_RESET); 1953 rtsx_write(sc, RTSX_CLK_CTL, RTSX_CHANGE_CLK, 0); 1954 rtsx_write(sc, RTSX_SD_CFG1, RTSX_SD_ASYNC_FIFO_NOT_RST, 0); 1955 } 1956 1957 static void 1958 rtsx_sd_tuning_rx_phase(struct rtsx_softc *sc, uint32_t *phase_map) 1959 { 1960 uint32_t raw_phase_map = 0; 1961 int i; 1962 int error; 1963 1964 for (i = 0; i < RTSX_RX_PHASE_MAX; i++) { 1965 error = rtsx_sd_tuning_rx_cmd(sc, (uint8_t)i); 1966 if (error == 0) 1967 raw_phase_map |= 1 << i; 1968 } 1969 if (phase_map != NULL) 1970 *phase_map = raw_phase_map; 1971 } 1972 1973 static int 1974 rtsx_sd_tuning_rx_cmd(struct rtsx_softc *sc, uint8_t sample_point) 1975 { 1976 struct mmc_request req = {}; 1977 struct mmc_command cmd = {}; 1978 int error = 0; 1979 1980 cmd.opcode = MMC_SEND_TUNING_BLOCK; 1981 cmd.arg = 0; 1982 req.cmd = &cmd; 1983 1984 RTSX_LOCK(sc); 1985 1986 sc->rtsx_req = &req; 1987 1988 rtsx_sd_change_rx_phase(sc, sample_point); 1989 1990 rtsx_write(sc, RTSX_SD_CFG3, RTSX_SD_RSP_80CLK_TIMEOUT_EN, 1991 RTSX_SD_RSP_80CLK_TIMEOUT_EN); 1992 1993 rtsx_init_cmd(sc, &cmd); 1994 rtsx_set_cmd_data_len(sc, 1, 0x40); 1995 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 0xff, 1996 RTSX_SD_CALCULATE_CRC7 | RTSX_SD_CHECK_CRC16 | 1997 RTSX_SD_NO_WAIT_BUSY_END | RTSX_SD_CHECK_CRC7 | RTSX_SD_RSP_LEN_6); 1998 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 1999 0xff, RTSX_TM_AUTO_TUNING | RTSX_SD_TRANSFER_START); 2000 rtsx_push_cmd(sc, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, 2001 RTSX_SD_TRANSFER_END, RTSX_SD_TRANSFER_END); 2002 2003 /* Set interrupt post processing */ 2004 sc->rtsx_intr_trans_ok = rtsx_sd_tuning_rx_cmd_wakeup; 2005 sc->rtsx_intr_trans_ko = rtsx_sd_tuning_rx_cmd_wakeup; 2006 2007 /* Run the command queue. */ 2008 rtsx_send_cmd(sc); 2009 2010 error = rtsx_sd_tuning_rx_cmd_wait(sc, &cmd); 2011 2012 if (error) { 2013 if (sc->rtsx_debug_mask & RTSX_DEBUG_TUNING) 2014 device_printf(sc->rtsx_dev, "rtsx_sd_tuning_rx_cmd() - error: %d\n", error); 2015 rtsx_sd_wait_data_idle(sc); 2016 rtsx_clear_error(sc); 2017 } 2018 rtsx_write(sc, RTSX_SD_CFG3, RTSX_SD_RSP_80CLK_TIMEOUT_EN, 0); 2019 2020 sc->rtsx_req = NULL; 2021 2022 RTSX_UNLOCK(sc); 2023 2024 return (error); 2025 } 2026 2027 static int 2028 rtsx_sd_tuning_rx_cmd_wait(struct rtsx_softc *sc, struct mmc_command *cmd) 2029 { 2030 int status; 2031 int mask = RTSX_TRANS_OK_INT | RTSX_TRANS_FAIL_INT; 2032 2033 status = sc->rtsx_intr_status & mask; 2034 while (status == 0) { 2035 if (msleep(&sc->rtsx_intr_status, &sc->rtsx_mtx, 0, "rtsxintr", sc->rtsx_timeout_cmd) == EWOULDBLOCK) { 2036 cmd->error = MMC_ERR_TIMEOUT; 2037 return (MMC_ERR_TIMEOUT); 2038 } 2039 status = sc->rtsx_intr_status & mask; 2040 } 2041 return (cmd->error); 2042 } 2043 2044 static void 2045 rtsx_sd_tuning_rx_cmd_wakeup(struct rtsx_softc *sc) 2046 { 2047 wakeup(&sc->rtsx_intr_status); 2048 } 2049 2050 static void 2051 rtsx_sd_wait_data_idle(struct rtsx_softc *sc) 2052 { 2053 int i; 2054 uint8_t val; 2055 2056 for (i = 0; i < 100; i++) { 2057 rtsx_read(sc, RTSX_SD_DATA_STATE, &val); 2058 if (val & RTSX_SD_DATA_IDLE) 2059 return; 2060 DELAY(100); 2061 } 2062 } 2063 2064 static uint8_t 2065 rtsx_sd_search_final_rx_phase(struct rtsx_softc *sc, uint32_t phase_map) 2066 { 2067 int start = 0, len = 0; 2068 int start_final = 0, len_final = 0; 2069 uint8_t final_phase = 0xff; 2070 2071 while (start < RTSX_RX_PHASE_MAX) { 2072 len = rtsx_sd_get_rx_phase_len(phase_map, start); 2073 if (len_final < len) { 2074 start_final = start; 2075 len_final = len; 2076 } 2077 start += len ? len : 1; 2078 } 2079 2080 final_phase = (start_final + len_final / 2) % RTSX_RX_PHASE_MAX; 2081 2082 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 2083 device_printf(sc->rtsx_dev, 2084 "rtsx_sd_search_final_rx_phase() - phase_map: %x, start_final: %d, len_final: %d, final_phase: %d\n", 2085 phase_map, start_final, len_final, final_phase); 2086 2087 return final_phase; 2088 } 2089 2090 static int 2091 rtsx_sd_get_rx_phase_len(uint32_t phase_map, int start_bit) 2092 { 2093 int i; 2094 2095 for (i = 0; i < RTSX_RX_PHASE_MAX; i++) { 2096 if ((phase_map & (1 << (start_bit + i) % RTSX_RX_PHASE_MAX)) == 0) 2097 return i; 2098 } 2099 return RTSX_RX_PHASE_MAX; 2100 } 2101 #endif /* !MMCCAM */ 2102 2103 #if 0 /* For led */ 2104 static int 2105 rtsx_led_enable(struct rtsx_softc *sc) 2106 { 2107 switch (sc->rtsx_device_id) { 2108 case RTSX_RTS5209: 2109 RTSX_CLR(sc, RTSX_CARD_GPIO, RTSX_CARD_GPIO_LED_OFF); 2110 RTSX_WRITE(sc, RTSX_CARD_AUTO_BLINK, 2111 RTSX_LED_BLINK_EN | RTSX_LED_BLINK_SPEED); 2112 break; 2113 case RTSX_RTL8411B: 2114 RTSX_CLR(sc, RTSX_GPIO_CTL, 0x01); 2115 RTSX_WRITE(sc, RTSX_CARD_AUTO_BLINK, 2116 RTSX_LED_BLINK_EN | RTSX_LED_BLINK_SPEED); 2117 break; 2118 default: 2119 RTSX_SET(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON); 2120 RTSX_SET(sc, RTSX_OLT_LED_CTL, RTSX_OLT_LED_AUTOBLINK); 2121 break; 2122 } 2123 2124 return (0); 2125 } 2126 2127 static int 2128 rtsx_led_disable(struct rtsx_softc *sc) 2129 { 2130 switch (sc->rtsx_device_id) { 2131 case RTSX_RTS5209: 2132 RTSX_CLR(sc, RTSX_CARD_AUTO_BLINK, RTSX_LED_BLINK_EN); 2133 RTSX_WRITE(sc, RTSX_CARD_GPIO, RTSX_CARD_GPIO_LED_OFF); 2134 break; 2135 case RTSX_RTL8411B: 2136 RTSX_CLR(sc, RTSX_CARD_AUTO_BLINK, RTSX_LED_BLINK_EN); 2137 RTSX_SET(sc, RTSX_GPIO_CTL, 0x01); 2138 break; 2139 default: 2140 RTSX_CLR(sc, RTSX_OLT_LED_CTL, RTSX_OLT_LED_AUTOBLINK); 2141 RTSX_CLR(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON); 2142 break; 2143 } 2144 2145 return (0); 2146 } 2147 #endif /* For led */ 2148 2149 static uint8_t 2150 rtsx_response_type(uint16_t mmc_rsp) 2151 { 2152 int i; 2153 struct rsp_type { 2154 uint16_t mmc_rsp; 2155 uint8_t rtsx_rsp; 2156 } rsp_types[] = { 2157 { MMC_RSP_NONE, RTSX_SD_RSP_TYPE_R0 }, 2158 { MMC_RSP_R1, RTSX_SD_RSP_TYPE_R1 }, 2159 { MMC_RSP_R1B, RTSX_SD_RSP_TYPE_R1B }, 2160 { MMC_RSP_R2, RTSX_SD_RSP_TYPE_R2 }, 2161 { MMC_RSP_R3, RTSX_SD_RSP_TYPE_R3 }, 2162 { MMC_RSP_R4, RTSX_SD_RSP_TYPE_R4 }, 2163 { MMC_RSP_R5, RTSX_SD_RSP_TYPE_R5 }, 2164 { MMC_RSP_R6, RTSX_SD_RSP_TYPE_R6 }, 2165 { MMC_RSP_R7, RTSX_SD_RSP_TYPE_R7 } 2166 }; 2167 2168 for (i = 0; i < nitems(rsp_types); i++) { 2169 if (mmc_rsp == rsp_types[i].mmc_rsp) 2170 return (rsp_types[i].rtsx_rsp); 2171 } 2172 2173 return (0); 2174 } 2175 2176 /* 2177 * Init command buffer with SD command index and argument. 2178 */ 2179 static void 2180 rtsx_init_cmd(struct rtsx_softc *sc, struct mmc_command *cmd) 2181 { 2182 sc->rtsx_cmd_index = 0; 2183 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CMD0, 2184 0xff, RTSX_SD_CMD_START | cmd->opcode); 2185 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CMD1, 2186 0xff, cmd->arg >> 24); 2187 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CMD2, 2188 0xff, cmd->arg >> 16); 2189 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CMD3, 2190 0xff, cmd->arg >> 8); 2191 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CMD4, 2192 0xff, cmd->arg); 2193 } 2194 2195 /* 2196 * Append a properly encoded host command to the host command buffer. 2197 */ 2198 static void 2199 rtsx_push_cmd(struct rtsx_softc *sc, uint8_t cmd, uint16_t reg, 2200 uint8_t mask, uint8_t data) 2201 { 2202 KASSERT(sc->rtsx_cmd_index < RTSX_HOSTCMD_MAX, 2203 ("rtsx: Too many host commands (%d)\n", sc->rtsx_cmd_index)); 2204 2205 uint32_t *cmd_buffer = (uint32_t *)(sc->rtsx_cmd_dmamem); 2206 cmd_buffer[sc->rtsx_cmd_index++] = 2207 htole32((uint32_t)(cmd & 0x3) << 30) | 2208 ((uint32_t)(reg & 0x3fff) << 16) | 2209 ((uint32_t)(mask) << 8) | 2210 ((uint32_t)data); 2211 } 2212 2213 /* 2214 * Queue commands to configure data transfer size. 2215 */ 2216 static void 2217 rtsx_set_cmd_data_len(struct rtsx_softc *sc, uint16_t block_cnt, uint16_t byte_cnt) 2218 { 2219 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BLOCK_CNT_L, 2220 0xff, block_cnt & 0xff); 2221 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BLOCK_CNT_H, 2222 0xff, block_cnt >> 8); 2223 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BYTE_CNT_L, 2224 0xff, byte_cnt & 0xff); 2225 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BYTE_CNT_H, 2226 0xff, byte_cnt >> 8); 2227 } 2228 2229 /* 2230 * Run the command queue. 2231 */ 2232 static void 2233 rtsx_send_cmd(struct rtsx_softc *sc) 2234 { 2235 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 2236 device_printf(sc->rtsx_dev, "rtsx_send_cmd()\n"); 2237 2238 sc->rtsx_intr_status = 0; 2239 2240 /* Sync command DMA buffer. */ 2241 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_PREREAD); 2242 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_PREWRITE); 2243 2244 /* Tell the chip where the command buffer is and run the commands. */ 2245 WRITE4(sc, RTSX_HCBAR, (uint32_t)sc->rtsx_cmd_buffer); 2246 WRITE4(sc, RTSX_HCBCTLR, 2247 ((sc->rtsx_cmd_index * 4) & 0x00ffffff) | RTSX_START_CMD | RTSX_HW_AUTO_RSP); 2248 } 2249 2250 /* 2251 * Stop previous command. 2252 */ 2253 static void 2254 rtsx_stop_cmd(struct rtsx_softc *sc) 2255 { 2256 /* Stop command transfer. */ 2257 WRITE4(sc, RTSX_HCBCTLR, RTSX_STOP_CMD); 2258 2259 /* Stop DMA transfer. */ 2260 WRITE4(sc, RTSX_HDBCTLR, RTSX_STOP_DMA); 2261 2262 switch (sc->rtsx_device_id) { 2263 case RTSX_RTS5260: 2264 rtsx_write(sc, RTSX_RTS5260_DMA_RST_CTL_0, 2265 RTSX_RTS5260_DMA_RST | RTSX_RTS5260_ADMA3_RST, 2266 RTSX_RTS5260_DMA_RST | RTSX_RTS5260_ADMA3_RST); 2267 rtsx_write(sc, RTSX_RBCTL, RTSX_RB_FLUSH, RTSX_RB_FLUSH); 2268 break; 2269 } 2270 2271 rtsx_write(sc, RTSX_DMACTL, RTSX_DMA_RST, RTSX_DMA_RST); 2272 2273 rtsx_write(sc, RTSX_RBCTL, RTSX_RB_FLUSH, RTSX_RB_FLUSH); 2274 } 2275 2276 /* 2277 * Clear error. 2278 */ 2279 static void 2280 rtsx_clear_error(struct rtsx_softc *sc) 2281 { 2282 /* Clear error. */ 2283 rtsx_write(sc, RTSX_CARD_STOP, RTSX_SD_STOP | RTSX_SD_CLR_ERR, 2284 RTSX_SD_STOP | RTSX_SD_CLR_ERR); 2285 } 2286 2287 /* 2288 * Signal end of request to mmc/mmcsd. 2289 */ 2290 static void 2291 rtsx_req_done(struct rtsx_softc *sc) 2292 { 2293 #ifdef MMCCAM 2294 union ccb *ccb; 2295 #endif /* MMCCAM */ 2296 struct mmc_request *req; 2297 2298 req = sc->rtsx_req; 2299 if (req->cmd->error == MMC_ERR_NONE) { 2300 if (req->cmd->opcode == MMC_READ_SINGLE_BLOCK || 2301 req->cmd->opcode == MMC_READ_MULTIPLE_BLOCK) 2302 sc->rtsx_read_count++; 2303 else if (req->cmd->opcode == MMC_WRITE_BLOCK || 2304 req->cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK) 2305 sc->rtsx_write_count++; 2306 } else { 2307 rtsx_clear_error(sc); 2308 } 2309 callout_stop(&sc->rtsx_timeout_callout); 2310 sc->rtsx_req = NULL; 2311 #ifdef MMCCAM 2312 ccb = sc->rtsx_ccb; 2313 sc->rtsx_ccb = NULL; 2314 ccb->ccb_h.status = (req->cmd->error == 0 ? CAM_REQ_CMP : CAM_REQ_CMP_ERR); 2315 xpt_done(ccb); 2316 #else /* !MMCCAM */ 2317 req->done(req); 2318 #endif /* MMCCAM */ 2319 } 2320 2321 /* 2322 * Send request. 2323 */ 2324 static int 2325 rtsx_send_req(struct rtsx_softc *sc, struct mmc_command *cmd) 2326 { 2327 uint8_t rsp_type; 2328 uint16_t reg; 2329 2330 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 2331 device_printf(sc->rtsx_dev, "rtsx_send_req() - CMD%d\n", cmd->opcode); 2332 2333 /* Convert response type. */ 2334 rsp_type = rtsx_response_type(cmd->flags & MMC_RSP_MASK); 2335 if (rsp_type == 0) { 2336 device_printf(sc->rtsx_dev, "Unknown rsp_type: 0x%lx\n", (cmd->flags & MMC_RSP_MASK)); 2337 cmd->error = MMC_ERR_INVALID; 2338 return (MMC_ERR_INVALID); 2339 } 2340 2341 rtsx_init_cmd(sc, cmd); 2342 2343 /* Queue command to set response type. */ 2344 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 0xff, rsp_type); 2345 2346 /* Use the ping-pong buffer (cmd buffer) for commands which do not transfer data. */ 2347 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_CARD_DATA_SOURCE, 2348 0x01, RTSX_PINGPONG_BUFFER); 2349 2350 /* Queue commands to perform SD transfer. */ 2351 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 2352 0xff, RTSX_TM_CMD_RSP | RTSX_SD_TRANSFER_START); 2353 rtsx_push_cmd(sc, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, 2354 RTSX_SD_TRANSFER_END|RTSX_SD_STAT_IDLE, 2355 RTSX_SD_TRANSFER_END|RTSX_SD_STAT_IDLE); 2356 2357 /* If needed queue commands to read back card status response. */ 2358 if (rsp_type == RTSX_SD_RSP_TYPE_R2) { 2359 /* Read data from ping-pong buffer. */ 2360 for (reg = RTSX_PPBUF_BASE2; reg < RTSX_PPBUF_BASE2 + 16; reg++) 2361 rtsx_push_cmd(sc, RTSX_READ_REG_CMD, reg, 0, 0); 2362 } else if (rsp_type != RTSX_SD_RSP_TYPE_R0) { 2363 /* Read data from SD_CMDx registers. */ 2364 for (reg = RTSX_SD_CMD0; reg <= RTSX_SD_CMD4; reg++) 2365 rtsx_push_cmd(sc, RTSX_READ_REG_CMD, reg, 0, 0); 2366 } 2367 rtsx_push_cmd(sc, RTSX_READ_REG_CMD, RTSX_SD_STAT1, 0, 0); 2368 2369 /* Set transfer OK function. */ 2370 if (sc->rtsx_intr_trans_ok == NULL) 2371 sc->rtsx_intr_trans_ok = rtsx_ret_resp; 2372 2373 /* Run the command queue. */ 2374 rtsx_send_cmd(sc); 2375 2376 return (0); 2377 } 2378 2379 /* 2380 * Return response of previous command (case cmd->data == NULL) and complete resquest. 2381 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2382 */ 2383 static void 2384 rtsx_ret_resp(struct rtsx_softc *sc) 2385 { 2386 struct mmc_command *cmd; 2387 2388 cmd = sc->rtsx_req->cmd; 2389 rtsx_set_resp(sc, cmd); 2390 rtsx_req_done(sc); 2391 } 2392 2393 /* 2394 * Set response of previous command. 2395 */ 2396 static void 2397 rtsx_set_resp(struct rtsx_softc *sc, struct mmc_command *cmd) 2398 { 2399 uint8_t rsp_type; 2400 2401 rsp_type = rtsx_response_type(cmd->flags & MMC_RSP_MASK); 2402 2403 /* Sync command DMA buffer. */ 2404 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTREAD); 2405 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTWRITE); 2406 2407 /* Copy card response into mmc response buffer. */ 2408 if (ISSET(cmd->flags, MMC_RSP_PRESENT)) { 2409 uint32_t *cmd_buffer = (uint32_t *)(sc->rtsx_cmd_dmamem); 2410 2411 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) { 2412 device_printf(sc->rtsx_dev, "cmd_buffer: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", 2413 cmd_buffer[0], cmd_buffer[1], cmd_buffer[2], cmd_buffer[3], cmd_buffer[4]); 2414 } 2415 2416 if (rsp_type == RTSX_SD_RSP_TYPE_R2) { 2417 /* First byte is CHECK_REG_CMD return value, skip it. */ 2418 unsigned char *ptr = (unsigned char *)cmd_buffer + 1; 2419 int i; 2420 2421 /* 2422 * The controller offloads the last byte {CRC-7, end bit 1} 2423 * of response type R2. Assign dummy CRC, 0, and end bit to this 2424 * byte (ptr[16], goes into the LSB of resp[3] later). 2425 */ 2426 ptr[16] = 0x01; 2427 /* The second byte is the status of response, skip it. */ 2428 for (i = 0; i < 4; i++) 2429 cmd->resp[i] = be32dec(ptr + 1 + i * 4); 2430 } else { 2431 /* 2432 * First byte is CHECK_REG_CMD return value, second 2433 * one is the command op code -- we skip those. 2434 */ 2435 cmd->resp[0] = 2436 ((be32toh(cmd_buffer[0]) & 0x0000ffff) << 16) | 2437 ((be32toh(cmd_buffer[1]) & 0xffff0000) >> 16); 2438 } 2439 2440 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 2441 device_printf(sc->rtsx_dev, "cmd->resp: 0x%08x 0x%08x 0x%08x 0x%08x\n", 2442 cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); 2443 } 2444 } 2445 2446 /* 2447 * Use the ping-pong buffer (cmd buffer) for transfer <= 512 bytes. 2448 */ 2449 static int 2450 rtsx_xfer_short(struct rtsx_softc *sc, struct mmc_command *cmd) 2451 { 2452 int read; 2453 2454 if (cmd->data == NULL || cmd->data->len == 0) { 2455 cmd->error = MMC_ERR_INVALID; 2456 return (MMC_ERR_INVALID); 2457 } 2458 cmd->data->xfer_len = (cmd->data->len > RTSX_MAX_DATA_BLKLEN) ? 2459 RTSX_MAX_DATA_BLKLEN : cmd->data->len; 2460 2461 read = ISSET(cmd->data->flags, MMC_DATA_READ); 2462 2463 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 2464 device_printf(sc->rtsx_dev, "rtsx_xfer_short() - %s xfer: %ld bytes with block size %ld\n", 2465 read ? "Read" : "Write", 2466 (unsigned long)cmd->data->len, (unsigned long)cmd->data->xfer_len); 2467 2468 if (cmd->data->len > 512) { 2469 device_printf(sc->rtsx_dev, "rtsx_xfer_short() - length too large: %ld > 512\n", 2470 (unsigned long)cmd->data->len); 2471 cmd->error = MMC_ERR_INVALID; 2472 return (MMC_ERR_INVALID); 2473 } 2474 2475 if (read) { 2476 if (sc->rtsx_discovery_mode) 2477 rtsx_write(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK, RTSX_CLK_DIVIDE_0); 2478 2479 rtsx_init_cmd(sc, cmd); 2480 2481 /* Queue commands to configure data transfer size. */ 2482 rtsx_set_cmd_data_len(sc, cmd->data->len / cmd->data->xfer_len, cmd->data->xfer_len); 2483 2484 /* From Linux: rtsx_pci_sdmmc.c sd_read_data(). */ 2485 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 0xff, 2486 RTSX_SD_CALCULATE_CRC7 | RTSX_SD_CHECK_CRC16 | 2487 RTSX_SD_NO_WAIT_BUSY_END | RTSX_SD_CHECK_CRC7 | RTSX_SD_RSP_LEN_6); 2488 2489 /* Use the ping-pong buffer (cmd buffer). */ 2490 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_CARD_DATA_SOURCE, 2491 0x01, RTSX_PINGPONG_BUFFER); 2492 2493 /* Queue commands to perform SD transfer. */ 2494 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 2495 0xff, RTSX_TM_NORMAL_READ | RTSX_SD_TRANSFER_START); 2496 rtsx_push_cmd(sc, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, 2497 RTSX_SD_TRANSFER_END, RTSX_SD_TRANSFER_END); 2498 2499 /* Set transfer OK function. */ 2500 sc->rtsx_intr_trans_ok = rtsx_ask_ppbuf_part1; 2501 2502 /* Run the command queue. */ 2503 rtsx_send_cmd(sc); 2504 } else { 2505 /* Set transfer OK function. */ 2506 sc->rtsx_intr_trans_ok = rtsx_put_ppbuf_part1; 2507 2508 /* Run the command queue. */ 2509 rtsx_send_req(sc, cmd); 2510 } 2511 2512 return (0); 2513 } 2514 2515 /* 2516 * Use the ping-pong buffer (cmd buffer) for the transfer - first part <= 256 bytes. 2517 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2518 */ 2519 static void 2520 rtsx_ask_ppbuf_part1(struct rtsx_softc *sc) 2521 { 2522 struct mmc_command *cmd; 2523 uint16_t reg = RTSX_PPBUF_BASE2; 2524 int len; 2525 int i; 2526 2527 cmd = sc->rtsx_req->cmd; 2528 len = (cmd->data->len > RTSX_HOSTCMD_MAX) ? RTSX_HOSTCMD_MAX : cmd->data->len; 2529 2530 sc->rtsx_cmd_index = 0; 2531 for (i = 0; i < len; i++) { 2532 rtsx_push_cmd(sc, RTSX_READ_REG_CMD, reg++, 0, 0); 2533 } 2534 2535 /* Set transfer OK function. */ 2536 sc->rtsx_intr_trans_ok = rtsx_get_ppbuf_part1; 2537 2538 /* Run the command queue. */ 2539 rtsx_send_cmd(sc); 2540 } 2541 2542 /* 2543 * Get the data from the ping-pong buffer (cmd buffer) - first part <= 256 bytes. 2544 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2545 */ 2546 static void 2547 rtsx_get_ppbuf_part1(struct rtsx_softc *sc) 2548 { 2549 struct mmc_command *cmd; 2550 uint8_t *ptr; 2551 int len; 2552 2553 cmd = sc->rtsx_req->cmd; 2554 ptr = cmd->data->data; 2555 len = (cmd->data->len > RTSX_HOSTCMD_MAX) ? RTSX_HOSTCMD_MAX : cmd->data->len; 2556 2557 /* Sync command DMA buffer. */ 2558 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTREAD); 2559 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTWRITE); 2560 2561 memcpy(ptr, sc->rtsx_cmd_dmamem, len); 2562 2563 len = (cmd->data->len > RTSX_HOSTCMD_MAX) ? cmd->data->len - RTSX_HOSTCMD_MAX : 0; 2564 2565 /* Use the ping-pong buffer (cmd buffer) for the transfer - second part > 256 bytes. */ 2566 if (len > 0) { 2567 uint16_t reg = RTSX_PPBUF_BASE2 + RTSX_HOSTCMD_MAX; 2568 int i; 2569 2570 sc->rtsx_cmd_index = 0; 2571 for (i = 0; i < len; i++) { 2572 rtsx_push_cmd(sc, RTSX_READ_REG_CMD, reg++, 0, 0); 2573 } 2574 2575 /* Set transfer OK function. */ 2576 sc->rtsx_intr_trans_ok = rtsx_get_ppbuf_part2; 2577 2578 /* Run the command queue. */ 2579 rtsx_send_cmd(sc); 2580 } else { 2581 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD && cmd->opcode == ACMD_SEND_SCR) { 2582 uint8_t *ptr = cmd->data->data; 2583 device_printf(sc->rtsx_dev, "SCR: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n", 2584 ptr[0], ptr[1], ptr[2], ptr[3], 2585 ptr[4], ptr[5], ptr[6], ptr[7]); 2586 } 2587 2588 if (sc->rtsx_discovery_mode) 2589 rtsx_write(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK, RTSX_CLK_DIVIDE_128); 2590 2591 rtsx_req_done(sc); 2592 } 2593 } 2594 2595 /* 2596 * Get the data from the ping-pong buffer (cmd buffer) - second part > 256 bytes. 2597 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2598 */ 2599 static void 2600 rtsx_get_ppbuf_part2(struct rtsx_softc *sc) 2601 { 2602 struct mmc_command *cmd; 2603 uint8_t *ptr; 2604 int len; 2605 2606 cmd = sc->rtsx_req->cmd; 2607 ptr = cmd->data->data; 2608 ptr += RTSX_HOSTCMD_MAX; 2609 len = cmd->data->len - RTSX_HOSTCMD_MAX; 2610 2611 /* Sync command DMA buffer. */ 2612 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTREAD); 2613 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTWRITE); 2614 2615 memcpy(ptr, sc->rtsx_cmd_dmamem, len); 2616 2617 if (sc->rtsx_discovery_mode) 2618 rtsx_write(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK, RTSX_CLK_DIVIDE_128); 2619 2620 rtsx_req_done(sc); 2621 } 2622 2623 /* 2624 * Use the ping-pong buffer (cmd buffer) for transfer - first part <= 256 bytes. 2625 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2626 */ 2627 static void 2628 rtsx_put_ppbuf_part1(struct rtsx_softc *sc) 2629 { 2630 struct mmc_command *cmd; 2631 uint16_t reg = RTSX_PPBUF_BASE2; 2632 uint8_t *ptr; 2633 int len; 2634 int i; 2635 2636 cmd = sc->rtsx_req->cmd; 2637 ptr = cmd->data->data; 2638 len = (cmd->data->len > RTSX_HOSTCMD_MAX) ? RTSX_HOSTCMD_MAX : cmd->data->len; 2639 2640 rtsx_set_resp(sc, cmd); 2641 2642 sc->rtsx_cmd_index = 0; 2643 for (i = 0; i < len; i++) { 2644 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, reg++, 0xff, *ptr); 2645 ptr++; 2646 } 2647 2648 /* Set transfer OK function. */ 2649 if (cmd->data->len > RTSX_HOSTCMD_MAX) 2650 sc->rtsx_intr_trans_ok = rtsx_put_ppbuf_part2; 2651 else 2652 sc->rtsx_intr_trans_ok = rtsx_write_ppbuf; 2653 2654 /* Run the command queue. */ 2655 rtsx_send_cmd(sc); 2656 } 2657 2658 /* 2659 * Use the ping-pong buffer (cmd buffer) for transfer - second part > 256 bytes. 2660 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2661 */ 2662 static void 2663 rtsx_put_ppbuf_part2(struct rtsx_softc *sc) 2664 { 2665 struct mmc_command *cmd; 2666 uint16_t reg = RTSX_PPBUF_BASE2 + RTSX_HOSTCMD_MAX; 2667 uint8_t *ptr; 2668 int len; 2669 int i; 2670 2671 cmd = sc->rtsx_req->cmd; 2672 ptr = cmd->data->data; 2673 ptr += RTSX_HOSTCMD_MAX; 2674 len = cmd->data->len - RTSX_HOSTCMD_MAX; 2675 2676 sc->rtsx_cmd_index = 0; 2677 for (i = 0; i < len; i++) { 2678 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, reg++, 0xff, *ptr); 2679 ptr++; 2680 } 2681 2682 /* Set transfer OK function. */ 2683 sc->rtsx_intr_trans_ok = rtsx_write_ppbuf; 2684 2685 /* Run the command queue. */ 2686 rtsx_send_cmd(sc); 2687 } 2688 2689 /* 2690 * Write the data previously given via the ping-pong buffer on the card. 2691 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2692 */ 2693 static void 2694 rtsx_write_ppbuf(struct rtsx_softc *sc) 2695 { 2696 struct mmc_command *cmd; 2697 2698 cmd = sc->rtsx_req->cmd; 2699 2700 sc->rtsx_cmd_index = 0; 2701 2702 /* Queue commands to configure data transfer size. */ 2703 rtsx_set_cmd_data_len(sc, cmd->data->len / cmd->data->xfer_len, cmd->data->xfer_len); 2704 2705 /* From Linux: rtsx_pci_sdmmc.c sd_write_data(). */ 2706 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 0xff, 2707 RTSX_SD_CALCULATE_CRC7 | RTSX_SD_CHECK_CRC16 | 2708 RTSX_SD_NO_WAIT_BUSY_END | RTSX_SD_CHECK_CRC7 | RTSX_SD_RSP_LEN_0); 2709 2710 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 0xff, 2711 RTSX_TM_AUTO_WRITE3 | RTSX_SD_TRANSFER_START); 2712 rtsx_push_cmd(sc, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, 2713 RTSX_SD_TRANSFER_END, RTSX_SD_TRANSFER_END); 2714 2715 /* Set transfer OK function. */ 2716 sc->rtsx_intr_trans_ok = rtsx_req_done; 2717 2718 /* Run the command queue. */ 2719 rtsx_send_cmd(sc); 2720 } 2721 2722 /* 2723 * Use the data buffer for transfer > 512 bytes. 2724 */ 2725 static int 2726 rtsx_xfer(struct rtsx_softc *sc, struct mmc_command *cmd) 2727 { 2728 int read = ISSET(cmd->data->flags, MMC_DATA_READ); 2729 2730 cmd->data->xfer_len = (cmd->data->len > RTSX_MAX_DATA_BLKLEN) ? 2731 RTSX_MAX_DATA_BLKLEN : cmd->data->len; 2732 2733 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 2734 device_printf(sc->rtsx_dev, "rtsx_xfer() - %s xfer: %ld bytes with block size %ld\n", 2735 read ? "Read" : "Write", 2736 (unsigned long)cmd->data->len, (unsigned long)cmd->data->xfer_len); 2737 2738 if (cmd->data->len > RTSX_DMA_DATA_BUFSIZE) { 2739 device_printf(sc->rtsx_dev, "rtsx_xfer() length too large: %ld > %d\n", 2740 (unsigned long)cmd->data->len, RTSX_DMA_DATA_BUFSIZE); 2741 cmd->error = MMC_ERR_INVALID; 2742 return (MMC_ERR_INVALID); 2743 } 2744 2745 if (!read) { 2746 /* Set transfer OK function. */ 2747 sc->rtsx_intr_trans_ok = rtsx_xfer_begin; 2748 2749 /* Run the command queue. */ 2750 rtsx_send_req(sc, cmd); 2751 } else { 2752 rtsx_xfer_start(sc); 2753 } 2754 2755 return (0); 2756 } 2757 2758 /* 2759 * Get request response and start dma data transfer (write command). 2760 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2761 */ 2762 static void 2763 rtsx_xfer_begin(struct rtsx_softc *sc) 2764 { 2765 struct mmc_command *cmd; 2766 2767 cmd = sc->rtsx_req->cmd; 2768 2769 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 2770 device_printf(sc->rtsx_dev, "rtsx_xfer_begin() - CMD%d\n", cmd->opcode); 2771 2772 rtsx_set_resp(sc, cmd); 2773 rtsx_xfer_start(sc); 2774 } 2775 2776 /* 2777 * Start dma data transfer. 2778 */ 2779 static void 2780 rtsx_xfer_start(struct rtsx_softc *sc) 2781 { 2782 struct mmc_command *cmd; 2783 int read; 2784 uint8_t cfg2; 2785 int dma_dir; 2786 int tmode; 2787 2788 cmd = sc->rtsx_req->cmd; 2789 read = ISSET(cmd->data->flags, MMC_DATA_READ); 2790 2791 /* Configure DMA transfer mode parameters. */ 2792 if (cmd->opcode == MMC_READ_MULTIPLE_BLOCK) 2793 cfg2 = RTSX_SD_CHECK_CRC16 | RTSX_SD_NO_WAIT_BUSY_END | RTSX_SD_RSP_LEN_6; 2794 else 2795 cfg2 = RTSX_SD_CHECK_CRC16 | RTSX_SD_NO_WAIT_BUSY_END | RTSX_SD_RSP_LEN_0; 2796 if (read) { 2797 dma_dir = RTSX_DMA_DIR_FROM_CARD; 2798 /* 2799 * Use transfer mode AUTO_READ1, which assume we not 2800 * already send the read command and don't need to send 2801 * CMD 12 manually after read. 2802 */ 2803 tmode = RTSX_TM_AUTO_READ1; 2804 cfg2 |= RTSX_SD_CALCULATE_CRC7 | RTSX_SD_CHECK_CRC7; 2805 2806 rtsx_init_cmd(sc, cmd); 2807 } else { 2808 dma_dir = RTSX_DMA_DIR_TO_CARD; 2809 /* 2810 * Use transfer mode AUTO_WRITE3, wich assumes we've already 2811 * sent the write command and gotten the response, and will 2812 * send CMD 12 manually after writing. 2813 */ 2814 tmode = RTSX_TM_AUTO_WRITE3; 2815 cfg2 |= RTSX_SD_NO_CALCULATE_CRC7 | RTSX_SD_NO_CHECK_CRC7; 2816 2817 sc->rtsx_cmd_index = 0; 2818 } 2819 2820 /* Queue commands to configure data transfer size. */ 2821 rtsx_set_cmd_data_len(sc, cmd->data->len / cmd->data->xfer_len, cmd->data->xfer_len); 2822 2823 /* Configure DMA controller. */ 2824 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_IRQSTAT0, 2825 RTSX_DMA_DONE_INT, RTSX_DMA_DONE_INT); 2826 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMATC3, 2827 0xff, cmd->data->len >> 24); 2828 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMATC2, 2829 0xff, cmd->data->len >> 16); 2830 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMATC1, 2831 0xff, cmd->data->len >> 8); 2832 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMATC0, 2833 0xff, cmd->data->len); 2834 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMACTL, 2835 RTSX_DMA_EN | RTSX_DMA_DIR | RTSX_DMA_PACK_SIZE_MASK, 2836 RTSX_DMA_EN | dma_dir | RTSX_DMA_512); 2837 2838 /* Use the DMA ring buffer for commands which transfer data. */ 2839 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_CARD_DATA_SOURCE, 2840 0x01, RTSX_RING_BUFFER); 2841 2842 /* Queue command to set response type. */ 2843 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 0xff, cfg2); 2844 2845 /* Queue commands to perform SD transfer. */ 2846 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 2847 0xff, tmode | RTSX_SD_TRANSFER_START); 2848 rtsx_push_cmd(sc, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, 2849 RTSX_SD_TRANSFER_END, RTSX_SD_TRANSFER_END); 2850 2851 /* Run the command queue. */ 2852 rtsx_send_cmd(sc); 2853 2854 if (!read) 2855 memcpy(sc->rtsx_data_dmamem, cmd->data->data, cmd->data->len); 2856 2857 /* Sync data DMA buffer. */ 2858 bus_dmamap_sync(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamap, BUS_DMASYNC_PREREAD); 2859 bus_dmamap_sync(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamap, BUS_DMASYNC_PREWRITE); 2860 2861 /* Set transfer OK function. */ 2862 sc->rtsx_intr_trans_ok = rtsx_xfer_finish; 2863 2864 /* Tell the chip where the data buffer is and run the transfer. */ 2865 WRITE4(sc, RTSX_HDBAR, sc->rtsx_data_buffer); 2866 WRITE4(sc, RTSX_HDBCTLR, RTSX_TRIG_DMA | (read ? RTSX_DMA_READ : 0) | 2867 (cmd->data->len & 0x00ffffff)); 2868 } 2869 2870 /* 2871 * Finish dma data transfer. 2872 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2873 */ 2874 static void 2875 rtsx_xfer_finish(struct rtsx_softc *sc) 2876 { 2877 struct mmc_command *cmd; 2878 int read; 2879 2880 cmd = sc->rtsx_req->cmd; 2881 2882 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 2883 device_printf(sc->rtsx_dev, "rtsx_xfer_finish() - CMD%d\n", cmd->opcode); 2884 2885 read = ISSET(cmd->data->flags, MMC_DATA_READ); 2886 2887 /* Sync data DMA buffer. */ 2888 bus_dmamap_sync(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamap, BUS_DMASYNC_POSTREAD); 2889 bus_dmamap_sync(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamap, BUS_DMASYNC_POSTWRITE); 2890 2891 if (read) { 2892 memcpy(cmd->data->data, sc->rtsx_data_dmamem, cmd->data->len); 2893 rtsx_req_done(sc); 2894 } else { 2895 /* Send CMD12 after AUTO_WRITE3 (see mmcsd_rw() in mmcsd.c) */ 2896 /* and complete request. */ 2897 sc->rtsx_intr_trans_ok = NULL; 2898 rtsx_send_req(sc, sc->rtsx_req->stop); 2899 } 2900 } 2901 2902 /* 2903 * Manage request timeout. 2904 */ 2905 static void 2906 rtsx_timeout(void *arg) 2907 { 2908 struct rtsx_softc *sc; 2909 2910 sc = (struct rtsx_softc *)arg; 2911 if (sc->rtsx_req != NULL) { 2912 device_printf(sc->rtsx_dev, "Controller timeout for CMD%u\n", 2913 sc->rtsx_req->cmd->opcode); 2914 sc->rtsx_req->cmd->error = MMC_ERR_TIMEOUT; 2915 rtsx_stop_cmd(sc); 2916 rtsx_req_done(sc); 2917 } else { 2918 device_printf(sc->rtsx_dev, "Controller timeout!\n"); 2919 } 2920 } 2921 2922 #ifdef MMCCAM 2923 static int 2924 rtsx_get_tran_settings(device_t dev, struct ccb_trans_settings_mmc *cts) 2925 { 2926 struct rtsx_softc *sc; 2927 2928 sc = device_get_softc(dev); 2929 2930 cts->host_ocr = sc->rtsx_host.host_ocr; 2931 cts->host_f_min = sc->rtsx_host.f_min; 2932 cts->host_f_max = sc->rtsx_host.f_max; 2933 cts->host_caps = sc->rtsx_host.caps; 2934 cts->host_max_data = RTSX_DMA_DATA_BUFSIZE / MMC_SECTOR_SIZE; 2935 memcpy(&cts->ios, &sc->rtsx_host.ios, sizeof(struct mmc_ios)); 2936 2937 return (0); 2938 } 2939 2940 /* 2941 * Apply settings and return status accordingly. 2942 */ 2943 static int 2944 rtsx_set_tran_settings(device_t dev, struct ccb_trans_settings_mmc *cts) 2945 { 2946 struct rtsx_softc *sc; 2947 struct mmc_ios *ios; 2948 struct mmc_ios *new_ios; 2949 2950 sc = device_get_softc(dev); 2951 2952 ios = &sc->rtsx_host.ios; 2953 new_ios = &cts->ios; 2954 2955 /* Update only requested fields */ 2956 if (cts->ios_valid & MMC_CLK) { 2957 ios->clock = new_ios->clock; 2958 sc->rtsx_ios_clock = -1; /* To be updated by rtsx_mmcbr_update_ios(). */ 2959 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 2960 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - clock: %u\n", ios->clock); 2961 } 2962 if (cts->ios_valid & MMC_VDD) { 2963 ios->vdd = new_ios->vdd; 2964 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 2965 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - vdd: %d\n", ios->vdd); 2966 } 2967 if (cts->ios_valid & MMC_CS) { 2968 ios->chip_select = new_ios->chip_select; 2969 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 2970 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - chip_select: %d\n", ios->chip_select); 2971 } 2972 if (cts->ios_valid & MMC_BW) { 2973 ios->bus_width = new_ios->bus_width; 2974 sc->rtsx_ios_bus_width = -1; /* To be updated by rtsx_mmcbr_update_ios(). */ 2975 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 2976 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - bus width: %d\n", ios->bus_width); 2977 } 2978 if (cts->ios_valid & MMC_PM) { 2979 ios->power_mode = new_ios->power_mode; 2980 sc->rtsx_ios_power_mode = -1; /* To be updated by rtsx_mmcbr_update_ios(). */ 2981 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 2982 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - power mode: %d\n", ios->power_mode); 2983 } 2984 if (cts->ios_valid & MMC_BT) { 2985 ios->timing = new_ios->timing; 2986 sc->rtsx_ios_timing = -1; /* To be updated by rtsx_mmcbr_update_ios(). */ 2987 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 2988 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - timing: %d\n", ios->timing); 2989 } 2990 if (cts->ios_valid & MMC_BM) { 2991 ios->bus_mode = new_ios->bus_mode; 2992 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 2993 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - bus mode: %d\n", ios->bus_mode); 2994 } 2995 #if __FreeBSD_version >= 1300000 2996 if (cts->ios_valid & MMC_VCCQ) { 2997 ios->vccq = new_ios->vccq; 2998 sc->rtsx_ios_vccq = -1; /* To be updated by rtsx_mmcbr_update_ios(). */ 2999 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 3000 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - vccq: %d\n", ios->vccq); 3001 } 3002 #endif /* __FreeBSD_version >= 1300000 */ 3003 if (rtsx_mmcbr_update_ios(sc->rtsx_dev, NULL) == 0) 3004 return (CAM_REQ_CMP); 3005 else 3006 return (CAM_REQ_CMP_ERR); 3007 } 3008 3009 /* 3010 * Build a request and run it. 3011 */ 3012 static int 3013 rtsx_cam_request(device_t dev, union ccb *ccb) 3014 { 3015 struct rtsx_softc *sc; 3016 3017 sc = device_get_softc(dev); 3018 3019 RTSX_LOCK(sc); 3020 if (sc->rtsx_ccb != NULL) { 3021 RTSX_UNLOCK(sc); 3022 return (CAM_BUSY); 3023 } 3024 sc->rtsx_ccb = ccb; 3025 sc->rtsx_cam_req.cmd = &ccb->mmcio.cmd; 3026 sc->rtsx_cam_req.stop = &ccb->mmcio.stop; 3027 RTSX_UNLOCK(sc); 3028 3029 rtsx_mmcbr_request(sc->rtsx_dev, NULL, &sc->rtsx_cam_req); 3030 return (0); 3031 } 3032 #endif /* MMCCAM */ 3033 3034 static int 3035 rtsx_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) 3036 { 3037 struct rtsx_softc *sc; 3038 3039 sc = device_get_softc(bus); 3040 switch (which) { 3041 case MMCBR_IVAR_BUS_MODE: /* ivar 0 - 1 = opendrain, 2 = pushpull */ 3042 *result = sc->rtsx_host.ios.bus_mode; 3043 break; 3044 case MMCBR_IVAR_BUS_WIDTH: /* ivar 1 - 0 = 1b 2 = 4b, 3 = 8b */ 3045 *result = sc->rtsx_host.ios.bus_width; 3046 break; 3047 case MMCBR_IVAR_CHIP_SELECT: /* ivar 2 - O = dontcare, 1 = cs_high, 2 = cs_low */ 3048 *result = sc->rtsx_host.ios.chip_select; 3049 break; 3050 case MMCBR_IVAR_CLOCK: /* ivar 3 - clock in Hz */ 3051 *result = sc->rtsx_host.ios.clock; 3052 break; 3053 case MMCBR_IVAR_F_MIN: /* ivar 4 */ 3054 *result = sc->rtsx_host.f_min; 3055 break; 3056 case MMCBR_IVAR_F_MAX: /* ivar 5 */ 3057 *result = sc->rtsx_host.f_max; 3058 break; 3059 case MMCBR_IVAR_HOST_OCR: /* ivar 6 - host operation conditions register */ 3060 *result = sc->rtsx_host.host_ocr; 3061 break; 3062 case MMCBR_IVAR_MODE: /* ivar 7 - 0 = mode_mmc, 1 = mode_sd */ 3063 *result = sc->rtsx_host.mode; 3064 break; 3065 case MMCBR_IVAR_OCR: /* ivar 8 - operation conditions register */ 3066 *result = sc->rtsx_host.ocr; 3067 break; 3068 case MMCBR_IVAR_POWER_MODE: /* ivar 9 - 0 = off, 1 = up, 2 = on */ 3069 *result = sc->rtsx_host.ios.power_mode; 3070 break; 3071 case MMCBR_IVAR_VDD: /* ivar 11 - voltage power pin */ 3072 *result = sc->rtsx_host.ios.vdd; 3073 break; 3074 case MMCBR_IVAR_VCCQ: /* ivar 12 - signaling: 0 = 1.20V, 1 = 1.80V, 2 = 3.30V */ 3075 *result = sc->rtsx_host.ios.vccq; 3076 break; 3077 case MMCBR_IVAR_CAPS: /* ivar 13 */ 3078 *result = sc->rtsx_host.caps; 3079 break; 3080 case MMCBR_IVAR_TIMING: /* ivar 14 - 0 = normal, 1 = timing_hs, ... */ 3081 *result = sc->rtsx_host.ios.timing; 3082 break; 3083 case MMCBR_IVAR_MAX_DATA: /* ivar 15 */ 3084 *result = RTSX_DMA_DATA_BUFSIZE / MMC_SECTOR_SIZE; 3085 break; 3086 case MMCBR_IVAR_RETUNE_REQ: /* ivar 10 */ 3087 case MMCBR_IVAR_MAX_BUSY_TIMEOUT: /* ivar 16 */ 3088 default: 3089 return (EINVAL); 3090 } 3091 3092 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 3093 device_printf(bus, "Read ivar #%d, value %#x / #%d\n", 3094 which, *(int *)result, *(int *)result); 3095 3096 return (0); 3097 } 3098 3099 static int 3100 rtsx_write_ivar(device_t bus, device_t child, int which, uintptr_t value) 3101 { 3102 struct rtsx_softc *sc; 3103 3104 sc = device_get_softc(bus); 3105 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 3106 device_printf(bus, "Write ivar #%d, value %#x / #%d\n", 3107 which, (int)value, (int)value); 3108 3109 switch (which) { 3110 case MMCBR_IVAR_BUS_MODE: /* ivar 0 - 1 = opendrain, 2 = pushpull */ 3111 sc->rtsx_host.ios.bus_mode = value; 3112 break; 3113 case MMCBR_IVAR_BUS_WIDTH: /* ivar 1 - 0 = 1b 2 = 4b, 3 = 8b */ 3114 sc->rtsx_host.ios.bus_width = value; 3115 sc->rtsx_ios_bus_width = -1; /* To be updated on next rtsx_mmcbr_update_ios(). */ 3116 break; 3117 case MMCBR_IVAR_CHIP_SELECT: /* ivar 2 - O = dontcare, 1 = cs_high, 2 = cs_low */ 3118 sc->rtsx_host.ios.chip_select = value; 3119 break; 3120 case MMCBR_IVAR_CLOCK: /* ivar 3 - clock in Hz */ 3121 sc->rtsx_host.ios.clock = value; 3122 sc->rtsx_ios_clock = -1; /* To be updated on next rtsx_mmcbr_update_ios(). */ 3123 break; 3124 case MMCBR_IVAR_MODE: /* ivar 7 - 0 = mode_mmc, 1 = mode_sd */ 3125 sc->rtsx_host.mode = value; 3126 break; 3127 case MMCBR_IVAR_OCR: /* ivar 8 - operation conditions register */ 3128 sc->rtsx_host.ocr = value; 3129 break; 3130 case MMCBR_IVAR_POWER_MODE: /* ivar 9 - 0 = off, 1 = up, 2 = on */ 3131 sc->rtsx_host.ios.power_mode = value; 3132 sc->rtsx_ios_power_mode = -1; /* To be updated on next rtsx_mmcbr_update_ios(). */ 3133 break; 3134 case MMCBR_IVAR_VDD: /* ivar 11 - voltage power pin */ 3135 sc->rtsx_host.ios.vdd = value; 3136 break; 3137 case MMCBR_IVAR_VCCQ: /* ivar 12 - signaling: 0 = 1.20V, 1 = 1.80V, 2 = 3.30V */ 3138 sc->rtsx_host.ios.vccq = value; 3139 sc->rtsx_ios_vccq = value; /* rtsx_mmcbr_switch_vccq() will be called by mmc.c (MMCCAM undef). */ 3140 break; 3141 case MMCBR_IVAR_TIMING: /* ivar 14 - 0 = normal, 1 = timing_hs, ... */ 3142 sc->rtsx_host.ios.timing = value; 3143 sc->rtsx_ios_timing = -1; /* To be updated on next rtsx_mmcbr_update_ios(). */ 3144 break; 3145 /* These are read-only. */ 3146 case MMCBR_IVAR_F_MIN: /* ivar 4 */ 3147 case MMCBR_IVAR_F_MAX: /* ivar 5 */ 3148 case MMCBR_IVAR_HOST_OCR: /* ivar 6 - host operation conditions register */ 3149 case MMCBR_IVAR_RETUNE_REQ: /* ivar 10 */ 3150 case MMCBR_IVAR_CAPS: /* ivar 13 */ 3151 case MMCBR_IVAR_MAX_DATA: /* ivar 15 */ 3152 case MMCBR_IVAR_MAX_BUSY_TIMEOUT: /* ivar 16 */ 3153 default: 3154 return (EINVAL); 3155 } 3156 3157 return (0); 3158 } 3159 3160 static int 3161 rtsx_mmcbr_update_ios(device_t bus, device_t child__unused) 3162 { 3163 struct rtsx_softc *sc; 3164 struct mmc_ios *ios; 3165 int error; 3166 3167 sc = device_get_softc(bus); 3168 ios = &sc->rtsx_host.ios; 3169 3170 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 3171 device_printf(bus, "rtsx_mmcbr_update_ios()\n"); 3172 3173 /* if MMCBR_IVAR_BUS_WIDTH updated. */ 3174 if (sc->rtsx_ios_bus_width < 0) { 3175 sc->rtsx_ios_bus_width = ios->bus_width; 3176 if ((error = rtsx_set_bus_width(sc, ios->bus_width))) 3177 return (error); 3178 } 3179 3180 /* if MMCBR_IVAR_POWER_MODE updated. */ 3181 if (sc->rtsx_ios_power_mode < 0) { 3182 sc->rtsx_ios_power_mode = ios->power_mode; 3183 switch (ios->power_mode) { 3184 case power_off: 3185 if ((error = rtsx_bus_power_off(sc))) 3186 return (error); 3187 break; 3188 case power_up: 3189 if ((error = rtsx_bus_power_on(sc))) 3190 return (error); 3191 break; 3192 case power_on: 3193 if ((error = rtsx_bus_power_on(sc))) 3194 return (error); 3195 break; 3196 } 3197 } 3198 3199 sc->rtsx_double_clk = true; 3200 sc->rtsx_vpclk = false; 3201 3202 /* if MMCBR_IVAR_TIMING updated. */ 3203 if (sc->rtsx_ios_timing < 0) { 3204 sc->rtsx_ios_timing = ios->timing; 3205 if ((error = rtsx_set_sd_timing(sc, ios->timing))) 3206 return (error); 3207 } 3208 3209 /* if MMCBR_IVAR_CLOCK updated, must be after rtsx_set_sd_timing() */ 3210 if (sc->rtsx_ios_clock < 0) { 3211 sc->rtsx_ios_clock = ios->clock; 3212 if ((error = rtsx_set_sd_clock(sc, ios->clock))) 3213 return (error); 3214 } 3215 3216 /* if MMCCAM and vccq updated */ 3217 if (sc->rtsx_ios_vccq < 0) { 3218 sc->rtsx_ios_vccq = ios->vccq; 3219 if ((error = rtsx_mmcbr_switch_vccq(sc->rtsx_dev, NULL))) 3220 return (error); 3221 } 3222 3223 return (0); 3224 } 3225 3226 /* 3227 * Set output stage logic power voltage. 3228 */ 3229 static int 3230 rtsx_mmcbr_switch_vccq(device_t bus, device_t child __unused) 3231 { 3232 struct rtsx_softc *sc; 3233 int vccq = 0; 3234 int error; 3235 3236 sc = device_get_softc(bus); 3237 3238 switch (sc->rtsx_host.ios.vccq) { 3239 case vccq_120: 3240 vccq = 120; 3241 break; 3242 case vccq_180: 3243 vccq = 180; 3244 break; 3245 case vccq_330: 3246 vccq = 330; 3247 break; 3248 }; 3249 /* It seems it is always vccq_330. */ 3250 if (vccq == 330) { 3251 switch (sc->rtsx_device_id) { 3252 uint16_t val; 3253 case RTSX_RTS5227: 3254 if ((error = rtsx_write_phy(sc, 0x08, 0x4FE4))) 3255 return (error); 3256 if ((error = rtsx_rts5227_fill_driving(sc))) 3257 return (error); 3258 break; 3259 case RTSX_RTS5209: 3260 case RTSX_RTS5229: 3261 RTSX_BITOP(sc, RTSX_SD30_CMD_DRIVE_SEL, RTSX_SD30_DRIVE_SEL_MASK, sc->rtsx_sd30_drive_sel_3v3); 3262 if ((error = rtsx_write_phy(sc, 0x08, 0x4FE4))) 3263 return (error); 3264 break; 3265 case RTSX_RTS522A: 3266 if ((error = rtsx_write_phy(sc, 0x08, 0x57E4))) 3267 return (error); 3268 if ((error = rtsx_rts5227_fill_driving(sc))) 3269 return (error); 3270 break; 3271 case RTSX_RTS525A: 3272 RTSX_BITOP(sc, RTSX_LDO_CONFIG2, RTSX_LDO_D3318_MASK, RTSX_LDO_D3318_33V); 3273 RTSX_BITOP(sc, RTSX_SD_PAD_CTL, RTSX_SD_IO_USING_1V8, 0); 3274 if ((error = rtsx_rts5249_fill_driving(sc))) 3275 return (error); 3276 break; 3277 case RTSX_RTS5249: 3278 if ((error = rtsx_read_phy(sc, RTSX_PHY_TUNE, &val))) 3279 return (error); 3280 if ((error = rtsx_write_phy(sc, RTSX_PHY_TUNE, 3281 (val & RTSX_PHY_TUNE_VOLTAGE_MASK) | RTSX_PHY_TUNE_VOLTAGE_3V3))) 3282 return (error); 3283 if ((error = rtsx_rts5249_fill_driving(sc))) 3284 return (error); 3285 break; 3286 case RTSX_RTS5260: 3287 RTSX_BITOP(sc, RTSX_LDO_CONFIG2, RTSX_DV331812_VDD1, RTSX_DV331812_VDD1); 3288 RTSX_BITOP(sc, RTSX_LDO_DV18_CFG, RTSX_DV331812_MASK, RTSX_DV331812_33); 3289 if ((error = rtsx_rts5260_fill_driving(sc))) 3290 return (error); 3291 break; 3292 case RTSX_RTL8402: 3293 RTSX_BITOP(sc, RTSX_SD30_CMD_DRIVE_SEL, RTSX_SD30_DRIVE_SEL_MASK, sc->rtsx_sd30_drive_sel_3v3); 3294 RTSX_BITOP(sc, RTSX_LDO_CTL, 3295 (RTSX_BPP_ASIC_MASK << RTSX_BPP_SHIFT_8402) | RTSX_BPP_PAD_MASK, 3296 (RTSX_BPP_ASIC_3V3 << RTSX_BPP_SHIFT_8402) | RTSX_BPP_PAD_3V3); 3297 break; 3298 case RTSX_RTL8411: 3299 case RTSX_RTL8411B: 3300 RTSX_BITOP(sc, RTSX_SD30_CMD_DRIVE_SEL, RTSX_SD30_DRIVE_SEL_MASK, sc->rtsx_sd30_drive_sel_3v3); 3301 RTSX_BITOP(sc, RTSX_LDO_CTL, 3302 (RTSX_BPP_ASIC_MASK << RTSX_BPP_SHIFT_8411) | RTSX_BPP_PAD_MASK, 3303 (RTSX_BPP_ASIC_3V3 << RTSX_BPP_SHIFT_8411) | RTSX_BPP_PAD_3V3); 3304 break; 3305 } 3306 DELAY(300); 3307 } 3308 3309 if (sc->rtsx_debug_mask & (RTSX_DEBUG_BASIC | RTSX_TRACE_SD_CMD)) 3310 device_printf(sc->rtsx_dev, "rtsx_mmcbr_switch_vccq(%d)\n", vccq); 3311 3312 return (0); 3313 } 3314 3315 #ifndef MMCCAM 3316 /* 3317 * Tune card if bus_timing_uhs_sdr50. 3318 */ 3319 static int 3320 rtsx_mmcbr_tune(device_t bus, device_t child __unused, bool hs400) 3321 { 3322 struct rtsx_softc *sc; 3323 uint32_t raw_phase_map[RTSX_RX_TUNING_CNT] = {0}; 3324 uint32_t phase_map; 3325 uint8_t final_phase; 3326 int i; 3327 3328 sc = device_get_softc(bus); 3329 3330 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 3331 device_printf(sc->rtsx_dev, "rtsx_mmcbr_tune() - hs400 is %s\n", 3332 (hs400) ? "true" : "false"); 3333 3334 if (sc->rtsx_ios_timing != bus_timing_uhs_sdr50) 3335 return (0); 3336 3337 sc->rtsx_tuning_mode = true; 3338 3339 switch (sc->rtsx_device_id) { 3340 case RTSX_RTS5209: 3341 case RTSX_RTS5227: 3342 rtsx_sd_change_tx_phase(sc, 27); 3343 break; 3344 case RTSX_RTS522A: 3345 rtsx_sd_change_tx_phase(sc, 20); 3346 break; 3347 case RTSX_RTS5229: 3348 rtsx_sd_change_tx_phase(sc, 27); 3349 break; 3350 case RTSX_RTS525A: 3351 case RTSX_RTS5249: 3352 rtsx_sd_change_tx_phase(sc, 29); 3353 break; 3354 case RTSX_RTL8402: 3355 case RTSX_RTL8411: 3356 case RTSX_RTL8411B: 3357 rtsx_sd_change_tx_phase(sc, 7); 3358 break; 3359 } 3360 3361 /* trying rx tuning for bus_timing_uhs_sdr50. */ 3362 for (i = 0; i < RTSX_RX_TUNING_CNT; i++) { 3363 rtsx_sd_tuning_rx_phase(sc, &(raw_phase_map[i])); 3364 if (raw_phase_map[i] == 0) 3365 break; 3366 } 3367 3368 phase_map = 0xffffffff; 3369 for (i = 0; i < RTSX_RX_TUNING_CNT; i++) { 3370 if (sc->rtsx_debug_mask & (RTSX_DEBUG_BASIC | RTSX_DEBUG_TUNING)) 3371 device_printf(sc->rtsx_dev, "rtsx_mmcbr_tune() - RX raw_phase_map[%d]: 0x%08x\n", 3372 i, raw_phase_map[i]); 3373 phase_map &= raw_phase_map[i]; 3374 } 3375 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 3376 device_printf(sc->rtsx_dev, "rtsx_mmcbr_tune() - RX phase_map: 0x%08x\n", phase_map); 3377 3378 if (phase_map) { 3379 final_phase = rtsx_sd_search_final_rx_phase(sc, phase_map); 3380 if (final_phase != 0xff) { 3381 rtsx_sd_change_rx_phase(sc, final_phase); 3382 } 3383 } 3384 3385 sc->rtsx_tuning_mode = false; 3386 3387 return (0); 3388 } 3389 3390 static int 3391 rtsx_mmcbr_retune(device_t bus, device_t child __unused, bool reset __unused) 3392 { 3393 struct rtsx_softc *sc; 3394 3395 sc = device_get_softc(bus); 3396 3397 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 3398 device_printf(sc->rtsx_dev, "rtsx_mmcbr_retune()\n"); 3399 3400 return (0); 3401 } 3402 #endif /* !MMCCAM */ 3403 3404 static int 3405 rtsx_mmcbr_request(device_t bus, device_t child __unused, struct mmc_request *req) 3406 { 3407 struct rtsx_softc *sc; 3408 struct mmc_command *cmd; 3409 int timeout; 3410 int error; 3411 3412 sc = device_get_softc(bus); 3413 3414 RTSX_LOCK(sc); 3415 if (sc->rtsx_req != NULL) { 3416 RTSX_UNLOCK(sc); 3417 return (EBUSY); 3418 } 3419 sc->rtsx_req = req; 3420 cmd = req->cmd; 3421 cmd->error = error = MMC_ERR_NONE; 3422 sc->rtsx_intr_status = 0; 3423 sc->rtsx_intr_trans_ok = NULL; 3424 sc->rtsx_intr_trans_ko = rtsx_req_done; 3425 3426 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 3427 device_printf(sc->rtsx_dev, "rtsx_mmcbr_request(CMD%u arg %#x, flags %#x, dlen %u, dflags %#x)\n", 3428 cmd->opcode, cmd->arg, cmd->flags, 3429 cmd->data != NULL ? (unsigned int)cmd->data->len : 0, 3430 cmd->data != NULL ? cmd->data->flags : 0); 3431 3432 /* Check if card present. */ 3433 if (!ISSET(sc->rtsx_flags, RTSX_F_CARD_PRESENT)) { 3434 cmd->error = error = MMC_ERR_FAILED; 3435 goto end; 3436 } 3437 3438 /* Refuse SDIO probe if the chip doesn't support SDIO. */ 3439 if (cmd->opcode == IO_SEND_OP_COND && 3440 !ISSET(sc->rtsx_flags, RTSX_F_SDIO_SUPPORT)) { 3441 cmd->error = error = MMC_ERR_INVALID; 3442 goto end; 3443 } 3444 3445 /* Return MMC_ERR_TIMEOUT for SD_IO_RW_DIRECT and IO_SEND_OP_COND. */ 3446 if (cmd->opcode == SD_IO_RW_DIRECT || cmd->opcode == IO_SEND_OP_COND) { 3447 cmd->error = error = MMC_ERR_TIMEOUT; 3448 goto end; 3449 } 3450 3451 /* Select SD card. */ 3452 RTSX_BITOP(sc, RTSX_CARD_SELECT, 0x07, RTSX_SD_MOD_SEL); 3453 RTSX_BITOP(sc, RTSX_CARD_SHARE_MODE, RTSX_CARD_SHARE_MASK, RTSX_CARD_SHARE_48_SD); 3454 3455 if (cmd->data == NULL) { 3456 DELAY(200); 3457 timeout = sc->rtsx_timeout_cmd; 3458 error = rtsx_send_req(sc, cmd); 3459 } else if (cmd->data->len <= 512) { 3460 timeout = sc->rtsx_timeout_io; 3461 error = rtsx_xfer_short(sc, cmd); 3462 } else { 3463 timeout = sc->rtsx_timeout_io; 3464 error = rtsx_xfer(sc, cmd); 3465 } 3466 end: 3467 if (error == MMC_ERR_NONE) { 3468 callout_reset(&sc->rtsx_timeout_callout, timeout * hz, rtsx_timeout, sc); 3469 } else { 3470 rtsx_req_done(sc); 3471 } 3472 RTSX_UNLOCK(sc); 3473 3474 return (error); 3475 } 3476 3477 #ifndef MMCCAM 3478 static int 3479 rtsx_mmcbr_get_ro(device_t bus, device_t child __unused) 3480 { 3481 struct rtsx_softc *sc; 3482 3483 sc = device_get_softc(bus); 3484 3485 if (sc->rtsx_inversion == 0) 3486 return (sc->rtsx_read_only); 3487 else 3488 return !(sc->rtsx_read_only); 3489 } 3490 3491 static int 3492 rtsx_mmcbr_acquire_host(device_t bus, device_t child __unused) 3493 { 3494 struct rtsx_softc *sc; 3495 3496 sc = device_get_softc(bus); 3497 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 3498 device_printf(bus, "rtsx_mmcbr_acquire_host()\n"); 3499 3500 RTSX_LOCK(sc); 3501 while (sc->rtsx_bus_busy) 3502 msleep(&sc->rtsx_bus_busy, &sc->rtsx_mtx, 0, "rtsxah", 0); 3503 sc->rtsx_bus_busy++; 3504 RTSX_UNLOCK(sc); 3505 3506 return (0); 3507 } 3508 3509 static int 3510 rtsx_mmcbr_release_host(device_t bus, device_t child __unused) 3511 { 3512 struct rtsx_softc *sc; 3513 3514 sc = device_get_softc(bus); 3515 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 3516 device_printf(bus, "rtsx_mmcbr_release_host()\n"); 3517 3518 RTSX_LOCK(sc); 3519 sc->rtsx_bus_busy--; 3520 wakeup(&sc->rtsx_bus_busy); 3521 RTSX_UNLOCK(sc); 3522 3523 return (0); 3524 } 3525 #endif /* !MMCCAM */ 3526 3527 /* 3528 * 3529 * PCI Support Functions 3530 * 3531 */ 3532 3533 /* 3534 * Compare the device ID (chip) of this device against the IDs that this driver 3535 * supports. If there is a match, set the description and return success. 3536 */ 3537 static int 3538 rtsx_probe(device_t dev) 3539 { 3540 uint16_t vendor_id; 3541 uint16_t device_id; 3542 int i; 3543 int result; 3544 3545 vendor_id = pci_get_vendor(dev); 3546 device_id = pci_get_device(dev); 3547 3548 result = ENXIO; 3549 for (i = 0; rtsx_devices[i].vendor_id != 0; i++) { 3550 if (rtsx_devices[i].vendor_id == vendor_id && 3551 rtsx_devices[i].device_id == device_id) { 3552 device_set_desc(dev, rtsx_devices[i].desc); 3553 result = BUS_PROBE_DEFAULT; 3554 break; 3555 } 3556 } 3557 3558 return (result); 3559 } 3560 3561 /* 3562 * Attach function is only called if the probe is successful. 3563 */ 3564 static int 3565 rtsx_attach(device_t dev) 3566 { 3567 struct rtsx_softc *sc = device_get_softc(dev); 3568 uint16_t vendor_id; 3569 uint16_t device_id; 3570 struct sysctl_ctx_list *ctx; 3571 struct sysctl_oid_list *tree; 3572 int msi_count = 1; 3573 uint32_t sdio_cfg; 3574 int error; 3575 char *maker; 3576 char *family; 3577 char *product; 3578 int i; 3579 3580 vendor_id = pci_get_vendor(dev); 3581 device_id = pci_get_device(dev); 3582 if (bootverbose) 3583 device_printf(dev, "Attach - Vendor ID: 0x%x - Device ID: 0x%x\n", 3584 vendor_id, device_id); 3585 3586 sc->rtsx_dev = dev; 3587 sc->rtsx_device_id = device_id; 3588 sc->rtsx_req = NULL; 3589 sc->rtsx_timeout_cmd = 1; 3590 sc->rtsx_timeout_io = 10; 3591 sc->rtsx_read_only = 0; 3592 sc->rtsx_inversion = 0; 3593 sc->rtsx_force_timing = 0; 3594 sc->rtsx_debug_mask = 0; 3595 sc->rtsx_read_count = 0; 3596 sc->rtsx_write_count = 0; 3597 3598 maker = kern_getenv("smbios.system.maker"); 3599 family = kern_getenv("smbios.system.family"); 3600 product = kern_getenv("smbios.system.product"); 3601 for (i = 0; rtsx_inversion_models[i].maker != NULL; i++) { 3602 if (strcmp(rtsx_inversion_models[i].maker, maker) == 0 && 3603 strcmp(rtsx_inversion_models[i].family, family) == 0 && 3604 strcmp(rtsx_inversion_models[i].product, product) == 0) { 3605 device_printf(dev, "Inversion activated for %s/%s/%s, see BUG in rtsx(4)\n", maker, family, product); 3606 device_printf(dev, "If a card is detected without an SD card present," 3607 " add dev.rtsx.0.inversion=0 in loader.conf(5)\n"); 3608 sc->rtsx_inversion = 1; 3609 } 3610 } 3611 3612 RTSX_LOCK_INIT(sc); 3613 3614 ctx = device_get_sysctl_ctx(dev); 3615 tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 3616 SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "timeout_io", CTLFLAG_RW, 3617 &sc->rtsx_timeout_io, 0, "Request timeout for I/O commands in seconds"); 3618 SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "timeout_cmd", CTLFLAG_RW, 3619 &sc->rtsx_timeout_cmd, 0, "Request timeout for setup commands in seconds"); 3620 SYSCTL_ADD_U8(ctx, tree, OID_AUTO, "read_only", CTLFLAG_RD, 3621 &sc->rtsx_read_only, 0, "Card is write protected"); 3622 SYSCTL_ADD_U8(ctx, tree, OID_AUTO, "inversion", CTLFLAG_RWTUN, 3623 &sc->rtsx_inversion, 0, "Inversion of card detection and read only status"); 3624 SYSCTL_ADD_U8(ctx, tree, OID_AUTO, "force_timing", CTLFLAG_RW, 3625 &sc->rtsx_force_timing, 0, "Force bus_timing_uhs_sdr50"); 3626 SYSCTL_ADD_U8(ctx, tree, OID_AUTO, "debug_mask", CTLFLAG_RWTUN, 3627 &sc->rtsx_debug_mask, 0, "debugging mask, see rtsx(4)"); 3628 SYSCTL_ADD_U64(ctx, tree, OID_AUTO, "read_count", CTLFLAG_RD | CTLFLAG_STATS, 3629 &sc->rtsx_read_count, 0, "Count of read operations"); 3630 SYSCTL_ADD_U64(ctx, tree, OID_AUTO, "write_count", CTLFLAG_RD | CTLFLAG_STATS, 3631 &sc->rtsx_write_count, 0, "Count of write operations"); 3632 3633 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 3634 device_printf(dev, "We are running with inversion: %d\n", sc->rtsx_inversion); 3635 3636 /* Allocate IRQ. */ 3637 sc->rtsx_irq_res_id = 0; 3638 if (pci_alloc_msi(dev, &msi_count) == 0) 3639 sc->rtsx_irq_res_id = 1; 3640 sc->rtsx_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->rtsx_irq_res_id, 3641 RF_ACTIVE | (sc->rtsx_irq_res_id != 0 ? 0 : RF_SHAREABLE)); 3642 if (sc->rtsx_irq_res == NULL) { 3643 device_printf(dev, "Can't allocate IRQ resources for %d\n", sc->rtsx_irq_res_id); 3644 pci_release_msi(dev); 3645 return (ENXIO); 3646 } 3647 3648 callout_init_mtx(&sc->rtsx_timeout_callout, &sc->rtsx_mtx, 0); 3649 3650 /* Allocate memory resource. */ 3651 if (sc->rtsx_device_id == RTSX_RTS525A) 3652 sc->rtsx_mem_res_id = PCIR_BAR(1); 3653 else 3654 sc->rtsx_mem_res_id = PCIR_BAR(0); 3655 sc->rtsx_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->rtsx_mem_res_id, RF_ACTIVE); 3656 if (sc->rtsx_mem_res == NULL) { 3657 device_printf(dev, "Can't allocate memory resource for %d\n", sc->rtsx_mem_res_id); 3658 goto destroy_rtsx_irq_res; 3659 } 3660 3661 if (bootverbose) 3662 device_printf(dev, "rtsx_irq_res_id: %d, rtsx_mem_res_id: %d\n", 3663 sc->rtsx_irq_res_id, sc->rtsx_mem_res_id); 3664 3665 sc->rtsx_mem_btag = rman_get_bustag(sc->rtsx_mem_res); 3666 sc->rtsx_mem_bhandle = rman_get_bushandle(sc->rtsx_mem_res); 3667 3668 TIMEOUT_TASK_INIT(taskqueue_swi_giant, &sc->rtsx_card_insert_task, 0, 3669 rtsx_card_task, sc); 3670 TASK_INIT(&sc->rtsx_card_remove_task, 0, rtsx_card_task, sc); 3671 3672 /* Allocate two DMA buffers: a command buffer and a data buffer. */ 3673 error = rtsx_dma_alloc(sc); 3674 if (error) 3675 goto destroy_rtsx_irq_res; 3676 3677 /* Activate the interrupt. */ 3678 error = bus_setup_intr(dev, sc->rtsx_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 3679 NULL, rtsx_intr, sc, &sc->rtsx_irq_cookie); 3680 if (error) { 3681 device_printf(dev, "Can't set up irq [0x%x]!\n", error); 3682 goto destroy_rtsx_mem_res; 3683 } 3684 pci_enable_busmaster(dev); 3685 3686 if (rtsx_read_cfg(sc, 0, RTSX_SDIOCFG_REG, &sdio_cfg) == 0) { 3687 if ((sdio_cfg & RTSX_SDIOCFG_SDIO_ONLY) || 3688 (sdio_cfg & RTSX_SDIOCFG_HAVE_SDIO)) 3689 sc->rtsx_flags |= RTSX_F_SDIO_SUPPORT; 3690 } 3691 3692 #ifdef MMCCAM 3693 sc->rtsx_ccb = NULL; 3694 sc->rtsx_cam_status = 0; 3695 3696 SYSCTL_ADD_U8(ctx, tree, OID_AUTO, "cam_status", CTLFLAG_RD, 3697 &sc->rtsx_cam_status, 0, "driver cam card present"); 3698 3699 if (mmc_cam_sim_alloc(dev, "rtsx_mmc", &sc->rtsx_mmc_sim) != 0) { 3700 device_printf(dev, "Can't allocate CAM SIM\n"); 3701 goto destroy_rtsx_irq; 3702 } 3703 #endif /* MMCCAM */ 3704 3705 /* Initialize device. */ 3706 error = rtsx_init(sc); 3707 if (error) { 3708 device_printf(dev, "Error %d during rtsx_init()\n", error); 3709 goto destroy_rtsx_irq; 3710 } 3711 3712 /* 3713 * Schedule a card detection as we won't get an interrupt 3714 * if the card is inserted when we attach. We wait a quarter 3715 * of a second to allow for a "spontaneous" interrupt which may 3716 * change the card presence state. This delay avoid a panic 3717 * on some configuration (e.g. Lenovo T540p). 3718 */ 3719 DELAY(250000); 3720 if (rtsx_is_card_present(sc)) 3721 device_printf(sc->rtsx_dev, "A card is detected\n"); 3722 else 3723 device_printf(sc->rtsx_dev, "No card is detected\n"); 3724 rtsx_card_task(sc, 0); 3725 3726 if (bootverbose) 3727 device_printf(dev, "Device attached\n"); 3728 3729 return (0); 3730 3731 destroy_rtsx_irq: 3732 bus_teardown_intr(dev, sc->rtsx_irq_res, sc->rtsx_irq_cookie); 3733 destroy_rtsx_mem_res: 3734 bus_release_resource(dev, SYS_RES_MEMORY, sc->rtsx_mem_res_id, 3735 sc->rtsx_mem_res); 3736 rtsx_dma_free(sc); 3737 destroy_rtsx_irq_res: 3738 callout_drain(&sc->rtsx_timeout_callout); 3739 bus_release_resource(dev, SYS_RES_IRQ, sc->rtsx_irq_res_id, 3740 sc->rtsx_irq_res); 3741 pci_release_msi(dev); 3742 RTSX_LOCK_DESTROY(sc); 3743 3744 return (ENXIO); 3745 } 3746 3747 static int 3748 rtsx_detach(device_t dev) 3749 { 3750 struct rtsx_softc *sc = device_get_softc(dev); 3751 int error; 3752 3753 if (bootverbose) 3754 device_printf(dev, "Detach - Vendor ID: 0x%x - Device ID: 0x%x\n", 3755 pci_get_vendor(dev), sc->rtsx_device_id); 3756 3757 /* Disable interrupts. */ 3758 sc->rtsx_intr_enabled = 0; 3759 WRITE4(sc, RTSX_BIER, sc->rtsx_intr_enabled); 3760 3761 /* Stop device. */ 3762 error = device_delete_children(sc->rtsx_dev); 3763 sc->rtsx_mmc_dev = NULL; 3764 if (error) 3765 return (error); 3766 3767 taskqueue_drain_timeout(taskqueue_swi_giant, &sc->rtsx_card_insert_task); 3768 taskqueue_drain(taskqueue_swi_giant, &sc->rtsx_card_remove_task); 3769 3770 /* Teardown the state in our softc created in our attach routine. */ 3771 rtsx_dma_free(sc); 3772 if (sc->rtsx_mem_res != NULL) 3773 bus_release_resource(dev, SYS_RES_MEMORY, sc->rtsx_mem_res_id, 3774 sc->rtsx_mem_res); 3775 if (sc->rtsx_irq_cookie != NULL) 3776 bus_teardown_intr(dev, sc->rtsx_irq_res, sc->rtsx_irq_cookie); 3777 if (sc->rtsx_irq_res != NULL) { 3778 callout_drain(&sc->rtsx_timeout_callout); 3779 bus_release_resource(dev, SYS_RES_IRQ, sc->rtsx_irq_res_id, 3780 sc->rtsx_irq_res); 3781 pci_release_msi(dev); 3782 } 3783 RTSX_LOCK_DESTROY(sc); 3784 #ifdef MMCCAM 3785 mmc_cam_sim_free(&sc->rtsx_mmc_sim); 3786 #endif /* MMCCAM */ 3787 3788 return (0); 3789 } 3790 3791 static int 3792 rtsx_shutdown(device_t dev) 3793 { 3794 if (bootverbose) 3795 device_printf(dev, "Shutdown\n"); 3796 3797 return (0); 3798 } 3799 3800 /* 3801 * Device suspend routine. 3802 */ 3803 static int 3804 rtsx_suspend(device_t dev) 3805 { 3806 struct rtsx_softc *sc = device_get_softc(dev); 3807 3808 device_printf(dev, "Suspend\n"); 3809 3810 #ifdef MMCCAM 3811 if (sc->rtsx_ccb != NULL) { 3812 device_printf(dev, "Request in progress: CMD%u, rtsr_intr_status: 0x%08x\n", 3813 sc->rtsx_ccb->mmcio.cmd.opcode, sc->rtsx_intr_status); 3814 } 3815 #else /* !MMCCAM */ 3816 if (sc->rtsx_req != NULL) { 3817 device_printf(dev, "Request in progress: CMD%u, rtsr_intr_status: 0x%08x\n", 3818 sc->rtsx_req->cmd->opcode, sc->rtsx_intr_status); 3819 } 3820 #endif /* MMCCAM */ 3821 3822 bus_generic_suspend(dev); 3823 3824 return (0); 3825 } 3826 3827 /* 3828 * Device resume routine. 3829 */ 3830 static int 3831 rtsx_resume(device_t dev) 3832 { 3833 device_printf(dev, "Resume\n"); 3834 3835 rtsx_init(device_get_softc(dev)); 3836 3837 bus_generic_resume(dev); 3838 3839 return (0); 3840 } 3841 3842 static device_method_t rtsx_methods[] = { 3843 /* Device interface */ 3844 DEVMETHOD(device_probe, rtsx_probe), 3845 DEVMETHOD(device_attach, rtsx_attach), 3846 DEVMETHOD(device_detach, rtsx_detach), 3847 DEVMETHOD(device_shutdown, rtsx_shutdown), 3848 DEVMETHOD(device_suspend, rtsx_suspend), 3849 DEVMETHOD(device_resume, rtsx_resume), 3850 3851 /* Bus interface */ 3852 DEVMETHOD(bus_read_ivar, rtsx_read_ivar), 3853 DEVMETHOD(bus_write_ivar, rtsx_write_ivar), 3854 3855 #ifndef MMCCAM 3856 /* MMC bridge interface */ 3857 DEVMETHOD(mmcbr_update_ios, rtsx_mmcbr_update_ios), 3858 DEVMETHOD(mmcbr_switch_vccq, rtsx_mmcbr_switch_vccq), 3859 DEVMETHOD(mmcbr_tune, rtsx_mmcbr_tune), 3860 DEVMETHOD(mmcbr_retune, rtsx_mmcbr_retune), 3861 DEVMETHOD(mmcbr_request, rtsx_mmcbr_request), 3862 DEVMETHOD(mmcbr_get_ro, rtsx_mmcbr_get_ro), 3863 DEVMETHOD(mmcbr_acquire_host, rtsx_mmcbr_acquire_host), 3864 DEVMETHOD(mmcbr_release_host, rtsx_mmcbr_release_host), 3865 #endif /* !MMCCAM */ 3866 3867 #ifdef MMCCAM 3868 /* MMCCAM interface */ 3869 DEVMETHOD(mmc_sim_get_tran_settings, rtsx_get_tran_settings), 3870 DEVMETHOD(mmc_sim_set_tran_settings, rtsx_set_tran_settings), 3871 DEVMETHOD(mmc_sim_cam_request, rtsx_cam_request), 3872 #endif /* MMCCAM */ 3873 3874 DEVMETHOD_END 3875 }; 3876 3877 static devclass_t rtsx_devclass; 3878 3879 DEFINE_CLASS_0(rtsx, rtsx_driver, rtsx_methods, sizeof(struct rtsx_softc)); 3880 DRIVER_MODULE(rtsx, pci, rtsx_driver, rtsx_devclass, NULL, NULL); 3881 #ifndef MMCCAM 3882 MMC_DECLARE_BRIDGE(rtsx); 3883 #endif /* !MMCCAM */ 3884