1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 5 * Copyright (c) 2012 Stefan Sperling <stsp@openbsd.org> 6 * Copyright (c) 2020 Henri Hennebert <hlh@restart.be> 7 * Copyright (c) 2020 Gary Jennejohn <gj@freebsd.org> 8 * Copyright (c) 2020 Jesper Schmitz Mouridsen <jsm@FreeBSD.org> 9 * All rights reserved. 10 * 11 * Patch from: 12 * - Lutz Bichler <Lutz.Bichler@gmail.com> 13 * 14 * Base on OpenBSD /sys/dev/pci/rtsx_pci.c & /dev/ic/rtsx.c 15 * on Linux /drivers/mmc/host/rtsx_pci_sdmmc.c, 16 * /include/linux/rtsx_pci.h & 17 * /drivers/misc/cardreader/rtsx_pcr.c 18 * on NetBSD /sys/dev/ic/rtsx.c 19 * 20 * Permission to use, copy, modify, and distribute this software for any 21 * purpose with or without fee is hereby granted, provided that the above 22 * copyright notice and this permission notice appear in all copies. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 */ 36 37 #include <sys/cdefs.h> 38 #include <sys/param.h> 39 #include <sys/module.h> 40 #include <sys/systm.h> /* For FreeBSD 11 */ 41 #include <sys/types.h> /* For FreeBSD 11 */ 42 #include <sys/errno.h> 43 #include <sys/kernel.h> 44 #include <sys/bus.h> 45 #include <sys/endian.h> 46 #include <machine/bus.h> 47 #include <sys/mutex.h> 48 #include <sys/malloc.h> 49 #include <sys/rman.h> 50 #include <sys/queue.h> 51 #include <sys/taskqueue.h> 52 #include <sys/sysctl.h> 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pcireg.h> 55 #include <dev/mmc/bridge.h> 56 #include <dev/mmc/mmcreg.h> 57 #include <dev/mmc/mmcbrvar.h> 58 #include <machine/_inttypes.h> 59 60 #include "opt_mmccam.h" 61 62 #ifdef MMCCAM 63 #include <cam/cam.h> 64 #include <cam/cam_ccb.h> 65 #include <cam/cam_debug.h> 66 #include <cam/cam_sim.h> 67 #include <cam/cam_xpt_sim.h> 68 #include <cam/mmc/mmc_sim.h> 69 #include "mmc_sim_if.h" 70 #endif /* MMCCAM */ 71 72 #include "rtsxreg.h" 73 74 /* The softc holds our per-instance data. */ 75 struct rtsx_softc { 76 struct mtx rtsx_mtx; /* device mutex */ 77 device_t rtsx_dev; /* device */ 78 uint16_t rtsx_flags; /* device flags */ 79 uint16_t rtsx_device_id; /* device ID */ 80 device_t rtsx_mmc_dev; /* device of mmc bus */ 81 uint32_t rtsx_intr_enabled; /* enabled interrupts */ 82 uint32_t rtsx_intr_status; /* soft interrupt status */ 83 int rtsx_irq_res_id; /* bus IRQ resource id */ 84 struct resource *rtsx_irq_res; /* bus IRQ resource */ 85 void *rtsx_irq_cookie; /* bus IRQ resource cookie */ 86 struct callout rtsx_timeout_callout; /* callout for timeout */ 87 int rtsx_timeout_cmd; /* interrupt timeout for setup commands */ 88 int rtsx_timeout_io; /* interrupt timeout for I/O commands */ 89 void (*rtsx_intr_trans_ok)(struct rtsx_softc *sc); 90 /* function to call if transfer succeed */ 91 void (*rtsx_intr_trans_ko)(struct rtsx_softc *sc); 92 /* function to call if transfer fail */ 93 94 struct timeout_task 95 rtsx_card_insert_task; /* card insert delayed task */ 96 struct task rtsx_card_remove_task; /* card remove task */ 97 98 int rtsx_mem_res_id; /* bus memory resource id */ 99 struct resource *rtsx_mem_res; /* bus memory resource */ 100 bus_space_tag_t rtsx_mem_btag; /* host register set tag */ 101 bus_space_handle_t rtsx_mem_bhandle; /* host register set handle */ 102 103 bus_dma_tag_t rtsx_cmd_dma_tag; /* DMA tag for command transfer */ 104 bus_dmamap_t rtsx_cmd_dmamap; /* DMA map for command transfer */ 105 void *rtsx_cmd_dmamem; /* DMA mem for command transfer */ 106 bus_addr_t rtsx_cmd_buffer; /* device visible address of the DMA segment */ 107 int rtsx_cmd_index; /* index in rtsx_cmd_buffer */ 108 109 bus_dma_tag_t rtsx_data_dma_tag; /* DMA tag for data transfer */ 110 bus_dmamap_t rtsx_data_dmamap; /* DMA map for data transfer */ 111 void *rtsx_data_dmamem; /* DMA mem for data transfer */ 112 bus_addr_t rtsx_data_buffer; /* device visible address of the DMA segment */ 113 114 #ifdef MMCCAM 115 union ccb *rtsx_ccb; /* CAM control block */ 116 struct mmc_sim rtsx_mmc_sim; /* CAM generic sim */ 117 struct mmc_request rtsx_cam_req; /* CAM MMC request */ 118 #endif /* MMCCAM */ 119 120 struct mmc_request *rtsx_req; /* MMC request */ 121 struct mmc_host rtsx_host; /* host parameters */ 122 int rtsx_pcie_cap; /* PCIe capability offset */ 123 int8_t rtsx_bus_busy; /* bus busy status */ 124 int8_t rtsx_ios_bus_width; /* current host.ios.bus_width */ 125 int32_t rtsx_ios_clock; /* current host.ios.clock */ 126 int8_t rtsx_ios_power_mode; /* current host.ios.power mode */ 127 int8_t rtsx_ios_timing; /* current host.ios.timing */ 128 int8_t rtsx_ios_vccq; /* current host.ios.vccq */ 129 uint8_t rtsx_read_only; /* card read only status */ 130 uint8_t rtsx_inversion; /* inversion of card detection and read only status */ 131 uint8_t rtsx_force_timing; /* force bus_timing_uhs_sdr50 */ 132 uint8_t rtsx_debug_mask; /* debugging mask */ 133 #define RTSX_DEBUG_BASIC 0x01 /* debug basic flow */ 134 #define RTSX_TRACE_SD_CMD 0x02 /* trace SD commands */ 135 #define RTSX_DEBUG_TUNING 0x04 /* debug tuning */ 136 #ifdef MMCCAM 137 uint8_t rtsx_cam_status; /* CAM status - 1 if card in use */ 138 #endif /* MMCCAM */ 139 uint64_t rtsx_read_count; /* count of read operations */ 140 uint64_t rtsx_write_count; /* count of write operations */ 141 bool rtsx_discovery_mode; /* are we in discovery mode? */ 142 bool rtsx_tuning_mode; /* are we tuning */ 143 bool rtsx_double_clk; /* double clock freqency */ 144 bool rtsx_vpclk; /* voltage at Pulse-width Modulation(PWM) clock? */ 145 uint8_t rtsx_ssc_depth; /* Spread spectrum clocking depth */ 146 uint8_t rtsx_card_drive_sel; /* value for RTSX_CARD_DRIVE_SEL */ 147 uint8_t rtsx_sd30_drive_sel_3v3;/* value for RTSX_SD30_DRIVE_SEL */ 148 }; 149 150 /* rtsx_flags values */ 151 #define RTSX_F_DEFAULT 0x0000 152 #define RTSX_F_CARD_PRESENT 0x0001 153 #define RTSX_F_SDIO_SUPPORT 0x0002 154 #define RTSX_F_VERSION_A 0x0004 155 #define RTSX_F_VERSION_B 0x0008 156 #define RTSX_F_VERSION_C 0x0010 157 #define RTSX_F_VERSION_D 0x0020 158 #define RTSX_F_8411B_QFN48 0x0040 159 #define RTSX_F_REVERSE_SOCKET 0x0080 160 161 #define RTSX_REALTEK 0x10ec 162 #define RTSX_RTS5209 0x5209 163 #define RTSX_RTS5227 0x5227 164 #define RTSX_RTS5229 0x5229 165 #define RTSX_RTS522A 0x522a 166 #define RTSX_RTS525A 0x525a 167 #define RTSX_RTS5249 0x5249 168 #define RTSX_RTS5260 0x5260 169 #define RTSX_RTL8402 0x5286 170 #define RTSX_RTL8411 0x5289 171 #define RTSX_RTL8411B 0x5287 172 173 #define RTSX_VERSION "2.1g" 174 175 static const struct rtsx_pciids { 176 uint16_t device_id; 177 const char *desc; 178 } rtsx_ids[] = { 179 { RTSX_RTS5209, RTSX_VERSION " Realtek RTS5209 PCIe SD Card Reader" }, 180 { RTSX_RTS5227, RTSX_VERSION " Realtek RTS5227 PCIe SD Card Reader" }, 181 { RTSX_RTS5229, RTSX_VERSION " Realtek RTS5229 PCIe SD Card Reader" }, 182 { RTSX_RTS522A, RTSX_VERSION " Realtek RTS522A PCIe SD Card Reader" }, 183 { RTSX_RTS525A, RTSX_VERSION " Realtek RTS525A PCIe SD Card Reader" }, 184 { RTSX_RTS5249, RTSX_VERSION " Realtek RTS5249 PCIe SD Card Reader" }, 185 { RTSX_RTS5260, RTSX_VERSION " Realtek RTS5260 PCIe SD Card Reader" }, 186 { RTSX_RTL8402, RTSX_VERSION " Realtek RTL8402 PCIe SD Card Reader" }, 187 { RTSX_RTL8411, RTSX_VERSION " Realtek RTL8411 PCIe SD Card Reader" }, 188 { RTSX_RTL8411B, RTSX_VERSION " Realtek RTL8411B PCIe SD Card Reader" }, 189 }; 190 191 /* See `kenv | grep smbios.system` */ 192 static const struct rtsx_inversion_model { 193 char *maker; 194 char *family; 195 char *product; 196 } rtsx_inversion_models[] = { 197 { "LENOVO", "ThinkPad T470p", "20J7S0PM00"}, 198 { "LENOVO", "ThinkPad X13 Gen 1", "20UF000QRT"}, 199 { NULL, NULL, NULL} 200 }; 201 202 static int rtsx_dma_alloc(struct rtsx_softc *sc); 203 static void rtsx_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 204 static void rtsx_dma_free(struct rtsx_softc *sc); 205 static void rtsx_intr(void *arg); 206 static void rtsx_handle_card_present(struct rtsx_softc *sc); 207 static void rtsx_card_task(void *arg, int pending __unused); 208 static bool rtsx_is_card_present(struct rtsx_softc *sc); 209 static int rtsx_init(struct rtsx_softc *sc); 210 static int rtsx_map_sd_drive(int index); 211 static int rtsx_rts5227_fill_driving(struct rtsx_softc *sc); 212 static int rtsx_rts5249_fill_driving(struct rtsx_softc *sc); 213 static int rtsx_rts5260_fill_driving(struct rtsx_softc *sc); 214 static int rtsx_read(struct rtsx_softc *, uint16_t, uint8_t *); 215 static int rtsx_read_cfg(struct rtsx_softc *sc, uint8_t func, uint16_t addr, uint32_t *val); 216 static int rtsx_write(struct rtsx_softc *sc, uint16_t addr, uint8_t mask, uint8_t val); 217 static int rtsx_read_phy(struct rtsx_softc *sc, uint8_t addr, uint16_t *val); 218 static int rtsx_write_phy(struct rtsx_softc *sc, uint8_t addr, uint16_t val); 219 static int rtsx_bus_power_off(struct rtsx_softc *sc); 220 static int rtsx_bus_power_on(struct rtsx_softc *sc); 221 static int rtsx_set_bus_width(struct rtsx_softc *sc, enum mmc_bus_width width); 222 static int rtsx_set_sd_timing(struct rtsx_softc *sc, enum mmc_bus_timing timing); 223 static int rtsx_set_sd_clock(struct rtsx_softc *sc, uint32_t freq); 224 static int rtsx_stop_sd_clock(struct rtsx_softc *sc); 225 static int rtsx_switch_sd_clock(struct rtsx_softc *sc, uint8_t clk, uint8_t n, uint8_t div, uint8_t mcu); 226 #ifndef MMCCAM 227 static void rtsx_sd_change_tx_phase(struct rtsx_softc *sc, uint8_t sample_point); 228 static void rtsx_sd_change_rx_phase(struct rtsx_softc *sc, uint8_t sample_point); 229 static void rtsx_sd_tuning_rx_phase(struct rtsx_softc *sc, uint32_t *phase_map); 230 static int rtsx_sd_tuning_rx_cmd(struct rtsx_softc *sc, uint8_t sample_point); 231 static int rtsx_sd_tuning_rx_cmd_wait(struct rtsx_softc *sc, struct mmc_command *cmd); 232 static void rtsx_sd_tuning_rx_cmd_wakeup(struct rtsx_softc *sc); 233 static void rtsx_sd_wait_data_idle(struct rtsx_softc *sc); 234 static uint8_t rtsx_sd_search_final_rx_phase(struct rtsx_softc *sc, uint32_t phase_map); 235 static int rtsx_sd_get_rx_phase_len(uint32_t phase_map, int start_bit); 236 #endif /* !MMCCAM */ 237 #if 0 /* For led */ 238 static int rtsx_led_enable(struct rtsx_softc *sc); 239 static int rtsx_led_disable(struct rtsx_softc *sc); 240 #endif /* For led */ 241 static uint8_t rtsx_response_type(uint16_t mmc_rsp); 242 static void rtsx_init_cmd(struct rtsx_softc *sc, struct mmc_command *cmd); 243 static void rtsx_push_cmd(struct rtsx_softc *sc, uint8_t cmd, uint16_t reg, 244 uint8_t mask, uint8_t data); 245 static void rtsx_set_cmd_data_len(struct rtsx_softc *sc, uint16_t block_cnt, uint16_t byte_cnt); 246 static void rtsx_send_cmd(struct rtsx_softc *sc); 247 static void rtsx_ret_resp(struct rtsx_softc *sc); 248 static void rtsx_set_resp(struct rtsx_softc *sc, struct mmc_command *cmd); 249 static void rtsx_stop_cmd(struct rtsx_softc *sc); 250 static void rtsx_clear_error(struct rtsx_softc *sc); 251 static void rtsx_req_done(struct rtsx_softc *sc); 252 static int rtsx_send_req(struct rtsx_softc *sc, struct mmc_command *cmd); 253 static int rtsx_xfer_short(struct rtsx_softc *sc, struct mmc_command *cmd); 254 static void rtsx_ask_ppbuf_part1(struct rtsx_softc *sc); 255 static void rtsx_get_ppbuf_part1(struct rtsx_softc *sc); 256 static void rtsx_get_ppbuf_part2(struct rtsx_softc *sc); 257 static void rtsx_put_ppbuf_part1(struct rtsx_softc *sc); 258 static void rtsx_put_ppbuf_part2(struct rtsx_softc *sc); 259 static void rtsx_write_ppbuf(struct rtsx_softc *sc); 260 static int rtsx_xfer(struct rtsx_softc *sc, struct mmc_command *cmd); 261 static void rtsx_xfer_begin(struct rtsx_softc *sc); 262 static void rtsx_xfer_start(struct rtsx_softc *sc); 263 static void rtsx_xfer_finish(struct rtsx_softc *sc); 264 static void rtsx_timeout(void *arg); 265 266 #ifdef MMCCAM 267 static int rtsx_get_tran_settings(device_t dev, struct ccb_trans_settings_mmc *cts); 268 static int rtsx_set_tran_settings(device_t dev, struct ccb_trans_settings_mmc *cts); 269 static int rtsx_cam_request(device_t dev, union ccb *ccb); 270 #endif /* MMCCAM */ 271 272 static int rtsx_read_ivar(device_t bus, device_t child, int which, uintptr_t *result); 273 static int rtsx_write_ivar(device_t bus, device_t child, int which, uintptr_t value); 274 275 static int rtsx_mmcbr_update_ios(device_t bus, device_t child __unused); 276 static int rtsx_mmcbr_switch_vccq(device_t bus, device_t child __unused); 277 static int rtsx_mmcbr_request(device_t bus, device_t child __unused, struct mmc_request *req); 278 #ifndef MMCCAM 279 static int rtsx_mmcbr_tune(device_t bus, device_t child __unused, bool hs400 __unused); 280 static int rtsx_mmcbr_retune(device_t bus, device_t child __unused, bool reset __unused); 281 static int rtsx_mmcbr_get_ro(device_t bus, device_t child __unused); 282 static int rtsx_mmcbr_acquire_host(device_t bus, device_t child __unused); 283 static int rtsx_mmcbr_release_host(device_t bus, device_t child __unused); 284 #endif /* !MMCCAM */ 285 286 static int rtsx_probe(device_t dev); 287 static int rtsx_attach(device_t dev); 288 static int rtsx_detach(device_t dev); 289 static int rtsx_shutdown(device_t dev); 290 static int rtsx_suspend(device_t dev); 291 static int rtsx_resume(device_t dev); 292 293 #define RTSX_LOCK_INIT(_sc) mtx_init(&(_sc)->rtsx_mtx, \ 294 device_get_nameunit(sc->rtsx_dev), "rtsx", MTX_DEF) 295 #define RTSX_LOCK(_sc) mtx_lock(&(_sc)->rtsx_mtx) 296 #define RTSX_UNLOCK(_sc) mtx_unlock(&(_sc)->rtsx_mtx) 297 #define RTSX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rtsx_mtx) 298 299 #define RTSX_SDCLK_OFF 0 300 #define RTSX_SDCLK_250KHZ 250000 301 #define RTSX_SDCLK_400KHZ 400000 302 #define RTSX_SDCLK_25MHZ 25000000 303 #define RTSX_SDCLK_50MHZ 50000000 304 #define RTSX_SDCLK_100MHZ 100000000 305 #define RTSX_SDCLK_208MHZ 208000000 306 307 #define RTSX_MIN_DIV_N 80 308 #define RTSX_MAX_DIV_N 208 309 310 #define RTSX_MAX_DATA_BLKLEN 512 311 312 #define RTSX_DMA_ALIGN 4 313 #define RTSX_HOSTCMD_MAX 256 314 #define RTSX_DMA_CMD_BIFSIZE (sizeof(uint32_t) * RTSX_HOSTCMD_MAX) 315 #define RTSX_DMA_DATA_BUFSIZE MAXPHYS 316 317 #define ISSET(t, f) ((t) & (f)) 318 319 #define READ4(sc, reg) \ 320 (bus_space_read_4((sc)->rtsx_mem_btag, (sc)->rtsx_mem_bhandle, (reg))) 321 #define WRITE4(sc, reg, val) \ 322 (bus_space_write_4((sc)->rtsx_mem_btag, (sc)->rtsx_mem_bhandle, (reg), (val))) 323 324 #define RTSX_READ(sc, reg, val) \ 325 do { \ 326 int err = rtsx_read((sc), (reg), (val)); \ 327 if (err) \ 328 return (err); \ 329 } while (0) 330 331 #define RTSX_WRITE(sc, reg, val) \ 332 do { \ 333 int err = rtsx_write((sc), (reg), 0xff, (val)); \ 334 if (err) \ 335 return (err); \ 336 } while (0) 337 #define RTSX_CLR(sc, reg, bits) \ 338 do { \ 339 int err = rtsx_write((sc), (reg), (bits), 0); \ 340 if (err) \ 341 return (err); \ 342 } while (0) 343 344 #define RTSX_SET(sc, reg, bits) \ 345 do { \ 346 int err = rtsx_write((sc), (reg), (bits), 0xff);\ 347 if (err) \ 348 return (err); \ 349 } while (0) 350 351 #define RTSX_BITOP(sc, reg, mask, bits) \ 352 do { \ 353 int err = rtsx_write((sc), (reg), (mask), (bits)); \ 354 if (err) \ 355 return (err); \ 356 } while (0) 357 358 /* 359 * We use two DMA buffers: a command buffer and a data buffer. 360 * 361 * The command buffer contains a command queue for the host controller, 362 * which describes SD/MMC commands to run, and other parameters. The chip 363 * runs the command queue when a special bit in the RTSX_HCBAR register is 364 * set and signals completion with the RTSX_TRANS_OK_INT interrupt. 365 * Each command is encoded as a 4 byte sequence containing command number 366 * (read, write, or check a host controller register), a register address, 367 * and a data bit-mask and value. 368 * SD/MMC commands which do not transfer any data from/to the card only use 369 * the command buffer. 370 * 371 * The data buffer is used for transfer longer than 512. Data transfer is 372 * controlled via the RTSX_HDBAR register and completion is signalled by 373 * the RTSX_TRANS_OK_INT interrupt. 374 * 375 * The chip is unable to perform DMA above 4GB. 376 */ 377 378 /* 379 * Main commands in the usual seqence used: 380 * 381 * CMD0 Go idle state 382 * CMD8 Send interface condition 383 * CMD55 Application Command for next ACMD 384 * ACMD41 Send Operation Conditions Register (OCR: voltage profile of the card) 385 * CMD2 Send Card Identification (CID) Register 386 * CMD3 Send relative address 387 * CMD9 Send Card Specific Data (CSD) 388 * CMD13 Send status (32 bits - bit 25: card password protected) 389 * CMD7 Select card (before Get card SCR) 390 * ACMD51 Send SCR (SD CARD Configuration Register - [51:48]: Bus widths supported) 391 * CMD6 SD switch function 392 * ACMD13 Send SD status (512 bits) 393 * ACMD42 Set/Clear card detect 394 * ACMD6 Set bus width 395 * CMD19 Send tuning block 396 * CMD12 Stop transmission 397 * 398 * CMD17 Read single block (<=512) 399 * CMD18 Read multiple blocks (>512) 400 * CMD24 Write single block (<=512) 401 * CMD25 Write multiple blocks (>512) 402 * 403 * CMD52 IO R/W direct 404 * CMD5 Send Operation Conditions 405 */ 406 407 static int 408 rtsx_dma_alloc(struct rtsx_softc *sc) 409 { 410 int error = 0; 411 412 error = bus_dma_tag_create(bus_get_dma_tag(sc->rtsx_dev), /* inherit from parent */ 413 RTSX_DMA_ALIGN, 0, /* alignment, boundary */ 414 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 415 BUS_SPACE_MAXADDR, /* highaddr */ 416 NULL, NULL, /* filter, filterarg */ 417 RTSX_DMA_CMD_BIFSIZE, 1, /* maxsize, nsegments */ 418 RTSX_DMA_CMD_BIFSIZE, /* maxsegsize */ 419 0, /* flags */ 420 NULL, NULL, /* lockfunc, lockarg */ 421 &sc->rtsx_cmd_dma_tag); 422 if (error) { 423 device_printf(sc->rtsx_dev, 424 "Can't create cmd parent DMA tag\n"); 425 return (error); 426 } 427 error = bus_dmamem_alloc(sc->rtsx_cmd_dma_tag, /* DMA tag */ 428 &sc->rtsx_cmd_dmamem, /* will hold the KVA pointer */ 429 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, /* flags */ 430 &sc->rtsx_cmd_dmamap); /* DMA map */ 431 if (error) { 432 device_printf(sc->rtsx_dev, 433 "Can't create DMA map for command transfer\n"); 434 goto destroy_cmd_dma_tag; 435 436 } 437 error = bus_dmamap_load(sc->rtsx_cmd_dma_tag, /* DMA tag */ 438 sc->rtsx_cmd_dmamap, /* DMA map */ 439 sc->rtsx_cmd_dmamem, /* KVA pointer to be mapped */ 440 RTSX_DMA_CMD_BIFSIZE, /* size of buffer */ 441 rtsx_dmamap_cb, /* callback */ 442 &sc->rtsx_cmd_buffer, /* first arg of callback */ 443 0); /* flags */ 444 if (error || sc->rtsx_cmd_buffer == 0) { 445 device_printf(sc->rtsx_dev, 446 "Can't load DMA memory for command transfer\n"); 447 error = (error) ? error : EFAULT; 448 goto destroy_cmd_dmamem_alloc; 449 } 450 451 error = bus_dma_tag_create(bus_get_dma_tag(sc->rtsx_dev), /* inherit from parent */ 452 RTSX_DMA_DATA_BUFSIZE, 0, /* alignment, boundary */ 453 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 454 BUS_SPACE_MAXADDR, /* highaddr */ 455 NULL, NULL, /* filter, filterarg */ 456 RTSX_DMA_DATA_BUFSIZE, 1, /* maxsize, nsegments */ 457 RTSX_DMA_DATA_BUFSIZE, /* maxsegsize */ 458 0, /* flags */ 459 NULL, NULL, /* lockfunc, lockarg */ 460 &sc->rtsx_data_dma_tag); 461 if (error) { 462 device_printf(sc->rtsx_dev, 463 "Can't create data parent DMA tag\n"); 464 goto destroy_cmd_dmamap_load; 465 } 466 error = bus_dmamem_alloc(sc->rtsx_data_dma_tag, /* DMA tag */ 467 &sc->rtsx_data_dmamem, /* will hold the KVA pointer */ 468 BUS_DMA_WAITOK | BUS_DMA_ZERO, /* flags */ 469 &sc->rtsx_data_dmamap); /* DMA map */ 470 if (error) { 471 device_printf(sc->rtsx_dev, 472 "Can't create DMA map for data transfer\n"); 473 goto destroy_data_dma_tag; 474 } 475 error = bus_dmamap_load(sc->rtsx_data_dma_tag, /* DMA tag */ 476 sc->rtsx_data_dmamap, /* DMA map */ 477 sc->rtsx_data_dmamem, /* KVA pointer to be mapped */ 478 RTSX_DMA_DATA_BUFSIZE, /* size of buffer */ 479 rtsx_dmamap_cb, /* callback */ 480 &sc->rtsx_data_buffer, /* first arg of callback */ 481 0); /* flags */ 482 if (error || sc->rtsx_data_buffer == 0) { 483 device_printf(sc->rtsx_dev, 484 "Can't load DMA memory for data transfer\n"); 485 error = (error) ? error : EFAULT; 486 goto destroy_data_dmamem_alloc; 487 } 488 return (error); 489 490 destroy_data_dmamem_alloc: 491 bus_dmamem_free(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamem, sc->rtsx_data_dmamap); 492 destroy_data_dma_tag: 493 bus_dma_tag_destroy(sc->rtsx_data_dma_tag); 494 destroy_cmd_dmamap_load: 495 bus_dmamap_unload(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap); 496 destroy_cmd_dmamem_alloc: 497 bus_dmamem_free(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamem, sc->rtsx_cmd_dmamap); 498 destroy_cmd_dma_tag: 499 bus_dma_tag_destroy(sc->rtsx_cmd_dma_tag); 500 501 return (error); 502 } 503 504 static void 505 rtsx_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 506 { 507 if (error) { 508 printf("rtsx_dmamap_cb: error %d\n", error); 509 return; 510 } 511 *(bus_addr_t *)arg = segs[0].ds_addr; 512 } 513 514 static void 515 rtsx_dma_free(struct rtsx_softc *sc) 516 { 517 if (sc->rtsx_cmd_dma_tag != NULL) { 518 if (sc->rtsx_cmd_dmamap != NULL) 519 bus_dmamap_unload(sc->rtsx_cmd_dma_tag, 520 sc->rtsx_cmd_dmamap); 521 if (sc->rtsx_cmd_dmamem != NULL) 522 bus_dmamem_free(sc->rtsx_cmd_dma_tag, 523 sc->rtsx_cmd_dmamem, 524 sc->rtsx_cmd_dmamap); 525 sc->rtsx_cmd_dmamap = NULL; 526 sc->rtsx_cmd_dmamem = NULL; 527 sc->rtsx_cmd_buffer = 0; 528 bus_dma_tag_destroy(sc->rtsx_cmd_dma_tag); 529 sc->rtsx_cmd_dma_tag = NULL; 530 } 531 if (sc->rtsx_data_dma_tag != NULL) { 532 if (sc->rtsx_data_dmamap != NULL) 533 bus_dmamap_unload(sc->rtsx_data_dma_tag, 534 sc->rtsx_data_dmamap); 535 if (sc->rtsx_data_dmamem != NULL) 536 bus_dmamem_free(sc->rtsx_data_dma_tag, 537 sc->rtsx_data_dmamem, 538 sc->rtsx_data_dmamap); 539 sc->rtsx_data_dmamap = NULL; 540 sc->rtsx_data_dmamem = NULL; 541 sc->rtsx_data_buffer = 0; 542 bus_dma_tag_destroy(sc->rtsx_data_dma_tag); 543 sc->rtsx_data_dma_tag = NULL; 544 } 545 } 546 547 static void 548 rtsx_intr(void *arg) 549 { 550 struct rtsx_softc *sc = arg; 551 uint32_t enabled; 552 uint32_t status; 553 554 RTSX_LOCK(sc); 555 556 enabled = sc->rtsx_intr_enabled; 557 status = READ4(sc, RTSX_BIPR); /* read Bus Interrupt Pending Register */ 558 sc->rtsx_intr_status = status; 559 560 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 561 device_printf(sc->rtsx_dev, "Interrupt handler - enabled: 0x%08x, status: 0x%08x\n", enabled, status); 562 563 /* Ack interrupts. */ 564 WRITE4(sc, RTSX_BIPR, status); 565 566 if (((enabled & status) == 0) || status == 0xffffffff) { 567 device_printf(sc->rtsx_dev, "Spurious interrupt - enabled: 0x%08x, status: 0x%08x\n", enabled, status); 568 RTSX_UNLOCK(sc); 569 return; 570 } 571 572 /* Detect write protect. */ 573 if (status & RTSX_SD_WRITE_PROTECT) 574 sc->rtsx_read_only = 1; 575 else 576 sc->rtsx_read_only = 0; 577 578 /* Start task to handle SD card status change (from dwmmc.c). */ 579 if (status & RTSX_SD_INT) { 580 device_printf(sc->rtsx_dev, "Interrupt card inserted/removed\n"); 581 rtsx_handle_card_present(sc); 582 } 583 584 if (sc->rtsx_req == NULL) { 585 RTSX_UNLOCK(sc); 586 return; 587 } 588 589 if (status & RTSX_TRANS_OK_INT) { 590 sc->rtsx_req->cmd->error = MMC_ERR_NONE; 591 if (sc->rtsx_intr_trans_ok != NULL) 592 sc->rtsx_intr_trans_ok(sc); 593 } else if (status & RTSX_TRANS_FAIL_INT) { 594 uint8_t stat1; 595 sc->rtsx_req->cmd->error = MMC_ERR_FAILED; 596 if (rtsx_read(sc, RTSX_SD_STAT1, &stat1) == 0 && 597 (stat1 & RTSX_SD_CRC_ERR)) { 598 device_printf(sc->rtsx_dev, "CRC error\n"); 599 sc->rtsx_req->cmd->error = MMC_ERR_BADCRC; 600 } 601 if (!sc->rtsx_tuning_mode) 602 device_printf(sc->rtsx_dev, "Transfer fail - status: 0x%08x\n", status); 603 rtsx_stop_cmd(sc); 604 if (sc->rtsx_intr_trans_ko != NULL) 605 sc->rtsx_intr_trans_ko(sc); 606 } 607 608 RTSX_UNLOCK(sc); 609 } 610 611 /* 612 * Function called from the IRQ handler (from dwmmc.c). 613 */ 614 static void 615 rtsx_handle_card_present(struct rtsx_softc *sc) 616 { 617 bool was_present; 618 bool is_present; 619 620 #ifdef MMCCAM 621 was_present = sc->rtsx_cam_status; 622 #else /* !MMCCAM */ 623 was_present = sc->rtsx_mmc_dev != NULL; 624 #endif /* MMCCAM */ 625 is_present = rtsx_is_card_present(sc); 626 if (is_present) 627 device_printf(sc->rtsx_dev, "Card present\n"); 628 else 629 device_printf(sc->rtsx_dev, "Card absent\n"); 630 631 if (!was_present && is_present) { 632 /* 633 * The delay is to debounce the card insert 634 * (sometimes the card detect pin stabilizes 635 * before the other pins have made good contact). 636 */ 637 taskqueue_enqueue_timeout(taskqueue_swi_giant, 638 &sc->rtsx_card_insert_task, -hz); 639 } else if (was_present && !is_present) { 640 taskqueue_enqueue(taskqueue_swi_giant, &sc->rtsx_card_remove_task); 641 } 642 } 643 644 /* 645 * This function is called at startup. 646 */ 647 static void 648 rtsx_card_task(void *arg, int pending __unused) 649 { 650 struct rtsx_softc *sc = arg; 651 652 if (rtsx_is_card_present(sc)) { 653 sc->rtsx_flags |= RTSX_F_CARD_PRESENT; 654 /* Card is present, attach if necessary. */ 655 #ifdef MMCCAM 656 if (sc->rtsx_cam_status == 0) { 657 #else /* !MMCCAM */ 658 if (sc->rtsx_mmc_dev == NULL) { 659 #endif /* MMCCAM */ 660 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 661 device_printf(sc->rtsx_dev, "Card inserted\n"); 662 663 sc->rtsx_read_count = sc->rtsx_write_count = 0; 664 #ifdef MMCCAM 665 sc->rtsx_cam_status = 1; 666 mmc_cam_sim_discover(&sc->rtsx_mmc_sim); 667 #else /* !MMCCAM */ 668 RTSX_LOCK(sc); 669 sc->rtsx_mmc_dev = device_add_child(sc->rtsx_dev, "mmc", -1); 670 RTSX_UNLOCK(sc); 671 if (sc->rtsx_mmc_dev == NULL) { 672 device_printf(sc->rtsx_dev, "Adding MMC bus failed\n"); 673 } else { 674 device_set_ivars(sc->rtsx_mmc_dev, sc); 675 device_probe_and_attach(sc->rtsx_mmc_dev); 676 } 677 #endif /* MMCCAM */ 678 } 679 } else { 680 sc->rtsx_flags &= ~RTSX_F_CARD_PRESENT; 681 /* Card isn't present, detach if necessary. */ 682 #ifdef MMCCAM 683 if (sc->rtsx_cam_status != 0) { 684 #else /* !MMCCAM */ 685 if (sc->rtsx_mmc_dev != NULL) { 686 #endif /* MMCCAM */ 687 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 688 device_printf(sc->rtsx_dev, "Card removed\n"); 689 690 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 691 device_printf(sc->rtsx_dev, "Read count: %" PRIu64 ", write count: %" PRIu64 "\n", 692 sc->rtsx_read_count, sc->rtsx_write_count); 693 #ifdef MMCCAM 694 sc->rtsx_cam_status = 0; 695 mmc_cam_sim_discover(&sc->rtsx_mmc_sim); 696 #else /* !MMCCAM */ 697 if (device_delete_child(sc->rtsx_dev, sc->rtsx_mmc_dev)) 698 device_printf(sc->rtsx_dev, "Detaching MMC bus failed\n"); 699 sc->rtsx_mmc_dev = NULL; 700 #endif /* MMCCAM */ 701 } 702 } 703 } 704 705 static bool 706 rtsx_is_card_present(struct rtsx_softc *sc) 707 { 708 uint32_t status; 709 710 status = READ4(sc, RTSX_BIPR); 711 if (sc->rtsx_inversion == 0) 712 return (status & RTSX_SD_EXIST); 713 else 714 return !(status & RTSX_SD_EXIST); 715 } 716 717 static int 718 rtsx_init(struct rtsx_softc *sc) 719 { 720 uint8_t version; 721 uint8_t val; 722 int error; 723 724 sc->rtsx_host.host_ocr = RTSX_SUPPORTED_VOLTAGE; 725 sc->rtsx_host.f_min = RTSX_SDCLK_250KHZ; 726 sc->rtsx_host.f_max = RTSX_SDCLK_208MHZ; 727 sc->rtsx_host.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_HSPEED | 728 MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 729 730 sc->rtsx_host.caps |= MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104; 731 if (sc->rtsx_device_id == RTSX_RTS5209) 732 sc->rtsx_host.caps |= MMC_CAP_8_BIT_DATA; 733 pci_find_cap(sc->rtsx_dev, PCIY_EXPRESS, &(sc->rtsx_pcie_cap)); 734 735 /* 736 * Check IC version. 737 */ 738 switch (sc->rtsx_device_id) { 739 case RTSX_RTS5229: 740 /* Read IC version from dummy register. */ 741 RTSX_READ(sc, RTSX_DUMMY_REG, &version); 742 if ((version & 0x0F) == RTSX_IC_VERSION_C) 743 sc->rtsx_flags |= RTSX_F_VERSION_C; 744 break; 745 case RTSX_RTS522A: 746 /* Read IC version from dummy register. */ 747 RTSX_READ(sc, RTSX_DUMMY_REG, &version); 748 if ((version & 0x0F) == RTSX_IC_VERSION_A) 749 sc->rtsx_flags |= RTSX_F_VERSION_A; 750 break; 751 case RTSX_RTS525A: 752 /* Read IC version from dummy register. */ 753 RTSX_READ(sc, RTSX_DUMMY_REG, &version); 754 if ((version & 0x0F) == RTSX_IC_VERSION_A) 755 sc->rtsx_flags |= RTSX_F_VERSION_A; 756 break; 757 case RTSX_RTL8411B: 758 RTSX_READ(sc, RTSX_RTL8411B_PACKAGE, &version); 759 if (version & RTSX_RTL8411B_QFN48) 760 sc->rtsx_flags |= RTSX_F_8411B_QFN48; 761 break; 762 } 763 764 /* 765 * Fetch vendor settings. 766 */ 767 /* 768 * Normally OEMs will set vendor setting to the config space 769 * of Realtek card reader in BIOS stage. This statement reads 770 * the setting and configure the internal registers according 771 * to it, to improve card reader's compatibility condition. 772 */ 773 sc->rtsx_card_drive_sel = RTSX_CARD_DRIVE_DEFAULT; 774 switch (sc->rtsx_device_id) { 775 uint32_t reg; 776 uint32_t reg1; 777 uint8_t reg3; 778 case RTSX_RTS5209: 779 sc->rtsx_card_drive_sel = RTSX_RTS5209_CARD_DRIVE_DEFAULT; 780 sc->rtsx_sd30_drive_sel_3v3 = RTSX_DRIVER_TYPE_D; 781 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG2, 4); 782 if (!(reg & 0x80)) { 783 sc->rtsx_card_drive_sel = (reg >> 8) & 0x3F; 784 sc->rtsx_sd30_drive_sel_3v3 = reg & 0x07; 785 } else if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) { 786 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg); 787 } 788 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 789 device_printf(sc->rtsx_dev, "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x\n", 790 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3); 791 break; 792 case RTSX_RTS5227: 793 case RTSX_RTS522A: 794 sc->rtsx_sd30_drive_sel_3v3 = RTSX_CFG_DRIVER_TYPE_B; 795 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4); 796 if (!(reg & 0x1000000)) { 797 sc->rtsx_card_drive_sel &= 0x3F; 798 sc->rtsx_card_drive_sel |= ((reg >> 25) & 0x01) << 6; 799 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG2, 4); 800 sc->rtsx_sd30_drive_sel_3v3 = (reg >> 5) & 0x03; 801 if (reg & 0x4000) 802 sc->rtsx_flags |= RTSX_F_REVERSE_SOCKET; 803 } else if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) { 804 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg); 805 } 806 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 807 device_printf(sc->rtsx_dev, 808 "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x, reverse_socket is %s\n", 809 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3, 810 (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) ? "true" : "false"); 811 break; 812 case RTSX_RTS5229: 813 sc->rtsx_sd30_drive_sel_3v3 = RTSX_DRIVER_TYPE_D; 814 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4); 815 if (!(reg & 0x1000000)) { 816 sc->rtsx_card_drive_sel &= 0x3F; 817 sc->rtsx_card_drive_sel |= ((reg >> 25) & 0x01) << 6; 818 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG2, 4); 819 sc->rtsx_sd30_drive_sel_3v3 = rtsx_map_sd_drive((reg >> 5) & 0x03); 820 } else if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) { 821 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg); 822 } 823 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 824 device_printf(sc->rtsx_dev, "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x\n", 825 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3); 826 break; 827 case RTSX_RTS525A: 828 case RTSX_RTS5249: 829 case RTSX_RTS5260: 830 sc->rtsx_sd30_drive_sel_3v3 = RTSX_CFG_DRIVER_TYPE_B; 831 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4); 832 if ((reg & 0x1000000)) { 833 sc->rtsx_card_drive_sel &= 0x3F; 834 sc->rtsx_card_drive_sel |= ((reg >> 25) & 0x01) << 6; 835 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG2, 4); 836 sc->rtsx_sd30_drive_sel_3v3 = (reg >> 5) & 0x03; 837 if (reg & 0x4000) 838 sc->rtsx_flags |= RTSX_F_REVERSE_SOCKET; 839 } else if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) { 840 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg); 841 } 842 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 843 device_printf(sc->rtsx_dev, 844 "card_drive_sel = 0x%02x, sd30_drive_sel_3v3: 0x%02x, reverse_socket is %s\n", 845 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3, 846 (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) ? "true" : "false"); 847 break; 848 case RTSX_RTL8402: 849 case RTSX_RTL8411: 850 sc->rtsx_card_drive_sel = RTSX_RTL8411_CARD_DRIVE_DEFAULT; 851 sc->rtsx_sd30_drive_sel_3v3 = RTSX_DRIVER_TYPE_D; 852 reg1 = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4); 853 if (reg1 & 0x1000000) { 854 sc->rtsx_card_drive_sel &= 0x3F; 855 sc->rtsx_card_drive_sel |= ((reg1 >> 25) & 0x01) << 6; 856 reg3 = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG3, 1); 857 sc->rtsx_sd30_drive_sel_3v3 = (reg3 >> 5) & 0x07; 858 } else if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) { 859 device_printf(sc->rtsx_dev, "pci_read_config() error - reg1: 0x%08x\n", reg1); 860 } 861 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 862 device_printf(sc->rtsx_dev, 863 "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x\n", 864 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3); 865 break; 866 case RTSX_RTL8411B: 867 sc->rtsx_card_drive_sel = RTSX_RTL8411_CARD_DRIVE_DEFAULT; 868 sc->rtsx_sd30_drive_sel_3v3 = RTSX_DRIVER_TYPE_D; 869 reg = pci_read_config(sc->rtsx_dev, RTSX_PCR_SETTING_REG1, 4); 870 if (!(reg & 0x1000000)) { 871 sc->rtsx_sd30_drive_sel_3v3 = rtsx_map_sd_drive(reg & 0x03); 872 } else if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) { 873 device_printf(sc->rtsx_dev, "pci_read_config() error - reg: 0x%08x\n", reg); 874 } 875 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 876 device_printf(sc->rtsx_dev, 877 "card_drive_sel: 0x%02x, sd30_drive_sel_3v3: 0x%02x\n", 878 sc->rtsx_card_drive_sel, sc->rtsx_sd30_drive_sel_3v3); 879 break; 880 } 881 882 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 883 device_printf(sc->rtsx_dev, "rtsx_init() rtsx_flags: 0x%04x\n", sc->rtsx_flags); 884 885 /* Enable interrupts. */ 886 sc->rtsx_intr_enabled = RTSX_TRANS_OK_INT_EN | RTSX_TRANS_FAIL_INT_EN | RTSX_SD_INT_EN; 887 WRITE4(sc, RTSX_BIER, sc->rtsx_intr_enabled); 888 889 /* Power on SSC clock. */ 890 RTSX_CLR(sc, RTSX_FPDCTL, RTSX_SSC_POWER_DOWN); 891 /* Wait SSC power stable. */ 892 DELAY(200); 893 894 /* Disable ASPM */ 895 val = pci_read_config(sc->rtsx_dev, sc->rtsx_pcie_cap + PCIER_LINK_CTL, 1); 896 pci_write_config(sc->rtsx_dev, sc->rtsx_pcie_cap + PCIER_LINK_CTL, val & 0xfc, 1); 897 898 /* 899 * Optimize phy. 900 */ 901 switch (sc->rtsx_device_id) { 902 case RTSX_RTS5209: 903 /* Some magic numbers from Linux driver. */ 904 if ((error = rtsx_write_phy(sc, 0x00, 0xB966))) 905 return (error); 906 break; 907 case RTSX_RTS5227: 908 RTSX_CLR(sc, RTSX_PM_CTRL3, RTSX_D3_DELINK_MODE_EN); 909 910 /* Optimize RX sensitivity. */ 911 if ((error = rtsx_write_phy(sc, 0x00, 0xBA42))) 912 return (error); 913 break; 914 case RTSX_RTS5229: 915 /* Optimize RX sensitivity. */ 916 if ((error = rtsx_write_phy(sc, 0x00, 0xBA42))) 917 return (error); 918 break; 919 case RTSX_RTS522A: 920 RTSX_CLR(sc, RTSX_RTS522A_PM_CTRL3, RTSX_D3_DELINK_MODE_EN); 921 if (sc->rtsx_flags & RTSX_F_VERSION_A) { 922 if ((error = rtsx_write_phy(sc, RTSX_PHY_RCR2, RTSX_PHY_RCR2_INIT_27S))) 923 return (error); 924 } 925 if ((error = rtsx_write_phy(sc, RTSX_PHY_RCR1, RTSX_PHY_RCR1_INIT_27S))) 926 return (error); 927 if ((error = rtsx_write_phy(sc, RTSX_PHY_FLD0, RTSX_PHY_FLD0_INIT_27S))) 928 return (error); 929 if ((error = rtsx_write_phy(sc, RTSX_PHY_FLD3, RTSX_PHY_FLD3_INIT_27S))) 930 return (error); 931 if ((error = rtsx_write_phy(sc, RTSX_PHY_FLD4, RTSX_PHY_FLD4_INIT_27S))) 932 return (error); 933 break; 934 case RTSX_RTS525A: 935 if ((error = rtsx_write_phy(sc, RTSX__PHY_FLD0, 936 RTSX__PHY_FLD0_CLK_REQ_20C | RTSX__PHY_FLD0_RX_IDLE_EN | 937 RTSX__PHY_FLD0_BIT_ERR_RSTN | RTSX__PHY_FLD0_BER_COUNT | 938 RTSX__PHY_FLD0_BER_TIMER | RTSX__PHY_FLD0_CHECK_EN))) 939 return (error); 940 if ((error = rtsx_write_phy(sc, RTSX__PHY_ANA03, 941 RTSX__PHY_ANA03_TIMER_MAX | RTSX__PHY_ANA03_OOBS_DEB_EN | 942 RTSX__PHY_CMU_DEBUG_EN))) 943 return (error); 944 if (sc->rtsx_flags & RTSX_F_VERSION_A) 945 if ((error = rtsx_write_phy(sc, RTSX__PHY_REV0, 946 RTSX__PHY_REV0_FILTER_OUT | RTSX__PHY_REV0_CDR_BYPASS_PFD | 947 RTSX__PHY_REV0_CDR_RX_IDLE_BYPASS))) 948 return (error); 949 break; 950 case RTSX_RTS5249: 951 RTSX_CLR(sc, RTSX_PM_CTRL3, RTSX_D3_DELINK_MODE_EN); 952 if ((error = rtsx_write_phy(sc, RTSX_PHY_REV, 953 RTSX_PHY_REV_RESV | RTSX_PHY_REV_RXIDLE_LATCHED | 954 RTSX_PHY_REV_P1_EN | RTSX_PHY_REV_RXIDLE_EN | 955 RTSX_PHY_REV_CLKREQ_TX_EN | RTSX_PHY_REV_RX_PWST | 956 RTSX_PHY_REV_CLKREQ_DT_1_0 | RTSX_PHY_REV_STOP_CLKRD | 957 RTSX_PHY_REV_STOP_CLKWR))) 958 return (error); 959 DELAY(1000); 960 if ((error = rtsx_write_phy(sc, RTSX_PHY_BPCR, 961 RTSX_PHY_BPCR_IBRXSEL | RTSX_PHY_BPCR_IBTXSEL | 962 RTSX_PHY_BPCR_IB_FILTER | RTSX_PHY_BPCR_CMIRROR_EN))) 963 return (error); 964 if ((error = rtsx_write_phy(sc, RTSX_PHY_PCR, 965 RTSX_PHY_PCR_FORCE_CODE | RTSX_PHY_PCR_OOBS_CALI_50 | 966 RTSX_PHY_PCR_OOBS_VCM_08 | RTSX_PHY_PCR_OOBS_SEN_90 | 967 RTSX_PHY_PCR_RSSI_EN | RTSX_PHY_PCR_RX10K))) 968 return (error); 969 if ((error = rtsx_write_phy(sc, RTSX_PHY_RCR2, 970 RTSX_PHY_RCR2_EMPHASE_EN | RTSX_PHY_RCR2_NADJR | 971 RTSX_PHY_RCR2_CDR_SR_2 | RTSX_PHY_RCR2_FREQSEL_12 | 972 RTSX_PHY_RCR2_CDR_SC_12P | RTSX_PHY_RCR2_CALIB_LATE))) 973 return (error); 974 if ((error = rtsx_write_phy(sc, RTSX_PHY_FLD4, 975 RTSX_PHY_FLD4_FLDEN_SEL | RTSX_PHY_FLD4_REQ_REF | 976 RTSX_PHY_FLD4_RXAMP_OFF | RTSX_PHY_FLD4_REQ_ADDA | 977 RTSX_PHY_FLD4_BER_COUNT | RTSX_PHY_FLD4_BER_TIMER | 978 RTSX_PHY_FLD4_BER_CHK_EN))) 979 return (error); 980 if ((error = rtsx_write_phy(sc, RTSX_PHY_RDR, 981 RTSX_PHY_RDR_RXDSEL_1_9 | RTSX_PHY_SSC_AUTO_PWD))) 982 return (error); 983 if ((error = rtsx_write_phy(sc, RTSX_PHY_RCR1, 984 RTSX_PHY_RCR1_ADP_TIME_4 | RTSX_PHY_RCR1_VCO_COARSE))) 985 return (error); 986 if ((error = rtsx_write_phy(sc, RTSX_PHY_FLD3, 987 RTSX_PHY_FLD3_TIMER_4 | RTSX_PHY_FLD3_TIMER_6 | 988 RTSX_PHY_FLD3_RXDELINK))) 989 return (error); 990 if ((error = rtsx_write_phy(sc, RTSX_PHY_TUNE, 991 RTSX_PHY_TUNE_TUNEREF_1_0 | RTSX_PHY_TUNE_VBGSEL_1252 | 992 RTSX_PHY_TUNE_SDBUS_33 | RTSX_PHY_TUNE_TUNED18 | 993 RTSX_PHY_TUNE_TUNED12 | RTSX_PHY_TUNE_TUNEA12))) 994 return (error); 995 break; 996 } 997 998 /* Set mcu_cnt to 7 to ensure data can be sampled properly. */ 999 RTSX_BITOP(sc, RTSX_CLK_DIV, 0x07, 0x07); 1000 1001 /* Disable sleep mode. */ 1002 RTSX_CLR(sc, RTSX_HOST_SLEEP_STATE, 1003 RTSX_HOST_ENTER_S1 | RTSX_HOST_ENTER_S3); 1004 1005 /* Disable card clock. */ 1006 RTSX_CLR(sc, RTSX_CARD_CLK_EN, RTSX_CARD_CLK_EN_ALL); 1007 1008 /* Reset delink mode. */ 1009 RTSX_CLR(sc, RTSX_CHANGE_LINK_STATE, 1010 RTSX_FORCE_RST_CORE_EN | RTSX_NON_STICKY_RST_N_DBG); 1011 1012 /* Card driving select. */ 1013 RTSX_WRITE(sc, RTSX_CARD_DRIVE_SEL, sc->rtsx_card_drive_sel); 1014 1015 /* Enable SSC clock. */ 1016 RTSX_WRITE(sc, RTSX_SSC_CTL1, RTSX_SSC_8X_EN | RTSX_SSC_SEL_4M); 1017 RTSX_WRITE(sc, RTSX_SSC_CTL2, 0x12); 1018 1019 /* Disable cd_pwr_save. */ 1020 RTSX_BITOP(sc, RTSX_CHANGE_LINK_STATE, 0x16, RTSX_MAC_PHY_RST_N_DBG); 1021 1022 /* Clear Link Ready Interrupt. */ 1023 RTSX_BITOP(sc, RTSX_IRQSTAT0, RTSX_LINK_READY_INT, RTSX_LINK_READY_INT); 1024 1025 /* Enlarge the estimation window of PERST# glitch 1026 * to reduce the chance of invalid card interrupt. */ 1027 RTSX_WRITE(sc, RTSX_PERST_GLITCH_WIDTH, 0x80); 1028 1029 /* Set RC oscillator to 400K. */ 1030 RTSX_CLR(sc, RTSX_RCCTL, RTSX_RCCTL_F_2M); 1031 1032 /* Enable interrupt write-clear (default is read-clear). */ 1033 RTSX_CLR(sc, RTSX_NFTS_TX_CTRL, RTSX_INT_READ_CLR); 1034 1035 switch (sc->rtsx_device_id) { 1036 case RTSX_RTS525A: 1037 case RTSX_RTS5260: 1038 RTSX_BITOP(sc, RTSX_PM_CLK_FORCE_CTL, 1, 1); 1039 break; 1040 } 1041 1042 /* OC power down. */ 1043 RTSX_BITOP(sc, RTSX_FPDCTL, RTSX_SD_OC_POWER_DOWN, RTSX_SD_OC_POWER_DOWN); 1044 1045 /* Enable clk_request_n to enable clock power management */ 1046 pci_write_config(sc->rtsx_dev, sc->rtsx_pcie_cap + PCIER_LINK_CTL + 1, 1, 1); 1047 1048 /* Enter L1 when host tx idle */ 1049 pci_write_config(sc->rtsx_dev, 0x70F, 0x5B, 1); 1050 1051 /* 1052 * Specific extra init. 1053 */ 1054 switch (sc->rtsx_device_id) { 1055 uint16_t cap; 1056 case RTSX_RTS5209: 1057 /* Turn off LED. */ 1058 RTSX_WRITE(sc, RTSX_CARD_GPIO, 0x03); 1059 /* Reset ASPM state to default value. */ 1060 RTSX_CLR(sc, RTSX_ASPM_FORCE_CTL, RTSX_ASPM_FORCE_MASK); 1061 /* Force CLKREQ# PIN to drive 0 to request clock. */ 1062 RTSX_BITOP(sc, RTSX_PETXCFG, 0x08, 0x08); 1063 /* Configure GPIO as output. */ 1064 RTSX_WRITE(sc, RTSX_CARD_GPIO_DIR, 0x03); 1065 /* Configure driving. */ 1066 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, sc->rtsx_sd30_drive_sel_3v3); 1067 break; 1068 case RTSX_RTS5227: 1069 /* Configure GPIO as output. */ 1070 RTSX_BITOP(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON, RTSX_GPIO_LED_ON); 1071 /* Reset ASPM state to default value. */ 1072 RTSX_BITOP(sc, RTSX_ASPM_FORCE_CTL, RTSX_ASPM_FORCE_MASK, RTSX_FORCE_ASPM_NO_ASPM); 1073 /* Switch LDO3318 source from DV33 to 3V3. */ 1074 RTSX_CLR(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33); 1075 RTSX_BITOP(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33, RTSX_LDO_PWR_SEL_3V3); 1076 /* Set default OLT blink period. */ 1077 RTSX_BITOP(sc, RTSX_OLT_LED_CTL, 0x0F, RTSX_OLT_LED_PERIOD); 1078 /* Configure LTR. */ 1079 cap = pci_read_config(sc->rtsx_dev, sc->rtsx_pcie_cap + PCIER_DEVICE_CTL2, 2); 1080 if (cap & PCIEM_CTL2_LTR_ENABLE) 1081 RTSX_WRITE(sc, RTSX_LTR_CTL, 0xa3); 1082 /* Configure OBFF. */ 1083 RTSX_BITOP(sc, RTSX_OBFF_CFG, RTSX_OBFF_EN_MASK, RTSX_OBFF_ENABLE); 1084 /* Configure driving. */ 1085 if ((error = rtsx_rts5227_fill_driving(sc))) 1086 return (error); 1087 /* Configure force_clock_req. */ 1088 if (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) 1089 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB8, 0xB8); 1090 else 1091 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB8, 0x88); 1092 RTSX_CLR(sc, RTSX_PM_CTRL3, RTSX_D3_DELINK_MODE_EN); 1093 /*!!! Added for reboot after Windows. */ 1094 RTSX_BITOP(sc, RTSX_PM_CTRL3, RTSX_PM_WAKE_EN, RTSX_PM_WAKE_EN); 1095 break; 1096 case RTSX_RTS5229: 1097 /* Configure GPIO as output. */ 1098 RTSX_BITOP(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON, RTSX_GPIO_LED_ON); 1099 /* Reset ASPM state to default value. */ 1100 /* With this reset: dd if=/dev/random of=/dev/mmcsd0 encounter a timeout. */ 1101 //!!! RTSX_BITOP(sc, RTSX_ASPM_FORCE_CTL, RTSX_ASPM_FORCE_MASK, RTSX_FORCE_ASPM_NO_ASPM); 1102 /* Force CLKREQ# PIN to drive 0 to request clock. */ 1103 RTSX_BITOP(sc, RTSX_PETXCFG, 0x08, 0x08); 1104 /* Switch LDO3318 source from DV33 to card_3v3. */ 1105 RTSX_CLR(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33); 1106 RTSX_BITOP(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33, RTSX_LDO_PWR_SEL_3V3); 1107 /* Set default OLT blink period. */ 1108 RTSX_BITOP(sc, RTSX_OLT_LED_CTL, 0x0F, RTSX_OLT_LED_PERIOD); 1109 /* Configure driving. */ 1110 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, sc->rtsx_sd30_drive_sel_3v3); 1111 break; 1112 case RTSX_RTS522A: 1113 /* Add specific init from RTS5227. */ 1114 /* Configure GPIO as output. */ 1115 RTSX_BITOP(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON, RTSX_GPIO_LED_ON); 1116 /* Reset ASPM state to default value. */ 1117 RTSX_BITOP(sc, RTSX_ASPM_FORCE_CTL, RTSX_ASPM_FORCE_MASK, RTSX_FORCE_ASPM_NO_ASPM); 1118 /* Switch LDO3318 source from DV33 to 3V3. */ 1119 RTSX_CLR(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33); 1120 RTSX_BITOP(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33, RTSX_LDO_PWR_SEL_3V3); 1121 /* Set default OLT blink period. */ 1122 RTSX_BITOP(sc, RTSX_OLT_LED_CTL, 0x0F, RTSX_OLT_LED_PERIOD); 1123 /* Configure LTR. */ 1124 cap = pci_read_config(sc->rtsx_dev, sc->rtsx_pcie_cap + PCIER_DEVICE_CTL2, 2); 1125 if (cap & PCIEM_CTL2_LTR_ENABLE) 1126 RTSX_WRITE(sc, RTSX_LTR_CTL, 0xa3); 1127 /* Configure OBFF. */ 1128 RTSX_BITOP(sc, RTSX_OBFF_CFG, RTSX_OBFF_EN_MASK, RTSX_OBFF_ENABLE); 1129 /* Configure driving. */ 1130 if ((error = rtsx_rts5227_fill_driving(sc))) 1131 return (error); 1132 /* Configure force_clock_req. */ 1133 if (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) 1134 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB8, 0xB8); 1135 else 1136 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB8, 0x88); 1137 RTSX_CLR(sc, RTSX_RTS522A_PM_CTRL3, 0x10); 1138 1139 /* specific for RTS522A. */ 1140 RTSX_BITOP(sc, RTSX_FUNC_FORCE_CTL, 1141 RTSX_FUNC_FORCE_UPME_XMT_DBG, RTSX_FUNC_FORCE_UPME_XMT_DBG); 1142 RTSX_BITOP(sc, RTSX_PCLK_CTL, 0x04, 0x04); 1143 RTSX_BITOP(sc, RTSX_PM_EVENT_DEBUG, 1144 RTSX_PME_DEBUG_0, RTSX_PME_DEBUG_0); 1145 RTSX_WRITE(sc, RTSX_PM_CLK_FORCE_CTL, 0x11); 1146 break; 1147 case RTSX_RTS525A: 1148 /* Add specific init from RTS5249. */ 1149 /* Rest L1SUB Config. */ 1150 RTSX_CLR(sc, RTSX_L1SUB_CONFIG3, 0xff); 1151 /* Configure GPIO as output. */ 1152 RTSX_BITOP(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON, RTSX_GPIO_LED_ON); 1153 /* Reset ASPM state to default value. */ 1154 RTSX_BITOP(sc, RTSX_ASPM_FORCE_CTL, RTSX_ASPM_FORCE_MASK, RTSX_FORCE_ASPM_NO_ASPM); 1155 /* Switch LDO3318 source from DV33 to 3V3. */ 1156 RTSX_CLR(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33); 1157 RTSX_BITOP(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33, RTSX_LDO_PWR_SEL_3V3); 1158 /* Set default OLT blink period. */ 1159 RTSX_BITOP(sc, RTSX_OLT_LED_CTL, 0x0F, RTSX_OLT_LED_PERIOD); 1160 /* Configure driving. */ 1161 if ((error = rtsx_rts5249_fill_driving(sc))) 1162 return (error); 1163 /* Configure force_clock_req. */ 1164 if (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) 1165 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0xB0); 1166 else 1167 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0x80); 1168 1169 /* Specifc for RTS525A. */ 1170 RTSX_BITOP(sc, RTSX_PCLK_CTL, RTSX_PCLK_MODE_SEL, RTSX_PCLK_MODE_SEL); 1171 if (sc->rtsx_flags & RTSX_F_VERSION_A) { 1172 RTSX_WRITE(sc, RTSX_L1SUB_CONFIG2, RTSX_L1SUB_AUTO_CFG); 1173 RTSX_BITOP(sc, RTSX_RREF_CFG, 1174 RTSX_RREF_VBGSEL_MASK, RTSX_RREF_VBGSEL_1V25); 1175 RTSX_BITOP(sc, RTSX_LDO_VIO_CFG, 1176 RTSX_LDO_VIO_TUNE_MASK, RTSX_LDO_VIO_1V7); 1177 RTSX_BITOP(sc, RTSX_LDO_DV12S_CFG, 1178 RTSX_LDO_D12_TUNE_MASK, RTSX_LDO_D12_TUNE_DF); 1179 RTSX_BITOP(sc, RTSX_LDO_AV12S_CFG, 1180 RTSX_LDO_AV12S_TUNE_MASK, RTSX_LDO_AV12S_TUNE_DF); 1181 RTSX_BITOP(sc, RTSX_LDO_VCC_CFG0, 1182 RTSX_LDO_VCC_LMTVTH_MASK, RTSX_LDO_VCC_LMTVTH_2A); 1183 RTSX_BITOP(sc, RTSX_OOBS_CONFIG, 1184 RTSX_OOBS_AUTOK_DIS | RTSX_OOBS_VAL_MASK, 0x89); 1185 } 1186 break; 1187 case RTSX_RTS5249: 1188 /* Rest L1SUB Config. */ 1189 RTSX_CLR(sc, RTSX_L1SUB_CONFIG3, 0xff); 1190 /* Configure GPIO as output. */ 1191 RTSX_BITOP(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON, RTSX_GPIO_LED_ON); 1192 /* Reset ASPM state to default value. */ 1193 RTSX_BITOP(sc, RTSX_ASPM_FORCE_CTL, RTSX_ASPM_FORCE_MASK, RTSX_FORCE_ASPM_NO_ASPM); 1194 /* Switch LDO3318 source from DV33 to 3V3. */ 1195 RTSX_CLR(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33); 1196 RTSX_BITOP(sc, RTSX_LDO_PWR_SEL, RTSX_LDO_PWR_SEL_DV33, RTSX_LDO_PWR_SEL_3V3); 1197 /* Set default OLT blink period. */ 1198 RTSX_BITOP(sc, RTSX_OLT_LED_CTL, 0x0F, RTSX_OLT_LED_PERIOD); 1199 /* Configure driving. */ 1200 if ((error = rtsx_rts5249_fill_driving(sc))) 1201 return (error); 1202 /* Configure force_clock_req. */ 1203 if (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) 1204 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0xB0); 1205 else 1206 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0x80); 1207 break; 1208 case RTSX_RTS5260: 1209 /* Set mcu_cnt to 7 to ensure data can be sampled properly. */ 1210 RTSX_BITOP(sc, RTSX_CLK_DIV, 0x07, 0x07); 1211 RTSX_WRITE(sc, RTSX_SSC_DIV_N_0, 0x5D); 1212 /* Force no MDIO */ 1213 RTSX_WRITE(sc, RTSX_RTS5260_AUTOLOAD_CFG4, RTSX_RTS5260_MIMO_DISABLE); 1214 /* Modify SDVCC Tune Default Parameters! */ 1215 RTSX_BITOP(sc, RTSX_LDO_VCC_CFG0, RTSX_RTS5260_DVCC_TUNE_MASK, RTSX_RTS5260_DVCC_33); 1216 1217 RTSX_BITOP(sc, RTSX_PCLK_CTL, RTSX_PCLK_MODE_SEL, RTSX_PCLK_MODE_SEL); 1218 1219 RTSX_BITOP(sc, RTSX_L1SUB_CONFIG1, RTSX_AUX_CLK_ACTIVE_SEL_MASK, RTSX_MAC_CKSW_DONE); 1220 /* Rest L1SUB Config */ 1221 RTSX_CLR(sc, RTSX_L1SUB_CONFIG3, 0xFF); 1222 RTSX_BITOP(sc, RTSX_PM_CLK_FORCE_CTL, RTSX_CLK_PM_EN, RTSX_CLK_PM_EN); 1223 RTSX_WRITE(sc, RTSX_PWD_SUSPEND_EN, 0xFF); 1224 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_PWR_GATE_EN, RTSX_PWR_GATE_EN); 1225 RTSX_BITOP(sc, RTSX_REG_VREF, RTSX_PWD_SUSPND_EN, RTSX_PWD_SUSPND_EN); 1226 RTSX_BITOP(sc, RTSX_RBCTL, RTSX_U_AUTO_DMA_EN_MASK, RTSX_U_AUTO_DMA_DISABLE); 1227 if (sc->rtsx_flags & RTSX_F_REVERSE_SOCKET) 1228 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0xB0); 1229 else 1230 RTSX_BITOP(sc, RTSX_PETXCFG, 0xB0, 0x80); 1231 RTSX_BITOP(sc, RTSX_OBFF_CFG, RTSX_OBFF_EN_MASK, RTSX_OBFF_DISABLE); 1232 1233 RTSX_CLR(sc, RTSX_RTS5260_DVCC_CTRL, RTSX_RTS5260_DVCC_OCP_EN | RTSX_RTS5260_DVCC_OCP_CL_EN); 1234 1235 /* CLKREQ# PIN will be forced to drive low. */ 1236 RTSX_BITOP(sc, RTSX_PETXCFG, RTSX_FORCE_CLKREQ_DELINK_MASK, RTSX_FORCE_CLKREQ_LOW); 1237 1238 RTSX_CLR(sc, RTSX_RTS522A_PM_CTRL3, 0x10); 1239 break; 1240 case RTSX_RTL8402: 1241 case RTSX_RTL8411: 1242 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, sc->rtsx_sd30_drive_sel_3v3); 1243 RTSX_BITOP(sc, RTSX_CARD_PAD_CTL, RTSX_CD_DISABLE_MASK | RTSX_CD_AUTO_DISABLE, 1244 RTSX_CD_ENABLE); 1245 break; 1246 case RTSX_RTL8411B: 1247 if (sc->rtsx_flags & RTSX_F_8411B_QFN48) 1248 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xf5); 1249 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, sc->rtsx_sd30_drive_sel_3v3); 1250 /* Enable SD interrupt. */ 1251 RTSX_BITOP(sc, RTSX_CARD_PAD_CTL, RTSX_CD_DISABLE_MASK | RTSX_CD_AUTO_DISABLE, 1252 RTSX_CD_ENABLE); 1253 /* Clear hw_pfm_en to disable hardware PFM mode. */ 1254 RTSX_BITOP(sc, RTSX_FUNC_FORCE_CTL, 0x06, 0x00); 1255 break; 1256 } 1257 1258 /*!!! Added for reboot after Windows. */ 1259 rtsx_bus_power_off(sc); 1260 rtsx_set_sd_timing(sc, bus_timing_normal); 1261 rtsx_set_sd_clock(sc, 0); 1262 /*!!! Added for reboot after Windows. */ 1263 1264 return (0); 1265 } 1266 1267 static int 1268 rtsx_map_sd_drive(int index) 1269 { 1270 uint8_t sd_drive[4] = 1271 { 1272 0x01, /* Type D */ 1273 0x02, /* Type C */ 1274 0x05, /* Type A */ 1275 0x03 /* Type B */ 1276 }; 1277 return (sd_drive[index]); 1278 } 1279 1280 /* For voltage 3v3. */ 1281 static int 1282 rtsx_rts5227_fill_driving(struct rtsx_softc *sc) 1283 { 1284 u_char driving_3v3[4][3] = { 1285 {0x13, 0x13, 0x13}, 1286 {0x96, 0x96, 0x96}, 1287 {0x7F, 0x7F, 0x7F}, 1288 {0x96, 0x96, 0x96}, 1289 }; 1290 RTSX_WRITE(sc, RTSX_SD30_CLK_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][0]); 1291 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][1]); 1292 RTSX_WRITE(sc, RTSX_SD30_DAT_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][2]); 1293 1294 return (0); 1295 } 1296 1297 /* For voltage 3v3. */ 1298 static int 1299 rtsx_rts5249_fill_driving(struct rtsx_softc *sc) 1300 { 1301 u_char driving_3v3[4][3] = { 1302 {0x11, 0x11, 0x18}, 1303 {0x55, 0x55, 0x5C}, 1304 {0xFF, 0xFF, 0xFF}, 1305 {0x96, 0x96, 0x96}, 1306 }; 1307 RTSX_WRITE(sc, RTSX_SD30_CLK_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][0]); 1308 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][1]); 1309 RTSX_WRITE(sc, RTSX_SD30_DAT_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][2]); 1310 1311 return (0); 1312 } 1313 1314 static int 1315 rtsx_rts5260_fill_driving(struct rtsx_softc *sc) 1316 { 1317 u_char driving_3v3[4][3] = { 1318 {0x11, 0x11, 0x11}, 1319 {0x22, 0x22, 0x22}, 1320 {0x55, 0x55, 0x55}, 1321 {0x33, 0x33, 0x33}, 1322 }; 1323 RTSX_WRITE(sc, RTSX_SD30_CLK_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][0]); 1324 RTSX_WRITE(sc, RTSX_SD30_CMD_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][1]); 1325 RTSX_WRITE(sc, RTSX_SD30_DAT_DRIVE_SEL, driving_3v3[sc->rtsx_sd30_drive_sel_3v3][2]); 1326 1327 return (0); 1328 } 1329 1330 static int 1331 rtsx_read(struct rtsx_softc *sc, uint16_t addr, uint8_t *val) 1332 { 1333 int tries = 1024; 1334 uint32_t arg; 1335 uint32_t reg; 1336 1337 arg = RTSX_HAIMR_BUSY | (uint32_t)((addr & 0x3FFF) << 16); 1338 WRITE4(sc, RTSX_HAIMR, arg); 1339 1340 while (tries--) { 1341 reg = READ4(sc, RTSX_HAIMR); 1342 if (!(reg & RTSX_HAIMR_BUSY)) 1343 break; 1344 } 1345 *val = (reg & 0xff); 1346 1347 if (tries > 0) { 1348 return (0); 1349 } else { 1350 device_printf(sc->rtsx_dev, "rtsx_read(0x%x) timeout\n", arg); 1351 return (ETIMEDOUT); 1352 } 1353 } 1354 1355 static int 1356 rtsx_read_cfg(struct rtsx_softc *sc, uint8_t func, uint16_t addr, uint32_t *val) 1357 { 1358 int tries = 1024; 1359 uint8_t data0, data1, data2, data3, rwctl; 1360 1361 RTSX_WRITE(sc, RTSX_CFGADDR0, addr); 1362 RTSX_WRITE(sc, RTSX_CFGADDR1, addr >> 8); 1363 RTSX_WRITE(sc, RTSX_CFGRWCTL, RTSX_CFG_BUSY | (func & 0x03 << 4)); 1364 1365 while (tries--) { 1366 RTSX_READ(sc, RTSX_CFGRWCTL, &rwctl); 1367 if (!(rwctl & RTSX_CFG_BUSY)) 1368 break; 1369 } 1370 1371 if (tries == 0) 1372 return (ETIMEDOUT); 1373 1374 RTSX_READ(sc, RTSX_CFGDATA0, &data0); 1375 RTSX_READ(sc, RTSX_CFGDATA1, &data1); 1376 RTSX_READ(sc, RTSX_CFGDATA2, &data2); 1377 RTSX_READ(sc, RTSX_CFGDATA3, &data3); 1378 1379 *val = (data3 << 24) | (data2 << 16) | (data1 << 8) | data0; 1380 1381 return (0); 1382 } 1383 1384 static int 1385 rtsx_write(struct rtsx_softc *sc, uint16_t addr, uint8_t mask, uint8_t val) 1386 { 1387 int tries = 1024; 1388 uint32_t arg; 1389 uint32_t reg; 1390 1391 arg = RTSX_HAIMR_BUSY | RTSX_HAIMR_WRITE | 1392 (uint32_t)(((addr & 0x3FFF) << 16) | 1393 (mask << 8) | val); 1394 WRITE4(sc, RTSX_HAIMR, arg); 1395 1396 while (tries--) { 1397 reg = READ4(sc, RTSX_HAIMR); 1398 if (!(reg & RTSX_HAIMR_BUSY)) { 1399 if (val != (reg & 0xff)) { 1400 device_printf(sc->rtsx_dev, "rtsx_write(0x%x) error reg=0x%x\n", arg, reg); 1401 return (EIO); 1402 } 1403 return (0); 1404 } 1405 } 1406 device_printf(sc->rtsx_dev, "rtsx_write(0x%x) timeout\n", arg); 1407 1408 return (ETIMEDOUT); 1409 } 1410 1411 static int 1412 rtsx_read_phy(struct rtsx_softc *sc, uint8_t addr, uint16_t *val) 1413 { 1414 int tries = 100000; 1415 uint8_t data0, data1, rwctl; 1416 1417 RTSX_WRITE(sc, RTSX_PHY_ADDR, addr); 1418 RTSX_WRITE(sc, RTSX_PHY_RWCTL, RTSX_PHY_BUSY | RTSX_PHY_READ); 1419 1420 while (tries--) { 1421 RTSX_READ(sc, RTSX_PHY_RWCTL, &rwctl); 1422 if (!(rwctl & RTSX_PHY_BUSY)) 1423 break; 1424 } 1425 if (tries == 0) 1426 return (ETIMEDOUT); 1427 1428 RTSX_READ(sc, RTSX_PHY_DATA0, &data0); 1429 RTSX_READ(sc, RTSX_PHY_DATA1, &data1); 1430 *val = data1 << 8 | data0; 1431 1432 return (0); 1433 } 1434 1435 static int 1436 rtsx_write_phy(struct rtsx_softc *sc, uint8_t addr, uint16_t val) 1437 { 1438 int tries = 100000; 1439 uint8_t rwctl; 1440 1441 RTSX_WRITE(sc, RTSX_PHY_DATA0, val); 1442 RTSX_WRITE(sc, RTSX_PHY_DATA1, val >> 8); 1443 RTSX_WRITE(sc, RTSX_PHY_ADDR, addr); 1444 RTSX_WRITE(sc, RTSX_PHY_RWCTL, RTSX_PHY_BUSY | RTSX_PHY_WRITE); 1445 1446 while (tries--) { 1447 RTSX_READ(sc, RTSX_PHY_RWCTL, &rwctl); 1448 if (!(rwctl & RTSX_PHY_BUSY)) 1449 break; 1450 } 1451 1452 return ((tries == 0) ? ETIMEDOUT : 0); 1453 } 1454 1455 /* 1456 * Notice that the meaning of RTSX_PWR_GATE_CTRL changes between RTS5209 and 1457 * RTS5229. In RTS5209 it is a mask of disabled power gates, while in RTS5229 1458 * it is a mask of *enabled* gates. 1459 */ 1460 static int 1461 rtsx_bus_power_off(struct rtsx_softc *sc) 1462 { 1463 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 1464 device_printf(sc->rtsx_dev, "rtsx_bus_power_off()\n"); 1465 1466 /* Disable SD clock. */ 1467 RTSX_CLR(sc, RTSX_CARD_CLK_EN, RTSX_SD_CLK_EN); 1468 1469 /* Disable SD output. */ 1470 RTSX_CLR(sc, RTSX_CARD_OE, RTSX_SD_OUTPUT_EN); 1471 1472 /* Turn off power. */ 1473 switch (sc->rtsx_device_id) { 1474 case RTSX_RTS5209: 1475 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK | RTSX_PMOS_STRG_MASK, 1476 RTSX_SD_PWR_OFF | RTSX_PMOS_STRG_400mA); 1477 RTSX_SET(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_OFF); 1478 break; 1479 case RTSX_RTS5227: 1480 case RTSX_RTS5229: 1481 case RTSX_RTS522A: 1482 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK | RTSX_PMOS_STRG_MASK, 1483 RTSX_SD_PWR_OFF | RTSX_PMOS_STRG_400mA); 1484 RTSX_CLR(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK); 1485 break; 1486 case RTSX_RTS5260: 1487 rtsx_stop_cmd(sc); 1488 /* Switch vccq to 330 */ 1489 RTSX_BITOP(sc, RTSX_LDO_CONFIG2, RTSX_DV331812_VDD1, RTSX_DV331812_VDD1); 1490 RTSX_BITOP(sc, RTSX_LDO_DV18_CFG, RTSX_DV331812_MASK, RTSX_DV331812_33); 1491 RTSX_CLR(sc, RTSX_SD_PAD_CTL, RTSX_SD_IO_USING_1V8); 1492 rtsx_rts5260_fill_driving(sc); 1493 1494 RTSX_BITOP(sc, RTSX_LDO_VCC_CFG1, RTSX_LDO_POW_SDVDD1_MASK, RTSX_LDO_POW_SDVDD1_OFF); 1495 RTSX_BITOP(sc, RTSX_LDO_CONFIG2, RTSX_DV331812_POWERON, RTSX_DV331812_POWEROFF); 1496 break; 1497 case RTSX_RTL8402: 1498 case RTSX_RTL8411: 1499 case RTSX_RTL8411B: 1500 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK, 1501 RTSX_BPP_POWER_OFF); 1502 RTSX_BITOP(sc, RTSX_LDO_CTL, RTSX_BPP_LDO_POWB, 1503 RTSX_BPP_LDO_SUSPEND); 1504 break; 1505 default: 1506 RTSX_CLR(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK); 1507 RTSX_SET(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_OFF); 1508 RTSX_CLR(sc, RTSX_CARD_PWR_CTL, RTSX_PMOS_STRG_800mA); 1509 break; 1510 } 1511 1512 /* Disable pull control. */ 1513 switch (sc->rtsx_device_id) { 1514 case RTSX_RTS5209: 1515 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, RTSX_PULL_CTL_DISABLE12); 1516 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_DISABLE12); 1517 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_DISABLE3); 1518 break; 1519 case RTSX_RTS5227: 1520 case RTSX_RTS522A: 1521 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_DISABLE12); 1522 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_DISABLE3); 1523 break; 1524 case RTSX_RTS5229: 1525 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_DISABLE12); 1526 if (sc->rtsx_flags & RTSX_F_VERSION_C) 1527 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_DISABLE3_TYPE_C); 1528 else 1529 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_DISABLE3); 1530 break; 1531 case RTSX_RTS525A: 1532 case RTSX_RTS5249: 1533 case RTSX_RTS5260: 1534 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0x66); 1535 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_DISABLE12); 1536 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_DISABLE3); 1537 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x55); 1538 break; 1539 case RTSX_RTL8402: 1540 case RTSX_RTL8411: 1541 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0x65); 1542 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0x55); 1543 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0x95); 1544 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x09); 1545 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL5, 0x05); 1546 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x04); 1547 break; 1548 case RTSX_RTL8411B: 1549 if (sc->rtsx_flags & RTSX_F_8411B_QFN48) { 1550 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0x55); 1551 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xf5); 1552 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x15); 1553 } else { 1554 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0x65); 1555 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0x55); 1556 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xd5); 1557 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x59); 1558 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL5, 0x55); 1559 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x15); 1560 } 1561 break; 1562 } 1563 1564 return (0); 1565 } 1566 1567 static int 1568 rtsx_bus_power_on(struct rtsx_softc *sc) 1569 { 1570 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 1571 device_printf(sc->rtsx_dev, "rtsx_bus_power_on()\n"); 1572 1573 /* Select SD card. */ 1574 RTSX_BITOP(sc, RTSX_CARD_SELECT, 0x07, RTSX_SD_MOD_SEL); 1575 RTSX_BITOP(sc, RTSX_CARD_SHARE_MODE, RTSX_CARD_SHARE_MASK, RTSX_CARD_SHARE_48_SD); 1576 1577 /* Enable SD clock. */ 1578 RTSX_BITOP(sc, RTSX_CARD_CLK_EN, RTSX_SD_CLK_EN, RTSX_SD_CLK_EN); 1579 1580 /* Enable pull control. */ 1581 switch (sc->rtsx_device_id) { 1582 case RTSX_RTS5209: 1583 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, RTSX_PULL_CTL_ENABLE12); 1584 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_ENABLE12); 1585 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_ENABLE3); 1586 break; 1587 case RTSX_RTS5227: 1588 case RTSX_RTS522A: 1589 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_ENABLE12); 1590 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_ENABLE3); 1591 break; 1592 case RTSX_RTS5229: 1593 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_ENABLE12); 1594 if (sc->rtsx_flags & RTSX_F_VERSION_C) 1595 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_ENABLE3_TYPE_C); 1596 else 1597 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_ENABLE3); 1598 break; 1599 case RTSX_RTS525A: 1600 case RTSX_RTS5249: 1601 case RTSX_RTS5260: 1602 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0x66); 1603 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, RTSX_PULL_CTL_ENABLE12); 1604 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, RTSX_PULL_CTL_ENABLE3); 1605 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0xaa); 1606 break; 1607 case RTSX_RTL8402: 1608 case RTSX_RTL8411: 1609 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0xaa); 1610 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0xaa); 1611 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xa9); 1612 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x09); 1613 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL5, 0x09); 1614 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x04); 1615 break; 1616 case RTSX_RTL8411B: 1617 if (sc->rtsx_flags & RTSX_F_8411B_QFN48) { 1618 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0xaa); 1619 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xf9); 1620 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x19); 1621 } else { 1622 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL1, 0xaa); 1623 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL2, 0xaa); 1624 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL3, 0xd9); 1625 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL4, 0x59); 1626 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL5, 0x55); 1627 RTSX_WRITE(sc, RTSX_CARD_PULL_CTL6, 0x15); 1628 } 1629 break; 1630 } 1631 1632 /* 1633 * To avoid a current peak, enable card power in two phases 1634 * with a delay in between. 1635 */ 1636 switch (sc->rtsx_device_id) { 1637 case RTSX_RTS5209: 1638 /* Partial power. */ 1639 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PARTIAL_PWR_ON); 1640 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, RTSX_LDO3318_VCC2); 1641 1642 DELAY(200); 1643 1644 /* Full power. */ 1645 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PWR_ON); 1646 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, RTSX_LDO3318_ON); 1647 break; 1648 case RTSX_RTS5227: 1649 case RTSX_RTS522A: 1650 /* Partial power. */ 1651 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PARTIAL_PWR_ON); 1652 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, RTSX_LDO3318_VCC1); 1653 1654 DELAY(20000); 1655 1656 /* Full power. */ 1657 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PWR_ON); 1658 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, 1659 RTSX_LDO3318_VCC1 | RTSX_LDO3318_VCC2); 1660 RTSX_BITOP(sc, RTSX_CARD_OE, RTSX_SD_OUTPUT_EN, RTSX_SD_OUTPUT_EN); 1661 RTSX_BITOP(sc, RTSX_CARD_OE, RTSX_MS_OUTPUT_EN, RTSX_MS_OUTPUT_EN); 1662 break; 1663 case RTSX_RTS5229: 1664 /* Partial power. */ 1665 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PARTIAL_PWR_ON); 1666 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, RTSX_LDO3318_VCC1); 1667 1668 DELAY(200); 1669 1670 /* Full power. */ 1671 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PWR_ON); 1672 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, 1673 RTSX_LDO3318_VCC1 | RTSX_LDO3318_VCC2); 1674 break; 1675 case RTSX_RTS525A: 1676 RTSX_BITOP(sc, RTSX_LDO_VCC_CFG1, RTSX_LDO_VCC_TUNE_MASK, RTSX_LDO_VCC_3V3); 1677 case RTSX_RTS5249: 1678 /* Partial power. */ 1679 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PARTIAL_PWR_ON); 1680 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, RTSX_LDO3318_VCC1); 1681 1682 DELAY(5000); 1683 1684 /* Full power. */ 1685 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_SD_PWR_MASK, RTSX_SD_PWR_ON); 1686 RTSX_BITOP(sc, RTSX_PWR_GATE_CTRL, RTSX_LDO3318_PWR_MASK, 1687 RTSX_LDO3318_VCC1 | RTSX_LDO3318_VCC2); 1688 break; 1689 case RTSX_RTS5260: 1690 RTSX_BITOP(sc, RTSX_LDO_CONFIG2, RTSX_DV331812_VDD1, RTSX_DV331812_VDD1); 1691 RTSX_BITOP(sc, RTSX_LDO_VCC_CFG0, RTSX_RTS5260_DVCC_TUNE_MASK, RTSX_RTS5260_DVCC_33); 1692 RTSX_BITOP(sc, RTSX_LDO_VCC_CFG1, RTSX_LDO_POW_SDVDD1_MASK, RTSX_LDO_POW_SDVDD1_ON); 1693 RTSX_BITOP(sc, RTSX_LDO_CONFIG2, RTSX_DV331812_POWERON, RTSX_DV331812_POWERON); 1694 1695 DELAY(20000); 1696 1697 RTSX_BITOP(sc, RTSX_SD_CFG1, RTSX_SD_MODE_MASK | RTSX_SD_ASYNC_FIFO_NOT_RST, 1698 RTSX_SD30_MODE | RTSX_SD_ASYNC_FIFO_NOT_RST); 1699 RTSX_BITOP(sc, RTSX_CLK_CTL, RTSX_CHANGE_CLK, RTSX_CLK_LOW_FREQ); 1700 RTSX_WRITE(sc, RTSX_CARD_CLK_SOURCE, 1701 RTSX_CRC_VAR_CLK0 | RTSX_SD30_FIX_CLK | RTSX_SAMPLE_VAR_CLK1); 1702 RTSX_CLR(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ); 1703 1704 /* Initialize SD_CFG1 register */ 1705 RTSX_WRITE(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_128 | RTSX_SD20_MODE); 1706 RTSX_WRITE(sc, RTSX_SD_SAMPLE_POINT_CTL, RTSX_SD20_RX_POS_EDGE); 1707 RTSX_CLR(sc, RTSX_SD_PUSH_POINT_CTL, 0xff); 1708 RTSX_BITOP(sc, RTSX_CARD_STOP, RTSX_SD_STOP | RTSX_SD_CLR_ERR, 1709 RTSX_SD_STOP | RTSX_SD_CLR_ERR); 1710 /* Reset SD_CFG3 register */ 1711 RTSX_CLR(sc, RTSX_SD_CFG3, RTSX_SD30_CLK_END_EN); 1712 RTSX_CLR(sc, RTSX_REG_SD_STOP_SDCLK_CFG, 1713 RTSX_SD30_CLK_STOP_CFG_EN | RTSX_SD30_CLK_STOP_CFG0 | RTSX_SD30_CLK_STOP_CFG1); 1714 RTSX_CLR(sc, RTSX_REG_PRE_RW_MODE, RTSX_EN_INFINITE_MODE); 1715 break; 1716 case RTSX_RTL8402: 1717 case RTSX_RTL8411: 1718 case RTSX_RTL8411B: 1719 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK, 1720 RTSX_BPP_POWER_5_PERCENT_ON); 1721 RTSX_BITOP(sc, RTSX_LDO_CTL, RTSX_BPP_LDO_POWB, 1722 RTSX_BPP_LDO_SUSPEND); 1723 DELAY(150); 1724 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK, 1725 RTSX_BPP_POWER_10_PERCENT_ON); 1726 DELAY(150); 1727 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK, 1728 RTSX_BPP_POWER_15_PERCENT_ON); 1729 DELAY(150); 1730 RTSX_BITOP(sc, RTSX_CARD_PWR_CTL, RTSX_BPP_POWER_MASK, 1731 RTSX_BPP_POWER_ON); 1732 RTSX_BITOP(sc, RTSX_LDO_CTL, RTSX_BPP_LDO_POWB, 1733 RTSX_BPP_LDO_ON); 1734 break; 1735 } 1736 1737 /* Enable SD card output. */ 1738 RTSX_WRITE(sc, RTSX_CARD_OE, RTSX_SD_OUTPUT_EN); 1739 1740 DELAY(200); 1741 1742 return (0); 1743 } 1744 1745 /* 1746 * Set but width. 1747 */ 1748 static int 1749 rtsx_set_bus_width(struct rtsx_softc *sc, enum mmc_bus_width width) 1750 { 1751 uint32_t bus_width; 1752 1753 switch (width) { 1754 case bus_width_1: 1755 bus_width = RTSX_BUS_WIDTH_1; 1756 break; 1757 case bus_width_4: 1758 bus_width = RTSX_BUS_WIDTH_4; 1759 break; 1760 case bus_width_8: 1761 bus_width = RTSX_BUS_WIDTH_8; 1762 break; 1763 default: 1764 return (MMC_ERR_INVALID); 1765 } 1766 RTSX_BITOP(sc, RTSX_SD_CFG1, RTSX_BUS_WIDTH_MASK, bus_width); 1767 1768 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) { 1769 char *busw[] = { 1770 "1 bit", 1771 "4 bits", 1772 "8 bits" 1773 }; 1774 device_printf(sc->rtsx_dev, "Setting bus width to %s\n", busw[bus_width]); 1775 } 1776 return (0); 1777 } 1778 1779 static int 1780 rtsx_set_sd_timing(struct rtsx_softc *sc, enum mmc_bus_timing timing) 1781 { 1782 if (timing == bus_timing_hs && sc->rtsx_force_timing) { 1783 timing = bus_timing_uhs_sdr50; 1784 sc->rtsx_ios_timing = timing; 1785 } 1786 1787 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 1788 device_printf(sc->rtsx_dev, "rtsx_set_sd_timing(%u)\n", timing); 1789 1790 switch (timing) { 1791 case bus_timing_uhs_sdr50: 1792 case bus_timing_uhs_sdr104: 1793 sc->rtsx_double_clk = false; 1794 sc->rtsx_vpclk = true; 1795 RTSX_BITOP(sc, RTSX_SD_CFG1, 0x0c | RTSX_SD_ASYNC_FIFO_NOT_RST, 1796 RTSX_SD30_MODE | RTSX_SD_ASYNC_FIFO_NOT_RST); 1797 RTSX_BITOP(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ, RTSX_CLK_LOW_FREQ); 1798 RTSX_WRITE(sc, RTSX_CARD_CLK_SOURCE, 1799 RTSX_CRC_VAR_CLK0 | RTSX_SD30_FIX_CLK | RTSX_SAMPLE_VAR_CLK1); 1800 RTSX_CLR(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ); 1801 break; 1802 case bus_timing_hs: 1803 RTSX_BITOP(sc, RTSX_SD_CFG1, RTSX_SD_MODE_MASK, RTSX_SD20_MODE); 1804 RTSX_BITOP(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ, RTSX_CLK_LOW_FREQ); 1805 RTSX_WRITE(sc, RTSX_CARD_CLK_SOURCE, 1806 RTSX_CRC_FIX_CLK | RTSX_SD30_VAR_CLK0 | RTSX_SAMPLE_VAR_CLK1); 1807 RTSX_CLR(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ); 1808 1809 RTSX_BITOP(sc, RTSX_SD_PUSH_POINT_CTL, 1810 RTSX_SD20_TX_SEL_MASK, RTSX_SD20_TX_14_AHEAD); 1811 RTSX_BITOP(sc, RTSX_SD_SAMPLE_POINT_CTL, 1812 RTSX_SD20_RX_SEL_MASK, RTSX_SD20_RX_14_DELAY); 1813 break; 1814 default: 1815 RTSX_BITOP(sc, RTSX_SD_CFG1, RTSX_SD_MODE_MASK, RTSX_SD20_MODE); 1816 RTSX_BITOP(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ, RTSX_CLK_LOW_FREQ); 1817 RTSX_WRITE(sc, RTSX_CARD_CLK_SOURCE, 1818 RTSX_CRC_FIX_CLK | RTSX_SD30_VAR_CLK0 | RTSX_SAMPLE_VAR_CLK1); 1819 RTSX_CLR(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ); 1820 1821 RTSX_WRITE(sc, RTSX_SD_PUSH_POINT_CTL, RTSX_SD20_TX_NEG_EDGE); 1822 RTSX_BITOP(sc, RTSX_SD_SAMPLE_POINT_CTL, 1823 RTSX_SD20_RX_SEL_MASK, RTSX_SD20_RX_POS_EDGE); 1824 break; 1825 } 1826 1827 return (0); 1828 } 1829 1830 /* 1831 * Set or change SDCLK frequency or disable the SD clock. 1832 * Return zero on success. 1833 */ 1834 static int 1835 rtsx_set_sd_clock(struct rtsx_softc *sc, uint32_t freq) 1836 { 1837 uint8_t clk; 1838 uint8_t clk_divider, n, div, mcu; 1839 int error = 0; 1840 1841 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 1842 device_printf(sc->rtsx_dev, "rtsx_set_sd_clock(%u)\n", freq); 1843 1844 if (freq == RTSX_SDCLK_OFF) { 1845 error = rtsx_stop_sd_clock(sc); 1846 return error; 1847 } 1848 1849 sc->rtsx_ssc_depth = RTSX_SSC_DEPTH_500K; 1850 sc->rtsx_discovery_mode = (freq <= 1000000) ? true : false; 1851 1852 if (sc->rtsx_discovery_mode) { 1853 /* We use 250k(around) here, in discovery stage. */ 1854 clk_divider = RTSX_CLK_DIVIDE_128; 1855 freq = 30000000; 1856 } else { 1857 clk_divider = RTSX_CLK_DIVIDE_0; 1858 } 1859 RTSX_BITOP(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK, clk_divider); 1860 1861 freq /= 1000000; 1862 if (sc->rtsx_discovery_mode || !sc->rtsx_double_clk) 1863 clk = freq; 1864 else 1865 clk = freq * 2; 1866 1867 switch (sc->rtsx_device_id) { 1868 case RTSX_RTL8402: 1869 case RTSX_RTL8411: 1870 case RTSX_RTL8411B: 1871 n = clk * 4 / 5 - 2; 1872 break; 1873 default: 1874 n = clk - 2; 1875 break; 1876 } 1877 if ((clk <= 2) || (n > RTSX_MAX_DIV_N)) 1878 return (MMC_ERR_INVALID); 1879 1880 mcu = 125 / clk + 3; 1881 if (mcu > 15) 1882 mcu = 15; 1883 1884 /* Make sure that the SSC clock div_n is not less than RTSX_MIN_DIV_N. */ 1885 div = RTSX_CLK_DIV_1; 1886 while ((n < RTSX_MIN_DIV_N) && (div < RTSX_CLK_DIV_8)) { 1887 switch (sc->rtsx_device_id) { 1888 case RTSX_RTL8402: 1889 case RTSX_RTL8411: 1890 case RTSX_RTL8411B: 1891 n = (((n + 2) * 5 / 4) * 2) * 4 / 5 - 2; 1892 break; 1893 default: 1894 n = (n + 2) * 2 - 2; 1895 break; 1896 } 1897 div++; 1898 } 1899 1900 if (sc->rtsx_double_clk && sc->rtsx_ssc_depth > 1) 1901 sc->rtsx_ssc_depth -= 1; 1902 1903 if (div > RTSX_CLK_DIV_1) { 1904 if (sc->rtsx_ssc_depth > (div - 1)) 1905 sc->rtsx_ssc_depth -= (div - 1); 1906 else 1907 sc->rtsx_ssc_depth = RTSX_SSC_DEPTH_4M; 1908 } 1909 1910 /* Enable SD clock. */ 1911 error = rtsx_switch_sd_clock(sc, clk, n, div, mcu); 1912 1913 return (error); 1914 } 1915 1916 static int 1917 rtsx_stop_sd_clock(struct rtsx_softc *sc) 1918 { 1919 RTSX_CLR(sc, RTSX_CARD_CLK_EN, RTSX_CARD_CLK_EN_ALL); 1920 RTSX_SET(sc, RTSX_SD_BUS_STAT, RTSX_SD_CLK_FORCE_STOP); 1921 1922 return (0); 1923 } 1924 1925 static int 1926 rtsx_switch_sd_clock(struct rtsx_softc *sc, uint8_t clk, uint8_t n, uint8_t div, uint8_t mcu) 1927 { 1928 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) { 1929 device_printf(sc->rtsx_dev, "rtsx_switch_sd_clock() - discovery-mode is %s, ssc_depth: %d\n", 1930 (sc->rtsx_discovery_mode) ? "true" : "false", sc->rtsx_ssc_depth); 1931 device_printf(sc->rtsx_dev, "rtsx_switch_sd_clock() - clk: %d, n: %d, div: %d, mcu: %d\n", 1932 clk, n, div, mcu); 1933 } 1934 1935 RTSX_BITOP(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ, RTSX_CLK_LOW_FREQ); 1936 RTSX_WRITE(sc, RTSX_CLK_DIV, (div << 4) | mcu); 1937 RTSX_CLR(sc, RTSX_SSC_CTL1, RTSX_RSTB); 1938 RTSX_BITOP(sc, RTSX_SSC_CTL2, RTSX_SSC_DEPTH_MASK, sc->rtsx_ssc_depth); 1939 RTSX_WRITE(sc, RTSX_SSC_DIV_N_0, n); 1940 RTSX_BITOP(sc, RTSX_SSC_CTL1, RTSX_RSTB, RTSX_RSTB); 1941 if (sc->rtsx_vpclk) { 1942 RTSX_CLR(sc, RTSX_SD_VPCLK0_CTL, RTSX_PHASE_NOT_RESET); 1943 RTSX_BITOP(sc, RTSX_SD_VPCLK0_CTL, RTSX_PHASE_NOT_RESET, RTSX_PHASE_NOT_RESET); 1944 } 1945 1946 /* Wait SSC clock stable. */ 1947 DELAY(200); 1948 1949 RTSX_CLR(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ); 1950 1951 return (0); 1952 } 1953 1954 #ifndef MMCCAM 1955 static void 1956 rtsx_sd_change_tx_phase(struct rtsx_softc *sc, uint8_t sample_point) 1957 { 1958 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 1959 device_printf(sc->rtsx_dev, "rtsx_sd_change_tx_phase() - sample_point: %d\n", sample_point); 1960 1961 rtsx_write(sc, RTSX_CLK_CTL, RTSX_CHANGE_CLK, RTSX_CHANGE_CLK); 1962 rtsx_write(sc, RTSX_SD_VPCLK0_CTL, RTSX_PHASE_SELECT_MASK, sample_point); 1963 rtsx_write(sc, RTSX_SD_VPCLK0_CTL, RTSX_PHASE_NOT_RESET, 0); 1964 rtsx_write(sc, RTSX_SD_VPCLK0_CTL, RTSX_PHASE_NOT_RESET, RTSX_PHASE_NOT_RESET); 1965 rtsx_write(sc, RTSX_CLK_CTL, RTSX_CHANGE_CLK, 0); 1966 rtsx_write(sc, RTSX_SD_CFG1, RTSX_SD_ASYNC_FIFO_NOT_RST, 0); 1967 } 1968 1969 static void 1970 rtsx_sd_change_rx_phase(struct rtsx_softc *sc, uint8_t sample_point) 1971 { 1972 if (sc->rtsx_debug_mask & RTSX_DEBUG_TUNING) 1973 device_printf(sc->rtsx_dev, "rtsx_sd_change_rx_phase() - sample_point: %d\n", sample_point); 1974 1975 rtsx_write(sc, RTSX_CLK_CTL, RTSX_CHANGE_CLK, RTSX_CHANGE_CLK); 1976 rtsx_write(sc, RTSX_SD_VPCLK1_CTL, RTSX_PHASE_SELECT_MASK, sample_point); 1977 rtsx_write(sc, RTSX_SD_VPCLK1_CTL, RTSX_PHASE_NOT_RESET, 0); 1978 rtsx_write(sc, RTSX_SD_VPCLK1_CTL, RTSX_PHASE_NOT_RESET, RTSX_PHASE_NOT_RESET); 1979 rtsx_write(sc, RTSX_CLK_CTL, RTSX_CHANGE_CLK, 0); 1980 rtsx_write(sc, RTSX_SD_CFG1, RTSX_SD_ASYNC_FIFO_NOT_RST, 0); 1981 } 1982 1983 static void 1984 rtsx_sd_tuning_rx_phase(struct rtsx_softc *sc, uint32_t *phase_map) 1985 { 1986 uint32_t raw_phase_map = 0; 1987 int i; 1988 int error; 1989 1990 for (i = 0; i < RTSX_RX_PHASE_MAX; i++) { 1991 error = rtsx_sd_tuning_rx_cmd(sc, (uint8_t)i); 1992 if (error == 0) 1993 raw_phase_map |= 1 << i; 1994 } 1995 if (phase_map != NULL) 1996 *phase_map = raw_phase_map; 1997 } 1998 1999 static int 2000 rtsx_sd_tuning_rx_cmd(struct rtsx_softc *sc, uint8_t sample_point) 2001 { 2002 struct mmc_request req = {}; 2003 struct mmc_command cmd = {}; 2004 int error = 0; 2005 2006 cmd.opcode = MMC_SEND_TUNING_BLOCK; 2007 cmd.arg = 0; 2008 req.cmd = &cmd; 2009 2010 RTSX_LOCK(sc); 2011 2012 sc->rtsx_req = &req; 2013 2014 rtsx_sd_change_rx_phase(sc, sample_point); 2015 2016 rtsx_write(sc, RTSX_SD_CFG3, RTSX_SD_RSP_80CLK_TIMEOUT_EN, 2017 RTSX_SD_RSP_80CLK_TIMEOUT_EN); 2018 2019 rtsx_init_cmd(sc, &cmd); 2020 rtsx_set_cmd_data_len(sc, 1, 0x40); 2021 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 0xff, 2022 RTSX_SD_CALCULATE_CRC7 | RTSX_SD_CHECK_CRC16 | 2023 RTSX_SD_NO_WAIT_BUSY_END | RTSX_SD_CHECK_CRC7 | RTSX_SD_RSP_LEN_6); 2024 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 2025 0xff, RTSX_TM_AUTO_TUNING | RTSX_SD_TRANSFER_START); 2026 rtsx_push_cmd(sc, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, 2027 RTSX_SD_TRANSFER_END, RTSX_SD_TRANSFER_END); 2028 2029 /* Set interrupt post processing */ 2030 sc->rtsx_intr_trans_ok = rtsx_sd_tuning_rx_cmd_wakeup; 2031 sc->rtsx_intr_trans_ko = rtsx_sd_tuning_rx_cmd_wakeup; 2032 2033 /* Run the command queue. */ 2034 rtsx_send_cmd(sc); 2035 2036 error = rtsx_sd_tuning_rx_cmd_wait(sc, &cmd); 2037 2038 if (error) { 2039 if (sc->rtsx_debug_mask & RTSX_DEBUG_TUNING) 2040 device_printf(sc->rtsx_dev, "rtsx_sd_tuning_rx_cmd() - error: %d\n", error); 2041 rtsx_sd_wait_data_idle(sc); 2042 rtsx_clear_error(sc); 2043 } 2044 rtsx_write(sc, RTSX_SD_CFG3, RTSX_SD_RSP_80CLK_TIMEOUT_EN, 0); 2045 2046 sc->rtsx_req = NULL; 2047 2048 RTSX_UNLOCK(sc); 2049 2050 return (error); 2051 } 2052 2053 static int 2054 rtsx_sd_tuning_rx_cmd_wait(struct rtsx_softc *sc, struct mmc_command *cmd) 2055 { 2056 int status; 2057 int mask = RTSX_TRANS_OK_INT | RTSX_TRANS_FAIL_INT; 2058 2059 status = sc->rtsx_intr_status & mask; 2060 while (status == 0) { 2061 if (msleep(&sc->rtsx_intr_status, &sc->rtsx_mtx, 0, "rtsxintr", sc->rtsx_timeout_cmd) == EWOULDBLOCK) { 2062 cmd->error = MMC_ERR_TIMEOUT; 2063 return (MMC_ERR_TIMEOUT); 2064 } 2065 status = sc->rtsx_intr_status & mask; 2066 } 2067 return (cmd->error); 2068 } 2069 2070 static void 2071 rtsx_sd_tuning_rx_cmd_wakeup(struct rtsx_softc *sc) 2072 { 2073 wakeup(&sc->rtsx_intr_status); 2074 } 2075 2076 static void 2077 rtsx_sd_wait_data_idle(struct rtsx_softc *sc) 2078 { 2079 int i; 2080 uint8_t val; 2081 2082 for (i = 0; i < 100; i++) { 2083 rtsx_read(sc, RTSX_SD_DATA_STATE, &val); 2084 if (val & RTSX_SD_DATA_IDLE) 2085 return; 2086 DELAY(100); 2087 } 2088 } 2089 2090 static uint8_t 2091 rtsx_sd_search_final_rx_phase(struct rtsx_softc *sc, uint32_t phase_map) 2092 { 2093 int start = 0, len = 0; 2094 int start_final = 0, len_final = 0; 2095 uint8_t final_phase = 0xff; 2096 2097 while (start < RTSX_RX_PHASE_MAX) { 2098 len = rtsx_sd_get_rx_phase_len(phase_map, start); 2099 if (len_final < len) { 2100 start_final = start; 2101 len_final = len; 2102 } 2103 start += len ? len : 1; 2104 } 2105 2106 final_phase = (start_final + len_final / 2) % RTSX_RX_PHASE_MAX; 2107 2108 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 2109 device_printf(sc->rtsx_dev, 2110 "rtsx_sd_search_final_rx_phase() - phase_map: %x, start_final: %d, len_final: %d, final_phase: %d\n", 2111 phase_map, start_final, len_final, final_phase); 2112 2113 return final_phase; 2114 } 2115 2116 static int 2117 rtsx_sd_get_rx_phase_len(uint32_t phase_map, int start_bit) 2118 { 2119 int i; 2120 2121 for (i = 0; i < RTSX_RX_PHASE_MAX; i++) { 2122 if ((phase_map & (1 << (start_bit + i) % RTSX_RX_PHASE_MAX)) == 0) 2123 return i; 2124 } 2125 return RTSX_RX_PHASE_MAX; 2126 } 2127 #endif /* !MMCCAM */ 2128 2129 #if 0 /* For led */ 2130 static int 2131 rtsx_led_enable(struct rtsx_softc *sc) 2132 { 2133 switch (sc->rtsx_device_id) { 2134 case RTSX_RTS5209: 2135 RTSX_CLR(sc, RTSX_CARD_GPIO, RTSX_CARD_GPIO_LED_OFF); 2136 RTSX_WRITE(sc, RTSX_CARD_AUTO_BLINK, 2137 RTSX_LED_BLINK_EN | RTSX_LED_BLINK_SPEED); 2138 break; 2139 case RTSX_RTL8411B: 2140 RTSX_CLR(sc, RTSX_GPIO_CTL, 0x01); 2141 RTSX_WRITE(sc, RTSX_CARD_AUTO_BLINK, 2142 RTSX_LED_BLINK_EN | RTSX_LED_BLINK_SPEED); 2143 break; 2144 default: 2145 RTSX_SET(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON); 2146 RTSX_SET(sc, RTSX_OLT_LED_CTL, RTSX_OLT_LED_AUTOBLINK); 2147 break; 2148 } 2149 2150 return (0); 2151 } 2152 2153 static int 2154 rtsx_led_disable(struct rtsx_softc *sc) 2155 { 2156 switch (sc->rtsx_device_id) { 2157 case RTSX_RTS5209: 2158 RTSX_CLR(sc, RTSX_CARD_AUTO_BLINK, RTSX_LED_BLINK_EN); 2159 RTSX_WRITE(sc, RTSX_CARD_GPIO, RTSX_CARD_GPIO_LED_OFF); 2160 break; 2161 case RTSX_RTL8411B: 2162 RTSX_CLR(sc, RTSX_CARD_AUTO_BLINK, RTSX_LED_BLINK_EN); 2163 RTSX_SET(sc, RTSX_GPIO_CTL, 0x01); 2164 break; 2165 default: 2166 RTSX_CLR(sc, RTSX_OLT_LED_CTL, RTSX_OLT_LED_AUTOBLINK); 2167 RTSX_CLR(sc, RTSX_GPIO_CTL, RTSX_GPIO_LED_ON); 2168 break; 2169 } 2170 2171 return (0); 2172 } 2173 #endif /* For led */ 2174 2175 static uint8_t 2176 rtsx_response_type(uint16_t mmc_rsp) 2177 { 2178 int i; 2179 struct rsp_type { 2180 uint16_t mmc_rsp; 2181 uint8_t rtsx_rsp; 2182 } rsp_types[] = { 2183 { MMC_RSP_NONE, RTSX_SD_RSP_TYPE_R0 }, 2184 { MMC_RSP_R1, RTSX_SD_RSP_TYPE_R1 }, 2185 { MMC_RSP_R1B, RTSX_SD_RSP_TYPE_R1B }, 2186 { MMC_RSP_R2, RTSX_SD_RSP_TYPE_R2 }, 2187 { MMC_RSP_R3, RTSX_SD_RSP_TYPE_R3 }, 2188 { MMC_RSP_R4, RTSX_SD_RSP_TYPE_R4 }, 2189 { MMC_RSP_R5, RTSX_SD_RSP_TYPE_R5 }, 2190 { MMC_RSP_R6, RTSX_SD_RSP_TYPE_R6 }, 2191 { MMC_RSP_R7, RTSX_SD_RSP_TYPE_R7 } 2192 }; 2193 2194 for (i = 0; i < nitems(rsp_types); i++) { 2195 if (mmc_rsp == rsp_types[i].mmc_rsp) 2196 return (rsp_types[i].rtsx_rsp); 2197 } 2198 2199 return (0); 2200 } 2201 2202 /* 2203 * Init command buffer with SD command index and argument. 2204 */ 2205 static void 2206 rtsx_init_cmd(struct rtsx_softc *sc, struct mmc_command *cmd) 2207 { 2208 sc->rtsx_cmd_index = 0; 2209 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CMD0, 2210 0xff, RTSX_SD_CMD_START | cmd->opcode); 2211 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CMD1, 2212 0xff, cmd->arg >> 24); 2213 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CMD2, 2214 0xff, cmd->arg >> 16); 2215 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CMD3, 2216 0xff, cmd->arg >> 8); 2217 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CMD4, 2218 0xff, cmd->arg); 2219 } 2220 2221 /* 2222 * Append a properly encoded host command to the host command buffer. 2223 */ 2224 static void 2225 rtsx_push_cmd(struct rtsx_softc *sc, uint8_t cmd, uint16_t reg, 2226 uint8_t mask, uint8_t data) 2227 { 2228 KASSERT(sc->rtsx_cmd_index < RTSX_HOSTCMD_MAX, 2229 ("rtsx: Too many host commands (%d)\n", sc->rtsx_cmd_index)); 2230 2231 uint32_t *cmd_buffer = (uint32_t *)(sc->rtsx_cmd_dmamem); 2232 cmd_buffer[sc->rtsx_cmd_index++] = 2233 htole32((uint32_t)(cmd & 0x3) << 30) | 2234 ((uint32_t)(reg & 0x3fff) << 16) | 2235 ((uint32_t)(mask) << 8) | 2236 ((uint32_t)data); 2237 } 2238 2239 /* 2240 * Queue commands to configure data transfer size. 2241 */ 2242 static void 2243 rtsx_set_cmd_data_len(struct rtsx_softc *sc, uint16_t block_cnt, uint16_t byte_cnt) 2244 { 2245 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BLOCK_CNT_L, 2246 0xff, block_cnt & 0xff); 2247 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BLOCK_CNT_H, 2248 0xff, block_cnt >> 8); 2249 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BYTE_CNT_L, 2250 0xff, byte_cnt & 0xff); 2251 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BYTE_CNT_H, 2252 0xff, byte_cnt >> 8); 2253 } 2254 2255 /* 2256 * Run the command queue. 2257 */ 2258 static void 2259 rtsx_send_cmd(struct rtsx_softc *sc) 2260 { 2261 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 2262 device_printf(sc->rtsx_dev, "rtsx_send_cmd()\n"); 2263 2264 sc->rtsx_intr_status = 0; 2265 2266 /* Sync command DMA buffer. */ 2267 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_PREREAD); 2268 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_PREWRITE); 2269 2270 /* Tell the chip where the command buffer is and run the commands. */ 2271 WRITE4(sc, RTSX_HCBAR, (uint32_t)sc->rtsx_cmd_buffer); 2272 WRITE4(sc, RTSX_HCBCTLR, 2273 ((sc->rtsx_cmd_index * 4) & 0x00ffffff) | RTSX_START_CMD | RTSX_HW_AUTO_RSP); 2274 } 2275 2276 /* 2277 * Stop previous command. 2278 */ 2279 static void 2280 rtsx_stop_cmd(struct rtsx_softc *sc) 2281 { 2282 /* Stop command transfer. */ 2283 WRITE4(sc, RTSX_HCBCTLR, RTSX_STOP_CMD); 2284 2285 /* Stop DMA transfer. */ 2286 WRITE4(sc, RTSX_HDBCTLR, RTSX_STOP_DMA); 2287 2288 switch (sc->rtsx_device_id) { 2289 case RTSX_RTS5260: 2290 rtsx_write(sc, RTSX_RTS5260_DMA_RST_CTL_0, 2291 RTSX_RTS5260_DMA_RST | RTSX_RTS5260_ADMA3_RST, 2292 RTSX_RTS5260_DMA_RST | RTSX_RTS5260_ADMA3_RST); 2293 rtsx_write(sc, RTSX_RBCTL, RTSX_RB_FLUSH, RTSX_RB_FLUSH); 2294 break; 2295 default: 2296 rtsx_write(sc, RTSX_DMACTL, RTSX_DMA_RST, RTSX_DMA_RST); 2297 2298 rtsx_write(sc, RTSX_RBCTL, RTSX_RB_FLUSH, RTSX_RB_FLUSH); 2299 break; 2300 } 2301 } 2302 2303 /* 2304 * Clear error. 2305 */ 2306 static void 2307 rtsx_clear_error(struct rtsx_softc *sc) 2308 { 2309 /* Clear error. */ 2310 rtsx_write(sc, RTSX_CARD_STOP, RTSX_SD_STOP | RTSX_SD_CLR_ERR, 2311 RTSX_SD_STOP | RTSX_SD_CLR_ERR); 2312 } 2313 2314 /* 2315 * Signal end of request to mmc/mmcsd. 2316 */ 2317 static void 2318 rtsx_req_done(struct rtsx_softc *sc) 2319 { 2320 #ifdef MMCCAM 2321 union ccb *ccb; 2322 #endif /* MMCCAM */ 2323 struct mmc_request *req; 2324 2325 req = sc->rtsx_req; 2326 if (req->cmd->error == MMC_ERR_NONE) { 2327 if (req->cmd->opcode == MMC_READ_SINGLE_BLOCK || 2328 req->cmd->opcode == MMC_READ_MULTIPLE_BLOCK) 2329 sc->rtsx_read_count++; 2330 else if (req->cmd->opcode == MMC_WRITE_BLOCK || 2331 req->cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK) 2332 sc->rtsx_write_count++; 2333 } else { 2334 rtsx_clear_error(sc); 2335 } 2336 callout_stop(&sc->rtsx_timeout_callout); 2337 sc->rtsx_req = NULL; 2338 #ifdef MMCCAM 2339 ccb = sc->rtsx_ccb; 2340 sc->rtsx_ccb = NULL; 2341 ccb->ccb_h.status = (req->cmd->error == 0 ? CAM_REQ_CMP : CAM_REQ_CMP_ERR); 2342 xpt_done(ccb); 2343 #else /* !MMCCAM */ 2344 req->done(req); 2345 #endif /* MMCCAM */ 2346 } 2347 2348 /* 2349 * Send request. 2350 */ 2351 static int 2352 rtsx_send_req(struct rtsx_softc *sc, struct mmc_command *cmd) 2353 { 2354 uint8_t rsp_type; 2355 uint16_t reg; 2356 2357 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 2358 device_printf(sc->rtsx_dev, "rtsx_send_req() - CMD%d\n", cmd->opcode); 2359 2360 /* Convert response type. */ 2361 rsp_type = rtsx_response_type(cmd->flags & MMC_RSP_MASK); 2362 if (rsp_type == 0) { 2363 device_printf(sc->rtsx_dev, "Unknown rsp_type: 0x%lx\n", (cmd->flags & MMC_RSP_MASK)); 2364 cmd->error = MMC_ERR_INVALID; 2365 return (MMC_ERR_INVALID); 2366 } 2367 2368 rtsx_init_cmd(sc, cmd); 2369 2370 /* Queue command to set response type. */ 2371 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 0xff, rsp_type); 2372 2373 /* Use the ping-pong buffer (cmd buffer) for commands which do not transfer data. */ 2374 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_CARD_DATA_SOURCE, 2375 0x01, RTSX_PINGPONG_BUFFER); 2376 2377 /* Queue commands to perform SD transfer. */ 2378 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 2379 0xff, RTSX_TM_CMD_RSP | RTSX_SD_TRANSFER_START); 2380 rtsx_push_cmd(sc, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, 2381 RTSX_SD_TRANSFER_END|RTSX_SD_STAT_IDLE, 2382 RTSX_SD_TRANSFER_END|RTSX_SD_STAT_IDLE); 2383 2384 /* If needed queue commands to read back card status response. */ 2385 if (rsp_type == RTSX_SD_RSP_TYPE_R2) { 2386 /* Read data from ping-pong buffer. */ 2387 for (reg = RTSX_PPBUF_BASE2; reg < RTSX_PPBUF_BASE2 + 16; reg++) 2388 rtsx_push_cmd(sc, RTSX_READ_REG_CMD, reg, 0, 0); 2389 } else if (rsp_type != RTSX_SD_RSP_TYPE_R0) { 2390 /* Read data from SD_CMDx registers. */ 2391 for (reg = RTSX_SD_CMD0; reg <= RTSX_SD_CMD4; reg++) 2392 rtsx_push_cmd(sc, RTSX_READ_REG_CMD, reg, 0, 0); 2393 } 2394 rtsx_push_cmd(sc, RTSX_READ_REG_CMD, RTSX_SD_STAT1, 0, 0); 2395 2396 /* Set transfer OK function. */ 2397 if (sc->rtsx_intr_trans_ok == NULL) 2398 sc->rtsx_intr_trans_ok = rtsx_ret_resp; 2399 2400 /* Run the command queue. */ 2401 rtsx_send_cmd(sc); 2402 2403 return (0); 2404 } 2405 2406 /* 2407 * Return response of previous command (case cmd->data == NULL) and complete resquest. 2408 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2409 */ 2410 static void 2411 rtsx_ret_resp(struct rtsx_softc *sc) 2412 { 2413 struct mmc_command *cmd; 2414 2415 cmd = sc->rtsx_req->cmd; 2416 rtsx_set_resp(sc, cmd); 2417 rtsx_req_done(sc); 2418 } 2419 2420 /* 2421 * Set response of previous command. 2422 */ 2423 static void 2424 rtsx_set_resp(struct rtsx_softc *sc, struct mmc_command *cmd) 2425 { 2426 uint8_t rsp_type; 2427 2428 rsp_type = rtsx_response_type(cmd->flags & MMC_RSP_MASK); 2429 2430 /* Sync command DMA buffer. */ 2431 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTREAD); 2432 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTWRITE); 2433 2434 /* Copy card response into mmc response buffer. */ 2435 if (ISSET(cmd->flags, MMC_RSP_PRESENT)) { 2436 uint32_t *cmd_buffer = (uint32_t *)(sc->rtsx_cmd_dmamem); 2437 2438 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) { 2439 device_printf(sc->rtsx_dev, "cmd_buffer: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", 2440 cmd_buffer[0], cmd_buffer[1], cmd_buffer[2], cmd_buffer[3], cmd_buffer[4]); 2441 } 2442 2443 if (rsp_type == RTSX_SD_RSP_TYPE_R2) { 2444 /* First byte is CHECK_REG_CMD return value, skip it. */ 2445 unsigned char *ptr = (unsigned char *)cmd_buffer + 1; 2446 int i; 2447 2448 /* 2449 * The controller offloads the last byte {CRC-7, end bit 1} 2450 * of response type R2. Assign dummy CRC, 0, and end bit to this 2451 * byte (ptr[16], goes into the LSB of resp[3] later). 2452 */ 2453 ptr[16] = 0x01; 2454 /* The second byte is the status of response, skip it. */ 2455 for (i = 0; i < 4; i++) 2456 cmd->resp[i] = be32dec(ptr + 1 + i * 4); 2457 } else { 2458 /* 2459 * First byte is CHECK_REG_CMD return value, second 2460 * one is the command op code -- we skip those. 2461 */ 2462 cmd->resp[0] = 2463 ((be32toh(cmd_buffer[0]) & 0x0000ffff) << 16) | 2464 ((be32toh(cmd_buffer[1]) & 0xffff0000) >> 16); 2465 } 2466 2467 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 2468 device_printf(sc->rtsx_dev, "cmd->resp: 0x%08x 0x%08x 0x%08x 0x%08x\n", 2469 cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); 2470 } 2471 } 2472 2473 /* 2474 * Use the ping-pong buffer (cmd buffer) for transfer <= 512 bytes. 2475 */ 2476 static int 2477 rtsx_xfer_short(struct rtsx_softc *sc, struct mmc_command *cmd) 2478 { 2479 int read; 2480 2481 if (cmd->data == NULL || cmd->data->len == 0) { 2482 cmd->error = MMC_ERR_INVALID; 2483 return (MMC_ERR_INVALID); 2484 } 2485 cmd->data->xfer_len = (cmd->data->len > RTSX_MAX_DATA_BLKLEN) ? 2486 RTSX_MAX_DATA_BLKLEN : cmd->data->len; 2487 2488 read = ISSET(cmd->data->flags, MMC_DATA_READ); 2489 2490 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 2491 device_printf(sc->rtsx_dev, "rtsx_xfer_short() - %s xfer: %ld bytes with block size %ld\n", 2492 read ? "Read" : "Write", 2493 (unsigned long)cmd->data->len, (unsigned long)cmd->data->xfer_len); 2494 2495 if (cmd->data->len > 512) { 2496 device_printf(sc->rtsx_dev, "rtsx_xfer_short() - length too large: %ld > 512\n", 2497 (unsigned long)cmd->data->len); 2498 cmd->error = MMC_ERR_INVALID; 2499 return (MMC_ERR_INVALID); 2500 } 2501 2502 if (read) { 2503 if (sc->rtsx_discovery_mode) 2504 rtsx_write(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK, RTSX_CLK_DIVIDE_0); 2505 2506 rtsx_init_cmd(sc, cmd); 2507 2508 /* Queue commands to configure data transfer size. */ 2509 rtsx_set_cmd_data_len(sc, cmd->data->len / cmd->data->xfer_len, cmd->data->xfer_len); 2510 2511 /* From Linux: rtsx_pci_sdmmc.c sd_read_data(). */ 2512 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 0xff, 2513 RTSX_SD_CALCULATE_CRC7 | RTSX_SD_CHECK_CRC16 | 2514 RTSX_SD_NO_WAIT_BUSY_END | RTSX_SD_CHECK_CRC7 | RTSX_SD_RSP_LEN_6); 2515 2516 /* Use the ping-pong buffer (cmd buffer). */ 2517 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_CARD_DATA_SOURCE, 2518 0x01, RTSX_PINGPONG_BUFFER); 2519 2520 /* Queue commands to perform SD transfer. */ 2521 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 2522 0xff, RTSX_TM_NORMAL_READ | RTSX_SD_TRANSFER_START); 2523 rtsx_push_cmd(sc, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, 2524 RTSX_SD_TRANSFER_END, RTSX_SD_TRANSFER_END); 2525 2526 /* Set transfer OK function. */ 2527 sc->rtsx_intr_trans_ok = rtsx_ask_ppbuf_part1; 2528 2529 /* Run the command queue. */ 2530 rtsx_send_cmd(sc); 2531 } else { 2532 /* Set transfer OK function. */ 2533 sc->rtsx_intr_trans_ok = rtsx_put_ppbuf_part1; 2534 2535 /* Run the command queue. */ 2536 rtsx_send_req(sc, cmd); 2537 } 2538 2539 return (0); 2540 } 2541 2542 /* 2543 * Use the ping-pong buffer (cmd buffer) for the transfer - first part <= 256 bytes. 2544 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2545 */ 2546 static void 2547 rtsx_ask_ppbuf_part1(struct rtsx_softc *sc) 2548 { 2549 struct mmc_command *cmd; 2550 uint16_t reg = RTSX_PPBUF_BASE2; 2551 int len; 2552 int i; 2553 2554 cmd = sc->rtsx_req->cmd; 2555 len = (cmd->data->len > RTSX_HOSTCMD_MAX) ? RTSX_HOSTCMD_MAX : cmd->data->len; 2556 2557 sc->rtsx_cmd_index = 0; 2558 for (i = 0; i < len; i++) { 2559 rtsx_push_cmd(sc, RTSX_READ_REG_CMD, reg++, 0, 0); 2560 } 2561 2562 /* Set transfer OK function. */ 2563 sc->rtsx_intr_trans_ok = rtsx_get_ppbuf_part1; 2564 2565 /* Run the command queue. */ 2566 rtsx_send_cmd(sc); 2567 } 2568 2569 /* 2570 * Get the data from the ping-pong buffer (cmd buffer) - first part <= 256 bytes. 2571 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2572 */ 2573 static void 2574 rtsx_get_ppbuf_part1(struct rtsx_softc *sc) 2575 { 2576 struct mmc_command *cmd; 2577 uint8_t *ptr; 2578 int len; 2579 2580 cmd = sc->rtsx_req->cmd; 2581 ptr = cmd->data->data; 2582 len = (cmd->data->len > RTSX_HOSTCMD_MAX) ? RTSX_HOSTCMD_MAX : cmd->data->len; 2583 2584 /* Sync command DMA buffer. */ 2585 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTREAD); 2586 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTWRITE); 2587 2588 memcpy(ptr, sc->rtsx_cmd_dmamem, len); 2589 2590 len = (cmd->data->len > RTSX_HOSTCMD_MAX) ? cmd->data->len - RTSX_HOSTCMD_MAX : 0; 2591 2592 /* Use the ping-pong buffer (cmd buffer) for the transfer - second part > 256 bytes. */ 2593 if (len > 0) { 2594 uint16_t reg = RTSX_PPBUF_BASE2 + RTSX_HOSTCMD_MAX; 2595 int i; 2596 2597 sc->rtsx_cmd_index = 0; 2598 for (i = 0; i < len; i++) { 2599 rtsx_push_cmd(sc, RTSX_READ_REG_CMD, reg++, 0, 0); 2600 } 2601 2602 /* Set transfer OK function. */ 2603 sc->rtsx_intr_trans_ok = rtsx_get_ppbuf_part2; 2604 2605 /* Run the command queue. */ 2606 rtsx_send_cmd(sc); 2607 } else { 2608 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD && cmd->opcode == ACMD_SEND_SCR) { 2609 uint8_t *ptr = cmd->data->data; 2610 device_printf(sc->rtsx_dev, "SCR: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n", 2611 ptr[0], ptr[1], ptr[2], ptr[3], 2612 ptr[4], ptr[5], ptr[6], ptr[7]); 2613 } 2614 2615 if (sc->rtsx_discovery_mode) 2616 rtsx_write(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK, RTSX_CLK_DIVIDE_128); 2617 2618 rtsx_req_done(sc); 2619 } 2620 } 2621 2622 /* 2623 * Get the data from the ping-pong buffer (cmd buffer) - second part > 256 bytes. 2624 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2625 */ 2626 static void 2627 rtsx_get_ppbuf_part2(struct rtsx_softc *sc) 2628 { 2629 struct mmc_command *cmd; 2630 uint8_t *ptr; 2631 int len; 2632 2633 cmd = sc->rtsx_req->cmd; 2634 ptr = cmd->data->data; 2635 ptr += RTSX_HOSTCMD_MAX; 2636 len = cmd->data->len - RTSX_HOSTCMD_MAX; 2637 2638 /* Sync command DMA buffer. */ 2639 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTREAD); 2640 bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTWRITE); 2641 2642 memcpy(ptr, sc->rtsx_cmd_dmamem, len); 2643 2644 if (sc->rtsx_discovery_mode) 2645 rtsx_write(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK, RTSX_CLK_DIVIDE_128); 2646 2647 rtsx_req_done(sc); 2648 } 2649 2650 /* 2651 * Use the ping-pong buffer (cmd buffer) for transfer - first part <= 256 bytes. 2652 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2653 */ 2654 static void 2655 rtsx_put_ppbuf_part1(struct rtsx_softc *sc) 2656 { 2657 struct mmc_command *cmd; 2658 uint16_t reg = RTSX_PPBUF_BASE2; 2659 uint8_t *ptr; 2660 int len; 2661 int i; 2662 2663 cmd = sc->rtsx_req->cmd; 2664 ptr = cmd->data->data; 2665 len = (cmd->data->len > RTSX_HOSTCMD_MAX) ? RTSX_HOSTCMD_MAX : cmd->data->len; 2666 2667 rtsx_set_resp(sc, cmd); 2668 2669 sc->rtsx_cmd_index = 0; 2670 for (i = 0; i < len; i++) { 2671 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, reg++, 0xff, *ptr); 2672 ptr++; 2673 } 2674 2675 /* Set transfer OK function. */ 2676 if (cmd->data->len > RTSX_HOSTCMD_MAX) 2677 sc->rtsx_intr_trans_ok = rtsx_put_ppbuf_part2; 2678 else 2679 sc->rtsx_intr_trans_ok = rtsx_write_ppbuf; 2680 2681 /* Run the command queue. */ 2682 rtsx_send_cmd(sc); 2683 } 2684 2685 /* 2686 * Use the ping-pong buffer (cmd buffer) for transfer - second part > 256 bytes. 2687 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2688 */ 2689 static void 2690 rtsx_put_ppbuf_part2(struct rtsx_softc *sc) 2691 { 2692 struct mmc_command *cmd; 2693 uint16_t reg = RTSX_PPBUF_BASE2 + RTSX_HOSTCMD_MAX; 2694 uint8_t *ptr; 2695 int len; 2696 int i; 2697 2698 cmd = sc->rtsx_req->cmd; 2699 ptr = cmd->data->data; 2700 ptr += RTSX_HOSTCMD_MAX; 2701 len = cmd->data->len - RTSX_HOSTCMD_MAX; 2702 2703 sc->rtsx_cmd_index = 0; 2704 for (i = 0; i < len; i++) { 2705 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, reg++, 0xff, *ptr); 2706 ptr++; 2707 } 2708 2709 /* Set transfer OK function. */ 2710 sc->rtsx_intr_trans_ok = rtsx_write_ppbuf; 2711 2712 /* Run the command queue. */ 2713 rtsx_send_cmd(sc); 2714 } 2715 2716 /* 2717 * Write the data previously given via the ping-pong buffer on the card. 2718 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2719 */ 2720 static void 2721 rtsx_write_ppbuf(struct rtsx_softc *sc) 2722 { 2723 struct mmc_command *cmd; 2724 2725 cmd = sc->rtsx_req->cmd; 2726 2727 sc->rtsx_cmd_index = 0; 2728 2729 /* Queue commands to configure data transfer size. */ 2730 rtsx_set_cmd_data_len(sc, cmd->data->len / cmd->data->xfer_len, cmd->data->xfer_len); 2731 2732 /* From Linux: rtsx_pci_sdmmc.c sd_write_data(). */ 2733 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 0xff, 2734 RTSX_SD_CALCULATE_CRC7 | RTSX_SD_CHECK_CRC16 | 2735 RTSX_SD_NO_WAIT_BUSY_END | RTSX_SD_CHECK_CRC7 | RTSX_SD_RSP_LEN_0); 2736 2737 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 0xff, 2738 RTSX_TM_AUTO_WRITE3 | RTSX_SD_TRANSFER_START); 2739 rtsx_push_cmd(sc, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, 2740 RTSX_SD_TRANSFER_END, RTSX_SD_TRANSFER_END); 2741 2742 /* Set transfer OK function. */ 2743 sc->rtsx_intr_trans_ok = rtsx_req_done; 2744 2745 /* Run the command queue. */ 2746 rtsx_send_cmd(sc); 2747 } 2748 2749 /* 2750 * Use the data buffer for transfer > 512 bytes. 2751 */ 2752 static int 2753 rtsx_xfer(struct rtsx_softc *sc, struct mmc_command *cmd) 2754 { 2755 int read = ISSET(cmd->data->flags, MMC_DATA_READ); 2756 2757 cmd->data->xfer_len = (cmd->data->len > RTSX_MAX_DATA_BLKLEN) ? 2758 RTSX_MAX_DATA_BLKLEN : cmd->data->len; 2759 2760 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 2761 device_printf(sc->rtsx_dev, "rtsx_xfer() - %s xfer: %ld bytes with block size %ld\n", 2762 read ? "Read" : "Write", 2763 (unsigned long)cmd->data->len, (unsigned long)cmd->data->xfer_len); 2764 2765 if (cmd->data->len > RTSX_DMA_DATA_BUFSIZE) { 2766 device_printf(sc->rtsx_dev, "rtsx_xfer() length too large: %ld > %d\n", 2767 (unsigned long)cmd->data->len, RTSX_DMA_DATA_BUFSIZE); 2768 cmd->error = MMC_ERR_INVALID; 2769 return (MMC_ERR_INVALID); 2770 } 2771 2772 if (!read) { 2773 /* Set transfer OK function. */ 2774 sc->rtsx_intr_trans_ok = rtsx_xfer_begin; 2775 2776 /* Run the command queue. */ 2777 rtsx_send_req(sc, cmd); 2778 } else { 2779 rtsx_xfer_start(sc); 2780 } 2781 2782 return (0); 2783 } 2784 2785 /* 2786 * Get request response and start dma data transfer (write command). 2787 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2788 */ 2789 static void 2790 rtsx_xfer_begin(struct rtsx_softc *sc) 2791 { 2792 struct mmc_command *cmd; 2793 2794 cmd = sc->rtsx_req->cmd; 2795 2796 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 2797 device_printf(sc->rtsx_dev, "rtsx_xfer_begin() - CMD%d\n", cmd->opcode); 2798 2799 rtsx_set_resp(sc, cmd); 2800 rtsx_xfer_start(sc); 2801 } 2802 2803 /* 2804 * Start dma data transfer. 2805 */ 2806 static void 2807 rtsx_xfer_start(struct rtsx_softc *sc) 2808 { 2809 struct mmc_command *cmd; 2810 int read; 2811 uint8_t cfg2; 2812 int dma_dir; 2813 int tmode; 2814 2815 cmd = sc->rtsx_req->cmd; 2816 read = ISSET(cmd->data->flags, MMC_DATA_READ); 2817 2818 /* Configure DMA transfer mode parameters. */ 2819 if (cmd->opcode == MMC_READ_MULTIPLE_BLOCK) 2820 cfg2 = RTSX_SD_CHECK_CRC16 | RTSX_SD_NO_WAIT_BUSY_END | RTSX_SD_RSP_LEN_6; 2821 else 2822 cfg2 = RTSX_SD_CHECK_CRC16 | RTSX_SD_NO_WAIT_BUSY_END | RTSX_SD_RSP_LEN_0; 2823 if (read) { 2824 dma_dir = RTSX_DMA_DIR_FROM_CARD; 2825 /* 2826 * Use transfer mode AUTO_READ1, which assume we not 2827 * already send the read command and don't need to send 2828 * CMD 12 manually after read. 2829 */ 2830 tmode = RTSX_TM_AUTO_READ1; 2831 cfg2 |= RTSX_SD_CALCULATE_CRC7 | RTSX_SD_CHECK_CRC7; 2832 2833 rtsx_init_cmd(sc, cmd); 2834 } else { 2835 dma_dir = RTSX_DMA_DIR_TO_CARD; 2836 /* 2837 * Use transfer mode AUTO_WRITE3, wich assumes we've already 2838 * sent the write command and gotten the response, and will 2839 * send CMD 12 manually after writing. 2840 */ 2841 tmode = RTSX_TM_AUTO_WRITE3; 2842 cfg2 |= RTSX_SD_NO_CALCULATE_CRC7 | RTSX_SD_NO_CHECK_CRC7; 2843 2844 sc->rtsx_cmd_index = 0; 2845 } 2846 2847 /* Queue commands to configure data transfer size. */ 2848 rtsx_set_cmd_data_len(sc, cmd->data->len / cmd->data->xfer_len, cmd->data->xfer_len); 2849 2850 /* Configure DMA controller. */ 2851 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_IRQSTAT0, 2852 RTSX_DMA_DONE_INT, RTSX_DMA_DONE_INT); 2853 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMATC3, 2854 0xff, cmd->data->len >> 24); 2855 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMATC2, 2856 0xff, cmd->data->len >> 16); 2857 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMATC1, 2858 0xff, cmd->data->len >> 8); 2859 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMATC0, 2860 0xff, cmd->data->len); 2861 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_DMACTL, 2862 RTSX_DMA_EN | RTSX_DMA_DIR | RTSX_DMA_PACK_SIZE_MASK, 2863 RTSX_DMA_EN | dma_dir | RTSX_DMA_512); 2864 2865 /* Use the DMA ring buffer for commands which transfer data. */ 2866 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_CARD_DATA_SOURCE, 2867 0x01, RTSX_RING_BUFFER); 2868 2869 /* Queue command to set response type. */ 2870 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 0xff, cfg2); 2871 2872 /* Queue commands to perform SD transfer. */ 2873 rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER, 2874 0xff, tmode | RTSX_SD_TRANSFER_START); 2875 rtsx_push_cmd(sc, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER, 2876 RTSX_SD_TRANSFER_END, RTSX_SD_TRANSFER_END); 2877 2878 /* Run the command queue. */ 2879 rtsx_send_cmd(sc); 2880 2881 if (!read) 2882 memcpy(sc->rtsx_data_dmamem, cmd->data->data, cmd->data->len); 2883 2884 /* Sync data DMA buffer. */ 2885 bus_dmamap_sync(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamap, BUS_DMASYNC_PREREAD); 2886 bus_dmamap_sync(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamap, BUS_DMASYNC_PREWRITE); 2887 2888 /* Set transfer OK function. */ 2889 sc->rtsx_intr_trans_ok = rtsx_xfer_finish; 2890 2891 /* Tell the chip where the data buffer is and run the transfer. */ 2892 WRITE4(sc, RTSX_HDBAR, sc->rtsx_data_buffer); 2893 WRITE4(sc, RTSX_HDBCTLR, RTSX_TRIG_DMA | (read ? RTSX_DMA_READ : 0) | 2894 (cmd->data->len & 0x00ffffff)); 2895 } 2896 2897 /* 2898 * Finish dma data transfer. 2899 * This Function is called by the interrupt handler via sc->rtsx_intr_trans_ok. 2900 */ 2901 static void 2902 rtsx_xfer_finish(struct rtsx_softc *sc) 2903 { 2904 struct mmc_command *cmd; 2905 int read; 2906 2907 cmd = sc->rtsx_req->cmd; 2908 2909 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 2910 device_printf(sc->rtsx_dev, "rtsx_xfer_finish() - CMD%d\n", cmd->opcode); 2911 2912 read = ISSET(cmd->data->flags, MMC_DATA_READ); 2913 2914 /* Sync data DMA buffer. */ 2915 bus_dmamap_sync(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamap, BUS_DMASYNC_POSTREAD); 2916 bus_dmamap_sync(sc->rtsx_data_dma_tag, sc->rtsx_data_dmamap, BUS_DMASYNC_POSTWRITE); 2917 2918 if (read) { 2919 memcpy(cmd->data->data, sc->rtsx_data_dmamem, cmd->data->len); 2920 rtsx_req_done(sc); 2921 } else { 2922 /* Send CMD12 after AUTO_WRITE3 (see mmcsd_rw() in mmcsd.c) */ 2923 /* and complete request. */ 2924 sc->rtsx_intr_trans_ok = NULL; 2925 rtsx_send_req(sc, sc->rtsx_req->stop); 2926 } 2927 } 2928 2929 /* 2930 * Manage request timeout. 2931 */ 2932 static void 2933 rtsx_timeout(void *arg) 2934 { 2935 struct rtsx_softc *sc; 2936 2937 sc = (struct rtsx_softc *)arg; 2938 if (sc->rtsx_req != NULL) { 2939 device_printf(sc->rtsx_dev, "Controller timeout for CMD%u\n", 2940 sc->rtsx_req->cmd->opcode); 2941 sc->rtsx_req->cmd->error = MMC_ERR_TIMEOUT; 2942 rtsx_stop_cmd(sc); 2943 rtsx_req_done(sc); 2944 } else { 2945 device_printf(sc->rtsx_dev, "Controller timeout!\n"); 2946 } 2947 } 2948 2949 #ifdef MMCCAM 2950 static int 2951 rtsx_get_tran_settings(device_t dev, struct ccb_trans_settings_mmc *cts) 2952 { 2953 struct rtsx_softc *sc; 2954 2955 sc = device_get_softc(dev); 2956 2957 cts->host_ocr = sc->rtsx_host.host_ocr; 2958 cts->host_f_min = sc->rtsx_host.f_min; 2959 cts->host_f_max = sc->rtsx_host.f_max; 2960 cts->host_caps = sc->rtsx_host.caps; 2961 cts->host_max_data = RTSX_DMA_DATA_BUFSIZE / MMC_SECTOR_SIZE; 2962 memcpy(&cts->ios, &sc->rtsx_host.ios, sizeof(struct mmc_ios)); 2963 2964 return (0); 2965 } 2966 2967 /* 2968 * Apply settings and return status accordingly. 2969 */ 2970 static int 2971 rtsx_set_tran_settings(device_t dev, struct ccb_trans_settings_mmc *cts) 2972 { 2973 struct rtsx_softc *sc; 2974 struct mmc_ios *ios; 2975 struct mmc_ios *new_ios; 2976 2977 sc = device_get_softc(dev); 2978 2979 ios = &sc->rtsx_host.ios; 2980 new_ios = &cts->ios; 2981 2982 /* Update only requested fields */ 2983 if (cts->ios_valid & MMC_CLK) { 2984 ios->clock = new_ios->clock; 2985 sc->rtsx_ios_clock = -1; /* To be updated by rtsx_mmcbr_update_ios(). */ 2986 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 2987 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - clock: %u\n", ios->clock); 2988 } 2989 if (cts->ios_valid & MMC_VDD) { 2990 ios->vdd = new_ios->vdd; 2991 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 2992 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - vdd: %d\n", ios->vdd); 2993 } 2994 if (cts->ios_valid & MMC_CS) { 2995 ios->chip_select = new_ios->chip_select; 2996 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 2997 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - chip_select: %d\n", ios->chip_select); 2998 } 2999 if (cts->ios_valid & MMC_BW) { 3000 ios->bus_width = new_ios->bus_width; 3001 sc->rtsx_ios_bus_width = -1; /* To be updated by rtsx_mmcbr_update_ios(). */ 3002 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 3003 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - bus width: %d\n", ios->bus_width); 3004 } 3005 if (cts->ios_valid & MMC_PM) { 3006 ios->power_mode = new_ios->power_mode; 3007 sc->rtsx_ios_power_mode = -1; /* To be updated by rtsx_mmcbr_update_ios(). */ 3008 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 3009 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - power mode: %d\n", ios->power_mode); 3010 } 3011 if (cts->ios_valid & MMC_BT) { 3012 ios->timing = new_ios->timing; 3013 sc->rtsx_ios_timing = -1; /* To be updated by rtsx_mmcbr_update_ios(). */ 3014 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 3015 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - timing: %d\n", ios->timing); 3016 } 3017 if (cts->ios_valid & MMC_BM) { 3018 ios->bus_mode = new_ios->bus_mode; 3019 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 3020 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - bus mode: %d\n", ios->bus_mode); 3021 } 3022 #if __FreeBSD_version >= 1300000 3023 if (cts->ios_valid & MMC_VCCQ) { 3024 ios->vccq = new_ios->vccq; 3025 sc->rtsx_ios_vccq = -1; /* To be updated by rtsx_mmcbr_update_ios(). */ 3026 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 3027 device_printf(sc->rtsx_dev, "rtsx_set_tran_settings() - vccq: %d\n", ios->vccq); 3028 } 3029 #endif /* __FreeBSD_version >= 1300000 */ 3030 if (rtsx_mmcbr_update_ios(sc->rtsx_dev, NULL) == 0) 3031 return (CAM_REQ_CMP); 3032 else 3033 return (CAM_REQ_CMP_ERR); 3034 } 3035 3036 /* 3037 * Build a request and run it. 3038 */ 3039 static int 3040 rtsx_cam_request(device_t dev, union ccb *ccb) 3041 { 3042 struct rtsx_softc *sc; 3043 3044 sc = device_get_softc(dev); 3045 3046 RTSX_LOCK(sc); 3047 if (sc->rtsx_ccb != NULL) { 3048 RTSX_UNLOCK(sc); 3049 return (CAM_BUSY); 3050 } 3051 sc->rtsx_ccb = ccb; 3052 sc->rtsx_cam_req.cmd = &ccb->mmcio.cmd; 3053 sc->rtsx_cam_req.stop = &ccb->mmcio.stop; 3054 RTSX_UNLOCK(sc); 3055 3056 rtsx_mmcbr_request(sc->rtsx_dev, NULL, &sc->rtsx_cam_req); 3057 return (0); 3058 } 3059 #endif /* MMCCAM */ 3060 3061 static int 3062 rtsx_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) 3063 { 3064 struct rtsx_softc *sc; 3065 3066 sc = device_get_softc(bus); 3067 switch (which) { 3068 case MMCBR_IVAR_BUS_MODE: /* ivar 0 - 1 = opendrain, 2 = pushpull */ 3069 *result = sc->rtsx_host.ios.bus_mode; 3070 break; 3071 case MMCBR_IVAR_BUS_WIDTH: /* ivar 1 - 0 = 1b 2 = 4b, 3 = 8b */ 3072 *result = sc->rtsx_host.ios.bus_width; 3073 break; 3074 case MMCBR_IVAR_CHIP_SELECT: /* ivar 2 - O = dontcare, 1 = cs_high, 2 = cs_low */ 3075 *result = sc->rtsx_host.ios.chip_select; 3076 break; 3077 case MMCBR_IVAR_CLOCK: /* ivar 3 - clock in Hz */ 3078 *result = sc->rtsx_host.ios.clock; 3079 break; 3080 case MMCBR_IVAR_F_MIN: /* ivar 4 */ 3081 *result = sc->rtsx_host.f_min; 3082 break; 3083 case MMCBR_IVAR_F_MAX: /* ivar 5 */ 3084 *result = sc->rtsx_host.f_max; 3085 break; 3086 case MMCBR_IVAR_HOST_OCR: /* ivar 6 - host operation conditions register */ 3087 *result = sc->rtsx_host.host_ocr; 3088 break; 3089 case MMCBR_IVAR_MODE: /* ivar 7 - 0 = mode_mmc, 1 = mode_sd */ 3090 *result = sc->rtsx_host.mode; 3091 break; 3092 case MMCBR_IVAR_OCR: /* ivar 8 - operation conditions register */ 3093 *result = sc->rtsx_host.ocr; 3094 break; 3095 case MMCBR_IVAR_POWER_MODE: /* ivar 9 - 0 = off, 1 = up, 2 = on */ 3096 *result = sc->rtsx_host.ios.power_mode; 3097 break; 3098 case MMCBR_IVAR_VDD: /* ivar 11 - voltage power pin */ 3099 *result = sc->rtsx_host.ios.vdd; 3100 break; 3101 case MMCBR_IVAR_VCCQ: /* ivar 12 - signaling: 0 = 1.20V, 1 = 1.80V, 2 = 3.30V */ 3102 *result = sc->rtsx_host.ios.vccq; 3103 break; 3104 case MMCBR_IVAR_CAPS: /* ivar 13 */ 3105 *result = sc->rtsx_host.caps; 3106 break; 3107 case MMCBR_IVAR_TIMING: /* ivar 14 - 0 = normal, 1 = timing_hs, ... */ 3108 *result = sc->rtsx_host.ios.timing; 3109 break; 3110 case MMCBR_IVAR_MAX_DATA: /* ivar 15 */ 3111 *result = RTSX_DMA_DATA_BUFSIZE / MMC_SECTOR_SIZE; 3112 break; 3113 case MMCBR_IVAR_RETUNE_REQ: /* ivar 10 */ 3114 case MMCBR_IVAR_MAX_BUSY_TIMEOUT: /* ivar 16 */ 3115 default: 3116 return (EINVAL); 3117 } 3118 3119 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 3120 device_printf(bus, "Read ivar #%d, value %#x / #%d\n", 3121 which, *(int *)result, *(int *)result); 3122 3123 return (0); 3124 } 3125 3126 static int 3127 rtsx_write_ivar(device_t bus, device_t child, int which, uintptr_t value) 3128 { 3129 struct rtsx_softc *sc; 3130 3131 sc = device_get_softc(bus); 3132 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 3133 device_printf(bus, "Write ivar #%d, value %#x / #%d\n", 3134 which, (int)value, (int)value); 3135 3136 switch (which) { 3137 case MMCBR_IVAR_BUS_MODE: /* ivar 0 - 1 = opendrain, 2 = pushpull */ 3138 sc->rtsx_host.ios.bus_mode = value; 3139 break; 3140 case MMCBR_IVAR_BUS_WIDTH: /* ivar 1 - 0 = 1b 2 = 4b, 3 = 8b */ 3141 sc->rtsx_host.ios.bus_width = value; 3142 sc->rtsx_ios_bus_width = -1; /* To be updated on next rtsx_mmcbr_update_ios(). */ 3143 break; 3144 case MMCBR_IVAR_CHIP_SELECT: /* ivar 2 - O = dontcare, 1 = cs_high, 2 = cs_low */ 3145 sc->rtsx_host.ios.chip_select = value; 3146 break; 3147 case MMCBR_IVAR_CLOCK: /* ivar 3 - clock in Hz */ 3148 sc->rtsx_host.ios.clock = value; 3149 sc->rtsx_ios_clock = -1; /* To be updated on next rtsx_mmcbr_update_ios(). */ 3150 break; 3151 case MMCBR_IVAR_MODE: /* ivar 7 - 0 = mode_mmc, 1 = mode_sd */ 3152 sc->rtsx_host.mode = value; 3153 break; 3154 case MMCBR_IVAR_OCR: /* ivar 8 - operation conditions register */ 3155 sc->rtsx_host.ocr = value; 3156 break; 3157 case MMCBR_IVAR_POWER_MODE: /* ivar 9 - 0 = off, 1 = up, 2 = on */ 3158 sc->rtsx_host.ios.power_mode = value; 3159 sc->rtsx_ios_power_mode = -1; /* To be updated on next rtsx_mmcbr_update_ios(). */ 3160 break; 3161 case MMCBR_IVAR_VDD: /* ivar 11 - voltage power pin */ 3162 sc->rtsx_host.ios.vdd = value; 3163 break; 3164 case MMCBR_IVAR_VCCQ: /* ivar 12 - signaling: 0 = 1.20V, 1 = 1.80V, 2 = 3.30V */ 3165 sc->rtsx_host.ios.vccq = value; 3166 sc->rtsx_ios_vccq = value; /* rtsx_mmcbr_switch_vccq() will be called by mmc.c (MMCCAM undef). */ 3167 break; 3168 case MMCBR_IVAR_TIMING: /* ivar 14 - 0 = normal, 1 = timing_hs, ... */ 3169 sc->rtsx_host.ios.timing = value; 3170 sc->rtsx_ios_timing = -1; /* To be updated on next rtsx_mmcbr_update_ios(). */ 3171 break; 3172 /* These are read-only. */ 3173 case MMCBR_IVAR_F_MIN: /* ivar 4 */ 3174 case MMCBR_IVAR_F_MAX: /* ivar 5 */ 3175 case MMCBR_IVAR_HOST_OCR: /* ivar 6 - host operation conditions register */ 3176 case MMCBR_IVAR_RETUNE_REQ: /* ivar 10 */ 3177 case MMCBR_IVAR_CAPS: /* ivar 13 */ 3178 case MMCBR_IVAR_MAX_DATA: /* ivar 15 */ 3179 case MMCBR_IVAR_MAX_BUSY_TIMEOUT: /* ivar 16 */ 3180 default: 3181 return (EINVAL); 3182 } 3183 3184 return (0); 3185 } 3186 3187 static int 3188 rtsx_mmcbr_update_ios(device_t bus, device_t child__unused) 3189 { 3190 struct rtsx_softc *sc; 3191 struct mmc_ios *ios; 3192 int error; 3193 3194 sc = device_get_softc(bus); 3195 ios = &sc->rtsx_host.ios; 3196 3197 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 3198 device_printf(bus, "rtsx_mmcbr_update_ios()\n"); 3199 3200 /* if MMCBR_IVAR_BUS_WIDTH updated. */ 3201 if (sc->rtsx_ios_bus_width < 0) { 3202 sc->rtsx_ios_bus_width = ios->bus_width; 3203 if ((error = rtsx_set_bus_width(sc, ios->bus_width))) 3204 return (error); 3205 } 3206 3207 /* if MMCBR_IVAR_POWER_MODE updated. */ 3208 if (sc->rtsx_ios_power_mode < 0) { 3209 sc->rtsx_ios_power_mode = ios->power_mode; 3210 switch (ios->power_mode) { 3211 case power_off: 3212 if ((error = rtsx_bus_power_off(sc))) 3213 return (error); 3214 break; 3215 case power_up: 3216 if ((error = rtsx_bus_power_on(sc))) 3217 return (error); 3218 break; 3219 case power_on: 3220 if ((error = rtsx_bus_power_on(sc))) 3221 return (error); 3222 break; 3223 } 3224 } 3225 3226 sc->rtsx_double_clk = true; 3227 sc->rtsx_vpclk = false; 3228 3229 /* if MMCBR_IVAR_TIMING updated. */ 3230 if (sc->rtsx_ios_timing < 0) { 3231 sc->rtsx_ios_timing = ios->timing; 3232 if ((error = rtsx_set_sd_timing(sc, ios->timing))) 3233 return (error); 3234 } 3235 3236 /* if MMCBR_IVAR_CLOCK updated, must be after rtsx_set_sd_timing() */ 3237 if (sc->rtsx_ios_clock < 0) { 3238 sc->rtsx_ios_clock = ios->clock; 3239 if ((error = rtsx_set_sd_clock(sc, ios->clock))) 3240 return (error); 3241 } 3242 3243 /* if MMCCAM and vccq updated */ 3244 if (sc->rtsx_ios_vccq < 0) { 3245 sc->rtsx_ios_vccq = ios->vccq; 3246 if ((error = rtsx_mmcbr_switch_vccq(sc->rtsx_dev, NULL))) 3247 return (error); 3248 } 3249 3250 return (0); 3251 } 3252 3253 /* 3254 * Set output stage logic power voltage. 3255 */ 3256 static int 3257 rtsx_mmcbr_switch_vccq(device_t bus, device_t child __unused) 3258 { 3259 struct rtsx_softc *sc; 3260 int vccq = 0; 3261 int error; 3262 3263 sc = device_get_softc(bus); 3264 3265 switch (sc->rtsx_host.ios.vccq) { 3266 case vccq_120: 3267 vccq = 120; 3268 break; 3269 case vccq_180: 3270 vccq = 180; 3271 break; 3272 case vccq_330: 3273 vccq = 330; 3274 break; 3275 }; 3276 /* It seems it is always vccq_330. */ 3277 if (vccq == 330) { 3278 switch (sc->rtsx_device_id) { 3279 uint16_t val; 3280 case RTSX_RTS5227: 3281 if ((error = rtsx_write_phy(sc, 0x08, 0x4FE4))) 3282 return (error); 3283 if ((error = rtsx_rts5227_fill_driving(sc))) 3284 return (error); 3285 break; 3286 case RTSX_RTS5209: 3287 case RTSX_RTS5229: 3288 RTSX_BITOP(sc, RTSX_SD30_CMD_DRIVE_SEL, RTSX_SD30_DRIVE_SEL_MASK, sc->rtsx_sd30_drive_sel_3v3); 3289 if ((error = rtsx_write_phy(sc, 0x08, 0x4FE4))) 3290 return (error); 3291 break; 3292 case RTSX_RTS522A: 3293 if ((error = rtsx_write_phy(sc, 0x08, 0x57E4))) 3294 return (error); 3295 if ((error = rtsx_rts5227_fill_driving(sc))) 3296 return (error); 3297 break; 3298 case RTSX_RTS525A: 3299 RTSX_BITOP(sc, RTSX_LDO_CONFIG2, RTSX_LDO_D3318_MASK, RTSX_LDO_D3318_33V); 3300 RTSX_BITOP(sc, RTSX_SD_PAD_CTL, RTSX_SD_IO_USING_1V8, 0); 3301 if ((error = rtsx_rts5249_fill_driving(sc))) 3302 return (error); 3303 break; 3304 case RTSX_RTS5249: 3305 if ((error = rtsx_read_phy(sc, RTSX_PHY_TUNE, &val))) 3306 return (error); 3307 if ((error = rtsx_write_phy(sc, RTSX_PHY_TUNE, 3308 (val & RTSX_PHY_TUNE_VOLTAGE_MASK) | RTSX_PHY_TUNE_VOLTAGE_3V3))) 3309 return (error); 3310 if ((error = rtsx_rts5249_fill_driving(sc))) 3311 return (error); 3312 break; 3313 case RTSX_RTS5260: 3314 RTSX_BITOP(sc, RTSX_LDO_CONFIG2, RTSX_DV331812_VDD1, RTSX_DV331812_VDD1); 3315 RTSX_BITOP(sc, RTSX_LDO_DV18_CFG, RTSX_DV331812_MASK, RTSX_DV331812_33); 3316 RTSX_CLR(sc, RTSX_SD_PAD_CTL, RTSX_SD_IO_USING_1V8); 3317 if ((error = rtsx_rts5260_fill_driving(sc))) 3318 return (error); 3319 break; 3320 case RTSX_RTL8402: 3321 RTSX_BITOP(sc, RTSX_SD30_CMD_DRIVE_SEL, RTSX_SD30_DRIVE_SEL_MASK, sc->rtsx_sd30_drive_sel_3v3); 3322 RTSX_BITOP(sc, RTSX_LDO_CTL, 3323 (RTSX_BPP_ASIC_MASK << RTSX_BPP_SHIFT_8402) | RTSX_BPP_PAD_MASK, 3324 (RTSX_BPP_ASIC_3V3 << RTSX_BPP_SHIFT_8402) | RTSX_BPP_PAD_3V3); 3325 break; 3326 case RTSX_RTL8411: 3327 case RTSX_RTL8411B: 3328 RTSX_BITOP(sc, RTSX_SD30_CMD_DRIVE_SEL, RTSX_SD30_DRIVE_SEL_MASK, sc->rtsx_sd30_drive_sel_3v3); 3329 RTSX_BITOP(sc, RTSX_LDO_CTL, 3330 (RTSX_BPP_ASIC_MASK << RTSX_BPP_SHIFT_8411) | RTSX_BPP_PAD_MASK, 3331 (RTSX_BPP_ASIC_3V3 << RTSX_BPP_SHIFT_8411) | RTSX_BPP_PAD_3V3); 3332 break; 3333 } 3334 DELAY(300); 3335 } 3336 3337 if (sc->rtsx_debug_mask & (RTSX_DEBUG_BASIC | RTSX_TRACE_SD_CMD)) 3338 device_printf(sc->rtsx_dev, "rtsx_mmcbr_switch_vccq(%d)\n", vccq); 3339 3340 return (0); 3341 } 3342 3343 #ifndef MMCCAM 3344 /* 3345 * Tune card if bus_timing_uhs_sdr50. 3346 */ 3347 static int 3348 rtsx_mmcbr_tune(device_t bus, device_t child __unused, bool hs400) 3349 { 3350 struct rtsx_softc *sc; 3351 uint32_t raw_phase_map[RTSX_RX_TUNING_CNT] = {0}; 3352 uint32_t phase_map; 3353 uint8_t final_phase; 3354 int i; 3355 3356 sc = device_get_softc(bus); 3357 3358 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 3359 device_printf(sc->rtsx_dev, "rtsx_mmcbr_tune() - hs400 is %s\n", 3360 (hs400) ? "true" : "false"); 3361 3362 if (sc->rtsx_ios_timing != bus_timing_uhs_sdr50) 3363 return (0); 3364 3365 sc->rtsx_tuning_mode = true; 3366 3367 switch (sc->rtsx_device_id) { 3368 case RTSX_RTS5209: 3369 case RTSX_RTS5227: 3370 rtsx_sd_change_tx_phase(sc, 27); 3371 break; 3372 case RTSX_RTS522A: 3373 rtsx_sd_change_tx_phase(sc, 20); 3374 break; 3375 case RTSX_RTS5229: 3376 rtsx_sd_change_tx_phase(sc, 27); 3377 break; 3378 case RTSX_RTS525A: 3379 case RTSX_RTS5249: 3380 rtsx_sd_change_tx_phase(sc, 29); 3381 break; 3382 case RTSX_RTL8402: 3383 case RTSX_RTL8411: 3384 case RTSX_RTL8411B: 3385 rtsx_sd_change_tx_phase(sc, 7); 3386 break; 3387 } 3388 3389 /* trying rx tuning for bus_timing_uhs_sdr50. */ 3390 for (i = 0; i < RTSX_RX_TUNING_CNT; i++) { 3391 rtsx_sd_tuning_rx_phase(sc, &(raw_phase_map[i])); 3392 if (raw_phase_map[i] == 0) 3393 break; 3394 } 3395 3396 phase_map = 0xffffffff; 3397 for (i = 0; i < RTSX_RX_TUNING_CNT; i++) { 3398 if (sc->rtsx_debug_mask & (RTSX_DEBUG_BASIC | RTSX_DEBUG_TUNING)) 3399 device_printf(sc->rtsx_dev, "rtsx_mmcbr_tune() - RX raw_phase_map[%d]: 0x%08x\n", 3400 i, raw_phase_map[i]); 3401 phase_map &= raw_phase_map[i]; 3402 } 3403 if (sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 3404 device_printf(sc->rtsx_dev, "rtsx_mmcbr_tune() - RX phase_map: 0x%08x\n", phase_map); 3405 3406 if (phase_map) { 3407 final_phase = rtsx_sd_search_final_rx_phase(sc, phase_map); 3408 if (final_phase != 0xff) { 3409 rtsx_sd_change_rx_phase(sc, final_phase); 3410 } 3411 } 3412 3413 sc->rtsx_tuning_mode = false; 3414 3415 return (0); 3416 } 3417 3418 static int 3419 rtsx_mmcbr_retune(device_t bus, device_t child __unused, bool reset __unused) 3420 { 3421 struct rtsx_softc *sc; 3422 3423 sc = device_get_softc(bus); 3424 3425 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 3426 device_printf(sc->rtsx_dev, "rtsx_mmcbr_retune()\n"); 3427 3428 return (0); 3429 } 3430 #endif /* !MMCCAM */ 3431 3432 static int 3433 rtsx_mmcbr_request(device_t bus, device_t child __unused, struct mmc_request *req) 3434 { 3435 struct rtsx_softc *sc; 3436 struct mmc_command *cmd; 3437 int timeout; 3438 int error; 3439 3440 sc = device_get_softc(bus); 3441 3442 RTSX_LOCK(sc); 3443 if (sc->rtsx_req != NULL) { 3444 RTSX_UNLOCK(sc); 3445 return (EBUSY); 3446 } 3447 sc->rtsx_req = req; 3448 cmd = req->cmd; 3449 cmd->error = error = MMC_ERR_NONE; 3450 sc->rtsx_intr_status = 0; 3451 sc->rtsx_intr_trans_ok = NULL; 3452 sc->rtsx_intr_trans_ko = rtsx_req_done; 3453 3454 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 3455 device_printf(sc->rtsx_dev, "rtsx_mmcbr_request(CMD%u arg %#x, flags %#x, dlen %u, dflags %#x)\n", 3456 cmd->opcode, cmd->arg, cmd->flags, 3457 cmd->data != NULL ? (unsigned int)cmd->data->len : 0, 3458 cmd->data != NULL ? cmd->data->flags : 0); 3459 3460 /* Check if card present. */ 3461 if (!ISSET(sc->rtsx_flags, RTSX_F_CARD_PRESENT)) { 3462 cmd->error = error = MMC_ERR_FAILED; 3463 goto end; 3464 } 3465 3466 /* Refuse SDIO probe if the chip doesn't support SDIO. */ 3467 if (cmd->opcode == IO_SEND_OP_COND && 3468 !ISSET(sc->rtsx_flags, RTSX_F_SDIO_SUPPORT)) { 3469 cmd->error = error = MMC_ERR_INVALID; 3470 goto end; 3471 } 3472 3473 /* Return MMC_ERR_TIMEOUT for SD_IO_RW_DIRECT and IO_SEND_OP_COND. */ 3474 if (cmd->opcode == SD_IO_RW_DIRECT || cmd->opcode == IO_SEND_OP_COND) { 3475 cmd->error = error = MMC_ERR_TIMEOUT; 3476 goto end; 3477 } 3478 3479 /* Select SD card. */ 3480 RTSX_BITOP(sc, RTSX_CARD_SELECT, 0x07, RTSX_SD_MOD_SEL); 3481 RTSX_BITOP(sc, RTSX_CARD_SHARE_MODE, RTSX_CARD_SHARE_MASK, RTSX_CARD_SHARE_48_SD); 3482 3483 if (cmd->data == NULL) { 3484 DELAY(200); 3485 timeout = sc->rtsx_timeout_cmd; 3486 error = rtsx_send_req(sc, cmd); 3487 } else if (cmd->data->len <= 512) { 3488 timeout = sc->rtsx_timeout_io; 3489 error = rtsx_xfer_short(sc, cmd); 3490 } else { 3491 timeout = sc->rtsx_timeout_io; 3492 error = rtsx_xfer(sc, cmd); 3493 } 3494 end: 3495 if (error == MMC_ERR_NONE) { 3496 callout_reset(&sc->rtsx_timeout_callout, timeout * hz, rtsx_timeout, sc); 3497 } else { 3498 rtsx_req_done(sc); 3499 } 3500 RTSX_UNLOCK(sc); 3501 3502 return (error); 3503 } 3504 3505 #ifndef MMCCAM 3506 static int 3507 rtsx_mmcbr_get_ro(device_t bus, device_t child __unused) 3508 { 3509 struct rtsx_softc *sc; 3510 3511 sc = device_get_softc(bus); 3512 3513 if (sc->rtsx_inversion == 0) 3514 return (sc->rtsx_read_only); 3515 else 3516 return !(sc->rtsx_read_only); 3517 } 3518 3519 static int 3520 rtsx_mmcbr_acquire_host(device_t bus, device_t child __unused) 3521 { 3522 struct rtsx_softc *sc; 3523 3524 sc = device_get_softc(bus); 3525 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 3526 device_printf(bus, "rtsx_mmcbr_acquire_host()\n"); 3527 3528 RTSX_LOCK(sc); 3529 while (sc->rtsx_bus_busy) 3530 msleep(&sc->rtsx_bus_busy, &sc->rtsx_mtx, 0, "rtsxah", 0); 3531 sc->rtsx_bus_busy++; 3532 RTSX_UNLOCK(sc); 3533 3534 return (0); 3535 } 3536 3537 static int 3538 rtsx_mmcbr_release_host(device_t bus, device_t child __unused) 3539 { 3540 struct rtsx_softc *sc; 3541 3542 sc = device_get_softc(bus); 3543 if (sc->rtsx_debug_mask & RTSX_TRACE_SD_CMD) 3544 device_printf(bus, "rtsx_mmcbr_release_host()\n"); 3545 3546 RTSX_LOCK(sc); 3547 sc->rtsx_bus_busy--; 3548 wakeup(&sc->rtsx_bus_busy); 3549 RTSX_UNLOCK(sc); 3550 3551 return (0); 3552 } 3553 #endif /* !MMCCAM */ 3554 3555 /* 3556 * 3557 * PCI Support Functions 3558 * 3559 */ 3560 3561 /* 3562 * Compare the device ID (chip) of this device against the IDs that this driver 3563 * supports. If there is a match, set the description and return success. 3564 */ 3565 static int 3566 rtsx_probe(device_t dev) 3567 { 3568 uint16_t vendor_id; 3569 uint16_t device_id; 3570 int i; 3571 3572 vendor_id = pci_get_vendor(dev); 3573 device_id = pci_get_device(dev); 3574 3575 if (vendor_id != RTSX_REALTEK) 3576 return (ENXIO); 3577 for (i = 0; i < nitems(rtsx_ids); i++) { 3578 if (rtsx_ids[i].device_id == device_id) { 3579 device_set_desc(dev, rtsx_ids[i].desc); 3580 return (BUS_PROBE_DEFAULT); 3581 } 3582 } 3583 return (ENXIO); 3584 } 3585 3586 /* 3587 * Attach function is only called if the probe is successful. 3588 */ 3589 static int 3590 rtsx_attach(device_t dev) 3591 { 3592 struct rtsx_softc *sc = device_get_softc(dev); 3593 uint16_t vendor_id; 3594 uint16_t device_id; 3595 struct sysctl_ctx_list *ctx; 3596 struct sysctl_oid_list *tree; 3597 int msi_count = 1; 3598 uint32_t sdio_cfg; 3599 int error; 3600 char *maker; 3601 char *family; 3602 char *product; 3603 int i; 3604 3605 vendor_id = pci_get_vendor(dev); 3606 device_id = pci_get_device(dev); 3607 if (bootverbose) 3608 device_printf(dev, "Attach - Vendor ID: 0x%x - Device ID: 0x%x\n", 3609 vendor_id, device_id); 3610 3611 sc->rtsx_dev = dev; 3612 sc->rtsx_device_id = device_id; 3613 sc->rtsx_req = NULL; 3614 sc->rtsx_timeout_cmd = 1; 3615 sc->rtsx_timeout_io = 10; 3616 sc->rtsx_read_only = 0; 3617 sc->rtsx_inversion = 0; 3618 sc->rtsx_force_timing = 0; 3619 sc->rtsx_debug_mask = 0; 3620 sc->rtsx_read_count = 0; 3621 sc->rtsx_write_count = 0; 3622 3623 maker = kern_getenv("smbios.system.maker"); 3624 family = kern_getenv("smbios.system.family"); 3625 product = kern_getenv("smbios.system.product"); 3626 for (i = 0; rtsx_inversion_models[i].maker != NULL; i++) { 3627 if (strcmp(rtsx_inversion_models[i].maker, maker) == 0 && 3628 strcmp(rtsx_inversion_models[i].family, family) == 0 && 3629 strcmp(rtsx_inversion_models[i].product, product) == 0) { 3630 device_printf(dev, "Inversion activated for %s/%s/%s, see BUG in rtsx(4)\n", maker, family, product); 3631 device_printf(dev, "If a card is detected without an SD card present," 3632 " add dev.rtsx.0.inversion=0 in loader.conf(5)\n"); 3633 sc->rtsx_inversion = 1; 3634 } 3635 } 3636 3637 RTSX_LOCK_INIT(sc); 3638 3639 ctx = device_get_sysctl_ctx(dev); 3640 tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 3641 SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "timeout_io", CTLFLAG_RW, 3642 &sc->rtsx_timeout_io, 0, "Request timeout for I/O commands in seconds"); 3643 SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "timeout_cmd", CTLFLAG_RW, 3644 &sc->rtsx_timeout_cmd, 0, "Request timeout for setup commands in seconds"); 3645 SYSCTL_ADD_U8(ctx, tree, OID_AUTO, "read_only", CTLFLAG_RD, 3646 &sc->rtsx_read_only, 0, "Card is write protected"); 3647 SYSCTL_ADD_U8(ctx, tree, OID_AUTO, "inversion", CTLFLAG_RWTUN, 3648 &sc->rtsx_inversion, 0, "Inversion of card detection and read only status"); 3649 SYSCTL_ADD_U8(ctx, tree, OID_AUTO, "force_timing", CTLFLAG_RW, 3650 &sc->rtsx_force_timing, 0, "Force bus_timing_uhs_sdr50"); 3651 SYSCTL_ADD_U8(ctx, tree, OID_AUTO, "debug_mask", CTLFLAG_RWTUN, 3652 &sc->rtsx_debug_mask, 0, "debugging mask, see rtsx(4)"); 3653 SYSCTL_ADD_U64(ctx, tree, OID_AUTO, "read_count", CTLFLAG_RD | CTLFLAG_STATS, 3654 &sc->rtsx_read_count, 0, "Count of read operations"); 3655 SYSCTL_ADD_U64(ctx, tree, OID_AUTO, "write_count", CTLFLAG_RD | CTLFLAG_STATS, 3656 &sc->rtsx_write_count, 0, "Count of write operations"); 3657 3658 if (bootverbose || sc->rtsx_debug_mask & RTSX_DEBUG_BASIC) 3659 device_printf(dev, "We are running with inversion: %d\n", sc->rtsx_inversion); 3660 3661 /* Allocate IRQ. */ 3662 sc->rtsx_irq_res_id = 0; 3663 if (pci_alloc_msi(dev, &msi_count) == 0) 3664 sc->rtsx_irq_res_id = 1; 3665 sc->rtsx_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->rtsx_irq_res_id, 3666 RF_ACTIVE | (sc->rtsx_irq_res_id != 0 ? 0 : RF_SHAREABLE)); 3667 if (sc->rtsx_irq_res == NULL) { 3668 device_printf(dev, "Can't allocate IRQ resources for %d\n", sc->rtsx_irq_res_id); 3669 pci_release_msi(dev); 3670 return (ENXIO); 3671 } 3672 3673 callout_init_mtx(&sc->rtsx_timeout_callout, &sc->rtsx_mtx, 0); 3674 3675 /* Allocate memory resource. */ 3676 if (sc->rtsx_device_id == RTSX_RTS525A) 3677 sc->rtsx_mem_res_id = PCIR_BAR(1); 3678 else 3679 sc->rtsx_mem_res_id = PCIR_BAR(0); 3680 sc->rtsx_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->rtsx_mem_res_id, RF_ACTIVE); 3681 if (sc->rtsx_mem_res == NULL) { 3682 device_printf(dev, "Can't allocate memory resource for %d\n", sc->rtsx_mem_res_id); 3683 goto destroy_rtsx_irq_res; 3684 } 3685 3686 if (bootverbose) 3687 device_printf(dev, "rtsx_irq_res_id: %d, rtsx_mem_res_id: %d\n", 3688 sc->rtsx_irq_res_id, sc->rtsx_mem_res_id); 3689 3690 sc->rtsx_mem_btag = rman_get_bustag(sc->rtsx_mem_res); 3691 sc->rtsx_mem_bhandle = rman_get_bushandle(sc->rtsx_mem_res); 3692 3693 TIMEOUT_TASK_INIT(taskqueue_swi_giant, &sc->rtsx_card_insert_task, 0, 3694 rtsx_card_task, sc); 3695 TASK_INIT(&sc->rtsx_card_remove_task, 0, rtsx_card_task, sc); 3696 3697 /* Allocate two DMA buffers: a command buffer and a data buffer. */ 3698 error = rtsx_dma_alloc(sc); 3699 if (error) 3700 goto destroy_rtsx_irq_res; 3701 3702 /* Activate the interrupt. */ 3703 error = bus_setup_intr(dev, sc->rtsx_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 3704 NULL, rtsx_intr, sc, &sc->rtsx_irq_cookie); 3705 if (error) { 3706 device_printf(dev, "Can't set up irq [0x%x]!\n", error); 3707 goto destroy_rtsx_mem_res; 3708 } 3709 pci_enable_busmaster(dev); 3710 3711 if (rtsx_read_cfg(sc, 0, RTSX_SDIOCFG_REG, &sdio_cfg) == 0) { 3712 if ((sdio_cfg & RTSX_SDIOCFG_SDIO_ONLY) || 3713 (sdio_cfg & RTSX_SDIOCFG_HAVE_SDIO)) 3714 sc->rtsx_flags |= RTSX_F_SDIO_SUPPORT; 3715 } 3716 3717 #ifdef MMCCAM 3718 sc->rtsx_ccb = NULL; 3719 sc->rtsx_cam_status = 0; 3720 3721 SYSCTL_ADD_U8(ctx, tree, OID_AUTO, "cam_status", CTLFLAG_RD, 3722 &sc->rtsx_cam_status, 0, "driver cam card present"); 3723 3724 if (mmc_cam_sim_alloc(dev, "rtsx_mmc", &sc->rtsx_mmc_sim) != 0) { 3725 device_printf(dev, "Can't allocate CAM SIM\n"); 3726 goto destroy_rtsx_irq; 3727 } 3728 #endif /* MMCCAM */ 3729 3730 /* Initialize device. */ 3731 error = rtsx_init(sc); 3732 if (error) { 3733 device_printf(dev, "Error %d during rtsx_init()\n", error); 3734 goto destroy_rtsx_irq; 3735 } 3736 3737 /* 3738 * Schedule a card detection as we won't get an interrupt 3739 * if the card is inserted when we attach. We wait a quarter 3740 * of a second to allow for a "spontaneous" interrupt which may 3741 * change the card presence state. This delay avoid a panic 3742 * on some configuration (e.g. Lenovo T540p). 3743 */ 3744 DELAY(250000); 3745 if (rtsx_is_card_present(sc)) 3746 device_printf(sc->rtsx_dev, "A card is detected\n"); 3747 else 3748 device_printf(sc->rtsx_dev, "No card is detected\n"); 3749 rtsx_card_task(sc, 0); 3750 3751 if (bootverbose) 3752 device_printf(dev, "Device attached\n"); 3753 3754 return (0); 3755 3756 destroy_rtsx_irq: 3757 bus_teardown_intr(dev, sc->rtsx_irq_res, sc->rtsx_irq_cookie); 3758 destroy_rtsx_mem_res: 3759 bus_release_resource(dev, SYS_RES_MEMORY, sc->rtsx_mem_res_id, 3760 sc->rtsx_mem_res); 3761 rtsx_dma_free(sc); 3762 destroy_rtsx_irq_res: 3763 callout_drain(&sc->rtsx_timeout_callout); 3764 bus_release_resource(dev, SYS_RES_IRQ, sc->rtsx_irq_res_id, 3765 sc->rtsx_irq_res); 3766 pci_release_msi(dev); 3767 RTSX_LOCK_DESTROY(sc); 3768 3769 return (ENXIO); 3770 } 3771 3772 static int 3773 rtsx_detach(device_t dev) 3774 { 3775 struct rtsx_softc *sc = device_get_softc(dev); 3776 int error; 3777 3778 if (bootverbose) 3779 device_printf(dev, "Detach - Vendor ID: 0x%x - Device ID: 0x%x\n", 3780 pci_get_vendor(dev), sc->rtsx_device_id); 3781 3782 /* Disable interrupts. */ 3783 sc->rtsx_intr_enabled = 0; 3784 WRITE4(sc, RTSX_BIER, sc->rtsx_intr_enabled); 3785 3786 /* Stop device. */ 3787 error = device_delete_children(sc->rtsx_dev); 3788 sc->rtsx_mmc_dev = NULL; 3789 if (error) 3790 return (error); 3791 3792 taskqueue_drain_timeout(taskqueue_swi_giant, &sc->rtsx_card_insert_task); 3793 taskqueue_drain(taskqueue_swi_giant, &sc->rtsx_card_remove_task); 3794 3795 /* Teardown the state in our softc created in our attach routine. */ 3796 rtsx_dma_free(sc); 3797 if (sc->rtsx_mem_res != NULL) 3798 bus_release_resource(dev, SYS_RES_MEMORY, sc->rtsx_mem_res_id, 3799 sc->rtsx_mem_res); 3800 if (sc->rtsx_irq_cookie != NULL) 3801 bus_teardown_intr(dev, sc->rtsx_irq_res, sc->rtsx_irq_cookie); 3802 if (sc->rtsx_irq_res != NULL) { 3803 callout_drain(&sc->rtsx_timeout_callout); 3804 bus_release_resource(dev, SYS_RES_IRQ, sc->rtsx_irq_res_id, 3805 sc->rtsx_irq_res); 3806 pci_release_msi(dev); 3807 } 3808 RTSX_LOCK_DESTROY(sc); 3809 #ifdef MMCCAM 3810 mmc_cam_sim_free(&sc->rtsx_mmc_sim); 3811 #endif /* MMCCAM */ 3812 3813 return (0); 3814 } 3815 3816 static int 3817 rtsx_shutdown(device_t dev) 3818 { 3819 if (bootverbose) 3820 device_printf(dev, "Shutdown\n"); 3821 3822 return (0); 3823 } 3824 3825 /* 3826 * Device suspend routine. 3827 */ 3828 static int 3829 rtsx_suspend(device_t dev) 3830 { 3831 struct rtsx_softc *sc = device_get_softc(dev); 3832 3833 device_printf(dev, "Suspend\n"); 3834 3835 #ifdef MMCCAM 3836 if (sc->rtsx_ccb != NULL) { 3837 device_printf(dev, "Request in progress: CMD%u, rtsr_intr_status: 0x%08x\n", 3838 sc->rtsx_ccb->mmcio.cmd.opcode, sc->rtsx_intr_status); 3839 } 3840 #else /* !MMCCAM */ 3841 if (sc->rtsx_req != NULL) { 3842 device_printf(dev, "Request in progress: CMD%u, rtsr_intr_status: 0x%08x\n", 3843 sc->rtsx_req->cmd->opcode, sc->rtsx_intr_status); 3844 } 3845 #endif /* MMCCAM */ 3846 3847 bus_generic_suspend(dev); 3848 3849 return (0); 3850 } 3851 3852 /* 3853 * Device resume routine. 3854 */ 3855 static int 3856 rtsx_resume(device_t dev) 3857 { 3858 device_printf(dev, "Resume\n"); 3859 3860 rtsx_init(device_get_softc(dev)); 3861 3862 bus_generic_resume(dev); 3863 3864 return (0); 3865 } 3866 3867 static device_method_t rtsx_methods[] = { 3868 /* Device interface */ 3869 DEVMETHOD(device_probe, rtsx_probe), 3870 DEVMETHOD(device_attach, rtsx_attach), 3871 DEVMETHOD(device_detach, rtsx_detach), 3872 DEVMETHOD(device_shutdown, rtsx_shutdown), 3873 DEVMETHOD(device_suspend, rtsx_suspend), 3874 DEVMETHOD(device_resume, rtsx_resume), 3875 3876 /* Bus interface */ 3877 DEVMETHOD(bus_read_ivar, rtsx_read_ivar), 3878 DEVMETHOD(bus_write_ivar, rtsx_write_ivar), 3879 3880 #ifndef MMCCAM 3881 /* MMC bridge interface */ 3882 DEVMETHOD(mmcbr_update_ios, rtsx_mmcbr_update_ios), 3883 DEVMETHOD(mmcbr_switch_vccq, rtsx_mmcbr_switch_vccq), 3884 DEVMETHOD(mmcbr_tune, rtsx_mmcbr_tune), 3885 DEVMETHOD(mmcbr_retune, rtsx_mmcbr_retune), 3886 DEVMETHOD(mmcbr_request, rtsx_mmcbr_request), 3887 DEVMETHOD(mmcbr_get_ro, rtsx_mmcbr_get_ro), 3888 DEVMETHOD(mmcbr_acquire_host, rtsx_mmcbr_acquire_host), 3889 DEVMETHOD(mmcbr_release_host, rtsx_mmcbr_release_host), 3890 #endif /* !MMCCAM */ 3891 3892 #ifdef MMCCAM 3893 /* MMCCAM interface */ 3894 DEVMETHOD(mmc_sim_get_tran_settings, rtsx_get_tran_settings), 3895 DEVMETHOD(mmc_sim_set_tran_settings, rtsx_set_tran_settings), 3896 DEVMETHOD(mmc_sim_cam_request, rtsx_cam_request), 3897 #endif /* MMCCAM */ 3898 3899 DEVMETHOD_END 3900 }; 3901 3902 DEFINE_CLASS_0(rtsx, rtsx_driver, rtsx_methods, sizeof(struct rtsx_softc)); 3903 DRIVER_MODULE(rtsx, pci, rtsx_driver, NULL, NULL); 3904 3905 /* For Plug and Play */ 3906 MODULE_PNP_INFO("U16:device;D:#;T:vendor=0x10ec", pci, rtsx, 3907 rtsx_ids, nitems(rtsx_ids)); 3908 3909 #ifndef MMCCAM 3910 MMC_DECLARE_BRIDGE(rtsx); 3911 #endif /* !MMCCAM */ 3912