1 /*- 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 /* 35 * RealTek 8129/8139 PCI NIC driver 36 * 37 * Supports several extremely cheap PCI 10/100 adapters based on 38 * the RealTek chipset. Datasheets can be obtained from 39 * www.realtek.com.tw. 40 * 41 * Written by Bill Paul <wpaul@ctr.columbia.edu> 42 * Electrical Engineering Department 43 * Columbia University, New York City 44 */ 45 /* 46 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 47 * probably the worst PCI ethernet controller ever made, with the possible 48 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 49 * DMA, but it has a terrible interface that nullifies any performance 50 * gains that bus-master DMA usually offers. 51 * 52 * For transmission, the chip offers a series of four TX descriptor 53 * registers. Each transmit frame must be in a contiguous buffer, aligned 54 * on a longword (32-bit) boundary. This means we almost always have to 55 * do mbuf copies in order to transmit a frame, except in the unlikely 56 * case where a) the packet fits into a single mbuf, and b) the packet 57 * is 32-bit aligned within the mbuf's data area. The presence of only 58 * four descriptor registers means that we can never have more than four 59 * packets queued for transmission at any one time. 60 * 61 * Reception is not much better. The driver has to allocate a single large 62 * buffer area (up to 64K in size) into which the chip will DMA received 63 * frames. Because we don't know where within this region received packets 64 * will begin or end, we have no choice but to copy data from the buffer 65 * area into mbufs in order to pass the packets up to the higher protocol 66 * levels. 67 * 68 * It's impossible given this rotten design to really achieve decent 69 * performance at 100Mbps, unless you happen to have a 400Mhz PII or 70 * some equally overmuscled CPU to drive it. 71 * 72 * On the bright side, the 8139 does have a built-in PHY, although 73 * rather than using an MDIO serial interface like most other NICs, the 74 * PHY registers are directly accessible through the 8139's register 75 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 76 * filter. 77 * 78 * The 8129 chip is an older version of the 8139 that uses an external PHY 79 * chip. The 8129 has a serial MDIO interface for accessing the MII where 80 * the 8139 lets you directly access the on-board PHY registers. We need 81 * to select which interface to use depending on the chip type. 82 */ 83 84 #ifdef HAVE_KERNEL_OPTION_HEADERS 85 #include "opt_device_polling.h" 86 #endif 87 88 #include <sys/param.h> 89 #include <sys/endian.h> 90 #include <sys/systm.h> 91 #include <sys/sockio.h> 92 #include <sys/mbuf.h> 93 #include <sys/malloc.h> 94 #include <sys/kernel.h> 95 #include <sys/module.h> 96 #include <sys/socket.h> 97 #include <sys/sysctl.h> 98 99 #include <net/if.h> 100 #include <net/if_var.h> 101 #include <net/if_arp.h> 102 #include <net/ethernet.h> 103 #include <net/if_dl.h> 104 #include <net/if_media.h> 105 #include <net/if_types.h> 106 107 #include <net/bpf.h> 108 109 #include <machine/bus.h> 110 #include <machine/resource.h> 111 #include <sys/bus.h> 112 #include <sys/rman.h> 113 114 #include <dev/mii/mii.h> 115 #include <dev/mii/mii_bitbang.h> 116 #include <dev/mii/miivar.h> 117 118 #include <dev/pci/pcireg.h> 119 #include <dev/pci/pcivar.h> 120 121 MODULE_DEPEND(rl, pci, 1, 1, 1); 122 MODULE_DEPEND(rl, ether, 1, 1, 1); 123 MODULE_DEPEND(rl, miibus, 1, 1, 1); 124 125 /* "device miibus" required. See GENERIC if you get errors here. */ 126 #include "miibus_if.h" 127 128 #include <dev/rl/if_rlreg.h> 129 130 /* 131 * Various supported device vendors/types and their names. 132 */ 133 static const struct rl_type rl_devs[] = { 134 { RT_VENDORID, RT_DEVICEID_8129, RL_8129, 135 "RealTek 8129 10/100BaseTX" }, 136 { RT_VENDORID, RT_DEVICEID_8139, RL_8139, 137 "RealTek 8139 10/100BaseTX" }, 138 { RT_VENDORID, RT_DEVICEID_8139D, RL_8139, 139 "RealTek 8139 10/100BaseTX" }, 140 { RT_VENDORID, RT_DEVICEID_8138, RL_8139, 141 "RealTek 8139 10/100BaseTX CardBus" }, 142 { RT_VENDORID, RT_DEVICEID_8100, RL_8139, 143 "RealTek 8100 10/100BaseTX" }, 144 { ACCTON_VENDORID, ACCTON_DEVICEID_5030, RL_8139, 145 "Accton MPX 5030/5038 10/100BaseTX" }, 146 { DELTA_VENDORID, DELTA_DEVICEID_8139, RL_8139, 147 "Delta Electronics 8139 10/100BaseTX" }, 148 { ADDTRON_VENDORID, ADDTRON_DEVICEID_8139, RL_8139, 149 "Addtron Technology 8139 10/100BaseTX" }, 150 { DLINK_VENDORID, DLINK_DEVICEID_520TX_REVC1, RL_8139, 151 "D-Link DFE-520TX (rev. C1) 10/100BaseTX" }, 152 { DLINK_VENDORID, DLINK_DEVICEID_530TXPLUS, RL_8139, 153 "D-Link DFE-530TX+ 10/100BaseTX" }, 154 { DLINK_VENDORID, DLINK_DEVICEID_690TXD, RL_8139, 155 "D-Link DFE-690TXD 10/100BaseTX" }, 156 { NORTEL_VENDORID, ACCTON_DEVICEID_5030, RL_8139, 157 "Nortel Networks 10/100BaseTX" }, 158 { COREGA_VENDORID, COREGA_DEVICEID_FETHERCBTXD, RL_8139, 159 "Corega FEther CB-TXD" }, 160 { COREGA_VENDORID, COREGA_DEVICEID_FETHERIICBTXD, RL_8139, 161 "Corega FEtherII CB-TXD" }, 162 { PEPPERCON_VENDORID, PEPPERCON_DEVICEID_ROLF, RL_8139, 163 "Peppercon AG ROL-F" }, 164 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3603TX, RL_8139, 165 "Planex FNW-3603-TX" }, 166 { PLANEX_VENDORID, PLANEX_DEVICEID_FNW3800TX, RL_8139, 167 "Planex FNW-3800-TX" }, 168 { CP_VENDORID, RT_DEVICEID_8139, RL_8139, 169 "Compaq HNE-300" }, 170 { LEVEL1_VENDORID, LEVEL1_DEVICEID_FPC0106TX, RL_8139, 171 "LevelOne FPC-0106TX" }, 172 { EDIMAX_VENDORID, EDIMAX_DEVICEID_EP4103DL, RL_8139, 173 "Edimax EP-4103DL CardBus" } 174 }; 175 176 static int rl_attach(device_t); 177 static int rl_detach(device_t); 178 static void rl_dmamap_cb(void *, bus_dma_segment_t *, int, int); 179 static int rl_dma_alloc(struct rl_softc *); 180 static void rl_dma_free(struct rl_softc *); 181 static void rl_eeprom_putbyte(struct rl_softc *, int); 182 static void rl_eeprom_getword(struct rl_softc *, int, uint16_t *); 183 static int rl_encap(struct rl_softc *, struct mbuf **); 184 static int rl_list_tx_init(struct rl_softc *); 185 static int rl_list_rx_init(struct rl_softc *); 186 static int rl_ifmedia_upd(if_t); 187 static void rl_ifmedia_sts(if_t, struct ifmediareq *); 188 static int rl_ioctl(if_t, u_long, caddr_t); 189 static void rl_intr(void *); 190 static void rl_init(void *); 191 static void rl_init_locked(struct rl_softc *sc); 192 static int rl_miibus_readreg(device_t, int, int); 193 static void rl_miibus_statchg(device_t); 194 static int rl_miibus_writereg(device_t, int, int, int); 195 #ifdef DEVICE_POLLING 196 static int rl_poll(if_t ifp, enum poll_cmd cmd, int count); 197 static int rl_poll_locked(if_t ifp, enum poll_cmd cmd, int count); 198 #endif 199 static int rl_probe(device_t); 200 static void rl_read_eeprom(struct rl_softc *, uint8_t *, int, int, int); 201 static void rl_reset(struct rl_softc *); 202 static int rl_resume(device_t); 203 static int rl_rxeof(struct rl_softc *); 204 static void rl_rxfilter(struct rl_softc *); 205 static int rl_shutdown(device_t); 206 static void rl_start(if_t); 207 static void rl_start_locked(if_t); 208 static void rl_stop(struct rl_softc *); 209 static int rl_suspend(device_t); 210 static void rl_tick(void *); 211 static void rl_txeof(struct rl_softc *); 212 static void rl_watchdog(struct rl_softc *); 213 static void rl_setwol(struct rl_softc *); 214 static void rl_clrwol(struct rl_softc *); 215 216 /* 217 * MII bit-bang glue 218 */ 219 static uint32_t rl_mii_bitbang_read(device_t); 220 static void rl_mii_bitbang_write(device_t, uint32_t); 221 222 static const struct mii_bitbang_ops rl_mii_bitbang_ops = { 223 rl_mii_bitbang_read, 224 rl_mii_bitbang_write, 225 { 226 RL_MII_DATAOUT, /* MII_BIT_MDO */ 227 RL_MII_DATAIN, /* MII_BIT_MDI */ 228 RL_MII_CLK, /* MII_BIT_MDC */ 229 RL_MII_DIR, /* MII_BIT_DIR_HOST_PHY */ 230 0, /* MII_BIT_DIR_PHY_HOST */ 231 } 232 }; 233 234 static device_method_t rl_methods[] = { 235 /* Device interface */ 236 DEVMETHOD(device_probe, rl_probe), 237 DEVMETHOD(device_attach, rl_attach), 238 DEVMETHOD(device_detach, rl_detach), 239 DEVMETHOD(device_suspend, rl_suspend), 240 DEVMETHOD(device_resume, rl_resume), 241 DEVMETHOD(device_shutdown, rl_shutdown), 242 243 /* MII interface */ 244 DEVMETHOD(miibus_readreg, rl_miibus_readreg), 245 DEVMETHOD(miibus_writereg, rl_miibus_writereg), 246 DEVMETHOD(miibus_statchg, rl_miibus_statchg), 247 248 DEVMETHOD_END 249 }; 250 251 static driver_t rl_driver = { 252 "rl", 253 rl_methods, 254 sizeof(struct rl_softc) 255 }; 256 257 DRIVER_MODULE(rl, pci, rl_driver, 0, 0); 258 MODULE_PNP_INFO("U16:vendor;U16:device", pci, rl, rl_devs, 259 nitems(rl_devs) - 1); 260 DRIVER_MODULE(rl, cardbus, rl_driver, 0, 0); 261 DRIVER_MODULE(miibus, rl, miibus_driver, 0, 0); 262 263 #define EE_SET(x) \ 264 CSR_WRITE_1(sc, RL_EECMD, \ 265 CSR_READ_1(sc, RL_EECMD) | x) 266 267 #define EE_CLR(x) \ 268 CSR_WRITE_1(sc, RL_EECMD, \ 269 CSR_READ_1(sc, RL_EECMD) & ~x) 270 271 /* 272 * Send a read command and address to the EEPROM, check for ACK. 273 */ 274 static void 275 rl_eeprom_putbyte(struct rl_softc *sc, int addr) 276 { 277 int d, i; 278 279 d = addr | sc->rl_eecmd_read; 280 281 /* 282 * Feed in each bit and strobe the clock. 283 */ 284 for (i = 0x400; i; i >>= 1) { 285 if (d & i) { 286 EE_SET(RL_EE_DATAIN); 287 } else { 288 EE_CLR(RL_EE_DATAIN); 289 } 290 DELAY(100); 291 EE_SET(RL_EE_CLK); 292 DELAY(150); 293 EE_CLR(RL_EE_CLK); 294 DELAY(100); 295 } 296 } 297 298 /* 299 * Read a word of data stored in the EEPROM at address 'addr.' 300 */ 301 static void 302 rl_eeprom_getword(struct rl_softc *sc, int addr, uint16_t *dest) 303 { 304 int i; 305 uint16_t word = 0; 306 307 /* Enter EEPROM access mode. */ 308 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 309 310 /* 311 * Send address of word we want to read. 312 */ 313 rl_eeprom_putbyte(sc, addr); 314 315 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 316 317 /* 318 * Start reading bits from EEPROM. 319 */ 320 for (i = 0x8000; i; i >>= 1) { 321 EE_SET(RL_EE_CLK); 322 DELAY(100); 323 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 324 word |= i; 325 EE_CLR(RL_EE_CLK); 326 DELAY(100); 327 } 328 329 /* Turn off EEPROM access mode. */ 330 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 331 332 *dest = word; 333 } 334 335 /* 336 * Read a sequence of words from the EEPROM. 337 */ 338 static void 339 rl_read_eeprom(struct rl_softc *sc, uint8_t *dest, int off, int cnt, int swap) 340 { 341 int i; 342 uint16_t word = 0, *ptr; 343 344 for (i = 0; i < cnt; i++) { 345 rl_eeprom_getword(sc, off + i, &word); 346 ptr = (uint16_t *)(dest + (i * 2)); 347 if (swap) 348 *ptr = ntohs(word); 349 else 350 *ptr = word; 351 } 352 } 353 354 /* 355 * Read the MII serial port for the MII bit-bang module. 356 */ 357 static uint32_t 358 rl_mii_bitbang_read(device_t dev) 359 { 360 struct rl_softc *sc; 361 uint32_t val; 362 363 sc = device_get_softc(dev); 364 365 val = CSR_READ_1(sc, RL_MII); 366 CSR_BARRIER(sc, RL_MII, 1, 367 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 368 369 return (val); 370 } 371 372 /* 373 * Write the MII serial port for the MII bit-bang module. 374 */ 375 static void 376 rl_mii_bitbang_write(device_t dev, uint32_t val) 377 { 378 struct rl_softc *sc; 379 380 sc = device_get_softc(dev); 381 382 CSR_WRITE_1(sc, RL_MII, val); 383 CSR_BARRIER(sc, RL_MII, 1, 384 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 385 } 386 387 static int 388 rl_miibus_readreg(device_t dev, int phy, int reg) 389 { 390 struct rl_softc *sc; 391 uint16_t rl8139_reg; 392 393 sc = device_get_softc(dev); 394 395 if (sc->rl_type == RL_8139) { 396 switch (reg) { 397 case MII_BMCR: 398 rl8139_reg = RL_BMCR; 399 break; 400 case MII_BMSR: 401 rl8139_reg = RL_BMSR; 402 break; 403 case MII_ANAR: 404 rl8139_reg = RL_ANAR; 405 break; 406 case MII_ANER: 407 rl8139_reg = RL_ANER; 408 break; 409 case MII_ANLPAR: 410 rl8139_reg = RL_LPAR; 411 break; 412 case MII_PHYIDR1: 413 case MII_PHYIDR2: 414 return (0); 415 /* 416 * Allow the rlphy driver to read the media status 417 * register. If we have a link partner which does not 418 * support NWAY, this is the register which will tell 419 * us the results of parallel detection. 420 */ 421 case RL_MEDIASTAT: 422 return (CSR_READ_1(sc, RL_MEDIASTAT)); 423 default: 424 device_printf(sc->rl_dev, "bad phy register\n"); 425 return (0); 426 } 427 return (CSR_READ_2(sc, rl8139_reg)); 428 } 429 430 return (mii_bitbang_readreg(dev, &rl_mii_bitbang_ops, phy, reg)); 431 } 432 433 static int 434 rl_miibus_writereg(device_t dev, int phy, int reg, int data) 435 { 436 struct rl_softc *sc; 437 uint16_t rl8139_reg; 438 439 sc = device_get_softc(dev); 440 441 if (sc->rl_type == RL_8139) { 442 switch (reg) { 443 case MII_BMCR: 444 rl8139_reg = RL_BMCR; 445 break; 446 case MII_BMSR: 447 rl8139_reg = RL_BMSR; 448 break; 449 case MII_ANAR: 450 rl8139_reg = RL_ANAR; 451 break; 452 case MII_ANER: 453 rl8139_reg = RL_ANER; 454 break; 455 case MII_ANLPAR: 456 rl8139_reg = RL_LPAR; 457 break; 458 case MII_PHYIDR1: 459 case MII_PHYIDR2: 460 return (0); 461 break; 462 default: 463 device_printf(sc->rl_dev, "bad phy register\n"); 464 return (0); 465 } 466 CSR_WRITE_2(sc, rl8139_reg, data); 467 return (0); 468 } 469 470 mii_bitbang_writereg(dev, &rl_mii_bitbang_ops, phy, reg, data); 471 472 return (0); 473 } 474 475 static void 476 rl_miibus_statchg(device_t dev) 477 { 478 struct rl_softc *sc; 479 if_t ifp; 480 struct mii_data *mii; 481 482 sc = device_get_softc(dev); 483 mii = device_get_softc(sc->rl_miibus); 484 ifp = sc->rl_ifp; 485 if (mii == NULL || ifp == NULL || 486 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 487 return; 488 489 sc->rl_flags &= ~RL_FLAG_LINK; 490 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 491 (IFM_ACTIVE | IFM_AVALID)) { 492 switch (IFM_SUBTYPE(mii->mii_media_active)) { 493 case IFM_10_T: 494 case IFM_100_TX: 495 sc->rl_flags |= RL_FLAG_LINK; 496 break; 497 default: 498 break; 499 } 500 } 501 /* 502 * RealTek controllers do not provide any interface to 503 * Tx/Rx MACs for resolved speed, duplex and flow-control 504 * parameters. 505 */ 506 } 507 508 static u_int 509 rl_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 510 { 511 uint32_t *hashes = arg; 512 int h; 513 514 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26; 515 if (h < 32) 516 hashes[0] |= (1 << h); 517 else 518 hashes[1] |= (1 << (h - 32)); 519 520 return (1); 521 } 522 523 /* 524 * Program the 64-bit multicast hash filter. 525 */ 526 static void 527 rl_rxfilter(struct rl_softc *sc) 528 { 529 if_t ifp = sc->rl_ifp; 530 uint32_t hashes[2] = { 0, 0 }; 531 uint32_t rxfilt; 532 533 RL_LOCK_ASSERT(sc); 534 535 rxfilt = CSR_READ_4(sc, RL_RXCFG); 536 rxfilt &= ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_BROAD | 537 RL_RXCFG_RX_MULTI); 538 /* Always accept frames destined for this host. */ 539 rxfilt |= RL_RXCFG_RX_INDIV; 540 /* Set capture broadcast bit to capture broadcast frames. */ 541 if (if_getflags(ifp) & IFF_BROADCAST) 542 rxfilt |= RL_RXCFG_RX_BROAD; 543 if (if_getflags(ifp) & IFF_ALLMULTI || if_getflags(ifp) & IFF_PROMISC) { 544 rxfilt |= RL_RXCFG_RX_MULTI; 545 if (if_getflags(ifp) & IFF_PROMISC) 546 rxfilt |= RL_RXCFG_RX_ALLPHYS; 547 hashes[0] = 0xFFFFFFFF; 548 hashes[1] = 0xFFFFFFFF; 549 } else { 550 /* Now program new ones. */ 551 if_foreach_llmaddr(ifp, rl_hash_maddr, hashes); 552 if (hashes[0] != 0 || hashes[1] != 0) 553 rxfilt |= RL_RXCFG_RX_MULTI; 554 } 555 556 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 557 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 558 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 559 } 560 561 static void 562 rl_reset(struct rl_softc *sc) 563 { 564 int i; 565 566 RL_LOCK_ASSERT(sc); 567 568 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 569 570 for (i = 0; i < RL_TIMEOUT; i++) { 571 DELAY(10); 572 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 573 break; 574 } 575 if (i == RL_TIMEOUT) 576 device_printf(sc->rl_dev, "reset never completed!\n"); 577 } 578 579 /* 580 * Probe for a RealTek 8129/8139 chip. Check the PCI vendor and device 581 * IDs against our list and return a device name if we find a match. 582 */ 583 static int 584 rl_probe(device_t dev) 585 { 586 const struct rl_type *t; 587 uint16_t devid, revid, vendor; 588 int i; 589 590 vendor = pci_get_vendor(dev); 591 devid = pci_get_device(dev); 592 revid = pci_get_revid(dev); 593 594 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 595 if (revid == 0x20) { 596 /* 8139C+, let re(4) take care of this device. */ 597 return (ENXIO); 598 } 599 } 600 t = rl_devs; 601 for (i = 0; i < nitems(rl_devs); i++, t++) { 602 if (vendor == t->rl_vid && devid == t->rl_did) { 603 device_set_desc(dev, t->rl_name); 604 return (BUS_PROBE_DEFAULT); 605 } 606 } 607 608 return (ENXIO); 609 } 610 611 struct rl_dmamap_arg { 612 bus_addr_t rl_busaddr; 613 }; 614 615 static void 616 rl_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 617 { 618 struct rl_dmamap_arg *ctx; 619 620 if (error != 0) 621 return; 622 623 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 624 625 ctx = (struct rl_dmamap_arg *)arg; 626 ctx->rl_busaddr = segs[0].ds_addr; 627 } 628 629 /* 630 * Attach the interface. Allocate softc structures, do ifmedia 631 * setup and ethernet/BPF attach. 632 */ 633 static int 634 rl_attach(device_t dev) 635 { 636 uint8_t eaddr[ETHER_ADDR_LEN]; 637 uint16_t as[3]; 638 if_t ifp; 639 struct rl_softc *sc; 640 const struct rl_type *t; 641 struct sysctl_ctx_list *ctx; 642 struct sysctl_oid_list *children; 643 int error = 0, hwrev, i, phy, rid; 644 int prefer_iomap, unit; 645 uint16_t rl_did = 0; 646 char tn[32]; 647 648 sc = device_get_softc(dev); 649 unit = device_get_unit(dev); 650 sc->rl_dev = dev; 651 652 sc->rl_twister_enable = 0; 653 snprintf(tn, sizeof(tn), "dev.rl.%d.twister_enable", unit); 654 TUNABLE_INT_FETCH(tn, &sc->rl_twister_enable); 655 ctx = device_get_sysctl_ctx(sc->rl_dev); 656 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev)); 657 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "twister_enable", CTLFLAG_RD, 658 &sc->rl_twister_enable, 0, ""); 659 660 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 661 MTX_DEF); 662 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 663 664 pci_enable_busmaster(dev); 665 666 /* 667 * Map control/status registers. 668 * Default to using PIO access for this driver. On SMP systems, 669 * there appear to be problems with memory mapped mode: it looks 670 * like doing too many memory mapped access back to back in rapid 671 * succession can hang the bus. I'm inclined to blame this on 672 * crummy design/construction on the part of RealTek. Memory 673 * mapped mode does appear to work on uniprocessor systems though. 674 */ 675 prefer_iomap = 1; 676 snprintf(tn, sizeof(tn), "dev.rl.%d.prefer_iomap", unit); 677 TUNABLE_INT_FETCH(tn, &prefer_iomap); 678 if (prefer_iomap) { 679 sc->rl_res_id = PCIR_BAR(0); 680 sc->rl_res_type = SYS_RES_IOPORT; 681 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 682 &sc->rl_res_id, RF_ACTIVE); 683 } 684 if (prefer_iomap == 0 || sc->rl_res == NULL) { 685 sc->rl_res_id = PCIR_BAR(1); 686 sc->rl_res_type = SYS_RES_MEMORY; 687 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 688 &sc->rl_res_id, RF_ACTIVE); 689 } 690 if (sc->rl_res == NULL) { 691 device_printf(dev, "couldn't map ports/memory\n"); 692 error = ENXIO; 693 goto fail; 694 } 695 696 #ifdef notdef 697 /* 698 * Detect the Realtek 8139B. For some reason, this chip is very 699 * unstable when left to autoselect the media 700 * The best workaround is to set the device to the required 701 * media type or to set it to the 10 Meg speed. 702 */ 703 if ((rman_get_end(sc->rl_res) - rman_get_start(sc->rl_res)) == 0xFF) 704 device_printf(dev, 705 "Realtek 8139B detected. Warning, this may be unstable in autoselect mode\n"); 706 #endif 707 708 sc->rl_btag = rman_get_bustag(sc->rl_res); 709 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 710 711 /* Allocate interrupt */ 712 rid = 0; 713 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 714 RF_SHAREABLE | RF_ACTIVE); 715 716 if (sc->rl_irq[0] == NULL) { 717 device_printf(dev, "couldn't map interrupt\n"); 718 error = ENXIO; 719 goto fail; 720 } 721 722 sc->rl_cfg0 = RL_8139_CFG0; 723 sc->rl_cfg1 = RL_8139_CFG1; 724 sc->rl_cfg2 = 0; 725 sc->rl_cfg3 = RL_8139_CFG3; 726 sc->rl_cfg4 = RL_8139_CFG4; 727 sc->rl_cfg5 = RL_8139_CFG5; 728 729 /* 730 * Reset the adapter. Only take the lock here as it's needed in 731 * order to call rl_reset(). 732 */ 733 RL_LOCK(sc); 734 rl_reset(sc); 735 RL_UNLOCK(sc); 736 737 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 738 rl_read_eeprom(sc, (uint8_t *)&rl_did, 0, 1, 0); 739 if (rl_did != 0x8129) 740 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 741 742 /* 743 * Get station address from the EEPROM. 744 */ 745 rl_read_eeprom(sc, (uint8_t *)as, RL_EE_EADDR, 3, 0); 746 for (i = 0; i < 3; i++) { 747 eaddr[(i * 2) + 0] = as[i] & 0xff; 748 eaddr[(i * 2) + 1] = as[i] >> 8; 749 } 750 751 /* 752 * Now read the exact device type from the EEPROM to find 753 * out if it's an 8129 or 8139. 754 */ 755 rl_read_eeprom(sc, (uint8_t *)&rl_did, RL_EE_PCI_DID, 1, 0); 756 757 t = rl_devs; 758 sc->rl_type = 0; 759 while(t->rl_name != NULL) { 760 if (rl_did == t->rl_did) { 761 sc->rl_type = t->rl_basetype; 762 break; 763 } 764 t++; 765 } 766 767 if (sc->rl_type == 0) { 768 device_printf(dev, "unknown device ID: %x assuming 8139\n", 769 rl_did); 770 sc->rl_type = RL_8139; 771 /* 772 * Read RL_IDR register to get ethernet address as accessing 773 * EEPROM may not extract correct address. 774 */ 775 for (i = 0; i < ETHER_ADDR_LEN; i++) 776 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 777 } 778 779 if ((error = rl_dma_alloc(sc)) != 0) 780 goto fail; 781 782 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 783 784 #define RL_PHYAD_INTERNAL 0 785 786 /* Do MII setup */ 787 phy = MII_PHY_ANY; 788 if (sc->rl_type == RL_8139) 789 phy = RL_PHYAD_INTERNAL; 790 error = mii_attach(dev, &sc->rl_miibus, ifp, rl_ifmedia_upd, 791 rl_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0); 792 if (error != 0) { 793 device_printf(dev, "attaching PHYs failed\n"); 794 goto fail; 795 } 796 797 if_setsoftc(ifp, sc); 798 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 799 if_setmtu(ifp, ETHERMTU); 800 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 801 if_setioctlfn(ifp, rl_ioctl); 802 if_setstartfn(ifp, rl_start); 803 if_setinitfn(ifp, rl_init); 804 if_setcapabilities(ifp, IFCAP_VLAN_MTU); 805 /* Check WOL for RTL8139B or newer controllers. */ 806 if (sc->rl_type == RL_8139 && pci_has_pm(sc->rl_dev)) { 807 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 808 switch (hwrev) { 809 case RL_HWREV_8139B: 810 case RL_HWREV_8130: 811 case RL_HWREV_8139C: 812 case RL_HWREV_8139D: 813 case RL_HWREV_8101: 814 case RL_HWREV_8100: 815 if_setcapabilitiesbit(ifp, IFCAP_WOL, 0); 816 /* Disable WOL. */ 817 rl_clrwol(sc); 818 break; 819 default: 820 break; 821 } 822 } 823 if_setcapenable(ifp, if_getcapabilities(ifp)); 824 if_setcapenablebit(ifp, 0, (IFCAP_WOL_UCAST | IFCAP_WOL_MCAST)); 825 #ifdef DEVICE_POLLING 826 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0); 827 #endif 828 if_setsendqlen(ifp, ifqmaxlen); 829 if_setsendqready(ifp); 830 831 /* 832 * Call MI attach routine. 833 */ 834 ether_ifattach(ifp, eaddr); 835 836 /* Hook interrupt last to avoid having to lock softc */ 837 error = bus_setup_intr(dev, sc->rl_irq[0], INTR_TYPE_NET | INTR_MPSAFE, 838 NULL, rl_intr, sc, &sc->rl_intrhand[0]); 839 if (error) { 840 device_printf(sc->rl_dev, "couldn't set up irq\n"); 841 ether_ifdetach(ifp); 842 } 843 844 fail: 845 if (error) 846 rl_detach(dev); 847 848 return (error); 849 } 850 851 /* 852 * Shutdown hardware and free up resources. This can be called any 853 * time after the mutex has been initialized. It is called in both 854 * the error case in attach and the normal detach case so it needs 855 * to be careful about only freeing resources that have actually been 856 * allocated. 857 */ 858 static int 859 rl_detach(device_t dev) 860 { 861 struct rl_softc *sc; 862 if_t ifp; 863 864 sc = device_get_softc(dev); 865 ifp = sc->rl_ifp; 866 867 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized")); 868 869 #ifdef DEVICE_POLLING 870 if (if_getcapenable(ifp) & IFCAP_POLLING) 871 ether_poll_deregister(ifp); 872 #endif 873 /* These should only be active if attach succeeded */ 874 if (device_is_attached(dev)) { 875 RL_LOCK(sc); 876 rl_stop(sc); 877 RL_UNLOCK(sc); 878 callout_drain(&sc->rl_stat_callout); 879 ether_ifdetach(ifp); 880 } 881 #if 0 882 sc->suspended = 1; 883 #endif 884 bus_generic_detach(dev); 885 886 if (sc->rl_intrhand[0]) 887 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]); 888 if (sc->rl_irq[0]) 889 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq[0]); 890 if (sc->rl_res) 891 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, 892 sc->rl_res); 893 894 if (ifp) 895 if_free(ifp); 896 897 rl_dma_free(sc); 898 899 mtx_destroy(&sc->rl_mtx); 900 901 return (0); 902 } 903 904 static int 905 rl_dma_alloc(struct rl_softc *sc) 906 { 907 struct rl_dmamap_arg ctx; 908 int error, i; 909 910 /* 911 * Allocate the parent bus DMA tag appropriate for PCI. 912 */ 913 error = bus_dma_tag_create(bus_get_dma_tag(sc->rl_dev), /* parent */ 914 1, 0, /* alignment, boundary */ 915 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 916 BUS_SPACE_MAXADDR, /* highaddr */ 917 NULL, NULL, /* filter, filterarg */ 918 BUS_SPACE_MAXSIZE_32BIT, 0, /* maxsize, nsegments */ 919 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 920 0, /* flags */ 921 NULL, NULL, /* lockfunc, lockarg */ 922 &sc->rl_parent_tag); 923 if (error) { 924 device_printf(sc->rl_dev, 925 "failed to create parent DMA tag.\n"); 926 goto fail; 927 } 928 /* Create DMA tag for Rx memory block. */ 929 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ 930 RL_RX_8139_BUF_ALIGN, 0, /* alignment, boundary */ 931 BUS_SPACE_MAXADDR, /* lowaddr */ 932 BUS_SPACE_MAXADDR, /* highaddr */ 933 NULL, NULL, /* filter, filterarg */ 934 RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, 1, /* maxsize,nsegments */ 935 RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, /* maxsegsize */ 936 0, /* flags */ 937 NULL, NULL, /* lockfunc, lockarg */ 938 &sc->rl_cdata.rl_rx_tag); 939 if (error) { 940 device_printf(sc->rl_dev, 941 "failed to create Rx memory block DMA tag.\n"); 942 goto fail; 943 } 944 /* Create DMA tag for Tx buffer. */ 945 error = bus_dma_tag_create(sc->rl_parent_tag, /* parent */ 946 RL_TX_8139_BUF_ALIGN, 0, /* alignment, boundary */ 947 BUS_SPACE_MAXADDR, /* lowaddr */ 948 BUS_SPACE_MAXADDR, /* highaddr */ 949 NULL, NULL, /* filter, filterarg */ 950 MCLBYTES, 1, /* maxsize, nsegments */ 951 MCLBYTES, /* maxsegsize */ 952 0, /* flags */ 953 NULL, NULL, /* lockfunc, lockarg */ 954 &sc->rl_cdata.rl_tx_tag); 955 if (error) { 956 device_printf(sc->rl_dev, "failed to create Tx DMA tag.\n"); 957 goto fail; 958 } 959 960 /* 961 * Allocate DMA'able memory and load DMA map for Rx memory block. 962 */ 963 error = bus_dmamem_alloc(sc->rl_cdata.rl_rx_tag, 964 (void **)&sc->rl_cdata.rl_rx_buf, BUS_DMA_WAITOK | 965 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->rl_cdata.rl_rx_dmamap); 966 if (error != 0) { 967 device_printf(sc->rl_dev, 968 "failed to allocate Rx DMA memory block.\n"); 969 goto fail; 970 } 971 ctx.rl_busaddr = 0; 972 error = bus_dmamap_load(sc->rl_cdata.rl_rx_tag, 973 sc->rl_cdata.rl_rx_dmamap, sc->rl_cdata.rl_rx_buf, 974 RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ, rl_dmamap_cb, &ctx, 975 BUS_DMA_NOWAIT); 976 if (error != 0 || ctx.rl_busaddr == 0) { 977 device_printf(sc->rl_dev, 978 "could not load Rx DMA memory block.\n"); 979 goto fail; 980 } 981 sc->rl_cdata.rl_rx_buf_paddr = ctx.rl_busaddr; 982 983 /* Create DMA maps for Tx buffers. */ 984 for (i = 0; i < RL_TX_LIST_CNT; i++) { 985 sc->rl_cdata.rl_tx_chain[i] = NULL; 986 sc->rl_cdata.rl_tx_dmamap[i] = NULL; 987 error = bus_dmamap_create(sc->rl_cdata.rl_tx_tag, 0, 988 &sc->rl_cdata.rl_tx_dmamap[i]); 989 if (error != 0) { 990 device_printf(sc->rl_dev, 991 "could not create Tx dmamap.\n"); 992 goto fail; 993 } 994 } 995 996 /* Leave a few bytes before the start of the RX ring buffer. */ 997 sc->rl_cdata.rl_rx_buf_ptr = sc->rl_cdata.rl_rx_buf; 998 sc->rl_cdata.rl_rx_buf += RL_RX_8139_BUF_RESERVE; 999 1000 fail: 1001 return (error); 1002 } 1003 1004 static void 1005 rl_dma_free(struct rl_softc *sc) 1006 { 1007 int i; 1008 1009 /* Rx memory block. */ 1010 if (sc->rl_cdata.rl_rx_tag != NULL) { 1011 if (sc->rl_cdata.rl_rx_buf_paddr != 0) 1012 bus_dmamap_unload(sc->rl_cdata.rl_rx_tag, 1013 sc->rl_cdata.rl_rx_dmamap); 1014 if (sc->rl_cdata.rl_rx_buf_ptr != NULL) 1015 bus_dmamem_free(sc->rl_cdata.rl_rx_tag, 1016 sc->rl_cdata.rl_rx_buf_ptr, 1017 sc->rl_cdata.rl_rx_dmamap); 1018 sc->rl_cdata.rl_rx_buf_ptr = NULL; 1019 sc->rl_cdata.rl_rx_buf = NULL; 1020 sc->rl_cdata.rl_rx_buf_paddr = 0; 1021 bus_dma_tag_destroy(sc->rl_cdata.rl_rx_tag); 1022 sc->rl_cdata.rl_tx_tag = NULL; 1023 } 1024 1025 /* Tx buffers. */ 1026 if (sc->rl_cdata.rl_tx_tag != NULL) { 1027 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1028 if (sc->rl_cdata.rl_tx_dmamap[i] != NULL) { 1029 bus_dmamap_destroy( 1030 sc->rl_cdata.rl_tx_tag, 1031 sc->rl_cdata.rl_tx_dmamap[i]); 1032 sc->rl_cdata.rl_tx_dmamap[i] = NULL; 1033 } 1034 } 1035 bus_dma_tag_destroy(sc->rl_cdata.rl_tx_tag); 1036 sc->rl_cdata.rl_tx_tag = NULL; 1037 } 1038 1039 if (sc->rl_parent_tag != NULL) { 1040 bus_dma_tag_destroy(sc->rl_parent_tag); 1041 sc->rl_parent_tag = NULL; 1042 } 1043 } 1044 1045 /* 1046 * Initialize the transmit descriptors. 1047 */ 1048 static int 1049 rl_list_tx_init(struct rl_softc *sc) 1050 { 1051 struct rl_chain_data *cd; 1052 int i; 1053 1054 RL_LOCK_ASSERT(sc); 1055 1056 cd = &sc->rl_cdata; 1057 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1058 cd->rl_tx_chain[i] = NULL; 1059 CSR_WRITE_4(sc, 1060 RL_TXADDR0 + (i * sizeof(uint32_t)), 0x0000000); 1061 } 1062 1063 sc->rl_cdata.cur_tx = 0; 1064 sc->rl_cdata.last_tx = 0; 1065 1066 return (0); 1067 } 1068 1069 static int 1070 rl_list_rx_init(struct rl_softc *sc) 1071 { 1072 1073 RL_LOCK_ASSERT(sc); 1074 1075 bzero(sc->rl_cdata.rl_rx_buf_ptr, 1076 RL_RXBUFLEN + RL_RX_8139_BUF_GUARD_SZ); 1077 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, sc->rl_cdata.rl_rx_dmamap, 1078 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1079 1080 return (0); 1081 } 1082 1083 /* 1084 * A frame has been uploaded: pass the resulting mbuf chain up to 1085 * the higher level protocols. 1086 * 1087 * You know there's something wrong with a PCI bus-master chip design 1088 * when you have to use m_devget(). 1089 * 1090 * The receive operation is badly documented in the datasheet, so I'll 1091 * attempt to document it here. The driver provides a buffer area and 1092 * places its base address in the RX buffer start address register. 1093 * The chip then begins copying frames into the RX buffer. Each frame 1094 * is preceded by a 32-bit RX status word which specifies the length 1095 * of the frame and certain other status bits. Each frame (starting with 1096 * the status word) is also 32-bit aligned. The frame length is in the 1097 * first 16 bits of the status word; the lower 15 bits correspond with 1098 * the 'rx status register' mentioned in the datasheet. 1099 * 1100 * Note: to make the Alpha happy, the frame payload needs to be aligned 1101 * on a 32-bit boundary. To achieve this, we pass RL_ETHER_ALIGN (2 bytes) 1102 * as the offset argument to m_devget(). 1103 */ 1104 static int 1105 rl_rxeof(struct rl_softc *sc) 1106 { 1107 struct mbuf *m; 1108 if_t ifp = sc->rl_ifp; 1109 uint8_t *rxbufpos; 1110 int total_len = 0; 1111 int wrap = 0; 1112 int rx_npkts = 0; 1113 uint32_t rxstat; 1114 uint16_t cur_rx; 1115 uint16_t limit; 1116 uint16_t max_bytes, rx_bytes = 0; 1117 1118 RL_LOCK_ASSERT(sc); 1119 1120 bus_dmamap_sync(sc->rl_cdata.rl_rx_tag, sc->rl_cdata.rl_rx_dmamap, 1121 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1122 1123 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; 1124 1125 /* Do not try to read past this point. */ 1126 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; 1127 1128 if (limit < cur_rx) 1129 max_bytes = (RL_RXBUFLEN - cur_rx) + limit; 1130 else 1131 max_bytes = limit - cur_rx; 1132 1133 while((CSR_READ_1(sc, RL_COMMAND) & RL_CMD_EMPTY_RXBUF) == 0) { 1134 #ifdef DEVICE_POLLING 1135 if (if_getcapenable(ifp) & IFCAP_POLLING) { 1136 if (sc->rxcycles <= 0) 1137 break; 1138 sc->rxcycles--; 1139 } 1140 #endif 1141 rxbufpos = sc->rl_cdata.rl_rx_buf + cur_rx; 1142 rxstat = le32toh(*(uint32_t *)rxbufpos); 1143 1144 /* 1145 * Here's a totally undocumented fact for you. When the 1146 * RealTek chip is in the process of copying a packet into 1147 * RAM for you, the length will be 0xfff0. If you spot a 1148 * packet header with this value, you need to stop. The 1149 * datasheet makes absolutely no mention of this and 1150 * RealTek should be shot for this. 1151 */ 1152 total_len = rxstat >> 16; 1153 if (total_len == RL_RXSTAT_UNFINISHED) 1154 break; 1155 1156 if (!(rxstat & RL_RXSTAT_RXOK) || 1157 total_len < ETHER_MIN_LEN || 1158 total_len > ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) { 1159 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1160 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1161 rl_init_locked(sc); 1162 return (rx_npkts); 1163 } 1164 1165 /* No errors; receive the packet. */ 1166 rx_bytes += total_len + 4; 1167 1168 /* 1169 * XXX The RealTek chip includes the CRC with every 1170 * received frame, and there's no way to turn this 1171 * behavior off (at least, I can't find anything in 1172 * the manual that explains how to do it) so we have 1173 * to trim off the CRC manually. 1174 */ 1175 total_len -= ETHER_CRC_LEN; 1176 1177 /* 1178 * Avoid trying to read more bytes than we know 1179 * the chip has prepared for us. 1180 */ 1181 if (rx_bytes > max_bytes) 1182 break; 1183 1184 rxbufpos = sc->rl_cdata.rl_rx_buf + 1185 ((cur_rx + sizeof(uint32_t)) % RL_RXBUFLEN); 1186 if (rxbufpos == (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN)) 1187 rxbufpos = sc->rl_cdata.rl_rx_buf; 1188 1189 wrap = (sc->rl_cdata.rl_rx_buf + RL_RXBUFLEN) - rxbufpos; 1190 if (total_len > wrap) { 1191 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 1192 NULL); 1193 if (m != NULL) 1194 m_copyback(m, wrap, total_len - wrap, 1195 sc->rl_cdata.rl_rx_buf); 1196 cur_rx = (total_len - wrap + ETHER_CRC_LEN); 1197 } else { 1198 m = m_devget(rxbufpos, total_len, RL_ETHER_ALIGN, ifp, 1199 NULL); 1200 cur_rx += total_len + 4 + ETHER_CRC_LEN; 1201 } 1202 1203 /* Round up to 32-bit boundary. */ 1204 cur_rx = (cur_rx + 3) & ~3; 1205 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); 1206 1207 if (m == NULL) { 1208 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1209 continue; 1210 } 1211 1212 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1213 RL_UNLOCK(sc); 1214 if_input(ifp, m); 1215 RL_LOCK(sc); 1216 rx_npkts++; 1217 } 1218 1219 /* No need to sync Rx memory block as we didn't modify it. */ 1220 return (rx_npkts); 1221 } 1222 1223 /* 1224 * A frame was downloaded to the chip. It's safe for us to clean up 1225 * the list buffers. 1226 */ 1227 static void 1228 rl_txeof(struct rl_softc *sc) 1229 { 1230 if_t ifp = sc->rl_ifp; 1231 uint32_t txstat; 1232 1233 RL_LOCK_ASSERT(sc); 1234 1235 /* 1236 * Go through our tx list and free mbufs for those 1237 * frames that have been uploaded. 1238 */ 1239 do { 1240 if (RL_LAST_TXMBUF(sc) == NULL) 1241 break; 1242 txstat = CSR_READ_4(sc, RL_LAST_TXSTAT(sc)); 1243 if (!(txstat & (RL_TXSTAT_TX_OK| 1244 RL_TXSTAT_TX_UNDERRUN|RL_TXSTAT_TXABRT))) 1245 break; 1246 1247 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, (txstat & RL_TXSTAT_COLLCNT) >> 24); 1248 1249 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc), 1250 BUS_DMASYNC_POSTWRITE); 1251 bus_dmamap_unload(sc->rl_cdata.rl_tx_tag, RL_LAST_DMAMAP(sc)); 1252 m_freem(RL_LAST_TXMBUF(sc)); 1253 RL_LAST_TXMBUF(sc) = NULL; 1254 /* 1255 * If there was a transmit underrun, bump the TX threshold. 1256 * Make sure not to overflow the 63 * 32byte we can address 1257 * with the 6 available bit. 1258 */ 1259 if ((txstat & RL_TXSTAT_TX_UNDERRUN) && 1260 (sc->rl_txthresh < 2016)) 1261 sc->rl_txthresh += 32; 1262 if (txstat & RL_TXSTAT_TX_OK) 1263 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 1264 else { 1265 int oldthresh; 1266 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1267 if ((txstat & RL_TXSTAT_TXABRT) || 1268 (txstat & RL_TXSTAT_OUTOFWIN)) 1269 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1270 oldthresh = sc->rl_txthresh; 1271 /* error recovery */ 1272 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1273 rl_init_locked(sc); 1274 /* restore original threshold */ 1275 sc->rl_txthresh = oldthresh; 1276 return; 1277 } 1278 RL_INC(sc->rl_cdata.last_tx); 1279 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1280 } while (sc->rl_cdata.last_tx != sc->rl_cdata.cur_tx); 1281 1282 if (RL_LAST_TXMBUF(sc) == NULL) 1283 sc->rl_watchdog_timer = 0; 1284 } 1285 1286 static void 1287 rl_twister_update(struct rl_softc *sc) 1288 { 1289 uint16_t linktest; 1290 /* 1291 * Table provided by RealTek (Kinston <shangh@realtek.com.tw>) for 1292 * Linux driver. Values undocumented otherwise. 1293 */ 1294 static const uint32_t param[4][4] = { 1295 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43}, 1296 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83}, 1297 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83}, 1298 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83} 1299 }; 1300 1301 /* 1302 * Tune the so-called twister registers of the RTL8139. These 1303 * are used to compensate for impedance mismatches. The 1304 * method for tuning these registers is undocumented and the 1305 * following procedure is collected from public sources. 1306 */ 1307 switch (sc->rl_twister) 1308 { 1309 case CHK_LINK: 1310 /* 1311 * If we have a sufficient link, then we can proceed in 1312 * the state machine to the next stage. If not, then 1313 * disable further tuning after writing sane defaults. 1314 */ 1315 if (CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_LINK_OK) { 1316 CSR_WRITE_2(sc, RL_CSCFG, RL_CSCFG_LINK_DOWN_OFF_CMD); 1317 sc->rl_twister = FIND_ROW; 1318 } else { 1319 CSR_WRITE_2(sc, RL_CSCFG, RL_CSCFG_LINK_DOWN_CMD); 1320 CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_CBL_TEST); 1321 CSR_WRITE_4(sc, RL_PARA78, RL_PARA78_DEF); 1322 CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_DEF); 1323 sc->rl_twister = DONE; 1324 } 1325 break; 1326 case FIND_ROW: 1327 /* 1328 * Read how long it took to see the echo to find the tuning 1329 * row to use. 1330 */ 1331 linktest = CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_STATUS; 1332 if (linktest == RL_CSCFG_ROW3) 1333 sc->rl_twist_row = 3; 1334 else if (linktest == RL_CSCFG_ROW2) 1335 sc->rl_twist_row = 2; 1336 else if (linktest == RL_CSCFG_ROW1) 1337 sc->rl_twist_row = 1; 1338 else 1339 sc->rl_twist_row = 0; 1340 sc->rl_twist_col = 0; 1341 sc->rl_twister = SET_PARAM; 1342 break; 1343 case SET_PARAM: 1344 if (sc->rl_twist_col == 0) 1345 CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_RESET); 1346 CSR_WRITE_4(sc, RL_PARA7C, 1347 param[sc->rl_twist_row][sc->rl_twist_col]); 1348 if (++sc->rl_twist_col == 4) { 1349 if (sc->rl_twist_row == 3) 1350 sc->rl_twister = RECHK_LONG; 1351 else 1352 sc->rl_twister = DONE; 1353 } 1354 break; 1355 case RECHK_LONG: 1356 /* 1357 * For long cables, we have to double check to make sure we 1358 * don't mistune. 1359 */ 1360 linktest = CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_STATUS; 1361 if (linktest == RL_CSCFG_ROW3) 1362 sc->rl_twister = DONE; 1363 else { 1364 CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_RETUNE); 1365 sc->rl_twister = RETUNE; 1366 } 1367 break; 1368 case RETUNE: 1369 /* Retune for a shorter cable (try column 2) */ 1370 CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_CBL_TEST); 1371 CSR_WRITE_4(sc, RL_PARA78, RL_PARA78_DEF); 1372 CSR_WRITE_4(sc, RL_PARA7C, RL_PARA7C_DEF); 1373 CSR_WRITE_4(sc, RL_NWAYTST, RL_NWAYTST_RESET); 1374 sc->rl_twist_row--; 1375 sc->rl_twist_col = 0; 1376 sc->rl_twister = SET_PARAM; 1377 break; 1378 1379 case DONE: 1380 break; 1381 } 1382 1383 } 1384 1385 static void 1386 rl_tick(void *xsc) 1387 { 1388 struct rl_softc *sc = xsc; 1389 struct mii_data *mii; 1390 int ticks; 1391 1392 RL_LOCK_ASSERT(sc); 1393 /* 1394 * If we're doing the twister cable calibration, then we need to defer 1395 * watchdog timeouts. This is a no-op in normal operations, but 1396 * can falsely trigger when the cable calibration takes a while and 1397 * there was traffic ready to go when rl was started. 1398 * 1399 * We don't defer mii_tick since that updates the mii status, which 1400 * helps the twister process, at least according to similar patches 1401 * for the Linux driver I found online while doing the fixes. Worst 1402 * case is a few extra mii reads during calibration. 1403 */ 1404 mii = device_get_softc(sc->rl_miibus); 1405 mii_tick(mii); 1406 if ((sc->rl_flags & RL_FLAG_LINK) == 0) 1407 rl_miibus_statchg(sc->rl_dev); 1408 if (sc->rl_twister_enable) { 1409 if (sc->rl_twister == DONE) 1410 rl_watchdog(sc); 1411 else 1412 rl_twister_update(sc); 1413 if (sc->rl_twister == DONE) 1414 ticks = hz; 1415 else 1416 ticks = hz / 10; 1417 } else { 1418 rl_watchdog(sc); 1419 ticks = hz; 1420 } 1421 1422 callout_reset(&sc->rl_stat_callout, ticks, rl_tick, sc); 1423 } 1424 1425 #ifdef DEVICE_POLLING 1426 static int 1427 rl_poll(if_t ifp, enum poll_cmd cmd, int count) 1428 { 1429 struct rl_softc *sc = if_getsoftc(ifp); 1430 int rx_npkts = 0; 1431 1432 RL_LOCK(sc); 1433 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 1434 rx_npkts = rl_poll_locked(ifp, cmd, count); 1435 RL_UNLOCK(sc); 1436 return (rx_npkts); 1437 } 1438 1439 static int 1440 rl_poll_locked(if_t ifp, enum poll_cmd cmd, int count) 1441 { 1442 struct rl_softc *sc = if_getsoftc(ifp); 1443 int rx_npkts; 1444 1445 RL_LOCK_ASSERT(sc); 1446 1447 sc->rxcycles = count; 1448 rx_npkts = rl_rxeof(sc); 1449 rl_txeof(sc); 1450 1451 if (!if_sendq_empty(ifp)) 1452 rl_start_locked(ifp); 1453 1454 if (cmd == POLL_AND_CHECK_STATUS) { 1455 uint16_t status; 1456 1457 /* We should also check the status register. */ 1458 status = CSR_READ_2(sc, RL_ISR); 1459 if (status == 0xffff) 1460 return (rx_npkts); 1461 if (status != 0) 1462 CSR_WRITE_2(sc, RL_ISR, status); 1463 1464 /* XXX We should check behaviour on receiver stalls. */ 1465 1466 if (status & RL_ISR_SYSTEM_ERR) { 1467 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1468 rl_init_locked(sc); 1469 } 1470 } 1471 return (rx_npkts); 1472 } 1473 #endif /* DEVICE_POLLING */ 1474 1475 static void 1476 rl_intr(void *arg) 1477 { 1478 struct rl_softc *sc = arg; 1479 if_t ifp = sc->rl_ifp; 1480 uint16_t status; 1481 int count; 1482 1483 RL_LOCK(sc); 1484 1485 if (sc->suspended) 1486 goto done_locked; 1487 1488 #ifdef DEVICE_POLLING 1489 if (if_getcapenable(ifp) & IFCAP_POLLING) 1490 goto done_locked; 1491 #endif 1492 1493 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 1494 goto done_locked2; 1495 status = CSR_READ_2(sc, RL_ISR); 1496 if (status == 0xffff || (status & RL_INTRS) == 0) 1497 goto done_locked; 1498 /* 1499 * Ours, disable further interrupts. 1500 */ 1501 CSR_WRITE_2(sc, RL_IMR, 0); 1502 for (count = 16; count > 0; count--) { 1503 CSR_WRITE_2(sc, RL_ISR, status); 1504 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 1505 if (status & (RL_ISR_RX_OK | RL_ISR_RX_ERR)) 1506 rl_rxeof(sc); 1507 if (status & (RL_ISR_TX_OK | RL_ISR_TX_ERR)) 1508 rl_txeof(sc); 1509 if (status & RL_ISR_SYSTEM_ERR) { 1510 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1511 rl_init_locked(sc); 1512 RL_UNLOCK(sc); 1513 return; 1514 } 1515 } 1516 status = CSR_READ_2(sc, RL_ISR); 1517 /* If the card has gone away, the read returns 0xffff. */ 1518 if (status == 0xffff || (status & RL_INTRS) == 0) 1519 break; 1520 } 1521 1522 if (!if_sendq_empty(ifp)) 1523 rl_start_locked(ifp); 1524 1525 done_locked2: 1526 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 1527 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1528 done_locked: 1529 RL_UNLOCK(sc); 1530 } 1531 1532 /* 1533 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1534 * pointers to the fragment pointers. 1535 */ 1536 static int 1537 rl_encap(struct rl_softc *sc, struct mbuf **m_head) 1538 { 1539 struct mbuf *m; 1540 bus_dma_segment_t txsegs[1]; 1541 int error, nsegs, padlen; 1542 1543 RL_LOCK_ASSERT(sc); 1544 1545 m = *m_head; 1546 padlen = 0; 1547 /* 1548 * Hardware doesn't auto-pad, so we have to make sure 1549 * pad short frames out to the minimum frame length. 1550 */ 1551 if (m->m_pkthdr.len < RL_MIN_FRAMELEN) 1552 padlen = RL_MIN_FRAMELEN - m->m_pkthdr.len; 1553 /* 1554 * The RealTek is brain damaged and wants longword-aligned 1555 * TX buffers, plus we can only have one fragment buffer 1556 * per packet. We have to copy pretty much all the time. 1557 */ 1558 if (m->m_next != NULL || (mtod(m, uintptr_t) & 3) != 0 || 1559 (padlen > 0 && M_TRAILINGSPACE(m) < padlen)) { 1560 m = m_defrag(*m_head, M_NOWAIT); 1561 if (m == NULL) { 1562 m_freem(*m_head); 1563 *m_head = NULL; 1564 return (ENOMEM); 1565 } 1566 } 1567 *m_head = m; 1568 1569 if (padlen > 0) { 1570 /* 1571 * Make security-conscious people happy: zero out the 1572 * bytes in the pad area, since we don't know what 1573 * this mbuf cluster buffer's previous user might 1574 * have left in it. 1575 */ 1576 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); 1577 m->m_pkthdr.len += padlen; 1578 m->m_len = m->m_pkthdr.len; 1579 } 1580 1581 error = bus_dmamap_load_mbuf_sg(sc->rl_cdata.rl_tx_tag, 1582 RL_CUR_DMAMAP(sc), m, txsegs, &nsegs, 0); 1583 if (error != 0) 1584 return (error); 1585 if (nsegs == 0) { 1586 m_freem(*m_head); 1587 *m_head = NULL; 1588 return (EIO); 1589 } 1590 1591 RL_CUR_TXMBUF(sc) = m; 1592 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, RL_CUR_DMAMAP(sc), 1593 BUS_DMASYNC_PREWRITE); 1594 CSR_WRITE_4(sc, RL_CUR_TXADDR(sc), RL_ADDR_LO(txsegs[0].ds_addr)); 1595 1596 return (0); 1597 } 1598 1599 /* 1600 * Main transmit routine. 1601 */ 1602 static void 1603 rl_start(if_t ifp) 1604 { 1605 struct rl_softc *sc = if_getsoftc(ifp); 1606 1607 RL_LOCK(sc); 1608 rl_start_locked(ifp); 1609 RL_UNLOCK(sc); 1610 } 1611 1612 static void 1613 rl_start_locked(if_t ifp) 1614 { 1615 struct rl_softc *sc = if_getsoftc(ifp); 1616 struct mbuf *m_head = NULL; 1617 1618 RL_LOCK_ASSERT(sc); 1619 1620 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1621 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) 1622 return; 1623 1624 while (RL_CUR_TXMBUF(sc) == NULL) { 1625 m_head = if_dequeue(ifp); 1626 1627 if (m_head == NULL) 1628 break; 1629 1630 if (rl_encap(sc, &m_head)) { 1631 if (m_head == NULL) 1632 break; 1633 if_sendq_prepend(ifp, m_head); 1634 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1635 break; 1636 } 1637 1638 /* Pass a copy of this mbuf chain to the bpf subsystem. */ 1639 BPF_MTAP(ifp, RL_CUR_TXMBUF(sc)); 1640 1641 /* Transmit the frame. */ 1642 CSR_WRITE_4(sc, RL_CUR_TXSTAT(sc), 1643 RL_TXTHRESH(sc->rl_txthresh) | 1644 RL_CUR_TXMBUF(sc)->m_pkthdr.len); 1645 1646 RL_INC(sc->rl_cdata.cur_tx); 1647 1648 /* Set a timeout in case the chip goes out to lunch. */ 1649 sc->rl_watchdog_timer = 5; 1650 } 1651 1652 /* 1653 * We broke out of the loop because all our TX slots are 1654 * full. Mark the NIC as busy until it drains some of the 1655 * packets from the queue. 1656 */ 1657 if (RL_CUR_TXMBUF(sc) != NULL) 1658 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1659 } 1660 1661 static void 1662 rl_init(void *xsc) 1663 { 1664 struct rl_softc *sc = xsc; 1665 1666 RL_LOCK(sc); 1667 rl_init_locked(sc); 1668 RL_UNLOCK(sc); 1669 } 1670 1671 static void 1672 rl_init_locked(struct rl_softc *sc) 1673 { 1674 if_t ifp = sc->rl_ifp; 1675 struct mii_data *mii; 1676 uint32_t eaddr[2]; 1677 1678 RL_LOCK_ASSERT(sc); 1679 1680 mii = device_get_softc(sc->rl_miibus); 1681 1682 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1683 return; 1684 1685 /* 1686 * Cancel pending I/O and free all RX/TX buffers. 1687 */ 1688 rl_stop(sc); 1689 1690 rl_reset(sc); 1691 if (sc->rl_twister_enable) { 1692 /* 1693 * Reset twister register tuning state. The twister 1694 * registers and their tuning are undocumented, but 1695 * are necessary to cope with bad links. rl_twister = 1696 * DONE here will disable this entirely. 1697 */ 1698 sc->rl_twister = CHK_LINK; 1699 } 1700 1701 /* 1702 * Init our MAC address. Even though the chipset 1703 * documentation doesn't mention it, we need to enter "Config 1704 * register write enable" mode to modify the ID registers. 1705 */ 1706 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 1707 bzero(eaddr, sizeof(eaddr)); 1708 bcopy(if_getlladdr(sc->rl_ifp), eaddr, ETHER_ADDR_LEN); 1709 CSR_WRITE_STREAM_4(sc, RL_IDR0, eaddr[0]); 1710 CSR_WRITE_STREAM_4(sc, RL_IDR4, eaddr[1]); 1711 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1712 1713 /* Init the RX memory block pointer register. */ 1714 CSR_WRITE_4(sc, RL_RXADDR, sc->rl_cdata.rl_rx_buf_paddr + 1715 RL_RX_8139_BUF_RESERVE); 1716 /* Init TX descriptors. */ 1717 rl_list_tx_init(sc); 1718 /* Init Rx memory block. */ 1719 rl_list_rx_init(sc); 1720 1721 /* 1722 * Enable transmit and receive. 1723 */ 1724 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1725 1726 /* 1727 * Set the initial TX and RX configuration. 1728 */ 1729 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 1730 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 1731 1732 /* Set RX filter. */ 1733 rl_rxfilter(sc); 1734 1735 #ifdef DEVICE_POLLING 1736 /* Disable interrupts if we are polling. */ 1737 if (if_getcapenable(ifp) & IFCAP_POLLING) 1738 CSR_WRITE_2(sc, RL_IMR, 0); 1739 else 1740 #endif 1741 /* Enable interrupts. */ 1742 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1743 1744 /* Set initial TX threshold */ 1745 sc->rl_txthresh = RL_TX_THRESH_INIT; 1746 1747 /* Start RX/TX process. */ 1748 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 1749 1750 /* Enable receiver and transmitter. */ 1751 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 1752 1753 sc->rl_flags &= ~RL_FLAG_LINK; 1754 mii_mediachg(mii); 1755 1756 CSR_WRITE_1(sc, sc->rl_cfg1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 1757 1758 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 1759 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1760 1761 callout_reset(&sc->rl_stat_callout, hz, rl_tick, sc); 1762 } 1763 1764 /* 1765 * Set media options. 1766 */ 1767 static int 1768 rl_ifmedia_upd(if_t ifp) 1769 { 1770 struct rl_softc *sc = if_getsoftc(ifp); 1771 struct mii_data *mii; 1772 1773 mii = device_get_softc(sc->rl_miibus); 1774 1775 RL_LOCK(sc); 1776 mii_mediachg(mii); 1777 RL_UNLOCK(sc); 1778 1779 return (0); 1780 } 1781 1782 /* 1783 * Report current media status. 1784 */ 1785 static void 1786 rl_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 1787 { 1788 struct rl_softc *sc = if_getsoftc(ifp); 1789 struct mii_data *mii; 1790 1791 mii = device_get_softc(sc->rl_miibus); 1792 1793 RL_LOCK(sc); 1794 mii_pollstat(mii); 1795 ifmr->ifm_active = mii->mii_media_active; 1796 ifmr->ifm_status = mii->mii_media_status; 1797 RL_UNLOCK(sc); 1798 } 1799 1800 static int 1801 rl_ioctl(if_t ifp, u_long command, caddr_t data) 1802 { 1803 struct ifreq *ifr = (struct ifreq *)data; 1804 struct mii_data *mii; 1805 struct rl_softc *sc = if_getsoftc(ifp); 1806 int error = 0, mask; 1807 1808 switch (command) { 1809 case SIOCSIFFLAGS: 1810 RL_LOCK(sc); 1811 if (if_getflags(ifp) & IFF_UP) { 1812 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING && 1813 ((if_getflags(ifp) ^ sc->rl_if_flags) & 1814 (IFF_PROMISC | IFF_ALLMULTI))) 1815 rl_rxfilter(sc); 1816 else 1817 rl_init_locked(sc); 1818 } else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 1819 rl_stop(sc); 1820 sc->rl_if_flags = if_getflags(ifp); 1821 RL_UNLOCK(sc); 1822 break; 1823 case SIOCADDMULTI: 1824 case SIOCDELMULTI: 1825 RL_LOCK(sc); 1826 rl_rxfilter(sc); 1827 RL_UNLOCK(sc); 1828 break; 1829 case SIOCGIFMEDIA: 1830 case SIOCSIFMEDIA: 1831 mii = device_get_softc(sc->rl_miibus); 1832 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1833 break; 1834 case SIOCSIFCAP: 1835 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 1836 #ifdef DEVICE_POLLING 1837 if (ifr->ifr_reqcap & IFCAP_POLLING && 1838 !(if_getcapenable(ifp) & IFCAP_POLLING)) { 1839 error = ether_poll_register(rl_poll, ifp); 1840 if (error) 1841 return(error); 1842 RL_LOCK(sc); 1843 /* Disable interrupts */ 1844 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1845 if_setcapenablebit(ifp, IFCAP_POLLING, 0); 1846 RL_UNLOCK(sc); 1847 return (error); 1848 1849 } 1850 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 1851 if_getcapenable(ifp) & IFCAP_POLLING) { 1852 error = ether_poll_deregister(ifp); 1853 /* Enable interrupts. */ 1854 RL_LOCK(sc); 1855 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); 1856 if_setcapenablebit(ifp, 0, IFCAP_POLLING); 1857 RL_UNLOCK(sc); 1858 return (error); 1859 } 1860 #endif /* DEVICE_POLLING */ 1861 if ((mask & IFCAP_WOL) != 0 && 1862 (if_getcapabilities(ifp) & IFCAP_WOL) != 0) { 1863 if ((mask & IFCAP_WOL_UCAST) != 0) 1864 if_togglecapenable(ifp, IFCAP_WOL_UCAST); 1865 if ((mask & IFCAP_WOL_MCAST) != 0) 1866 if_togglecapenable(ifp, IFCAP_WOL_MCAST); 1867 if ((mask & IFCAP_WOL_MAGIC) != 0) 1868 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 1869 } 1870 break; 1871 default: 1872 error = ether_ioctl(ifp, command, data); 1873 break; 1874 } 1875 1876 return (error); 1877 } 1878 1879 static void 1880 rl_watchdog(struct rl_softc *sc) 1881 { 1882 1883 RL_LOCK_ASSERT(sc); 1884 1885 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer >0) 1886 return; 1887 1888 device_printf(sc->rl_dev, "watchdog timeout\n"); 1889 if_inc_counter(sc->rl_ifp, IFCOUNTER_OERRORS, 1); 1890 1891 rl_txeof(sc); 1892 rl_rxeof(sc); 1893 if_setdrvflagbits(sc->rl_ifp, 0, IFF_DRV_RUNNING); 1894 rl_init_locked(sc); 1895 } 1896 1897 /* 1898 * Stop the adapter and free any mbufs allocated to the 1899 * RX and TX lists. 1900 */ 1901 static void 1902 rl_stop(struct rl_softc *sc) 1903 { 1904 int i; 1905 if_t ifp = sc->rl_ifp; 1906 1907 RL_LOCK_ASSERT(sc); 1908 1909 sc->rl_watchdog_timer = 0; 1910 callout_stop(&sc->rl_stat_callout); 1911 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 1912 sc->rl_flags &= ~RL_FLAG_LINK; 1913 1914 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 1915 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1916 for (i = 0; i < RL_TIMEOUT; i++) { 1917 DELAY(10); 1918 if ((CSR_READ_1(sc, RL_COMMAND) & 1919 (RL_CMD_RX_ENB | RL_CMD_TX_ENB)) == 0) 1920 break; 1921 } 1922 if (i == RL_TIMEOUT) 1923 device_printf(sc->rl_dev, "Unable to stop Tx/Rx MAC\n"); 1924 1925 /* 1926 * Free the TX list buffers. 1927 */ 1928 for (i = 0; i < RL_TX_LIST_CNT; i++) { 1929 if (sc->rl_cdata.rl_tx_chain[i] != NULL) { 1930 bus_dmamap_sync(sc->rl_cdata.rl_tx_tag, 1931 sc->rl_cdata.rl_tx_dmamap[i], 1932 BUS_DMASYNC_POSTWRITE); 1933 bus_dmamap_unload(sc->rl_cdata.rl_tx_tag, 1934 sc->rl_cdata.rl_tx_dmamap[i]); 1935 m_freem(sc->rl_cdata.rl_tx_chain[i]); 1936 sc->rl_cdata.rl_tx_chain[i] = NULL; 1937 CSR_WRITE_4(sc, RL_TXADDR0 + (i * sizeof(uint32_t)), 1938 0x0000000); 1939 } 1940 } 1941 } 1942 1943 /* 1944 * Device suspend routine. Stop the interface and save some PCI 1945 * settings in case the BIOS doesn't restore them properly on 1946 * resume. 1947 */ 1948 static int 1949 rl_suspend(device_t dev) 1950 { 1951 struct rl_softc *sc; 1952 1953 sc = device_get_softc(dev); 1954 1955 RL_LOCK(sc); 1956 rl_stop(sc); 1957 rl_setwol(sc); 1958 sc->suspended = 1; 1959 RL_UNLOCK(sc); 1960 1961 return (0); 1962 } 1963 1964 /* 1965 * Device resume routine. Restore some PCI settings in case the BIOS 1966 * doesn't, re-enable busmastering, and restart the interface if 1967 * appropriate. 1968 */ 1969 static int 1970 rl_resume(device_t dev) 1971 { 1972 struct rl_softc *sc; 1973 if_t ifp; 1974 1975 sc = device_get_softc(dev); 1976 ifp = sc->rl_ifp; 1977 1978 RL_LOCK(sc); 1979 1980 if ((if_getcapabilities(ifp) & IFCAP_WOL) != 0) { 1981 /* 1982 * Clear WOL matching such that normal Rx filtering 1983 * wouldn't interfere with WOL patterns. 1984 */ 1985 rl_clrwol(sc); 1986 } 1987 1988 /* reinitialize interface if necessary */ 1989 if (if_getflags(ifp) & IFF_UP) 1990 rl_init_locked(sc); 1991 1992 sc->suspended = 0; 1993 1994 RL_UNLOCK(sc); 1995 1996 return (0); 1997 } 1998 1999 /* 2000 * Stop all chip I/O so that the kernel's probe routines don't 2001 * get confused by errant DMAs when rebooting. 2002 */ 2003 static int 2004 rl_shutdown(device_t dev) 2005 { 2006 struct rl_softc *sc; 2007 2008 sc = device_get_softc(dev); 2009 2010 RL_LOCK(sc); 2011 rl_stop(sc); 2012 /* 2013 * Mark interface as down since otherwise we will panic if 2014 * interrupt comes in later on, which can happen in some 2015 * cases. 2016 */ 2017 if_setflagbits(sc->rl_ifp, 0, IFF_UP); 2018 rl_setwol(sc); 2019 RL_UNLOCK(sc); 2020 2021 return (0); 2022 } 2023 2024 static void 2025 rl_setwol(struct rl_softc *sc) 2026 { 2027 if_t ifp; 2028 uint8_t v; 2029 2030 RL_LOCK_ASSERT(sc); 2031 2032 ifp = sc->rl_ifp; 2033 if ((if_getcapabilities(ifp) & IFCAP_WOL) == 0) 2034 return; 2035 2036 /* Enable config register write. */ 2037 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 2038 2039 /* Enable PME. */ 2040 v = CSR_READ_1(sc, sc->rl_cfg1); 2041 v &= ~RL_CFG1_PME; 2042 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 2043 v |= RL_CFG1_PME; 2044 CSR_WRITE_1(sc, sc->rl_cfg1, v); 2045 2046 v = CSR_READ_1(sc, sc->rl_cfg3); 2047 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 2048 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 2049 v |= RL_CFG3_WOL_MAGIC; 2050 CSR_WRITE_1(sc, sc->rl_cfg3, v); 2051 2052 v = CSR_READ_1(sc, sc->rl_cfg5); 2053 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 2054 v &= ~RL_CFG5_WOL_LANWAKE; 2055 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) != 0) 2056 v |= RL_CFG5_WOL_UCAST; 2057 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0) 2058 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 2059 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 2060 v |= RL_CFG5_WOL_LANWAKE; 2061 CSR_WRITE_1(sc, sc->rl_cfg5, v); 2062 2063 /* Config register write done. */ 2064 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2065 2066 /* Request PME if WOL is requested. */ 2067 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 2068 pci_enable_pme(sc->rl_dev); 2069 } 2070 2071 static void 2072 rl_clrwol(struct rl_softc *sc) 2073 { 2074 if_t ifp; 2075 uint8_t v; 2076 2077 ifp = sc->rl_ifp; 2078 if ((if_getcapabilities(ifp) & IFCAP_WOL) == 0) 2079 return; 2080 2081 /* Enable config register write. */ 2082 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 2083 2084 v = CSR_READ_1(sc, sc->rl_cfg3); 2085 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 2086 CSR_WRITE_1(sc, sc->rl_cfg3, v); 2087 2088 /* Config register write done. */ 2089 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2090 2091 v = CSR_READ_1(sc, sc->rl_cfg5); 2092 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 2093 v &= ~RL_CFG5_WOL_LANWAKE; 2094 CSR_WRITE_1(sc, sc->rl_cfg5, v); 2095 } 2096