1 /*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44 /* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111 #ifdef HAVE_KERNEL_OPTION_HEADERS 112 #include "opt_device_polling.h" 113 #endif 114 115 #include <sys/param.h> 116 #include <sys/endian.h> 117 #include <sys/systm.h> 118 #include <sys/sockio.h> 119 #include <sys/mbuf.h> 120 #include <sys/malloc.h> 121 #include <sys/module.h> 122 #include <sys/kernel.h> 123 #include <sys/socket.h> 124 #include <sys/lock.h> 125 #include <sys/mutex.h> 126 #include <sys/sysctl.h> 127 #include <sys/taskqueue.h> 128 129 #include <net/if.h> 130 #include <net/if_var.h> 131 #include <net/if_arp.h> 132 #include <net/ethernet.h> 133 #include <net/if_dl.h> 134 #include <net/if_media.h> 135 #include <net/if_types.h> 136 #include <net/if_vlan_var.h> 137 138 #include <net/bpf.h> 139 140 #include <machine/bus.h> 141 #include <machine/resource.h> 142 #include <sys/bus.h> 143 #include <sys/rman.h> 144 145 #include <dev/mii/mii.h> 146 #include <dev/mii/miivar.h> 147 148 #include <dev/pci/pcireg.h> 149 #include <dev/pci/pcivar.h> 150 151 #include <dev/rl/if_rlreg.h> 152 153 MODULE_DEPEND(re, pci, 1, 1, 1); 154 MODULE_DEPEND(re, ether, 1, 1, 1); 155 MODULE_DEPEND(re, miibus, 1, 1, 1); 156 157 /* "device miibus" required. See GENERIC if you get errors here. */ 158 #include "miibus_if.h" 159 160 /* Tunables. */ 161 static int intr_filter = 0; 162 TUNABLE_INT("hw.re.intr_filter", &intr_filter); 163 static int msi_disable = 0; 164 TUNABLE_INT("hw.re.msi_disable", &msi_disable); 165 static int msix_disable = 0; 166 TUNABLE_INT("hw.re.msix_disable", &msix_disable); 167 static int prefer_iomap = 0; 168 TUNABLE_INT("hw.re.prefer_iomap", &prefer_iomap); 169 170 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 171 172 /* 173 * Various supported device vendors/types and their names. 174 */ 175 static const struct rl_type re_devs[] = { 176 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0, 177 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 178 { DLINK_VENDORID, DLINK_DEVICEID_530T_REVC, 0, 179 "D-Link DGE-530(T) Gigabit Ethernet Adapter" }, 180 { RT_VENDORID, RT_DEVICEID_8139, 0, 181 "RealTek 8139C+ 10/100BaseTX" }, 182 { RT_VENDORID, RT_DEVICEID_8101E, 0, 183 "RealTek 810xE PCIe 10/100baseTX" }, 184 { RT_VENDORID, RT_DEVICEID_8168, 0, 185 "RealTek 8168/8111 B/C/CP/D/DP/E/F/G PCIe Gigabit Ethernet" }, 186 { RT_VENDORID, RT_DEVICEID_8169, 0, 187 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" }, 188 { RT_VENDORID, RT_DEVICEID_8169SC, 0, 189 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 190 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0, 191 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 192 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0, 193 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 194 { USR_VENDORID, USR_DEVICEID_997902, 0, 195 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 196 }; 197 198 static const struct rl_hwrev re_hwrevs[] = { 199 { RL_HWREV_8139, RL_8139, "", RL_MTU }, 200 { RL_HWREV_8139A, RL_8139, "A", RL_MTU }, 201 { RL_HWREV_8139AG, RL_8139, "A-G", RL_MTU }, 202 { RL_HWREV_8139B, RL_8139, "B", RL_MTU }, 203 { RL_HWREV_8130, RL_8139, "8130", RL_MTU }, 204 { RL_HWREV_8139C, RL_8139, "C", RL_MTU }, 205 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C", RL_MTU }, 206 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+", RL_MTU }, 207 { RL_HWREV_8168B_SPIN1, RL_8169, "8168", RL_JUMBO_MTU }, 208 { RL_HWREV_8169, RL_8169, "8169", RL_JUMBO_MTU }, 209 { RL_HWREV_8169S, RL_8169, "8169S", RL_JUMBO_MTU }, 210 { RL_HWREV_8110S, RL_8169, "8110S", RL_JUMBO_MTU }, 211 { RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB", RL_JUMBO_MTU }, 212 { RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU }, 213 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL", RL_JUMBO_MTU }, 214 { RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU }, 215 { RL_HWREV_8100, RL_8139, "8100", RL_MTU }, 216 { RL_HWREV_8101, RL_8139, "8101", RL_MTU }, 217 { RL_HWREV_8100E, RL_8169, "8100E", RL_MTU }, 218 { RL_HWREV_8101E, RL_8169, "8101E", RL_MTU }, 219 { RL_HWREV_8102E, RL_8169, "8102E", RL_MTU }, 220 { RL_HWREV_8102EL, RL_8169, "8102EL", RL_MTU }, 221 { RL_HWREV_8102EL_SPIN1, RL_8169, "8102EL", RL_MTU }, 222 { RL_HWREV_8103E, RL_8169, "8103E", RL_MTU }, 223 { RL_HWREV_8401E, RL_8169, "8401E", RL_MTU }, 224 { RL_HWREV_8402, RL_8169, "8402", RL_MTU }, 225 { RL_HWREV_8105E, RL_8169, "8105E", RL_MTU }, 226 { RL_HWREV_8105E_SPIN1, RL_8169, "8105E", RL_MTU }, 227 { RL_HWREV_8106E, RL_8169, "8106E", RL_MTU }, 228 { RL_HWREV_8168B_SPIN2, RL_8169, "8168", RL_JUMBO_MTU }, 229 { RL_HWREV_8168B_SPIN3, RL_8169, "8168", RL_JUMBO_MTU }, 230 { RL_HWREV_8168C, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K }, 231 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K }, 232 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP", RL_JUMBO_MTU_6K }, 233 { RL_HWREV_8168D, RL_8169, "8168D/8111D", RL_JUMBO_MTU_9K }, 234 { RL_HWREV_8168DP, RL_8169, "8168DP/8111DP", RL_JUMBO_MTU_9K }, 235 { RL_HWREV_8168E, RL_8169, "8168E/8111E", RL_JUMBO_MTU_9K}, 236 { RL_HWREV_8168E_VL, RL_8169, "8168E/8111E-VL", RL_JUMBO_MTU_6K}, 237 { RL_HWREV_8168EP, RL_8169, "8168EP/8111EP", RL_JUMBO_MTU_9K}, 238 { RL_HWREV_8168F, RL_8169, "8168F/8111F", RL_JUMBO_MTU_9K}, 239 { RL_HWREV_8168G, RL_8169, "8168G/8111G", RL_JUMBO_MTU_9K}, 240 { RL_HWREV_8168GU, RL_8169, "8168GU/8111GU", RL_JUMBO_MTU_9K}, 241 { RL_HWREV_8411, RL_8169, "8411", RL_JUMBO_MTU_9K}, 242 { RL_HWREV_8411B, RL_8169, "8411B", RL_JUMBO_MTU_9K}, 243 { 0, 0, NULL, 0 } 244 }; 245 246 static int re_probe (device_t); 247 static int re_attach (device_t); 248 static int re_detach (device_t); 249 250 static int re_encap (struct rl_softc *, struct mbuf **); 251 252 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 253 static int re_allocmem (device_t, struct rl_softc *); 254 static __inline void re_discard_rxbuf 255 (struct rl_softc *, int); 256 static int re_newbuf (struct rl_softc *, int); 257 static int re_jumbo_newbuf (struct rl_softc *, int); 258 static int re_rx_list_init (struct rl_softc *); 259 static int re_jrx_list_init (struct rl_softc *); 260 static int re_tx_list_init (struct rl_softc *); 261 #ifdef RE_FIXUP_RX 262 static __inline void re_fixup_rx 263 (struct mbuf *); 264 #endif 265 static int re_rxeof (struct rl_softc *, int *); 266 static void re_txeof (struct rl_softc *); 267 #ifdef DEVICE_POLLING 268 static int re_poll (struct ifnet *, enum poll_cmd, int); 269 static int re_poll_locked (struct ifnet *, enum poll_cmd, int); 270 #endif 271 static int re_intr (void *); 272 static void re_intr_msi (void *); 273 static void re_tick (void *); 274 static void re_int_task (void *, int); 275 static void re_start (struct ifnet *); 276 static void re_start_locked (struct ifnet *); 277 static int re_ioctl (struct ifnet *, u_long, caddr_t); 278 static void re_init (void *); 279 static void re_init_locked (struct rl_softc *); 280 static void re_stop (struct rl_softc *); 281 static void re_watchdog (struct rl_softc *); 282 static int re_suspend (device_t); 283 static int re_resume (device_t); 284 static int re_shutdown (device_t); 285 static int re_ifmedia_upd (struct ifnet *); 286 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 287 288 static void re_eeprom_putbyte (struct rl_softc *, int); 289 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 290 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 291 static int re_gmii_readreg (device_t, int, int); 292 static int re_gmii_writereg (device_t, int, int, int); 293 294 static int re_miibus_readreg (device_t, int, int); 295 static int re_miibus_writereg (device_t, int, int, int); 296 static void re_miibus_statchg (device_t); 297 298 static void re_set_jumbo (struct rl_softc *, int); 299 static void re_set_rxmode (struct rl_softc *); 300 static void re_reset (struct rl_softc *); 301 static void re_setwol (struct rl_softc *); 302 static void re_clrwol (struct rl_softc *); 303 static void re_set_linkspeed (struct rl_softc *); 304 305 #ifdef DEV_NETMAP /* see ixgbe.c for details */ 306 #include <dev/netmap/if_re_netmap.h> 307 MODULE_DEPEND(re, netmap, 1, 1, 1); 308 #endif /* !DEV_NETMAP */ 309 310 #ifdef RE_DIAG 311 static int re_diag (struct rl_softc *); 312 #endif 313 314 static void re_add_sysctls (struct rl_softc *); 315 static int re_sysctl_stats (SYSCTL_HANDLER_ARGS); 316 static int sysctl_int_range (SYSCTL_HANDLER_ARGS, int, int); 317 static int sysctl_hw_re_int_mod (SYSCTL_HANDLER_ARGS); 318 319 static device_method_t re_methods[] = { 320 /* Device interface */ 321 DEVMETHOD(device_probe, re_probe), 322 DEVMETHOD(device_attach, re_attach), 323 DEVMETHOD(device_detach, re_detach), 324 DEVMETHOD(device_suspend, re_suspend), 325 DEVMETHOD(device_resume, re_resume), 326 DEVMETHOD(device_shutdown, re_shutdown), 327 328 /* MII interface */ 329 DEVMETHOD(miibus_readreg, re_miibus_readreg), 330 DEVMETHOD(miibus_writereg, re_miibus_writereg), 331 DEVMETHOD(miibus_statchg, re_miibus_statchg), 332 333 DEVMETHOD_END 334 }; 335 336 static driver_t re_driver = { 337 "re", 338 re_methods, 339 sizeof(struct rl_softc) 340 }; 341 342 static devclass_t re_devclass; 343 344 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 345 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 346 347 #define EE_SET(x) \ 348 CSR_WRITE_1(sc, RL_EECMD, \ 349 CSR_READ_1(sc, RL_EECMD) | x) 350 351 #define EE_CLR(x) \ 352 CSR_WRITE_1(sc, RL_EECMD, \ 353 CSR_READ_1(sc, RL_EECMD) & ~x) 354 355 /* 356 * Send a read command and address to the EEPROM, check for ACK. 357 */ 358 static void 359 re_eeprom_putbyte(struct rl_softc *sc, int addr) 360 { 361 int d, i; 362 363 d = addr | (RL_9346_READ << sc->rl_eewidth); 364 365 /* 366 * Feed in each bit and strobe the clock. 367 */ 368 369 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 370 if (d & i) { 371 EE_SET(RL_EE_DATAIN); 372 } else { 373 EE_CLR(RL_EE_DATAIN); 374 } 375 DELAY(100); 376 EE_SET(RL_EE_CLK); 377 DELAY(150); 378 EE_CLR(RL_EE_CLK); 379 DELAY(100); 380 } 381 } 382 383 /* 384 * Read a word of data stored in the EEPROM at address 'addr.' 385 */ 386 static void 387 re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest) 388 { 389 int i; 390 u_int16_t word = 0; 391 392 /* 393 * Send address of word we want to read. 394 */ 395 re_eeprom_putbyte(sc, addr); 396 397 /* 398 * Start reading bits from EEPROM. 399 */ 400 for (i = 0x8000; i; i >>= 1) { 401 EE_SET(RL_EE_CLK); 402 DELAY(100); 403 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 404 word |= i; 405 EE_CLR(RL_EE_CLK); 406 DELAY(100); 407 } 408 409 *dest = word; 410 } 411 412 /* 413 * Read a sequence of words from the EEPROM. 414 */ 415 static void 416 re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt) 417 { 418 int i; 419 u_int16_t word = 0, *ptr; 420 421 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 422 423 DELAY(100); 424 425 for (i = 0; i < cnt; i++) { 426 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 427 re_eeprom_getword(sc, off + i, &word); 428 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 429 ptr = (u_int16_t *)(dest + (i * 2)); 430 *ptr = word; 431 } 432 433 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 434 } 435 436 static int 437 re_gmii_readreg(device_t dev, int phy, int reg) 438 { 439 struct rl_softc *sc; 440 u_int32_t rval; 441 int i; 442 443 sc = device_get_softc(dev); 444 445 /* Let the rgephy driver read the GMEDIASTAT register */ 446 447 if (reg == RL_GMEDIASTAT) { 448 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 449 return (rval); 450 } 451 452 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 453 454 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 455 rval = CSR_READ_4(sc, RL_PHYAR); 456 if (rval & RL_PHYAR_BUSY) 457 break; 458 DELAY(25); 459 } 460 461 if (i == RL_PHY_TIMEOUT) { 462 device_printf(sc->rl_dev, "PHY read failed\n"); 463 return (0); 464 } 465 466 /* 467 * Controller requires a 20us delay to process next MDIO request. 468 */ 469 DELAY(20); 470 471 return (rval & RL_PHYAR_PHYDATA); 472 } 473 474 static int 475 re_gmii_writereg(device_t dev, int phy, int reg, int data) 476 { 477 struct rl_softc *sc; 478 u_int32_t rval; 479 int i; 480 481 sc = device_get_softc(dev); 482 483 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 484 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 485 486 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 487 rval = CSR_READ_4(sc, RL_PHYAR); 488 if (!(rval & RL_PHYAR_BUSY)) 489 break; 490 DELAY(25); 491 } 492 493 if (i == RL_PHY_TIMEOUT) { 494 device_printf(sc->rl_dev, "PHY write failed\n"); 495 return (0); 496 } 497 498 /* 499 * Controller requires a 20us delay to process next MDIO request. 500 */ 501 DELAY(20); 502 503 return (0); 504 } 505 506 static int 507 re_miibus_readreg(device_t dev, int phy, int reg) 508 { 509 struct rl_softc *sc; 510 u_int16_t rval = 0; 511 u_int16_t re8139_reg = 0; 512 513 sc = device_get_softc(dev); 514 515 if (sc->rl_type == RL_8169) { 516 rval = re_gmii_readreg(dev, phy, reg); 517 return (rval); 518 } 519 520 switch (reg) { 521 case MII_BMCR: 522 re8139_reg = RL_BMCR; 523 break; 524 case MII_BMSR: 525 re8139_reg = RL_BMSR; 526 break; 527 case MII_ANAR: 528 re8139_reg = RL_ANAR; 529 break; 530 case MII_ANER: 531 re8139_reg = RL_ANER; 532 break; 533 case MII_ANLPAR: 534 re8139_reg = RL_LPAR; 535 break; 536 case MII_PHYIDR1: 537 case MII_PHYIDR2: 538 return (0); 539 /* 540 * Allow the rlphy driver to read the media status 541 * register. If we have a link partner which does not 542 * support NWAY, this is the register which will tell 543 * us the results of parallel detection. 544 */ 545 case RL_MEDIASTAT: 546 rval = CSR_READ_1(sc, RL_MEDIASTAT); 547 return (rval); 548 default: 549 device_printf(sc->rl_dev, "bad phy register\n"); 550 return (0); 551 } 552 rval = CSR_READ_2(sc, re8139_reg); 553 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 554 /* 8139C+ has different bit layout. */ 555 rval &= ~(BMCR_LOOP | BMCR_ISO); 556 } 557 return (rval); 558 } 559 560 static int 561 re_miibus_writereg(device_t dev, int phy, int reg, int data) 562 { 563 struct rl_softc *sc; 564 u_int16_t re8139_reg = 0; 565 int rval = 0; 566 567 sc = device_get_softc(dev); 568 569 if (sc->rl_type == RL_8169) { 570 rval = re_gmii_writereg(dev, phy, reg, data); 571 return (rval); 572 } 573 574 switch (reg) { 575 case MII_BMCR: 576 re8139_reg = RL_BMCR; 577 if (sc->rl_type == RL_8139CPLUS) { 578 /* 8139C+ has different bit layout. */ 579 data &= ~(BMCR_LOOP | BMCR_ISO); 580 } 581 break; 582 case MII_BMSR: 583 re8139_reg = RL_BMSR; 584 break; 585 case MII_ANAR: 586 re8139_reg = RL_ANAR; 587 break; 588 case MII_ANER: 589 re8139_reg = RL_ANER; 590 break; 591 case MII_ANLPAR: 592 re8139_reg = RL_LPAR; 593 break; 594 case MII_PHYIDR1: 595 case MII_PHYIDR2: 596 return (0); 597 break; 598 default: 599 device_printf(sc->rl_dev, "bad phy register\n"); 600 return (0); 601 } 602 CSR_WRITE_2(sc, re8139_reg, data); 603 return (0); 604 } 605 606 static void 607 re_miibus_statchg(device_t dev) 608 { 609 struct rl_softc *sc; 610 struct ifnet *ifp; 611 struct mii_data *mii; 612 613 sc = device_get_softc(dev); 614 mii = device_get_softc(sc->rl_miibus); 615 ifp = sc->rl_ifp; 616 if (mii == NULL || ifp == NULL || 617 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 618 return; 619 620 sc->rl_flags &= ~RL_FLAG_LINK; 621 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 622 (IFM_ACTIVE | IFM_AVALID)) { 623 switch (IFM_SUBTYPE(mii->mii_media_active)) { 624 case IFM_10_T: 625 case IFM_100_TX: 626 sc->rl_flags |= RL_FLAG_LINK; 627 break; 628 case IFM_1000_T: 629 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0) 630 break; 631 sc->rl_flags |= RL_FLAG_LINK; 632 break; 633 default: 634 break; 635 } 636 } 637 /* 638 * RealTek controllers does not provide any interface to 639 * Tx/Rx MACs for resolved speed, duplex and flow-control 640 * parameters. 641 */ 642 } 643 644 /* 645 * Set the RX configuration and 64-bit multicast hash filter. 646 */ 647 static void 648 re_set_rxmode(struct rl_softc *sc) 649 { 650 struct ifnet *ifp; 651 struct ifmultiaddr *ifma; 652 uint32_t hashes[2] = { 0, 0 }; 653 uint32_t h, rxfilt; 654 655 RL_LOCK_ASSERT(sc); 656 657 ifp = sc->rl_ifp; 658 659 rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD; 660 if ((sc->rl_flags & RL_FLAG_EARLYOFF) != 0) 661 rxfilt |= RL_RXCFG_EARLYOFF; 662 else if ((sc->rl_flags & RL_FLAG_EARLYOFFV2) != 0) 663 rxfilt |= RL_RXCFG_EARLYOFFV2; 664 665 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 666 if (ifp->if_flags & IFF_PROMISC) 667 rxfilt |= RL_RXCFG_RX_ALLPHYS; 668 /* 669 * Unlike other hardwares, we have to explicitly set 670 * RL_RXCFG_RX_MULTI to receive multicast frames in 671 * promiscuous mode. 672 */ 673 rxfilt |= RL_RXCFG_RX_MULTI; 674 hashes[0] = hashes[1] = 0xffffffff; 675 goto done; 676 } 677 678 if_maddr_rlock(ifp); 679 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 680 if (ifma->ifma_addr->sa_family != AF_LINK) 681 continue; 682 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 683 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 684 if (h < 32) 685 hashes[0] |= (1 << h); 686 else 687 hashes[1] |= (1 << (h - 32)); 688 } 689 if_maddr_runlock(ifp); 690 691 if (hashes[0] != 0 || hashes[1] != 0) { 692 /* 693 * For some unfathomable reason, RealTek decided to 694 * reverse the order of the multicast hash registers 695 * in the PCI Express parts. This means we have to 696 * write the hash pattern in reverse order for those 697 * devices. 698 */ 699 if ((sc->rl_flags & RL_FLAG_PCIE) != 0) { 700 h = bswap32(hashes[0]); 701 hashes[0] = bswap32(hashes[1]); 702 hashes[1] = h; 703 } 704 rxfilt |= RL_RXCFG_RX_MULTI; 705 } 706 707 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168F) { 708 /* Disable multicast filtering due to silicon bug. */ 709 hashes[0] = 0xffffffff; 710 hashes[1] = 0xffffffff; 711 } 712 713 done: 714 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 715 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 716 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 717 } 718 719 static void 720 re_reset(struct rl_softc *sc) 721 { 722 int i; 723 724 RL_LOCK_ASSERT(sc); 725 726 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 727 728 for (i = 0; i < RL_TIMEOUT; i++) { 729 DELAY(10); 730 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 731 break; 732 } 733 if (i == RL_TIMEOUT) 734 device_printf(sc->rl_dev, "reset never completed!\n"); 735 736 if ((sc->rl_flags & RL_FLAG_MACRESET) != 0) 737 CSR_WRITE_1(sc, 0x82, 1); 738 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169S) 739 re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0); 740 } 741 742 #ifdef RE_DIAG 743 744 /* 745 * The following routine is designed to test for a defect on some 746 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 747 * lines connected to the bus, however for a 32-bit only card, they 748 * should be pulled high. The result of this defect is that the 749 * NIC will not work right if you plug it into a 64-bit slot: DMA 750 * operations will be done with 64-bit transfers, which will fail 751 * because the 64-bit data lines aren't connected. 752 * 753 * There's no way to work around this (short of talking a soldering 754 * iron to the board), however we can detect it. The method we use 755 * here is to put the NIC into digital loopback mode, set the receiver 756 * to promiscuous mode, and then try to send a frame. We then compare 757 * the frame data we sent to what was received. If the data matches, 758 * then the NIC is working correctly, otherwise we know the user has 759 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 760 * slot. In the latter case, there's no way the NIC can work correctly, 761 * so we print out a message on the console and abort the device attach. 762 */ 763 764 static int 765 re_diag(struct rl_softc *sc) 766 { 767 struct ifnet *ifp = sc->rl_ifp; 768 struct mbuf *m0; 769 struct ether_header *eh; 770 struct rl_desc *cur_rx; 771 u_int16_t status; 772 u_int32_t rxstat; 773 int total_len, i, error = 0, phyaddr; 774 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 775 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 776 777 /* Allocate a single mbuf */ 778 MGETHDR(m0, M_NOWAIT, MT_DATA); 779 if (m0 == NULL) 780 return (ENOBUFS); 781 782 RL_LOCK(sc); 783 784 /* 785 * Initialize the NIC in test mode. This sets the chip up 786 * so that it can send and receive frames, but performs the 787 * following special functions: 788 * - Puts receiver in promiscuous mode 789 * - Enables digital loopback mode 790 * - Leaves interrupts turned off 791 */ 792 793 ifp->if_flags |= IFF_PROMISC; 794 sc->rl_testmode = 1; 795 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 796 re_init_locked(sc); 797 sc->rl_flags |= RL_FLAG_LINK; 798 if (sc->rl_type == RL_8169) 799 phyaddr = 1; 800 else 801 phyaddr = 0; 802 803 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 804 for (i = 0; i < RL_TIMEOUT; i++) { 805 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 806 if (!(status & BMCR_RESET)) 807 break; 808 } 809 810 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 811 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 812 813 DELAY(100000); 814 815 /* Put some data in the mbuf */ 816 817 eh = mtod(m0, struct ether_header *); 818 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 819 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 820 eh->ether_type = htons(ETHERTYPE_IP); 821 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 822 823 /* 824 * Queue the packet, start transmission. 825 * Note: IF_HANDOFF() ultimately calls re_start() for us. 826 */ 827 828 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 829 RL_UNLOCK(sc); 830 /* XXX: re_diag must not be called when in ALTQ mode */ 831 IF_HANDOFF(&ifp->if_snd, m0, ifp); 832 RL_LOCK(sc); 833 m0 = NULL; 834 835 /* Wait for it to propagate through the chip */ 836 837 DELAY(100000); 838 for (i = 0; i < RL_TIMEOUT; i++) { 839 status = CSR_READ_2(sc, RL_ISR); 840 CSR_WRITE_2(sc, RL_ISR, status); 841 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 842 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 843 break; 844 DELAY(10); 845 } 846 847 if (i == RL_TIMEOUT) { 848 device_printf(sc->rl_dev, 849 "diagnostic failed, failed to receive packet in" 850 " loopback mode\n"); 851 error = EIO; 852 goto done; 853 } 854 855 /* 856 * The packet should have been dumped into the first 857 * entry in the RX DMA ring. Grab it from there. 858 */ 859 860 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 861 sc->rl_ldata.rl_rx_list_map, 862 BUS_DMASYNC_POSTREAD); 863 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 864 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 865 BUS_DMASYNC_POSTREAD); 866 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 867 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 868 869 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 870 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 871 eh = mtod(m0, struct ether_header *); 872 873 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 874 total_len = RL_RXBYTES(cur_rx); 875 rxstat = le32toh(cur_rx->rl_cmdstat); 876 877 if (total_len != ETHER_MIN_LEN) { 878 device_printf(sc->rl_dev, 879 "diagnostic failed, received short packet\n"); 880 error = EIO; 881 goto done; 882 } 883 884 /* Test that the received packet data matches what we sent. */ 885 886 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 887 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 888 ntohs(eh->ether_type) != ETHERTYPE_IP) { 889 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 890 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 891 dst, ":", src, ":", ETHERTYPE_IP); 892 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 893 eh->ether_dhost, ":", eh->ether_shost, ":", 894 ntohs(eh->ether_type)); 895 device_printf(sc->rl_dev, "You may have a defective 32-bit " 896 "NIC plugged into a 64-bit PCI slot.\n"); 897 device_printf(sc->rl_dev, "Please re-install the NIC in a " 898 "32-bit slot for proper operation.\n"); 899 device_printf(sc->rl_dev, "Read the re(4) man page for more " 900 "details.\n"); 901 error = EIO; 902 } 903 904 done: 905 /* Turn interface off, release resources */ 906 907 sc->rl_testmode = 0; 908 sc->rl_flags &= ~RL_FLAG_LINK; 909 ifp->if_flags &= ~IFF_PROMISC; 910 re_stop(sc); 911 if (m0 != NULL) 912 m_freem(m0); 913 914 RL_UNLOCK(sc); 915 916 return (error); 917 } 918 919 #endif 920 921 /* 922 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 923 * IDs against our list and return a device name if we find a match. 924 */ 925 static int 926 re_probe(device_t dev) 927 { 928 const struct rl_type *t; 929 uint16_t devid, vendor; 930 uint16_t revid, sdevid; 931 int i; 932 933 vendor = pci_get_vendor(dev); 934 devid = pci_get_device(dev); 935 revid = pci_get_revid(dev); 936 sdevid = pci_get_subdevice(dev); 937 938 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 939 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 940 /* 941 * Only attach to rev. 3 of the Linksys EG1032 adapter. 942 * Rev. 2 is supported by sk(4). 943 */ 944 return (ENXIO); 945 } 946 } 947 948 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 949 if (revid != 0x20) { 950 /* 8139, let rl(4) take care of this device. */ 951 return (ENXIO); 952 } 953 } 954 955 t = re_devs; 956 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) { 957 if (vendor == t->rl_vid && devid == t->rl_did) { 958 device_set_desc(dev, t->rl_name); 959 return (BUS_PROBE_DEFAULT); 960 } 961 } 962 963 return (ENXIO); 964 } 965 966 /* 967 * Map a single buffer address. 968 */ 969 970 static void 971 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 972 { 973 bus_addr_t *addr; 974 975 if (error) 976 return; 977 978 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 979 addr = arg; 980 *addr = segs->ds_addr; 981 } 982 983 static int 984 re_allocmem(device_t dev, struct rl_softc *sc) 985 { 986 bus_addr_t lowaddr; 987 bus_size_t rx_list_size, tx_list_size; 988 int error; 989 int i; 990 991 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 992 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 993 994 /* 995 * Allocate the parent bus DMA tag appropriate for PCI. 996 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD 997 * register should be set. However some RealTek chips are known 998 * to be buggy on DAC handling, therefore disable DAC by limiting 999 * DMA address space to 32bit. PCIe variants of RealTek chips 1000 * may not have the limitation. 1001 */ 1002 lowaddr = BUS_SPACE_MAXADDR; 1003 if ((sc->rl_flags & RL_FLAG_PCIE) == 0) 1004 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1005 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 1006 lowaddr, BUS_SPACE_MAXADDR, NULL, NULL, 1007 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 1008 NULL, NULL, &sc->rl_parent_tag); 1009 if (error) { 1010 device_printf(dev, "could not allocate parent DMA tag\n"); 1011 return (error); 1012 } 1013 1014 /* 1015 * Allocate map for TX mbufs. 1016 */ 1017 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 1018 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1019 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 1020 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 1021 if (error) { 1022 device_printf(dev, "could not allocate TX DMA tag\n"); 1023 return (error); 1024 } 1025 1026 /* 1027 * Allocate map for RX mbufs. 1028 */ 1029 1030 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 1031 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 1032 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1033 MJUM9BYTES, 1, MJUM9BYTES, 0, NULL, NULL, 1034 &sc->rl_ldata.rl_jrx_mtag); 1035 if (error) { 1036 device_printf(dev, 1037 "could not allocate jumbo RX DMA tag\n"); 1038 return (error); 1039 } 1040 } 1041 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 1042 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1043 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 1044 if (error) { 1045 device_printf(dev, "could not allocate RX DMA tag\n"); 1046 return (error); 1047 } 1048 1049 /* 1050 * Allocate map for TX descriptor list. 1051 */ 1052 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1053 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1054 NULL, tx_list_size, 1, tx_list_size, 0, 1055 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1056 if (error) { 1057 device_printf(dev, "could not allocate TX DMA ring tag\n"); 1058 return (error); 1059 } 1060 1061 /* Allocate DMA'able memory for the TX ring */ 1062 1063 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1064 (void **)&sc->rl_ldata.rl_tx_list, 1065 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1066 &sc->rl_ldata.rl_tx_list_map); 1067 if (error) { 1068 device_printf(dev, "could not allocate TX DMA ring\n"); 1069 return (error); 1070 } 1071 1072 /* Load the map for the TX ring. */ 1073 1074 sc->rl_ldata.rl_tx_list_addr = 0; 1075 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1076 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1077 tx_list_size, re_dma_map_addr, 1078 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1079 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 1080 device_printf(dev, "could not load TX DMA ring\n"); 1081 return (ENOMEM); 1082 } 1083 1084 /* Create DMA maps for TX buffers */ 1085 1086 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1087 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1088 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1089 if (error) { 1090 device_printf(dev, "could not create DMA map for TX\n"); 1091 return (error); 1092 } 1093 } 1094 1095 /* 1096 * Allocate map for RX descriptor list. 1097 */ 1098 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1099 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1100 NULL, rx_list_size, 1, rx_list_size, 0, 1101 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1102 if (error) { 1103 device_printf(dev, "could not create RX DMA ring tag\n"); 1104 return (error); 1105 } 1106 1107 /* Allocate DMA'able memory for the RX ring */ 1108 1109 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1110 (void **)&sc->rl_ldata.rl_rx_list, 1111 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1112 &sc->rl_ldata.rl_rx_list_map); 1113 if (error) { 1114 device_printf(dev, "could not allocate RX DMA ring\n"); 1115 return (error); 1116 } 1117 1118 /* Load the map for the RX ring. */ 1119 1120 sc->rl_ldata.rl_rx_list_addr = 0; 1121 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1122 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1123 rx_list_size, re_dma_map_addr, 1124 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1125 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1126 device_printf(dev, "could not load RX DMA ring\n"); 1127 return (ENOMEM); 1128 } 1129 1130 /* Create DMA maps for RX buffers */ 1131 1132 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 1133 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0, 1134 &sc->rl_ldata.rl_jrx_sparemap); 1135 if (error) { 1136 device_printf(dev, 1137 "could not create spare DMA map for jumbo RX\n"); 1138 return (error); 1139 } 1140 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1141 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0, 1142 &sc->rl_ldata.rl_jrx_desc[i].rx_dmamap); 1143 if (error) { 1144 device_printf(dev, 1145 "could not create DMA map for jumbo RX\n"); 1146 return (error); 1147 } 1148 } 1149 } 1150 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1151 &sc->rl_ldata.rl_rx_sparemap); 1152 if (error) { 1153 device_printf(dev, "could not create spare DMA map for RX\n"); 1154 return (error); 1155 } 1156 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1157 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1158 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1159 if (error) { 1160 device_printf(dev, "could not create DMA map for RX\n"); 1161 return (error); 1162 } 1163 } 1164 1165 /* Create DMA map for statistics. */ 1166 error = bus_dma_tag_create(sc->rl_parent_tag, RL_DUMP_ALIGN, 0, 1167 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1168 sizeof(struct rl_stats), 1, sizeof(struct rl_stats), 0, NULL, NULL, 1169 &sc->rl_ldata.rl_stag); 1170 if (error) { 1171 device_printf(dev, "could not create statistics DMA tag\n"); 1172 return (error); 1173 } 1174 /* Allocate DMA'able memory for statistics. */ 1175 error = bus_dmamem_alloc(sc->rl_ldata.rl_stag, 1176 (void **)&sc->rl_ldata.rl_stats, 1177 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1178 &sc->rl_ldata.rl_smap); 1179 if (error) { 1180 device_printf(dev, 1181 "could not allocate statistics DMA memory\n"); 1182 return (error); 1183 } 1184 /* Load the map for statistics. */ 1185 sc->rl_ldata.rl_stats_addr = 0; 1186 error = bus_dmamap_load(sc->rl_ldata.rl_stag, sc->rl_ldata.rl_smap, 1187 sc->rl_ldata.rl_stats, sizeof(struct rl_stats), re_dma_map_addr, 1188 &sc->rl_ldata.rl_stats_addr, BUS_DMA_NOWAIT); 1189 if (error != 0 || sc->rl_ldata.rl_stats_addr == 0) { 1190 device_printf(dev, "could not load statistics DMA memory\n"); 1191 return (ENOMEM); 1192 } 1193 1194 return (0); 1195 } 1196 1197 /* 1198 * Attach the interface. Allocate softc structures, do ifmedia 1199 * setup and ethernet/BPF attach. 1200 */ 1201 static int 1202 re_attach(device_t dev) 1203 { 1204 u_char eaddr[ETHER_ADDR_LEN]; 1205 u_int16_t as[ETHER_ADDR_LEN / 2]; 1206 struct rl_softc *sc; 1207 struct ifnet *ifp; 1208 const struct rl_hwrev *hw_rev; 1209 u_int32_t cap, ctl; 1210 int hwrev; 1211 u_int16_t devid, re_did = 0; 1212 int error = 0, i, phy, rid; 1213 int msic, msixc, reg; 1214 uint8_t cfg; 1215 1216 sc = device_get_softc(dev); 1217 sc->rl_dev = dev; 1218 1219 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1220 MTX_DEF); 1221 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1222 1223 /* 1224 * Map control/status registers. 1225 */ 1226 pci_enable_busmaster(dev); 1227 1228 devid = pci_get_device(dev); 1229 /* 1230 * Prefer memory space register mapping over IO space. 1231 * Because RTL8169SC does not seem to work when memory mapping 1232 * is used always activate io mapping. 1233 */ 1234 if (devid == RT_DEVICEID_8169SC) 1235 prefer_iomap = 1; 1236 if (prefer_iomap == 0) { 1237 sc->rl_res_id = PCIR_BAR(1); 1238 sc->rl_res_type = SYS_RES_MEMORY; 1239 /* RTL8168/8101E seems to use different BARs. */ 1240 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E) 1241 sc->rl_res_id = PCIR_BAR(2); 1242 } else { 1243 sc->rl_res_id = PCIR_BAR(0); 1244 sc->rl_res_type = SYS_RES_IOPORT; 1245 } 1246 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1247 &sc->rl_res_id, RF_ACTIVE); 1248 if (sc->rl_res == NULL && prefer_iomap == 0) { 1249 sc->rl_res_id = PCIR_BAR(0); 1250 sc->rl_res_type = SYS_RES_IOPORT; 1251 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1252 &sc->rl_res_id, RF_ACTIVE); 1253 } 1254 if (sc->rl_res == NULL) { 1255 device_printf(dev, "couldn't map ports/memory\n"); 1256 error = ENXIO; 1257 goto fail; 1258 } 1259 1260 sc->rl_btag = rman_get_bustag(sc->rl_res); 1261 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1262 1263 msic = pci_msi_count(dev); 1264 msixc = pci_msix_count(dev); 1265 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 1266 sc->rl_flags |= RL_FLAG_PCIE; 1267 sc->rl_expcap = reg; 1268 } 1269 if (bootverbose) { 1270 device_printf(dev, "MSI count : %d\n", msic); 1271 device_printf(dev, "MSI-X count : %d\n", msixc); 1272 } 1273 if (msix_disable > 0) 1274 msixc = 0; 1275 if (msi_disable > 0) 1276 msic = 0; 1277 /* Prefer MSI-X to MSI. */ 1278 if (msixc > 0) { 1279 msixc = RL_MSI_MESSAGES; 1280 rid = PCIR_BAR(4); 1281 sc->rl_res_pba = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1282 &rid, RF_ACTIVE); 1283 if (sc->rl_res_pba == NULL) { 1284 device_printf(sc->rl_dev, 1285 "could not allocate MSI-X PBA resource\n"); 1286 } 1287 if (sc->rl_res_pba != NULL && 1288 pci_alloc_msix(dev, &msixc) == 0) { 1289 if (msixc == RL_MSI_MESSAGES) { 1290 device_printf(dev, "Using %d MSI-X message\n", 1291 msixc); 1292 sc->rl_flags |= RL_FLAG_MSIX; 1293 } else 1294 pci_release_msi(dev); 1295 } 1296 if ((sc->rl_flags & RL_FLAG_MSIX) == 0) { 1297 if (sc->rl_res_pba != NULL) 1298 bus_release_resource(dev, SYS_RES_MEMORY, rid, 1299 sc->rl_res_pba); 1300 sc->rl_res_pba = NULL; 1301 msixc = 0; 1302 } 1303 } 1304 /* Prefer MSI to INTx. */ 1305 if (msixc == 0 && msic > 0) { 1306 msic = RL_MSI_MESSAGES; 1307 if (pci_alloc_msi(dev, &msic) == 0) { 1308 if (msic == RL_MSI_MESSAGES) { 1309 device_printf(dev, "Using %d MSI message\n", 1310 msic); 1311 sc->rl_flags |= RL_FLAG_MSI; 1312 /* Explicitly set MSI enable bit. */ 1313 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1314 cfg = CSR_READ_1(sc, RL_CFG2); 1315 cfg |= RL_CFG2_MSI; 1316 CSR_WRITE_1(sc, RL_CFG2, cfg); 1317 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1318 } else 1319 pci_release_msi(dev); 1320 } 1321 if ((sc->rl_flags & RL_FLAG_MSI) == 0) 1322 msic = 0; 1323 } 1324 1325 /* Allocate interrupt */ 1326 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) { 1327 rid = 0; 1328 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1329 RF_SHAREABLE | RF_ACTIVE); 1330 if (sc->rl_irq[0] == NULL) { 1331 device_printf(dev, "couldn't allocate IRQ resources\n"); 1332 error = ENXIO; 1333 goto fail; 1334 } 1335 } else { 1336 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1337 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1338 SYS_RES_IRQ, &rid, RF_ACTIVE); 1339 if (sc->rl_irq[i] == NULL) { 1340 device_printf(dev, 1341 "couldn't allocate IRQ resources for " 1342 "message %d\n", rid); 1343 error = ENXIO; 1344 goto fail; 1345 } 1346 } 1347 } 1348 1349 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1350 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1351 cfg = CSR_READ_1(sc, RL_CFG2); 1352 if ((cfg & RL_CFG2_MSI) != 0) { 1353 device_printf(dev, "turning off MSI enable bit.\n"); 1354 cfg &= ~RL_CFG2_MSI; 1355 CSR_WRITE_1(sc, RL_CFG2, cfg); 1356 } 1357 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1358 } 1359 1360 /* Disable ASPM L0S/L1. */ 1361 if (sc->rl_expcap != 0) { 1362 cap = pci_read_config(dev, sc->rl_expcap + 1363 PCIER_LINK_CAP, 2); 1364 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { 1365 ctl = pci_read_config(dev, sc->rl_expcap + 1366 PCIER_LINK_CTL, 2); 1367 if ((ctl & PCIEM_LINK_CTL_ASPMC) != 0) { 1368 ctl &= ~PCIEM_LINK_CTL_ASPMC; 1369 pci_write_config(dev, sc->rl_expcap + 1370 PCIER_LINK_CTL, ctl, 2); 1371 device_printf(dev, "ASPM disabled\n"); 1372 } 1373 } else 1374 device_printf(dev, "no ASPM capability\n"); 1375 } 1376 1377 hw_rev = re_hwrevs; 1378 hwrev = CSR_READ_4(sc, RL_TXCFG); 1379 switch (hwrev & 0x70000000) { 1380 case 0x00000000: 1381 case 0x10000000: 1382 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000); 1383 hwrev &= (RL_TXCFG_HWREV | 0x80000000); 1384 break; 1385 default: 1386 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000); 1387 sc->rl_macrev = hwrev & 0x00700000; 1388 hwrev &= RL_TXCFG_HWREV; 1389 break; 1390 } 1391 device_printf(dev, "MAC rev. 0x%08x\n", sc->rl_macrev); 1392 while (hw_rev->rl_desc != NULL) { 1393 if (hw_rev->rl_rev == hwrev) { 1394 sc->rl_type = hw_rev->rl_type; 1395 sc->rl_hwrev = hw_rev; 1396 break; 1397 } 1398 hw_rev++; 1399 } 1400 if (hw_rev->rl_desc == NULL) { 1401 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev); 1402 error = ENXIO; 1403 goto fail; 1404 } 1405 1406 switch (hw_rev->rl_rev) { 1407 case RL_HWREV_8139CPLUS: 1408 sc->rl_flags |= RL_FLAG_FASTETHER | RL_FLAG_AUTOPAD; 1409 break; 1410 case RL_HWREV_8100E: 1411 case RL_HWREV_8101E: 1412 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_FASTETHER; 1413 break; 1414 case RL_HWREV_8102E: 1415 case RL_HWREV_8102EL: 1416 case RL_HWREV_8102EL_SPIN1: 1417 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1418 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | 1419 RL_FLAG_AUTOPAD; 1420 break; 1421 case RL_HWREV_8103E: 1422 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1423 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | 1424 RL_FLAG_AUTOPAD | RL_FLAG_MACSLEEP; 1425 break; 1426 case RL_HWREV_8401E: 1427 case RL_HWREV_8105E: 1428 case RL_HWREV_8105E_SPIN1: 1429 case RL_HWREV_8106E: 1430 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1431 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1432 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD; 1433 break; 1434 case RL_HWREV_8402: 1435 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1436 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1437 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | 1438 RL_FLAG_CMDSTOP_WAIT_TXQ; 1439 break; 1440 case RL_HWREV_8168B_SPIN1: 1441 case RL_HWREV_8168B_SPIN2: 1442 sc->rl_flags |= RL_FLAG_WOLRXENB; 1443 /* FALLTHROUGH */ 1444 case RL_HWREV_8168B_SPIN3: 1445 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT; 1446 break; 1447 case RL_HWREV_8168C_SPIN2: 1448 sc->rl_flags |= RL_FLAG_MACSLEEP; 1449 /* FALLTHROUGH */ 1450 case RL_HWREV_8168C: 1451 if (sc->rl_macrev == 0x00200000) 1452 sc->rl_flags |= RL_FLAG_MACSLEEP; 1453 /* FALLTHROUGH */ 1454 case RL_HWREV_8168CP: 1455 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1456 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1457 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK; 1458 break; 1459 case RL_HWREV_8168D: 1460 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1461 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1462 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1463 RL_FLAG_WOL_MANLINK; 1464 break; 1465 case RL_HWREV_8168DP: 1466 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1467 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_AUTOPAD | 1468 RL_FLAG_JUMBOV2 | RL_FLAG_WAIT_TXPOLL | RL_FLAG_WOL_MANLINK; 1469 break; 1470 case RL_HWREV_8168E: 1471 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1472 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1473 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1474 RL_FLAG_WOL_MANLINK; 1475 break; 1476 case RL_HWREV_8168E_VL: 1477 case RL_HWREV_8168F: 1478 sc->rl_flags |= RL_FLAG_EARLYOFF; 1479 /* FALLTHROUGH */ 1480 case RL_HWREV_8411: 1481 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1482 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1483 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1484 RL_FLAG_CMDSTOP_WAIT_TXQ | RL_FLAG_WOL_MANLINK; 1485 break; 1486 case RL_HWREV_8168EP: 1487 case RL_HWREV_8168G: 1488 case RL_HWREV_8411B: 1489 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1490 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1491 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1492 RL_FLAG_CMDSTOP_WAIT_TXQ | RL_FLAG_WOL_MANLINK | 1493 RL_FLAG_EARLYOFFV2 | RL_FLAG_RXDV_GATED; 1494 break; 1495 case RL_HWREV_8168GU: 1496 if (pci_get_device(dev) == RT_DEVICEID_8101E) { 1497 /* RTL8106EUS */ 1498 sc->rl_flags |= RL_FLAG_FASTETHER; 1499 } else 1500 sc->rl_flags |= RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK; 1501 1502 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1503 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1504 RL_FLAG_AUTOPAD | RL_FLAG_CMDSTOP_WAIT_TXQ | 1505 RL_FLAG_EARLYOFFV2 | RL_FLAG_RXDV_GATED; 1506 break; 1507 case RL_HWREV_8169_8110SB: 1508 case RL_HWREV_8169_8110SBL: 1509 case RL_HWREV_8169_8110SC: 1510 case RL_HWREV_8169_8110SCE: 1511 sc->rl_flags |= RL_FLAG_PHYWAKE; 1512 /* FALLTHROUGH */ 1513 case RL_HWREV_8169: 1514 case RL_HWREV_8169S: 1515 case RL_HWREV_8110S: 1516 sc->rl_flags |= RL_FLAG_MACRESET; 1517 break; 1518 default: 1519 break; 1520 } 1521 1522 if (sc->rl_hwrev->rl_rev == RL_HWREV_8139CPLUS) { 1523 sc->rl_cfg0 = RL_8139_CFG0; 1524 sc->rl_cfg1 = RL_8139_CFG1; 1525 sc->rl_cfg2 = 0; 1526 sc->rl_cfg3 = RL_8139_CFG3; 1527 sc->rl_cfg4 = RL_8139_CFG4; 1528 sc->rl_cfg5 = RL_8139_CFG5; 1529 } else { 1530 sc->rl_cfg0 = RL_CFG0; 1531 sc->rl_cfg1 = RL_CFG1; 1532 sc->rl_cfg2 = RL_CFG2; 1533 sc->rl_cfg3 = RL_CFG3; 1534 sc->rl_cfg4 = RL_CFG4; 1535 sc->rl_cfg5 = RL_CFG5; 1536 } 1537 1538 /* Reset the adapter. */ 1539 RL_LOCK(sc); 1540 re_reset(sc); 1541 RL_UNLOCK(sc); 1542 1543 /* Enable PME. */ 1544 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1545 cfg = CSR_READ_1(sc, sc->rl_cfg1); 1546 cfg |= RL_CFG1_PME; 1547 CSR_WRITE_1(sc, sc->rl_cfg1, cfg); 1548 cfg = CSR_READ_1(sc, sc->rl_cfg5); 1549 cfg &= RL_CFG5_PME_STS; 1550 CSR_WRITE_1(sc, sc->rl_cfg5, cfg); 1551 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1552 1553 if ((sc->rl_flags & RL_FLAG_PAR) != 0) { 1554 /* 1555 * XXX Should have a better way to extract station 1556 * address from EEPROM. 1557 */ 1558 for (i = 0; i < ETHER_ADDR_LEN; i++) 1559 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1560 } else { 1561 sc->rl_eewidth = RL_9356_ADDR_LEN; 1562 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1563 if (re_did != 0x8129) 1564 sc->rl_eewidth = RL_9346_ADDR_LEN; 1565 1566 /* 1567 * Get station address from the EEPROM. 1568 */ 1569 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1570 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1571 as[i] = le16toh(as[i]); 1572 bcopy(as, eaddr, ETHER_ADDR_LEN); 1573 } 1574 1575 if (sc->rl_type == RL_8169) { 1576 /* Set RX length mask and number of descriptors. */ 1577 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1578 sc->rl_txstart = RL_GTXSTART; 1579 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1580 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1581 } else { 1582 /* Set RX length mask and number of descriptors. */ 1583 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1584 sc->rl_txstart = RL_TXSTART; 1585 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1586 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1587 } 1588 1589 error = re_allocmem(dev, sc); 1590 if (error) 1591 goto fail; 1592 re_add_sysctls(sc); 1593 1594 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1595 if (ifp == NULL) { 1596 device_printf(dev, "can not if_alloc()\n"); 1597 error = ENOSPC; 1598 goto fail; 1599 } 1600 1601 /* Take controller out of deep sleep mode. */ 1602 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 1603 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 1604 CSR_WRITE_1(sc, RL_GPIO, 1605 CSR_READ_1(sc, RL_GPIO) | 0x01); 1606 else 1607 CSR_WRITE_1(sc, RL_GPIO, 1608 CSR_READ_1(sc, RL_GPIO) & ~0x01); 1609 } 1610 1611 /* Take PHY out of power down mode. */ 1612 if ((sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) { 1613 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80); 1614 if (hw_rev->rl_rev == RL_HWREV_8401E) 1615 CSR_WRITE_1(sc, 0xD1, CSR_READ_1(sc, 0xD1) & ~0x08); 1616 } 1617 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) { 1618 re_gmii_writereg(dev, 1, 0x1f, 0); 1619 re_gmii_writereg(dev, 1, 0x0e, 0); 1620 } 1621 1622 ifp->if_softc = sc; 1623 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1624 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1625 ifp->if_ioctl = re_ioctl; 1626 ifp->if_start = re_start; 1627 /* 1628 * RTL8168/8111C generates wrong IP checksummed frame if the 1629 * packet has IP options so disable TX checksum offloading. 1630 */ 1631 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168C || 1632 sc->rl_hwrev->rl_rev == RL_HWREV_8168C_SPIN2 || 1633 sc->rl_hwrev->rl_rev == RL_HWREV_8168CP) { 1634 ifp->if_hwassist = 0; 1635 ifp->if_capabilities = IFCAP_RXCSUM | IFCAP_TSO4; 1636 } else { 1637 ifp->if_hwassist = CSUM_IP | CSUM_TCP | CSUM_UDP; 1638 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 1639 } 1640 ifp->if_hwassist |= CSUM_TSO; 1641 ifp->if_capenable = ifp->if_capabilities; 1642 ifp->if_init = re_init; 1643 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1644 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1645 IFQ_SET_READY(&ifp->if_snd); 1646 1647 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1648 1649 #define RE_PHYAD_INTERNAL 0 1650 1651 /* Do MII setup. */ 1652 phy = RE_PHYAD_INTERNAL; 1653 if (sc->rl_type == RL_8169) 1654 phy = 1; 1655 error = mii_attach(dev, &sc->rl_miibus, ifp, re_ifmedia_upd, 1656 re_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, MIIF_DOPAUSE); 1657 if (error != 0) { 1658 device_printf(dev, "attaching PHYs failed\n"); 1659 goto fail; 1660 } 1661 1662 /* 1663 * Call MI attach routine. 1664 */ 1665 ether_ifattach(ifp, eaddr); 1666 1667 /* VLAN capability setup */ 1668 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1669 if (ifp->if_capabilities & IFCAP_HWCSUM) 1670 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1671 /* Enable WOL if PM is supported. */ 1672 if (pci_find_cap(sc->rl_dev, PCIY_PMG, ®) == 0) 1673 ifp->if_capabilities |= IFCAP_WOL; 1674 ifp->if_capenable = ifp->if_capabilities; 1675 ifp->if_capenable &= ~(IFCAP_WOL_UCAST | IFCAP_WOL_MCAST); 1676 /* 1677 * Don't enable TSO by default. It is known to generate 1678 * corrupted TCP segments(bad TCP options) under certain 1679 * circumstances. 1680 */ 1681 ifp->if_hwassist &= ~CSUM_TSO; 1682 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO); 1683 #ifdef DEVICE_POLLING 1684 ifp->if_capabilities |= IFCAP_POLLING; 1685 #endif 1686 /* 1687 * Tell the upper layer(s) we support long frames. 1688 * Must appear after the call to ether_ifattach() because 1689 * ether_ifattach() sets ifi_hdrlen to the default value. 1690 */ 1691 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 1692 1693 #ifdef DEV_NETMAP 1694 re_netmap_attach(sc); 1695 #endif /* DEV_NETMAP */ 1696 #ifdef RE_DIAG 1697 /* 1698 * Perform hardware diagnostic on the original RTL8169. 1699 * Some 32-bit cards were incorrectly wired and would 1700 * malfunction if plugged into a 64-bit slot. 1701 */ 1702 1703 if (hwrev == RL_HWREV_8169) { 1704 error = re_diag(sc); 1705 if (error) { 1706 device_printf(dev, 1707 "attach aborted due to hardware diag failure\n"); 1708 ether_ifdetach(ifp); 1709 goto fail; 1710 } 1711 } 1712 #endif 1713 1714 #ifdef RE_TX_MODERATION 1715 intr_filter = 1; 1716 #endif 1717 /* Hook interrupt last to avoid having to lock softc */ 1718 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 && 1719 intr_filter == 0) { 1720 error = bus_setup_intr(dev, sc->rl_irq[0], 1721 INTR_TYPE_NET | INTR_MPSAFE, NULL, re_intr_msi, sc, 1722 &sc->rl_intrhand[0]); 1723 } else { 1724 error = bus_setup_intr(dev, sc->rl_irq[0], 1725 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1726 &sc->rl_intrhand[0]); 1727 } 1728 if (error) { 1729 device_printf(dev, "couldn't set up irq\n"); 1730 ether_ifdetach(ifp); 1731 } 1732 1733 fail: 1734 1735 if (error) 1736 re_detach(dev); 1737 1738 return (error); 1739 } 1740 1741 /* 1742 * Shutdown hardware and free up resources. This can be called any 1743 * time after the mutex has been initialized. It is called in both 1744 * the error case in attach and the normal detach case so it needs 1745 * to be careful about only freeing resources that have actually been 1746 * allocated. 1747 */ 1748 static int 1749 re_detach(device_t dev) 1750 { 1751 struct rl_softc *sc; 1752 struct ifnet *ifp; 1753 int i, rid; 1754 1755 sc = device_get_softc(dev); 1756 ifp = sc->rl_ifp; 1757 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1758 1759 /* These should only be active if attach succeeded */ 1760 if (device_is_attached(dev)) { 1761 #ifdef DEVICE_POLLING 1762 if (ifp->if_capenable & IFCAP_POLLING) 1763 ether_poll_deregister(ifp); 1764 #endif 1765 RL_LOCK(sc); 1766 #if 0 1767 sc->suspended = 1; 1768 #endif 1769 re_stop(sc); 1770 RL_UNLOCK(sc); 1771 callout_drain(&sc->rl_stat_callout); 1772 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1773 /* 1774 * Force off the IFF_UP flag here, in case someone 1775 * still had a BPF descriptor attached to this 1776 * interface. If they do, ether_ifdetach() will cause 1777 * the BPF code to try and clear the promisc mode 1778 * flag, which will bubble down to re_ioctl(), 1779 * which will try to call re_init() again. This will 1780 * turn the NIC back on and restart the MII ticker, 1781 * which will panic the system when the kernel tries 1782 * to invoke the re_tick() function that isn't there 1783 * anymore. 1784 */ 1785 ifp->if_flags &= ~IFF_UP; 1786 ether_ifdetach(ifp); 1787 } 1788 if (sc->rl_miibus) 1789 device_delete_child(dev, sc->rl_miibus); 1790 bus_generic_detach(dev); 1791 1792 /* 1793 * The rest is resource deallocation, so we should already be 1794 * stopped here. 1795 */ 1796 1797 if (sc->rl_intrhand[0] != NULL) { 1798 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]); 1799 sc->rl_intrhand[0] = NULL; 1800 } 1801 if (ifp != NULL) { 1802 #ifdef DEV_NETMAP 1803 netmap_detach(ifp); 1804 #endif /* DEV_NETMAP */ 1805 if_free(ifp); 1806 } 1807 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) 1808 rid = 0; 1809 else 1810 rid = 1; 1811 if (sc->rl_irq[0] != NULL) { 1812 bus_release_resource(dev, SYS_RES_IRQ, rid, sc->rl_irq[0]); 1813 sc->rl_irq[0] = NULL; 1814 } 1815 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0) 1816 pci_release_msi(dev); 1817 if (sc->rl_res_pba) { 1818 rid = PCIR_BAR(4); 1819 bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->rl_res_pba); 1820 } 1821 if (sc->rl_res) 1822 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, 1823 sc->rl_res); 1824 1825 /* Unload and free the RX DMA ring memory and map */ 1826 1827 if (sc->rl_ldata.rl_rx_list_tag) { 1828 if (sc->rl_ldata.rl_rx_list_addr) 1829 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1830 sc->rl_ldata.rl_rx_list_map); 1831 if (sc->rl_ldata.rl_rx_list) 1832 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1833 sc->rl_ldata.rl_rx_list, 1834 sc->rl_ldata.rl_rx_list_map); 1835 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1836 } 1837 1838 /* Unload and free the TX DMA ring memory and map */ 1839 1840 if (sc->rl_ldata.rl_tx_list_tag) { 1841 if (sc->rl_ldata.rl_tx_list_addr) 1842 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1843 sc->rl_ldata.rl_tx_list_map); 1844 if (sc->rl_ldata.rl_tx_list) 1845 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1846 sc->rl_ldata.rl_tx_list, 1847 sc->rl_ldata.rl_tx_list_map); 1848 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1849 } 1850 1851 /* Destroy all the RX and TX buffer maps */ 1852 1853 if (sc->rl_ldata.rl_tx_mtag) { 1854 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1855 if (sc->rl_ldata.rl_tx_desc[i].tx_dmamap) 1856 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1857 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1858 } 1859 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1860 } 1861 if (sc->rl_ldata.rl_rx_mtag) { 1862 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1863 if (sc->rl_ldata.rl_rx_desc[i].rx_dmamap) 1864 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1865 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1866 } 1867 if (sc->rl_ldata.rl_rx_sparemap) 1868 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1869 sc->rl_ldata.rl_rx_sparemap); 1870 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1871 } 1872 if (sc->rl_ldata.rl_jrx_mtag) { 1873 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1874 if (sc->rl_ldata.rl_jrx_desc[i].rx_dmamap) 1875 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag, 1876 sc->rl_ldata.rl_jrx_desc[i].rx_dmamap); 1877 } 1878 if (sc->rl_ldata.rl_jrx_sparemap) 1879 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag, 1880 sc->rl_ldata.rl_jrx_sparemap); 1881 bus_dma_tag_destroy(sc->rl_ldata.rl_jrx_mtag); 1882 } 1883 /* Unload and free the stats buffer and map */ 1884 1885 if (sc->rl_ldata.rl_stag) { 1886 if (sc->rl_ldata.rl_stats_addr) 1887 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1888 sc->rl_ldata.rl_smap); 1889 if (sc->rl_ldata.rl_stats) 1890 bus_dmamem_free(sc->rl_ldata.rl_stag, 1891 sc->rl_ldata.rl_stats, sc->rl_ldata.rl_smap); 1892 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1893 } 1894 1895 if (sc->rl_parent_tag) 1896 bus_dma_tag_destroy(sc->rl_parent_tag); 1897 1898 mtx_destroy(&sc->rl_mtx); 1899 1900 return (0); 1901 } 1902 1903 static __inline void 1904 re_discard_rxbuf(struct rl_softc *sc, int idx) 1905 { 1906 struct rl_desc *desc; 1907 struct rl_rxdesc *rxd; 1908 uint32_t cmdstat; 1909 1910 if (sc->rl_ifp->if_mtu > RL_MTU && 1911 (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) 1912 rxd = &sc->rl_ldata.rl_jrx_desc[idx]; 1913 else 1914 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1915 desc = &sc->rl_ldata.rl_rx_list[idx]; 1916 desc->rl_vlanctl = 0; 1917 cmdstat = rxd->rx_size; 1918 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1919 cmdstat |= RL_RDESC_CMD_EOR; 1920 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1921 } 1922 1923 static int 1924 re_newbuf(struct rl_softc *sc, int idx) 1925 { 1926 struct mbuf *m; 1927 struct rl_rxdesc *rxd; 1928 bus_dma_segment_t segs[1]; 1929 bus_dmamap_t map; 1930 struct rl_desc *desc; 1931 uint32_t cmdstat; 1932 int error, nsegs; 1933 1934 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1935 if (m == NULL) 1936 return (ENOBUFS); 1937 1938 m->m_len = m->m_pkthdr.len = MCLBYTES; 1939 #ifdef RE_FIXUP_RX 1940 /* 1941 * This is part of an evil trick to deal with non-x86 platforms. 1942 * The RealTek chip requires RX buffers to be aligned on 64-bit 1943 * boundaries, but that will hose non-x86 machines. To get around 1944 * this, we leave some empty space at the start of each buffer 1945 * and for non-x86 hosts, we copy the buffer back six bytes 1946 * to achieve word alignment. This is slightly more efficient 1947 * than allocating a new buffer, copying the contents, and 1948 * discarding the old buffer. 1949 */ 1950 m_adj(m, RE_ETHER_ALIGN); 1951 #endif 1952 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1953 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1954 if (error != 0) { 1955 m_freem(m); 1956 return (ENOBUFS); 1957 } 1958 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1959 1960 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1961 if (rxd->rx_m != NULL) { 1962 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1963 BUS_DMASYNC_POSTREAD); 1964 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1965 } 1966 1967 rxd->rx_m = m; 1968 map = rxd->rx_dmamap; 1969 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1970 rxd->rx_size = segs[0].ds_len; 1971 sc->rl_ldata.rl_rx_sparemap = map; 1972 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1973 BUS_DMASYNC_PREREAD); 1974 1975 desc = &sc->rl_ldata.rl_rx_list[idx]; 1976 desc->rl_vlanctl = 0; 1977 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1978 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1979 cmdstat = segs[0].ds_len; 1980 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1981 cmdstat |= RL_RDESC_CMD_EOR; 1982 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1983 1984 return (0); 1985 } 1986 1987 static int 1988 re_jumbo_newbuf(struct rl_softc *sc, int idx) 1989 { 1990 struct mbuf *m; 1991 struct rl_rxdesc *rxd; 1992 bus_dma_segment_t segs[1]; 1993 bus_dmamap_t map; 1994 struct rl_desc *desc; 1995 uint32_t cmdstat; 1996 int error, nsegs; 1997 1998 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 1999 if (m == NULL) 2000 return (ENOBUFS); 2001 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 2002 #ifdef RE_FIXUP_RX 2003 m_adj(m, RE_ETHER_ALIGN); 2004 #endif 2005 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_jrx_mtag, 2006 sc->rl_ldata.rl_jrx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 2007 if (error != 0) { 2008 m_freem(m); 2009 return (ENOBUFS); 2010 } 2011 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 2012 2013 rxd = &sc->rl_ldata.rl_jrx_desc[idx]; 2014 if (rxd->rx_m != NULL) { 2015 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap, 2016 BUS_DMASYNC_POSTREAD); 2017 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap); 2018 } 2019 2020 rxd->rx_m = m; 2021 map = rxd->rx_dmamap; 2022 rxd->rx_dmamap = sc->rl_ldata.rl_jrx_sparemap; 2023 rxd->rx_size = segs[0].ds_len; 2024 sc->rl_ldata.rl_jrx_sparemap = map; 2025 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap, 2026 BUS_DMASYNC_PREREAD); 2027 2028 desc = &sc->rl_ldata.rl_rx_list[idx]; 2029 desc->rl_vlanctl = 0; 2030 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 2031 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 2032 cmdstat = segs[0].ds_len; 2033 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 2034 cmdstat |= RL_RDESC_CMD_EOR; 2035 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 2036 2037 return (0); 2038 } 2039 2040 #ifdef RE_FIXUP_RX 2041 static __inline void 2042 re_fixup_rx(struct mbuf *m) 2043 { 2044 int i; 2045 uint16_t *src, *dst; 2046 2047 src = mtod(m, uint16_t *); 2048 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 2049 2050 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 2051 *dst++ = *src++; 2052 2053 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 2054 } 2055 #endif 2056 2057 static int 2058 re_tx_list_init(struct rl_softc *sc) 2059 { 2060 struct rl_desc *desc; 2061 int i; 2062 2063 RL_LOCK_ASSERT(sc); 2064 2065 bzero(sc->rl_ldata.rl_tx_list, 2066 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 2067 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 2068 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 2069 #ifdef DEV_NETMAP 2070 re_netmap_tx_init(sc); 2071 #endif /* DEV_NETMAP */ 2072 /* Set EOR. */ 2073 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 2074 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 2075 2076 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2077 sc->rl_ldata.rl_tx_list_map, 2078 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2079 2080 sc->rl_ldata.rl_tx_prodidx = 0; 2081 sc->rl_ldata.rl_tx_considx = 0; 2082 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 2083 2084 return (0); 2085 } 2086 2087 static int 2088 re_rx_list_init(struct rl_softc *sc) 2089 { 2090 int error, i; 2091 2092 bzero(sc->rl_ldata.rl_rx_list, 2093 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 2094 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2095 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 2096 if ((error = re_newbuf(sc, i)) != 0) 2097 return (error); 2098 } 2099 #ifdef DEV_NETMAP 2100 re_netmap_rx_init(sc); 2101 #endif /* DEV_NETMAP */ 2102 2103 /* Flush the RX descriptors */ 2104 2105 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2106 sc->rl_ldata.rl_rx_list_map, 2107 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2108 2109 sc->rl_ldata.rl_rx_prodidx = 0; 2110 sc->rl_head = sc->rl_tail = NULL; 2111 sc->rl_int_rx_act = 0; 2112 2113 return (0); 2114 } 2115 2116 static int 2117 re_jrx_list_init(struct rl_softc *sc) 2118 { 2119 int error, i; 2120 2121 bzero(sc->rl_ldata.rl_rx_list, 2122 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 2123 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2124 sc->rl_ldata.rl_jrx_desc[i].rx_m = NULL; 2125 if ((error = re_jumbo_newbuf(sc, i)) != 0) 2126 return (error); 2127 } 2128 2129 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2130 sc->rl_ldata.rl_rx_list_map, 2131 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2132 2133 sc->rl_ldata.rl_rx_prodidx = 0; 2134 sc->rl_head = sc->rl_tail = NULL; 2135 sc->rl_int_rx_act = 0; 2136 2137 return (0); 2138 } 2139 2140 /* 2141 * RX handler for C+ and 8169. For the gigE chips, we support 2142 * the reception of jumbo frames that have been fragmented 2143 * across multiple 2K mbuf cluster buffers. 2144 */ 2145 static int 2146 re_rxeof(struct rl_softc *sc, int *rx_npktsp) 2147 { 2148 struct mbuf *m; 2149 struct ifnet *ifp; 2150 int i, rxerr, total_len; 2151 struct rl_desc *cur_rx; 2152 u_int32_t rxstat, rxvlan; 2153 int jumbo, maxpkt = 16, rx_npkts = 0; 2154 2155 RL_LOCK_ASSERT(sc); 2156 2157 ifp = sc->rl_ifp; 2158 #ifdef DEV_NETMAP 2159 if (netmap_rx_irq(ifp, 0, &rx_npkts)) 2160 return 0; 2161 #endif /* DEV_NETMAP */ 2162 if (ifp->if_mtu > RL_MTU && (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) 2163 jumbo = 1; 2164 else 2165 jumbo = 0; 2166 2167 /* Invalidate the descriptor memory */ 2168 2169 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2170 sc->rl_ldata.rl_rx_list_map, 2171 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2172 2173 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 2174 i = RL_RX_DESC_NXT(sc, i)) { 2175 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2176 break; 2177 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 2178 rxstat = le32toh(cur_rx->rl_cmdstat); 2179 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 2180 break; 2181 total_len = rxstat & sc->rl_rxlenmask; 2182 rxvlan = le32toh(cur_rx->rl_vlanctl); 2183 if (jumbo != 0) 2184 m = sc->rl_ldata.rl_jrx_desc[i].rx_m; 2185 else 2186 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 2187 2188 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 2189 (rxstat & (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) != 2190 (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) { 2191 /* 2192 * RTL8168C or later controllers do not 2193 * support multi-fragment packet. 2194 */ 2195 re_discard_rxbuf(sc, i); 2196 continue; 2197 } else if ((rxstat & RL_RDESC_STAT_EOF) == 0) { 2198 if (re_newbuf(sc, i) != 0) { 2199 /* 2200 * If this is part of a multi-fragment packet, 2201 * discard all the pieces. 2202 */ 2203 if (sc->rl_head != NULL) { 2204 m_freem(sc->rl_head); 2205 sc->rl_head = sc->rl_tail = NULL; 2206 } 2207 re_discard_rxbuf(sc, i); 2208 continue; 2209 } 2210 m->m_len = RE_RX_DESC_BUFLEN; 2211 if (sc->rl_head == NULL) 2212 sc->rl_head = sc->rl_tail = m; 2213 else { 2214 m->m_flags &= ~M_PKTHDR; 2215 sc->rl_tail->m_next = m; 2216 sc->rl_tail = m; 2217 } 2218 continue; 2219 } 2220 2221 /* 2222 * NOTE: for the 8139C+, the frame length field 2223 * is always 12 bits in size, but for the gigE chips, 2224 * it is 13 bits (since the max RX frame length is 16K). 2225 * Unfortunately, all 32 bits in the status word 2226 * were already used, so to make room for the extra 2227 * length bit, RealTek took out the 'frame alignment 2228 * error' bit and shifted the other status bits 2229 * over one slot. The OWN, EOR, FS and LS bits are 2230 * still in the same places. We have already extracted 2231 * the frame length and checked the OWN bit, so rather 2232 * than using an alternate bit mapping, we shift the 2233 * status bits one space to the right so we can evaluate 2234 * them using the 8169 status as though it was in the 2235 * same format as that of the 8139C+. 2236 */ 2237 if (sc->rl_type == RL_8169) 2238 rxstat >>= 1; 2239 2240 /* 2241 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 2242 * set, but if CRC is clear, it will still be a valid frame. 2243 */ 2244 if ((rxstat & RL_RDESC_STAT_RXERRSUM) != 0) { 2245 rxerr = 1; 2246 if ((sc->rl_flags & RL_FLAG_JUMBOV2) == 0 && 2247 total_len > 8191 && 2248 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT) 2249 rxerr = 0; 2250 if (rxerr != 0) { 2251 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2252 /* 2253 * If this is part of a multi-fragment packet, 2254 * discard all the pieces. 2255 */ 2256 if (sc->rl_head != NULL) { 2257 m_freem(sc->rl_head); 2258 sc->rl_head = sc->rl_tail = NULL; 2259 } 2260 re_discard_rxbuf(sc, i); 2261 continue; 2262 } 2263 } 2264 2265 /* 2266 * If allocating a replacement mbuf fails, 2267 * reload the current one. 2268 */ 2269 if (jumbo != 0) 2270 rxerr = re_jumbo_newbuf(sc, i); 2271 else 2272 rxerr = re_newbuf(sc, i); 2273 if (rxerr != 0) { 2274 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2275 if (sc->rl_head != NULL) { 2276 m_freem(sc->rl_head); 2277 sc->rl_head = sc->rl_tail = NULL; 2278 } 2279 re_discard_rxbuf(sc, i); 2280 continue; 2281 } 2282 2283 if (sc->rl_head != NULL) { 2284 if (jumbo != 0) 2285 m->m_len = total_len; 2286 else { 2287 m->m_len = total_len % RE_RX_DESC_BUFLEN; 2288 if (m->m_len == 0) 2289 m->m_len = RE_RX_DESC_BUFLEN; 2290 } 2291 /* 2292 * Special case: if there's 4 bytes or less 2293 * in this buffer, the mbuf can be discarded: 2294 * the last 4 bytes is the CRC, which we don't 2295 * care about anyway. 2296 */ 2297 if (m->m_len <= ETHER_CRC_LEN) { 2298 sc->rl_tail->m_len -= 2299 (ETHER_CRC_LEN - m->m_len); 2300 m_freem(m); 2301 } else { 2302 m->m_len -= ETHER_CRC_LEN; 2303 m->m_flags &= ~M_PKTHDR; 2304 sc->rl_tail->m_next = m; 2305 } 2306 m = sc->rl_head; 2307 sc->rl_head = sc->rl_tail = NULL; 2308 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 2309 } else 2310 m->m_pkthdr.len = m->m_len = 2311 (total_len - ETHER_CRC_LEN); 2312 2313 #ifdef RE_FIXUP_RX 2314 re_fixup_rx(m); 2315 #endif 2316 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 2317 m->m_pkthdr.rcvif = ifp; 2318 2319 /* Do RX checksumming if enabled */ 2320 2321 if (ifp->if_capenable & IFCAP_RXCSUM) { 2322 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2323 /* Check IP header checksum */ 2324 if (rxstat & RL_RDESC_STAT_PROTOID) 2325 m->m_pkthdr.csum_flags |= 2326 CSUM_IP_CHECKED; 2327 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 2328 m->m_pkthdr.csum_flags |= 2329 CSUM_IP_VALID; 2330 2331 /* Check TCP/UDP checksum */ 2332 if ((RL_TCPPKT(rxstat) && 2333 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 2334 (RL_UDPPKT(rxstat) && 2335 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 2336 m->m_pkthdr.csum_flags |= 2337 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2338 m->m_pkthdr.csum_data = 0xffff; 2339 } 2340 } else { 2341 /* 2342 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP 2343 */ 2344 if ((rxstat & RL_RDESC_STAT_PROTOID) && 2345 (rxvlan & RL_RDESC_IPV4)) 2346 m->m_pkthdr.csum_flags |= 2347 CSUM_IP_CHECKED; 2348 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) && 2349 (rxvlan & RL_RDESC_IPV4)) 2350 m->m_pkthdr.csum_flags |= 2351 CSUM_IP_VALID; 2352 if (((rxstat & RL_RDESC_STAT_TCP) && 2353 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 2354 ((rxstat & RL_RDESC_STAT_UDP) && 2355 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 2356 m->m_pkthdr.csum_flags |= 2357 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2358 m->m_pkthdr.csum_data = 0xffff; 2359 } 2360 } 2361 } 2362 maxpkt--; 2363 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 2364 m->m_pkthdr.ether_vtag = 2365 bswap16((rxvlan & RL_RDESC_VLANCTL_DATA)); 2366 m->m_flags |= M_VLANTAG; 2367 } 2368 RL_UNLOCK(sc); 2369 (*ifp->if_input)(ifp, m); 2370 RL_LOCK(sc); 2371 rx_npkts++; 2372 } 2373 2374 /* Flush the RX DMA ring */ 2375 2376 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2377 sc->rl_ldata.rl_rx_list_map, 2378 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2379 2380 sc->rl_ldata.rl_rx_prodidx = i; 2381 2382 if (rx_npktsp != NULL) 2383 *rx_npktsp = rx_npkts; 2384 if (maxpkt) 2385 return (EAGAIN); 2386 2387 return (0); 2388 } 2389 2390 static void 2391 re_txeof(struct rl_softc *sc) 2392 { 2393 struct ifnet *ifp; 2394 struct rl_txdesc *txd; 2395 u_int32_t txstat; 2396 int cons; 2397 2398 cons = sc->rl_ldata.rl_tx_considx; 2399 if (cons == sc->rl_ldata.rl_tx_prodidx) 2400 return; 2401 2402 ifp = sc->rl_ifp; 2403 #ifdef DEV_NETMAP 2404 if (netmap_tx_irq(ifp, 0)) 2405 return; 2406 #endif /* DEV_NETMAP */ 2407 /* Invalidate the TX descriptor list */ 2408 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2409 sc->rl_ldata.rl_tx_list_map, 2410 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2411 2412 for (; cons != sc->rl_ldata.rl_tx_prodidx; 2413 cons = RL_TX_DESC_NXT(sc, cons)) { 2414 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 2415 if (txstat & RL_TDESC_STAT_OWN) 2416 break; 2417 /* 2418 * We only stash mbufs in the last descriptor 2419 * in a fragment chain, which also happens to 2420 * be the only place where the TX status bits 2421 * are valid. 2422 */ 2423 if (txstat & RL_TDESC_CMD_EOF) { 2424 txd = &sc->rl_ldata.rl_tx_desc[cons]; 2425 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2426 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2427 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2428 txd->tx_dmamap); 2429 KASSERT(txd->tx_m != NULL, 2430 ("%s: freeing NULL mbufs!", __func__)); 2431 m_freem(txd->tx_m); 2432 txd->tx_m = NULL; 2433 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 2434 RL_TDESC_STAT_COLCNT)) 2435 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 2436 if (txstat & RL_TDESC_STAT_TXERRSUM) 2437 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2438 else 2439 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 2440 } 2441 sc->rl_ldata.rl_tx_free++; 2442 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2443 } 2444 sc->rl_ldata.rl_tx_considx = cons; 2445 2446 /* No changes made to the TX ring, so no flush needed */ 2447 2448 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 2449 #ifdef RE_TX_MODERATION 2450 /* 2451 * If not all descriptors have been reaped yet, reload 2452 * the timer so that we will eventually get another 2453 * interrupt that will cause us to re-enter this routine. 2454 * This is done in case the transmitter has gone idle. 2455 */ 2456 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2457 #endif 2458 } else 2459 sc->rl_watchdog_timer = 0; 2460 } 2461 2462 static void 2463 re_tick(void *xsc) 2464 { 2465 struct rl_softc *sc; 2466 struct mii_data *mii; 2467 2468 sc = xsc; 2469 2470 RL_LOCK_ASSERT(sc); 2471 2472 mii = device_get_softc(sc->rl_miibus); 2473 mii_tick(mii); 2474 if ((sc->rl_flags & RL_FLAG_LINK) == 0) 2475 re_miibus_statchg(sc->rl_dev); 2476 /* 2477 * Reclaim transmitted frames here. Technically it is not 2478 * necessary to do here but it ensures periodic reclamation 2479 * regardless of Tx completion interrupt which seems to be 2480 * lost on PCIe based controllers under certain situations. 2481 */ 2482 re_txeof(sc); 2483 re_watchdog(sc); 2484 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2485 } 2486 2487 #ifdef DEVICE_POLLING 2488 static int 2489 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2490 { 2491 struct rl_softc *sc = ifp->if_softc; 2492 int rx_npkts = 0; 2493 2494 RL_LOCK(sc); 2495 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2496 rx_npkts = re_poll_locked(ifp, cmd, count); 2497 RL_UNLOCK(sc); 2498 return (rx_npkts); 2499 } 2500 2501 static int 2502 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2503 { 2504 struct rl_softc *sc = ifp->if_softc; 2505 int rx_npkts; 2506 2507 RL_LOCK_ASSERT(sc); 2508 2509 sc->rxcycles = count; 2510 re_rxeof(sc, &rx_npkts); 2511 re_txeof(sc); 2512 2513 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2514 re_start_locked(ifp); 2515 2516 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2517 u_int16_t status; 2518 2519 status = CSR_READ_2(sc, RL_ISR); 2520 if (status == 0xffff) 2521 return (rx_npkts); 2522 if (status) 2523 CSR_WRITE_2(sc, RL_ISR, status); 2524 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2525 (sc->rl_flags & RL_FLAG_PCIE)) 2526 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2527 2528 /* 2529 * XXX check behaviour on receiver stalls. 2530 */ 2531 2532 if (status & RL_ISR_SYSTEM_ERR) { 2533 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2534 re_init_locked(sc); 2535 } 2536 } 2537 return (rx_npkts); 2538 } 2539 #endif /* DEVICE_POLLING */ 2540 2541 static int 2542 re_intr(void *arg) 2543 { 2544 struct rl_softc *sc; 2545 uint16_t status; 2546 2547 sc = arg; 2548 2549 status = CSR_READ_2(sc, RL_ISR); 2550 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2551 return (FILTER_STRAY); 2552 CSR_WRITE_2(sc, RL_IMR, 0); 2553 2554 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2555 2556 return (FILTER_HANDLED); 2557 } 2558 2559 static void 2560 re_int_task(void *arg, int npending) 2561 { 2562 struct rl_softc *sc; 2563 struct ifnet *ifp; 2564 u_int16_t status; 2565 int rval = 0; 2566 2567 sc = arg; 2568 ifp = sc->rl_ifp; 2569 2570 RL_LOCK(sc); 2571 2572 status = CSR_READ_2(sc, RL_ISR); 2573 CSR_WRITE_2(sc, RL_ISR, status); 2574 2575 if (sc->suspended || 2576 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2577 RL_UNLOCK(sc); 2578 return; 2579 } 2580 2581 #ifdef DEVICE_POLLING 2582 if (ifp->if_capenable & IFCAP_POLLING) { 2583 RL_UNLOCK(sc); 2584 return; 2585 } 2586 #endif 2587 2588 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2589 rval = re_rxeof(sc, NULL); 2590 2591 /* 2592 * Some chips will ignore a second TX request issued 2593 * while an existing transmission is in progress. If 2594 * the transmitter goes idle but there are still 2595 * packets waiting to be sent, we need to restart the 2596 * channel here to flush them out. This only seems to 2597 * be required with the PCIe devices. 2598 */ 2599 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2600 (sc->rl_flags & RL_FLAG_PCIE)) 2601 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2602 if (status & ( 2603 #ifdef RE_TX_MODERATION 2604 RL_ISR_TIMEOUT_EXPIRED| 2605 #else 2606 RL_ISR_TX_OK| 2607 #endif 2608 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2609 re_txeof(sc); 2610 2611 if (status & RL_ISR_SYSTEM_ERR) { 2612 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2613 re_init_locked(sc); 2614 } 2615 2616 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2617 re_start_locked(ifp); 2618 2619 RL_UNLOCK(sc); 2620 2621 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2622 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2623 return; 2624 } 2625 2626 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2627 } 2628 2629 static void 2630 re_intr_msi(void *xsc) 2631 { 2632 struct rl_softc *sc; 2633 struct ifnet *ifp; 2634 uint16_t intrs, status; 2635 2636 sc = xsc; 2637 RL_LOCK(sc); 2638 2639 ifp = sc->rl_ifp; 2640 #ifdef DEVICE_POLLING 2641 if (ifp->if_capenable & IFCAP_POLLING) { 2642 RL_UNLOCK(sc); 2643 return; 2644 } 2645 #endif 2646 /* Disable interrupts. */ 2647 CSR_WRITE_2(sc, RL_IMR, 0); 2648 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2649 RL_UNLOCK(sc); 2650 return; 2651 } 2652 2653 intrs = RL_INTRS_CPLUS; 2654 status = CSR_READ_2(sc, RL_ISR); 2655 CSR_WRITE_2(sc, RL_ISR, status); 2656 if (sc->rl_int_rx_act > 0) { 2657 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW | 2658 RL_ISR_RX_OVERRUN); 2659 status &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW | 2660 RL_ISR_RX_OVERRUN); 2661 } 2662 2663 if (status & (RL_ISR_TIMEOUT_EXPIRED | RL_ISR_RX_OK | RL_ISR_RX_ERR | 2664 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) { 2665 re_rxeof(sc, NULL); 2666 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2667 if (sc->rl_int_rx_mod != 0 && 2668 (status & (RL_ISR_RX_OK | RL_ISR_RX_ERR | 2669 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) != 0) { 2670 /* Rearm one-shot timer. */ 2671 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2672 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | 2673 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN); 2674 sc->rl_int_rx_act = 1; 2675 } else { 2676 intrs |= RL_ISR_RX_OK | RL_ISR_RX_ERR | 2677 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN; 2678 sc->rl_int_rx_act = 0; 2679 } 2680 } 2681 } 2682 2683 /* 2684 * Some chips will ignore a second TX request issued 2685 * while an existing transmission is in progress. If 2686 * the transmitter goes idle but there are still 2687 * packets waiting to be sent, we need to restart the 2688 * channel here to flush them out. This only seems to 2689 * be required with the PCIe devices. 2690 */ 2691 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2692 (sc->rl_flags & RL_FLAG_PCIE)) 2693 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2694 if (status & (RL_ISR_TX_OK | RL_ISR_TX_ERR | RL_ISR_TX_DESC_UNAVAIL)) 2695 re_txeof(sc); 2696 2697 if (status & RL_ISR_SYSTEM_ERR) { 2698 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2699 re_init_locked(sc); 2700 } 2701 2702 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2703 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2704 re_start_locked(ifp); 2705 CSR_WRITE_2(sc, RL_IMR, intrs); 2706 } 2707 RL_UNLOCK(sc); 2708 } 2709 2710 static int 2711 re_encap(struct rl_softc *sc, struct mbuf **m_head) 2712 { 2713 struct rl_txdesc *txd, *txd_last; 2714 bus_dma_segment_t segs[RL_NTXSEGS]; 2715 bus_dmamap_t map; 2716 struct mbuf *m_new; 2717 struct rl_desc *desc; 2718 int nsegs, prod; 2719 int i, error, ei, si; 2720 int padlen; 2721 uint32_t cmdstat, csum_flags, vlanctl; 2722 2723 RL_LOCK_ASSERT(sc); 2724 M_ASSERTPKTHDR((*m_head)); 2725 2726 /* 2727 * With some of the RealTek chips, using the checksum offload 2728 * support in conjunction with the autopadding feature results 2729 * in the transmission of corrupt frames. For example, if we 2730 * need to send a really small IP fragment that's less than 60 2731 * bytes in size, and IP header checksumming is enabled, the 2732 * resulting ethernet frame that appears on the wire will 2733 * have garbled payload. To work around this, if TX IP checksum 2734 * offload is enabled, we always manually pad short frames out 2735 * to the minimum ethernet frame size. 2736 */ 2737 if ((sc->rl_flags & RL_FLAG_AUTOPAD) == 0 && 2738 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN && 2739 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) { 2740 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2741 if (M_WRITABLE(*m_head) == 0) { 2742 /* Get a writable copy. */ 2743 m_new = m_dup(*m_head, M_NOWAIT); 2744 m_freem(*m_head); 2745 if (m_new == NULL) { 2746 *m_head = NULL; 2747 return (ENOBUFS); 2748 } 2749 *m_head = m_new; 2750 } 2751 if ((*m_head)->m_next != NULL || 2752 M_TRAILINGSPACE(*m_head) < padlen) { 2753 m_new = m_defrag(*m_head, M_NOWAIT); 2754 if (m_new == NULL) { 2755 m_freem(*m_head); 2756 *m_head = NULL; 2757 return (ENOBUFS); 2758 } 2759 } else 2760 m_new = *m_head; 2761 2762 /* 2763 * Manually pad short frames, and zero the pad space 2764 * to avoid leaking data. 2765 */ 2766 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2767 m_new->m_pkthdr.len += padlen; 2768 m_new->m_len = m_new->m_pkthdr.len; 2769 *m_head = m_new; 2770 } 2771 2772 prod = sc->rl_ldata.rl_tx_prodidx; 2773 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2774 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2775 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2776 if (error == EFBIG) { 2777 m_new = m_collapse(*m_head, M_NOWAIT, RL_NTXSEGS); 2778 if (m_new == NULL) { 2779 m_freem(*m_head); 2780 *m_head = NULL; 2781 return (ENOBUFS); 2782 } 2783 *m_head = m_new; 2784 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2785 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2786 if (error != 0) { 2787 m_freem(*m_head); 2788 *m_head = NULL; 2789 return (error); 2790 } 2791 } else if (error != 0) 2792 return (error); 2793 if (nsegs == 0) { 2794 m_freem(*m_head); 2795 *m_head = NULL; 2796 return (EIO); 2797 } 2798 2799 /* Check for number of available descriptors. */ 2800 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2801 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2802 return (ENOBUFS); 2803 } 2804 2805 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2806 BUS_DMASYNC_PREWRITE); 2807 2808 /* 2809 * Set up checksum offload. Note: checksum offload bits must 2810 * appear in all descriptors of a multi-descriptor transmit 2811 * attempt. This is according to testing done with an 8169 2812 * chip. This is a requirement. 2813 */ 2814 vlanctl = 0; 2815 csum_flags = 0; 2816 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2817 if ((sc->rl_flags & RL_FLAG_DESCV2) != 0) { 2818 csum_flags |= RL_TDESC_CMD_LGSEND; 2819 vlanctl |= ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2820 RL_TDESC_CMD_MSSVALV2_SHIFT); 2821 } else { 2822 csum_flags |= RL_TDESC_CMD_LGSEND | 2823 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2824 RL_TDESC_CMD_MSSVAL_SHIFT); 2825 } 2826 } else { 2827 /* 2828 * Unconditionally enable IP checksum if TCP or UDP 2829 * checksum is required. Otherwise, TCP/UDP checksum 2830 * doesn't make effects. 2831 */ 2832 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) { 2833 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2834 csum_flags |= RL_TDESC_CMD_IPCSUM; 2835 if (((*m_head)->m_pkthdr.csum_flags & 2836 CSUM_TCP) != 0) 2837 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2838 if (((*m_head)->m_pkthdr.csum_flags & 2839 CSUM_UDP) != 0) 2840 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2841 } else { 2842 vlanctl |= RL_TDESC_CMD_IPCSUMV2; 2843 if (((*m_head)->m_pkthdr.csum_flags & 2844 CSUM_TCP) != 0) 2845 vlanctl |= RL_TDESC_CMD_TCPCSUMV2; 2846 if (((*m_head)->m_pkthdr.csum_flags & 2847 CSUM_UDP) != 0) 2848 vlanctl |= RL_TDESC_CMD_UDPCSUMV2; 2849 } 2850 } 2851 } 2852 2853 /* 2854 * Set up hardware VLAN tagging. Note: vlan tag info must 2855 * appear in all descriptors of a multi-descriptor 2856 * transmission attempt. 2857 */ 2858 if ((*m_head)->m_flags & M_VLANTAG) 2859 vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) | 2860 RL_TDESC_VLANCTL_TAG; 2861 2862 si = prod; 2863 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2864 desc = &sc->rl_ldata.rl_tx_list[prod]; 2865 desc->rl_vlanctl = htole32(vlanctl); 2866 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2867 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2868 cmdstat = segs[i].ds_len; 2869 if (i != 0) 2870 cmdstat |= RL_TDESC_CMD_OWN; 2871 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2872 cmdstat |= RL_TDESC_CMD_EOR; 2873 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2874 sc->rl_ldata.rl_tx_free--; 2875 } 2876 /* Update producer index. */ 2877 sc->rl_ldata.rl_tx_prodidx = prod; 2878 2879 /* Set EOF on the last descriptor. */ 2880 ei = RL_TX_DESC_PRV(sc, prod); 2881 desc = &sc->rl_ldata.rl_tx_list[ei]; 2882 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2883 2884 desc = &sc->rl_ldata.rl_tx_list[si]; 2885 /* Set SOF and transfer ownership of packet to the chip. */ 2886 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2887 2888 /* 2889 * Insure that the map for this transmission 2890 * is placed at the array index of the last descriptor 2891 * in this chain. (Swap last and first dmamaps.) 2892 */ 2893 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2894 map = txd->tx_dmamap; 2895 txd->tx_dmamap = txd_last->tx_dmamap; 2896 txd_last->tx_dmamap = map; 2897 txd_last->tx_m = *m_head; 2898 2899 return (0); 2900 } 2901 2902 static void 2903 re_start(struct ifnet *ifp) 2904 { 2905 struct rl_softc *sc; 2906 2907 sc = ifp->if_softc; 2908 RL_LOCK(sc); 2909 re_start_locked(ifp); 2910 RL_UNLOCK(sc); 2911 } 2912 2913 /* 2914 * Main transmit routine for C+ and gigE NICs. 2915 */ 2916 static void 2917 re_start_locked(struct ifnet *ifp) 2918 { 2919 struct rl_softc *sc; 2920 struct mbuf *m_head; 2921 int queued; 2922 2923 sc = ifp->if_softc; 2924 2925 #ifdef DEV_NETMAP 2926 /* XXX is this necessary ? */ 2927 if (ifp->if_capenable & IFCAP_NETMAP) { 2928 struct netmap_kring *kring = &NA(ifp)->tx_rings[0]; 2929 if (sc->rl_ldata.rl_tx_prodidx != kring->nr_hwcur) { 2930 /* kick the tx unit */ 2931 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2932 #ifdef RE_TX_MODERATION 2933 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2934 #endif 2935 sc->rl_watchdog_timer = 5; 2936 } 2937 return; 2938 } 2939 #endif /* DEV_NETMAP */ 2940 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2941 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) 2942 return; 2943 2944 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2945 sc->rl_ldata.rl_tx_free > 1;) { 2946 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2947 if (m_head == NULL) 2948 break; 2949 2950 if (re_encap(sc, &m_head) != 0) { 2951 if (m_head == NULL) 2952 break; 2953 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2954 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2955 break; 2956 } 2957 2958 /* 2959 * If there's a BPF listener, bounce a copy of this frame 2960 * to him. 2961 */ 2962 ETHER_BPF_MTAP(ifp, m_head); 2963 2964 queued++; 2965 } 2966 2967 if (queued == 0) { 2968 #ifdef RE_TX_MODERATION 2969 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2970 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2971 #endif 2972 return; 2973 } 2974 2975 /* Flush the TX descriptors */ 2976 2977 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2978 sc->rl_ldata.rl_tx_list_map, 2979 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2980 2981 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2982 2983 #ifdef RE_TX_MODERATION 2984 /* 2985 * Use the countdown timer for interrupt moderation. 2986 * 'TX done' interrupts are disabled. Instead, we reset the 2987 * countdown timer, which will begin counting until it hits 2988 * the value in the TIMERINT register, and then trigger an 2989 * interrupt. Each time we write to the TIMERCNT register, 2990 * the timer count is reset to 0. 2991 */ 2992 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2993 #endif 2994 2995 /* 2996 * Set a timeout in case the chip goes out to lunch. 2997 */ 2998 sc->rl_watchdog_timer = 5; 2999 } 3000 3001 static void 3002 re_set_jumbo(struct rl_softc *sc, int jumbo) 3003 { 3004 3005 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168E_VL) { 3006 pci_set_max_read_req(sc->rl_dev, 4096); 3007 return; 3008 } 3009 3010 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 3011 if (jumbo != 0) { 3012 CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) | 3013 RL_CFG3_JUMBO_EN0); 3014 switch (sc->rl_hwrev->rl_rev) { 3015 case RL_HWREV_8168DP: 3016 break; 3017 case RL_HWREV_8168E: 3018 CSR_WRITE_1(sc, sc->rl_cfg4, 3019 CSR_READ_1(sc, sc->rl_cfg4) | 0x01); 3020 break; 3021 default: 3022 CSR_WRITE_1(sc, sc->rl_cfg4, 3023 CSR_READ_1(sc, sc->rl_cfg4) | RL_CFG4_JUMBO_EN1); 3024 } 3025 } else { 3026 CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) & 3027 ~RL_CFG3_JUMBO_EN0); 3028 switch (sc->rl_hwrev->rl_rev) { 3029 case RL_HWREV_8168DP: 3030 break; 3031 case RL_HWREV_8168E: 3032 CSR_WRITE_1(sc, sc->rl_cfg4, 3033 CSR_READ_1(sc, sc->rl_cfg4) & ~0x01); 3034 break; 3035 default: 3036 CSR_WRITE_1(sc, sc->rl_cfg4, 3037 CSR_READ_1(sc, sc->rl_cfg4) & ~RL_CFG4_JUMBO_EN1); 3038 } 3039 } 3040 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3041 3042 switch (sc->rl_hwrev->rl_rev) { 3043 case RL_HWREV_8168DP: 3044 pci_set_max_read_req(sc->rl_dev, 4096); 3045 break; 3046 default: 3047 if (jumbo != 0) 3048 pci_set_max_read_req(sc->rl_dev, 512); 3049 else 3050 pci_set_max_read_req(sc->rl_dev, 4096); 3051 } 3052 } 3053 3054 static void 3055 re_init(void *xsc) 3056 { 3057 struct rl_softc *sc = xsc; 3058 3059 RL_LOCK(sc); 3060 re_init_locked(sc); 3061 RL_UNLOCK(sc); 3062 } 3063 3064 static void 3065 re_init_locked(struct rl_softc *sc) 3066 { 3067 struct ifnet *ifp = sc->rl_ifp; 3068 struct mii_data *mii; 3069 uint32_t reg; 3070 uint16_t cfg; 3071 union { 3072 uint32_t align_dummy; 3073 u_char eaddr[ETHER_ADDR_LEN]; 3074 } eaddr; 3075 3076 RL_LOCK_ASSERT(sc); 3077 3078 mii = device_get_softc(sc->rl_miibus); 3079 3080 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3081 return; 3082 3083 /* 3084 * Cancel pending I/O and free all RX/TX buffers. 3085 */ 3086 re_stop(sc); 3087 3088 /* Put controller into known state. */ 3089 re_reset(sc); 3090 3091 /* 3092 * For C+ mode, initialize the RX descriptors and mbufs. 3093 */ 3094 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3095 if (ifp->if_mtu > RL_MTU) { 3096 if (re_jrx_list_init(sc) != 0) { 3097 device_printf(sc->rl_dev, 3098 "no memory for jumbo RX buffers\n"); 3099 re_stop(sc); 3100 return; 3101 } 3102 /* Disable checksum offloading for jumbo frames. */ 3103 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_TSO4); 3104 ifp->if_hwassist &= ~(RE_CSUM_FEATURES | CSUM_TSO); 3105 } else { 3106 if (re_rx_list_init(sc) != 0) { 3107 device_printf(sc->rl_dev, 3108 "no memory for RX buffers\n"); 3109 re_stop(sc); 3110 return; 3111 } 3112 } 3113 re_set_jumbo(sc, ifp->if_mtu > RL_MTU); 3114 } else { 3115 if (re_rx_list_init(sc) != 0) { 3116 device_printf(sc->rl_dev, "no memory for RX buffers\n"); 3117 re_stop(sc); 3118 return; 3119 } 3120 if ((sc->rl_flags & RL_FLAG_PCIE) != 0 && 3121 pci_get_device(sc->rl_dev) != RT_DEVICEID_8101E) { 3122 if (ifp->if_mtu > RL_MTU) 3123 pci_set_max_read_req(sc->rl_dev, 512); 3124 else 3125 pci_set_max_read_req(sc->rl_dev, 4096); 3126 } 3127 } 3128 re_tx_list_init(sc); 3129 3130 /* 3131 * Enable C+ RX and TX mode, as well as VLAN stripping and 3132 * RX checksum offload. We must configure the C+ register 3133 * before all others. 3134 */ 3135 cfg = RL_CPLUSCMD_PCI_MRW; 3136 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 3137 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 3138 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3139 cfg |= RL_CPLUSCMD_VLANSTRIP; 3140 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) { 3141 cfg |= RL_CPLUSCMD_MACSTAT_DIS; 3142 /* XXX magic. */ 3143 cfg |= 0x0001; 3144 } else 3145 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB; 3146 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg); 3147 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SC || 3148 sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) { 3149 reg = 0x000fff00; 3150 if ((CSR_READ_1(sc, sc->rl_cfg2) & RL_CFG2_PCI66MHZ) != 0) 3151 reg |= 0x000000ff; 3152 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) 3153 reg |= 0x00f00000; 3154 CSR_WRITE_4(sc, 0x7c, reg); 3155 /* Disable interrupt mitigation. */ 3156 CSR_WRITE_2(sc, 0xe2, 0); 3157 } 3158 /* 3159 * Disable TSO if interface MTU size is greater than MSS 3160 * allowed in controller. 3161 */ 3162 if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) { 3163 ifp->if_capenable &= ~IFCAP_TSO4; 3164 ifp->if_hwassist &= ~CSUM_TSO; 3165 } 3166 3167 /* 3168 * Init our MAC address. Even though the chipset 3169 * documentation doesn't mention it, we need to enter "Config 3170 * register write enable" mode to modify the ID registers. 3171 */ 3172 /* Copy MAC address on stack to align. */ 3173 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 3174 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 3175 CSR_WRITE_4(sc, RL_IDR0, 3176 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 3177 CSR_WRITE_4(sc, RL_IDR4, 3178 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 3179 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3180 3181 /* 3182 * Load the addresses of the RX and TX lists into the chip. 3183 */ 3184 3185 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 3186 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 3187 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 3188 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 3189 3190 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 3191 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 3192 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 3193 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 3194 3195 if ((sc->rl_flags & RL_FLAG_RXDV_GATED) != 0) 3196 CSR_WRITE_4(sc, RL_MISC, CSR_READ_4(sc, RL_MISC) & 3197 ~0x00080000); 3198 3199 /* 3200 * Set the initial TX configuration. 3201 */ 3202 if (sc->rl_testmode) { 3203 if (sc->rl_type == RL_8169) 3204 CSR_WRITE_4(sc, RL_TXCFG, 3205 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 3206 else 3207 CSR_WRITE_4(sc, RL_TXCFG, 3208 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 3209 } else 3210 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 3211 3212 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 3213 3214 /* 3215 * Set the initial RX configuration. 3216 */ 3217 re_set_rxmode(sc); 3218 3219 /* Configure interrupt moderation. */ 3220 if (sc->rl_type == RL_8169) { 3221 /* Magic from vendor. */ 3222 CSR_WRITE_2(sc, RL_INTRMOD, 0x5100); 3223 } 3224 3225 /* 3226 * Enable transmit and receive. 3227 */ 3228 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB | RL_CMD_RX_ENB); 3229 3230 #ifdef DEVICE_POLLING 3231 /* 3232 * Disable interrupts if we are polling. 3233 */ 3234 if (ifp->if_capenable & IFCAP_POLLING) 3235 CSR_WRITE_2(sc, RL_IMR, 0); 3236 else /* otherwise ... */ 3237 #endif 3238 3239 /* 3240 * Enable interrupts. 3241 */ 3242 if (sc->rl_testmode) 3243 CSR_WRITE_2(sc, RL_IMR, 0); 3244 else 3245 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 3246 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 3247 3248 /* Set initial TX threshold */ 3249 sc->rl_txthresh = RL_TX_THRESH_INIT; 3250 3251 /* Start RX/TX process. */ 3252 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 3253 3254 /* 3255 * Initialize the timer interrupt register so that 3256 * a timer interrupt will be generated once the timer 3257 * reaches a certain number of ticks. The timer is 3258 * reloaded on each transmit. 3259 */ 3260 #ifdef RE_TX_MODERATION 3261 /* 3262 * Use timer interrupt register to moderate TX interrupt 3263 * moderation, which dramatically improves TX frame rate. 3264 */ 3265 if (sc->rl_type == RL_8169) 3266 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 3267 else 3268 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 3269 #else 3270 /* 3271 * Use timer interrupt register to moderate RX interrupt 3272 * moderation. 3273 */ 3274 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 && 3275 intr_filter == 0) { 3276 if (sc->rl_type == RL_8169) 3277 CSR_WRITE_4(sc, RL_TIMERINT_8169, 3278 RL_USECS(sc->rl_int_rx_mod)); 3279 } else { 3280 if (sc->rl_type == RL_8169) 3281 CSR_WRITE_4(sc, RL_TIMERINT_8169, RL_USECS(0)); 3282 } 3283 #endif 3284 3285 /* 3286 * For 8169 gigE NICs, set the max allowed RX packet 3287 * size so we can receive jumbo frames. 3288 */ 3289 if (sc->rl_type == RL_8169) { 3290 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3291 /* 3292 * For controllers that use new jumbo frame scheme, 3293 * set maximum size of jumbo frame depending on 3294 * controller revisions. 3295 */ 3296 if (ifp->if_mtu > RL_MTU) 3297 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 3298 sc->rl_hwrev->rl_max_mtu + 3299 ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN + 3300 ETHER_CRC_LEN); 3301 else 3302 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 3303 RE_RX_DESC_BUFLEN); 3304 } else if ((sc->rl_flags & RL_FLAG_PCIE) != 0 && 3305 sc->rl_hwrev->rl_max_mtu == RL_MTU) { 3306 /* RTL810x has no jumbo frame support. */ 3307 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, RE_RX_DESC_BUFLEN); 3308 } else 3309 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 3310 } 3311 3312 if (sc->rl_testmode) 3313 return; 3314 3315 CSR_WRITE_1(sc, sc->rl_cfg1, CSR_READ_1(sc, sc->rl_cfg1) | 3316 RL_CFG1_DRVLOAD); 3317 3318 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3319 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3320 3321 sc->rl_flags &= ~RL_FLAG_LINK; 3322 mii_mediachg(mii); 3323 3324 sc->rl_watchdog_timer = 0; 3325 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 3326 } 3327 3328 /* 3329 * Set media options. 3330 */ 3331 static int 3332 re_ifmedia_upd(struct ifnet *ifp) 3333 { 3334 struct rl_softc *sc; 3335 struct mii_data *mii; 3336 int error; 3337 3338 sc = ifp->if_softc; 3339 mii = device_get_softc(sc->rl_miibus); 3340 RL_LOCK(sc); 3341 error = mii_mediachg(mii); 3342 RL_UNLOCK(sc); 3343 3344 return (error); 3345 } 3346 3347 /* 3348 * Report current media status. 3349 */ 3350 static void 3351 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3352 { 3353 struct rl_softc *sc; 3354 struct mii_data *mii; 3355 3356 sc = ifp->if_softc; 3357 mii = device_get_softc(sc->rl_miibus); 3358 3359 RL_LOCK(sc); 3360 mii_pollstat(mii); 3361 ifmr->ifm_active = mii->mii_media_active; 3362 ifmr->ifm_status = mii->mii_media_status; 3363 RL_UNLOCK(sc); 3364 } 3365 3366 static int 3367 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3368 { 3369 struct rl_softc *sc = ifp->if_softc; 3370 struct ifreq *ifr = (struct ifreq *) data; 3371 struct mii_data *mii; 3372 int error = 0; 3373 3374 switch (command) { 3375 case SIOCSIFMTU: 3376 if (ifr->ifr_mtu < ETHERMIN || 3377 ifr->ifr_mtu > sc->rl_hwrev->rl_max_mtu || 3378 ((sc->rl_flags & RL_FLAG_FASTETHER) != 0 && 3379 ifr->ifr_mtu > RL_MTU)) { 3380 error = EINVAL; 3381 break; 3382 } 3383 RL_LOCK(sc); 3384 if (ifp->if_mtu != ifr->ifr_mtu) { 3385 ifp->if_mtu = ifr->ifr_mtu; 3386 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 3387 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3388 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3389 re_init_locked(sc); 3390 } 3391 if (ifp->if_mtu > RL_TSO_MTU && 3392 (ifp->if_capenable & IFCAP_TSO4) != 0) { 3393 ifp->if_capenable &= ~(IFCAP_TSO4 | 3394 IFCAP_VLAN_HWTSO); 3395 ifp->if_hwassist &= ~CSUM_TSO; 3396 } 3397 VLAN_CAPABILITIES(ifp); 3398 } 3399 RL_UNLOCK(sc); 3400 break; 3401 case SIOCSIFFLAGS: 3402 RL_LOCK(sc); 3403 if ((ifp->if_flags & IFF_UP) != 0) { 3404 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3405 if (((ifp->if_flags ^ sc->rl_if_flags) 3406 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 3407 re_set_rxmode(sc); 3408 } else 3409 re_init_locked(sc); 3410 } else { 3411 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3412 re_stop(sc); 3413 } 3414 sc->rl_if_flags = ifp->if_flags; 3415 RL_UNLOCK(sc); 3416 break; 3417 case SIOCADDMULTI: 3418 case SIOCDELMULTI: 3419 RL_LOCK(sc); 3420 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3421 re_set_rxmode(sc); 3422 RL_UNLOCK(sc); 3423 break; 3424 case SIOCGIFMEDIA: 3425 case SIOCSIFMEDIA: 3426 mii = device_get_softc(sc->rl_miibus); 3427 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3428 break; 3429 case SIOCSIFCAP: 3430 { 3431 int mask, reinit; 3432 3433 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3434 reinit = 0; 3435 #ifdef DEVICE_POLLING 3436 if (mask & IFCAP_POLLING) { 3437 if (ifr->ifr_reqcap & IFCAP_POLLING) { 3438 error = ether_poll_register(re_poll, ifp); 3439 if (error) 3440 return (error); 3441 RL_LOCK(sc); 3442 /* Disable interrupts */ 3443 CSR_WRITE_2(sc, RL_IMR, 0x0000); 3444 ifp->if_capenable |= IFCAP_POLLING; 3445 RL_UNLOCK(sc); 3446 } else { 3447 error = ether_poll_deregister(ifp); 3448 /* Enable interrupts. */ 3449 RL_LOCK(sc); 3450 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 3451 ifp->if_capenable &= ~IFCAP_POLLING; 3452 RL_UNLOCK(sc); 3453 } 3454 } 3455 #endif /* DEVICE_POLLING */ 3456 RL_LOCK(sc); 3457 if ((mask & IFCAP_TXCSUM) != 0 && 3458 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 3459 ifp->if_capenable ^= IFCAP_TXCSUM; 3460 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 3461 ifp->if_hwassist |= RE_CSUM_FEATURES; 3462 else 3463 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 3464 reinit = 1; 3465 } 3466 if ((mask & IFCAP_RXCSUM) != 0 && 3467 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 3468 ifp->if_capenable ^= IFCAP_RXCSUM; 3469 reinit = 1; 3470 } 3471 if ((mask & IFCAP_TSO4) != 0 && 3472 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 3473 ifp->if_capenable ^= IFCAP_TSO4; 3474 if ((IFCAP_TSO4 & ifp->if_capenable) != 0) 3475 ifp->if_hwassist |= CSUM_TSO; 3476 else 3477 ifp->if_hwassist &= ~CSUM_TSO; 3478 if (ifp->if_mtu > RL_TSO_MTU && 3479 (ifp->if_capenable & IFCAP_TSO4) != 0) { 3480 ifp->if_capenable &= ~IFCAP_TSO4; 3481 ifp->if_hwassist &= ~CSUM_TSO; 3482 } 3483 } 3484 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 3485 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 3486 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 3487 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3488 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 3489 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 3490 /* TSO over VLAN requires VLAN hardware tagging. */ 3491 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 3492 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 3493 reinit = 1; 3494 } 3495 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 3496 (mask & (IFCAP_HWCSUM | IFCAP_TSO4 | 3497 IFCAP_VLAN_HWTSO)) != 0) 3498 reinit = 1; 3499 if ((mask & IFCAP_WOL) != 0 && 3500 (ifp->if_capabilities & IFCAP_WOL) != 0) { 3501 if ((mask & IFCAP_WOL_UCAST) != 0) 3502 ifp->if_capenable ^= IFCAP_WOL_UCAST; 3503 if ((mask & IFCAP_WOL_MCAST) != 0) 3504 ifp->if_capenable ^= IFCAP_WOL_MCAST; 3505 if ((mask & IFCAP_WOL_MAGIC) != 0) 3506 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 3507 } 3508 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) { 3509 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3510 re_init_locked(sc); 3511 } 3512 RL_UNLOCK(sc); 3513 VLAN_CAPABILITIES(ifp); 3514 } 3515 break; 3516 default: 3517 error = ether_ioctl(ifp, command, data); 3518 break; 3519 } 3520 3521 return (error); 3522 } 3523 3524 static void 3525 re_watchdog(struct rl_softc *sc) 3526 { 3527 struct ifnet *ifp; 3528 3529 RL_LOCK_ASSERT(sc); 3530 3531 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 3532 return; 3533 3534 ifp = sc->rl_ifp; 3535 re_txeof(sc); 3536 if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) { 3537 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 3538 "-- recovering\n"); 3539 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3540 re_start_locked(ifp); 3541 return; 3542 } 3543 3544 if_printf(ifp, "watchdog timeout\n"); 3545 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3546 3547 re_rxeof(sc, NULL); 3548 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3549 re_init_locked(sc); 3550 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3551 re_start_locked(ifp); 3552 } 3553 3554 /* 3555 * Stop the adapter and free any mbufs allocated to the 3556 * RX and TX lists. 3557 */ 3558 static void 3559 re_stop(struct rl_softc *sc) 3560 { 3561 int i; 3562 struct ifnet *ifp; 3563 struct rl_txdesc *txd; 3564 struct rl_rxdesc *rxd; 3565 3566 RL_LOCK_ASSERT(sc); 3567 3568 ifp = sc->rl_ifp; 3569 3570 sc->rl_watchdog_timer = 0; 3571 callout_stop(&sc->rl_stat_callout); 3572 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3573 3574 /* 3575 * Disable accepting frames to put RX MAC into idle state. 3576 * Otherwise it's possible to get frames while stop command 3577 * execution is in progress and controller can DMA the frame 3578 * to already freed RX buffer during that period. 3579 */ 3580 CSR_WRITE_4(sc, RL_RXCFG, CSR_READ_4(sc, RL_RXCFG) & 3581 ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_MULTI | 3582 RL_RXCFG_RX_BROAD)); 3583 3584 if ((sc->rl_flags & RL_FLAG_WAIT_TXPOLL) != 0) { 3585 for (i = RL_TIMEOUT; i > 0; i--) { 3586 if ((CSR_READ_1(sc, sc->rl_txstart) & 3587 RL_TXSTART_START) == 0) 3588 break; 3589 DELAY(20); 3590 } 3591 if (i == 0) 3592 device_printf(sc->rl_dev, 3593 "stopping TX poll timed out!\n"); 3594 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 3595 } else if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0) { 3596 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB | 3597 RL_CMD_RX_ENB); 3598 if ((sc->rl_flags & RL_FLAG_CMDSTOP_WAIT_TXQ) != 0) { 3599 for (i = RL_TIMEOUT; i > 0; i--) { 3600 if ((CSR_READ_4(sc, RL_TXCFG) & 3601 RL_TXCFG_QUEUE_EMPTY) != 0) 3602 break; 3603 DELAY(100); 3604 } 3605 if (i == 0) 3606 device_printf(sc->rl_dev, 3607 "stopping TXQ timed out!\n"); 3608 } 3609 } else 3610 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 3611 DELAY(1000); 3612 CSR_WRITE_2(sc, RL_IMR, 0x0000); 3613 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 3614 3615 if (sc->rl_head != NULL) { 3616 m_freem(sc->rl_head); 3617 sc->rl_head = sc->rl_tail = NULL; 3618 } 3619 3620 /* Free the TX list buffers. */ 3621 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 3622 txd = &sc->rl_ldata.rl_tx_desc[i]; 3623 if (txd->tx_m != NULL) { 3624 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 3625 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3626 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 3627 txd->tx_dmamap); 3628 m_freem(txd->tx_m); 3629 txd->tx_m = NULL; 3630 } 3631 } 3632 3633 /* Free the RX list buffers. */ 3634 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 3635 rxd = &sc->rl_ldata.rl_rx_desc[i]; 3636 if (rxd->rx_m != NULL) { 3637 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 3638 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3639 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 3640 rxd->rx_dmamap); 3641 m_freem(rxd->rx_m); 3642 rxd->rx_m = NULL; 3643 } 3644 } 3645 3646 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3647 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 3648 rxd = &sc->rl_ldata.rl_jrx_desc[i]; 3649 if (rxd->rx_m != NULL) { 3650 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, 3651 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3652 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, 3653 rxd->rx_dmamap); 3654 m_freem(rxd->rx_m); 3655 rxd->rx_m = NULL; 3656 } 3657 } 3658 } 3659 } 3660 3661 /* 3662 * Device suspend routine. Stop the interface and save some PCI 3663 * settings in case the BIOS doesn't restore them properly on 3664 * resume. 3665 */ 3666 static int 3667 re_suspend(device_t dev) 3668 { 3669 struct rl_softc *sc; 3670 3671 sc = device_get_softc(dev); 3672 3673 RL_LOCK(sc); 3674 re_stop(sc); 3675 re_setwol(sc); 3676 sc->suspended = 1; 3677 RL_UNLOCK(sc); 3678 3679 return (0); 3680 } 3681 3682 /* 3683 * Device resume routine. Restore some PCI settings in case the BIOS 3684 * doesn't, re-enable busmastering, and restart the interface if 3685 * appropriate. 3686 */ 3687 static int 3688 re_resume(device_t dev) 3689 { 3690 struct rl_softc *sc; 3691 struct ifnet *ifp; 3692 3693 sc = device_get_softc(dev); 3694 3695 RL_LOCK(sc); 3696 3697 ifp = sc->rl_ifp; 3698 /* Take controller out of sleep mode. */ 3699 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3700 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3701 CSR_WRITE_1(sc, RL_GPIO, 3702 CSR_READ_1(sc, RL_GPIO) | 0x01); 3703 } 3704 3705 /* 3706 * Clear WOL matching such that normal Rx filtering 3707 * wouldn't interfere with WOL patterns. 3708 */ 3709 re_clrwol(sc); 3710 3711 /* reinitialize interface if necessary */ 3712 if (ifp->if_flags & IFF_UP) 3713 re_init_locked(sc); 3714 3715 sc->suspended = 0; 3716 RL_UNLOCK(sc); 3717 3718 return (0); 3719 } 3720 3721 /* 3722 * Stop all chip I/O so that the kernel's probe routines don't 3723 * get confused by errant DMAs when rebooting. 3724 */ 3725 static int 3726 re_shutdown(device_t dev) 3727 { 3728 struct rl_softc *sc; 3729 3730 sc = device_get_softc(dev); 3731 3732 RL_LOCK(sc); 3733 re_stop(sc); 3734 /* 3735 * Mark interface as down since otherwise we will panic if 3736 * interrupt comes in later on, which can happen in some 3737 * cases. 3738 */ 3739 sc->rl_ifp->if_flags &= ~IFF_UP; 3740 re_setwol(sc); 3741 RL_UNLOCK(sc); 3742 3743 return (0); 3744 } 3745 3746 static void 3747 re_set_linkspeed(struct rl_softc *sc) 3748 { 3749 struct mii_softc *miisc; 3750 struct mii_data *mii; 3751 int aneg, i, phyno; 3752 3753 RL_LOCK_ASSERT(sc); 3754 3755 mii = device_get_softc(sc->rl_miibus); 3756 mii_pollstat(mii); 3757 aneg = 0; 3758 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 3759 (IFM_ACTIVE | IFM_AVALID)) { 3760 switch IFM_SUBTYPE(mii->mii_media_active) { 3761 case IFM_10_T: 3762 case IFM_100_TX: 3763 return; 3764 case IFM_1000_T: 3765 aneg++; 3766 break; 3767 default: 3768 break; 3769 } 3770 } 3771 miisc = LIST_FIRST(&mii->mii_phys); 3772 phyno = miisc->mii_phy; 3773 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 3774 PHY_RESET(miisc); 3775 re_miibus_writereg(sc->rl_dev, phyno, MII_100T2CR, 0); 3776 re_miibus_writereg(sc->rl_dev, phyno, 3777 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 3778 re_miibus_writereg(sc->rl_dev, phyno, 3779 MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 3780 DELAY(1000); 3781 if (aneg != 0) { 3782 /* 3783 * Poll link state until re(4) get a 10/100Mbps link. 3784 */ 3785 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 3786 mii_pollstat(mii); 3787 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 3788 == (IFM_ACTIVE | IFM_AVALID)) { 3789 switch (IFM_SUBTYPE(mii->mii_media_active)) { 3790 case IFM_10_T: 3791 case IFM_100_TX: 3792 return; 3793 default: 3794 break; 3795 } 3796 } 3797 RL_UNLOCK(sc); 3798 pause("relnk", hz); 3799 RL_LOCK(sc); 3800 } 3801 if (i == MII_ANEGTICKS_GIGE) 3802 device_printf(sc->rl_dev, 3803 "establishing a link failed, WOL may not work!"); 3804 } 3805 /* 3806 * No link, force MAC to have 100Mbps, full-duplex link. 3807 * MAC does not require reprogramming on resolved speed/duplex, 3808 * so this is just for completeness. 3809 */ 3810 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 3811 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 3812 } 3813 3814 static void 3815 re_setwol(struct rl_softc *sc) 3816 { 3817 struct ifnet *ifp; 3818 int pmc; 3819 uint16_t pmstat; 3820 uint8_t v; 3821 3822 RL_LOCK_ASSERT(sc); 3823 3824 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3825 return; 3826 3827 ifp = sc->rl_ifp; 3828 /* Put controller into sleep mode. */ 3829 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3830 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3831 CSR_WRITE_1(sc, RL_GPIO, 3832 CSR_READ_1(sc, RL_GPIO) & ~0x01); 3833 } 3834 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 3835 re_set_rxmode(sc); 3836 if ((sc->rl_flags & RL_FLAG_WOL_MANLINK) != 0) 3837 re_set_linkspeed(sc); 3838 if ((sc->rl_flags & RL_FLAG_WOLRXENB) != 0) 3839 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB); 3840 } 3841 /* Enable config register write. */ 3842 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3843 3844 /* Enable PME. */ 3845 v = CSR_READ_1(sc, sc->rl_cfg1); 3846 v &= ~RL_CFG1_PME; 3847 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3848 v |= RL_CFG1_PME; 3849 CSR_WRITE_1(sc, sc->rl_cfg1, v); 3850 3851 v = CSR_READ_1(sc, sc->rl_cfg3); 3852 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3853 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3854 v |= RL_CFG3_WOL_MAGIC; 3855 CSR_WRITE_1(sc, sc->rl_cfg3, v); 3856 3857 v = CSR_READ_1(sc, sc->rl_cfg5); 3858 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST | 3859 RL_CFG5_WOL_LANWAKE); 3860 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 3861 v |= RL_CFG5_WOL_UCAST; 3862 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 3863 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 3864 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3865 v |= RL_CFG5_WOL_LANWAKE; 3866 CSR_WRITE_1(sc, sc->rl_cfg5, v); 3867 3868 /* Config register write done. */ 3869 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3870 3871 if ((ifp->if_capenable & IFCAP_WOL) == 0 && 3872 (sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) 3873 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) & ~0x80); 3874 /* 3875 * It seems that hardware resets its link speed to 100Mbps in 3876 * power down mode so switching to 100Mbps in driver is not 3877 * needed. 3878 */ 3879 3880 /* Request PME if WOL is requested. */ 3881 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 3882 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3883 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3884 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3885 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 3886 } 3887 3888 static void 3889 re_clrwol(struct rl_softc *sc) 3890 { 3891 int pmc; 3892 uint8_t v; 3893 3894 RL_LOCK_ASSERT(sc); 3895 3896 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3897 return; 3898 3899 /* Enable config register write. */ 3900 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3901 3902 v = CSR_READ_1(sc, sc->rl_cfg3); 3903 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3904 CSR_WRITE_1(sc, sc->rl_cfg3, v); 3905 3906 /* Config register write done. */ 3907 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3908 3909 v = CSR_READ_1(sc, sc->rl_cfg5); 3910 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3911 v &= ~RL_CFG5_WOL_LANWAKE; 3912 CSR_WRITE_1(sc, sc->rl_cfg5, v); 3913 } 3914 3915 static void 3916 re_add_sysctls(struct rl_softc *sc) 3917 { 3918 struct sysctl_ctx_list *ctx; 3919 struct sysctl_oid_list *children; 3920 int error; 3921 3922 ctx = device_get_sysctl_ctx(sc->rl_dev); 3923 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev)); 3924 3925 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "stats", 3926 CTLTYPE_INT | CTLFLAG_RW, sc, 0, re_sysctl_stats, "I", 3927 "Statistics Information"); 3928 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) 3929 return; 3930 3931 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "int_rx_mod", 3932 CTLTYPE_INT | CTLFLAG_RW, &sc->rl_int_rx_mod, 0, 3933 sysctl_hw_re_int_mod, "I", "re RX interrupt moderation"); 3934 /* Pull in device tunables. */ 3935 sc->rl_int_rx_mod = RL_TIMER_DEFAULT; 3936 error = resource_int_value(device_get_name(sc->rl_dev), 3937 device_get_unit(sc->rl_dev), "int_rx_mod", &sc->rl_int_rx_mod); 3938 if (error == 0) { 3939 if (sc->rl_int_rx_mod < RL_TIMER_MIN || 3940 sc->rl_int_rx_mod > RL_TIMER_MAX) { 3941 device_printf(sc->rl_dev, "int_rx_mod value out of " 3942 "range; using default: %d\n", 3943 RL_TIMER_DEFAULT); 3944 sc->rl_int_rx_mod = RL_TIMER_DEFAULT; 3945 } 3946 } 3947 3948 } 3949 3950 static int 3951 re_sysctl_stats(SYSCTL_HANDLER_ARGS) 3952 { 3953 struct rl_softc *sc; 3954 struct rl_stats *stats; 3955 int error, i, result; 3956 3957 result = -1; 3958 error = sysctl_handle_int(oidp, &result, 0, req); 3959 if (error || req->newptr == NULL) 3960 return (error); 3961 3962 if (result == 1) { 3963 sc = (struct rl_softc *)arg1; 3964 RL_LOCK(sc); 3965 if ((sc->rl_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 3966 RL_UNLOCK(sc); 3967 goto done; 3968 } 3969 bus_dmamap_sync(sc->rl_ldata.rl_stag, 3970 sc->rl_ldata.rl_smap, BUS_DMASYNC_PREREAD); 3971 CSR_WRITE_4(sc, RL_DUMPSTATS_HI, 3972 RL_ADDR_HI(sc->rl_ldata.rl_stats_addr)); 3973 CSR_WRITE_4(sc, RL_DUMPSTATS_LO, 3974 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr)); 3975 CSR_WRITE_4(sc, RL_DUMPSTATS_LO, 3976 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr | 3977 RL_DUMPSTATS_START)); 3978 for (i = RL_TIMEOUT; i > 0; i--) { 3979 if ((CSR_READ_4(sc, RL_DUMPSTATS_LO) & 3980 RL_DUMPSTATS_START) == 0) 3981 break; 3982 DELAY(1000); 3983 } 3984 bus_dmamap_sync(sc->rl_ldata.rl_stag, 3985 sc->rl_ldata.rl_smap, BUS_DMASYNC_POSTREAD); 3986 RL_UNLOCK(sc); 3987 if (i == 0) { 3988 device_printf(sc->rl_dev, 3989 "DUMP statistics request timed out\n"); 3990 return (ETIMEDOUT); 3991 } 3992 done: 3993 stats = sc->rl_ldata.rl_stats; 3994 printf("%s statistics:\n", device_get_nameunit(sc->rl_dev)); 3995 printf("Tx frames : %ju\n", 3996 (uintmax_t)le64toh(stats->rl_tx_pkts)); 3997 printf("Rx frames : %ju\n", 3998 (uintmax_t)le64toh(stats->rl_rx_pkts)); 3999 printf("Tx errors : %ju\n", 4000 (uintmax_t)le64toh(stats->rl_tx_errs)); 4001 printf("Rx errors : %u\n", 4002 le32toh(stats->rl_rx_errs)); 4003 printf("Rx missed frames : %u\n", 4004 (uint32_t)le16toh(stats->rl_missed_pkts)); 4005 printf("Rx frame alignment errs : %u\n", 4006 (uint32_t)le16toh(stats->rl_rx_framealign_errs)); 4007 printf("Tx single collisions : %u\n", 4008 le32toh(stats->rl_tx_onecoll)); 4009 printf("Tx multiple collisions : %u\n", 4010 le32toh(stats->rl_tx_multicolls)); 4011 printf("Rx unicast frames : %ju\n", 4012 (uintmax_t)le64toh(stats->rl_rx_ucasts)); 4013 printf("Rx broadcast frames : %ju\n", 4014 (uintmax_t)le64toh(stats->rl_rx_bcasts)); 4015 printf("Rx multicast frames : %u\n", 4016 le32toh(stats->rl_rx_mcasts)); 4017 printf("Tx aborts : %u\n", 4018 (uint32_t)le16toh(stats->rl_tx_aborts)); 4019 printf("Tx underruns : %u\n", 4020 (uint32_t)le16toh(stats->rl_rx_underruns)); 4021 } 4022 4023 return (error); 4024 } 4025 4026 static int 4027 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4028 { 4029 int error, value; 4030 4031 if (arg1 == NULL) 4032 return (EINVAL); 4033 value = *(int *)arg1; 4034 error = sysctl_handle_int(oidp, &value, 0, req); 4035 if (error || req->newptr == NULL) 4036 return (error); 4037 if (value < low || value > high) 4038 return (EINVAL); 4039 *(int *)arg1 = value; 4040 4041 return (0); 4042 } 4043 4044 static int 4045 sysctl_hw_re_int_mod(SYSCTL_HANDLER_ARGS) 4046 { 4047 4048 return (sysctl_int_range(oidp, arg1, arg2, req, RL_TIMER_MIN, 4049 RL_TIMER_MAX)); 4050 } 4051