1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 1997, 1998-2003 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 /* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44 /* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111 #ifdef HAVE_KERNEL_OPTION_HEADERS 112 #include "opt_device_polling.h" 113 #endif 114 115 #include <sys/param.h> 116 #include <sys/endian.h> 117 #include <sys/systm.h> 118 #include <sys/sockio.h> 119 #include <sys/mbuf.h> 120 #include <sys/malloc.h> 121 #include <sys/module.h> 122 #include <sys/kernel.h> 123 #include <sys/socket.h> 124 #include <sys/lock.h> 125 #include <sys/mutex.h> 126 #include <sys/sysctl.h> 127 #include <sys/taskqueue.h> 128 129 #include <net/debugnet.h> 130 #include <net/if.h> 131 #include <net/if_var.h> 132 #include <net/if_arp.h> 133 #include <net/ethernet.h> 134 #include <net/if_dl.h> 135 #include <net/if_media.h> 136 #include <net/if_types.h> 137 #include <net/if_vlan_var.h> 138 139 #include <net/bpf.h> 140 141 #include <machine/bus.h> 142 #include <machine/resource.h> 143 #include <sys/bus.h> 144 #include <sys/rman.h> 145 146 #include <dev/mii/mii.h> 147 #include <dev/mii/miivar.h> 148 149 #include <dev/pci/pcireg.h> 150 #include <dev/pci/pcivar.h> 151 152 #include <dev/rl/if_rlreg.h> 153 154 MODULE_DEPEND(re, pci, 1, 1, 1); 155 MODULE_DEPEND(re, ether, 1, 1, 1); 156 MODULE_DEPEND(re, miibus, 1, 1, 1); 157 158 /* "device miibus" required. See GENERIC if you get errors here. */ 159 #include "miibus_if.h" 160 161 /* Tunables. */ 162 static int intr_filter = 0; 163 TUNABLE_INT("hw.re.intr_filter", &intr_filter); 164 static int msi_disable = 0; 165 TUNABLE_INT("hw.re.msi_disable", &msi_disable); 166 static int msix_disable = 0; 167 TUNABLE_INT("hw.re.msix_disable", &msix_disable); 168 static int prefer_iomap = 0; 169 TUNABLE_INT("hw.re.prefer_iomap", &prefer_iomap); 170 171 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 172 173 /* 174 * Various supported device vendors/types and their names. 175 */ 176 static const struct rl_type re_devs[] = { 177 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0, 178 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 179 { DLINK_VENDORID, DLINK_DEVICEID_530T_REVC, 0, 180 "D-Link DGE-530(T) Gigabit Ethernet Adapter" }, 181 { RT_VENDORID, RT_DEVICEID_2600, 0, 182 "RealTek Killer E2600 Gigabit Ethernet Controller" }, 183 { RT_VENDORID, RT_DEVICEID_8139, 0, 184 "RealTek 8139C+ 10/100BaseTX" }, 185 { RT_VENDORID, RT_DEVICEID_8101E, 0, 186 "RealTek 810xE PCIe 10/100baseTX" }, 187 { RT_VENDORID, RT_DEVICEID_8168, 0, 188 "RealTek 8168/8111 B/C/CP/D/DP/E/F/G PCIe Gigabit Ethernet" }, 189 { RT_VENDORID, RT_DEVICEID_8161, 0, 190 "RealTek 8168 Gigabit Ethernet" }, 191 { NCUBE_VENDORID, RT_DEVICEID_8168, 0, 192 "TP-Link TG-3468 v2 (RTL8168) Gigabit Ethernet" }, 193 { RT_VENDORID, RT_DEVICEID_8169, 0, 194 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" }, 195 { RT_VENDORID, RT_DEVICEID_8169SC, 0, 196 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 197 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0, 198 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 199 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0, 200 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 201 { USR_VENDORID, USR_DEVICEID_997902, 0, 202 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 203 }; 204 205 static const struct rl_hwrev re_hwrevs[] = { 206 { RL_HWREV_8139, RL_8139, "", RL_MTU }, 207 { RL_HWREV_8139A, RL_8139, "A", RL_MTU }, 208 { RL_HWREV_8139AG, RL_8139, "A-G", RL_MTU }, 209 { RL_HWREV_8139B, RL_8139, "B", RL_MTU }, 210 { RL_HWREV_8130, RL_8139, "8130", RL_MTU }, 211 { RL_HWREV_8139C, RL_8139, "C", RL_MTU }, 212 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C", RL_MTU }, 213 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+", RL_MTU }, 214 { RL_HWREV_8168B_SPIN1, RL_8169, "8168", RL_JUMBO_MTU }, 215 { RL_HWREV_8169, RL_8169, "8169", RL_JUMBO_MTU }, 216 { RL_HWREV_8169S, RL_8169, "8169S", RL_JUMBO_MTU }, 217 { RL_HWREV_8110S, RL_8169, "8110S", RL_JUMBO_MTU }, 218 { RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB", RL_JUMBO_MTU }, 219 { RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU }, 220 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL", RL_JUMBO_MTU }, 221 { RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU }, 222 { RL_HWREV_8100, RL_8139, "8100", RL_MTU }, 223 { RL_HWREV_8101, RL_8139, "8101", RL_MTU }, 224 { RL_HWREV_8100E, RL_8169, "8100E", RL_MTU }, 225 { RL_HWREV_8101E, RL_8169, "8101E", RL_MTU }, 226 { RL_HWREV_8102E, RL_8169, "8102E", RL_MTU }, 227 { RL_HWREV_8102EL, RL_8169, "8102EL", RL_MTU }, 228 { RL_HWREV_8102EL_SPIN1, RL_8169, "8102EL", RL_MTU }, 229 { RL_HWREV_8103E, RL_8169, "8103E", RL_MTU }, 230 { RL_HWREV_8401E, RL_8169, "8401E", RL_MTU }, 231 { RL_HWREV_8402, RL_8169, "8402", RL_MTU }, 232 { RL_HWREV_8105E, RL_8169, "8105E", RL_MTU }, 233 { RL_HWREV_8105E_SPIN1, RL_8169, "8105E", RL_MTU }, 234 { RL_HWREV_8106E, RL_8169, "8106E", RL_MTU }, 235 { RL_HWREV_8168B_SPIN2, RL_8169, "8168", RL_JUMBO_MTU }, 236 { RL_HWREV_8168B_SPIN3, RL_8169, "8168", RL_JUMBO_MTU }, 237 { RL_HWREV_8168C, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K }, 238 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K }, 239 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP", RL_JUMBO_MTU_6K }, 240 { RL_HWREV_8168D, RL_8169, "8168D/8111D", RL_JUMBO_MTU_9K }, 241 { RL_HWREV_8168DP, RL_8169, "8168DP/8111DP", RL_JUMBO_MTU_9K }, 242 { RL_HWREV_8168E, RL_8169, "8168E/8111E", RL_JUMBO_MTU_9K}, 243 { RL_HWREV_8168E_VL, RL_8169, "8168E/8111E-VL", RL_JUMBO_MTU_6K}, 244 { RL_HWREV_8168EP, RL_8169, "8168EP/8111EP", RL_JUMBO_MTU_9K}, 245 { RL_HWREV_8168F, RL_8169, "8168F/8111F", RL_JUMBO_MTU_9K}, 246 { RL_HWREV_8168FP, RL_8169, "8168FP/8111FP", RL_JUMBO_MTU_9K}, 247 { RL_HWREV_8168G, RL_8169, "8168G/8111G", RL_JUMBO_MTU_9K}, 248 { RL_HWREV_8168GU, RL_8169, "8168GU/8111GU", RL_JUMBO_MTU_9K}, 249 { RL_HWREV_8168H, RL_8169, "8168H/8111H", RL_JUMBO_MTU_9K}, 250 { RL_HWREV_8411, RL_8169, "8411", RL_JUMBO_MTU_9K}, 251 { RL_HWREV_8411B, RL_8169, "8411B", RL_JUMBO_MTU_9K}, 252 { 0, 0, NULL, 0 } 253 }; 254 255 static int re_probe (device_t); 256 static int re_attach (device_t); 257 static int re_detach (device_t); 258 259 static int re_encap (struct rl_softc *, struct mbuf **); 260 261 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 262 static int re_allocmem (device_t, struct rl_softc *); 263 static __inline void re_discard_rxbuf 264 (struct rl_softc *, int); 265 static int re_newbuf (struct rl_softc *, int); 266 static int re_jumbo_newbuf (struct rl_softc *, int); 267 static int re_rx_list_init (struct rl_softc *); 268 static int re_jrx_list_init (struct rl_softc *); 269 static int re_tx_list_init (struct rl_softc *); 270 #ifdef RE_FIXUP_RX 271 static __inline void re_fixup_rx 272 (struct mbuf *); 273 #endif 274 static int re_rxeof (struct rl_softc *, int *); 275 static void re_txeof (struct rl_softc *); 276 #ifdef DEVICE_POLLING 277 static int re_poll (if_t, enum poll_cmd, int); 278 static int re_poll_locked (if_t, enum poll_cmd, int); 279 #endif 280 static int re_intr (void *); 281 static void re_intr_msi (void *); 282 static void re_tick (void *); 283 static void re_int_task (void *, int); 284 static void re_start (if_t); 285 static void re_start_locked (if_t); 286 static void re_start_tx (struct rl_softc *); 287 static int re_ioctl (if_t, u_long, caddr_t); 288 static void re_init (void *); 289 static void re_init_locked (struct rl_softc *); 290 static void re_stop (struct rl_softc *); 291 static void re_watchdog (struct rl_softc *); 292 static int re_suspend (device_t); 293 static int re_resume (device_t); 294 static int re_shutdown (device_t); 295 static int re_ifmedia_upd (if_t); 296 static void re_ifmedia_sts (if_t, struct ifmediareq *); 297 298 static void re_eeprom_putbyte (struct rl_softc *, int); 299 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 300 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 301 static int re_gmii_readreg (device_t, int, int); 302 static int re_gmii_writereg (device_t, int, int, int); 303 304 static int re_miibus_readreg (device_t, int, int); 305 static int re_miibus_writereg (device_t, int, int, int); 306 static void re_miibus_statchg (device_t); 307 308 static void re_set_jumbo (struct rl_softc *, int); 309 static void re_set_rxmode (struct rl_softc *); 310 static void re_reset (struct rl_softc *); 311 static void re_setwol (struct rl_softc *); 312 static void re_clrwol (struct rl_softc *); 313 static void re_set_linkspeed (struct rl_softc *); 314 315 DEBUGNET_DEFINE(re); 316 317 #ifdef DEV_NETMAP /* see ixgbe.c for details */ 318 #include <dev/netmap/if_re_netmap.h> 319 MODULE_DEPEND(re, netmap, 1, 1, 1); 320 #endif /* !DEV_NETMAP */ 321 322 #ifdef RE_DIAG 323 static int re_diag (struct rl_softc *); 324 #endif 325 326 static void re_add_sysctls (struct rl_softc *); 327 static int re_sysctl_stats (SYSCTL_HANDLER_ARGS); 328 static int sysctl_int_range (SYSCTL_HANDLER_ARGS, int, int); 329 static int sysctl_hw_re_int_mod (SYSCTL_HANDLER_ARGS); 330 331 static device_method_t re_methods[] = { 332 /* Device interface */ 333 DEVMETHOD(device_probe, re_probe), 334 DEVMETHOD(device_attach, re_attach), 335 DEVMETHOD(device_detach, re_detach), 336 DEVMETHOD(device_suspend, re_suspend), 337 DEVMETHOD(device_resume, re_resume), 338 DEVMETHOD(device_shutdown, re_shutdown), 339 340 /* MII interface */ 341 DEVMETHOD(miibus_readreg, re_miibus_readreg), 342 DEVMETHOD(miibus_writereg, re_miibus_writereg), 343 DEVMETHOD(miibus_statchg, re_miibus_statchg), 344 345 DEVMETHOD_END 346 }; 347 348 static driver_t re_driver = { 349 "re", 350 re_methods, 351 sizeof(struct rl_softc) 352 }; 353 354 DRIVER_MODULE(re, pci, re_driver, 0, 0); 355 DRIVER_MODULE(miibus, re, miibus_driver, 0, 0); 356 357 #define EE_SET(x) \ 358 CSR_WRITE_1(sc, RL_EECMD, \ 359 CSR_READ_1(sc, RL_EECMD) | x) 360 361 #define EE_CLR(x) \ 362 CSR_WRITE_1(sc, RL_EECMD, \ 363 CSR_READ_1(sc, RL_EECMD) & ~x) 364 365 /* 366 * Send a read command and address to the EEPROM, check for ACK. 367 */ 368 static void 369 re_eeprom_putbyte(struct rl_softc *sc, int addr) 370 { 371 int d, i; 372 373 d = addr | (RL_9346_READ << sc->rl_eewidth); 374 375 /* 376 * Feed in each bit and strobe the clock. 377 */ 378 379 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 380 if (d & i) { 381 EE_SET(RL_EE_DATAIN); 382 } else { 383 EE_CLR(RL_EE_DATAIN); 384 } 385 DELAY(100); 386 EE_SET(RL_EE_CLK); 387 DELAY(150); 388 EE_CLR(RL_EE_CLK); 389 DELAY(100); 390 } 391 } 392 393 /* 394 * Read a word of data stored in the EEPROM at address 'addr.' 395 */ 396 static void 397 re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest) 398 { 399 int i; 400 u_int16_t word = 0; 401 402 /* 403 * Send address of word we want to read. 404 */ 405 re_eeprom_putbyte(sc, addr); 406 407 /* 408 * Start reading bits from EEPROM. 409 */ 410 for (i = 0x8000; i; i >>= 1) { 411 EE_SET(RL_EE_CLK); 412 DELAY(100); 413 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 414 word |= i; 415 EE_CLR(RL_EE_CLK); 416 DELAY(100); 417 } 418 419 *dest = word; 420 } 421 422 /* 423 * Read a sequence of words from the EEPROM. 424 */ 425 static void 426 re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt) 427 { 428 int i; 429 u_int16_t word = 0, *ptr; 430 431 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 432 433 DELAY(100); 434 435 for (i = 0; i < cnt; i++) { 436 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 437 re_eeprom_getword(sc, off + i, &word); 438 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 439 ptr = (u_int16_t *)(dest + (i * 2)); 440 *ptr = word; 441 } 442 443 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 444 } 445 446 static int 447 re_gmii_readreg(device_t dev, int phy, int reg) 448 { 449 struct rl_softc *sc; 450 u_int32_t rval; 451 int i; 452 453 sc = device_get_softc(dev); 454 455 /* Let the rgephy driver read the GMEDIASTAT register */ 456 457 if (reg == RL_GMEDIASTAT) { 458 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 459 return (rval); 460 } 461 462 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 463 464 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 465 rval = CSR_READ_4(sc, RL_PHYAR); 466 if (rval & RL_PHYAR_BUSY) 467 break; 468 DELAY(25); 469 } 470 471 if (i == RL_PHY_TIMEOUT) { 472 device_printf(sc->rl_dev, "PHY read failed\n"); 473 return (0); 474 } 475 476 /* 477 * Controller requires a 20us delay to process next MDIO request. 478 */ 479 DELAY(20); 480 481 return (rval & RL_PHYAR_PHYDATA); 482 } 483 484 static int 485 re_gmii_writereg(device_t dev, int phy, int reg, int data) 486 { 487 struct rl_softc *sc; 488 u_int32_t rval; 489 int i; 490 491 sc = device_get_softc(dev); 492 493 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 494 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 495 496 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 497 rval = CSR_READ_4(sc, RL_PHYAR); 498 if (!(rval & RL_PHYAR_BUSY)) 499 break; 500 DELAY(25); 501 } 502 503 if (i == RL_PHY_TIMEOUT) { 504 device_printf(sc->rl_dev, "PHY write failed\n"); 505 return (0); 506 } 507 508 /* 509 * Controller requires a 20us delay to process next MDIO request. 510 */ 511 DELAY(20); 512 513 return (0); 514 } 515 516 static int 517 re_miibus_readreg(device_t dev, int phy, int reg) 518 { 519 struct rl_softc *sc; 520 u_int16_t rval = 0; 521 u_int16_t re8139_reg = 0; 522 523 sc = device_get_softc(dev); 524 525 if (sc->rl_type == RL_8169) { 526 rval = re_gmii_readreg(dev, phy, reg); 527 return (rval); 528 } 529 530 switch (reg) { 531 case MII_BMCR: 532 re8139_reg = RL_BMCR; 533 break; 534 case MII_BMSR: 535 re8139_reg = RL_BMSR; 536 break; 537 case MII_ANAR: 538 re8139_reg = RL_ANAR; 539 break; 540 case MII_ANER: 541 re8139_reg = RL_ANER; 542 break; 543 case MII_ANLPAR: 544 re8139_reg = RL_LPAR; 545 break; 546 case MII_PHYIDR1: 547 case MII_PHYIDR2: 548 return (0); 549 /* 550 * Allow the rlphy driver to read the media status 551 * register. If we have a link partner which does not 552 * support NWAY, this is the register which will tell 553 * us the results of parallel detection. 554 */ 555 case RL_MEDIASTAT: 556 rval = CSR_READ_1(sc, RL_MEDIASTAT); 557 return (rval); 558 default: 559 device_printf(sc->rl_dev, "bad phy register\n"); 560 return (0); 561 } 562 rval = CSR_READ_2(sc, re8139_reg); 563 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 564 /* 8139C+ has different bit layout. */ 565 rval &= ~(BMCR_LOOP | BMCR_ISO); 566 } 567 return (rval); 568 } 569 570 static int 571 re_miibus_writereg(device_t dev, int phy, int reg, int data) 572 { 573 struct rl_softc *sc; 574 u_int16_t re8139_reg = 0; 575 int rval = 0; 576 577 sc = device_get_softc(dev); 578 579 if (sc->rl_type == RL_8169) { 580 rval = re_gmii_writereg(dev, phy, reg, data); 581 return (rval); 582 } 583 584 switch (reg) { 585 case MII_BMCR: 586 re8139_reg = RL_BMCR; 587 if (sc->rl_type == RL_8139CPLUS) { 588 /* 8139C+ has different bit layout. */ 589 data &= ~(BMCR_LOOP | BMCR_ISO); 590 } 591 break; 592 case MII_BMSR: 593 re8139_reg = RL_BMSR; 594 break; 595 case MII_ANAR: 596 re8139_reg = RL_ANAR; 597 break; 598 case MII_ANER: 599 re8139_reg = RL_ANER; 600 break; 601 case MII_ANLPAR: 602 re8139_reg = RL_LPAR; 603 break; 604 case MII_PHYIDR1: 605 case MII_PHYIDR2: 606 return (0); 607 break; 608 default: 609 device_printf(sc->rl_dev, "bad phy register\n"); 610 return (0); 611 } 612 CSR_WRITE_2(sc, re8139_reg, data); 613 return (0); 614 } 615 616 static void 617 re_miibus_statchg(device_t dev) 618 { 619 struct rl_softc *sc; 620 if_t ifp; 621 struct mii_data *mii; 622 623 sc = device_get_softc(dev); 624 mii = device_get_softc(sc->rl_miibus); 625 ifp = sc->rl_ifp; 626 if (mii == NULL || ifp == NULL || 627 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 628 return; 629 630 sc->rl_flags &= ~RL_FLAG_LINK; 631 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 632 (IFM_ACTIVE | IFM_AVALID)) { 633 switch (IFM_SUBTYPE(mii->mii_media_active)) { 634 case IFM_10_T: 635 case IFM_100_TX: 636 sc->rl_flags |= RL_FLAG_LINK; 637 break; 638 case IFM_1000_T: 639 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0) 640 break; 641 sc->rl_flags |= RL_FLAG_LINK; 642 break; 643 default: 644 break; 645 } 646 } 647 /* 648 * RealTek controllers do not provide any interface to the RX/TX 649 * MACs for resolved speed, duplex and flow-control parameters. 650 */ 651 } 652 653 static u_int 654 re_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 655 { 656 uint32_t h, *hashes = arg; 657 658 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26; 659 if (h < 32) 660 hashes[0] |= (1 << h); 661 else 662 hashes[1] |= (1 << (h - 32)); 663 664 return (1); 665 } 666 667 /* 668 * Set the RX configuration and 64-bit multicast hash filter. 669 */ 670 static void 671 re_set_rxmode(struct rl_softc *sc) 672 { 673 if_t ifp; 674 uint32_t h, hashes[2] = { 0, 0 }; 675 uint32_t rxfilt; 676 677 RL_LOCK_ASSERT(sc); 678 679 ifp = sc->rl_ifp; 680 681 rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD; 682 if ((sc->rl_flags & RL_FLAG_EARLYOFF) != 0) 683 rxfilt |= RL_RXCFG_EARLYOFF; 684 else if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0) 685 rxfilt |= RL_RXCFG_EARLYOFFV2; 686 687 if (if_getflags(ifp) & (IFF_ALLMULTI | IFF_PROMISC)) { 688 if (if_getflags(ifp) & IFF_PROMISC) 689 rxfilt |= RL_RXCFG_RX_ALLPHYS; 690 /* 691 * Unlike other hardwares, we have to explicitly set 692 * RL_RXCFG_RX_MULTI to receive multicast frames in 693 * promiscuous mode. 694 */ 695 rxfilt |= RL_RXCFG_RX_MULTI; 696 hashes[0] = hashes[1] = 0xffffffff; 697 goto done; 698 } 699 700 if_foreach_llmaddr(ifp, re_hash_maddr, hashes); 701 702 if (hashes[0] != 0 || hashes[1] != 0) { 703 /* 704 * For some unfathomable reason, RealTek decided to 705 * reverse the order of the multicast hash registers 706 * in the PCI Express parts. This means we have to 707 * write the hash pattern in reverse order for those 708 * devices. 709 */ 710 if ((sc->rl_flags & RL_FLAG_PCIE) != 0) { 711 h = bswap32(hashes[0]); 712 hashes[0] = bswap32(hashes[1]); 713 hashes[1] = h; 714 } 715 rxfilt |= RL_RXCFG_RX_MULTI; 716 } 717 718 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168F) { 719 /* Disable multicast filtering due to silicon bug. */ 720 hashes[0] = 0xffffffff; 721 hashes[1] = 0xffffffff; 722 } 723 724 done: 725 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 726 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 727 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 728 } 729 730 static void 731 re_reset(struct rl_softc *sc) 732 { 733 int i; 734 735 RL_LOCK_ASSERT(sc); 736 737 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 738 739 for (i = 0; i < RL_TIMEOUT; i++) { 740 DELAY(10); 741 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 742 break; 743 } 744 if (i == RL_TIMEOUT) 745 device_printf(sc->rl_dev, "reset never completed!\n"); 746 747 if ((sc->rl_flags & RL_FLAG_MACRESET) != 0) 748 CSR_WRITE_1(sc, 0x82, 1); 749 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169S) 750 re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0); 751 } 752 753 #ifdef RE_DIAG 754 755 /* 756 * The following routine is designed to test for a defect on some 757 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 758 * lines connected to the bus, however for a 32-bit only card, they 759 * should be pulled high. The result of this defect is that the 760 * NIC will not work right if you plug it into a 64-bit slot: DMA 761 * operations will be done with 64-bit transfers, which will fail 762 * because the 64-bit data lines aren't connected. 763 * 764 * There's no way to work around this (short of talking a soldering 765 * iron to the board), however we can detect it. The method we use 766 * here is to put the NIC into digital loopback mode, set the receiver 767 * to promiscuous mode, and then try to send a frame. We then compare 768 * the frame data we sent to what was received. If the data matches, 769 * then the NIC is working correctly, otherwise we know the user has 770 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 771 * slot. In the latter case, there's no way the NIC can work correctly, 772 * so we print out a message on the console and abort the device attach. 773 */ 774 775 static int 776 re_diag(struct rl_softc *sc) 777 { 778 if_t ifp = sc->rl_ifp; 779 struct mbuf *m0; 780 struct ether_header *eh; 781 struct rl_desc *cur_rx; 782 u_int16_t status; 783 u_int32_t rxstat; 784 int total_len, i, error = 0, phyaddr; 785 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 786 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 787 788 /* Allocate a single mbuf */ 789 MGETHDR(m0, M_NOWAIT, MT_DATA); 790 if (m0 == NULL) 791 return (ENOBUFS); 792 793 RL_LOCK(sc); 794 795 /* 796 * Initialize the NIC in test mode. This sets the chip up 797 * so that it can send and receive frames, but performs the 798 * following special functions: 799 * - Puts receiver in promiscuous mode 800 * - Enables digital loopback mode 801 * - Leaves interrupts turned off 802 */ 803 804 if_setflagbit(ifp, IFF_PROMISC, 0); 805 sc->rl_testmode = 1; 806 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 807 re_init_locked(sc); 808 sc->rl_flags |= RL_FLAG_LINK; 809 if (sc->rl_type == RL_8169) 810 phyaddr = 1; 811 else 812 phyaddr = 0; 813 814 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 815 for (i = 0; i < RL_TIMEOUT; i++) { 816 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 817 if (!(status & BMCR_RESET)) 818 break; 819 } 820 821 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 822 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 823 824 DELAY(100000); 825 826 /* Put some data in the mbuf */ 827 828 eh = mtod(m0, struct ether_header *); 829 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 830 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 831 eh->ether_type = htons(ETHERTYPE_IP); 832 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 833 834 /* 835 * Queue the packet, start transmission. 836 * Note: IF_HANDOFF() ultimately calls re_start() for us. 837 */ 838 839 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 840 RL_UNLOCK(sc); 841 /* XXX: re_diag must not be called when in ALTQ mode */ 842 if_handoff(ifp, m0, ifp); 843 RL_LOCK(sc); 844 m0 = NULL; 845 846 /* Wait for it to propagate through the chip */ 847 848 DELAY(100000); 849 for (i = 0; i < RL_TIMEOUT; i++) { 850 status = CSR_READ_2(sc, RL_ISR); 851 CSR_WRITE_2(sc, RL_ISR, status); 852 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 853 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 854 break; 855 DELAY(10); 856 } 857 858 if (i == RL_TIMEOUT) { 859 device_printf(sc->rl_dev, 860 "diagnostic failed, failed to receive packet in" 861 " loopback mode\n"); 862 error = EIO; 863 goto done; 864 } 865 866 /* 867 * The packet should have been dumped into the first 868 * entry in the RX DMA ring. Grab it from there. 869 */ 870 871 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 872 sc->rl_ldata.rl_rx_list_map, 873 BUS_DMASYNC_POSTREAD); 874 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 875 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 876 BUS_DMASYNC_POSTREAD); 877 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 878 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 879 880 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 881 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 882 eh = mtod(m0, struct ether_header *); 883 884 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 885 total_len = RL_RXBYTES(cur_rx); 886 rxstat = le32toh(cur_rx->rl_cmdstat); 887 888 if (total_len != ETHER_MIN_LEN) { 889 device_printf(sc->rl_dev, 890 "diagnostic failed, received short packet\n"); 891 error = EIO; 892 goto done; 893 } 894 895 /* Test that the received packet data matches what we sent. */ 896 897 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 898 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 899 ntohs(eh->ether_type) != ETHERTYPE_IP) { 900 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 901 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 902 dst, ":", src, ":", ETHERTYPE_IP); 903 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 904 eh->ether_dhost, ":", eh->ether_shost, ":", 905 ntohs(eh->ether_type)); 906 device_printf(sc->rl_dev, "You may have a defective 32-bit " 907 "NIC plugged into a 64-bit PCI slot.\n"); 908 device_printf(sc->rl_dev, "Please re-install the NIC in a " 909 "32-bit slot for proper operation.\n"); 910 device_printf(sc->rl_dev, "Read the re(4) man page for more " 911 "details.\n"); 912 error = EIO; 913 } 914 915 done: 916 /* Turn interface off, release resources */ 917 918 sc->rl_testmode = 0; 919 sc->rl_flags &= ~RL_FLAG_LINK; 920 if_setflagbit(ifp, 0, IFF_PROMISC); 921 re_stop(sc); 922 if (m0 != NULL) 923 m_freem(m0); 924 925 RL_UNLOCK(sc); 926 927 return (error); 928 } 929 930 #endif 931 932 /* 933 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 934 * IDs against our list and return a device name if we find a match. 935 */ 936 static int 937 re_probe(device_t dev) 938 { 939 const struct rl_type *t; 940 uint16_t devid, vendor; 941 uint16_t revid, sdevid; 942 int i; 943 944 vendor = pci_get_vendor(dev); 945 devid = pci_get_device(dev); 946 revid = pci_get_revid(dev); 947 sdevid = pci_get_subdevice(dev); 948 949 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 950 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 951 /* 952 * Only attach to rev. 3 of the Linksys EG1032 adapter. 953 * Rev. 2 is supported by sk(4). 954 */ 955 return (ENXIO); 956 } 957 } 958 959 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 960 if (revid != 0x20) { 961 /* 8139, let rl(4) take care of this device. */ 962 return (ENXIO); 963 } 964 } 965 966 t = re_devs; 967 for (i = 0; i < nitems(re_devs); i++, t++) { 968 if (vendor == t->rl_vid && devid == t->rl_did) { 969 device_set_desc(dev, t->rl_name); 970 return (BUS_PROBE_DEFAULT); 971 } 972 } 973 974 return (ENXIO); 975 } 976 977 /* 978 * Map a single buffer address. 979 */ 980 981 static void 982 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 983 { 984 bus_addr_t *addr; 985 986 if (error) 987 return; 988 989 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 990 addr = arg; 991 *addr = segs->ds_addr; 992 } 993 994 static int 995 re_allocmem(device_t dev, struct rl_softc *sc) 996 { 997 bus_addr_t lowaddr; 998 bus_size_t rx_list_size, tx_list_size; 999 int error; 1000 int i; 1001 1002 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 1003 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 1004 1005 /* 1006 * Allocate the parent bus DMA tag appropriate for PCI. 1007 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD 1008 * register should be set. However some RealTek chips are known 1009 * to be buggy on DAC handling, therefore disable DAC by limiting 1010 * DMA address space to 32bit. PCIe variants of RealTek chips 1011 * may not have the limitation. 1012 */ 1013 lowaddr = BUS_SPACE_MAXADDR; 1014 if ((sc->rl_flags & RL_FLAG_PCIE) == 0) 1015 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1016 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 1017 lowaddr, BUS_SPACE_MAXADDR, NULL, NULL, 1018 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 1019 NULL, NULL, &sc->rl_parent_tag); 1020 if (error) { 1021 device_printf(dev, "could not allocate parent DMA tag\n"); 1022 return (error); 1023 } 1024 1025 /* 1026 * Allocate map for TX mbufs. 1027 */ 1028 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 1029 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1030 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 1031 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 1032 if (error) { 1033 device_printf(dev, "could not allocate TX DMA tag\n"); 1034 return (error); 1035 } 1036 1037 /* 1038 * Allocate map for RX mbufs. 1039 */ 1040 1041 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 1042 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 1043 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1044 MJUM9BYTES, 1, MJUM9BYTES, 0, NULL, NULL, 1045 &sc->rl_ldata.rl_jrx_mtag); 1046 if (error) { 1047 device_printf(dev, 1048 "could not allocate jumbo RX DMA tag\n"); 1049 return (error); 1050 } 1051 } 1052 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 1053 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1054 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 1055 if (error) { 1056 device_printf(dev, "could not allocate RX DMA tag\n"); 1057 return (error); 1058 } 1059 1060 /* 1061 * Allocate map for TX descriptor list. 1062 */ 1063 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1064 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1065 NULL, tx_list_size, 1, tx_list_size, 0, 1066 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1067 if (error) { 1068 device_printf(dev, "could not allocate TX DMA ring tag\n"); 1069 return (error); 1070 } 1071 1072 /* Allocate DMA'able memory for the TX ring */ 1073 1074 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1075 (void **)&sc->rl_ldata.rl_tx_list, 1076 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1077 &sc->rl_ldata.rl_tx_list_map); 1078 if (error) { 1079 device_printf(dev, "could not allocate TX DMA ring\n"); 1080 return (error); 1081 } 1082 1083 /* Load the map for the TX ring. */ 1084 1085 sc->rl_ldata.rl_tx_list_addr = 0; 1086 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1087 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1088 tx_list_size, re_dma_map_addr, 1089 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1090 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 1091 device_printf(dev, "could not load TX DMA ring\n"); 1092 return (ENOMEM); 1093 } 1094 1095 /* Create DMA maps for TX buffers */ 1096 1097 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1098 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1099 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1100 if (error) { 1101 device_printf(dev, "could not create DMA map for TX\n"); 1102 return (error); 1103 } 1104 } 1105 1106 /* 1107 * Allocate map for RX descriptor list. 1108 */ 1109 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1110 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1111 NULL, rx_list_size, 1, rx_list_size, 0, 1112 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1113 if (error) { 1114 device_printf(dev, "could not create RX DMA ring tag\n"); 1115 return (error); 1116 } 1117 1118 /* Allocate DMA'able memory for the RX ring */ 1119 1120 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1121 (void **)&sc->rl_ldata.rl_rx_list, 1122 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1123 &sc->rl_ldata.rl_rx_list_map); 1124 if (error) { 1125 device_printf(dev, "could not allocate RX DMA ring\n"); 1126 return (error); 1127 } 1128 1129 /* Load the map for the RX ring. */ 1130 1131 sc->rl_ldata.rl_rx_list_addr = 0; 1132 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1133 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1134 rx_list_size, re_dma_map_addr, 1135 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1136 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1137 device_printf(dev, "could not load RX DMA ring\n"); 1138 return (ENOMEM); 1139 } 1140 1141 /* Create DMA maps for RX buffers */ 1142 1143 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 1144 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0, 1145 &sc->rl_ldata.rl_jrx_sparemap); 1146 if (error) { 1147 device_printf(dev, 1148 "could not create spare DMA map for jumbo RX\n"); 1149 return (error); 1150 } 1151 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1152 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0, 1153 &sc->rl_ldata.rl_jrx_desc[i].rx_dmamap); 1154 if (error) { 1155 device_printf(dev, 1156 "could not create DMA map for jumbo RX\n"); 1157 return (error); 1158 } 1159 } 1160 } 1161 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1162 &sc->rl_ldata.rl_rx_sparemap); 1163 if (error) { 1164 device_printf(dev, "could not create spare DMA map for RX\n"); 1165 return (error); 1166 } 1167 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1168 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1169 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1170 if (error) { 1171 device_printf(dev, "could not create DMA map for RX\n"); 1172 return (error); 1173 } 1174 } 1175 1176 /* Create DMA map for statistics. */ 1177 error = bus_dma_tag_create(sc->rl_parent_tag, RL_DUMP_ALIGN, 0, 1178 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1179 sizeof(struct rl_stats), 1, sizeof(struct rl_stats), 0, NULL, NULL, 1180 &sc->rl_ldata.rl_stag); 1181 if (error) { 1182 device_printf(dev, "could not create statistics DMA tag\n"); 1183 return (error); 1184 } 1185 /* Allocate DMA'able memory for statistics. */ 1186 error = bus_dmamem_alloc(sc->rl_ldata.rl_stag, 1187 (void **)&sc->rl_ldata.rl_stats, 1188 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1189 &sc->rl_ldata.rl_smap); 1190 if (error) { 1191 device_printf(dev, 1192 "could not allocate statistics DMA memory\n"); 1193 return (error); 1194 } 1195 /* Load the map for statistics. */ 1196 sc->rl_ldata.rl_stats_addr = 0; 1197 error = bus_dmamap_load(sc->rl_ldata.rl_stag, sc->rl_ldata.rl_smap, 1198 sc->rl_ldata.rl_stats, sizeof(struct rl_stats), re_dma_map_addr, 1199 &sc->rl_ldata.rl_stats_addr, BUS_DMA_NOWAIT); 1200 if (error != 0 || sc->rl_ldata.rl_stats_addr == 0) { 1201 device_printf(dev, "could not load statistics DMA memory\n"); 1202 return (ENOMEM); 1203 } 1204 1205 return (0); 1206 } 1207 1208 /* 1209 * Attach the interface. Allocate softc structures, do ifmedia 1210 * setup and ethernet/BPF attach. 1211 */ 1212 static int 1213 re_attach(device_t dev) 1214 { 1215 u_char eaddr[ETHER_ADDR_LEN]; 1216 u_int16_t as[ETHER_ADDR_LEN / 2]; 1217 struct rl_softc *sc; 1218 if_t ifp; 1219 const struct rl_hwrev *hw_rev; 1220 int capmask, error = 0, hwrev, i, msic, msixc, 1221 phy, reg, rid; 1222 u_int32_t cap, ctl; 1223 u_int16_t devid, re_did = 0; 1224 uint8_t cfg; 1225 1226 sc = device_get_softc(dev); 1227 sc->rl_dev = dev; 1228 1229 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1230 MTX_DEF); 1231 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1232 1233 /* 1234 * Map control/status registers. 1235 */ 1236 pci_enable_busmaster(dev); 1237 1238 devid = pci_get_device(dev); 1239 /* 1240 * Prefer memory space register mapping over IO space. 1241 * Because RTL8169SC does not seem to work when memory mapping 1242 * is used always activate io mapping. 1243 */ 1244 if (devid == RT_DEVICEID_8169SC) 1245 prefer_iomap = 1; 1246 if (prefer_iomap == 0) { 1247 sc->rl_res_id = PCIR_BAR(1); 1248 sc->rl_res_type = SYS_RES_MEMORY; 1249 /* RTL8168/8101E seems to use different BARs. */ 1250 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E) 1251 sc->rl_res_id = PCIR_BAR(2); 1252 } else { 1253 sc->rl_res_id = PCIR_BAR(0); 1254 sc->rl_res_type = SYS_RES_IOPORT; 1255 } 1256 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1257 &sc->rl_res_id, RF_ACTIVE); 1258 if (sc->rl_res == NULL && prefer_iomap == 0) { 1259 sc->rl_res_id = PCIR_BAR(0); 1260 sc->rl_res_type = SYS_RES_IOPORT; 1261 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1262 &sc->rl_res_id, RF_ACTIVE); 1263 } 1264 if (sc->rl_res == NULL) { 1265 device_printf(dev, "couldn't map ports/memory\n"); 1266 error = ENXIO; 1267 goto fail; 1268 } 1269 1270 sc->rl_btag = rman_get_bustag(sc->rl_res); 1271 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1272 1273 msic = pci_msi_count(dev); 1274 msixc = pci_msix_count(dev); 1275 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 1276 sc->rl_flags |= RL_FLAG_PCIE; 1277 sc->rl_expcap = reg; 1278 } 1279 if (bootverbose) { 1280 device_printf(dev, "MSI count : %d\n", msic); 1281 device_printf(dev, "MSI-X count : %d\n", msixc); 1282 } 1283 if (msix_disable > 0) 1284 msixc = 0; 1285 if (msi_disable > 0) 1286 msic = 0; 1287 /* Prefer MSI-X to MSI. */ 1288 if (msixc > 0) { 1289 msixc = RL_MSI_MESSAGES; 1290 rid = PCIR_BAR(4); 1291 sc->rl_res_pba = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1292 &rid, RF_ACTIVE); 1293 if (sc->rl_res_pba == NULL) { 1294 device_printf(sc->rl_dev, 1295 "could not allocate MSI-X PBA resource\n"); 1296 } 1297 if (sc->rl_res_pba != NULL && 1298 pci_alloc_msix(dev, &msixc) == 0) { 1299 if (msixc == RL_MSI_MESSAGES) { 1300 device_printf(dev, "Using %d MSI-X message\n", 1301 msixc); 1302 sc->rl_flags |= RL_FLAG_MSIX; 1303 } else 1304 pci_release_msi(dev); 1305 } 1306 if ((sc->rl_flags & RL_FLAG_MSIX) == 0) { 1307 if (sc->rl_res_pba != NULL) 1308 bus_release_resource(dev, SYS_RES_MEMORY, rid, 1309 sc->rl_res_pba); 1310 sc->rl_res_pba = NULL; 1311 msixc = 0; 1312 } 1313 } 1314 /* Prefer MSI to INTx. */ 1315 if (msixc == 0 && msic > 0) { 1316 msic = RL_MSI_MESSAGES; 1317 if (pci_alloc_msi(dev, &msic) == 0) { 1318 if (msic == RL_MSI_MESSAGES) { 1319 device_printf(dev, "Using %d MSI message\n", 1320 msic); 1321 sc->rl_flags |= RL_FLAG_MSI; 1322 /* Explicitly set MSI enable bit. */ 1323 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1324 cfg = CSR_READ_1(sc, RL_CFG2); 1325 cfg |= RL_CFG2_MSI; 1326 CSR_WRITE_1(sc, RL_CFG2, cfg); 1327 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1328 } else 1329 pci_release_msi(dev); 1330 } 1331 if ((sc->rl_flags & RL_FLAG_MSI) == 0) 1332 msic = 0; 1333 } 1334 1335 /* Allocate interrupt */ 1336 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) { 1337 rid = 0; 1338 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1339 RF_SHAREABLE | RF_ACTIVE); 1340 if (sc->rl_irq[0] == NULL) { 1341 device_printf(dev, "couldn't allocate IRQ resources\n"); 1342 error = ENXIO; 1343 goto fail; 1344 } 1345 } else { 1346 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1347 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1348 SYS_RES_IRQ, &rid, RF_ACTIVE); 1349 if (sc->rl_irq[i] == NULL) { 1350 device_printf(dev, 1351 "couldn't allocate IRQ resources for " 1352 "message %d\n", rid); 1353 error = ENXIO; 1354 goto fail; 1355 } 1356 } 1357 } 1358 1359 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1360 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1361 cfg = CSR_READ_1(sc, RL_CFG2); 1362 if ((cfg & RL_CFG2_MSI) != 0) { 1363 device_printf(dev, "turning off MSI enable bit.\n"); 1364 cfg &= ~RL_CFG2_MSI; 1365 CSR_WRITE_1(sc, RL_CFG2, cfg); 1366 } 1367 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1368 } 1369 1370 /* Disable ASPM L0S/L1 and CLKREQ. */ 1371 if (sc->rl_expcap != 0) { 1372 cap = pci_read_config(dev, sc->rl_expcap + 1373 PCIER_LINK_CAP, 2); 1374 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { 1375 ctl = pci_read_config(dev, sc->rl_expcap + 1376 PCIER_LINK_CTL, 2); 1377 if ((ctl & (PCIEM_LINK_CTL_ECPM | 1378 PCIEM_LINK_CTL_ASPMC))!= 0) { 1379 ctl &= ~(PCIEM_LINK_CTL_ECPM | 1380 PCIEM_LINK_CTL_ASPMC); 1381 pci_write_config(dev, sc->rl_expcap + 1382 PCIER_LINK_CTL, ctl, 2); 1383 device_printf(dev, "ASPM disabled\n"); 1384 } 1385 } else 1386 device_printf(dev, "no ASPM capability\n"); 1387 } 1388 1389 hw_rev = re_hwrevs; 1390 hwrev = CSR_READ_4(sc, RL_TXCFG); 1391 switch (hwrev & 0x70000000) { 1392 case 0x00000000: 1393 case 0x10000000: 1394 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000); 1395 hwrev &= (RL_TXCFG_HWREV | 0x80000000); 1396 break; 1397 default: 1398 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000); 1399 sc->rl_macrev = hwrev & 0x00700000; 1400 hwrev &= RL_TXCFG_HWREV; 1401 break; 1402 } 1403 device_printf(dev, "MAC rev. 0x%08x\n", sc->rl_macrev); 1404 while (hw_rev->rl_desc != NULL) { 1405 if (hw_rev->rl_rev == hwrev) { 1406 sc->rl_type = hw_rev->rl_type; 1407 sc->rl_hwrev = hw_rev; 1408 break; 1409 } 1410 hw_rev++; 1411 } 1412 if (hw_rev->rl_desc == NULL) { 1413 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev); 1414 error = ENXIO; 1415 goto fail; 1416 } 1417 1418 switch (hw_rev->rl_rev) { 1419 case RL_HWREV_8139CPLUS: 1420 sc->rl_flags |= RL_FLAG_FASTETHER | RL_FLAG_AUTOPAD; 1421 break; 1422 case RL_HWREV_8100E: 1423 case RL_HWREV_8101E: 1424 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_FASTETHER; 1425 break; 1426 case RL_HWREV_8102E: 1427 case RL_HWREV_8102EL: 1428 case RL_HWREV_8102EL_SPIN1: 1429 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1430 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | 1431 RL_FLAG_AUTOPAD; 1432 break; 1433 case RL_HWREV_8103E: 1434 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1435 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | 1436 RL_FLAG_AUTOPAD | RL_FLAG_MACSLEEP; 1437 break; 1438 case RL_HWREV_8401E: 1439 case RL_HWREV_8105E: 1440 case RL_HWREV_8105E_SPIN1: 1441 case RL_HWREV_8106E: 1442 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1443 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1444 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD; 1445 break; 1446 case RL_HWREV_8402: 1447 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1448 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1449 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | 1450 RL_FLAG_CMDSTOP_WAIT_TXQ; 1451 break; 1452 case RL_HWREV_8168B_SPIN1: 1453 case RL_HWREV_8168B_SPIN2: 1454 sc->rl_flags |= RL_FLAG_WOLRXENB; 1455 /* FALLTHROUGH */ 1456 case RL_HWREV_8168B_SPIN3: 1457 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT; 1458 break; 1459 case RL_HWREV_8168C_SPIN2: 1460 sc->rl_flags |= RL_FLAG_MACSLEEP; 1461 /* FALLTHROUGH */ 1462 case RL_HWREV_8168C: 1463 if (sc->rl_macrev == 0x00200000) 1464 sc->rl_flags |= RL_FLAG_MACSLEEP; 1465 /* FALLTHROUGH */ 1466 case RL_HWREV_8168CP: 1467 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1468 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1469 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK; 1470 break; 1471 case RL_HWREV_8168D: 1472 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1473 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1474 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1475 RL_FLAG_WOL_MANLINK; 1476 break; 1477 case RL_HWREV_8168DP: 1478 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1479 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_AUTOPAD | 1480 RL_FLAG_JUMBOV2 | RL_FLAG_WAIT_TXPOLL | RL_FLAG_WOL_MANLINK; 1481 break; 1482 case RL_HWREV_8168E: 1483 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1484 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1485 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1486 RL_FLAG_WOL_MANLINK; 1487 break; 1488 case RL_HWREV_8168E_VL: 1489 case RL_HWREV_8168F: 1490 sc->rl_flags |= RL_FLAG_EARLYOFF; 1491 /* FALLTHROUGH */ 1492 case RL_HWREV_8411: 1493 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1494 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1495 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1496 RL_FLAG_CMDSTOP_WAIT_TXQ | RL_FLAG_WOL_MANLINK; 1497 break; 1498 case RL_HWREV_8168EP: 1499 case RL_HWREV_8168FP: 1500 case RL_HWREV_8168G: 1501 case RL_HWREV_8411B: 1502 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1503 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1504 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1505 RL_FLAG_CMDSTOP_WAIT_TXQ | RL_FLAG_WOL_MANLINK | 1506 RL_FLAG_8168G_PLUS; 1507 break; 1508 case RL_HWREV_8168GU: 1509 case RL_HWREV_8168H: 1510 if (pci_get_device(dev) == RT_DEVICEID_8101E) { 1511 /* RTL8106E(US), RTL8107E */ 1512 sc->rl_flags |= RL_FLAG_FASTETHER; 1513 } else 1514 sc->rl_flags |= RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK; 1515 1516 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1517 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1518 RL_FLAG_AUTOPAD | RL_FLAG_CMDSTOP_WAIT_TXQ | 1519 RL_FLAG_8168G_PLUS; 1520 break; 1521 case RL_HWREV_8169_8110SB: 1522 case RL_HWREV_8169_8110SBL: 1523 case RL_HWREV_8169_8110SC: 1524 case RL_HWREV_8169_8110SCE: 1525 sc->rl_flags |= RL_FLAG_PHYWAKE; 1526 /* FALLTHROUGH */ 1527 case RL_HWREV_8169: 1528 case RL_HWREV_8169S: 1529 case RL_HWREV_8110S: 1530 sc->rl_flags |= RL_FLAG_MACRESET; 1531 break; 1532 default: 1533 break; 1534 } 1535 1536 if (sc->rl_hwrev->rl_rev == RL_HWREV_8139CPLUS) { 1537 sc->rl_cfg0 = RL_8139_CFG0; 1538 sc->rl_cfg1 = RL_8139_CFG1; 1539 sc->rl_cfg2 = 0; 1540 sc->rl_cfg3 = RL_8139_CFG3; 1541 sc->rl_cfg4 = RL_8139_CFG4; 1542 sc->rl_cfg5 = RL_8139_CFG5; 1543 } else { 1544 sc->rl_cfg0 = RL_CFG0; 1545 sc->rl_cfg1 = RL_CFG1; 1546 sc->rl_cfg2 = RL_CFG2; 1547 sc->rl_cfg3 = RL_CFG3; 1548 sc->rl_cfg4 = RL_CFG4; 1549 sc->rl_cfg5 = RL_CFG5; 1550 } 1551 1552 /* Reset the adapter. */ 1553 RL_LOCK(sc); 1554 re_reset(sc); 1555 RL_UNLOCK(sc); 1556 1557 /* Enable PME. */ 1558 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1559 cfg = CSR_READ_1(sc, sc->rl_cfg1); 1560 cfg |= RL_CFG1_PME; 1561 CSR_WRITE_1(sc, sc->rl_cfg1, cfg); 1562 cfg = CSR_READ_1(sc, sc->rl_cfg5); 1563 cfg &= RL_CFG5_PME_STS; 1564 CSR_WRITE_1(sc, sc->rl_cfg5, cfg); 1565 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1566 1567 if ((sc->rl_flags & RL_FLAG_PAR) != 0) { 1568 /* 1569 * XXX Should have a better way to extract station 1570 * address from EEPROM. 1571 */ 1572 for (i = 0; i < ETHER_ADDR_LEN; i++) 1573 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1574 } else { 1575 sc->rl_eewidth = RL_9356_ADDR_LEN; 1576 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1577 if (re_did != 0x8129) 1578 sc->rl_eewidth = RL_9346_ADDR_LEN; 1579 1580 /* 1581 * Get station address from the EEPROM. 1582 */ 1583 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1584 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1585 as[i] = le16toh(as[i]); 1586 bcopy(as, eaddr, ETHER_ADDR_LEN); 1587 } 1588 1589 if (sc->rl_type == RL_8169) { 1590 /* Set RX length mask and number of descriptors. */ 1591 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1592 sc->rl_txstart = RL_GTXSTART; 1593 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1594 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1595 } else { 1596 /* Set RX length mask and number of descriptors. */ 1597 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1598 sc->rl_txstart = RL_TXSTART; 1599 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1600 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1601 } 1602 1603 error = re_allocmem(dev, sc); 1604 if (error) 1605 goto fail; 1606 re_add_sysctls(sc); 1607 1608 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1609 1610 /* Take controller out of deep sleep mode. */ 1611 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 1612 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 1613 CSR_WRITE_1(sc, RL_GPIO, 1614 CSR_READ_1(sc, RL_GPIO) | 0x01); 1615 else 1616 CSR_WRITE_1(sc, RL_GPIO, 1617 CSR_READ_1(sc, RL_GPIO) & ~0x01); 1618 } 1619 1620 /* Take PHY out of power down mode. */ 1621 if ((sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) { 1622 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80); 1623 if (hw_rev->rl_rev == RL_HWREV_8401E) 1624 CSR_WRITE_1(sc, 0xD1, CSR_READ_1(sc, 0xD1) & ~0x08); 1625 } 1626 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) { 1627 re_gmii_writereg(dev, 1, 0x1f, 0); 1628 re_gmii_writereg(dev, 1, 0x0e, 0); 1629 } 1630 1631 if_setsoftc(ifp, sc); 1632 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1633 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 1634 if_setioctlfn(ifp, re_ioctl); 1635 if_setstartfn(ifp, re_start); 1636 /* 1637 * RTL8168/8111C generates wrong IP checksummed frame if the 1638 * packet has IP options so disable TX checksum offloading. 1639 */ 1640 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168C || 1641 sc->rl_hwrev->rl_rev == RL_HWREV_8168C_SPIN2 || 1642 sc->rl_hwrev->rl_rev == RL_HWREV_8168CP) { 1643 if_sethwassist(ifp, 0); 1644 if_setcapabilities(ifp, IFCAP_RXCSUM | IFCAP_TSO4); 1645 } else { 1646 if_sethwassist(ifp, CSUM_IP | CSUM_TCP | CSUM_UDP); 1647 if_setcapabilities(ifp, IFCAP_HWCSUM | IFCAP_TSO4); 1648 } 1649 if_sethwassistbits(ifp, CSUM_TSO, 0); 1650 if_setcapenable(ifp, if_getcapabilities(ifp)); 1651 if_setinitfn(ifp, re_init); 1652 if_setsendqlen(ifp, RL_IFQ_MAXLEN); 1653 if_setsendqready(ifp); 1654 1655 NET_TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1656 1657 #define RE_PHYAD_INTERNAL 0 1658 1659 /* Do MII setup. */ 1660 phy = RE_PHYAD_INTERNAL; 1661 if (sc->rl_type == RL_8169) 1662 phy = 1; 1663 capmask = BMSR_DEFCAPMASK; 1664 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0) 1665 capmask &= ~BMSR_EXTSTAT; 1666 error = mii_attach(dev, &sc->rl_miibus, ifp, re_ifmedia_upd, 1667 re_ifmedia_sts, capmask, phy, MII_OFFSET_ANY, MIIF_DOPAUSE); 1668 if (error != 0) { 1669 device_printf(dev, "attaching PHYs failed\n"); 1670 goto fail; 1671 } 1672 1673 /* If address was not found, create one based on the hostid and name. */ 1674 if (ETHER_IS_ZERO(eaddr)) { 1675 ether_gen_addr(ifp, (struct ether_addr *)eaddr); 1676 } 1677 1678 /* 1679 * Call MI attach routine. 1680 */ 1681 ether_ifattach(ifp, eaddr); 1682 1683 /* VLAN capability setup */ 1684 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING, 0); 1685 if (if_getcapabilities(ifp) & IFCAP_HWCSUM) 1686 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM, 0); 1687 /* Enable WOL if PM is supported. */ 1688 if (pci_find_cap(sc->rl_dev, PCIY_PMG, ®) == 0) 1689 if_setcapabilitiesbit(ifp, IFCAP_WOL, 0); 1690 if_setcapenable(ifp, if_getcapabilities(ifp)); 1691 if_setcapenablebit(ifp, 0, (IFCAP_WOL_UCAST | IFCAP_WOL_MCAST)); 1692 /* 1693 * Don't enable TSO by default. It is known to generate 1694 * corrupted TCP segments(bad TCP options) under certain 1695 * circumstances. 1696 */ 1697 if_sethwassistbits(ifp, 0, CSUM_TSO); 1698 if_setcapenablebit(ifp, 0, (IFCAP_TSO4 | IFCAP_VLAN_HWTSO)); 1699 #ifdef DEVICE_POLLING 1700 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0); 1701 #endif 1702 /* 1703 * Tell the upper layer(s) we support long frames. 1704 * Must appear after the call to ether_ifattach() because 1705 * ether_ifattach() sets ifi_hdrlen to the default value. 1706 */ 1707 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 1708 1709 #ifdef DEV_NETMAP 1710 re_netmap_attach(sc); 1711 #endif /* DEV_NETMAP */ 1712 1713 #ifdef RE_DIAG 1714 /* 1715 * Perform hardware diagnostic on the original RTL8169. 1716 * Some 32-bit cards were incorrectly wired and would 1717 * malfunction if plugged into a 64-bit slot. 1718 */ 1719 if (hwrev == RL_HWREV_8169) { 1720 error = re_diag(sc); 1721 if (error) { 1722 device_printf(dev, 1723 "attach aborted due to hardware diag failure\n"); 1724 ether_ifdetach(ifp); 1725 goto fail; 1726 } 1727 } 1728 #endif 1729 1730 #ifdef RE_TX_MODERATION 1731 intr_filter = 1; 1732 #endif 1733 /* Hook interrupt last to avoid having to lock softc */ 1734 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 && 1735 intr_filter == 0) { 1736 error = bus_setup_intr(dev, sc->rl_irq[0], 1737 INTR_TYPE_NET | INTR_MPSAFE, NULL, re_intr_msi, sc, 1738 &sc->rl_intrhand[0]); 1739 } else { 1740 error = bus_setup_intr(dev, sc->rl_irq[0], 1741 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1742 &sc->rl_intrhand[0]); 1743 } 1744 if (error) { 1745 device_printf(dev, "couldn't set up irq\n"); 1746 ether_ifdetach(ifp); 1747 goto fail; 1748 } 1749 1750 DEBUGNET_SET(ifp, re); 1751 1752 fail: 1753 if (error) 1754 re_detach(dev); 1755 1756 return (error); 1757 } 1758 1759 /* 1760 * Shutdown hardware and free up resources. This can be called any 1761 * time after the mutex has been initialized. It is called in both 1762 * the error case in attach and the normal detach case so it needs 1763 * to be careful about only freeing resources that have actually been 1764 * allocated. 1765 */ 1766 static int 1767 re_detach(device_t dev) 1768 { 1769 struct rl_softc *sc; 1770 if_t ifp; 1771 int i, rid; 1772 1773 sc = device_get_softc(dev); 1774 ifp = sc->rl_ifp; 1775 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1776 1777 /* These should only be active if attach succeeded */ 1778 if (device_is_attached(dev)) { 1779 #ifdef DEVICE_POLLING 1780 if (if_getcapenable(ifp) & IFCAP_POLLING) 1781 ether_poll_deregister(ifp); 1782 #endif 1783 RL_LOCK(sc); 1784 #if 0 1785 sc->suspended = 1; 1786 #endif 1787 re_stop(sc); 1788 RL_UNLOCK(sc); 1789 callout_drain(&sc->rl_stat_callout); 1790 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1791 /* 1792 * Force off the IFF_UP flag here, in case someone 1793 * still had a BPF descriptor attached to this 1794 * interface. If they do, ether_ifdetach() will cause 1795 * the BPF code to try and clear the promisc mode 1796 * flag, which will bubble down to re_ioctl(), 1797 * which will try to call re_init() again. This will 1798 * turn the NIC back on and restart the MII ticker, 1799 * which will panic the system when the kernel tries 1800 * to invoke the re_tick() function that isn't there 1801 * anymore. 1802 */ 1803 if_setflagbits(ifp, 0, IFF_UP); 1804 ether_ifdetach(ifp); 1805 } 1806 bus_generic_detach(dev); 1807 1808 /* 1809 * The rest is resource deallocation, so we should already be 1810 * stopped here. 1811 */ 1812 1813 if (sc->rl_intrhand[0] != NULL) { 1814 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]); 1815 sc->rl_intrhand[0] = NULL; 1816 } 1817 if (ifp != NULL) { 1818 #ifdef DEV_NETMAP 1819 netmap_detach(ifp); 1820 #endif /* DEV_NETMAP */ 1821 if_free(ifp); 1822 } 1823 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) 1824 rid = 0; 1825 else 1826 rid = 1; 1827 if (sc->rl_irq[0] != NULL) { 1828 bus_release_resource(dev, SYS_RES_IRQ, rid, sc->rl_irq[0]); 1829 sc->rl_irq[0] = NULL; 1830 } 1831 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0) 1832 pci_release_msi(dev); 1833 if (sc->rl_res_pba) { 1834 rid = PCIR_BAR(4); 1835 bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->rl_res_pba); 1836 } 1837 if (sc->rl_res) 1838 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, 1839 sc->rl_res); 1840 1841 /* Unload and free the RX DMA ring memory and map */ 1842 1843 if (sc->rl_ldata.rl_rx_list_tag) { 1844 if (sc->rl_ldata.rl_rx_list_addr) 1845 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1846 sc->rl_ldata.rl_rx_list_map); 1847 if (sc->rl_ldata.rl_rx_list) 1848 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1849 sc->rl_ldata.rl_rx_list, 1850 sc->rl_ldata.rl_rx_list_map); 1851 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1852 } 1853 1854 /* Unload and free the TX DMA ring memory and map */ 1855 1856 if (sc->rl_ldata.rl_tx_list_tag) { 1857 if (sc->rl_ldata.rl_tx_list_addr) 1858 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1859 sc->rl_ldata.rl_tx_list_map); 1860 if (sc->rl_ldata.rl_tx_list) 1861 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1862 sc->rl_ldata.rl_tx_list, 1863 sc->rl_ldata.rl_tx_list_map); 1864 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1865 } 1866 1867 /* Destroy all the RX and TX buffer maps */ 1868 1869 if (sc->rl_ldata.rl_tx_mtag) { 1870 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1871 if (sc->rl_ldata.rl_tx_desc[i].tx_dmamap) 1872 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1873 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1874 } 1875 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1876 } 1877 if (sc->rl_ldata.rl_rx_mtag) { 1878 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1879 if (sc->rl_ldata.rl_rx_desc[i].rx_dmamap) 1880 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1881 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1882 } 1883 if (sc->rl_ldata.rl_rx_sparemap) 1884 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1885 sc->rl_ldata.rl_rx_sparemap); 1886 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1887 } 1888 if (sc->rl_ldata.rl_jrx_mtag) { 1889 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1890 if (sc->rl_ldata.rl_jrx_desc[i].rx_dmamap) 1891 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag, 1892 sc->rl_ldata.rl_jrx_desc[i].rx_dmamap); 1893 } 1894 if (sc->rl_ldata.rl_jrx_sparemap) 1895 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag, 1896 sc->rl_ldata.rl_jrx_sparemap); 1897 bus_dma_tag_destroy(sc->rl_ldata.rl_jrx_mtag); 1898 } 1899 /* Unload and free the stats buffer and map */ 1900 1901 if (sc->rl_ldata.rl_stag) { 1902 if (sc->rl_ldata.rl_stats_addr) 1903 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1904 sc->rl_ldata.rl_smap); 1905 if (sc->rl_ldata.rl_stats) 1906 bus_dmamem_free(sc->rl_ldata.rl_stag, 1907 sc->rl_ldata.rl_stats, sc->rl_ldata.rl_smap); 1908 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1909 } 1910 1911 if (sc->rl_parent_tag) 1912 bus_dma_tag_destroy(sc->rl_parent_tag); 1913 1914 mtx_destroy(&sc->rl_mtx); 1915 1916 return (0); 1917 } 1918 1919 static __inline void 1920 re_discard_rxbuf(struct rl_softc *sc, int idx) 1921 { 1922 struct rl_desc *desc; 1923 struct rl_rxdesc *rxd; 1924 uint32_t cmdstat; 1925 1926 if (if_getmtu(sc->rl_ifp) > RL_MTU && 1927 (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) 1928 rxd = &sc->rl_ldata.rl_jrx_desc[idx]; 1929 else 1930 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1931 desc = &sc->rl_ldata.rl_rx_list[idx]; 1932 desc->rl_vlanctl = 0; 1933 cmdstat = rxd->rx_size; 1934 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1935 cmdstat |= RL_RDESC_CMD_EOR; 1936 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1937 } 1938 1939 static int 1940 re_newbuf(struct rl_softc *sc, int idx) 1941 { 1942 struct mbuf *m; 1943 struct rl_rxdesc *rxd; 1944 bus_dma_segment_t segs[1]; 1945 bus_dmamap_t map; 1946 struct rl_desc *desc; 1947 uint32_t cmdstat; 1948 int error, nsegs; 1949 1950 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1951 if (m == NULL) 1952 return (ENOBUFS); 1953 1954 m->m_len = m->m_pkthdr.len = MCLBYTES; 1955 #ifdef RE_FIXUP_RX 1956 /* 1957 * This is part of an evil trick to deal with non-x86 platforms. 1958 * The RealTek chip requires RX buffers to be aligned on 64-bit 1959 * boundaries, but that will hose non-x86 machines. To get around 1960 * this, we leave some empty space at the start of each buffer 1961 * and for non-x86 hosts, we copy the buffer back six bytes 1962 * to achieve word alignment. This is slightly more efficient 1963 * than allocating a new buffer, copying the contents, and 1964 * discarding the old buffer. 1965 */ 1966 m_adj(m, RE_ETHER_ALIGN); 1967 #endif 1968 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1969 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1970 if (error != 0) { 1971 m_freem(m); 1972 return (ENOBUFS); 1973 } 1974 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1975 1976 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1977 if (rxd->rx_m != NULL) { 1978 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1979 BUS_DMASYNC_POSTREAD); 1980 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1981 } 1982 1983 rxd->rx_m = m; 1984 map = rxd->rx_dmamap; 1985 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1986 rxd->rx_size = segs[0].ds_len; 1987 sc->rl_ldata.rl_rx_sparemap = map; 1988 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1989 BUS_DMASYNC_PREREAD); 1990 1991 desc = &sc->rl_ldata.rl_rx_list[idx]; 1992 desc->rl_vlanctl = 0; 1993 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1994 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1995 cmdstat = segs[0].ds_len; 1996 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1997 cmdstat |= RL_RDESC_CMD_EOR; 1998 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1999 2000 return (0); 2001 } 2002 2003 static int 2004 re_jumbo_newbuf(struct rl_softc *sc, int idx) 2005 { 2006 struct mbuf *m; 2007 struct rl_rxdesc *rxd; 2008 bus_dma_segment_t segs[1]; 2009 bus_dmamap_t map; 2010 struct rl_desc *desc; 2011 uint32_t cmdstat; 2012 int error, nsegs; 2013 2014 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 2015 if (m == NULL) 2016 return (ENOBUFS); 2017 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 2018 #ifdef RE_FIXUP_RX 2019 m_adj(m, RE_ETHER_ALIGN); 2020 #endif 2021 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_jrx_mtag, 2022 sc->rl_ldata.rl_jrx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 2023 if (error != 0) { 2024 m_freem(m); 2025 return (ENOBUFS); 2026 } 2027 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 2028 2029 rxd = &sc->rl_ldata.rl_jrx_desc[idx]; 2030 if (rxd->rx_m != NULL) { 2031 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap, 2032 BUS_DMASYNC_POSTREAD); 2033 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap); 2034 } 2035 2036 rxd->rx_m = m; 2037 map = rxd->rx_dmamap; 2038 rxd->rx_dmamap = sc->rl_ldata.rl_jrx_sparemap; 2039 rxd->rx_size = segs[0].ds_len; 2040 sc->rl_ldata.rl_jrx_sparemap = map; 2041 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap, 2042 BUS_DMASYNC_PREREAD); 2043 2044 desc = &sc->rl_ldata.rl_rx_list[idx]; 2045 desc->rl_vlanctl = 0; 2046 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 2047 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 2048 cmdstat = segs[0].ds_len; 2049 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 2050 cmdstat |= RL_RDESC_CMD_EOR; 2051 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 2052 2053 return (0); 2054 } 2055 2056 #ifdef RE_FIXUP_RX 2057 static __inline void 2058 re_fixup_rx(struct mbuf *m) 2059 { 2060 int i; 2061 uint16_t *src, *dst; 2062 2063 src = mtod(m, uint16_t *); 2064 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 2065 2066 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 2067 *dst++ = *src++; 2068 2069 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 2070 } 2071 #endif 2072 2073 static int 2074 re_tx_list_init(struct rl_softc *sc) 2075 { 2076 struct rl_desc *desc; 2077 int i; 2078 2079 RL_LOCK_ASSERT(sc); 2080 2081 bzero(sc->rl_ldata.rl_tx_list, 2082 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 2083 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 2084 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 2085 #ifdef DEV_NETMAP 2086 re_netmap_tx_init(sc); 2087 #endif /* DEV_NETMAP */ 2088 /* Set EOR. */ 2089 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 2090 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 2091 2092 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2093 sc->rl_ldata.rl_tx_list_map, 2094 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2095 2096 sc->rl_ldata.rl_tx_prodidx = 0; 2097 sc->rl_ldata.rl_tx_considx = 0; 2098 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 2099 2100 return (0); 2101 } 2102 2103 static int 2104 re_rx_list_init(struct rl_softc *sc) 2105 { 2106 int error, i; 2107 2108 bzero(sc->rl_ldata.rl_rx_list, 2109 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 2110 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2111 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 2112 if ((error = re_newbuf(sc, i)) != 0) 2113 return (error); 2114 } 2115 #ifdef DEV_NETMAP 2116 re_netmap_rx_init(sc); 2117 #endif /* DEV_NETMAP */ 2118 2119 /* Flush the RX descriptors */ 2120 2121 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2122 sc->rl_ldata.rl_rx_list_map, 2123 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2124 2125 sc->rl_ldata.rl_rx_prodidx = 0; 2126 sc->rl_head = sc->rl_tail = NULL; 2127 sc->rl_int_rx_act = 0; 2128 2129 return (0); 2130 } 2131 2132 static int 2133 re_jrx_list_init(struct rl_softc *sc) 2134 { 2135 int error, i; 2136 2137 bzero(sc->rl_ldata.rl_rx_list, 2138 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 2139 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2140 sc->rl_ldata.rl_jrx_desc[i].rx_m = NULL; 2141 if ((error = re_jumbo_newbuf(sc, i)) != 0) 2142 return (error); 2143 } 2144 2145 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2146 sc->rl_ldata.rl_rx_list_map, 2147 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2148 2149 sc->rl_ldata.rl_rx_prodidx = 0; 2150 sc->rl_head = sc->rl_tail = NULL; 2151 sc->rl_int_rx_act = 0; 2152 2153 return (0); 2154 } 2155 2156 /* 2157 * RX handler for C+ and 8169. For the gigE chips, we support 2158 * the reception of jumbo frames that have been fragmented 2159 * across multiple 2K mbuf cluster buffers. 2160 */ 2161 static int 2162 re_rxeof(struct rl_softc *sc, int *rx_npktsp) 2163 { 2164 struct mbuf *m; 2165 if_t ifp; 2166 int i, rxerr, total_len; 2167 struct rl_desc *cur_rx; 2168 u_int32_t rxstat, rxvlan; 2169 int jumbo, maxpkt = 16, rx_npkts = 0; 2170 2171 RL_LOCK_ASSERT(sc); 2172 2173 ifp = sc->rl_ifp; 2174 #ifdef DEV_NETMAP 2175 if (netmap_rx_irq(ifp, 0, &rx_npkts)) 2176 return 0; 2177 #endif /* DEV_NETMAP */ 2178 if (if_getmtu(ifp) > RL_MTU && (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) 2179 jumbo = 1; 2180 else 2181 jumbo = 0; 2182 2183 /* Invalidate the descriptor memory */ 2184 2185 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2186 sc->rl_ldata.rl_rx_list_map, 2187 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2188 2189 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 2190 i = RL_RX_DESC_NXT(sc, i)) { 2191 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 2192 break; 2193 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 2194 rxstat = le32toh(cur_rx->rl_cmdstat); 2195 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 2196 break; 2197 total_len = rxstat & sc->rl_rxlenmask; 2198 rxvlan = le32toh(cur_rx->rl_vlanctl); 2199 if (jumbo != 0) 2200 m = sc->rl_ldata.rl_jrx_desc[i].rx_m; 2201 else 2202 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 2203 2204 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 2205 (rxstat & (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) != 2206 (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) { 2207 /* 2208 * RTL8168C or later controllers do not 2209 * support multi-fragment packet. 2210 */ 2211 re_discard_rxbuf(sc, i); 2212 continue; 2213 } else if ((rxstat & RL_RDESC_STAT_EOF) == 0) { 2214 if (re_newbuf(sc, i) != 0) { 2215 /* 2216 * If this is part of a multi-fragment packet, 2217 * discard all the pieces. 2218 */ 2219 if (sc->rl_head != NULL) { 2220 m_freem(sc->rl_head); 2221 sc->rl_head = sc->rl_tail = NULL; 2222 } 2223 re_discard_rxbuf(sc, i); 2224 continue; 2225 } 2226 m->m_len = RE_RX_DESC_BUFLEN; 2227 if (sc->rl_head == NULL) 2228 sc->rl_head = sc->rl_tail = m; 2229 else { 2230 m->m_flags &= ~M_PKTHDR; 2231 sc->rl_tail->m_next = m; 2232 sc->rl_tail = m; 2233 } 2234 continue; 2235 } 2236 2237 /* 2238 * NOTE: for the 8139C+, the frame length field 2239 * is always 12 bits in size, but for the gigE chips, 2240 * it is 13 bits (since the max RX frame length is 16K). 2241 * Unfortunately, all 32 bits in the status word 2242 * were already used, so to make room for the extra 2243 * length bit, RealTek took out the 'frame alignment 2244 * error' bit and shifted the other status bits 2245 * over one slot. The OWN, EOR, FS and LS bits are 2246 * still in the same places. We have already extracted 2247 * the frame length and checked the OWN bit, so rather 2248 * than using an alternate bit mapping, we shift the 2249 * status bits one space to the right so we can evaluate 2250 * them using the 8169 status as though it was in the 2251 * same format as that of the 8139C+. 2252 */ 2253 if (sc->rl_type == RL_8169) 2254 rxstat >>= 1; 2255 2256 /* 2257 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 2258 * set, but if CRC is clear, it will still be a valid frame. 2259 */ 2260 if ((rxstat & RL_RDESC_STAT_RXERRSUM) != 0) { 2261 rxerr = 1; 2262 if ((sc->rl_flags & RL_FLAG_JUMBOV2) == 0 && 2263 total_len > 8191 && 2264 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT) 2265 rxerr = 0; 2266 if (rxerr != 0) { 2267 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2268 /* 2269 * If this is part of a multi-fragment packet, 2270 * discard all the pieces. 2271 */ 2272 if (sc->rl_head != NULL) { 2273 m_freem(sc->rl_head); 2274 sc->rl_head = sc->rl_tail = NULL; 2275 } 2276 re_discard_rxbuf(sc, i); 2277 continue; 2278 } 2279 } 2280 2281 /* 2282 * If allocating a replacement mbuf fails, 2283 * reload the current one. 2284 */ 2285 if (jumbo != 0) 2286 rxerr = re_jumbo_newbuf(sc, i); 2287 else 2288 rxerr = re_newbuf(sc, i); 2289 if (rxerr != 0) { 2290 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2291 if (sc->rl_head != NULL) { 2292 m_freem(sc->rl_head); 2293 sc->rl_head = sc->rl_tail = NULL; 2294 } 2295 re_discard_rxbuf(sc, i); 2296 continue; 2297 } 2298 2299 if (sc->rl_head != NULL) { 2300 if (jumbo != 0) 2301 m->m_len = total_len; 2302 else { 2303 m->m_len = total_len % RE_RX_DESC_BUFLEN; 2304 if (m->m_len == 0) 2305 m->m_len = RE_RX_DESC_BUFLEN; 2306 } 2307 /* 2308 * Special case: if there's 4 bytes or less 2309 * in this buffer, the mbuf can be discarded: 2310 * the last 4 bytes is the CRC, which we don't 2311 * care about anyway. 2312 */ 2313 if (m->m_len <= ETHER_CRC_LEN) { 2314 sc->rl_tail->m_len -= 2315 (ETHER_CRC_LEN - m->m_len); 2316 m_freem(m); 2317 } else { 2318 m->m_len -= ETHER_CRC_LEN; 2319 m->m_flags &= ~M_PKTHDR; 2320 sc->rl_tail->m_next = m; 2321 } 2322 m = sc->rl_head; 2323 sc->rl_head = sc->rl_tail = NULL; 2324 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 2325 } else 2326 m->m_pkthdr.len = m->m_len = 2327 (total_len - ETHER_CRC_LEN); 2328 2329 #ifdef RE_FIXUP_RX 2330 re_fixup_rx(m); 2331 #endif 2332 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 2333 m->m_pkthdr.rcvif = ifp; 2334 2335 /* Do RX checksumming if enabled */ 2336 2337 if (if_getcapenable(ifp) & IFCAP_RXCSUM) { 2338 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2339 /* Check IP header checksum */ 2340 if (rxstat & RL_RDESC_STAT_PROTOID) 2341 m->m_pkthdr.csum_flags |= 2342 CSUM_IP_CHECKED; 2343 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 2344 m->m_pkthdr.csum_flags |= 2345 CSUM_IP_VALID; 2346 2347 /* Check TCP/UDP checksum */ 2348 if ((RL_TCPPKT(rxstat) && 2349 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 2350 (RL_UDPPKT(rxstat) && 2351 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 2352 m->m_pkthdr.csum_flags |= 2353 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2354 m->m_pkthdr.csum_data = 0xffff; 2355 } 2356 } else { 2357 /* 2358 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP 2359 */ 2360 if ((rxstat & RL_RDESC_STAT_PROTOID) && 2361 (rxvlan & RL_RDESC_IPV4)) 2362 m->m_pkthdr.csum_flags |= 2363 CSUM_IP_CHECKED; 2364 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) && 2365 (rxvlan & RL_RDESC_IPV4)) 2366 m->m_pkthdr.csum_flags |= 2367 CSUM_IP_VALID; 2368 if (((rxstat & RL_RDESC_STAT_TCP) && 2369 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 2370 ((rxstat & RL_RDESC_STAT_UDP) && 2371 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 2372 m->m_pkthdr.csum_flags |= 2373 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2374 m->m_pkthdr.csum_data = 0xffff; 2375 } 2376 } 2377 } 2378 maxpkt--; 2379 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 2380 m->m_pkthdr.ether_vtag = 2381 bswap16((rxvlan & RL_RDESC_VLANCTL_DATA)); 2382 m->m_flags |= M_VLANTAG; 2383 } 2384 RL_UNLOCK(sc); 2385 if_input(ifp, m); 2386 RL_LOCK(sc); 2387 rx_npkts++; 2388 } 2389 2390 /* Flush the RX DMA ring */ 2391 2392 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2393 sc->rl_ldata.rl_rx_list_map, 2394 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2395 2396 sc->rl_ldata.rl_rx_prodidx = i; 2397 2398 if (rx_npktsp != NULL) 2399 *rx_npktsp = rx_npkts; 2400 if (maxpkt) 2401 return (EAGAIN); 2402 2403 return (0); 2404 } 2405 2406 static void 2407 re_txeof(struct rl_softc *sc) 2408 { 2409 if_t ifp; 2410 struct rl_txdesc *txd; 2411 u_int32_t txstat; 2412 int cons; 2413 2414 cons = sc->rl_ldata.rl_tx_considx; 2415 if (cons == sc->rl_ldata.rl_tx_prodidx) 2416 return; 2417 2418 ifp = sc->rl_ifp; 2419 #ifdef DEV_NETMAP 2420 if (netmap_tx_irq(ifp, 0)) 2421 return; 2422 #endif /* DEV_NETMAP */ 2423 /* Invalidate the TX descriptor list */ 2424 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2425 sc->rl_ldata.rl_tx_list_map, 2426 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2427 2428 for (; cons != sc->rl_ldata.rl_tx_prodidx; 2429 cons = RL_TX_DESC_NXT(sc, cons)) { 2430 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 2431 if (txstat & RL_TDESC_STAT_OWN) 2432 break; 2433 /* 2434 * We only stash mbufs in the last descriptor 2435 * in a fragment chain, which also happens to 2436 * be the only place where the TX status bits 2437 * are valid. 2438 */ 2439 if (txstat & RL_TDESC_CMD_EOF) { 2440 txd = &sc->rl_ldata.rl_tx_desc[cons]; 2441 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2442 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2443 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2444 txd->tx_dmamap); 2445 KASSERT(txd->tx_m != NULL, 2446 ("%s: freeing NULL mbufs!", __func__)); 2447 m_freem(txd->tx_m); 2448 txd->tx_m = NULL; 2449 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 2450 RL_TDESC_STAT_COLCNT)) 2451 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 2452 if (txstat & RL_TDESC_STAT_TXERRSUM) 2453 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2454 else 2455 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 2456 } 2457 sc->rl_ldata.rl_tx_free++; 2458 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2459 } 2460 sc->rl_ldata.rl_tx_considx = cons; 2461 2462 /* No changes made to the TX ring, so no flush needed */ 2463 2464 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 2465 #ifdef RE_TX_MODERATION 2466 /* 2467 * If not all descriptors have been reaped yet, reload 2468 * the timer so that we will eventually get another 2469 * interrupt that will cause us to re-enter this routine. 2470 * This is done in case the transmitter has gone idle. 2471 */ 2472 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2473 #endif 2474 } else 2475 sc->rl_watchdog_timer = 0; 2476 } 2477 2478 static void 2479 re_tick(void *xsc) 2480 { 2481 struct rl_softc *sc; 2482 struct mii_data *mii; 2483 2484 sc = xsc; 2485 2486 RL_LOCK_ASSERT(sc); 2487 2488 mii = device_get_softc(sc->rl_miibus); 2489 mii_tick(mii); 2490 if ((sc->rl_flags & RL_FLAG_LINK) == 0) 2491 re_miibus_statchg(sc->rl_dev); 2492 /* 2493 * Reclaim transmitted frames here. Technically it is not 2494 * necessary to do here but it ensures periodic reclamation 2495 * regardless of Tx completion interrupt which seems to be 2496 * lost on PCIe based controllers under certain situations. 2497 */ 2498 re_txeof(sc); 2499 re_watchdog(sc); 2500 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2501 } 2502 2503 #ifdef DEVICE_POLLING 2504 static int 2505 re_poll(if_t ifp, enum poll_cmd cmd, int count) 2506 { 2507 struct rl_softc *sc = if_getsoftc(ifp); 2508 int rx_npkts = 0; 2509 2510 RL_LOCK(sc); 2511 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 2512 rx_npkts = re_poll_locked(ifp, cmd, count); 2513 RL_UNLOCK(sc); 2514 return (rx_npkts); 2515 } 2516 2517 static int 2518 re_poll_locked(if_t ifp, enum poll_cmd cmd, int count) 2519 { 2520 struct rl_softc *sc = if_getsoftc(ifp); 2521 int rx_npkts; 2522 2523 RL_LOCK_ASSERT(sc); 2524 2525 sc->rxcycles = count; 2526 re_rxeof(sc, &rx_npkts); 2527 re_txeof(sc); 2528 2529 if (!if_sendq_empty(ifp)) 2530 re_start_locked(ifp); 2531 2532 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2533 u_int16_t status; 2534 2535 status = CSR_READ_2(sc, RL_ISR); 2536 if (status == 0xffff) 2537 return (rx_npkts); 2538 if (status) 2539 CSR_WRITE_2(sc, RL_ISR, status); 2540 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2541 (sc->rl_flags & RL_FLAG_PCIE)) 2542 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2543 2544 /* 2545 * XXX check behaviour on receiver stalls. 2546 */ 2547 2548 if (status & RL_ISR_SYSTEM_ERR) { 2549 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2550 re_init_locked(sc); 2551 } 2552 } 2553 return (rx_npkts); 2554 } 2555 #endif /* DEVICE_POLLING */ 2556 2557 static int 2558 re_intr(void *arg) 2559 { 2560 struct rl_softc *sc; 2561 uint16_t status; 2562 2563 sc = arg; 2564 2565 status = CSR_READ_2(sc, RL_ISR); 2566 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2567 return (FILTER_STRAY); 2568 CSR_WRITE_2(sc, RL_IMR, 0); 2569 2570 taskqueue_enqueue(taskqueue_fast, &sc->rl_inttask); 2571 2572 return (FILTER_HANDLED); 2573 } 2574 2575 static void 2576 re_int_task(void *arg, int npending) 2577 { 2578 struct rl_softc *sc; 2579 if_t ifp; 2580 u_int16_t status; 2581 int rval = 0; 2582 2583 sc = arg; 2584 ifp = sc->rl_ifp; 2585 2586 RL_LOCK(sc); 2587 2588 status = CSR_READ_2(sc, RL_ISR); 2589 CSR_WRITE_2(sc, RL_ISR, status); 2590 2591 if (sc->suspended || 2592 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 2593 RL_UNLOCK(sc); 2594 return; 2595 } 2596 2597 #ifdef DEVICE_POLLING 2598 if (if_getcapenable(ifp) & IFCAP_POLLING) { 2599 RL_UNLOCK(sc); 2600 return; 2601 } 2602 #endif 2603 2604 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2605 rval = re_rxeof(sc, NULL); 2606 2607 /* 2608 * Some chips will ignore a second TX request issued 2609 * while an existing transmission is in progress. If 2610 * the transmitter goes idle but there are still 2611 * packets waiting to be sent, we need to restart the 2612 * channel here to flush them out. This only seems to 2613 * be required with the PCIe devices. 2614 */ 2615 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2616 (sc->rl_flags & RL_FLAG_PCIE)) 2617 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2618 if (status & ( 2619 #ifdef RE_TX_MODERATION 2620 RL_ISR_TIMEOUT_EXPIRED| 2621 #else 2622 RL_ISR_TX_OK| 2623 #endif 2624 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2625 re_txeof(sc); 2626 2627 if (status & RL_ISR_SYSTEM_ERR) { 2628 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2629 re_init_locked(sc); 2630 } 2631 2632 if (!if_sendq_empty(ifp)) 2633 re_start_locked(ifp); 2634 2635 RL_UNLOCK(sc); 2636 2637 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2638 taskqueue_enqueue(taskqueue_fast, &sc->rl_inttask); 2639 return; 2640 } 2641 2642 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2643 } 2644 2645 static void 2646 re_intr_msi(void *xsc) 2647 { 2648 struct rl_softc *sc; 2649 if_t ifp; 2650 uint16_t intrs, status; 2651 2652 sc = xsc; 2653 RL_LOCK(sc); 2654 2655 ifp = sc->rl_ifp; 2656 #ifdef DEVICE_POLLING 2657 if (if_getcapenable(ifp) & IFCAP_POLLING) { 2658 RL_UNLOCK(sc); 2659 return; 2660 } 2661 #endif 2662 /* Disable interrupts. */ 2663 CSR_WRITE_2(sc, RL_IMR, 0); 2664 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 2665 RL_UNLOCK(sc); 2666 return; 2667 } 2668 2669 intrs = RL_INTRS_CPLUS; 2670 status = CSR_READ_2(sc, RL_ISR); 2671 CSR_WRITE_2(sc, RL_ISR, status); 2672 if (sc->rl_int_rx_act > 0) { 2673 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW | 2674 RL_ISR_RX_OVERRUN); 2675 status &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW | 2676 RL_ISR_RX_OVERRUN); 2677 } 2678 2679 if (status & (RL_ISR_TIMEOUT_EXPIRED | RL_ISR_RX_OK | RL_ISR_RX_ERR | 2680 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) { 2681 re_rxeof(sc, NULL); 2682 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2683 if (sc->rl_int_rx_mod != 0 && 2684 (status & (RL_ISR_RX_OK | RL_ISR_RX_ERR | 2685 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) != 0) { 2686 /* Rearm one-shot timer. */ 2687 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2688 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | 2689 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN); 2690 sc->rl_int_rx_act = 1; 2691 } else { 2692 intrs |= RL_ISR_RX_OK | RL_ISR_RX_ERR | 2693 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN; 2694 sc->rl_int_rx_act = 0; 2695 } 2696 } 2697 } 2698 2699 /* 2700 * Some chips will ignore a second TX request issued 2701 * while an existing transmission is in progress. If 2702 * the transmitter goes idle but there are still 2703 * packets waiting to be sent, we need to restart the 2704 * channel here to flush them out. This only seems to 2705 * be required with the PCIe devices. 2706 */ 2707 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2708 (sc->rl_flags & RL_FLAG_PCIE)) 2709 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2710 if (status & (RL_ISR_TX_OK | RL_ISR_TX_ERR | RL_ISR_TX_DESC_UNAVAIL)) 2711 re_txeof(sc); 2712 2713 if (status & RL_ISR_SYSTEM_ERR) { 2714 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2715 re_init_locked(sc); 2716 } 2717 2718 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2719 if (!if_sendq_empty(ifp)) 2720 re_start_locked(ifp); 2721 CSR_WRITE_2(sc, RL_IMR, intrs); 2722 } 2723 RL_UNLOCK(sc); 2724 } 2725 2726 static int 2727 re_encap(struct rl_softc *sc, struct mbuf **m_head) 2728 { 2729 struct rl_txdesc *txd, *txd_last; 2730 bus_dma_segment_t segs[RL_NTXSEGS]; 2731 bus_dmamap_t map; 2732 struct mbuf *m_new; 2733 struct rl_desc *desc; 2734 int nsegs, prod; 2735 int i, error, ei, si; 2736 int padlen; 2737 uint32_t cmdstat, csum_flags, vlanctl; 2738 2739 RL_LOCK_ASSERT(sc); 2740 M_ASSERTPKTHDR((*m_head)); 2741 2742 /* 2743 * With some of the RealTek chips, using the checksum offload 2744 * support in conjunction with the autopadding feature results 2745 * in the transmission of corrupt frames. For example, if we 2746 * need to send a really small IP fragment that's less than 60 2747 * bytes in size, and IP header checksumming is enabled, the 2748 * resulting ethernet frame that appears on the wire will 2749 * have garbled payload. To work around this, if TX IP checksum 2750 * offload is enabled, we always manually pad short frames out 2751 * to the minimum ethernet frame size. 2752 */ 2753 if ((sc->rl_flags & RL_FLAG_AUTOPAD) == 0 && 2754 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN && 2755 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) { 2756 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2757 if (M_WRITABLE(*m_head) == 0) { 2758 /* Get a writable copy. */ 2759 m_new = m_dup(*m_head, M_NOWAIT); 2760 m_freem(*m_head); 2761 if (m_new == NULL) { 2762 *m_head = NULL; 2763 return (ENOBUFS); 2764 } 2765 *m_head = m_new; 2766 } 2767 if ((*m_head)->m_next != NULL || 2768 M_TRAILINGSPACE(*m_head) < padlen) { 2769 m_new = m_defrag(*m_head, M_NOWAIT); 2770 if (m_new == NULL) { 2771 m_freem(*m_head); 2772 *m_head = NULL; 2773 return (ENOBUFS); 2774 } 2775 } else 2776 m_new = *m_head; 2777 2778 /* 2779 * Manually pad short frames, and zero the pad space 2780 * to avoid leaking data. 2781 */ 2782 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2783 m_new->m_pkthdr.len += padlen; 2784 m_new->m_len = m_new->m_pkthdr.len; 2785 *m_head = m_new; 2786 } 2787 2788 prod = sc->rl_ldata.rl_tx_prodidx; 2789 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2790 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2791 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2792 if (error == EFBIG) { 2793 m_new = m_collapse(*m_head, M_NOWAIT, RL_NTXSEGS); 2794 if (m_new == NULL) { 2795 m_freem(*m_head); 2796 *m_head = NULL; 2797 return (ENOBUFS); 2798 } 2799 *m_head = m_new; 2800 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2801 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2802 if (error != 0) { 2803 m_freem(*m_head); 2804 *m_head = NULL; 2805 return (error); 2806 } 2807 } else if (error != 0) 2808 return (error); 2809 if (nsegs == 0) { 2810 m_freem(*m_head); 2811 *m_head = NULL; 2812 return (EIO); 2813 } 2814 2815 /* Check for number of available descriptors. */ 2816 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2817 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2818 return (ENOBUFS); 2819 } 2820 2821 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2822 BUS_DMASYNC_PREWRITE); 2823 2824 /* 2825 * Set up checksum offload. Note: checksum offload bits must 2826 * appear in all descriptors of a multi-descriptor transmit 2827 * attempt. This is according to testing done with an 8169 2828 * chip. This is a requirement. 2829 */ 2830 vlanctl = 0; 2831 csum_flags = 0; 2832 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2833 if ((sc->rl_flags & RL_FLAG_DESCV2) != 0) { 2834 csum_flags |= RL_TDESC_CMD_LGSEND; 2835 vlanctl |= ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2836 RL_TDESC_CMD_MSSVALV2_SHIFT); 2837 } else { 2838 csum_flags |= RL_TDESC_CMD_LGSEND | 2839 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2840 RL_TDESC_CMD_MSSVAL_SHIFT); 2841 } 2842 } else { 2843 /* 2844 * Unconditionally enable IP checksum if TCP or UDP 2845 * checksum is required. Otherwise, TCP/UDP checksum 2846 * doesn't make effects. 2847 */ 2848 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) { 2849 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2850 csum_flags |= RL_TDESC_CMD_IPCSUM; 2851 if (((*m_head)->m_pkthdr.csum_flags & 2852 CSUM_TCP) != 0) 2853 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2854 if (((*m_head)->m_pkthdr.csum_flags & 2855 CSUM_UDP) != 0) 2856 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2857 } else { 2858 vlanctl |= RL_TDESC_CMD_IPCSUMV2; 2859 if (((*m_head)->m_pkthdr.csum_flags & 2860 CSUM_TCP) != 0) 2861 vlanctl |= RL_TDESC_CMD_TCPCSUMV2; 2862 if (((*m_head)->m_pkthdr.csum_flags & 2863 CSUM_UDP) != 0) 2864 vlanctl |= RL_TDESC_CMD_UDPCSUMV2; 2865 } 2866 } 2867 } 2868 2869 /* 2870 * Set up hardware VLAN tagging. Note: vlan tag info must 2871 * appear in all descriptors of a multi-descriptor 2872 * transmission attempt. 2873 */ 2874 if ((*m_head)->m_flags & M_VLANTAG) 2875 vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) | 2876 RL_TDESC_VLANCTL_TAG; 2877 2878 si = prod; 2879 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2880 desc = &sc->rl_ldata.rl_tx_list[prod]; 2881 desc->rl_vlanctl = htole32(vlanctl); 2882 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2883 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2884 cmdstat = segs[i].ds_len; 2885 if (i != 0) 2886 cmdstat |= RL_TDESC_CMD_OWN; 2887 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2888 cmdstat |= RL_TDESC_CMD_EOR; 2889 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2890 sc->rl_ldata.rl_tx_free--; 2891 } 2892 /* Update producer index. */ 2893 sc->rl_ldata.rl_tx_prodidx = prod; 2894 2895 /* Set EOF on the last descriptor. */ 2896 ei = RL_TX_DESC_PRV(sc, prod); 2897 desc = &sc->rl_ldata.rl_tx_list[ei]; 2898 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2899 2900 desc = &sc->rl_ldata.rl_tx_list[si]; 2901 /* Set SOF and transfer ownership of packet to the chip. */ 2902 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2903 2904 /* 2905 * Insure that the map for this transmission 2906 * is placed at the array index of the last descriptor 2907 * in this chain. (Swap last and first dmamaps.) 2908 */ 2909 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2910 map = txd->tx_dmamap; 2911 txd->tx_dmamap = txd_last->tx_dmamap; 2912 txd_last->tx_dmamap = map; 2913 txd_last->tx_m = *m_head; 2914 2915 return (0); 2916 } 2917 2918 static void 2919 re_start(if_t ifp) 2920 { 2921 struct rl_softc *sc; 2922 2923 sc = if_getsoftc(ifp); 2924 RL_LOCK(sc); 2925 re_start_locked(ifp); 2926 RL_UNLOCK(sc); 2927 } 2928 2929 /* 2930 * Main transmit routine for C+ and gigE NICs. 2931 */ 2932 static void 2933 re_start_locked(if_t ifp) 2934 { 2935 struct rl_softc *sc; 2936 struct mbuf *m_head; 2937 int queued; 2938 2939 sc = if_getsoftc(ifp); 2940 2941 #ifdef DEV_NETMAP 2942 /* XXX is this necessary ? */ 2943 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 2944 struct netmap_kring *kring = NA(ifp)->tx_rings[0]; 2945 if (sc->rl_ldata.rl_tx_prodidx != kring->nr_hwcur) { 2946 /* kick the tx unit */ 2947 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2948 #ifdef RE_TX_MODERATION 2949 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2950 #endif 2951 sc->rl_watchdog_timer = 5; 2952 } 2953 return; 2954 } 2955 #endif /* DEV_NETMAP */ 2956 2957 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2958 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) 2959 return; 2960 2961 for (queued = 0; !if_sendq_empty(ifp) && 2962 sc->rl_ldata.rl_tx_free > 1;) { 2963 m_head = if_dequeue(ifp); 2964 if (m_head == NULL) 2965 break; 2966 2967 if (re_encap(sc, &m_head) != 0) { 2968 if (m_head == NULL) 2969 break; 2970 if_sendq_prepend(ifp, m_head); 2971 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 2972 break; 2973 } 2974 2975 /* 2976 * If there's a BPF listener, bounce a copy of this frame 2977 * to him. 2978 */ 2979 ETHER_BPF_MTAP(ifp, m_head); 2980 2981 queued++; 2982 } 2983 2984 if (queued == 0) { 2985 #ifdef RE_TX_MODERATION 2986 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2987 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2988 #endif 2989 return; 2990 } 2991 2992 re_start_tx(sc); 2993 } 2994 2995 static void 2996 re_start_tx(struct rl_softc *sc) 2997 { 2998 2999 /* Flush the TX descriptors */ 3000 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 3001 sc->rl_ldata.rl_tx_list_map, 3002 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 3003 3004 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 3005 3006 #ifdef RE_TX_MODERATION 3007 /* 3008 * Use the countdown timer for interrupt moderation. 3009 * 'TX done' interrupts are disabled. Instead, we reset the 3010 * countdown timer, which will begin counting until it hits 3011 * the value in the TIMERINT register, and then trigger an 3012 * interrupt. Each time we write to the TIMERCNT register, 3013 * the timer count is reset to 0. 3014 */ 3015 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 3016 #endif 3017 3018 /* 3019 * Set a timeout in case the chip goes out to lunch. 3020 */ 3021 sc->rl_watchdog_timer = 5; 3022 } 3023 3024 static void 3025 re_set_jumbo(struct rl_softc *sc, int jumbo) 3026 { 3027 3028 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168E_VL) { 3029 pci_set_max_read_req(sc->rl_dev, 4096); 3030 return; 3031 } 3032 3033 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 3034 if (jumbo != 0) { 3035 CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) | 3036 RL_CFG3_JUMBO_EN0); 3037 switch (sc->rl_hwrev->rl_rev) { 3038 case RL_HWREV_8168DP: 3039 break; 3040 case RL_HWREV_8168E: 3041 CSR_WRITE_1(sc, sc->rl_cfg4, 3042 CSR_READ_1(sc, sc->rl_cfg4) | 0x01); 3043 break; 3044 default: 3045 CSR_WRITE_1(sc, sc->rl_cfg4, 3046 CSR_READ_1(sc, sc->rl_cfg4) | RL_CFG4_JUMBO_EN1); 3047 } 3048 } else { 3049 CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) & 3050 ~RL_CFG3_JUMBO_EN0); 3051 switch (sc->rl_hwrev->rl_rev) { 3052 case RL_HWREV_8168DP: 3053 break; 3054 case RL_HWREV_8168E: 3055 CSR_WRITE_1(sc, sc->rl_cfg4, 3056 CSR_READ_1(sc, sc->rl_cfg4) & ~0x01); 3057 break; 3058 default: 3059 CSR_WRITE_1(sc, sc->rl_cfg4, 3060 CSR_READ_1(sc, sc->rl_cfg4) & ~RL_CFG4_JUMBO_EN1); 3061 } 3062 } 3063 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3064 3065 switch (sc->rl_hwrev->rl_rev) { 3066 case RL_HWREV_8168DP: 3067 pci_set_max_read_req(sc->rl_dev, 4096); 3068 break; 3069 default: 3070 if (jumbo != 0) 3071 pci_set_max_read_req(sc->rl_dev, 512); 3072 else 3073 pci_set_max_read_req(sc->rl_dev, 4096); 3074 } 3075 } 3076 3077 static void 3078 re_init(void *xsc) 3079 { 3080 struct rl_softc *sc = xsc; 3081 3082 RL_LOCK(sc); 3083 re_init_locked(sc); 3084 RL_UNLOCK(sc); 3085 } 3086 3087 static void 3088 re_init_locked(struct rl_softc *sc) 3089 { 3090 if_t ifp = sc->rl_ifp; 3091 struct mii_data *mii; 3092 uint32_t reg; 3093 uint16_t cfg; 3094 uint32_t idr[2]; 3095 3096 RL_LOCK_ASSERT(sc); 3097 3098 mii = device_get_softc(sc->rl_miibus); 3099 3100 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 3101 return; 3102 3103 /* 3104 * Cancel pending I/O and free all RX/TX buffers. 3105 */ 3106 re_stop(sc); 3107 3108 /* Put controller into known state. */ 3109 re_reset(sc); 3110 3111 /* 3112 * For C+ mode, initialize the RX descriptors and mbufs. 3113 */ 3114 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3115 if (if_getmtu(ifp) > RL_MTU) { 3116 if (re_jrx_list_init(sc) != 0) { 3117 device_printf(sc->rl_dev, 3118 "no memory for jumbo RX buffers\n"); 3119 re_stop(sc); 3120 return; 3121 } 3122 /* Disable checksum offloading for jumbo frames. */ 3123 if_setcapenablebit(ifp, 0, (IFCAP_HWCSUM | IFCAP_TSO4)); 3124 if_sethwassistbits(ifp, 0, (RE_CSUM_FEATURES | CSUM_TSO)); 3125 } else { 3126 if (re_rx_list_init(sc) != 0) { 3127 device_printf(sc->rl_dev, 3128 "no memory for RX buffers\n"); 3129 re_stop(sc); 3130 return; 3131 } 3132 } 3133 re_set_jumbo(sc, if_getmtu(ifp) > RL_MTU); 3134 } else { 3135 if (re_rx_list_init(sc) != 0) { 3136 device_printf(sc->rl_dev, "no memory for RX buffers\n"); 3137 re_stop(sc); 3138 return; 3139 } 3140 if ((sc->rl_flags & RL_FLAG_PCIE) != 0 && 3141 pci_get_device(sc->rl_dev) != RT_DEVICEID_8101E) { 3142 if (if_getmtu(ifp) > RL_MTU) 3143 pci_set_max_read_req(sc->rl_dev, 512); 3144 else 3145 pci_set_max_read_req(sc->rl_dev, 4096); 3146 } 3147 } 3148 re_tx_list_init(sc); 3149 3150 /* 3151 * Enable C+ RX and TX mode, as well as VLAN stripping and 3152 * RX checksum offload. We must configure the C+ register 3153 * before all others. 3154 */ 3155 cfg = RL_CPLUSCMD_PCI_MRW; 3156 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 3157 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 3158 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 3159 cfg |= RL_CPLUSCMD_VLANSTRIP; 3160 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) { 3161 cfg |= RL_CPLUSCMD_MACSTAT_DIS; 3162 /* XXX magic. */ 3163 cfg |= 0x0001; 3164 } else 3165 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB; 3166 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg); 3167 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SC || 3168 sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) { 3169 reg = 0x000fff00; 3170 if ((CSR_READ_1(sc, sc->rl_cfg2) & RL_CFG2_PCI66MHZ) != 0) 3171 reg |= 0x000000ff; 3172 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) 3173 reg |= 0x00f00000; 3174 CSR_WRITE_4(sc, 0x7c, reg); 3175 /* Disable interrupt mitigation. */ 3176 CSR_WRITE_2(sc, 0xe2, 0); 3177 } 3178 /* 3179 * Disable TSO if interface MTU size is greater than MSS 3180 * allowed in controller. 3181 */ 3182 if (if_getmtu(ifp) > RL_TSO_MTU && (if_getcapenable(ifp) & IFCAP_TSO4) != 0) { 3183 if_setcapenablebit(ifp, 0, IFCAP_TSO4); 3184 if_sethwassistbits(ifp, 0, CSUM_TSO); 3185 } 3186 3187 /* 3188 * Init our MAC address. Even though the chipset 3189 * documentation doesn't mention it, we need to enter "Config 3190 * register write enable" mode to modify the ID registers. 3191 */ 3192 /* Copy MAC address on stack to align. */ 3193 bzero(idr, sizeof(idr)); 3194 bcopy(if_getlladdr(ifp), idr, ETHER_ADDR_LEN); 3195 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 3196 CSR_WRITE_4(sc, RL_IDR0, htole32(idr[0])); 3197 CSR_WRITE_4(sc, RL_IDR4, htole32(idr[1])); 3198 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3199 3200 /* 3201 * Load the addresses of the RX and TX lists into the chip. 3202 */ 3203 3204 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 3205 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 3206 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 3207 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 3208 3209 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 3210 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 3211 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 3212 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 3213 3214 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0) { 3215 /* Disable RXDV gate. */ 3216 CSR_WRITE_4(sc, RL_MISC, CSR_READ_4(sc, RL_MISC) & 3217 ~0x00080000); 3218 } 3219 3220 /* 3221 * Enable transmit and receive for pre-RTL8168G controllers. 3222 * RX/TX MACs should be enabled before RX/TX configuration. 3223 */ 3224 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) == 0) 3225 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB | RL_CMD_RX_ENB); 3226 3227 /* 3228 * Set the initial TX configuration. 3229 */ 3230 if (sc->rl_testmode) { 3231 if (sc->rl_type == RL_8169) 3232 CSR_WRITE_4(sc, RL_TXCFG, 3233 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 3234 else 3235 CSR_WRITE_4(sc, RL_TXCFG, 3236 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 3237 } else 3238 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 3239 3240 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 3241 3242 /* 3243 * Set the initial RX configuration. 3244 */ 3245 re_set_rxmode(sc); 3246 3247 /* Configure interrupt moderation. */ 3248 if (sc->rl_type == RL_8169) { 3249 /* Magic from vendor. */ 3250 CSR_WRITE_2(sc, RL_INTRMOD, 0x5100); 3251 } 3252 3253 /* 3254 * Enable transmit and receive for RTL8168G and later controllers. 3255 * RX/TX MACs should be enabled after RX/TX configuration. 3256 */ 3257 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0) 3258 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB | RL_CMD_RX_ENB); 3259 3260 #ifdef DEVICE_POLLING 3261 /* 3262 * Disable interrupts if we are polling. 3263 */ 3264 if (if_getcapenable(ifp) & IFCAP_POLLING) 3265 CSR_WRITE_2(sc, RL_IMR, 0); 3266 else /* otherwise ... */ 3267 #endif 3268 3269 /* 3270 * Enable interrupts. 3271 */ 3272 if (sc->rl_testmode) 3273 CSR_WRITE_2(sc, RL_IMR, 0); 3274 else 3275 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 3276 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 3277 3278 /* Set initial TX threshold */ 3279 sc->rl_txthresh = RL_TX_THRESH_INIT; 3280 3281 /* Start RX/TX process. */ 3282 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 3283 3284 /* 3285 * Initialize the timer interrupt register so that 3286 * a timer interrupt will be generated once the timer 3287 * reaches a certain number of ticks. The timer is 3288 * reloaded on each transmit. 3289 */ 3290 #ifdef RE_TX_MODERATION 3291 /* 3292 * Use timer interrupt register to moderate TX interrupt 3293 * moderation, which dramatically improves TX frame rate. 3294 */ 3295 if (sc->rl_type == RL_8169) 3296 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 3297 else 3298 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 3299 #else 3300 /* 3301 * Use timer interrupt register to moderate RX interrupt 3302 * moderation. 3303 */ 3304 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 && 3305 intr_filter == 0) { 3306 if (sc->rl_type == RL_8169) 3307 CSR_WRITE_4(sc, RL_TIMERINT_8169, 3308 RL_USECS(sc->rl_int_rx_mod)); 3309 } else { 3310 if (sc->rl_type == RL_8169) 3311 CSR_WRITE_4(sc, RL_TIMERINT_8169, RL_USECS(0)); 3312 } 3313 #endif 3314 3315 /* 3316 * For 8169 gigE NICs, set the max allowed RX packet 3317 * size so we can receive jumbo frames. 3318 */ 3319 if (sc->rl_type == RL_8169) { 3320 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3321 /* 3322 * For controllers that use new jumbo frame scheme, 3323 * set maximum size of jumbo frame depending on 3324 * controller revisions. 3325 */ 3326 if (if_getmtu(ifp) > RL_MTU) 3327 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 3328 sc->rl_hwrev->rl_max_mtu + 3329 ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN + 3330 ETHER_CRC_LEN); 3331 else 3332 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 3333 RE_RX_DESC_BUFLEN); 3334 } else if ((sc->rl_flags & RL_FLAG_PCIE) != 0 && 3335 sc->rl_hwrev->rl_max_mtu == RL_MTU) { 3336 /* RTL810x has no jumbo frame support. */ 3337 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, RE_RX_DESC_BUFLEN); 3338 } else 3339 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 3340 } 3341 3342 if (sc->rl_testmode) 3343 return; 3344 3345 CSR_WRITE_1(sc, sc->rl_cfg1, CSR_READ_1(sc, sc->rl_cfg1) | 3346 RL_CFG1_DRVLOAD); 3347 3348 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 3349 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 3350 3351 sc->rl_flags &= ~RL_FLAG_LINK; 3352 mii_mediachg(mii); 3353 3354 sc->rl_watchdog_timer = 0; 3355 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 3356 3357 #ifdef DEV_NETMAP 3358 netmap_enable_all_rings(ifp); 3359 #endif /* DEV_NETMAP */ 3360 } 3361 3362 /* 3363 * Set media options. 3364 */ 3365 static int 3366 re_ifmedia_upd(if_t ifp) 3367 { 3368 struct rl_softc *sc; 3369 struct mii_data *mii; 3370 int error; 3371 3372 sc = if_getsoftc(ifp); 3373 mii = device_get_softc(sc->rl_miibus); 3374 RL_LOCK(sc); 3375 error = mii_mediachg(mii); 3376 RL_UNLOCK(sc); 3377 3378 return (error); 3379 } 3380 3381 /* 3382 * Report current media status. 3383 */ 3384 static void 3385 re_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 3386 { 3387 struct rl_softc *sc; 3388 struct mii_data *mii; 3389 3390 sc = if_getsoftc(ifp); 3391 mii = device_get_softc(sc->rl_miibus); 3392 3393 RL_LOCK(sc); 3394 mii_pollstat(mii); 3395 ifmr->ifm_active = mii->mii_media_active; 3396 ifmr->ifm_status = mii->mii_media_status; 3397 RL_UNLOCK(sc); 3398 } 3399 3400 static int 3401 re_ioctl(if_t ifp, u_long command, caddr_t data) 3402 { 3403 struct rl_softc *sc = if_getsoftc(ifp); 3404 struct ifreq *ifr = (struct ifreq *) data; 3405 struct mii_data *mii; 3406 int error = 0; 3407 3408 switch (command) { 3409 case SIOCSIFMTU: 3410 if (ifr->ifr_mtu < ETHERMIN || 3411 ifr->ifr_mtu > sc->rl_hwrev->rl_max_mtu || 3412 ((sc->rl_flags & RL_FLAG_FASTETHER) != 0 && 3413 ifr->ifr_mtu > RL_MTU)) { 3414 error = EINVAL; 3415 break; 3416 } 3417 RL_LOCK(sc); 3418 if (if_getmtu(ifp) != ifr->ifr_mtu) { 3419 if_setmtu(ifp, ifr->ifr_mtu); 3420 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 3421 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 3422 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3423 re_init_locked(sc); 3424 } 3425 if (if_getmtu(ifp) > RL_TSO_MTU && 3426 (if_getcapenable(ifp) & IFCAP_TSO4) != 0) { 3427 if_setcapenablebit(ifp, 0, 3428 IFCAP_TSO4 | IFCAP_VLAN_HWTSO); 3429 if_sethwassistbits(ifp, 0, CSUM_TSO); 3430 } 3431 VLAN_CAPABILITIES(ifp); 3432 } 3433 RL_UNLOCK(sc); 3434 break; 3435 case SIOCSIFFLAGS: 3436 RL_LOCK(sc); 3437 if ((if_getflags(ifp) & IFF_UP) != 0) { 3438 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 3439 if (((if_getflags(ifp) ^ sc->rl_if_flags) 3440 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 3441 re_set_rxmode(sc); 3442 } else 3443 re_init_locked(sc); 3444 } else { 3445 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 3446 re_stop(sc); 3447 } 3448 sc->rl_if_flags = if_getflags(ifp); 3449 RL_UNLOCK(sc); 3450 break; 3451 case SIOCADDMULTI: 3452 case SIOCDELMULTI: 3453 RL_LOCK(sc); 3454 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 3455 re_set_rxmode(sc); 3456 RL_UNLOCK(sc); 3457 break; 3458 case SIOCGIFMEDIA: 3459 case SIOCSIFMEDIA: 3460 mii = device_get_softc(sc->rl_miibus); 3461 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3462 break; 3463 case SIOCSIFCAP: 3464 { 3465 int mask, reinit; 3466 3467 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 3468 reinit = 0; 3469 #ifdef DEVICE_POLLING 3470 if (mask & IFCAP_POLLING) { 3471 if (ifr->ifr_reqcap & IFCAP_POLLING) { 3472 error = ether_poll_register(re_poll, ifp); 3473 if (error) 3474 return (error); 3475 RL_LOCK(sc); 3476 /* Disable interrupts */ 3477 CSR_WRITE_2(sc, RL_IMR, 0x0000); 3478 if_setcapenablebit(ifp, IFCAP_POLLING, 0); 3479 RL_UNLOCK(sc); 3480 } else { 3481 error = ether_poll_deregister(ifp); 3482 /* Enable interrupts. */ 3483 RL_LOCK(sc); 3484 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 3485 if_setcapenablebit(ifp, 0, IFCAP_POLLING); 3486 RL_UNLOCK(sc); 3487 } 3488 } 3489 #endif /* DEVICE_POLLING */ 3490 RL_LOCK(sc); 3491 if ((mask & IFCAP_TXCSUM) != 0 && 3492 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { 3493 if_togglecapenable(ifp, IFCAP_TXCSUM); 3494 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 3495 if_sethwassistbits(ifp, RE_CSUM_FEATURES, 0); 3496 else 3497 if_sethwassistbits(ifp, 0, RE_CSUM_FEATURES); 3498 reinit = 1; 3499 } 3500 if ((mask & IFCAP_RXCSUM) != 0 && 3501 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) { 3502 if_togglecapenable(ifp, IFCAP_RXCSUM); 3503 reinit = 1; 3504 } 3505 if ((mask & IFCAP_TSO4) != 0 && 3506 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) { 3507 if_togglecapenable(ifp, IFCAP_TSO4); 3508 if ((IFCAP_TSO4 & if_getcapenable(ifp)) != 0) 3509 if_sethwassistbits(ifp, CSUM_TSO, 0); 3510 else 3511 if_sethwassistbits(ifp, 0, CSUM_TSO); 3512 if (if_getmtu(ifp) > RL_TSO_MTU && 3513 (if_getcapenable(ifp) & IFCAP_TSO4) != 0) { 3514 if_setcapenablebit(ifp, 0, IFCAP_TSO4); 3515 if_sethwassistbits(ifp, 0, CSUM_TSO); 3516 } 3517 } 3518 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 3519 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0) 3520 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 3521 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3522 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 3523 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 3524 /* TSO over VLAN requires VLAN hardware tagging. */ 3525 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0) 3526 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO); 3527 reinit = 1; 3528 } 3529 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 3530 (mask & (IFCAP_HWCSUM | IFCAP_TSO4 | 3531 IFCAP_VLAN_HWTSO)) != 0) 3532 reinit = 1; 3533 if ((mask & IFCAP_WOL) != 0 && 3534 (if_getcapabilities(ifp) & IFCAP_WOL) != 0) { 3535 if ((mask & IFCAP_WOL_UCAST) != 0) 3536 if_togglecapenable(ifp, IFCAP_WOL_UCAST); 3537 if ((mask & IFCAP_WOL_MCAST) != 0) 3538 if_togglecapenable(ifp, IFCAP_WOL_MCAST); 3539 if ((mask & IFCAP_WOL_MAGIC) != 0) 3540 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 3541 } 3542 if (reinit && if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3543 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3544 re_init_locked(sc); 3545 } 3546 RL_UNLOCK(sc); 3547 VLAN_CAPABILITIES(ifp); 3548 } 3549 break; 3550 default: 3551 error = ether_ioctl(ifp, command, data); 3552 break; 3553 } 3554 3555 return (error); 3556 } 3557 3558 static void 3559 re_watchdog(struct rl_softc *sc) 3560 { 3561 if_t ifp; 3562 3563 RL_LOCK_ASSERT(sc); 3564 3565 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 3566 return; 3567 3568 ifp = sc->rl_ifp; 3569 re_txeof(sc); 3570 if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) { 3571 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 3572 "-- recovering\n"); 3573 if (!if_sendq_empty(ifp)) 3574 re_start_locked(ifp); 3575 return; 3576 } 3577 3578 if_printf(ifp, "watchdog timeout\n"); 3579 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3580 3581 re_rxeof(sc, NULL); 3582 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3583 re_init_locked(sc); 3584 if (!if_sendq_empty(ifp)) 3585 re_start_locked(ifp); 3586 } 3587 3588 /* 3589 * Stop the adapter and free any mbufs allocated to the 3590 * RX and TX lists. 3591 */ 3592 static void 3593 re_stop(struct rl_softc *sc) 3594 { 3595 int i; 3596 if_t ifp; 3597 struct rl_txdesc *txd; 3598 struct rl_rxdesc *rxd; 3599 3600 RL_LOCK_ASSERT(sc); 3601 3602 ifp = sc->rl_ifp; 3603 3604 sc->rl_watchdog_timer = 0; 3605 callout_stop(&sc->rl_stat_callout); 3606 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 3607 3608 #ifdef DEV_NETMAP 3609 netmap_disable_all_rings(ifp); 3610 #endif /* DEV_NETMAP */ 3611 3612 /* 3613 * Disable accepting frames to put RX MAC into idle state. 3614 * Otherwise it's possible to get frames while stop command 3615 * execution is in progress and controller can DMA the frame 3616 * to already freed RX buffer during that period. 3617 */ 3618 CSR_WRITE_4(sc, RL_RXCFG, CSR_READ_4(sc, RL_RXCFG) & 3619 ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_MULTI | 3620 RL_RXCFG_RX_BROAD)); 3621 3622 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0) { 3623 /* Enable RXDV gate. */ 3624 CSR_WRITE_4(sc, RL_MISC, CSR_READ_4(sc, RL_MISC) | 3625 0x00080000); 3626 } 3627 3628 if ((sc->rl_flags & RL_FLAG_WAIT_TXPOLL) != 0) { 3629 for (i = RL_TIMEOUT; i > 0; i--) { 3630 if ((CSR_READ_1(sc, sc->rl_txstart) & 3631 RL_TXSTART_START) == 0) 3632 break; 3633 DELAY(20); 3634 } 3635 if (i == 0) 3636 device_printf(sc->rl_dev, 3637 "stopping TX poll timed out!\n"); 3638 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 3639 } else if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0) { 3640 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB | 3641 RL_CMD_RX_ENB); 3642 if ((sc->rl_flags & RL_FLAG_CMDSTOP_WAIT_TXQ) != 0) { 3643 for (i = RL_TIMEOUT; i > 0; i--) { 3644 if ((CSR_READ_4(sc, RL_TXCFG) & 3645 RL_TXCFG_QUEUE_EMPTY) != 0) 3646 break; 3647 DELAY(100); 3648 } 3649 if (i == 0) 3650 device_printf(sc->rl_dev, 3651 "stopping TXQ timed out!\n"); 3652 } 3653 } else 3654 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 3655 DELAY(1000); 3656 CSR_WRITE_2(sc, RL_IMR, 0x0000); 3657 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 3658 3659 if (sc->rl_head != NULL) { 3660 m_freem(sc->rl_head); 3661 sc->rl_head = sc->rl_tail = NULL; 3662 } 3663 3664 /* Free the TX list buffers. */ 3665 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 3666 txd = &sc->rl_ldata.rl_tx_desc[i]; 3667 if (txd->tx_m != NULL) { 3668 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 3669 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3670 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 3671 txd->tx_dmamap); 3672 m_freem(txd->tx_m); 3673 txd->tx_m = NULL; 3674 } 3675 } 3676 3677 /* Free the RX list buffers. */ 3678 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 3679 rxd = &sc->rl_ldata.rl_rx_desc[i]; 3680 if (rxd->rx_m != NULL) { 3681 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 3682 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3683 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 3684 rxd->rx_dmamap); 3685 m_freem(rxd->rx_m); 3686 rxd->rx_m = NULL; 3687 } 3688 } 3689 3690 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3691 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 3692 rxd = &sc->rl_ldata.rl_jrx_desc[i]; 3693 if (rxd->rx_m != NULL) { 3694 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, 3695 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3696 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, 3697 rxd->rx_dmamap); 3698 m_freem(rxd->rx_m); 3699 rxd->rx_m = NULL; 3700 } 3701 } 3702 } 3703 } 3704 3705 /* 3706 * Device suspend routine. Stop the interface and save some PCI 3707 * settings in case the BIOS doesn't restore them properly on 3708 * resume. 3709 */ 3710 static int 3711 re_suspend(device_t dev) 3712 { 3713 struct rl_softc *sc; 3714 3715 sc = device_get_softc(dev); 3716 3717 RL_LOCK(sc); 3718 re_stop(sc); 3719 re_setwol(sc); 3720 sc->suspended = 1; 3721 RL_UNLOCK(sc); 3722 3723 return (0); 3724 } 3725 3726 /* 3727 * Device resume routine. Restore some PCI settings in case the BIOS 3728 * doesn't, re-enable busmastering, and restart the interface if 3729 * appropriate. 3730 */ 3731 static int 3732 re_resume(device_t dev) 3733 { 3734 struct rl_softc *sc; 3735 if_t ifp; 3736 3737 sc = device_get_softc(dev); 3738 3739 RL_LOCK(sc); 3740 3741 ifp = sc->rl_ifp; 3742 /* Take controller out of sleep mode. */ 3743 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3744 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3745 CSR_WRITE_1(sc, RL_GPIO, 3746 CSR_READ_1(sc, RL_GPIO) | 0x01); 3747 } 3748 3749 /* 3750 * Clear WOL matching such that normal Rx filtering 3751 * wouldn't interfere with WOL patterns. 3752 */ 3753 re_clrwol(sc); 3754 3755 /* reinitialize interface if necessary */ 3756 if (if_getflags(ifp) & IFF_UP) 3757 re_init_locked(sc); 3758 3759 sc->suspended = 0; 3760 RL_UNLOCK(sc); 3761 3762 return (0); 3763 } 3764 3765 /* 3766 * Stop all chip I/O so that the kernel's probe routines don't 3767 * get confused by errant DMAs when rebooting. 3768 */ 3769 static int 3770 re_shutdown(device_t dev) 3771 { 3772 struct rl_softc *sc; 3773 3774 sc = device_get_softc(dev); 3775 3776 RL_LOCK(sc); 3777 re_stop(sc); 3778 /* 3779 * Mark interface as down since otherwise we will panic if 3780 * interrupt comes in later on, which can happen in some 3781 * cases. 3782 */ 3783 if_setflagbits(sc->rl_ifp, 0, IFF_UP); 3784 re_setwol(sc); 3785 RL_UNLOCK(sc); 3786 3787 return (0); 3788 } 3789 3790 static void 3791 re_set_linkspeed(struct rl_softc *sc) 3792 { 3793 struct mii_softc *miisc; 3794 struct mii_data *mii; 3795 int aneg, i, phyno; 3796 3797 RL_LOCK_ASSERT(sc); 3798 3799 mii = device_get_softc(sc->rl_miibus); 3800 mii_pollstat(mii); 3801 aneg = 0; 3802 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 3803 (IFM_ACTIVE | IFM_AVALID)) { 3804 switch IFM_SUBTYPE(mii->mii_media_active) { 3805 case IFM_10_T: 3806 case IFM_100_TX: 3807 return; 3808 case IFM_1000_T: 3809 aneg++; 3810 break; 3811 default: 3812 break; 3813 } 3814 } 3815 miisc = LIST_FIRST(&mii->mii_phys); 3816 phyno = miisc->mii_phy; 3817 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 3818 PHY_RESET(miisc); 3819 re_miibus_writereg(sc->rl_dev, phyno, MII_100T2CR, 0); 3820 re_miibus_writereg(sc->rl_dev, phyno, 3821 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 3822 re_miibus_writereg(sc->rl_dev, phyno, 3823 MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 3824 DELAY(1000); 3825 if (aneg != 0) { 3826 /* 3827 * Poll link state until re(4) get a 10/100Mbps link. 3828 */ 3829 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 3830 mii_pollstat(mii); 3831 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 3832 == (IFM_ACTIVE | IFM_AVALID)) { 3833 switch (IFM_SUBTYPE(mii->mii_media_active)) { 3834 case IFM_10_T: 3835 case IFM_100_TX: 3836 return; 3837 default: 3838 break; 3839 } 3840 } 3841 RL_UNLOCK(sc); 3842 pause("relnk", hz); 3843 RL_LOCK(sc); 3844 } 3845 if (i == MII_ANEGTICKS_GIGE) 3846 device_printf(sc->rl_dev, 3847 "establishing a link failed, WOL may not work!"); 3848 } 3849 /* 3850 * No link, force MAC to have 100Mbps, full-duplex link. 3851 * MAC does not require reprogramming on resolved speed/duplex, 3852 * so this is just for completeness. 3853 */ 3854 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 3855 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 3856 } 3857 3858 static void 3859 re_setwol(struct rl_softc *sc) 3860 { 3861 if_t ifp; 3862 int pmc; 3863 uint16_t pmstat; 3864 uint8_t v; 3865 3866 RL_LOCK_ASSERT(sc); 3867 3868 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3869 return; 3870 3871 ifp = sc->rl_ifp; 3872 /* Put controller into sleep mode. */ 3873 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3874 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3875 CSR_WRITE_1(sc, RL_GPIO, 3876 CSR_READ_1(sc, RL_GPIO) & ~0x01); 3877 } 3878 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) { 3879 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0) { 3880 /* Disable RXDV gate. */ 3881 CSR_WRITE_4(sc, RL_MISC, CSR_READ_4(sc, RL_MISC) & 3882 ~0x00080000); 3883 } 3884 re_set_rxmode(sc); 3885 if ((sc->rl_flags & RL_FLAG_WOL_MANLINK) != 0) 3886 re_set_linkspeed(sc); 3887 if ((sc->rl_flags & RL_FLAG_WOLRXENB) != 0) 3888 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB); 3889 } 3890 /* Enable config register write. */ 3891 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3892 3893 /* Enable PME. */ 3894 v = CSR_READ_1(sc, sc->rl_cfg1); 3895 v &= ~RL_CFG1_PME; 3896 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 3897 v |= RL_CFG1_PME; 3898 CSR_WRITE_1(sc, sc->rl_cfg1, v); 3899 3900 v = CSR_READ_1(sc, sc->rl_cfg3); 3901 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3902 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 3903 v |= RL_CFG3_WOL_MAGIC; 3904 CSR_WRITE_1(sc, sc->rl_cfg3, v); 3905 3906 v = CSR_READ_1(sc, sc->rl_cfg5); 3907 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST | 3908 RL_CFG5_WOL_LANWAKE); 3909 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) != 0) 3910 v |= RL_CFG5_WOL_UCAST; 3911 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0) 3912 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 3913 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 3914 v |= RL_CFG5_WOL_LANWAKE; 3915 CSR_WRITE_1(sc, sc->rl_cfg5, v); 3916 3917 /* Config register write done. */ 3918 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3919 3920 if ((if_getcapenable(ifp) & IFCAP_WOL) == 0 && 3921 (sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) 3922 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) & ~0x80); 3923 /* 3924 * It seems that hardware resets its link speed to 100Mbps in 3925 * power down mode so switching to 100Mbps in driver is not 3926 * needed. 3927 */ 3928 3929 /* Request PME if WOL is requested. */ 3930 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 3931 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3932 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 3933 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3934 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 3935 } 3936 3937 static void 3938 re_clrwol(struct rl_softc *sc) 3939 { 3940 int pmc; 3941 uint8_t v; 3942 3943 RL_LOCK_ASSERT(sc); 3944 3945 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3946 return; 3947 3948 /* Enable config register write. */ 3949 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3950 3951 v = CSR_READ_1(sc, sc->rl_cfg3); 3952 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3953 CSR_WRITE_1(sc, sc->rl_cfg3, v); 3954 3955 /* Config register write done. */ 3956 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3957 3958 v = CSR_READ_1(sc, sc->rl_cfg5); 3959 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3960 v &= ~RL_CFG5_WOL_LANWAKE; 3961 CSR_WRITE_1(sc, sc->rl_cfg5, v); 3962 } 3963 3964 static void 3965 re_add_sysctls(struct rl_softc *sc) 3966 { 3967 struct sysctl_ctx_list *ctx; 3968 struct sysctl_oid_list *children; 3969 int error; 3970 3971 ctx = device_get_sysctl_ctx(sc->rl_dev); 3972 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev)); 3973 3974 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "stats", 3975 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 3976 re_sysctl_stats, "I", "Statistics Information"); 3977 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) 3978 return; 3979 3980 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "int_rx_mod", 3981 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 3982 &sc->rl_int_rx_mod, 0, sysctl_hw_re_int_mod, "I", 3983 "re RX interrupt moderation"); 3984 /* Pull in device tunables. */ 3985 sc->rl_int_rx_mod = RL_TIMER_DEFAULT; 3986 error = resource_int_value(device_get_name(sc->rl_dev), 3987 device_get_unit(sc->rl_dev), "int_rx_mod", &sc->rl_int_rx_mod); 3988 if (error == 0) { 3989 if (sc->rl_int_rx_mod < RL_TIMER_MIN || 3990 sc->rl_int_rx_mod > RL_TIMER_MAX) { 3991 device_printf(sc->rl_dev, "int_rx_mod value out of " 3992 "range; using default: %d\n", 3993 RL_TIMER_DEFAULT); 3994 sc->rl_int_rx_mod = RL_TIMER_DEFAULT; 3995 } 3996 } 3997 } 3998 3999 static int 4000 re_sysctl_stats(SYSCTL_HANDLER_ARGS) 4001 { 4002 struct rl_softc *sc; 4003 struct rl_stats *stats; 4004 int error, i, result; 4005 4006 result = -1; 4007 error = sysctl_handle_int(oidp, &result, 0, req); 4008 if (error || req->newptr == NULL) 4009 return (error); 4010 4011 if (result == 1) { 4012 sc = (struct rl_softc *)arg1; 4013 RL_LOCK(sc); 4014 if ((if_getdrvflags(sc->rl_ifp) & IFF_DRV_RUNNING) == 0) { 4015 RL_UNLOCK(sc); 4016 goto done; 4017 } 4018 bus_dmamap_sync(sc->rl_ldata.rl_stag, 4019 sc->rl_ldata.rl_smap, BUS_DMASYNC_PREREAD); 4020 CSR_WRITE_4(sc, RL_DUMPSTATS_HI, 4021 RL_ADDR_HI(sc->rl_ldata.rl_stats_addr)); 4022 CSR_WRITE_4(sc, RL_DUMPSTATS_LO, 4023 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr)); 4024 CSR_WRITE_4(sc, RL_DUMPSTATS_LO, 4025 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr | 4026 RL_DUMPSTATS_START)); 4027 for (i = RL_TIMEOUT; i > 0; i--) { 4028 if ((CSR_READ_4(sc, RL_DUMPSTATS_LO) & 4029 RL_DUMPSTATS_START) == 0) 4030 break; 4031 DELAY(1000); 4032 } 4033 bus_dmamap_sync(sc->rl_ldata.rl_stag, 4034 sc->rl_ldata.rl_smap, BUS_DMASYNC_POSTREAD); 4035 RL_UNLOCK(sc); 4036 if (i == 0) { 4037 device_printf(sc->rl_dev, 4038 "DUMP statistics request timed out\n"); 4039 return (ETIMEDOUT); 4040 } 4041 done: 4042 stats = sc->rl_ldata.rl_stats; 4043 printf("%s statistics:\n", device_get_nameunit(sc->rl_dev)); 4044 printf("Tx frames : %ju\n", 4045 (uintmax_t)le64toh(stats->rl_tx_pkts)); 4046 printf("Rx frames : %ju\n", 4047 (uintmax_t)le64toh(stats->rl_rx_pkts)); 4048 printf("Tx errors : %ju\n", 4049 (uintmax_t)le64toh(stats->rl_tx_errs)); 4050 printf("Rx errors : %u\n", 4051 le32toh(stats->rl_rx_errs)); 4052 printf("Rx missed frames : %u\n", 4053 (uint32_t)le16toh(stats->rl_missed_pkts)); 4054 printf("Rx frame alignment errs : %u\n", 4055 (uint32_t)le16toh(stats->rl_rx_framealign_errs)); 4056 printf("Tx single collisions : %u\n", 4057 le32toh(stats->rl_tx_onecoll)); 4058 printf("Tx multiple collisions : %u\n", 4059 le32toh(stats->rl_tx_multicolls)); 4060 printf("Rx unicast frames : %ju\n", 4061 (uintmax_t)le64toh(stats->rl_rx_ucasts)); 4062 printf("Rx broadcast frames : %ju\n", 4063 (uintmax_t)le64toh(stats->rl_rx_bcasts)); 4064 printf("Rx multicast frames : %u\n", 4065 le32toh(stats->rl_rx_mcasts)); 4066 printf("Tx aborts : %u\n", 4067 (uint32_t)le16toh(stats->rl_tx_aborts)); 4068 printf("Tx underruns : %u\n", 4069 (uint32_t)le16toh(stats->rl_rx_underruns)); 4070 } 4071 4072 return (error); 4073 } 4074 4075 static int 4076 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4077 { 4078 int error, value; 4079 4080 if (arg1 == NULL) 4081 return (EINVAL); 4082 value = *(int *)arg1; 4083 error = sysctl_handle_int(oidp, &value, 0, req); 4084 if (error || req->newptr == NULL) 4085 return (error); 4086 if (value < low || value > high) 4087 return (EINVAL); 4088 *(int *)arg1 = value; 4089 4090 return (0); 4091 } 4092 4093 static int 4094 sysctl_hw_re_int_mod(SYSCTL_HANDLER_ARGS) 4095 { 4096 4097 return (sysctl_int_range(oidp, arg1, arg2, req, RL_TIMER_MIN, 4098 RL_TIMER_MAX)); 4099 } 4100 4101 #ifdef DEBUGNET 4102 static void 4103 re_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 4104 { 4105 struct rl_softc *sc; 4106 4107 sc = if_getsoftc(ifp); 4108 RL_LOCK(sc); 4109 *nrxr = sc->rl_ldata.rl_rx_desc_cnt; 4110 *ncl = DEBUGNET_MAX_IN_FLIGHT; 4111 *clsize = (if_getmtu(ifp) > RL_MTU && 4112 (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) ? MJUM9BYTES : MCLBYTES; 4113 RL_UNLOCK(sc); 4114 } 4115 4116 static void 4117 re_debugnet_event(if_t ifp __unused, enum debugnet_ev event __unused) 4118 { 4119 } 4120 4121 static int 4122 re_debugnet_transmit(if_t ifp, struct mbuf *m) 4123 { 4124 struct rl_softc *sc; 4125 int error; 4126 4127 sc = if_getsoftc(ifp); 4128 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 4129 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) 4130 return (EBUSY); 4131 4132 error = re_encap(sc, &m); 4133 if (error == 0) 4134 re_start_tx(sc); 4135 return (error); 4136 } 4137 4138 static int 4139 re_debugnet_poll(if_t ifp, int count) 4140 { 4141 struct rl_softc *sc; 4142 int error; 4143 4144 sc = if_getsoftc(ifp); 4145 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0 || 4146 (sc->rl_flags & RL_FLAG_LINK) == 0) 4147 return (EBUSY); 4148 4149 re_txeof(sc); 4150 error = re_rxeof(sc, NULL); 4151 if (error != 0 && error != EAGAIN) 4152 return (error); 4153 return (0); 4154 } 4155 #endif /* DEBUGNET */ 4156