1 /*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44 /* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111 #ifdef HAVE_KERNEL_OPTION_HEADERS 112 #include "opt_device_polling.h" 113 #endif 114 115 #include <sys/param.h> 116 #include <sys/endian.h> 117 #include <sys/systm.h> 118 #include <sys/sockio.h> 119 #include <sys/mbuf.h> 120 #include <sys/malloc.h> 121 #include <sys/module.h> 122 #include <sys/kernel.h> 123 #include <sys/socket.h> 124 #include <sys/lock.h> 125 #include <sys/mutex.h> 126 #include <sys/taskqueue.h> 127 128 #include <net/if.h> 129 #include <net/if_arp.h> 130 #include <net/ethernet.h> 131 #include <net/if_dl.h> 132 #include <net/if_media.h> 133 #include <net/if_types.h> 134 #include <net/if_vlan_var.h> 135 136 #include <net/bpf.h> 137 138 #include <machine/bus.h> 139 #include <machine/resource.h> 140 #include <sys/bus.h> 141 #include <sys/rman.h> 142 143 #include <dev/mii/mii.h> 144 #include <dev/mii/miivar.h> 145 146 #include <dev/pci/pcireg.h> 147 #include <dev/pci/pcivar.h> 148 149 #include <pci/if_rlreg.h> 150 151 MODULE_DEPEND(re, pci, 1, 1, 1); 152 MODULE_DEPEND(re, ether, 1, 1, 1); 153 MODULE_DEPEND(re, miibus, 1, 1, 1); 154 155 /* "device miibus" required. See GENERIC if you get errors here. */ 156 #include "miibus_if.h" 157 158 /* Tunables. */ 159 static int msi_disable = 0; 160 TUNABLE_INT("hw.re.msi_disable", &msi_disable); 161 static int prefer_iomap = 0; 162 TUNABLE_INT("hw.re.prefer_iomap", &prefer_iomap); 163 164 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 165 166 /* 167 * Various supported device vendors/types and their names. 168 */ 169 static struct rl_type re_devs[] = { 170 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0, 171 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 172 { RT_VENDORID, RT_DEVICEID_8139, 0, 173 "RealTek 8139C+ 10/100BaseTX" }, 174 { RT_VENDORID, RT_DEVICEID_8101E, 0, 175 "RealTek 8101E/8102E/8102EL/8103E PCIe 10/100baseTX" }, 176 { RT_VENDORID, RT_DEVICEID_8168, 0, 177 "RealTek 8168/8111 B/C/CP/D/DP/E PCIe Gigabit Ethernet" }, 178 { RT_VENDORID, RT_DEVICEID_8169, 0, 179 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" }, 180 { RT_VENDORID, RT_DEVICEID_8169SC, 0, 181 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 182 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0, 183 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 184 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0, 185 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 186 { USR_VENDORID, USR_DEVICEID_997902, 0, 187 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 188 }; 189 190 static struct rl_hwrev re_hwrevs[] = { 191 { RL_HWREV_8139, RL_8139, "" }, 192 { RL_HWREV_8139A, RL_8139, "A" }, 193 { RL_HWREV_8139AG, RL_8139, "A-G" }, 194 { RL_HWREV_8139B, RL_8139, "B" }, 195 { RL_HWREV_8130, RL_8139, "8130" }, 196 { RL_HWREV_8139C, RL_8139, "C" }, 197 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 198 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 199 { RL_HWREV_8168_SPIN1, RL_8169, "8168"}, 200 { RL_HWREV_8169, RL_8169, "8169"}, 201 { RL_HWREV_8169S, RL_8169, "8169S"}, 202 { RL_HWREV_8110S, RL_8169, "8110S"}, 203 { RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB"}, 204 { RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC"}, 205 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL"}, 206 { RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC"}, 207 { RL_HWREV_8100, RL_8139, "8100"}, 208 { RL_HWREV_8101, RL_8139, "8101"}, 209 { RL_HWREV_8100E, RL_8169, "8100E"}, 210 { RL_HWREV_8101E, RL_8169, "8101E"}, 211 { RL_HWREV_8102E, RL_8169, "8102E"}, 212 { RL_HWREV_8102EL, RL_8169, "8102EL"}, 213 { RL_HWREV_8102EL_SPIN1, RL_8169, "8102EL"}, 214 { RL_HWREV_8103E, RL_8169, "8103E"}, 215 { RL_HWREV_8168_SPIN2, RL_8169, "8168"}, 216 { RL_HWREV_8168_SPIN3, RL_8169, "8168"}, 217 { RL_HWREV_8168C, RL_8169, "8168C/8111C"}, 218 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C"}, 219 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP"}, 220 { RL_HWREV_8168D, RL_8169, "8168D/8111D"}, 221 { RL_HWREV_8168DP, RL_8169, "8168DP/8111DP"}, 222 { RL_HWREV_8168E, RL_8169, "8168E/8111E"}, 223 { 0, 0, NULL } 224 }; 225 226 static int re_probe (device_t); 227 static int re_attach (device_t); 228 static int re_detach (device_t); 229 230 static int re_encap (struct rl_softc *, struct mbuf **); 231 232 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 233 static int re_allocmem (device_t, struct rl_softc *); 234 static __inline void re_discard_rxbuf 235 (struct rl_softc *, int); 236 static int re_newbuf (struct rl_softc *, int); 237 static int re_rx_list_init (struct rl_softc *); 238 static int re_tx_list_init (struct rl_softc *); 239 #ifdef RE_FIXUP_RX 240 static __inline void re_fixup_rx 241 (struct mbuf *); 242 #endif 243 static int re_rxeof (struct rl_softc *, int *); 244 static void re_txeof (struct rl_softc *); 245 #ifdef DEVICE_POLLING 246 static int re_poll (struct ifnet *, enum poll_cmd, int); 247 static int re_poll_locked (struct ifnet *, enum poll_cmd, int); 248 #endif 249 static int re_intr (void *); 250 static void re_tick (void *); 251 static void re_tx_task (void *, int); 252 static void re_int_task (void *, int); 253 static void re_start (struct ifnet *); 254 static int re_ioctl (struct ifnet *, u_long, caddr_t); 255 static void re_init (void *); 256 static void re_init_locked (struct rl_softc *); 257 static void re_stop (struct rl_softc *); 258 static void re_watchdog (struct rl_softc *); 259 static int re_suspend (device_t); 260 static int re_resume (device_t); 261 static int re_shutdown (device_t); 262 static int re_ifmedia_upd (struct ifnet *); 263 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 264 265 static void re_eeprom_putbyte (struct rl_softc *, int); 266 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 267 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 268 static int re_gmii_readreg (device_t, int, int); 269 static int re_gmii_writereg (device_t, int, int, int); 270 271 static int re_miibus_readreg (device_t, int, int); 272 static int re_miibus_writereg (device_t, int, int, int); 273 static void re_miibus_statchg (device_t); 274 275 static void re_set_rxmode (struct rl_softc *); 276 static void re_reset (struct rl_softc *); 277 static void re_setwol (struct rl_softc *); 278 static void re_clrwol (struct rl_softc *); 279 280 #ifdef RE_DIAG 281 static int re_diag (struct rl_softc *); 282 #endif 283 284 static device_method_t re_methods[] = { 285 /* Device interface */ 286 DEVMETHOD(device_probe, re_probe), 287 DEVMETHOD(device_attach, re_attach), 288 DEVMETHOD(device_detach, re_detach), 289 DEVMETHOD(device_suspend, re_suspend), 290 DEVMETHOD(device_resume, re_resume), 291 DEVMETHOD(device_shutdown, re_shutdown), 292 293 /* bus interface */ 294 DEVMETHOD(bus_print_child, bus_generic_print_child), 295 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 296 297 /* MII interface */ 298 DEVMETHOD(miibus_readreg, re_miibus_readreg), 299 DEVMETHOD(miibus_writereg, re_miibus_writereg), 300 DEVMETHOD(miibus_statchg, re_miibus_statchg), 301 302 { 0, 0 } 303 }; 304 305 static driver_t re_driver = { 306 "re", 307 re_methods, 308 sizeof(struct rl_softc) 309 }; 310 311 static devclass_t re_devclass; 312 313 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 314 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 315 316 #define EE_SET(x) \ 317 CSR_WRITE_1(sc, RL_EECMD, \ 318 CSR_READ_1(sc, RL_EECMD) | x) 319 320 #define EE_CLR(x) \ 321 CSR_WRITE_1(sc, RL_EECMD, \ 322 CSR_READ_1(sc, RL_EECMD) & ~x) 323 324 /* 325 * Send a read command and address to the EEPROM, check for ACK. 326 */ 327 static void 328 re_eeprom_putbyte(struct rl_softc *sc, int addr) 329 { 330 int d, i; 331 332 d = addr | (RL_9346_READ << sc->rl_eewidth); 333 334 /* 335 * Feed in each bit and strobe the clock. 336 */ 337 338 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 339 if (d & i) { 340 EE_SET(RL_EE_DATAIN); 341 } else { 342 EE_CLR(RL_EE_DATAIN); 343 } 344 DELAY(100); 345 EE_SET(RL_EE_CLK); 346 DELAY(150); 347 EE_CLR(RL_EE_CLK); 348 DELAY(100); 349 } 350 } 351 352 /* 353 * Read a word of data stored in the EEPROM at address 'addr.' 354 */ 355 static void 356 re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest) 357 { 358 int i; 359 u_int16_t word = 0; 360 361 /* 362 * Send address of word we want to read. 363 */ 364 re_eeprom_putbyte(sc, addr); 365 366 /* 367 * Start reading bits from EEPROM. 368 */ 369 for (i = 0x8000; i; i >>= 1) { 370 EE_SET(RL_EE_CLK); 371 DELAY(100); 372 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 373 word |= i; 374 EE_CLR(RL_EE_CLK); 375 DELAY(100); 376 } 377 378 *dest = word; 379 } 380 381 /* 382 * Read a sequence of words from the EEPROM. 383 */ 384 static void 385 re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt) 386 { 387 int i; 388 u_int16_t word = 0, *ptr; 389 390 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 391 392 DELAY(100); 393 394 for (i = 0; i < cnt; i++) { 395 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 396 re_eeprom_getword(sc, off + i, &word); 397 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 398 ptr = (u_int16_t *)(dest + (i * 2)); 399 *ptr = word; 400 } 401 402 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 403 } 404 405 static int 406 re_gmii_readreg(device_t dev, int phy, int reg) 407 { 408 struct rl_softc *sc; 409 u_int32_t rval; 410 int i; 411 412 sc = device_get_softc(dev); 413 414 /* Let the rgephy driver read the GMEDIASTAT register */ 415 416 if (reg == RL_GMEDIASTAT) { 417 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 418 return (rval); 419 } 420 421 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 422 DELAY(1000); 423 424 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 425 rval = CSR_READ_4(sc, RL_PHYAR); 426 if (rval & RL_PHYAR_BUSY) 427 break; 428 DELAY(100); 429 } 430 431 if (i == RL_PHY_TIMEOUT) { 432 device_printf(sc->rl_dev, "PHY read failed\n"); 433 return (0); 434 } 435 436 return (rval & RL_PHYAR_PHYDATA); 437 } 438 439 static int 440 re_gmii_writereg(device_t dev, int phy, int reg, int data) 441 { 442 struct rl_softc *sc; 443 u_int32_t rval; 444 int i; 445 446 sc = device_get_softc(dev); 447 448 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 449 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 450 DELAY(1000); 451 452 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 453 rval = CSR_READ_4(sc, RL_PHYAR); 454 if (!(rval & RL_PHYAR_BUSY)) 455 break; 456 DELAY(100); 457 } 458 459 if (i == RL_PHY_TIMEOUT) { 460 device_printf(sc->rl_dev, "PHY write failed\n"); 461 return (0); 462 } 463 464 return (0); 465 } 466 467 static int 468 re_miibus_readreg(device_t dev, int phy, int reg) 469 { 470 struct rl_softc *sc; 471 u_int16_t rval = 0; 472 u_int16_t re8139_reg = 0; 473 474 sc = device_get_softc(dev); 475 476 if (sc->rl_type == RL_8169) { 477 rval = re_gmii_readreg(dev, phy, reg); 478 return (rval); 479 } 480 481 switch (reg) { 482 case MII_BMCR: 483 re8139_reg = RL_BMCR; 484 break; 485 case MII_BMSR: 486 re8139_reg = RL_BMSR; 487 break; 488 case MII_ANAR: 489 re8139_reg = RL_ANAR; 490 break; 491 case MII_ANER: 492 re8139_reg = RL_ANER; 493 break; 494 case MII_ANLPAR: 495 re8139_reg = RL_LPAR; 496 break; 497 case MII_PHYIDR1: 498 case MII_PHYIDR2: 499 return (0); 500 /* 501 * Allow the rlphy driver to read the media status 502 * register. If we have a link partner which does not 503 * support NWAY, this is the register which will tell 504 * us the results of parallel detection. 505 */ 506 case RL_MEDIASTAT: 507 rval = CSR_READ_1(sc, RL_MEDIASTAT); 508 return (rval); 509 default: 510 device_printf(sc->rl_dev, "bad phy register\n"); 511 return (0); 512 } 513 rval = CSR_READ_2(sc, re8139_reg); 514 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 515 /* 8139C+ has different bit layout. */ 516 rval &= ~(BMCR_LOOP | BMCR_ISO); 517 } 518 return (rval); 519 } 520 521 static int 522 re_miibus_writereg(device_t dev, int phy, int reg, int data) 523 { 524 struct rl_softc *sc; 525 u_int16_t re8139_reg = 0; 526 int rval = 0; 527 528 sc = device_get_softc(dev); 529 530 if (sc->rl_type == RL_8169) { 531 rval = re_gmii_writereg(dev, phy, reg, data); 532 return (rval); 533 } 534 535 switch (reg) { 536 case MII_BMCR: 537 re8139_reg = RL_BMCR; 538 if (sc->rl_type == RL_8139CPLUS) { 539 /* 8139C+ has different bit layout. */ 540 data &= ~(BMCR_LOOP | BMCR_ISO); 541 } 542 break; 543 case MII_BMSR: 544 re8139_reg = RL_BMSR; 545 break; 546 case MII_ANAR: 547 re8139_reg = RL_ANAR; 548 break; 549 case MII_ANER: 550 re8139_reg = RL_ANER; 551 break; 552 case MII_ANLPAR: 553 re8139_reg = RL_LPAR; 554 break; 555 case MII_PHYIDR1: 556 case MII_PHYIDR2: 557 return (0); 558 break; 559 default: 560 device_printf(sc->rl_dev, "bad phy register\n"); 561 return (0); 562 } 563 CSR_WRITE_2(sc, re8139_reg, data); 564 return (0); 565 } 566 567 static void 568 re_miibus_statchg(device_t dev) 569 { 570 struct rl_softc *sc; 571 struct ifnet *ifp; 572 struct mii_data *mii; 573 574 sc = device_get_softc(dev); 575 mii = device_get_softc(sc->rl_miibus); 576 ifp = sc->rl_ifp; 577 if (mii == NULL || ifp == NULL || 578 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 579 return; 580 581 sc->rl_flags &= ~RL_FLAG_LINK; 582 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 583 (IFM_ACTIVE | IFM_AVALID)) { 584 switch (IFM_SUBTYPE(mii->mii_media_active)) { 585 case IFM_10_T: 586 case IFM_100_TX: 587 sc->rl_flags |= RL_FLAG_LINK; 588 break; 589 case IFM_1000_T: 590 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0) 591 break; 592 sc->rl_flags |= RL_FLAG_LINK; 593 break; 594 default: 595 break; 596 } 597 } 598 /* 599 * RealTek controllers does not provide any interface to 600 * Tx/Rx MACs for resolved speed, duplex and flow-control 601 * parameters. 602 */ 603 } 604 605 /* 606 * Set the RX configuration and 64-bit multicast hash filter. 607 */ 608 static void 609 re_set_rxmode(struct rl_softc *sc) 610 { 611 struct ifnet *ifp; 612 struct ifmultiaddr *ifma; 613 uint32_t hashes[2] = { 0, 0 }; 614 uint32_t h, rxfilt; 615 616 RL_LOCK_ASSERT(sc); 617 618 ifp = sc->rl_ifp; 619 620 rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD; 621 622 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 623 if (ifp->if_flags & IFF_PROMISC) 624 rxfilt |= RL_RXCFG_RX_ALLPHYS; 625 /* 626 * Unlike other hardwares, we have to explicitly set 627 * RL_RXCFG_RX_MULTI to receive multicast frames in 628 * promiscuous mode. 629 */ 630 rxfilt |= RL_RXCFG_RX_MULTI; 631 hashes[0] = hashes[1] = 0xffffffff; 632 goto done; 633 } 634 635 if_maddr_rlock(ifp); 636 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 637 if (ifma->ifma_addr->sa_family != AF_LINK) 638 continue; 639 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 640 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 641 if (h < 32) 642 hashes[0] |= (1 << h); 643 else 644 hashes[1] |= (1 << (h - 32)); 645 } 646 if_maddr_runlock(ifp); 647 648 if (hashes[0] != 0 || hashes[1] != 0) { 649 /* 650 * For some unfathomable reason, RealTek decided to 651 * reverse the order of the multicast hash registers 652 * in the PCI Express parts. This means we have to 653 * write the hash pattern in reverse order for those 654 * devices. 655 */ 656 if ((sc->rl_flags & RL_FLAG_PCIE) != 0) { 657 h = bswap32(hashes[0]); 658 hashes[0] = bswap32(hashes[1]); 659 hashes[1] = h; 660 } 661 rxfilt |= RL_RXCFG_RX_MULTI; 662 } 663 664 done: 665 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 666 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 667 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 668 } 669 670 static void 671 re_reset(struct rl_softc *sc) 672 { 673 int i; 674 675 RL_LOCK_ASSERT(sc); 676 677 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 678 679 for (i = 0; i < RL_TIMEOUT; i++) { 680 DELAY(10); 681 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 682 break; 683 } 684 if (i == RL_TIMEOUT) 685 device_printf(sc->rl_dev, "reset never completed!\n"); 686 687 if ((sc->rl_flags & RL_FLAG_MACRESET) != 0) 688 CSR_WRITE_1(sc, 0x82, 1); 689 if (sc->rl_hwrev == RL_HWREV_8169S) 690 re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0); 691 } 692 693 #ifdef RE_DIAG 694 695 /* 696 * The following routine is designed to test for a defect on some 697 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 698 * lines connected to the bus, however for a 32-bit only card, they 699 * should be pulled high. The result of this defect is that the 700 * NIC will not work right if you plug it into a 64-bit slot: DMA 701 * operations will be done with 64-bit transfers, which will fail 702 * because the 64-bit data lines aren't connected. 703 * 704 * There's no way to work around this (short of talking a soldering 705 * iron to the board), however we can detect it. The method we use 706 * here is to put the NIC into digital loopback mode, set the receiver 707 * to promiscuous mode, and then try to send a frame. We then compare 708 * the frame data we sent to what was received. If the data matches, 709 * then the NIC is working correctly, otherwise we know the user has 710 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 711 * slot. In the latter case, there's no way the NIC can work correctly, 712 * so we print out a message on the console and abort the device attach. 713 */ 714 715 static int 716 re_diag(struct rl_softc *sc) 717 { 718 struct ifnet *ifp = sc->rl_ifp; 719 struct mbuf *m0; 720 struct ether_header *eh; 721 struct rl_desc *cur_rx; 722 u_int16_t status; 723 u_int32_t rxstat; 724 int total_len, i, error = 0, phyaddr; 725 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 726 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 727 728 /* Allocate a single mbuf */ 729 MGETHDR(m0, M_DONTWAIT, MT_DATA); 730 if (m0 == NULL) 731 return (ENOBUFS); 732 733 RL_LOCK(sc); 734 735 /* 736 * Initialize the NIC in test mode. This sets the chip up 737 * so that it can send and receive frames, but performs the 738 * following special functions: 739 * - Puts receiver in promiscuous mode 740 * - Enables digital loopback mode 741 * - Leaves interrupts turned off 742 */ 743 744 ifp->if_flags |= IFF_PROMISC; 745 sc->rl_testmode = 1; 746 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 747 re_init_locked(sc); 748 sc->rl_flags |= RL_FLAG_LINK; 749 if (sc->rl_type == RL_8169) 750 phyaddr = 1; 751 else 752 phyaddr = 0; 753 754 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 755 for (i = 0; i < RL_TIMEOUT; i++) { 756 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 757 if (!(status & BMCR_RESET)) 758 break; 759 } 760 761 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 762 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 763 764 DELAY(100000); 765 766 /* Put some data in the mbuf */ 767 768 eh = mtod(m0, struct ether_header *); 769 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 770 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 771 eh->ether_type = htons(ETHERTYPE_IP); 772 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 773 774 /* 775 * Queue the packet, start transmission. 776 * Note: IF_HANDOFF() ultimately calls re_start() for us. 777 */ 778 779 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 780 RL_UNLOCK(sc); 781 /* XXX: re_diag must not be called when in ALTQ mode */ 782 IF_HANDOFF(&ifp->if_snd, m0, ifp); 783 RL_LOCK(sc); 784 m0 = NULL; 785 786 /* Wait for it to propagate through the chip */ 787 788 DELAY(100000); 789 for (i = 0; i < RL_TIMEOUT; i++) { 790 status = CSR_READ_2(sc, RL_ISR); 791 CSR_WRITE_2(sc, RL_ISR, status); 792 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 793 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 794 break; 795 DELAY(10); 796 } 797 798 if (i == RL_TIMEOUT) { 799 device_printf(sc->rl_dev, 800 "diagnostic failed, failed to receive packet in" 801 " loopback mode\n"); 802 error = EIO; 803 goto done; 804 } 805 806 /* 807 * The packet should have been dumped into the first 808 * entry in the RX DMA ring. Grab it from there. 809 */ 810 811 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 812 sc->rl_ldata.rl_rx_list_map, 813 BUS_DMASYNC_POSTREAD); 814 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 815 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 816 BUS_DMASYNC_POSTREAD); 817 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 818 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 819 820 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 821 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 822 eh = mtod(m0, struct ether_header *); 823 824 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 825 total_len = RL_RXBYTES(cur_rx); 826 rxstat = le32toh(cur_rx->rl_cmdstat); 827 828 if (total_len != ETHER_MIN_LEN) { 829 device_printf(sc->rl_dev, 830 "diagnostic failed, received short packet\n"); 831 error = EIO; 832 goto done; 833 } 834 835 /* Test that the received packet data matches what we sent. */ 836 837 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 838 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 839 ntohs(eh->ether_type) != ETHERTYPE_IP) { 840 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 841 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 842 dst, ":", src, ":", ETHERTYPE_IP); 843 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 844 eh->ether_dhost, ":", eh->ether_shost, ":", 845 ntohs(eh->ether_type)); 846 device_printf(sc->rl_dev, "You may have a defective 32-bit " 847 "NIC plugged into a 64-bit PCI slot.\n"); 848 device_printf(sc->rl_dev, "Please re-install the NIC in a " 849 "32-bit slot for proper operation.\n"); 850 device_printf(sc->rl_dev, "Read the re(4) man page for more " 851 "details.\n"); 852 error = EIO; 853 } 854 855 done: 856 /* Turn interface off, release resources */ 857 858 sc->rl_testmode = 0; 859 sc->rl_flags &= ~RL_FLAG_LINK; 860 ifp->if_flags &= ~IFF_PROMISC; 861 re_stop(sc); 862 if (m0 != NULL) 863 m_freem(m0); 864 865 RL_UNLOCK(sc); 866 867 return (error); 868 } 869 870 #endif 871 872 /* 873 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 874 * IDs against our list and return a device name if we find a match. 875 */ 876 static int 877 re_probe(device_t dev) 878 { 879 struct rl_type *t; 880 uint16_t devid, vendor; 881 uint16_t revid, sdevid; 882 int i; 883 884 vendor = pci_get_vendor(dev); 885 devid = pci_get_device(dev); 886 revid = pci_get_revid(dev); 887 sdevid = pci_get_subdevice(dev); 888 889 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 890 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 891 /* 892 * Only attach to rev. 3 of the Linksys EG1032 adapter. 893 * Rev. 2 is supported by sk(4). 894 */ 895 return (ENXIO); 896 } 897 } 898 899 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 900 if (revid != 0x20) { 901 /* 8139, let rl(4) take care of this device. */ 902 return (ENXIO); 903 } 904 } 905 906 t = re_devs; 907 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) { 908 if (vendor == t->rl_vid && devid == t->rl_did) { 909 device_set_desc(dev, t->rl_name); 910 return (BUS_PROBE_DEFAULT); 911 } 912 } 913 914 return (ENXIO); 915 } 916 917 /* 918 * Map a single buffer address. 919 */ 920 921 static void 922 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 923 { 924 bus_addr_t *addr; 925 926 if (error) 927 return; 928 929 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 930 addr = arg; 931 *addr = segs->ds_addr; 932 } 933 934 static int 935 re_allocmem(device_t dev, struct rl_softc *sc) 936 { 937 bus_size_t rx_list_size, tx_list_size; 938 int error; 939 int i; 940 941 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 942 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 943 944 /* 945 * Allocate the parent bus DMA tag appropriate for PCI. 946 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD 947 * register should be set. However some RealTek chips are known 948 * to be buggy on DAC handling, therefore disable DAC by limiting 949 * DMA address space to 32bit. PCIe variants of RealTek chips 950 * may not have the limitation but I took safer path. 951 */ 952 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 953 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 954 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 955 NULL, NULL, &sc->rl_parent_tag); 956 if (error) { 957 device_printf(dev, "could not allocate parent DMA tag\n"); 958 return (error); 959 } 960 961 /* 962 * Allocate map for TX mbufs. 963 */ 964 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 965 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 966 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 967 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 968 if (error) { 969 device_printf(dev, "could not allocate TX DMA tag\n"); 970 return (error); 971 } 972 973 /* 974 * Allocate map for RX mbufs. 975 */ 976 977 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 978 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 979 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 980 if (error) { 981 device_printf(dev, "could not allocate RX DMA tag\n"); 982 return (error); 983 } 984 985 /* 986 * Allocate map for TX descriptor list. 987 */ 988 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 989 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 990 NULL, tx_list_size, 1, tx_list_size, 0, 991 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 992 if (error) { 993 device_printf(dev, "could not allocate TX DMA ring tag\n"); 994 return (error); 995 } 996 997 /* Allocate DMA'able memory for the TX ring */ 998 999 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1000 (void **)&sc->rl_ldata.rl_tx_list, 1001 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1002 &sc->rl_ldata.rl_tx_list_map); 1003 if (error) { 1004 device_printf(dev, "could not allocate TX DMA ring\n"); 1005 return (error); 1006 } 1007 1008 /* Load the map for the TX ring. */ 1009 1010 sc->rl_ldata.rl_tx_list_addr = 0; 1011 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1012 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1013 tx_list_size, re_dma_map_addr, 1014 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1015 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 1016 device_printf(dev, "could not load TX DMA ring\n"); 1017 return (ENOMEM); 1018 } 1019 1020 /* Create DMA maps for TX buffers */ 1021 1022 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1023 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1024 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1025 if (error) { 1026 device_printf(dev, "could not create DMA map for TX\n"); 1027 return (error); 1028 } 1029 } 1030 1031 /* 1032 * Allocate map for RX descriptor list. 1033 */ 1034 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1035 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1036 NULL, rx_list_size, 1, rx_list_size, 0, 1037 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1038 if (error) { 1039 device_printf(dev, "could not create RX DMA ring tag\n"); 1040 return (error); 1041 } 1042 1043 /* Allocate DMA'able memory for the RX ring */ 1044 1045 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1046 (void **)&sc->rl_ldata.rl_rx_list, 1047 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1048 &sc->rl_ldata.rl_rx_list_map); 1049 if (error) { 1050 device_printf(dev, "could not allocate RX DMA ring\n"); 1051 return (error); 1052 } 1053 1054 /* Load the map for the RX ring. */ 1055 1056 sc->rl_ldata.rl_rx_list_addr = 0; 1057 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1058 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1059 rx_list_size, re_dma_map_addr, 1060 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1061 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1062 device_printf(dev, "could not load RX DMA ring\n"); 1063 return (ENOMEM); 1064 } 1065 1066 /* Create DMA maps for RX buffers */ 1067 1068 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1069 &sc->rl_ldata.rl_rx_sparemap); 1070 if (error) { 1071 device_printf(dev, "could not create spare DMA map for RX\n"); 1072 return (error); 1073 } 1074 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1075 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1076 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1077 if (error) { 1078 device_printf(dev, "could not create DMA map for RX\n"); 1079 return (error); 1080 } 1081 } 1082 1083 return (0); 1084 } 1085 1086 /* 1087 * Attach the interface. Allocate softc structures, do ifmedia 1088 * setup and ethernet/BPF attach. 1089 */ 1090 static int 1091 re_attach(device_t dev) 1092 { 1093 u_char eaddr[ETHER_ADDR_LEN]; 1094 u_int16_t as[ETHER_ADDR_LEN / 2]; 1095 struct rl_softc *sc; 1096 struct ifnet *ifp; 1097 struct rl_hwrev *hw_rev; 1098 int hwrev; 1099 u_int16_t devid, re_did = 0; 1100 int error = 0, i, phy, rid; 1101 int msic, reg; 1102 uint8_t cfg; 1103 1104 sc = device_get_softc(dev); 1105 sc->rl_dev = dev; 1106 1107 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1108 MTX_DEF); 1109 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1110 1111 /* 1112 * Map control/status registers. 1113 */ 1114 pci_enable_busmaster(dev); 1115 1116 devid = pci_get_device(dev); 1117 /* 1118 * Prefer memory space register mapping over IO space. 1119 * Because RTL8169SC does not seem to work when memory mapping 1120 * is used always activate io mapping. 1121 */ 1122 if (devid == RT_DEVICEID_8169SC) 1123 prefer_iomap = 1; 1124 if (prefer_iomap == 0) { 1125 sc->rl_res_id = PCIR_BAR(1); 1126 sc->rl_res_type = SYS_RES_MEMORY; 1127 /* RTL8168/8101E seems to use different BARs. */ 1128 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E) 1129 sc->rl_res_id = PCIR_BAR(2); 1130 } else { 1131 sc->rl_res_id = PCIR_BAR(0); 1132 sc->rl_res_type = SYS_RES_IOPORT; 1133 } 1134 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1135 &sc->rl_res_id, RF_ACTIVE); 1136 if (sc->rl_res == NULL && prefer_iomap == 0) { 1137 sc->rl_res_id = PCIR_BAR(0); 1138 sc->rl_res_type = SYS_RES_IOPORT; 1139 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1140 &sc->rl_res_id, RF_ACTIVE); 1141 } 1142 if (sc->rl_res == NULL) { 1143 device_printf(dev, "couldn't map ports/memory\n"); 1144 error = ENXIO; 1145 goto fail; 1146 } 1147 1148 sc->rl_btag = rman_get_bustag(sc->rl_res); 1149 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1150 1151 msic = 0; 1152 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 1153 sc->rl_flags |= RL_FLAG_PCIE; 1154 if (devid != RT_DEVICEID_8101E) { 1155 /* Set PCIe maximum read request size to 2048. */ 1156 if (pci_get_max_read_req(dev) < 2048) 1157 pci_set_max_read_req(dev, 2048); 1158 } 1159 msic = pci_msi_count(dev); 1160 if (bootverbose) 1161 device_printf(dev, "MSI count : %d\n", msic); 1162 } 1163 if (msic > 0 && msi_disable == 0) { 1164 msic = 1; 1165 if (pci_alloc_msi(dev, &msic) == 0) { 1166 if (msic == RL_MSI_MESSAGES) { 1167 device_printf(dev, "Using %d MSI messages\n", 1168 msic); 1169 sc->rl_flags |= RL_FLAG_MSI; 1170 /* Explicitly set MSI enable bit. */ 1171 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1172 cfg = CSR_READ_1(sc, RL_CFG2); 1173 cfg |= RL_CFG2_MSI; 1174 CSR_WRITE_1(sc, RL_CFG2, cfg); 1175 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1176 } else 1177 pci_release_msi(dev); 1178 } 1179 } 1180 1181 /* Allocate interrupt */ 1182 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1183 rid = 0; 1184 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1185 RF_SHAREABLE | RF_ACTIVE); 1186 if (sc->rl_irq[0] == NULL) { 1187 device_printf(dev, "couldn't allocate IRQ resources\n"); 1188 error = ENXIO; 1189 goto fail; 1190 } 1191 } else { 1192 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1193 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1194 SYS_RES_IRQ, &rid, RF_ACTIVE); 1195 if (sc->rl_irq[i] == NULL) { 1196 device_printf(dev, 1197 "couldn't llocate IRQ resources for " 1198 "message %d\n", rid); 1199 error = ENXIO; 1200 goto fail; 1201 } 1202 } 1203 } 1204 1205 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1206 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1207 cfg = CSR_READ_1(sc, RL_CFG2); 1208 if ((cfg & RL_CFG2_MSI) != 0) { 1209 device_printf(dev, "turning off MSI enable bit.\n"); 1210 cfg &= ~RL_CFG2_MSI; 1211 CSR_WRITE_1(sc, RL_CFG2, cfg); 1212 } 1213 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1214 } 1215 1216 /* Reset the adapter. */ 1217 RL_LOCK(sc); 1218 re_reset(sc); 1219 RL_UNLOCK(sc); 1220 1221 hw_rev = re_hwrevs; 1222 hwrev = CSR_READ_4(sc, RL_TXCFG); 1223 switch (hwrev & 0x70000000) { 1224 case 0x00000000: 1225 case 0x10000000: 1226 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000); 1227 hwrev &= (RL_TXCFG_HWREV | 0x80000000); 1228 break; 1229 default: 1230 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000); 1231 hwrev &= RL_TXCFG_HWREV; 1232 break; 1233 } 1234 device_printf(dev, "MAC rev. 0x%08x\n", hwrev & 0x00700000); 1235 while (hw_rev->rl_desc != NULL) { 1236 if (hw_rev->rl_rev == hwrev) { 1237 sc->rl_type = hw_rev->rl_type; 1238 sc->rl_hwrev = hw_rev->rl_rev; 1239 break; 1240 } 1241 hw_rev++; 1242 } 1243 if (hw_rev->rl_desc == NULL) { 1244 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev); 1245 error = ENXIO; 1246 goto fail; 1247 } 1248 1249 switch (hw_rev->rl_rev) { 1250 case RL_HWREV_8139CPLUS: 1251 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_FASTETHER | 1252 RL_FLAG_AUTOPAD; 1253 break; 1254 case RL_HWREV_8100E: 1255 case RL_HWREV_8101E: 1256 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_PHYWAKE | 1257 RL_FLAG_FASTETHER; 1258 break; 1259 case RL_HWREV_8102E: 1260 case RL_HWREV_8102EL: 1261 case RL_HWREV_8102EL_SPIN1: 1262 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_PHYWAKE | 1263 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1264 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD; 1265 break; 1266 case RL_HWREV_8103E: 1267 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_PHYWAKE | 1268 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1269 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | 1270 RL_FLAG_MACSLEEP; 1271 break; 1272 case RL_HWREV_8168_SPIN1: 1273 case RL_HWREV_8168_SPIN2: 1274 sc->rl_flags |= RL_FLAG_WOLRXENB; 1275 /* FALLTHROUGH */ 1276 case RL_HWREV_8168_SPIN3: 1277 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT; 1278 break; 1279 case RL_HWREV_8168C_SPIN2: 1280 sc->rl_flags |= RL_FLAG_MACSLEEP; 1281 /* FALLTHROUGH */ 1282 case RL_HWREV_8168C: 1283 if ((hwrev & 0x00700000) == 0x00200000) 1284 sc->rl_flags |= RL_FLAG_MACSLEEP; 1285 /* FALLTHROUGH */ 1286 case RL_HWREV_8168CP: 1287 case RL_HWREV_8168D: 1288 case RL_HWREV_8168DP: 1289 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1290 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1291 RL_FLAG_AUTOPAD; 1292 /* 1293 * These controllers support jumbo frame but it seems 1294 * that enabling it requires touching additional magic 1295 * registers. Depending on MAC revisions some 1296 * controllers need to disable checksum offload. So 1297 * disable jumbo frame until I have better idea what 1298 * it really requires to make it support. 1299 * RTL8168C/CP : supports up to 6KB jumbo frame. 1300 * RTL8111C/CP : supports up to 9KB jumbo frame. 1301 */ 1302 sc->rl_flags |= RL_FLAG_NOJUMBO; 1303 break; 1304 case RL_HWREV_8168E: 1305 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1306 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1307 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_NOJUMBO; 1308 break; 1309 case RL_HWREV_8169_8110SB: 1310 case RL_HWREV_8169_8110SBL: 1311 case RL_HWREV_8169_8110SC: 1312 case RL_HWREV_8169_8110SCE: 1313 sc->rl_flags |= RL_FLAG_PHYWAKE; 1314 /* FALLTHROUGH */ 1315 case RL_HWREV_8169: 1316 case RL_HWREV_8169S: 1317 case RL_HWREV_8110S: 1318 sc->rl_flags |= RL_FLAG_MACRESET; 1319 break; 1320 default: 1321 break; 1322 } 1323 1324 /* Enable PME. */ 1325 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1326 cfg = CSR_READ_1(sc, RL_CFG1); 1327 cfg |= RL_CFG1_PME; 1328 CSR_WRITE_1(sc, RL_CFG1, cfg); 1329 cfg = CSR_READ_1(sc, RL_CFG5); 1330 cfg &= RL_CFG5_PME_STS; 1331 CSR_WRITE_1(sc, RL_CFG5, cfg); 1332 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1333 1334 if ((sc->rl_flags & RL_FLAG_PAR) != 0) { 1335 /* 1336 * XXX Should have a better way to extract station 1337 * address from EEPROM. 1338 */ 1339 for (i = 0; i < ETHER_ADDR_LEN; i++) 1340 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1341 } else { 1342 sc->rl_eewidth = RL_9356_ADDR_LEN; 1343 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1344 if (re_did != 0x8129) 1345 sc->rl_eewidth = RL_9346_ADDR_LEN; 1346 1347 /* 1348 * Get station address from the EEPROM. 1349 */ 1350 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1351 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1352 as[i] = le16toh(as[i]); 1353 bcopy(as, eaddr, sizeof(eaddr)); 1354 } 1355 1356 if (sc->rl_type == RL_8169) { 1357 /* Set RX length mask and number of descriptors. */ 1358 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1359 sc->rl_txstart = RL_GTXSTART; 1360 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1361 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1362 } else { 1363 /* Set RX length mask and number of descriptors. */ 1364 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1365 sc->rl_txstart = RL_TXSTART; 1366 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1367 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1368 } 1369 1370 error = re_allocmem(dev, sc); 1371 if (error) 1372 goto fail; 1373 1374 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1375 if (ifp == NULL) { 1376 device_printf(dev, "can not if_alloc()\n"); 1377 error = ENOSPC; 1378 goto fail; 1379 } 1380 1381 /* Take controller out of deep sleep mode. */ 1382 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 1383 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 1384 CSR_WRITE_1(sc, RL_GPIO, 1385 CSR_READ_1(sc, RL_GPIO) | 0x01); 1386 else 1387 CSR_WRITE_1(sc, RL_GPIO, 1388 CSR_READ_1(sc, RL_GPIO) & ~0x01); 1389 } 1390 1391 /* Take PHY out of power down mode. */ 1392 if ((sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) 1393 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80); 1394 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) { 1395 re_gmii_writereg(dev, 1, 0x1f, 0); 1396 re_gmii_writereg(dev, 1, 0x0e, 0); 1397 } 1398 1399 #define RE_PHYAD_INTERNAL 0 1400 1401 /* Do MII setup. */ 1402 phy = RE_PHYAD_INTERNAL; 1403 if (sc->rl_type == RL_8169) 1404 phy = 1; 1405 error = mii_attach(dev, &sc->rl_miibus, ifp, re_ifmedia_upd, 1406 re_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0); 1407 if (error != 0) { 1408 device_printf(dev, "attaching PHYs failed\n"); 1409 goto fail; 1410 } 1411 1412 ifp->if_softc = sc; 1413 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1414 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1415 ifp->if_ioctl = re_ioctl; 1416 ifp->if_start = re_start; 1417 ifp->if_hwassist = RE_CSUM_FEATURES; 1418 ifp->if_capabilities = IFCAP_HWCSUM; 1419 ifp->if_capenable = ifp->if_capabilities; 1420 ifp->if_init = re_init; 1421 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1422 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1423 IFQ_SET_READY(&ifp->if_snd); 1424 1425 TASK_INIT(&sc->rl_txtask, 1, re_tx_task, ifp); 1426 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1427 1428 /* 1429 * XXX 1430 * Still have no idea how to make TSO work on 8168C, 8168CP, 1431 * 8111C and 8111CP. 1432 */ 1433 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 1434 ifp->if_hwassist |= CSUM_TSO; 1435 ifp->if_capabilities |= IFCAP_TSO4 | IFCAP_VLAN_HWTSO; 1436 } 1437 1438 /* 1439 * Call MI attach routine. 1440 */ 1441 ether_ifattach(ifp, eaddr); 1442 1443 /* VLAN capability setup */ 1444 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1445 if (ifp->if_capabilities & IFCAP_HWCSUM) 1446 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1447 /* Enable WOL if PM is supported. */ 1448 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, ®) == 0) 1449 ifp->if_capabilities |= IFCAP_WOL; 1450 ifp->if_capenable = ifp->if_capabilities; 1451 /* 1452 * Don't enable TSO by default. Under certain 1453 * circumtances the controller generated corrupted 1454 * packets in TSO size. 1455 */ 1456 ifp->if_hwassist &= ~CSUM_TSO; 1457 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO); 1458 #ifdef DEVICE_POLLING 1459 ifp->if_capabilities |= IFCAP_POLLING; 1460 #endif 1461 /* 1462 * Tell the upper layer(s) we support long frames. 1463 * Must appear after the call to ether_ifattach() because 1464 * ether_ifattach() sets ifi_hdrlen to the default value. 1465 */ 1466 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1467 1468 #ifdef RE_DIAG 1469 /* 1470 * Perform hardware diagnostic on the original RTL8169. 1471 * Some 32-bit cards were incorrectly wired and would 1472 * malfunction if plugged into a 64-bit slot. 1473 */ 1474 1475 if (hwrev == RL_HWREV_8169) { 1476 error = re_diag(sc); 1477 if (error) { 1478 device_printf(dev, 1479 "attach aborted due to hardware diag failure\n"); 1480 ether_ifdetach(ifp); 1481 goto fail; 1482 } 1483 } 1484 #endif 1485 1486 /* Hook interrupt last to avoid having to lock softc */ 1487 if ((sc->rl_flags & RL_FLAG_MSI) == 0) 1488 error = bus_setup_intr(dev, sc->rl_irq[0], 1489 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1490 &sc->rl_intrhand[0]); 1491 else { 1492 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1493 error = bus_setup_intr(dev, sc->rl_irq[i], 1494 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1495 &sc->rl_intrhand[i]); 1496 if (error != 0) 1497 break; 1498 } 1499 } 1500 if (error) { 1501 device_printf(dev, "couldn't set up irq\n"); 1502 ether_ifdetach(ifp); 1503 } 1504 1505 fail: 1506 1507 if (error) 1508 re_detach(dev); 1509 1510 return (error); 1511 } 1512 1513 /* 1514 * Shutdown hardware and free up resources. This can be called any 1515 * time after the mutex has been initialized. It is called in both 1516 * the error case in attach and the normal detach case so it needs 1517 * to be careful about only freeing resources that have actually been 1518 * allocated. 1519 */ 1520 static int 1521 re_detach(device_t dev) 1522 { 1523 struct rl_softc *sc; 1524 struct ifnet *ifp; 1525 int i, rid; 1526 1527 sc = device_get_softc(dev); 1528 ifp = sc->rl_ifp; 1529 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1530 1531 /* These should only be active if attach succeeded */ 1532 if (device_is_attached(dev)) { 1533 #ifdef DEVICE_POLLING 1534 if (ifp->if_capenable & IFCAP_POLLING) 1535 ether_poll_deregister(ifp); 1536 #endif 1537 RL_LOCK(sc); 1538 #if 0 1539 sc->suspended = 1; 1540 #endif 1541 re_stop(sc); 1542 RL_UNLOCK(sc); 1543 callout_drain(&sc->rl_stat_callout); 1544 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1545 taskqueue_drain(taskqueue_fast, &sc->rl_txtask); 1546 /* 1547 * Force off the IFF_UP flag here, in case someone 1548 * still had a BPF descriptor attached to this 1549 * interface. If they do, ether_ifdetach() will cause 1550 * the BPF code to try and clear the promisc mode 1551 * flag, which will bubble down to re_ioctl(), 1552 * which will try to call re_init() again. This will 1553 * turn the NIC back on and restart the MII ticker, 1554 * which will panic the system when the kernel tries 1555 * to invoke the re_tick() function that isn't there 1556 * anymore. 1557 */ 1558 ifp->if_flags &= ~IFF_UP; 1559 ether_ifdetach(ifp); 1560 } 1561 if (sc->rl_miibus) 1562 device_delete_child(dev, sc->rl_miibus); 1563 bus_generic_detach(dev); 1564 1565 /* 1566 * The rest is resource deallocation, so we should already be 1567 * stopped here. 1568 */ 1569 1570 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1571 if (sc->rl_intrhand[i] != NULL) { 1572 bus_teardown_intr(dev, sc->rl_irq[i], 1573 sc->rl_intrhand[i]); 1574 sc->rl_intrhand[i] = NULL; 1575 } 1576 } 1577 if (ifp != NULL) 1578 if_free(ifp); 1579 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1580 if (sc->rl_irq[0] != NULL) { 1581 bus_release_resource(dev, SYS_RES_IRQ, 0, 1582 sc->rl_irq[0]); 1583 sc->rl_irq[0] = NULL; 1584 } 1585 } else { 1586 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1587 if (sc->rl_irq[i] != NULL) { 1588 bus_release_resource(dev, SYS_RES_IRQ, rid, 1589 sc->rl_irq[i]); 1590 sc->rl_irq[i] = NULL; 1591 } 1592 } 1593 pci_release_msi(dev); 1594 } 1595 if (sc->rl_res) 1596 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, 1597 sc->rl_res); 1598 1599 /* Unload and free the RX DMA ring memory and map */ 1600 1601 if (sc->rl_ldata.rl_rx_list_tag) { 1602 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1603 sc->rl_ldata.rl_rx_list_map); 1604 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1605 sc->rl_ldata.rl_rx_list, 1606 sc->rl_ldata.rl_rx_list_map); 1607 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1608 } 1609 1610 /* Unload and free the TX DMA ring memory and map */ 1611 1612 if (sc->rl_ldata.rl_tx_list_tag) { 1613 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1614 sc->rl_ldata.rl_tx_list_map); 1615 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1616 sc->rl_ldata.rl_tx_list, 1617 sc->rl_ldata.rl_tx_list_map); 1618 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1619 } 1620 1621 /* Destroy all the RX and TX buffer maps */ 1622 1623 if (sc->rl_ldata.rl_tx_mtag) { 1624 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1625 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1626 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1627 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1628 } 1629 if (sc->rl_ldata.rl_rx_mtag) { 1630 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) 1631 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1632 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1633 if (sc->rl_ldata.rl_rx_sparemap) 1634 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1635 sc->rl_ldata.rl_rx_sparemap); 1636 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1637 } 1638 1639 /* Unload and free the stats buffer and map */ 1640 1641 if (sc->rl_ldata.rl_stag) { 1642 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1643 sc->rl_ldata.rl_rx_list_map); 1644 bus_dmamem_free(sc->rl_ldata.rl_stag, 1645 sc->rl_ldata.rl_stats, 1646 sc->rl_ldata.rl_smap); 1647 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1648 } 1649 1650 if (sc->rl_parent_tag) 1651 bus_dma_tag_destroy(sc->rl_parent_tag); 1652 1653 mtx_destroy(&sc->rl_mtx); 1654 1655 return (0); 1656 } 1657 1658 static __inline void 1659 re_discard_rxbuf(struct rl_softc *sc, int idx) 1660 { 1661 struct rl_desc *desc; 1662 struct rl_rxdesc *rxd; 1663 uint32_t cmdstat; 1664 1665 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1666 desc = &sc->rl_ldata.rl_rx_list[idx]; 1667 desc->rl_vlanctl = 0; 1668 cmdstat = rxd->rx_size; 1669 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1670 cmdstat |= RL_RDESC_CMD_EOR; 1671 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1672 } 1673 1674 static int 1675 re_newbuf(struct rl_softc *sc, int idx) 1676 { 1677 struct mbuf *m; 1678 struct rl_rxdesc *rxd; 1679 bus_dma_segment_t segs[1]; 1680 bus_dmamap_t map; 1681 struct rl_desc *desc; 1682 uint32_t cmdstat; 1683 int error, nsegs; 1684 1685 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1686 if (m == NULL) 1687 return (ENOBUFS); 1688 1689 m->m_len = m->m_pkthdr.len = MCLBYTES; 1690 #ifdef RE_FIXUP_RX 1691 /* 1692 * This is part of an evil trick to deal with non-x86 platforms. 1693 * The RealTek chip requires RX buffers to be aligned on 64-bit 1694 * boundaries, but that will hose non-x86 machines. To get around 1695 * this, we leave some empty space at the start of each buffer 1696 * and for non-x86 hosts, we copy the buffer back six bytes 1697 * to achieve word alignment. This is slightly more efficient 1698 * than allocating a new buffer, copying the contents, and 1699 * discarding the old buffer. 1700 */ 1701 m_adj(m, RE_ETHER_ALIGN); 1702 #endif 1703 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1704 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1705 if (error != 0) { 1706 m_freem(m); 1707 return (ENOBUFS); 1708 } 1709 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1710 1711 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1712 if (rxd->rx_m != NULL) { 1713 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1714 BUS_DMASYNC_POSTREAD); 1715 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1716 } 1717 1718 rxd->rx_m = m; 1719 map = rxd->rx_dmamap; 1720 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1721 rxd->rx_size = segs[0].ds_len; 1722 sc->rl_ldata.rl_rx_sparemap = map; 1723 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1724 BUS_DMASYNC_PREREAD); 1725 1726 desc = &sc->rl_ldata.rl_rx_list[idx]; 1727 desc->rl_vlanctl = 0; 1728 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1729 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1730 cmdstat = segs[0].ds_len; 1731 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1732 cmdstat |= RL_RDESC_CMD_EOR; 1733 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1734 1735 return (0); 1736 } 1737 1738 #ifdef RE_FIXUP_RX 1739 static __inline void 1740 re_fixup_rx(struct mbuf *m) 1741 { 1742 int i; 1743 uint16_t *src, *dst; 1744 1745 src = mtod(m, uint16_t *); 1746 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1747 1748 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1749 *dst++ = *src++; 1750 1751 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1752 } 1753 #endif 1754 1755 static int 1756 re_tx_list_init(struct rl_softc *sc) 1757 { 1758 struct rl_desc *desc; 1759 int i; 1760 1761 RL_LOCK_ASSERT(sc); 1762 1763 bzero(sc->rl_ldata.rl_tx_list, 1764 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 1765 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1766 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 1767 /* Set EOR. */ 1768 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 1769 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 1770 1771 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1772 sc->rl_ldata.rl_tx_list_map, 1773 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1774 1775 sc->rl_ldata.rl_tx_prodidx = 0; 1776 sc->rl_ldata.rl_tx_considx = 0; 1777 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 1778 1779 return (0); 1780 } 1781 1782 static int 1783 re_rx_list_init(struct rl_softc *sc) 1784 { 1785 int error, i; 1786 1787 bzero(sc->rl_ldata.rl_rx_list, 1788 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 1789 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1790 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 1791 if ((error = re_newbuf(sc, i)) != 0) 1792 return (error); 1793 } 1794 1795 /* Flush the RX descriptors */ 1796 1797 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1798 sc->rl_ldata.rl_rx_list_map, 1799 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1800 1801 sc->rl_ldata.rl_rx_prodidx = 0; 1802 sc->rl_head = sc->rl_tail = NULL; 1803 1804 return (0); 1805 } 1806 1807 /* 1808 * RX handler for C+ and 8169. For the gigE chips, we support 1809 * the reception of jumbo frames that have been fragmented 1810 * across multiple 2K mbuf cluster buffers. 1811 */ 1812 static int 1813 re_rxeof(struct rl_softc *sc, int *rx_npktsp) 1814 { 1815 struct mbuf *m; 1816 struct ifnet *ifp; 1817 int i, total_len; 1818 struct rl_desc *cur_rx; 1819 u_int32_t rxstat, rxvlan; 1820 int maxpkt = 16, rx_npkts = 0; 1821 1822 RL_LOCK_ASSERT(sc); 1823 1824 ifp = sc->rl_ifp; 1825 1826 /* Invalidate the descriptor memory */ 1827 1828 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1829 sc->rl_ldata.rl_rx_list_map, 1830 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1831 1832 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 1833 i = RL_RX_DESC_NXT(sc, i)) { 1834 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1835 break; 1836 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1837 rxstat = le32toh(cur_rx->rl_cmdstat); 1838 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 1839 break; 1840 total_len = rxstat & sc->rl_rxlenmask; 1841 rxvlan = le32toh(cur_rx->rl_vlanctl); 1842 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 1843 1844 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1845 if (re_newbuf(sc, i) != 0) { 1846 /* 1847 * If this is part of a multi-fragment packet, 1848 * discard all the pieces. 1849 */ 1850 if (sc->rl_head != NULL) { 1851 m_freem(sc->rl_head); 1852 sc->rl_head = sc->rl_tail = NULL; 1853 } 1854 re_discard_rxbuf(sc, i); 1855 continue; 1856 } 1857 m->m_len = RE_RX_DESC_BUFLEN; 1858 if (sc->rl_head == NULL) 1859 sc->rl_head = sc->rl_tail = m; 1860 else { 1861 m->m_flags &= ~M_PKTHDR; 1862 sc->rl_tail->m_next = m; 1863 sc->rl_tail = m; 1864 } 1865 continue; 1866 } 1867 1868 /* 1869 * NOTE: for the 8139C+, the frame length field 1870 * is always 12 bits in size, but for the gigE chips, 1871 * it is 13 bits (since the max RX frame length is 16K). 1872 * Unfortunately, all 32 bits in the status word 1873 * were already used, so to make room for the extra 1874 * length bit, RealTek took out the 'frame alignment 1875 * error' bit and shifted the other status bits 1876 * over one slot. The OWN, EOR, FS and LS bits are 1877 * still in the same places. We have already extracted 1878 * the frame length and checked the OWN bit, so rather 1879 * than using an alternate bit mapping, we shift the 1880 * status bits one space to the right so we can evaluate 1881 * them using the 8169 status as though it was in the 1882 * same format as that of the 8139C+. 1883 */ 1884 if (sc->rl_type == RL_8169) 1885 rxstat >>= 1; 1886 1887 /* 1888 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 1889 * set, but if CRC is clear, it will still be a valid frame. 1890 */ 1891 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 && 1892 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) { 1893 ifp->if_ierrors++; 1894 /* 1895 * If this is part of a multi-fragment packet, 1896 * discard all the pieces. 1897 */ 1898 if (sc->rl_head != NULL) { 1899 m_freem(sc->rl_head); 1900 sc->rl_head = sc->rl_tail = NULL; 1901 } 1902 re_discard_rxbuf(sc, i); 1903 continue; 1904 } 1905 1906 /* 1907 * If allocating a replacement mbuf fails, 1908 * reload the current one. 1909 */ 1910 1911 if (re_newbuf(sc, i) != 0) { 1912 ifp->if_iqdrops++; 1913 if (sc->rl_head != NULL) { 1914 m_freem(sc->rl_head); 1915 sc->rl_head = sc->rl_tail = NULL; 1916 } 1917 re_discard_rxbuf(sc, i); 1918 continue; 1919 } 1920 1921 if (sc->rl_head != NULL) { 1922 m->m_len = total_len % RE_RX_DESC_BUFLEN; 1923 if (m->m_len == 0) 1924 m->m_len = RE_RX_DESC_BUFLEN; 1925 /* 1926 * Special case: if there's 4 bytes or less 1927 * in this buffer, the mbuf can be discarded: 1928 * the last 4 bytes is the CRC, which we don't 1929 * care about anyway. 1930 */ 1931 if (m->m_len <= ETHER_CRC_LEN) { 1932 sc->rl_tail->m_len -= 1933 (ETHER_CRC_LEN - m->m_len); 1934 m_freem(m); 1935 } else { 1936 m->m_len -= ETHER_CRC_LEN; 1937 m->m_flags &= ~M_PKTHDR; 1938 sc->rl_tail->m_next = m; 1939 } 1940 m = sc->rl_head; 1941 sc->rl_head = sc->rl_tail = NULL; 1942 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1943 } else 1944 m->m_pkthdr.len = m->m_len = 1945 (total_len - ETHER_CRC_LEN); 1946 1947 #ifdef RE_FIXUP_RX 1948 re_fixup_rx(m); 1949 #endif 1950 ifp->if_ipackets++; 1951 m->m_pkthdr.rcvif = ifp; 1952 1953 /* Do RX checksumming if enabled */ 1954 1955 if (ifp->if_capenable & IFCAP_RXCSUM) { 1956 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 1957 /* Check IP header checksum */ 1958 if (rxstat & RL_RDESC_STAT_PROTOID) 1959 m->m_pkthdr.csum_flags |= 1960 CSUM_IP_CHECKED; 1961 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1962 m->m_pkthdr.csum_flags |= 1963 CSUM_IP_VALID; 1964 1965 /* Check TCP/UDP checksum */ 1966 if ((RL_TCPPKT(rxstat) && 1967 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1968 (RL_UDPPKT(rxstat) && 1969 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1970 m->m_pkthdr.csum_flags |= 1971 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1972 m->m_pkthdr.csum_data = 0xffff; 1973 } 1974 } else { 1975 /* 1976 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP 1977 */ 1978 if ((rxstat & RL_RDESC_STAT_PROTOID) && 1979 (rxvlan & RL_RDESC_IPV4)) 1980 m->m_pkthdr.csum_flags |= 1981 CSUM_IP_CHECKED; 1982 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) && 1983 (rxvlan & RL_RDESC_IPV4)) 1984 m->m_pkthdr.csum_flags |= 1985 CSUM_IP_VALID; 1986 if (((rxstat & RL_RDESC_STAT_TCP) && 1987 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1988 ((rxstat & RL_RDESC_STAT_UDP) && 1989 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1990 m->m_pkthdr.csum_flags |= 1991 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1992 m->m_pkthdr.csum_data = 0xffff; 1993 } 1994 } 1995 } 1996 maxpkt--; 1997 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 1998 m->m_pkthdr.ether_vtag = 1999 bswap16((rxvlan & RL_RDESC_VLANCTL_DATA)); 2000 m->m_flags |= M_VLANTAG; 2001 } 2002 RL_UNLOCK(sc); 2003 (*ifp->if_input)(ifp, m); 2004 RL_LOCK(sc); 2005 rx_npkts++; 2006 } 2007 2008 /* Flush the RX DMA ring */ 2009 2010 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2011 sc->rl_ldata.rl_rx_list_map, 2012 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2013 2014 sc->rl_ldata.rl_rx_prodidx = i; 2015 2016 if (rx_npktsp != NULL) 2017 *rx_npktsp = rx_npkts; 2018 if (maxpkt) 2019 return(EAGAIN); 2020 2021 return(0); 2022 } 2023 2024 static void 2025 re_txeof(struct rl_softc *sc) 2026 { 2027 struct ifnet *ifp; 2028 struct rl_txdesc *txd; 2029 u_int32_t txstat; 2030 int cons; 2031 2032 cons = sc->rl_ldata.rl_tx_considx; 2033 if (cons == sc->rl_ldata.rl_tx_prodidx) 2034 return; 2035 2036 ifp = sc->rl_ifp; 2037 /* Invalidate the TX descriptor list */ 2038 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2039 sc->rl_ldata.rl_tx_list_map, 2040 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2041 2042 for (; cons != sc->rl_ldata.rl_tx_prodidx; 2043 cons = RL_TX_DESC_NXT(sc, cons)) { 2044 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 2045 if (txstat & RL_TDESC_STAT_OWN) 2046 break; 2047 /* 2048 * We only stash mbufs in the last descriptor 2049 * in a fragment chain, which also happens to 2050 * be the only place where the TX status bits 2051 * are valid. 2052 */ 2053 if (txstat & RL_TDESC_CMD_EOF) { 2054 txd = &sc->rl_ldata.rl_tx_desc[cons]; 2055 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2056 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2057 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2058 txd->tx_dmamap); 2059 KASSERT(txd->tx_m != NULL, 2060 ("%s: freeing NULL mbufs!", __func__)); 2061 m_freem(txd->tx_m); 2062 txd->tx_m = NULL; 2063 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 2064 RL_TDESC_STAT_COLCNT)) 2065 ifp->if_collisions++; 2066 if (txstat & RL_TDESC_STAT_TXERRSUM) 2067 ifp->if_oerrors++; 2068 else 2069 ifp->if_opackets++; 2070 } 2071 sc->rl_ldata.rl_tx_free++; 2072 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2073 } 2074 sc->rl_ldata.rl_tx_considx = cons; 2075 2076 /* No changes made to the TX ring, so no flush needed */ 2077 2078 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 2079 #ifdef RE_TX_MODERATION 2080 /* 2081 * If not all descriptors have been reaped yet, reload 2082 * the timer so that we will eventually get another 2083 * interrupt that will cause us to re-enter this routine. 2084 * This is done in case the transmitter has gone idle. 2085 */ 2086 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2087 #endif 2088 } else 2089 sc->rl_watchdog_timer = 0; 2090 } 2091 2092 static void 2093 re_tick(void *xsc) 2094 { 2095 struct rl_softc *sc; 2096 struct mii_data *mii; 2097 2098 sc = xsc; 2099 2100 RL_LOCK_ASSERT(sc); 2101 2102 mii = device_get_softc(sc->rl_miibus); 2103 mii_tick(mii); 2104 if ((sc->rl_flags & RL_FLAG_LINK) == 0) 2105 re_miibus_statchg(sc->rl_dev); 2106 /* 2107 * Reclaim transmitted frames here. Technically it is not 2108 * necessary to do here but it ensures periodic reclamation 2109 * regardless of Tx completion interrupt which seems to be 2110 * lost on PCIe based controllers under certain situations. 2111 */ 2112 re_txeof(sc); 2113 re_watchdog(sc); 2114 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2115 } 2116 2117 #ifdef DEVICE_POLLING 2118 static int 2119 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2120 { 2121 struct rl_softc *sc = ifp->if_softc; 2122 int rx_npkts = 0; 2123 2124 RL_LOCK(sc); 2125 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2126 rx_npkts = re_poll_locked(ifp, cmd, count); 2127 RL_UNLOCK(sc); 2128 return (rx_npkts); 2129 } 2130 2131 static int 2132 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2133 { 2134 struct rl_softc *sc = ifp->if_softc; 2135 int rx_npkts; 2136 2137 RL_LOCK_ASSERT(sc); 2138 2139 sc->rxcycles = count; 2140 re_rxeof(sc, &rx_npkts); 2141 re_txeof(sc); 2142 2143 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2144 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2145 2146 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2147 u_int16_t status; 2148 2149 status = CSR_READ_2(sc, RL_ISR); 2150 if (status == 0xffff) 2151 return (rx_npkts); 2152 if (status) 2153 CSR_WRITE_2(sc, RL_ISR, status); 2154 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2155 (sc->rl_flags & RL_FLAG_PCIE)) 2156 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2157 2158 /* 2159 * XXX check behaviour on receiver stalls. 2160 */ 2161 2162 if (status & RL_ISR_SYSTEM_ERR) { 2163 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2164 re_init_locked(sc); 2165 } 2166 } 2167 return (rx_npkts); 2168 } 2169 #endif /* DEVICE_POLLING */ 2170 2171 static int 2172 re_intr(void *arg) 2173 { 2174 struct rl_softc *sc; 2175 uint16_t status; 2176 2177 sc = arg; 2178 2179 status = CSR_READ_2(sc, RL_ISR); 2180 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2181 return (FILTER_STRAY); 2182 CSR_WRITE_2(sc, RL_IMR, 0); 2183 2184 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2185 2186 return (FILTER_HANDLED); 2187 } 2188 2189 static void 2190 re_int_task(void *arg, int npending) 2191 { 2192 struct rl_softc *sc; 2193 struct ifnet *ifp; 2194 u_int16_t status; 2195 int rval = 0; 2196 2197 sc = arg; 2198 ifp = sc->rl_ifp; 2199 2200 RL_LOCK(sc); 2201 2202 status = CSR_READ_2(sc, RL_ISR); 2203 CSR_WRITE_2(sc, RL_ISR, status); 2204 2205 if (sc->suspended || 2206 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2207 RL_UNLOCK(sc); 2208 return; 2209 } 2210 2211 #ifdef DEVICE_POLLING 2212 if (ifp->if_capenable & IFCAP_POLLING) { 2213 RL_UNLOCK(sc); 2214 return; 2215 } 2216 #endif 2217 2218 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2219 rval = re_rxeof(sc, NULL); 2220 2221 /* 2222 * Some chips will ignore a second TX request issued 2223 * while an existing transmission is in progress. If 2224 * the transmitter goes idle but there are still 2225 * packets waiting to be sent, we need to restart the 2226 * channel here to flush them out. This only seems to 2227 * be required with the PCIe devices. 2228 */ 2229 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2230 (sc->rl_flags & RL_FLAG_PCIE)) 2231 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2232 if (status & ( 2233 #ifdef RE_TX_MODERATION 2234 RL_ISR_TIMEOUT_EXPIRED| 2235 #else 2236 RL_ISR_TX_OK| 2237 #endif 2238 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2239 re_txeof(sc); 2240 2241 if (status & RL_ISR_SYSTEM_ERR) { 2242 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2243 re_init_locked(sc); 2244 } 2245 2246 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2247 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2248 2249 RL_UNLOCK(sc); 2250 2251 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2252 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2253 return; 2254 } 2255 2256 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2257 } 2258 2259 static int 2260 re_encap(struct rl_softc *sc, struct mbuf **m_head) 2261 { 2262 struct rl_txdesc *txd, *txd_last; 2263 bus_dma_segment_t segs[RL_NTXSEGS]; 2264 bus_dmamap_t map; 2265 struct mbuf *m_new; 2266 struct rl_desc *desc; 2267 int nsegs, prod; 2268 int i, error, ei, si; 2269 int padlen; 2270 uint32_t cmdstat, csum_flags, vlanctl; 2271 2272 RL_LOCK_ASSERT(sc); 2273 M_ASSERTPKTHDR((*m_head)); 2274 2275 /* 2276 * With some of the RealTek chips, using the checksum offload 2277 * support in conjunction with the autopadding feature results 2278 * in the transmission of corrupt frames. For example, if we 2279 * need to send a really small IP fragment that's less than 60 2280 * bytes in size, and IP header checksumming is enabled, the 2281 * resulting ethernet frame that appears on the wire will 2282 * have garbled payload. To work around this, if TX IP checksum 2283 * offload is enabled, we always manually pad short frames out 2284 * to the minimum ethernet frame size. 2285 */ 2286 if ((sc->rl_flags & RL_FLAG_AUTOPAD) == 0 && 2287 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN && 2288 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) { 2289 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2290 if (M_WRITABLE(*m_head) == 0) { 2291 /* Get a writable copy. */ 2292 m_new = m_dup(*m_head, M_DONTWAIT); 2293 m_freem(*m_head); 2294 if (m_new == NULL) { 2295 *m_head = NULL; 2296 return (ENOBUFS); 2297 } 2298 *m_head = m_new; 2299 } 2300 if ((*m_head)->m_next != NULL || 2301 M_TRAILINGSPACE(*m_head) < padlen) { 2302 m_new = m_defrag(*m_head, M_DONTWAIT); 2303 if (m_new == NULL) { 2304 m_freem(*m_head); 2305 *m_head = NULL; 2306 return (ENOBUFS); 2307 } 2308 } else 2309 m_new = *m_head; 2310 2311 /* 2312 * Manually pad short frames, and zero the pad space 2313 * to avoid leaking data. 2314 */ 2315 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2316 m_new->m_pkthdr.len += padlen; 2317 m_new->m_len = m_new->m_pkthdr.len; 2318 *m_head = m_new; 2319 } 2320 2321 prod = sc->rl_ldata.rl_tx_prodidx; 2322 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2323 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2324 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2325 if (error == EFBIG) { 2326 m_new = m_collapse(*m_head, M_DONTWAIT, RL_NTXSEGS); 2327 if (m_new == NULL) { 2328 m_freem(*m_head); 2329 *m_head = NULL; 2330 return (ENOBUFS); 2331 } 2332 *m_head = m_new; 2333 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2334 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2335 if (error != 0) { 2336 m_freem(*m_head); 2337 *m_head = NULL; 2338 return (error); 2339 } 2340 } else if (error != 0) 2341 return (error); 2342 if (nsegs == 0) { 2343 m_freem(*m_head); 2344 *m_head = NULL; 2345 return (EIO); 2346 } 2347 2348 /* Check for number of available descriptors. */ 2349 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2350 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2351 return (ENOBUFS); 2352 } 2353 2354 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2355 BUS_DMASYNC_PREWRITE); 2356 2357 /* 2358 * Set up checksum offload. Note: checksum offload bits must 2359 * appear in all descriptors of a multi-descriptor transmit 2360 * attempt. This is according to testing done with an 8169 2361 * chip. This is a requirement. 2362 */ 2363 vlanctl = 0; 2364 csum_flags = 0; 2365 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) 2366 csum_flags = RL_TDESC_CMD_LGSEND | 2367 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2368 RL_TDESC_CMD_MSSVAL_SHIFT); 2369 else { 2370 /* 2371 * Unconditionally enable IP checksum if TCP or UDP 2372 * checksum is required. Otherwise, TCP/UDP checksum 2373 * does't make effects. 2374 */ 2375 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) { 2376 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2377 csum_flags |= RL_TDESC_CMD_IPCSUM; 2378 if (((*m_head)->m_pkthdr.csum_flags & 2379 CSUM_TCP) != 0) 2380 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2381 if (((*m_head)->m_pkthdr.csum_flags & 2382 CSUM_UDP) != 0) 2383 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2384 } else { 2385 vlanctl |= RL_TDESC_CMD_IPCSUMV2; 2386 if (((*m_head)->m_pkthdr.csum_flags & 2387 CSUM_TCP) != 0) 2388 vlanctl |= RL_TDESC_CMD_TCPCSUMV2; 2389 if (((*m_head)->m_pkthdr.csum_flags & 2390 CSUM_UDP) != 0) 2391 vlanctl |= RL_TDESC_CMD_UDPCSUMV2; 2392 } 2393 } 2394 } 2395 2396 /* 2397 * Set up hardware VLAN tagging. Note: vlan tag info must 2398 * appear in all descriptors of a multi-descriptor 2399 * transmission attempt. 2400 */ 2401 if ((*m_head)->m_flags & M_VLANTAG) 2402 vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) | 2403 RL_TDESC_VLANCTL_TAG; 2404 2405 si = prod; 2406 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2407 desc = &sc->rl_ldata.rl_tx_list[prod]; 2408 desc->rl_vlanctl = htole32(vlanctl); 2409 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2410 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2411 cmdstat = segs[i].ds_len; 2412 if (i != 0) 2413 cmdstat |= RL_TDESC_CMD_OWN; 2414 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2415 cmdstat |= RL_TDESC_CMD_EOR; 2416 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2417 sc->rl_ldata.rl_tx_free--; 2418 } 2419 /* Update producer index. */ 2420 sc->rl_ldata.rl_tx_prodidx = prod; 2421 2422 /* Set EOF on the last descriptor. */ 2423 ei = RL_TX_DESC_PRV(sc, prod); 2424 desc = &sc->rl_ldata.rl_tx_list[ei]; 2425 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2426 2427 desc = &sc->rl_ldata.rl_tx_list[si]; 2428 /* Set SOF and transfer ownership of packet to the chip. */ 2429 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2430 2431 /* 2432 * Insure that the map for this transmission 2433 * is placed at the array index of the last descriptor 2434 * in this chain. (Swap last and first dmamaps.) 2435 */ 2436 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2437 map = txd->tx_dmamap; 2438 txd->tx_dmamap = txd_last->tx_dmamap; 2439 txd_last->tx_dmamap = map; 2440 txd_last->tx_m = *m_head; 2441 2442 return (0); 2443 } 2444 2445 static void 2446 re_tx_task(void *arg, int npending) 2447 { 2448 struct ifnet *ifp; 2449 2450 ifp = arg; 2451 re_start(ifp); 2452 } 2453 2454 /* 2455 * Main transmit routine for C+ and gigE NICs. 2456 */ 2457 static void 2458 re_start(struct ifnet *ifp) 2459 { 2460 struct rl_softc *sc; 2461 struct mbuf *m_head; 2462 int queued; 2463 2464 sc = ifp->if_softc; 2465 2466 RL_LOCK(sc); 2467 2468 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2469 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) { 2470 RL_UNLOCK(sc); 2471 return; 2472 } 2473 2474 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2475 sc->rl_ldata.rl_tx_free > 1;) { 2476 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2477 if (m_head == NULL) 2478 break; 2479 2480 if (re_encap(sc, &m_head) != 0) { 2481 if (m_head == NULL) 2482 break; 2483 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2484 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2485 break; 2486 } 2487 2488 /* 2489 * If there's a BPF listener, bounce a copy of this frame 2490 * to him. 2491 */ 2492 ETHER_BPF_MTAP(ifp, m_head); 2493 2494 queued++; 2495 } 2496 2497 if (queued == 0) { 2498 #ifdef RE_TX_MODERATION 2499 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2500 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2501 #endif 2502 RL_UNLOCK(sc); 2503 return; 2504 } 2505 2506 /* Flush the TX descriptors */ 2507 2508 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2509 sc->rl_ldata.rl_tx_list_map, 2510 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2511 2512 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2513 2514 #ifdef RE_TX_MODERATION 2515 /* 2516 * Use the countdown timer for interrupt moderation. 2517 * 'TX done' interrupts are disabled. Instead, we reset the 2518 * countdown timer, which will begin counting until it hits 2519 * the value in the TIMERINT register, and then trigger an 2520 * interrupt. Each time we write to the TIMERCNT register, 2521 * the timer count is reset to 0. 2522 */ 2523 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2524 #endif 2525 2526 /* 2527 * Set a timeout in case the chip goes out to lunch. 2528 */ 2529 sc->rl_watchdog_timer = 5; 2530 2531 RL_UNLOCK(sc); 2532 } 2533 2534 static void 2535 re_init(void *xsc) 2536 { 2537 struct rl_softc *sc = xsc; 2538 2539 RL_LOCK(sc); 2540 re_init_locked(sc); 2541 RL_UNLOCK(sc); 2542 } 2543 2544 static void 2545 re_init_locked(struct rl_softc *sc) 2546 { 2547 struct ifnet *ifp = sc->rl_ifp; 2548 struct mii_data *mii; 2549 uint32_t reg; 2550 uint16_t cfg; 2551 union { 2552 uint32_t align_dummy; 2553 u_char eaddr[ETHER_ADDR_LEN]; 2554 } eaddr; 2555 2556 RL_LOCK_ASSERT(sc); 2557 2558 mii = device_get_softc(sc->rl_miibus); 2559 2560 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2561 return; 2562 2563 /* 2564 * Cancel pending I/O and free all RX/TX buffers. 2565 */ 2566 re_stop(sc); 2567 2568 /* Put controller into known state. */ 2569 re_reset(sc); 2570 2571 /* 2572 * Enable C+ RX and TX mode, as well as VLAN stripping and 2573 * RX checksum offload. We must configure the C+ register 2574 * before all others. 2575 */ 2576 cfg = RL_CPLUSCMD_PCI_MRW; 2577 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2578 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 2579 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2580 cfg |= RL_CPLUSCMD_VLANSTRIP; 2581 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) { 2582 cfg |= RL_CPLUSCMD_MACSTAT_DIS; 2583 /* XXX magic. */ 2584 cfg |= 0x0001; 2585 } else 2586 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB; 2587 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg); 2588 if (sc->rl_hwrev == RL_HWREV_8169_8110SC || 2589 sc->rl_hwrev == RL_HWREV_8169_8110SCE) { 2590 reg = 0x000fff00; 2591 if ((CSR_READ_1(sc, RL_CFG2) & RL_CFG2_PCI66MHZ) != 0) 2592 reg |= 0x000000ff; 2593 if (sc->rl_hwrev == RL_HWREV_8169_8110SCE) 2594 reg |= 0x00f00000; 2595 CSR_WRITE_4(sc, 0x7c, reg); 2596 /* Disable interrupt mitigation. */ 2597 CSR_WRITE_2(sc, 0xe2, 0); 2598 } 2599 /* 2600 * Disable TSO if interface MTU size is greater than MSS 2601 * allowed in controller. 2602 */ 2603 if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) { 2604 ifp->if_capenable &= ~IFCAP_TSO4; 2605 ifp->if_hwassist &= ~CSUM_TSO; 2606 } 2607 2608 /* 2609 * Init our MAC address. Even though the chipset 2610 * documentation doesn't mention it, we need to enter "Config 2611 * register write enable" mode to modify the ID registers. 2612 */ 2613 /* Copy MAC address on stack to align. */ 2614 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 2615 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2616 CSR_WRITE_4(sc, RL_IDR0, 2617 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 2618 CSR_WRITE_4(sc, RL_IDR4, 2619 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 2620 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2621 2622 /* 2623 * For C+ mode, initialize the RX descriptors and mbufs. 2624 */ 2625 re_rx_list_init(sc); 2626 re_tx_list_init(sc); 2627 2628 /* 2629 * Load the addresses of the RX and TX lists into the chip. 2630 */ 2631 2632 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2633 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2634 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2635 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2636 2637 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2638 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2639 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2640 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2641 2642 /* 2643 * Enable transmit and receive. 2644 */ 2645 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2646 2647 /* 2648 * Set the initial TX configuration. 2649 */ 2650 if (sc->rl_testmode) { 2651 if (sc->rl_type == RL_8169) 2652 CSR_WRITE_4(sc, RL_TXCFG, 2653 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2654 else 2655 CSR_WRITE_4(sc, RL_TXCFG, 2656 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2657 } else 2658 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2659 2660 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2661 2662 /* 2663 * Set the initial RX configuration. 2664 */ 2665 re_set_rxmode(sc); 2666 2667 #ifdef DEVICE_POLLING 2668 /* 2669 * Disable interrupts if we are polling. 2670 */ 2671 if (ifp->if_capenable & IFCAP_POLLING) 2672 CSR_WRITE_2(sc, RL_IMR, 0); 2673 else /* otherwise ... */ 2674 #endif 2675 2676 /* 2677 * Enable interrupts. 2678 */ 2679 if (sc->rl_testmode) 2680 CSR_WRITE_2(sc, RL_IMR, 0); 2681 else 2682 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2683 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 2684 2685 /* Set initial TX threshold */ 2686 sc->rl_txthresh = RL_TX_THRESH_INIT; 2687 2688 /* Start RX/TX process. */ 2689 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2690 #ifdef notdef 2691 /* Enable receiver and transmitter. */ 2692 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2693 #endif 2694 2695 #ifdef RE_TX_MODERATION 2696 /* 2697 * Initialize the timer interrupt register so that 2698 * a timer interrupt will be generated once the timer 2699 * reaches a certain number of ticks. The timer is 2700 * reloaded on each transmit. This gives us TX interrupt 2701 * moderation, which dramatically improves TX frame rate. 2702 */ 2703 if (sc->rl_type == RL_8169) 2704 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2705 else 2706 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2707 #endif 2708 2709 /* 2710 * For 8169 gigE NICs, set the max allowed RX packet 2711 * size so we can receive jumbo frames. 2712 */ 2713 if (sc->rl_type == RL_8169) 2714 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2715 2716 if (sc->rl_testmode) 2717 return; 2718 2719 mii_mediachg(mii); 2720 2721 CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD); 2722 2723 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2724 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2725 2726 sc->rl_flags &= ~RL_FLAG_LINK; 2727 sc->rl_watchdog_timer = 0; 2728 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2729 } 2730 2731 /* 2732 * Set media options. 2733 */ 2734 static int 2735 re_ifmedia_upd(struct ifnet *ifp) 2736 { 2737 struct rl_softc *sc; 2738 struct mii_data *mii; 2739 int error; 2740 2741 sc = ifp->if_softc; 2742 mii = device_get_softc(sc->rl_miibus); 2743 RL_LOCK(sc); 2744 error = mii_mediachg(mii); 2745 RL_UNLOCK(sc); 2746 2747 return (error); 2748 } 2749 2750 /* 2751 * Report current media status. 2752 */ 2753 static void 2754 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2755 { 2756 struct rl_softc *sc; 2757 struct mii_data *mii; 2758 2759 sc = ifp->if_softc; 2760 mii = device_get_softc(sc->rl_miibus); 2761 2762 RL_LOCK(sc); 2763 mii_pollstat(mii); 2764 RL_UNLOCK(sc); 2765 ifmr->ifm_active = mii->mii_media_active; 2766 ifmr->ifm_status = mii->mii_media_status; 2767 } 2768 2769 static int 2770 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2771 { 2772 struct rl_softc *sc = ifp->if_softc; 2773 struct ifreq *ifr = (struct ifreq *) data; 2774 struct mii_data *mii; 2775 int error = 0; 2776 2777 switch (command) { 2778 case SIOCSIFMTU: 2779 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > RL_JUMBO_MTU) { 2780 error = EINVAL; 2781 break; 2782 } 2783 if ((sc->rl_flags & RL_FLAG_NOJUMBO) != 0 && 2784 ifr->ifr_mtu > RL_MAX_FRAMELEN) { 2785 error = EINVAL; 2786 break; 2787 } 2788 RL_LOCK(sc); 2789 if (ifp->if_mtu != ifr->ifr_mtu) 2790 ifp->if_mtu = ifr->ifr_mtu; 2791 if (ifp->if_mtu > RL_TSO_MTU && 2792 (ifp->if_capenable & IFCAP_TSO4) != 0) { 2793 ifp->if_capenable &= ~IFCAP_TSO4; 2794 ifp->if_hwassist &= ~CSUM_TSO; 2795 VLAN_CAPABILITIES(ifp); 2796 } 2797 RL_UNLOCK(sc); 2798 break; 2799 case SIOCSIFFLAGS: 2800 RL_LOCK(sc); 2801 if ((ifp->if_flags & IFF_UP) != 0) { 2802 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2803 if (((ifp->if_flags ^ sc->rl_if_flags) 2804 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2805 re_set_rxmode(sc); 2806 } else 2807 re_init_locked(sc); 2808 } else { 2809 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2810 re_stop(sc); 2811 } 2812 sc->rl_if_flags = ifp->if_flags; 2813 RL_UNLOCK(sc); 2814 break; 2815 case SIOCADDMULTI: 2816 case SIOCDELMULTI: 2817 RL_LOCK(sc); 2818 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2819 re_set_rxmode(sc); 2820 RL_UNLOCK(sc); 2821 break; 2822 case SIOCGIFMEDIA: 2823 case SIOCSIFMEDIA: 2824 mii = device_get_softc(sc->rl_miibus); 2825 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2826 break; 2827 case SIOCSIFCAP: 2828 { 2829 int mask, reinit; 2830 2831 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2832 reinit = 0; 2833 #ifdef DEVICE_POLLING 2834 if (mask & IFCAP_POLLING) { 2835 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2836 error = ether_poll_register(re_poll, ifp); 2837 if (error) 2838 return(error); 2839 RL_LOCK(sc); 2840 /* Disable interrupts */ 2841 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2842 ifp->if_capenable |= IFCAP_POLLING; 2843 RL_UNLOCK(sc); 2844 } else { 2845 error = ether_poll_deregister(ifp); 2846 /* Enable interrupts. */ 2847 RL_LOCK(sc); 2848 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2849 ifp->if_capenable &= ~IFCAP_POLLING; 2850 RL_UNLOCK(sc); 2851 } 2852 } 2853 #endif /* DEVICE_POLLING */ 2854 if (mask & IFCAP_HWCSUM) { 2855 ifp->if_capenable ^= IFCAP_HWCSUM; 2856 if (ifp->if_capenable & IFCAP_TXCSUM) 2857 ifp->if_hwassist |= RE_CSUM_FEATURES; 2858 else 2859 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 2860 reinit = 1; 2861 } 2862 if ((mask & IFCAP_TSO4) != 0 && 2863 (ifp->if_capabilities & IFCAP_TSO) != 0) { 2864 ifp->if_capenable ^= IFCAP_TSO4; 2865 if ((IFCAP_TSO4 & ifp->if_capenable) != 0) 2866 ifp->if_hwassist |= CSUM_TSO; 2867 else 2868 ifp->if_hwassist &= ~CSUM_TSO; 2869 if (ifp->if_mtu > RL_TSO_MTU && 2870 (ifp->if_capenable & IFCAP_TSO4) != 0) { 2871 ifp->if_capenable &= ~IFCAP_TSO4; 2872 ifp->if_hwassist &= ~CSUM_TSO; 2873 } 2874 } 2875 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2876 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 2877 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 2878 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2879 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2880 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2881 /* TSO over VLAN requires VLAN hardware tagging. */ 2882 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 2883 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 2884 reinit = 1; 2885 } 2886 if ((mask & IFCAP_WOL) != 0 && 2887 (ifp->if_capabilities & IFCAP_WOL) != 0) { 2888 if ((mask & IFCAP_WOL_UCAST) != 0) 2889 ifp->if_capenable ^= IFCAP_WOL_UCAST; 2890 if ((mask & IFCAP_WOL_MCAST) != 0) 2891 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2892 if ((mask & IFCAP_WOL_MAGIC) != 0) 2893 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2894 } 2895 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) { 2896 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2897 re_init(sc); 2898 } 2899 VLAN_CAPABILITIES(ifp); 2900 } 2901 break; 2902 default: 2903 error = ether_ioctl(ifp, command, data); 2904 break; 2905 } 2906 2907 return (error); 2908 } 2909 2910 static void 2911 re_watchdog(struct rl_softc *sc) 2912 { 2913 struct ifnet *ifp; 2914 2915 RL_LOCK_ASSERT(sc); 2916 2917 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 2918 return; 2919 2920 ifp = sc->rl_ifp; 2921 re_txeof(sc); 2922 if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) { 2923 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 2924 "-- recovering\n"); 2925 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2926 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2927 return; 2928 } 2929 2930 if_printf(ifp, "watchdog timeout\n"); 2931 ifp->if_oerrors++; 2932 2933 re_rxeof(sc, NULL); 2934 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2935 re_init_locked(sc); 2936 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2937 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2938 } 2939 2940 /* 2941 * Stop the adapter and free any mbufs allocated to the 2942 * RX and TX lists. 2943 */ 2944 static void 2945 re_stop(struct rl_softc *sc) 2946 { 2947 int i; 2948 struct ifnet *ifp; 2949 struct rl_txdesc *txd; 2950 struct rl_rxdesc *rxd; 2951 2952 RL_LOCK_ASSERT(sc); 2953 2954 ifp = sc->rl_ifp; 2955 2956 sc->rl_watchdog_timer = 0; 2957 callout_stop(&sc->rl_stat_callout); 2958 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2959 2960 if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0) 2961 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB | 2962 RL_CMD_RX_ENB); 2963 else 2964 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2965 DELAY(1000); 2966 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2967 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 2968 2969 if (sc->rl_head != NULL) { 2970 m_freem(sc->rl_head); 2971 sc->rl_head = sc->rl_tail = NULL; 2972 } 2973 2974 /* Free the TX list buffers. */ 2975 2976 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 2977 txd = &sc->rl_ldata.rl_tx_desc[i]; 2978 if (txd->tx_m != NULL) { 2979 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2980 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2981 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2982 txd->tx_dmamap); 2983 m_freem(txd->tx_m); 2984 txd->tx_m = NULL; 2985 } 2986 } 2987 2988 /* Free the RX list buffers. */ 2989 2990 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2991 rxd = &sc->rl_ldata.rl_rx_desc[i]; 2992 if (rxd->rx_m != NULL) { 2993 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2994 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2995 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 2996 rxd->rx_dmamap); 2997 m_freem(rxd->rx_m); 2998 rxd->rx_m = NULL; 2999 } 3000 } 3001 } 3002 3003 /* 3004 * Device suspend routine. Stop the interface and save some PCI 3005 * settings in case the BIOS doesn't restore them properly on 3006 * resume. 3007 */ 3008 static int 3009 re_suspend(device_t dev) 3010 { 3011 struct rl_softc *sc; 3012 3013 sc = device_get_softc(dev); 3014 3015 RL_LOCK(sc); 3016 re_stop(sc); 3017 re_setwol(sc); 3018 sc->suspended = 1; 3019 RL_UNLOCK(sc); 3020 3021 return (0); 3022 } 3023 3024 /* 3025 * Device resume routine. Restore some PCI settings in case the BIOS 3026 * doesn't, re-enable busmastering, and restart the interface if 3027 * appropriate. 3028 */ 3029 static int 3030 re_resume(device_t dev) 3031 { 3032 struct rl_softc *sc; 3033 struct ifnet *ifp; 3034 3035 sc = device_get_softc(dev); 3036 3037 RL_LOCK(sc); 3038 3039 ifp = sc->rl_ifp; 3040 /* Take controller out of sleep mode. */ 3041 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3042 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3043 CSR_WRITE_1(sc, RL_GPIO, 3044 CSR_READ_1(sc, RL_GPIO) | 0x01); 3045 } 3046 3047 /* 3048 * Clear WOL matching such that normal Rx filtering 3049 * wouldn't interfere with WOL patterns. 3050 */ 3051 re_clrwol(sc); 3052 3053 /* reinitialize interface if necessary */ 3054 if (ifp->if_flags & IFF_UP) 3055 re_init_locked(sc); 3056 3057 sc->suspended = 0; 3058 RL_UNLOCK(sc); 3059 3060 return (0); 3061 } 3062 3063 /* 3064 * Stop all chip I/O so that the kernel's probe routines don't 3065 * get confused by errant DMAs when rebooting. 3066 */ 3067 static int 3068 re_shutdown(device_t dev) 3069 { 3070 struct rl_softc *sc; 3071 3072 sc = device_get_softc(dev); 3073 3074 RL_LOCK(sc); 3075 re_stop(sc); 3076 /* 3077 * Mark interface as down since otherwise we will panic if 3078 * interrupt comes in later on, which can happen in some 3079 * cases. 3080 */ 3081 sc->rl_ifp->if_flags &= ~IFF_UP; 3082 re_setwol(sc); 3083 RL_UNLOCK(sc); 3084 3085 return (0); 3086 } 3087 3088 static void 3089 re_setwol(struct rl_softc *sc) 3090 { 3091 struct ifnet *ifp; 3092 int pmc; 3093 uint16_t pmstat; 3094 uint8_t v; 3095 3096 RL_LOCK_ASSERT(sc); 3097 3098 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3099 return; 3100 3101 ifp = sc->rl_ifp; 3102 /* Put controller into sleep mode. */ 3103 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3104 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3105 CSR_WRITE_1(sc, RL_GPIO, 3106 CSR_READ_1(sc, RL_GPIO) & ~0x01); 3107 } 3108 if ((ifp->if_capenable & IFCAP_WOL) != 0 && 3109 (sc->rl_flags & RL_FLAG_WOLRXENB) != 0) 3110 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB); 3111 /* Enable config register write. */ 3112 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3113 3114 /* Enable PME. */ 3115 v = CSR_READ_1(sc, RL_CFG1); 3116 v &= ~RL_CFG1_PME; 3117 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3118 v |= RL_CFG1_PME; 3119 CSR_WRITE_1(sc, RL_CFG1, v); 3120 3121 v = CSR_READ_1(sc, RL_CFG3); 3122 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3123 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3124 v |= RL_CFG3_WOL_MAGIC; 3125 CSR_WRITE_1(sc, RL_CFG3, v); 3126 3127 /* Config register write done. */ 3128 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3129 3130 v = CSR_READ_1(sc, RL_CFG5); 3131 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3132 v &= ~RL_CFG5_WOL_LANWAKE; 3133 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 3134 v |= RL_CFG5_WOL_UCAST; 3135 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 3136 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 3137 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3138 v |= RL_CFG5_WOL_LANWAKE; 3139 CSR_WRITE_1(sc, RL_CFG5, v); 3140 3141 if ((ifp->if_capenable & IFCAP_WOL) != 0 && 3142 (sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) 3143 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) & ~0x80); 3144 /* 3145 * It seems that hardware resets its link speed to 100Mbps in 3146 * power down mode so switching to 100Mbps in driver is not 3147 * needed. 3148 */ 3149 3150 /* Request PME if WOL is requested. */ 3151 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 3152 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3153 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3154 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3155 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 3156 } 3157 3158 static void 3159 re_clrwol(struct rl_softc *sc) 3160 { 3161 int pmc; 3162 uint8_t v; 3163 3164 RL_LOCK_ASSERT(sc); 3165 3166 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3167 return; 3168 3169 /* Enable config register write. */ 3170 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3171 3172 v = CSR_READ_1(sc, RL_CFG3); 3173 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3174 CSR_WRITE_1(sc, RL_CFG3, v); 3175 3176 /* Config register write done. */ 3177 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3178 3179 v = CSR_READ_1(sc, RL_CFG5); 3180 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3181 v &= ~RL_CFG5_WOL_LANWAKE; 3182 CSR_WRITE_1(sc, RL_CFG5, v); 3183 } 3184