1 /* 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44 /* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S 48 * and the RTL8110S. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7.5K, so the max MTU possible with this 108 * driver is 7500 bytes. 109 */ 110 111 #include <sys/param.h> 112 #include <sys/endian.h> 113 #include <sys/systm.h> 114 #include <sys/sockio.h> 115 #include <sys/mbuf.h> 116 #include <sys/malloc.h> 117 #include <sys/module.h> 118 #include <sys/kernel.h> 119 #include <sys/socket.h> 120 121 #include <net/if.h> 122 #include <net/if_arp.h> 123 #include <net/ethernet.h> 124 #include <net/if_dl.h> 125 #include <net/if_media.h> 126 #include <net/if_vlan_var.h> 127 128 #include <net/bpf.h> 129 130 #include <machine/bus_pio.h> 131 #include <machine/bus_memio.h> 132 #include <machine/bus.h> 133 #include <machine/resource.h> 134 #include <sys/bus.h> 135 #include <sys/rman.h> 136 137 #include <dev/mii/mii.h> 138 #include <dev/mii/miivar.h> 139 140 #include <dev/pci/pcireg.h> 141 #include <dev/pci/pcivar.h> 142 143 MODULE_DEPEND(re, pci, 1, 1, 1); 144 MODULE_DEPEND(re, ether, 1, 1, 1); 145 MODULE_DEPEND(re, miibus, 1, 1, 1); 146 147 /* "controller miibus0" required. See GENERIC if you get errors here. */ 148 #include "miibus_if.h" 149 150 /* 151 * Default to using PIO access for this driver. 152 */ 153 #define RE_USEIOSPACE 154 155 #include <pci/if_rlreg.h> 156 157 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 158 159 /* 160 * Various supported device vendors/types and their names. 161 */ 162 static struct rl_type re_devs[] = { 163 { RT_VENDORID, RT_DEVICEID_8139, RL_HWREV_8139CPLUS, 164 "RealTek 8139C+ 10/100BaseTX" }, 165 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169, 166 "RealTek 8169 Gigabit Ethernet" }, 167 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169S, 168 "RealTek 8169S Single-chip Gigabit Ethernet" }, 169 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8110S, 170 "RealTek 8110S Single-chip Gigabit Ethernet" }, 171 { 0, 0, 0, NULL } 172 }; 173 174 static struct rl_hwrev re_hwrevs[] = { 175 { RL_HWREV_8139, RL_8139, "" }, 176 { RL_HWREV_8139A, RL_8139, "A" }, 177 { RL_HWREV_8139AG, RL_8139, "A-G" }, 178 { RL_HWREV_8139B, RL_8139, "B" }, 179 { RL_HWREV_8130, RL_8139, "8130" }, 180 { RL_HWREV_8139C, RL_8139, "C" }, 181 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 182 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 183 { RL_HWREV_8169, RL_8169, "8169"}, 184 { RL_HWREV_8169S, RL_8169, "8169S"}, 185 { RL_HWREV_8110S, RL_8169, "8110S"}, 186 { RL_HWREV_8100, RL_8139, "8100"}, 187 { RL_HWREV_8101, RL_8139, "8101"}, 188 { 0, 0, NULL } 189 }; 190 191 static int re_probe (device_t); 192 static int re_attach (device_t); 193 static int re_detach (device_t); 194 195 static int re_encap (struct rl_softc *, struct mbuf *, int *); 196 197 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 198 static void re_dma_map_desc (void *, bus_dma_segment_t *, int, 199 bus_size_t, int); 200 static int re_allocmem (device_t, struct rl_softc *); 201 static int re_newbuf (struct rl_softc *, int, struct mbuf *); 202 static int re_rx_list_init (struct rl_softc *); 203 static int re_tx_list_init (struct rl_softc *); 204 static void re_rxeof (struct rl_softc *); 205 static void re_txeof (struct rl_softc *); 206 static void re_intr (void *); 207 static void re_tick (void *); 208 static void re_start (struct ifnet *); 209 static int re_ioctl (struct ifnet *, u_long, caddr_t); 210 static void re_init (void *); 211 static void re_stop (struct rl_softc *); 212 static void re_watchdog (struct ifnet *); 213 static int re_suspend (device_t); 214 static int re_resume (device_t); 215 static void re_shutdown (device_t); 216 static int re_ifmedia_upd (struct ifnet *); 217 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 218 219 static void re_eeprom_putbyte (struct rl_softc *, int); 220 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 221 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int, int); 222 static int re_gmii_readreg (device_t, int, int); 223 static int re_gmii_writereg (device_t, int, int, int); 224 225 static int re_miibus_readreg (device_t, int, int); 226 static int re_miibus_writereg (device_t, int, int, int); 227 static void re_miibus_statchg (device_t); 228 229 static void re_setmulti (struct rl_softc *); 230 static void re_reset (struct rl_softc *); 231 232 static int re_diag (struct rl_softc *); 233 234 #ifdef RE_USEIOSPACE 235 #define RL_RES SYS_RES_IOPORT 236 #define RL_RID RL_PCI_LOIO 237 #else 238 #define RL_RES SYS_RES_MEMORY 239 #define RL_RID RL_PCI_LOMEM 240 #endif 241 242 static device_method_t re_methods[] = { 243 /* Device interface */ 244 DEVMETHOD(device_probe, re_probe), 245 DEVMETHOD(device_attach, re_attach), 246 DEVMETHOD(device_detach, re_detach), 247 DEVMETHOD(device_suspend, re_suspend), 248 DEVMETHOD(device_resume, re_resume), 249 DEVMETHOD(device_shutdown, re_shutdown), 250 251 /* bus interface */ 252 DEVMETHOD(bus_print_child, bus_generic_print_child), 253 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 254 255 /* MII interface */ 256 DEVMETHOD(miibus_readreg, re_miibus_readreg), 257 DEVMETHOD(miibus_writereg, re_miibus_writereg), 258 DEVMETHOD(miibus_statchg, re_miibus_statchg), 259 260 { 0, 0 } 261 }; 262 263 static driver_t re_driver = { 264 "re", 265 re_methods, 266 sizeof(struct rl_softc) 267 }; 268 269 static devclass_t re_devclass; 270 271 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 272 DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0); 273 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 274 275 #define EE_SET(x) \ 276 CSR_WRITE_1(sc, RL_EECMD, \ 277 CSR_READ_1(sc, RL_EECMD) | x) 278 279 #define EE_CLR(x) \ 280 CSR_WRITE_1(sc, RL_EECMD, \ 281 CSR_READ_1(sc, RL_EECMD) & ~x) 282 283 /* 284 * Send a read command and address to the EEPROM, check for ACK. 285 */ 286 static void 287 re_eeprom_putbyte(sc, addr) 288 struct rl_softc *sc; 289 int addr; 290 { 291 register int d, i; 292 293 d = addr | sc->rl_eecmd_read; 294 295 /* 296 * Feed in each bit and strobe the clock. 297 */ 298 for (i = 0x400; i; i >>= 1) { 299 if (d & i) { 300 EE_SET(RL_EE_DATAIN); 301 } else { 302 EE_CLR(RL_EE_DATAIN); 303 } 304 DELAY(100); 305 EE_SET(RL_EE_CLK); 306 DELAY(150); 307 EE_CLR(RL_EE_CLK); 308 DELAY(100); 309 } 310 311 return; 312 } 313 314 /* 315 * Read a word of data stored in the EEPROM at address 'addr.' 316 */ 317 static void 318 re_eeprom_getword(sc, addr, dest) 319 struct rl_softc *sc; 320 int addr; 321 u_int16_t *dest; 322 { 323 register int i; 324 u_int16_t word = 0; 325 326 /* Enter EEPROM access mode. */ 327 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 328 329 /* 330 * Send address of word we want to read. 331 */ 332 re_eeprom_putbyte(sc, addr); 333 334 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 335 336 /* 337 * Start reading bits from EEPROM. 338 */ 339 for (i = 0x8000; i; i >>= 1) { 340 EE_SET(RL_EE_CLK); 341 DELAY(100); 342 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 343 word |= i; 344 EE_CLR(RL_EE_CLK); 345 DELAY(100); 346 } 347 348 /* Turn off EEPROM access mode. */ 349 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 350 351 *dest = word; 352 353 return; 354 } 355 356 /* 357 * Read a sequence of words from the EEPROM. 358 */ 359 static void 360 re_read_eeprom(sc, dest, off, cnt, swap) 361 struct rl_softc *sc; 362 caddr_t dest; 363 int off; 364 int cnt; 365 int swap; 366 { 367 int i; 368 u_int16_t word = 0, *ptr; 369 370 for (i = 0; i < cnt; i++) { 371 re_eeprom_getword(sc, off + i, &word); 372 ptr = (u_int16_t *)(dest + (i * 2)); 373 if (swap) 374 *ptr = ntohs(word); 375 else 376 *ptr = word; 377 } 378 379 return; 380 } 381 382 static int 383 re_gmii_readreg(dev, phy, reg) 384 device_t dev; 385 int phy, reg; 386 { 387 struct rl_softc *sc; 388 u_int32_t rval; 389 int i; 390 391 if (phy != 1) 392 return(0); 393 394 sc = device_get_softc(dev); 395 396 /* Let the rgephy driver read the GMEDIASTAT register */ 397 398 if (reg == RL_GMEDIASTAT) { 399 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 400 return(rval); 401 } 402 403 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 404 DELAY(1000); 405 406 for (i = 0; i < RL_TIMEOUT; i++) { 407 rval = CSR_READ_4(sc, RL_PHYAR); 408 if (rval & RL_PHYAR_BUSY) 409 break; 410 DELAY(100); 411 } 412 413 if (i == RL_TIMEOUT) { 414 printf ("re%d: PHY read failed\n", sc->rl_unit); 415 return (0); 416 } 417 418 return (rval & RL_PHYAR_PHYDATA); 419 } 420 421 static int 422 re_gmii_writereg(dev, phy, reg, data) 423 device_t dev; 424 int phy, reg, data; 425 { 426 struct rl_softc *sc; 427 u_int32_t rval; 428 int i; 429 430 sc = device_get_softc(dev); 431 432 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 433 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 434 DELAY(1000); 435 436 for (i = 0; i < RL_TIMEOUT; i++) { 437 rval = CSR_READ_4(sc, RL_PHYAR); 438 if (!(rval & RL_PHYAR_BUSY)) 439 break; 440 DELAY(100); 441 } 442 443 if (i == RL_TIMEOUT) { 444 printf ("re%d: PHY write failed\n", sc->rl_unit); 445 return (0); 446 } 447 448 return (0); 449 } 450 451 static int 452 re_miibus_readreg(dev, phy, reg) 453 device_t dev; 454 int phy, reg; 455 { 456 struct rl_softc *sc; 457 u_int16_t rval = 0; 458 u_int16_t re8139_reg = 0; 459 460 sc = device_get_softc(dev); 461 RL_LOCK(sc); 462 463 if (sc->rl_type == RL_8169) { 464 rval = re_gmii_readreg(dev, phy, reg); 465 RL_UNLOCK(sc); 466 return (rval); 467 } 468 469 /* Pretend the internal PHY is only at address 0 */ 470 if (phy) { 471 RL_UNLOCK(sc); 472 return(0); 473 } 474 switch(reg) { 475 case MII_BMCR: 476 re8139_reg = RL_BMCR; 477 break; 478 case MII_BMSR: 479 re8139_reg = RL_BMSR; 480 break; 481 case MII_ANAR: 482 re8139_reg = RL_ANAR; 483 break; 484 case MII_ANER: 485 re8139_reg = RL_ANER; 486 break; 487 case MII_ANLPAR: 488 re8139_reg = RL_LPAR; 489 break; 490 case MII_PHYIDR1: 491 case MII_PHYIDR2: 492 RL_UNLOCK(sc); 493 return(0); 494 /* 495 * Allow the rlphy driver to read the media status 496 * register. If we have a link partner which does not 497 * support NWAY, this is the register which will tell 498 * us the results of parallel detection. 499 */ 500 case RL_MEDIASTAT: 501 rval = CSR_READ_1(sc, RL_MEDIASTAT); 502 RL_UNLOCK(sc); 503 return(rval); 504 default: 505 printf("re%d: bad phy register\n", sc->rl_unit); 506 RL_UNLOCK(sc); 507 return(0); 508 } 509 rval = CSR_READ_2(sc, re8139_reg); 510 RL_UNLOCK(sc); 511 return(rval); 512 } 513 514 static int 515 re_miibus_writereg(dev, phy, reg, data) 516 device_t dev; 517 int phy, reg, data; 518 { 519 struct rl_softc *sc; 520 u_int16_t re8139_reg = 0; 521 int rval = 0; 522 523 sc = device_get_softc(dev); 524 RL_LOCK(sc); 525 526 if (sc->rl_type == RL_8169) { 527 rval = re_gmii_writereg(dev, phy, reg, data); 528 RL_UNLOCK(sc); 529 return (rval); 530 } 531 532 /* Pretend the internal PHY is only at address 0 */ 533 if (phy) { 534 RL_UNLOCK(sc); 535 return(0); 536 } 537 switch(reg) { 538 case MII_BMCR: 539 re8139_reg = RL_BMCR; 540 break; 541 case MII_BMSR: 542 re8139_reg = RL_BMSR; 543 break; 544 case MII_ANAR: 545 re8139_reg = RL_ANAR; 546 break; 547 case MII_ANER: 548 re8139_reg = RL_ANER; 549 break; 550 case MII_ANLPAR: 551 re8139_reg = RL_LPAR; 552 break; 553 case MII_PHYIDR1: 554 case MII_PHYIDR2: 555 RL_UNLOCK(sc); 556 return(0); 557 break; 558 default: 559 printf("re%d: bad phy register\n", sc->rl_unit); 560 RL_UNLOCK(sc); 561 return(0); 562 } 563 CSR_WRITE_2(sc, re8139_reg, data); 564 RL_UNLOCK(sc); 565 return(0); 566 } 567 568 static void 569 re_miibus_statchg(dev) 570 device_t dev; 571 { 572 return; 573 } 574 575 /* 576 * Program the 64-bit multicast hash filter. 577 */ 578 static void 579 re_setmulti(sc) 580 struct rl_softc *sc; 581 { 582 struct ifnet *ifp; 583 int h = 0; 584 u_int32_t hashes[2] = { 0, 0 }; 585 struct ifmultiaddr *ifma; 586 u_int32_t rxfilt; 587 int mcnt = 0; 588 589 ifp = &sc->arpcom.ac_if; 590 591 rxfilt = CSR_READ_4(sc, RL_RXCFG); 592 593 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 594 rxfilt |= RL_RXCFG_RX_MULTI; 595 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 596 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 597 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 598 return; 599 } 600 601 /* first, zot all the existing hash bits */ 602 CSR_WRITE_4(sc, RL_MAR0, 0); 603 CSR_WRITE_4(sc, RL_MAR4, 0); 604 605 /* now program new ones */ 606 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 607 if (ifma->ifma_addr->sa_family != AF_LINK) 608 continue; 609 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 610 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 611 if (h < 32) 612 hashes[0] |= (1 << h); 613 else 614 hashes[1] |= (1 << (h - 32)); 615 mcnt++; 616 } 617 618 if (mcnt) 619 rxfilt |= RL_RXCFG_RX_MULTI; 620 else 621 rxfilt &= ~RL_RXCFG_RX_MULTI; 622 623 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 624 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 625 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 626 627 return; 628 } 629 630 static void 631 re_reset(sc) 632 struct rl_softc *sc; 633 { 634 register int i; 635 636 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 637 638 for (i = 0; i < RL_TIMEOUT; i++) { 639 DELAY(10); 640 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 641 break; 642 } 643 if (i == RL_TIMEOUT) 644 printf("re%d: reset never completed!\n", sc->rl_unit); 645 646 CSR_WRITE_1(sc, 0x82, 1); 647 648 return; 649 } 650 651 /* 652 * The following routine is designed to test for a defect on some 653 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 654 * lines connected to the bus, however for a 32-bit only card, they 655 * should be pulled high. The result of this defect is that the 656 * NIC will not work right if you plug it into a 64-bit slot: DMA 657 * operations will be done with 64-bit transfers, which will fail 658 * because the 64-bit data lines aren't connected. 659 * 660 * There's no way to work around this (short of talking a soldering 661 * iron to the board), however we can detect it. The method we use 662 * here is to put the NIC into digital loopback mode, set the receiver 663 * to promiscuous mode, and then try to send a frame. We then compare 664 * the frame data we sent to what was received. If the data matches, 665 * then the NIC is working correctly, otherwise we know the user has 666 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 667 * slot. In the latter case, there's no way the NIC can work correctly, 668 * so we print out a message on the console and abort the device attach. 669 */ 670 671 static int 672 re_diag(sc) 673 struct rl_softc *sc; 674 { 675 struct ifnet *ifp = &sc->arpcom.ac_if; 676 struct mbuf *m0; 677 struct ether_header *eh; 678 struct rl_desc *cur_rx; 679 u_int16_t status; 680 u_int32_t rxstat; 681 int total_len, i, error = 0; 682 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 683 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 684 685 /* Allocate a single mbuf */ 686 687 MGETHDR(m0, M_DONTWAIT, MT_DATA); 688 if (m0 == NULL) 689 return(ENOBUFS); 690 691 /* 692 * Initialize the NIC in test mode. This sets the chip up 693 * so that it can send and receive frames, but performs the 694 * following special functions: 695 * - Puts receiver in promiscuous mode 696 * - Enables digital loopback mode 697 * - Leaves interrupts turned off 698 */ 699 700 ifp->if_flags |= IFF_PROMISC; 701 sc->rl_testmode = 1; 702 re_init(sc); 703 re_stop(sc); 704 DELAY(100000); 705 re_init(sc); 706 707 /* Put some data in the mbuf */ 708 709 eh = mtod(m0, struct ether_header *); 710 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 711 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 712 eh->ether_type = htons(ETHERTYPE_IP); 713 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 714 715 /* 716 * Queue the packet, start transmission. 717 * Note: IF_HANDOFF() ultimately calls re_start() for us. 718 */ 719 720 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 721 IF_HANDOFF(&ifp->if_snd, m0, ifp); 722 m0 = NULL; 723 724 /* Wait for it to propagate through the chip */ 725 726 DELAY(100000); 727 for (i = 0; i < RL_TIMEOUT; i++) { 728 status = CSR_READ_2(sc, RL_ISR); 729 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 730 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 731 break; 732 DELAY(10); 733 } 734 735 if (i == RL_TIMEOUT) { 736 printf("re%d: diagnostic failed, failed to receive packet " 737 "in loopback mode\n", sc->rl_unit); 738 error = EIO; 739 goto done; 740 } 741 742 /* 743 * The packet should have been dumped into the first 744 * entry in the RX DMA ring. Grab it from there. 745 */ 746 747 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 748 sc->rl_ldata.rl_rx_list_map, 749 BUS_DMASYNC_POSTREAD); 750 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 751 sc->rl_ldata.rl_rx_dmamap[0], 752 BUS_DMASYNC_POSTWRITE); 753 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 754 sc->rl_ldata.rl_rx_dmamap[0]); 755 756 m0 = sc->rl_ldata.rl_rx_mbuf[0]; 757 sc->rl_ldata.rl_rx_mbuf[0] = NULL; 758 eh = mtod(m0, struct ether_header *); 759 760 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 761 total_len = RL_RXBYTES(cur_rx); 762 rxstat = le32toh(cur_rx->rl_cmdstat); 763 764 if (total_len != ETHER_MIN_LEN) { 765 printf("re%d: diagnostic failed, received short packet\n", 766 sc->rl_unit); 767 error = EIO; 768 goto done; 769 } 770 771 /* Test that the received packet data matches what we sent. */ 772 773 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 774 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 775 ntohs(eh->ether_type) != ETHERTYPE_IP) { 776 printf("re%d: WARNING, DMA FAILURE!\n", sc->rl_unit); 777 printf("re%d: expected TX data: %6D/%6D/0x%x\n", sc->rl_unit, 778 dst, ":", src, ":", ETHERTYPE_IP); 779 printf("re%d: received RX data: %6D/%6D/0x%x\n", sc->rl_unit, 780 eh->ether_dhost, ":", eh->ether_shost, ":", 781 ntohs(eh->ether_type)); 782 printf("re%d: You may have a defective 32-bit NIC plugged " 783 "into a 64-bit PCI slot.\n", sc->rl_unit); 784 printf("re%d: Please re-install the NIC in a 32-bit slot " 785 "for proper operation.\n", sc->rl_unit); 786 printf("re%d: Read the re(4) man page for more details.\n", 787 sc->rl_unit); 788 error = EIO; 789 } 790 791 done: 792 /* Turn interface off, release resources */ 793 794 sc->rl_testmode = 0; 795 ifp->if_flags &= ~IFF_PROMISC; 796 re_stop(sc); 797 if (m0 != NULL) 798 m_freem(m0); 799 800 return (error); 801 } 802 803 /* 804 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 805 * IDs against our list and return a device name if we find a match. 806 */ 807 static int 808 re_probe(dev) 809 device_t dev; 810 { 811 struct rl_type *t; 812 struct rl_softc *sc; 813 int rid; 814 u_int32_t hwrev; 815 816 t = re_devs; 817 sc = device_get_softc(dev); 818 819 while(t->rl_name != NULL) { 820 if ((pci_get_vendor(dev) == t->rl_vid) && 821 (pci_get_device(dev) == t->rl_did)) { 822 823 /* 824 * Temporarily map the I/O space 825 * so we can read the chip ID register. 826 */ 827 rid = RL_RID; 828 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 829 RF_ACTIVE); 830 if (sc->rl_res == NULL) { 831 device_printf(dev, 832 "couldn't map ports/memory\n"); 833 return(ENXIO); 834 } 835 sc->rl_btag = rman_get_bustag(sc->rl_res); 836 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 837 mtx_init(&sc->rl_mtx, 838 device_get_nameunit(dev), 839 MTX_NETWORK_LOCK, MTX_DEF); 840 RL_LOCK(sc); 841 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 842 bus_release_resource(dev, RL_RES, 843 RL_RID, sc->rl_res); 844 RL_UNLOCK(sc); 845 mtx_destroy(&sc->rl_mtx); 846 if (t->rl_basetype == hwrev) { 847 device_set_desc(dev, t->rl_name); 848 return(0); 849 } 850 } 851 t++; 852 } 853 854 return(ENXIO); 855 } 856 857 /* 858 * This routine takes the segment list provided as the result of 859 * a bus_dma_map_load() operation and assigns the addresses/lengths 860 * to RealTek DMA descriptors. This can be called either by the RX 861 * code or the TX code. In the RX case, we'll probably wind up mapping 862 * at most one segment. For the TX case, there could be any number of 863 * segments since TX packets may span multiple mbufs. In either case, 864 * if the number of segments is larger than the rl_maxsegs limit 865 * specified by the caller, we abort the mapping operation. Sadly, 866 * whoever designed the buffer mapping API did not provide a way to 867 * return an error from here, so we have to fake it a bit. 868 */ 869 870 static void 871 re_dma_map_desc(arg, segs, nseg, mapsize, error) 872 void *arg; 873 bus_dma_segment_t *segs; 874 int nseg; 875 bus_size_t mapsize; 876 int error; 877 { 878 struct rl_dmaload_arg *ctx; 879 struct rl_desc *d = NULL; 880 int i = 0, idx; 881 882 if (error) 883 return; 884 885 ctx = arg; 886 887 /* Signal error to caller if there's too many segments */ 888 if (nseg > ctx->rl_maxsegs) { 889 ctx->rl_maxsegs = 0; 890 return; 891 } 892 893 /* 894 * Map the segment array into descriptors. Note that we set the 895 * start-of-frame and end-of-frame markers for either TX or RX, but 896 * they really only have meaning in the TX case. (In the RX case, 897 * it's the chip that tells us where packets begin and end.) 898 * We also keep track of the end of the ring and set the 899 * end-of-ring bits as needed, and we set the ownership bits 900 * in all except the very first descriptor. (The caller will 901 * set this descriptor later when it start transmission or 902 * reception.) 903 */ 904 idx = ctx->rl_idx; 905 while(1) { 906 u_int32_t cmdstat; 907 d = &ctx->rl_ring[idx]; 908 if (le32toh(d->rl_cmdstat) & RL_RDESC_STAT_OWN) { 909 ctx->rl_maxsegs = 0; 910 return; 911 } 912 cmdstat = segs[i].ds_len; 913 d->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 914 d->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 915 if (i == 0) 916 cmdstat |= RL_TDESC_CMD_SOF; 917 else 918 cmdstat |= RL_TDESC_CMD_OWN; 919 if (idx == (RL_RX_DESC_CNT - 1)) 920 cmdstat |= RL_TDESC_CMD_EOR; 921 d->rl_cmdstat = htole32(cmdstat | ctx->rl_flags); 922 i++; 923 if (i == nseg) 924 break; 925 RL_DESC_INC(idx); 926 } 927 928 d->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 929 ctx->rl_maxsegs = nseg; 930 ctx->rl_idx = idx; 931 932 return; 933 } 934 935 /* 936 * Map a single buffer address. 937 */ 938 939 static void 940 re_dma_map_addr(arg, segs, nseg, error) 941 void *arg; 942 bus_dma_segment_t *segs; 943 int nseg; 944 int error; 945 { 946 u_int32_t *addr; 947 948 if (error) 949 return; 950 951 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 952 addr = arg; 953 *addr = segs->ds_addr; 954 955 return; 956 } 957 958 static int 959 re_allocmem(dev, sc) 960 device_t dev; 961 struct rl_softc *sc; 962 { 963 int error; 964 int nseg; 965 int i; 966 967 /* 968 * Allocate map for RX mbufs. 969 */ 970 nseg = 32; 971 error = bus_dma_tag_create(sc->rl_parent_tag, ETHER_ALIGN, 0, 972 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 973 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 974 NULL, NULL, &sc->rl_ldata.rl_mtag); 975 if (error) { 976 device_printf(dev, "could not allocate dma tag\n"); 977 return (ENOMEM); 978 } 979 980 /* 981 * Allocate map for TX descriptor list. 982 */ 983 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 984 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 985 NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 986 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 987 if (error) { 988 device_printf(dev, "could not allocate dma tag\n"); 989 return (ENOMEM); 990 } 991 992 /* Allocate DMA'able memory for the TX ring */ 993 994 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 995 (void **)&sc->rl_ldata.rl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 996 &sc->rl_ldata.rl_tx_list_map); 997 if (error) 998 return (ENOMEM); 999 1000 /* Load the map for the TX ring. */ 1001 1002 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1003 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1004 RL_TX_LIST_SZ, re_dma_map_addr, 1005 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1006 1007 /* Create DMA maps for TX buffers */ 1008 1009 for (i = 0; i < RL_TX_DESC_CNT; i++) { 1010 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1011 &sc->rl_ldata.rl_tx_dmamap[i]); 1012 if (error) { 1013 device_printf(dev, "can't create DMA map for TX\n"); 1014 return(ENOMEM); 1015 } 1016 } 1017 1018 /* 1019 * Allocate map for RX descriptor list. 1020 */ 1021 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1022 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1023 NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 1024 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1025 if (error) { 1026 device_printf(dev, "could not allocate dma tag\n"); 1027 return (ENOMEM); 1028 } 1029 1030 /* Allocate DMA'able memory for the RX ring */ 1031 1032 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1033 (void **)&sc->rl_ldata.rl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1034 &sc->rl_ldata.rl_rx_list_map); 1035 if (error) 1036 return (ENOMEM); 1037 1038 /* Load the map for the RX ring. */ 1039 1040 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1041 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1042 RL_TX_LIST_SZ, re_dma_map_addr, 1043 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1044 1045 /* Create DMA maps for RX buffers */ 1046 1047 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1048 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1049 &sc->rl_ldata.rl_rx_dmamap[i]); 1050 if (error) { 1051 device_printf(dev, "can't create DMA map for RX\n"); 1052 return(ENOMEM); 1053 } 1054 } 1055 1056 return(0); 1057 } 1058 1059 /* 1060 * Attach the interface. Allocate softc structures, do ifmedia 1061 * setup and ethernet/BPF attach. 1062 */ 1063 static int 1064 re_attach(dev) 1065 device_t dev; 1066 { 1067 u_char eaddr[ETHER_ADDR_LEN]; 1068 u_int16_t as[3]; 1069 struct rl_softc *sc; 1070 struct ifnet *ifp; 1071 struct rl_hwrev *hw_rev; 1072 int hwrev; 1073 u_int16_t re_did = 0; 1074 int unit, error = 0, rid, i; 1075 1076 sc = device_get_softc(dev); 1077 unit = device_get_unit(dev); 1078 1079 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1080 MTX_DEF | MTX_RECURSE); 1081 /* 1082 * Map control/status registers. 1083 */ 1084 pci_enable_busmaster(dev); 1085 1086 rid = RL_RID; 1087 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 1088 RF_ACTIVE); 1089 1090 if (sc->rl_res == NULL) { 1091 printf ("re%d: couldn't map ports/memory\n", unit); 1092 error = ENXIO; 1093 goto fail; 1094 } 1095 1096 sc->rl_btag = rman_get_bustag(sc->rl_res); 1097 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1098 1099 /* Allocate interrupt */ 1100 rid = 0; 1101 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1102 RF_SHAREABLE | RF_ACTIVE); 1103 1104 if (sc->rl_irq == NULL) { 1105 printf("re%d: couldn't map interrupt\n", unit); 1106 error = ENXIO; 1107 goto fail; 1108 } 1109 1110 /* Reset the adapter. */ 1111 re_reset(sc); 1112 1113 hw_rev = re_hwrevs; 1114 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 1115 while (hw_rev->rl_desc != NULL) { 1116 if (hw_rev->rl_rev == hwrev) { 1117 sc->rl_type = hw_rev->rl_type; 1118 break; 1119 } 1120 hw_rev++; 1121 } 1122 1123 if (sc->rl_type == RL_8169) { 1124 1125 /* Set RX length mask */ 1126 1127 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1128 1129 /* Force station address autoload from the EEPROM */ 1130 1131 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_AUTOLOAD); 1132 for (i = 0; i < RL_TIMEOUT; i++) { 1133 if (!(CSR_READ_1(sc, RL_EECMD) & RL_EEMODE_AUTOLOAD)) 1134 break; 1135 DELAY(100); 1136 } 1137 if (i == RL_TIMEOUT) 1138 printf ("re%d: eeprom autoload timed out\n", unit); 1139 1140 for (i = 0; i < ETHER_ADDR_LEN; i++) 1141 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1142 } else { 1143 1144 /* Set RX length mask */ 1145 1146 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1147 1148 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 1149 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1, 0); 1150 if (re_did != 0x8129) 1151 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 1152 1153 /* 1154 * Get station address from the EEPROM. 1155 */ 1156 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0); 1157 for (i = 0; i < 3; i++) { 1158 eaddr[(i * 2) + 0] = as[i] & 0xff; 1159 eaddr[(i * 2) + 1] = as[i] >> 8; 1160 } 1161 } 1162 1163 sc->rl_unit = unit; 1164 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1165 1166 /* 1167 * Allocate the parent bus DMA tag appropriate for PCI. 1168 */ 1169 #define RL_NSEG_NEW 32 1170 error = bus_dma_tag_create(NULL, /* parent */ 1171 1, 0, /* alignment, boundary */ 1172 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1173 BUS_SPACE_MAXADDR, /* highaddr */ 1174 NULL, NULL, /* filter, filterarg */ 1175 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 1176 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1177 BUS_DMA_ALLOCNOW, /* flags */ 1178 NULL, NULL, /* lockfunc, lockarg */ 1179 &sc->rl_parent_tag); 1180 if (error) 1181 goto fail; 1182 1183 error = re_allocmem(dev, sc); 1184 1185 if (error) 1186 goto fail; 1187 1188 /* Do MII setup */ 1189 if (mii_phy_probe(dev, &sc->rl_miibus, 1190 re_ifmedia_upd, re_ifmedia_sts)) { 1191 printf("re%d: MII without any phy!\n", sc->rl_unit); 1192 error = ENXIO; 1193 goto fail; 1194 } 1195 1196 ifp = &sc->arpcom.ac_if; 1197 ifp->if_softc = sc; 1198 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1199 ifp->if_mtu = ETHERMTU; 1200 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1201 ifp->if_ioctl = re_ioctl; 1202 ifp->if_capabilities = IFCAP_VLAN_MTU; 1203 ifp->if_start = re_start; 1204 ifp->if_hwassist = RE_CSUM_FEATURES; 1205 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1206 #ifdef DEVICE_POLLING 1207 ifp->if_capabilities |= IFCAP_POLLING; 1208 #endif 1209 ifp->if_watchdog = re_watchdog; 1210 ifp->if_init = re_init; 1211 if (sc->rl_type == RL_8169) 1212 ifp->if_baudrate = 1000000000; 1213 else 1214 ifp->if_baudrate = 100000000; 1215 ifp->if_snd.ifq_maxlen = RL_IFQ_MAXLEN; 1216 ifp->if_capenable = ifp->if_capabilities; 1217 1218 callout_handle_init(&sc->rl_stat_ch); 1219 1220 /* 1221 * Call MI attach routine. 1222 */ 1223 ether_ifattach(ifp, eaddr); 1224 1225 /* Perform hardware diagnostic. */ 1226 error = re_diag(sc); 1227 1228 if (error) { 1229 printf("re%d: attach aborted due to hardware diag failure\n", 1230 unit); 1231 ether_ifdetach(ifp); 1232 goto fail; 1233 } 1234 1235 /* Hook interrupt last to avoid having to lock softc */ 1236 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, 1237 re_intr, sc, &sc->rl_intrhand); 1238 1239 if (error) { 1240 printf("re%d: couldn't set up irq\n", unit); 1241 ether_ifdetach(ifp); 1242 goto fail; 1243 } 1244 1245 fail: 1246 if (error) 1247 re_detach(dev); 1248 1249 return (error); 1250 } 1251 1252 /* 1253 * Shutdown hardware and free up resources. This can be called any 1254 * time after the mutex has been initialized. It is called in both 1255 * the error case in attach and the normal detach case so it needs 1256 * to be careful about only freeing resources that have actually been 1257 * allocated. 1258 */ 1259 static int 1260 re_detach(dev) 1261 device_t dev; 1262 { 1263 struct rl_softc *sc; 1264 struct ifnet *ifp; 1265 int i; 1266 1267 sc = device_get_softc(dev); 1268 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized")); 1269 RL_LOCK(sc); 1270 ifp = &sc->arpcom.ac_if; 1271 1272 /* These should only be active if attach succeeded */ 1273 if (device_is_attached(dev)) { 1274 re_stop(sc); 1275 /* 1276 * Force off the IFF_UP flag here, in case someone 1277 * still had a BPF descriptor attached to this 1278 * interface. If they do, ether_ifattach() will cause 1279 * the BPF code to try and clear the promisc mode 1280 * flag, which will bubble down to re_ioctl(), 1281 * which will try to call re_init() again. This will 1282 * turn the NIC back on and restart the MII ticker, 1283 * which will panic the system when the kernel tries 1284 * to invoke the re_tick() function that isn't there 1285 * anymore. 1286 */ 1287 ifp->if_flags &= ~IFF_UP; 1288 ether_ifdetach(ifp); 1289 } 1290 if (sc->rl_miibus) 1291 device_delete_child(dev, sc->rl_miibus); 1292 bus_generic_detach(dev); 1293 1294 if (sc->rl_intrhand) 1295 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1296 if (sc->rl_irq) 1297 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1298 if (sc->rl_res) 1299 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1300 1301 1302 /* Unload and free the RX DMA ring memory and map */ 1303 1304 if (sc->rl_ldata.rl_rx_list_tag) { 1305 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1306 sc->rl_ldata.rl_rx_list_map); 1307 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1308 sc->rl_ldata.rl_rx_list, 1309 sc->rl_ldata.rl_rx_list_map); 1310 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1311 } 1312 1313 /* Unload and free the TX DMA ring memory and map */ 1314 1315 if (sc->rl_ldata.rl_tx_list_tag) { 1316 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1317 sc->rl_ldata.rl_tx_list_map); 1318 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1319 sc->rl_ldata.rl_tx_list, 1320 sc->rl_ldata.rl_tx_list_map); 1321 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1322 } 1323 1324 /* Destroy all the RX and TX buffer maps */ 1325 1326 if (sc->rl_ldata.rl_mtag) { 1327 for (i = 0; i < RL_TX_DESC_CNT; i++) 1328 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1329 sc->rl_ldata.rl_tx_dmamap[i]); 1330 for (i = 0; i < RL_RX_DESC_CNT; i++) 1331 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1332 sc->rl_ldata.rl_rx_dmamap[i]); 1333 bus_dma_tag_destroy(sc->rl_ldata.rl_mtag); 1334 } 1335 1336 /* Unload and free the stats buffer and map */ 1337 1338 if (sc->rl_ldata.rl_stag) { 1339 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1340 sc->rl_ldata.rl_rx_list_map); 1341 bus_dmamem_free(sc->rl_ldata.rl_stag, 1342 sc->rl_ldata.rl_stats, 1343 sc->rl_ldata.rl_smap); 1344 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1345 } 1346 1347 if (sc->rl_parent_tag) 1348 bus_dma_tag_destroy(sc->rl_parent_tag); 1349 1350 RL_UNLOCK(sc); 1351 mtx_destroy(&sc->rl_mtx); 1352 1353 return(0); 1354 } 1355 1356 static int 1357 re_newbuf(sc, idx, m) 1358 struct rl_softc *sc; 1359 int idx; 1360 struct mbuf *m; 1361 { 1362 struct rl_dmaload_arg arg; 1363 struct mbuf *n = NULL; 1364 int error; 1365 1366 if (m == NULL) { 1367 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1368 if (n == NULL) 1369 return(ENOBUFS); 1370 m = n; 1371 } else 1372 m->m_data = m->m_ext.ext_buf; 1373 1374 /* 1375 * Initialize mbuf length fields and fixup 1376 * alignment so that the frame payload is 1377 * longword aligned. 1378 */ 1379 m->m_len = m->m_pkthdr.len = MCLBYTES; 1380 m_adj(m, ETHER_ALIGN); 1381 1382 arg.sc = sc; 1383 arg.rl_idx = idx; 1384 arg.rl_maxsegs = 1; 1385 arg.rl_flags = 0; 1386 arg.rl_ring = sc->rl_ldata.rl_rx_list; 1387 1388 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, 1389 sc->rl_ldata.rl_rx_dmamap[idx], m, re_dma_map_desc, 1390 &arg, BUS_DMA_NOWAIT); 1391 if (error || arg.rl_maxsegs != 1) { 1392 if (n != NULL) 1393 m_freem(n); 1394 return (ENOMEM); 1395 } 1396 1397 sc->rl_ldata.rl_rx_list[idx].rl_cmdstat |= htole32(RL_RDESC_CMD_OWN); 1398 sc->rl_ldata.rl_rx_mbuf[idx] = m; 1399 1400 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1401 sc->rl_ldata.rl_rx_dmamap[idx], 1402 BUS_DMASYNC_PREREAD); 1403 1404 return(0); 1405 } 1406 1407 static int 1408 re_tx_list_init(sc) 1409 struct rl_softc *sc; 1410 { 1411 bzero ((char *)sc->rl_ldata.rl_tx_list, RL_TX_LIST_SZ); 1412 bzero ((char *)&sc->rl_ldata.rl_tx_mbuf, 1413 (RL_TX_DESC_CNT * sizeof(struct mbuf *))); 1414 1415 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1416 sc->rl_ldata.rl_tx_list_map, BUS_DMASYNC_PREWRITE); 1417 sc->rl_ldata.rl_tx_prodidx = 0; 1418 sc->rl_ldata.rl_tx_considx = 0; 1419 sc->rl_ldata.rl_tx_free = RL_TX_DESC_CNT; 1420 1421 return(0); 1422 } 1423 1424 static int 1425 re_rx_list_init(sc) 1426 struct rl_softc *sc; 1427 { 1428 int i; 1429 1430 bzero ((char *)sc->rl_ldata.rl_rx_list, RL_RX_LIST_SZ); 1431 bzero ((char *)&sc->rl_ldata.rl_rx_mbuf, 1432 (RL_RX_DESC_CNT * sizeof(struct mbuf *))); 1433 1434 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1435 if (re_newbuf(sc, i, NULL) == ENOBUFS) 1436 return(ENOBUFS); 1437 } 1438 1439 /* Flush the RX descriptors */ 1440 1441 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1442 sc->rl_ldata.rl_rx_list_map, 1443 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1444 1445 sc->rl_ldata.rl_rx_prodidx = 0; 1446 sc->rl_head = sc->rl_tail = NULL; 1447 1448 return(0); 1449 } 1450 1451 /* 1452 * RX handler for C+ and 8169. For the gigE chips, we support 1453 * the reception of jumbo frames that have been fragmented 1454 * across multiple 2K mbuf cluster buffers. 1455 */ 1456 static void 1457 re_rxeof(sc) 1458 struct rl_softc *sc; 1459 { 1460 struct mbuf *m; 1461 struct ifnet *ifp; 1462 int i, total_len; 1463 struct rl_desc *cur_rx; 1464 u_int32_t rxstat, rxvlan; 1465 1466 RL_LOCK_ASSERT(sc); 1467 1468 ifp = &sc->arpcom.ac_if; 1469 i = sc->rl_ldata.rl_rx_prodidx; 1470 1471 /* Invalidate the descriptor memory */ 1472 1473 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1474 sc->rl_ldata.rl_rx_list_map, 1475 BUS_DMASYNC_POSTREAD); 1476 1477 while (!RL_OWN(&sc->rl_ldata.rl_rx_list[i])) { 1478 1479 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1480 m = sc->rl_ldata.rl_rx_mbuf[i]; 1481 total_len = RL_RXBYTES(cur_rx); 1482 rxstat = le32toh(cur_rx->rl_cmdstat); 1483 rxvlan = le32toh(cur_rx->rl_vlanctl); 1484 1485 /* Invalidate the RX mbuf and unload its map */ 1486 1487 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1488 sc->rl_ldata.rl_rx_dmamap[i], 1489 BUS_DMASYNC_POSTWRITE); 1490 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1491 sc->rl_ldata.rl_rx_dmamap[i]); 1492 1493 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1494 m->m_len = MCLBYTES - ETHER_ALIGN; 1495 if (sc->rl_head == NULL) 1496 sc->rl_head = sc->rl_tail = m; 1497 else { 1498 m->m_flags &= ~M_PKTHDR; 1499 sc->rl_tail->m_next = m; 1500 sc->rl_tail = m; 1501 } 1502 re_newbuf(sc, i, NULL); 1503 RL_DESC_INC(i); 1504 continue; 1505 } 1506 1507 /* 1508 * NOTE: for the 8139C+, the frame length field 1509 * is always 12 bits in size, but for the gigE chips, 1510 * it is 13 bits (since the max RX frame length is 16K). 1511 * Unfortunately, all 32 bits in the status word 1512 * were already used, so to make room for the extra 1513 * length bit, RealTek took out the 'frame alignment 1514 * error' bit and shifted the other status bits 1515 * over one slot. The OWN, EOR, FS and LS bits are 1516 * still in the same places. We have already extracted 1517 * the frame length and checked the OWN bit, so rather 1518 * than using an alternate bit mapping, we shift the 1519 * status bits one space to the right so we can evaluate 1520 * them using the 8169 status as though it was in the 1521 * same format as that of the 8139C+. 1522 */ 1523 if (sc->rl_type == RL_8169) 1524 rxstat >>= 1; 1525 1526 if (rxstat & RL_RDESC_STAT_RXERRSUM) { 1527 ifp->if_ierrors++; 1528 /* 1529 * If this is part of a multi-fragment packet, 1530 * discard all the pieces. 1531 */ 1532 if (sc->rl_head != NULL) { 1533 m_freem(sc->rl_head); 1534 sc->rl_head = sc->rl_tail = NULL; 1535 } 1536 re_newbuf(sc, i, m); 1537 RL_DESC_INC(i); 1538 continue; 1539 } 1540 1541 /* 1542 * If allocating a replacement mbuf fails, 1543 * reload the current one. 1544 */ 1545 1546 if (re_newbuf(sc, i, NULL)) { 1547 ifp->if_ierrors++; 1548 if (sc->rl_head != NULL) { 1549 m_freem(sc->rl_head); 1550 sc->rl_head = sc->rl_tail = NULL; 1551 } 1552 re_newbuf(sc, i, m); 1553 RL_DESC_INC(i); 1554 continue; 1555 } 1556 1557 RL_DESC_INC(i); 1558 1559 if (sc->rl_head != NULL) { 1560 m->m_len = total_len % (MCLBYTES - ETHER_ALIGN); 1561 /* 1562 * Special case: if there's 4 bytes or less 1563 * in this buffer, the mbuf can be discarded: 1564 * the last 4 bytes is the CRC, which we don't 1565 * care about anyway. 1566 */ 1567 if (m->m_len <= ETHER_CRC_LEN) { 1568 sc->rl_tail->m_len -= 1569 (ETHER_CRC_LEN - m->m_len); 1570 m_freem(m); 1571 } else { 1572 m->m_len -= ETHER_CRC_LEN; 1573 m->m_flags &= ~M_PKTHDR; 1574 sc->rl_tail->m_next = m; 1575 } 1576 m = sc->rl_head; 1577 sc->rl_head = sc->rl_tail = NULL; 1578 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1579 } else 1580 m->m_pkthdr.len = m->m_len = 1581 (total_len - ETHER_CRC_LEN); 1582 1583 ifp->if_ipackets++; 1584 m->m_pkthdr.rcvif = ifp; 1585 1586 /* Do RX checksumming if enabled */ 1587 1588 if (ifp->if_capenable & IFCAP_RXCSUM) { 1589 1590 /* Check IP header checksum */ 1591 if (rxstat & RL_RDESC_STAT_PROTOID) 1592 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1593 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1594 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1595 1596 /* Check TCP/UDP checksum */ 1597 if ((RL_TCPPKT(rxstat) && 1598 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1599 (RL_UDPPKT(rxstat) && 1600 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1601 m->m_pkthdr.csum_flags |= 1602 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1603 m->m_pkthdr.csum_data = 0xffff; 1604 } 1605 } 1606 1607 if (rxvlan & RL_RDESC_VLANCTL_TAG) 1608 VLAN_INPUT_TAG(ifp, m, 1609 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)), continue); 1610 RL_UNLOCK(sc); 1611 (*ifp->if_input)(ifp, m); 1612 RL_LOCK(sc); 1613 } 1614 1615 /* Flush the RX DMA ring */ 1616 1617 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1618 sc->rl_ldata.rl_rx_list_map, 1619 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1620 1621 sc->rl_ldata.rl_rx_prodidx = i; 1622 1623 return; 1624 } 1625 1626 static void 1627 re_txeof(sc) 1628 struct rl_softc *sc; 1629 { 1630 struct ifnet *ifp; 1631 u_int32_t txstat; 1632 int idx; 1633 1634 ifp = &sc->arpcom.ac_if; 1635 idx = sc->rl_ldata.rl_tx_considx; 1636 1637 /* Invalidate the TX descriptor list */ 1638 1639 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1640 sc->rl_ldata.rl_tx_list_map, 1641 BUS_DMASYNC_POSTREAD); 1642 1643 while (idx != sc->rl_ldata.rl_tx_prodidx) { 1644 1645 txstat = le32toh(sc->rl_ldata.rl_tx_list[idx].rl_cmdstat); 1646 if (txstat & RL_TDESC_CMD_OWN) 1647 break; 1648 1649 /* 1650 * We only stash mbufs in the last descriptor 1651 * in a fragment chain, which also happens to 1652 * be the only place where the TX status bits 1653 * are valid. 1654 */ 1655 1656 if (txstat & RL_TDESC_CMD_EOF) { 1657 m_freem(sc->rl_ldata.rl_tx_mbuf[idx]); 1658 sc->rl_ldata.rl_tx_mbuf[idx] = NULL; 1659 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1660 sc->rl_ldata.rl_tx_dmamap[idx]); 1661 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 1662 RL_TDESC_STAT_COLCNT)) 1663 ifp->if_collisions++; 1664 if (txstat & RL_TDESC_STAT_TXERRSUM) 1665 ifp->if_oerrors++; 1666 else 1667 ifp->if_opackets++; 1668 } 1669 sc->rl_ldata.rl_tx_free++; 1670 RL_DESC_INC(idx); 1671 } 1672 1673 /* No changes made to the TX ring, so no flush needed */ 1674 1675 if (idx != sc->rl_ldata.rl_tx_considx) { 1676 sc->rl_ldata.rl_tx_considx = idx; 1677 ifp->if_flags &= ~IFF_OACTIVE; 1678 ifp->if_timer = 0; 1679 } 1680 1681 /* 1682 * If not all descriptors have been released reaped yet, 1683 * reload the timer so that we will eventually get another 1684 * interrupt that will cause us to re-enter this routine. 1685 * This is done in case the transmitter has gone idle. 1686 */ 1687 if (sc->rl_ldata.rl_tx_free != RL_TX_DESC_CNT) 1688 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 1689 1690 return; 1691 } 1692 1693 static void 1694 re_tick(xsc) 1695 void *xsc; 1696 { 1697 struct rl_softc *sc; 1698 struct mii_data *mii; 1699 1700 sc = xsc; 1701 RL_LOCK(sc); 1702 mii = device_get_softc(sc->rl_miibus); 1703 1704 mii_tick(mii); 1705 1706 sc->rl_stat_ch = timeout(re_tick, sc, hz); 1707 RL_UNLOCK(sc); 1708 1709 return; 1710 } 1711 1712 #ifdef DEVICE_POLLING 1713 static void 1714 re_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1715 { 1716 struct rl_softc *sc = ifp->if_softc; 1717 1718 RL_LOCK(sc); 1719 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1720 ether_poll_deregister(ifp); 1721 cmd = POLL_DEREGISTER; 1722 } 1723 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1724 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 1725 goto done; 1726 } 1727 1728 sc->rxcycles = count; 1729 re_rxeof(sc); 1730 re_txeof(sc); 1731 1732 if (ifp->if_snd.ifq_head != NULL) 1733 (*ifp->if_start)(ifp); 1734 1735 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1736 u_int16_t status; 1737 1738 status = CSR_READ_2(sc, RL_ISR); 1739 if (status == 0xffff) 1740 goto done; 1741 if (status) 1742 CSR_WRITE_2(sc, RL_ISR, status); 1743 1744 /* 1745 * XXX check behaviour on receiver stalls. 1746 */ 1747 1748 if (status & RL_ISR_SYSTEM_ERR) { 1749 re_reset(sc); 1750 re_init(sc); 1751 } 1752 } 1753 done: 1754 RL_UNLOCK(sc); 1755 } 1756 #endif /* DEVICE_POLLING */ 1757 1758 static void 1759 re_intr(arg) 1760 void *arg; 1761 { 1762 struct rl_softc *sc; 1763 struct ifnet *ifp; 1764 u_int16_t status; 1765 1766 sc = arg; 1767 1768 if (sc->suspended) { 1769 return; 1770 } 1771 1772 RL_LOCK(sc); 1773 ifp = &sc->arpcom.ac_if; 1774 1775 if (!(ifp->if_flags & IFF_UP)) { 1776 RL_UNLOCK(sc); 1777 return; 1778 } 1779 1780 #ifdef DEVICE_POLLING 1781 if (ifp->if_flags & IFF_POLLING) 1782 goto done; 1783 if ((ifp->if_capenable & IFCAP_POLLING) && 1784 ether_poll_register(re_poll, ifp)) { /* ok, disable interrupts */ 1785 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1786 re_poll(ifp, 0, 1); 1787 goto done; 1788 } 1789 #endif /* DEVICE_POLLING */ 1790 1791 for (;;) { 1792 1793 status = CSR_READ_2(sc, RL_ISR); 1794 /* If the card has gone away the read returns 0xffff. */ 1795 if (status == 0xffff) 1796 break; 1797 if (status) 1798 CSR_WRITE_2(sc, RL_ISR, status); 1799 1800 if ((status & RL_INTRS_CPLUS) == 0) 1801 break; 1802 1803 if (status & RL_ISR_RX_OK) 1804 re_rxeof(sc); 1805 1806 if (status & RL_ISR_RX_ERR) 1807 re_rxeof(sc); 1808 1809 if ((status & RL_ISR_TIMEOUT_EXPIRED) || 1810 (status & RL_ISR_TX_ERR) || 1811 (status & RL_ISR_TX_DESC_UNAVAIL)) 1812 re_txeof(sc); 1813 1814 if (status & RL_ISR_SYSTEM_ERR) { 1815 re_reset(sc); 1816 re_init(sc); 1817 } 1818 1819 if (status & RL_ISR_LINKCHG) { 1820 untimeout(re_tick, sc, sc->rl_stat_ch); 1821 re_tick(sc); 1822 } 1823 } 1824 1825 if (ifp->if_snd.ifq_head != NULL) 1826 (*ifp->if_start)(ifp); 1827 1828 #ifdef DEVICE_POLLING 1829 done: 1830 #endif 1831 RL_UNLOCK(sc); 1832 1833 return; 1834 } 1835 1836 static int 1837 re_encap(sc, m_head, idx) 1838 struct rl_softc *sc; 1839 struct mbuf *m_head; 1840 int *idx; 1841 { 1842 struct mbuf *m_new = NULL; 1843 struct rl_dmaload_arg arg; 1844 bus_dmamap_t map; 1845 int error; 1846 struct m_tag *mtag; 1847 1848 if (sc->rl_ldata.rl_tx_free <= 4) 1849 return(EFBIG); 1850 1851 /* 1852 * Set up checksum offload. Note: checksum offload bits must 1853 * appear in all descriptors of a multi-descriptor transmit 1854 * attempt. (This is according to testing done with an 8169 1855 * chip. I'm not sure if this is a requirement or a bug.) 1856 */ 1857 1858 arg.rl_flags = 0; 1859 1860 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1861 arg.rl_flags |= RL_TDESC_CMD_IPCSUM; 1862 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1863 arg.rl_flags |= RL_TDESC_CMD_TCPCSUM; 1864 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1865 arg.rl_flags |= RL_TDESC_CMD_UDPCSUM; 1866 1867 arg.sc = sc; 1868 arg.rl_idx = *idx; 1869 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 1870 if (arg.rl_maxsegs > 4) 1871 arg.rl_maxsegs -= 4; 1872 arg.rl_ring = sc->rl_ldata.rl_tx_list; 1873 1874 map = sc->rl_ldata.rl_tx_dmamap[*idx]; 1875 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 1876 m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1877 1878 if (error && error != EFBIG) { 1879 printf("re%d: can't map mbuf (error %d)\n", sc->rl_unit, error); 1880 return(ENOBUFS); 1881 } 1882 1883 /* Too many segments to map, coalesce into a single mbuf */ 1884 1885 if (error || arg.rl_maxsegs == 0) { 1886 m_new = m_defrag(m_head, M_DONTWAIT); 1887 if (m_new == NULL) 1888 return(1); 1889 else 1890 m_head = m_new; 1891 1892 arg.sc = sc; 1893 arg.rl_idx = *idx; 1894 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 1895 arg.rl_ring = sc->rl_ldata.rl_tx_list; 1896 1897 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 1898 m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1899 if (error) { 1900 printf("re%d: can't map mbuf (error %d)\n", 1901 sc->rl_unit, error); 1902 return(EFBIG); 1903 } 1904 } 1905 1906 /* 1907 * Insure that the map for this transmission 1908 * is placed at the array index of the last descriptor 1909 * in this chain. 1910 */ 1911 sc->rl_ldata.rl_tx_dmamap[*idx] = 1912 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx]; 1913 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx] = map; 1914 1915 sc->rl_ldata.rl_tx_mbuf[arg.rl_idx] = m_head; 1916 sc->rl_ldata.rl_tx_free -= arg.rl_maxsegs; 1917 1918 /* 1919 * Set up hardware VLAN tagging. Note: vlan tag info must 1920 * appear in the first descriptor of a multi-descriptor 1921 * transmission attempt. 1922 */ 1923 1924 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m_head); 1925 if (mtag != NULL) 1926 sc->rl_ldata.rl_tx_list[*idx].rl_vlanctl = 1927 htole32(htons(VLAN_TAG_VALUE(mtag)) | RL_TDESC_VLANCTL_TAG); 1928 1929 /* Transfer ownership of packet to the chip. */ 1930 1931 sc->rl_ldata.rl_tx_list[arg.rl_idx].rl_cmdstat |= 1932 htole32(RL_TDESC_CMD_OWN); 1933 if (*idx != arg.rl_idx) 1934 sc->rl_ldata.rl_tx_list[*idx].rl_cmdstat |= 1935 htole32(RL_TDESC_CMD_OWN); 1936 1937 RL_DESC_INC(arg.rl_idx); 1938 *idx = arg.rl_idx; 1939 1940 return(0); 1941 } 1942 1943 /* 1944 * Main transmit routine for C+ and gigE NICs. 1945 */ 1946 1947 static void 1948 re_start(ifp) 1949 struct ifnet *ifp; 1950 { 1951 struct rl_softc *sc; 1952 struct mbuf *m_head = NULL; 1953 int idx; 1954 1955 sc = ifp->if_softc; 1956 RL_LOCK(sc); 1957 1958 idx = sc->rl_ldata.rl_tx_prodidx; 1959 1960 while (sc->rl_ldata.rl_tx_mbuf[idx] == NULL) { 1961 IF_DEQUEUE(&ifp->if_snd, m_head); 1962 if (m_head == NULL) 1963 break; 1964 1965 if (re_encap(sc, m_head, &idx)) { 1966 IF_PREPEND(&ifp->if_snd, m_head); 1967 ifp->if_flags |= IFF_OACTIVE; 1968 break; 1969 } 1970 1971 /* 1972 * If there's a BPF listener, bounce a copy of this frame 1973 * to him. 1974 */ 1975 BPF_MTAP(ifp, m_head); 1976 } 1977 1978 /* Flush the TX descriptors */ 1979 1980 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1981 sc->rl_ldata.rl_tx_list_map, 1982 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1983 1984 sc->rl_ldata.rl_tx_prodidx = idx; 1985 1986 /* 1987 * RealTek put the TX poll request register in a different 1988 * location on the 8169 gigE chip. I don't know why. 1989 */ 1990 1991 if (sc->rl_type == RL_8169) 1992 CSR_WRITE_2(sc, RL_GTXSTART, RL_TXSTART_START); 1993 else 1994 CSR_WRITE_2(sc, RL_TXSTART, RL_TXSTART_START); 1995 1996 /* 1997 * Use the countdown timer for interrupt moderation. 1998 * 'TX done' interrupts are disabled. Instead, we reset the 1999 * countdown timer, which will begin counting until it hits 2000 * the value in the TIMERINT register, and then trigger an 2001 * interrupt. Each time we write to the TIMERCNT register, 2002 * the timer count is reset to 0. 2003 */ 2004 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2005 2006 RL_UNLOCK(sc); 2007 2008 /* 2009 * Set a timeout in case the chip goes out to lunch. 2010 */ 2011 ifp->if_timer = 5; 2012 2013 return; 2014 } 2015 2016 static void 2017 re_init(xsc) 2018 void *xsc; 2019 { 2020 struct rl_softc *sc = xsc; 2021 struct ifnet *ifp = &sc->arpcom.ac_if; 2022 struct mii_data *mii; 2023 u_int32_t rxcfg = 0; 2024 2025 RL_LOCK(sc); 2026 mii = device_get_softc(sc->rl_miibus); 2027 2028 /* 2029 * Cancel pending I/O and free all RX/TX buffers. 2030 */ 2031 re_stop(sc); 2032 2033 /* 2034 * Enable C+ RX and TX mode, as well as VLAN stripping and 2035 * RX checksum offload. We must configure the C+ register 2036 * before all others. 2037 */ 2038 CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB| 2039 RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW| 2040 RL_CPLUSCMD_VLANSTRIP| 2041 (ifp->if_capenable & IFCAP_RXCSUM ? 2042 RL_CPLUSCMD_RXCSUM_ENB : 0)); 2043 2044 /* 2045 * Init our MAC address. Even though the chipset 2046 * documentation doesn't mention it, we need to enter "Config 2047 * register write enable" mode to modify the ID registers. 2048 */ 2049 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2050 CSR_WRITE_STREAM_4(sc, RL_IDR0, 2051 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 2052 CSR_WRITE_STREAM_4(sc, RL_IDR4, 2053 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 2054 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2055 2056 /* 2057 * For C+ mode, initialize the RX descriptors and mbufs. 2058 */ 2059 re_rx_list_init(sc); 2060 re_tx_list_init(sc); 2061 2062 /* 2063 * Enable transmit and receive. 2064 */ 2065 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2066 2067 /* 2068 * Set the initial TX and RX configuration. 2069 */ 2070 if (sc->rl_testmode) { 2071 if (sc->rl_type == RL_8169) 2072 CSR_WRITE_4(sc, RL_TXCFG, 2073 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2074 else 2075 CSR_WRITE_4(sc, RL_TXCFG, 2076 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2077 } else 2078 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2079 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 2080 2081 /* Set the individual bit to receive frames for this host only. */ 2082 rxcfg = CSR_READ_4(sc, RL_RXCFG); 2083 rxcfg |= RL_RXCFG_RX_INDIV; 2084 2085 /* If we want promiscuous mode, set the allframes bit. */ 2086 if (ifp->if_flags & IFF_PROMISC) { 2087 rxcfg |= RL_RXCFG_RX_ALLPHYS; 2088 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2089 } else { 2090 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 2091 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2092 } 2093 2094 /* 2095 * Set capture broadcast bit to capture broadcast frames. 2096 */ 2097 if (ifp->if_flags & IFF_BROADCAST) { 2098 rxcfg |= RL_RXCFG_RX_BROAD; 2099 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2100 } else { 2101 rxcfg &= ~RL_RXCFG_RX_BROAD; 2102 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2103 } 2104 2105 /* 2106 * Program the multicast filter, if necessary. 2107 */ 2108 re_setmulti(sc); 2109 2110 #ifdef DEVICE_POLLING 2111 /* 2112 * Disable interrupts if we are polling. 2113 */ 2114 if (ifp->if_flags & IFF_POLLING) 2115 CSR_WRITE_2(sc, RL_IMR, 0); 2116 else /* otherwise ... */ 2117 #endif /* DEVICE_POLLING */ 2118 /* 2119 * Enable interrupts. 2120 */ 2121 if (sc->rl_testmode) 2122 CSR_WRITE_2(sc, RL_IMR, 0); 2123 else 2124 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2125 2126 /* Set initial TX threshold */ 2127 sc->rl_txthresh = RL_TX_THRESH_INIT; 2128 2129 /* Start RX/TX process. */ 2130 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2131 #ifdef notdef 2132 /* Enable receiver and transmitter. */ 2133 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2134 #endif 2135 /* 2136 * Load the addresses of the RX and TX lists into the chip. 2137 */ 2138 2139 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2140 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2141 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2142 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2143 2144 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2145 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2146 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2147 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2148 2149 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2150 2151 /* 2152 * Initialize the timer interrupt register so that 2153 * a timer interrupt will be generated once the timer 2154 * reaches a certain number of ticks. The timer is 2155 * reloaded on each transmit. This gives us TX interrupt 2156 * moderation, which dramatically improves TX frame rate. 2157 */ 2158 2159 if (sc->rl_type == RL_8169) 2160 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2161 else 2162 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2163 2164 /* 2165 * For 8169 gigE NICs, set the max allowed RX packet 2166 * size so we can receive jumbo frames. 2167 */ 2168 if (sc->rl_type == RL_8169) 2169 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2170 2171 if (sc->rl_testmode) { 2172 RL_UNLOCK(sc); 2173 return; 2174 } 2175 2176 mii_mediachg(mii); 2177 2178 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 2179 2180 ifp->if_flags |= IFF_RUNNING; 2181 ifp->if_flags &= ~IFF_OACTIVE; 2182 2183 sc->rl_stat_ch = timeout(re_tick, sc, hz); 2184 RL_UNLOCK(sc); 2185 2186 return; 2187 } 2188 2189 /* 2190 * Set media options. 2191 */ 2192 static int 2193 re_ifmedia_upd(ifp) 2194 struct ifnet *ifp; 2195 { 2196 struct rl_softc *sc; 2197 struct mii_data *mii; 2198 2199 sc = ifp->if_softc; 2200 mii = device_get_softc(sc->rl_miibus); 2201 mii_mediachg(mii); 2202 2203 return(0); 2204 } 2205 2206 /* 2207 * Report current media status. 2208 */ 2209 static void 2210 re_ifmedia_sts(ifp, ifmr) 2211 struct ifnet *ifp; 2212 struct ifmediareq *ifmr; 2213 { 2214 struct rl_softc *sc; 2215 struct mii_data *mii; 2216 2217 sc = ifp->if_softc; 2218 mii = device_get_softc(sc->rl_miibus); 2219 2220 mii_pollstat(mii); 2221 ifmr->ifm_active = mii->mii_media_active; 2222 ifmr->ifm_status = mii->mii_media_status; 2223 2224 return; 2225 } 2226 2227 static int 2228 re_ioctl(ifp, command, data) 2229 struct ifnet *ifp; 2230 u_long command; 2231 caddr_t data; 2232 { 2233 struct rl_softc *sc = ifp->if_softc; 2234 struct ifreq *ifr = (struct ifreq *) data; 2235 struct mii_data *mii; 2236 int error = 0; 2237 2238 RL_LOCK(sc); 2239 2240 switch(command) { 2241 case SIOCSIFMTU: 2242 if (ifr->ifr_mtu > RL_JUMBO_MTU) 2243 error = EINVAL; 2244 ifp->if_mtu = ifr->ifr_mtu; 2245 break; 2246 case SIOCSIFFLAGS: 2247 if (ifp->if_flags & IFF_UP) { 2248 re_init(sc); 2249 } else { 2250 if (ifp->if_flags & IFF_RUNNING) 2251 re_stop(sc); 2252 } 2253 error = 0; 2254 break; 2255 case SIOCADDMULTI: 2256 case SIOCDELMULTI: 2257 re_setmulti(sc); 2258 error = 0; 2259 break; 2260 case SIOCGIFMEDIA: 2261 case SIOCSIFMEDIA: 2262 mii = device_get_softc(sc->rl_miibus); 2263 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2264 break; 2265 case SIOCSIFCAP: 2266 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_POLLING); 2267 ifp->if_capenable |= 2268 ifr->ifr_reqcap & (IFCAP_HWCSUM | IFCAP_POLLING); 2269 if (ifp->if_capenable & IFCAP_TXCSUM) 2270 ifp->if_hwassist = RE_CSUM_FEATURES; 2271 else 2272 ifp->if_hwassist = 0; 2273 if (ifp->if_flags & IFF_RUNNING) 2274 re_init(sc); 2275 break; 2276 default: 2277 error = ether_ioctl(ifp, command, data); 2278 break; 2279 } 2280 2281 RL_UNLOCK(sc); 2282 2283 return(error); 2284 } 2285 2286 static void 2287 re_watchdog(ifp) 2288 struct ifnet *ifp; 2289 { 2290 struct rl_softc *sc; 2291 2292 sc = ifp->if_softc; 2293 RL_LOCK(sc); 2294 printf("re%d: watchdog timeout\n", sc->rl_unit); 2295 ifp->if_oerrors++; 2296 2297 re_txeof(sc); 2298 re_rxeof(sc); 2299 2300 re_init(sc); 2301 2302 RL_UNLOCK(sc); 2303 2304 return; 2305 } 2306 2307 /* 2308 * Stop the adapter and free any mbufs allocated to the 2309 * RX and TX lists. 2310 */ 2311 static void 2312 re_stop(sc) 2313 struct rl_softc *sc; 2314 { 2315 register int i; 2316 struct ifnet *ifp; 2317 2318 RL_LOCK(sc); 2319 ifp = &sc->arpcom.ac_if; 2320 ifp->if_timer = 0; 2321 2322 untimeout(re_tick, sc, sc->rl_stat_ch); 2323 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2324 #ifdef DEVICE_POLLING 2325 ether_poll_deregister(ifp); 2326 #endif /* DEVICE_POLLING */ 2327 2328 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2329 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2330 2331 if (sc->rl_head != NULL) { 2332 m_freem(sc->rl_head); 2333 sc->rl_head = sc->rl_tail = NULL; 2334 } 2335 2336 /* Free the TX list buffers. */ 2337 2338 for (i = 0; i < RL_TX_DESC_CNT; i++) { 2339 if (sc->rl_ldata.rl_tx_mbuf[i] != NULL) { 2340 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2341 sc->rl_ldata.rl_tx_dmamap[i]); 2342 m_freem(sc->rl_ldata.rl_tx_mbuf[i]); 2343 sc->rl_ldata.rl_tx_mbuf[i] = NULL; 2344 } 2345 } 2346 2347 /* Free the RX list buffers. */ 2348 2349 for (i = 0; i < RL_RX_DESC_CNT; i++) { 2350 if (sc->rl_ldata.rl_rx_mbuf[i] != NULL) { 2351 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2352 sc->rl_ldata.rl_rx_dmamap[i]); 2353 m_freem(sc->rl_ldata.rl_rx_mbuf[i]); 2354 sc->rl_ldata.rl_rx_mbuf[i] = NULL; 2355 } 2356 } 2357 2358 RL_UNLOCK(sc); 2359 return; 2360 } 2361 2362 /* 2363 * Device suspend routine. Stop the interface and save some PCI 2364 * settings in case the BIOS doesn't restore them properly on 2365 * resume. 2366 */ 2367 static int 2368 re_suspend(dev) 2369 device_t dev; 2370 { 2371 struct rl_softc *sc; 2372 2373 sc = device_get_softc(dev); 2374 2375 re_stop(sc); 2376 sc->suspended = 1; 2377 2378 return (0); 2379 } 2380 2381 /* 2382 * Device resume routine. Restore some PCI settings in case the BIOS 2383 * doesn't, re-enable busmastering, and restart the interface if 2384 * appropriate. 2385 */ 2386 static int 2387 re_resume(dev) 2388 device_t dev; 2389 { 2390 struct rl_softc *sc; 2391 struct ifnet *ifp; 2392 2393 sc = device_get_softc(dev); 2394 ifp = &sc->arpcom.ac_if; 2395 2396 /* reinitialize interface if necessary */ 2397 if (ifp->if_flags & IFF_UP) 2398 re_init(sc); 2399 2400 sc->suspended = 0; 2401 2402 return (0); 2403 } 2404 2405 /* 2406 * Stop all chip I/O so that the kernel's probe routines don't 2407 * get confused by errant DMAs when rebooting. 2408 */ 2409 static void 2410 re_shutdown(dev) 2411 device_t dev; 2412 { 2413 struct rl_softc *sc; 2414 2415 sc = device_get_softc(dev); 2416 2417 re_stop(sc); 2418 2419 return; 2420 } 2421