1 /*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44 /* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111 #ifdef HAVE_KERNEL_OPTION_HEADERS 112 #include "opt_device_polling.h" 113 #endif 114 115 #include <sys/param.h> 116 #include <sys/endian.h> 117 #include <sys/systm.h> 118 #include <sys/sockio.h> 119 #include <sys/mbuf.h> 120 #include <sys/malloc.h> 121 #include <sys/module.h> 122 #include <sys/kernel.h> 123 #include <sys/socket.h> 124 #include <sys/lock.h> 125 #include <sys/mutex.h> 126 #include <sys/sysctl.h> 127 #include <sys/taskqueue.h> 128 129 #include <net/if.h> 130 #include <net/if_var.h> 131 #include <net/if_arp.h> 132 #include <net/ethernet.h> 133 #include <net/if_dl.h> 134 #include <net/if_media.h> 135 #include <net/if_types.h> 136 #include <net/if_vlan_var.h> 137 138 #include <net/bpf.h> 139 140 #include <machine/bus.h> 141 #include <machine/resource.h> 142 #include <sys/bus.h> 143 #include <sys/rman.h> 144 145 #include <dev/mii/mii.h> 146 #include <dev/mii/miivar.h> 147 148 #include <dev/pci/pcireg.h> 149 #include <dev/pci/pcivar.h> 150 151 #include <dev/rl/if_rlreg.h> 152 153 MODULE_DEPEND(re, pci, 1, 1, 1); 154 MODULE_DEPEND(re, ether, 1, 1, 1); 155 MODULE_DEPEND(re, miibus, 1, 1, 1); 156 157 /* "device miibus" required. See GENERIC if you get errors here. */ 158 #include "miibus_if.h" 159 160 /* Tunables. */ 161 static int intr_filter = 0; 162 TUNABLE_INT("hw.re.intr_filter", &intr_filter); 163 static int msi_disable = 0; 164 TUNABLE_INT("hw.re.msi_disable", &msi_disable); 165 static int msix_disable = 0; 166 TUNABLE_INT("hw.re.msix_disable", &msix_disable); 167 static int prefer_iomap = 0; 168 TUNABLE_INT("hw.re.prefer_iomap", &prefer_iomap); 169 170 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 171 172 /* 173 * Various supported device vendors/types and their names. 174 */ 175 static const struct rl_type re_devs[] = { 176 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0, 177 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 178 { DLINK_VENDORID, DLINK_DEVICEID_530T_REVC, 0, 179 "D-Link DGE-530(T) Gigabit Ethernet Adapter" }, 180 { RT_VENDORID, RT_DEVICEID_8139, 0, 181 "RealTek 8139C+ 10/100BaseTX" }, 182 { RT_VENDORID, RT_DEVICEID_8101E, 0, 183 "RealTek 810xE PCIe 10/100baseTX" }, 184 { RT_VENDORID, RT_DEVICEID_8168, 0, 185 "RealTek 8168/8111 B/C/CP/D/DP/E/F/G PCIe Gigabit Ethernet" }, 186 { NCUBE_VENDORID, RT_DEVICEID_8168, 0, 187 "TP-Link TG-3468 v2 (RTL8168) Gigabit Ethernet" }, 188 { RT_VENDORID, RT_DEVICEID_8169, 0, 189 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" }, 190 { RT_VENDORID, RT_DEVICEID_8169SC, 0, 191 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 192 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0, 193 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 194 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0, 195 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 196 { USR_VENDORID, USR_DEVICEID_997902, 0, 197 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 198 }; 199 200 static const struct rl_hwrev re_hwrevs[] = { 201 { RL_HWREV_8139, RL_8139, "", RL_MTU }, 202 { RL_HWREV_8139A, RL_8139, "A", RL_MTU }, 203 { RL_HWREV_8139AG, RL_8139, "A-G", RL_MTU }, 204 { RL_HWREV_8139B, RL_8139, "B", RL_MTU }, 205 { RL_HWREV_8130, RL_8139, "8130", RL_MTU }, 206 { RL_HWREV_8139C, RL_8139, "C", RL_MTU }, 207 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C", RL_MTU }, 208 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+", RL_MTU }, 209 { RL_HWREV_8168B_SPIN1, RL_8169, "8168", RL_JUMBO_MTU }, 210 { RL_HWREV_8169, RL_8169, "8169", RL_JUMBO_MTU }, 211 { RL_HWREV_8169S, RL_8169, "8169S", RL_JUMBO_MTU }, 212 { RL_HWREV_8110S, RL_8169, "8110S", RL_JUMBO_MTU }, 213 { RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB", RL_JUMBO_MTU }, 214 { RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU }, 215 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL", RL_JUMBO_MTU }, 216 { RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU }, 217 { RL_HWREV_8100, RL_8139, "8100", RL_MTU }, 218 { RL_HWREV_8101, RL_8139, "8101", RL_MTU }, 219 { RL_HWREV_8100E, RL_8169, "8100E", RL_MTU }, 220 { RL_HWREV_8101E, RL_8169, "8101E", RL_MTU }, 221 { RL_HWREV_8102E, RL_8169, "8102E", RL_MTU }, 222 { RL_HWREV_8102EL, RL_8169, "8102EL", RL_MTU }, 223 { RL_HWREV_8102EL_SPIN1, RL_8169, "8102EL", RL_MTU }, 224 { RL_HWREV_8103E, RL_8169, "8103E", RL_MTU }, 225 { RL_HWREV_8401E, RL_8169, "8401E", RL_MTU }, 226 { RL_HWREV_8402, RL_8169, "8402", RL_MTU }, 227 { RL_HWREV_8105E, RL_8169, "8105E", RL_MTU }, 228 { RL_HWREV_8105E_SPIN1, RL_8169, "8105E", RL_MTU }, 229 { RL_HWREV_8106E, RL_8169, "8106E", RL_MTU }, 230 { RL_HWREV_8168B_SPIN2, RL_8169, "8168", RL_JUMBO_MTU }, 231 { RL_HWREV_8168B_SPIN3, RL_8169, "8168", RL_JUMBO_MTU }, 232 { RL_HWREV_8168C, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K }, 233 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K }, 234 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP", RL_JUMBO_MTU_6K }, 235 { RL_HWREV_8168D, RL_8169, "8168D/8111D", RL_JUMBO_MTU_9K }, 236 { RL_HWREV_8168DP, RL_8169, "8168DP/8111DP", RL_JUMBO_MTU_9K }, 237 { RL_HWREV_8168E, RL_8169, "8168E/8111E", RL_JUMBO_MTU_9K}, 238 { RL_HWREV_8168E_VL, RL_8169, "8168E/8111E-VL", RL_JUMBO_MTU_6K}, 239 { RL_HWREV_8168EP, RL_8169, "8168EP/8111EP", RL_JUMBO_MTU_9K}, 240 { RL_HWREV_8168F, RL_8169, "8168F/8111F", RL_JUMBO_MTU_9K}, 241 { RL_HWREV_8168G, RL_8169, "8168G/8111G", RL_JUMBO_MTU_9K}, 242 { RL_HWREV_8168GU, RL_8169, "8168GU/8111GU", RL_JUMBO_MTU_9K}, 243 { RL_HWREV_8168H, RL_8169, "8168H/8111H", RL_JUMBO_MTU_9K}, 244 { RL_HWREV_8411, RL_8169, "8411", RL_JUMBO_MTU_9K}, 245 { RL_HWREV_8411B, RL_8169, "8411B", RL_JUMBO_MTU_9K}, 246 { 0, 0, NULL, 0 } 247 }; 248 249 static int re_probe (device_t); 250 static int re_attach (device_t); 251 static int re_detach (device_t); 252 253 static int re_encap (struct rl_softc *, struct mbuf **); 254 255 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 256 static int re_allocmem (device_t, struct rl_softc *); 257 static __inline void re_discard_rxbuf 258 (struct rl_softc *, int); 259 static int re_newbuf (struct rl_softc *, int); 260 static int re_jumbo_newbuf (struct rl_softc *, int); 261 static int re_rx_list_init (struct rl_softc *); 262 static int re_jrx_list_init (struct rl_softc *); 263 static int re_tx_list_init (struct rl_softc *); 264 #ifdef RE_FIXUP_RX 265 static __inline void re_fixup_rx 266 (struct mbuf *); 267 #endif 268 static int re_rxeof (struct rl_softc *, int *); 269 static void re_txeof (struct rl_softc *); 270 #ifdef DEVICE_POLLING 271 static int re_poll (struct ifnet *, enum poll_cmd, int); 272 static int re_poll_locked (struct ifnet *, enum poll_cmd, int); 273 #endif 274 static int re_intr (void *); 275 static void re_intr_msi (void *); 276 static void re_tick (void *); 277 static void re_int_task (void *, int); 278 static void re_start (struct ifnet *); 279 static void re_start_locked (struct ifnet *); 280 static int re_ioctl (struct ifnet *, u_long, caddr_t); 281 static void re_init (void *); 282 static void re_init_locked (struct rl_softc *); 283 static void re_stop (struct rl_softc *); 284 static void re_watchdog (struct rl_softc *); 285 static int re_suspend (device_t); 286 static int re_resume (device_t); 287 static int re_shutdown (device_t); 288 static int re_ifmedia_upd (struct ifnet *); 289 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 290 291 static void re_eeprom_putbyte (struct rl_softc *, int); 292 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 293 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 294 static int re_gmii_readreg (device_t, int, int); 295 static int re_gmii_writereg (device_t, int, int, int); 296 297 static int re_miibus_readreg (device_t, int, int); 298 static int re_miibus_writereg (device_t, int, int, int); 299 static void re_miibus_statchg (device_t); 300 301 static void re_set_jumbo (struct rl_softc *, int); 302 static void re_set_rxmode (struct rl_softc *); 303 static void re_reset (struct rl_softc *); 304 static void re_setwol (struct rl_softc *); 305 static void re_clrwol (struct rl_softc *); 306 static void re_set_linkspeed (struct rl_softc *); 307 308 #ifdef DEV_NETMAP /* see ixgbe.c for details */ 309 #include <dev/netmap/if_re_netmap.h> 310 MODULE_DEPEND(re, netmap, 1, 1, 1); 311 #endif /* !DEV_NETMAP */ 312 313 #ifdef RE_DIAG 314 static int re_diag (struct rl_softc *); 315 #endif 316 317 static void re_add_sysctls (struct rl_softc *); 318 static int re_sysctl_stats (SYSCTL_HANDLER_ARGS); 319 static int sysctl_int_range (SYSCTL_HANDLER_ARGS, int, int); 320 static int sysctl_hw_re_int_mod (SYSCTL_HANDLER_ARGS); 321 322 static device_method_t re_methods[] = { 323 /* Device interface */ 324 DEVMETHOD(device_probe, re_probe), 325 DEVMETHOD(device_attach, re_attach), 326 DEVMETHOD(device_detach, re_detach), 327 DEVMETHOD(device_suspend, re_suspend), 328 DEVMETHOD(device_resume, re_resume), 329 DEVMETHOD(device_shutdown, re_shutdown), 330 331 /* MII interface */ 332 DEVMETHOD(miibus_readreg, re_miibus_readreg), 333 DEVMETHOD(miibus_writereg, re_miibus_writereg), 334 DEVMETHOD(miibus_statchg, re_miibus_statchg), 335 336 DEVMETHOD_END 337 }; 338 339 static driver_t re_driver = { 340 "re", 341 re_methods, 342 sizeof(struct rl_softc) 343 }; 344 345 static devclass_t re_devclass; 346 347 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 348 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 349 350 #define EE_SET(x) \ 351 CSR_WRITE_1(sc, RL_EECMD, \ 352 CSR_READ_1(sc, RL_EECMD) | x) 353 354 #define EE_CLR(x) \ 355 CSR_WRITE_1(sc, RL_EECMD, \ 356 CSR_READ_1(sc, RL_EECMD) & ~x) 357 358 /* 359 * Send a read command and address to the EEPROM, check for ACK. 360 */ 361 static void 362 re_eeprom_putbyte(struct rl_softc *sc, int addr) 363 { 364 int d, i; 365 366 d = addr | (RL_9346_READ << sc->rl_eewidth); 367 368 /* 369 * Feed in each bit and strobe the clock. 370 */ 371 372 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 373 if (d & i) { 374 EE_SET(RL_EE_DATAIN); 375 } else { 376 EE_CLR(RL_EE_DATAIN); 377 } 378 DELAY(100); 379 EE_SET(RL_EE_CLK); 380 DELAY(150); 381 EE_CLR(RL_EE_CLK); 382 DELAY(100); 383 } 384 } 385 386 /* 387 * Read a word of data stored in the EEPROM at address 'addr.' 388 */ 389 static void 390 re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest) 391 { 392 int i; 393 u_int16_t word = 0; 394 395 /* 396 * Send address of word we want to read. 397 */ 398 re_eeprom_putbyte(sc, addr); 399 400 /* 401 * Start reading bits from EEPROM. 402 */ 403 for (i = 0x8000; i; i >>= 1) { 404 EE_SET(RL_EE_CLK); 405 DELAY(100); 406 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 407 word |= i; 408 EE_CLR(RL_EE_CLK); 409 DELAY(100); 410 } 411 412 *dest = word; 413 } 414 415 /* 416 * Read a sequence of words from the EEPROM. 417 */ 418 static void 419 re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt) 420 { 421 int i; 422 u_int16_t word = 0, *ptr; 423 424 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 425 426 DELAY(100); 427 428 for (i = 0; i < cnt; i++) { 429 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 430 re_eeprom_getword(sc, off + i, &word); 431 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 432 ptr = (u_int16_t *)(dest + (i * 2)); 433 *ptr = word; 434 } 435 436 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 437 } 438 439 static int 440 re_gmii_readreg(device_t dev, int phy, int reg) 441 { 442 struct rl_softc *sc; 443 u_int32_t rval; 444 int i; 445 446 sc = device_get_softc(dev); 447 448 /* Let the rgephy driver read the GMEDIASTAT register */ 449 450 if (reg == RL_GMEDIASTAT) { 451 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 452 return (rval); 453 } 454 455 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 456 457 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 458 rval = CSR_READ_4(sc, RL_PHYAR); 459 if (rval & RL_PHYAR_BUSY) 460 break; 461 DELAY(25); 462 } 463 464 if (i == RL_PHY_TIMEOUT) { 465 device_printf(sc->rl_dev, "PHY read failed\n"); 466 return (0); 467 } 468 469 /* 470 * Controller requires a 20us delay to process next MDIO request. 471 */ 472 DELAY(20); 473 474 return (rval & RL_PHYAR_PHYDATA); 475 } 476 477 static int 478 re_gmii_writereg(device_t dev, int phy, int reg, int data) 479 { 480 struct rl_softc *sc; 481 u_int32_t rval; 482 int i; 483 484 sc = device_get_softc(dev); 485 486 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 487 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 488 489 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 490 rval = CSR_READ_4(sc, RL_PHYAR); 491 if (!(rval & RL_PHYAR_BUSY)) 492 break; 493 DELAY(25); 494 } 495 496 if (i == RL_PHY_TIMEOUT) { 497 device_printf(sc->rl_dev, "PHY write failed\n"); 498 return (0); 499 } 500 501 /* 502 * Controller requires a 20us delay to process next MDIO request. 503 */ 504 DELAY(20); 505 506 return (0); 507 } 508 509 static int 510 re_miibus_readreg(device_t dev, int phy, int reg) 511 { 512 struct rl_softc *sc; 513 u_int16_t rval = 0; 514 u_int16_t re8139_reg = 0; 515 516 sc = device_get_softc(dev); 517 518 if (sc->rl_type == RL_8169) { 519 rval = re_gmii_readreg(dev, phy, reg); 520 return (rval); 521 } 522 523 switch (reg) { 524 case MII_BMCR: 525 re8139_reg = RL_BMCR; 526 break; 527 case MII_BMSR: 528 re8139_reg = RL_BMSR; 529 break; 530 case MII_ANAR: 531 re8139_reg = RL_ANAR; 532 break; 533 case MII_ANER: 534 re8139_reg = RL_ANER; 535 break; 536 case MII_ANLPAR: 537 re8139_reg = RL_LPAR; 538 break; 539 case MII_PHYIDR1: 540 case MII_PHYIDR2: 541 return (0); 542 /* 543 * Allow the rlphy driver to read the media status 544 * register. If we have a link partner which does not 545 * support NWAY, this is the register which will tell 546 * us the results of parallel detection. 547 */ 548 case RL_MEDIASTAT: 549 rval = CSR_READ_1(sc, RL_MEDIASTAT); 550 return (rval); 551 default: 552 device_printf(sc->rl_dev, "bad phy register\n"); 553 return (0); 554 } 555 rval = CSR_READ_2(sc, re8139_reg); 556 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 557 /* 8139C+ has different bit layout. */ 558 rval &= ~(BMCR_LOOP | BMCR_ISO); 559 } 560 return (rval); 561 } 562 563 static int 564 re_miibus_writereg(device_t dev, int phy, int reg, int data) 565 { 566 struct rl_softc *sc; 567 u_int16_t re8139_reg = 0; 568 int rval = 0; 569 570 sc = device_get_softc(dev); 571 572 if (sc->rl_type == RL_8169) { 573 rval = re_gmii_writereg(dev, phy, reg, data); 574 return (rval); 575 } 576 577 switch (reg) { 578 case MII_BMCR: 579 re8139_reg = RL_BMCR; 580 if (sc->rl_type == RL_8139CPLUS) { 581 /* 8139C+ has different bit layout. */ 582 data &= ~(BMCR_LOOP | BMCR_ISO); 583 } 584 break; 585 case MII_BMSR: 586 re8139_reg = RL_BMSR; 587 break; 588 case MII_ANAR: 589 re8139_reg = RL_ANAR; 590 break; 591 case MII_ANER: 592 re8139_reg = RL_ANER; 593 break; 594 case MII_ANLPAR: 595 re8139_reg = RL_LPAR; 596 break; 597 case MII_PHYIDR1: 598 case MII_PHYIDR2: 599 return (0); 600 break; 601 default: 602 device_printf(sc->rl_dev, "bad phy register\n"); 603 return (0); 604 } 605 CSR_WRITE_2(sc, re8139_reg, data); 606 return (0); 607 } 608 609 static void 610 re_miibus_statchg(device_t dev) 611 { 612 struct rl_softc *sc; 613 struct ifnet *ifp; 614 struct mii_data *mii; 615 616 sc = device_get_softc(dev); 617 mii = device_get_softc(sc->rl_miibus); 618 ifp = sc->rl_ifp; 619 if (mii == NULL || ifp == NULL || 620 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 621 return; 622 623 sc->rl_flags &= ~RL_FLAG_LINK; 624 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 625 (IFM_ACTIVE | IFM_AVALID)) { 626 switch (IFM_SUBTYPE(mii->mii_media_active)) { 627 case IFM_10_T: 628 case IFM_100_TX: 629 sc->rl_flags |= RL_FLAG_LINK; 630 break; 631 case IFM_1000_T: 632 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0) 633 break; 634 sc->rl_flags |= RL_FLAG_LINK; 635 break; 636 default: 637 break; 638 } 639 } 640 /* 641 * RealTek controllers do not provide any interface to the RX/TX 642 * MACs for resolved speed, duplex and flow-control parameters. 643 */ 644 } 645 646 /* 647 * Set the RX configuration and 64-bit multicast hash filter. 648 */ 649 static void 650 re_set_rxmode(struct rl_softc *sc) 651 { 652 struct ifnet *ifp; 653 struct ifmultiaddr *ifma; 654 uint32_t hashes[2] = { 0, 0 }; 655 uint32_t h, rxfilt; 656 657 RL_LOCK_ASSERT(sc); 658 659 ifp = sc->rl_ifp; 660 661 rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD; 662 if ((sc->rl_flags & RL_FLAG_EARLYOFF) != 0) 663 rxfilt |= RL_RXCFG_EARLYOFF; 664 else if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0) 665 rxfilt |= RL_RXCFG_EARLYOFFV2; 666 667 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 668 if (ifp->if_flags & IFF_PROMISC) 669 rxfilt |= RL_RXCFG_RX_ALLPHYS; 670 /* 671 * Unlike other hardwares, we have to explicitly set 672 * RL_RXCFG_RX_MULTI to receive multicast frames in 673 * promiscuous mode. 674 */ 675 rxfilt |= RL_RXCFG_RX_MULTI; 676 hashes[0] = hashes[1] = 0xffffffff; 677 goto done; 678 } 679 680 if_maddr_rlock(ifp); 681 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 682 if (ifma->ifma_addr->sa_family != AF_LINK) 683 continue; 684 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 685 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 686 if (h < 32) 687 hashes[0] |= (1 << h); 688 else 689 hashes[1] |= (1 << (h - 32)); 690 } 691 if_maddr_runlock(ifp); 692 693 if (hashes[0] != 0 || hashes[1] != 0) { 694 /* 695 * For some unfathomable reason, RealTek decided to 696 * reverse the order of the multicast hash registers 697 * in the PCI Express parts. This means we have to 698 * write the hash pattern in reverse order for those 699 * devices. 700 */ 701 if ((sc->rl_flags & RL_FLAG_PCIE) != 0) { 702 h = bswap32(hashes[0]); 703 hashes[0] = bswap32(hashes[1]); 704 hashes[1] = h; 705 } 706 rxfilt |= RL_RXCFG_RX_MULTI; 707 } 708 709 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168F) { 710 /* Disable multicast filtering due to silicon bug. */ 711 hashes[0] = 0xffffffff; 712 hashes[1] = 0xffffffff; 713 } 714 715 done: 716 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 717 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 718 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 719 } 720 721 static void 722 re_reset(struct rl_softc *sc) 723 { 724 int i; 725 726 RL_LOCK_ASSERT(sc); 727 728 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 729 730 for (i = 0; i < RL_TIMEOUT; i++) { 731 DELAY(10); 732 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 733 break; 734 } 735 if (i == RL_TIMEOUT) 736 device_printf(sc->rl_dev, "reset never completed!\n"); 737 738 if ((sc->rl_flags & RL_FLAG_MACRESET) != 0) 739 CSR_WRITE_1(sc, 0x82, 1); 740 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169S) 741 re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0); 742 } 743 744 #ifdef RE_DIAG 745 746 /* 747 * The following routine is designed to test for a defect on some 748 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 749 * lines connected to the bus, however for a 32-bit only card, they 750 * should be pulled high. The result of this defect is that the 751 * NIC will not work right if you plug it into a 64-bit slot: DMA 752 * operations will be done with 64-bit transfers, which will fail 753 * because the 64-bit data lines aren't connected. 754 * 755 * There's no way to work around this (short of talking a soldering 756 * iron to the board), however we can detect it. The method we use 757 * here is to put the NIC into digital loopback mode, set the receiver 758 * to promiscuous mode, and then try to send a frame. We then compare 759 * the frame data we sent to what was received. If the data matches, 760 * then the NIC is working correctly, otherwise we know the user has 761 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 762 * slot. In the latter case, there's no way the NIC can work correctly, 763 * so we print out a message on the console and abort the device attach. 764 */ 765 766 static int 767 re_diag(struct rl_softc *sc) 768 { 769 struct ifnet *ifp = sc->rl_ifp; 770 struct mbuf *m0; 771 struct ether_header *eh; 772 struct rl_desc *cur_rx; 773 u_int16_t status; 774 u_int32_t rxstat; 775 int total_len, i, error = 0, phyaddr; 776 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 777 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 778 779 /* Allocate a single mbuf */ 780 MGETHDR(m0, M_NOWAIT, MT_DATA); 781 if (m0 == NULL) 782 return (ENOBUFS); 783 784 RL_LOCK(sc); 785 786 /* 787 * Initialize the NIC in test mode. This sets the chip up 788 * so that it can send and receive frames, but performs the 789 * following special functions: 790 * - Puts receiver in promiscuous mode 791 * - Enables digital loopback mode 792 * - Leaves interrupts turned off 793 */ 794 795 ifp->if_flags |= IFF_PROMISC; 796 sc->rl_testmode = 1; 797 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 798 re_init_locked(sc); 799 sc->rl_flags |= RL_FLAG_LINK; 800 if (sc->rl_type == RL_8169) 801 phyaddr = 1; 802 else 803 phyaddr = 0; 804 805 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 806 for (i = 0; i < RL_TIMEOUT; i++) { 807 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 808 if (!(status & BMCR_RESET)) 809 break; 810 } 811 812 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 813 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 814 815 DELAY(100000); 816 817 /* Put some data in the mbuf */ 818 819 eh = mtod(m0, struct ether_header *); 820 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 821 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 822 eh->ether_type = htons(ETHERTYPE_IP); 823 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 824 825 /* 826 * Queue the packet, start transmission. 827 * Note: IF_HANDOFF() ultimately calls re_start() for us. 828 */ 829 830 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 831 RL_UNLOCK(sc); 832 /* XXX: re_diag must not be called when in ALTQ mode */ 833 IF_HANDOFF(&ifp->if_snd, m0, ifp); 834 RL_LOCK(sc); 835 m0 = NULL; 836 837 /* Wait for it to propagate through the chip */ 838 839 DELAY(100000); 840 for (i = 0; i < RL_TIMEOUT; i++) { 841 status = CSR_READ_2(sc, RL_ISR); 842 CSR_WRITE_2(sc, RL_ISR, status); 843 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 844 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 845 break; 846 DELAY(10); 847 } 848 849 if (i == RL_TIMEOUT) { 850 device_printf(sc->rl_dev, 851 "diagnostic failed, failed to receive packet in" 852 " loopback mode\n"); 853 error = EIO; 854 goto done; 855 } 856 857 /* 858 * The packet should have been dumped into the first 859 * entry in the RX DMA ring. Grab it from there. 860 */ 861 862 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 863 sc->rl_ldata.rl_rx_list_map, 864 BUS_DMASYNC_POSTREAD); 865 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 866 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 867 BUS_DMASYNC_POSTREAD); 868 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 869 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 870 871 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 872 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 873 eh = mtod(m0, struct ether_header *); 874 875 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 876 total_len = RL_RXBYTES(cur_rx); 877 rxstat = le32toh(cur_rx->rl_cmdstat); 878 879 if (total_len != ETHER_MIN_LEN) { 880 device_printf(sc->rl_dev, 881 "diagnostic failed, received short packet\n"); 882 error = EIO; 883 goto done; 884 } 885 886 /* Test that the received packet data matches what we sent. */ 887 888 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 889 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 890 ntohs(eh->ether_type) != ETHERTYPE_IP) { 891 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 892 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 893 dst, ":", src, ":", ETHERTYPE_IP); 894 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 895 eh->ether_dhost, ":", eh->ether_shost, ":", 896 ntohs(eh->ether_type)); 897 device_printf(sc->rl_dev, "You may have a defective 32-bit " 898 "NIC plugged into a 64-bit PCI slot.\n"); 899 device_printf(sc->rl_dev, "Please re-install the NIC in a " 900 "32-bit slot for proper operation.\n"); 901 device_printf(sc->rl_dev, "Read the re(4) man page for more " 902 "details.\n"); 903 error = EIO; 904 } 905 906 done: 907 /* Turn interface off, release resources */ 908 909 sc->rl_testmode = 0; 910 sc->rl_flags &= ~RL_FLAG_LINK; 911 ifp->if_flags &= ~IFF_PROMISC; 912 re_stop(sc); 913 if (m0 != NULL) 914 m_freem(m0); 915 916 RL_UNLOCK(sc); 917 918 return (error); 919 } 920 921 #endif 922 923 /* 924 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 925 * IDs against our list and return a device name if we find a match. 926 */ 927 static int 928 re_probe(device_t dev) 929 { 930 const struct rl_type *t; 931 uint16_t devid, vendor; 932 uint16_t revid, sdevid; 933 int i; 934 935 vendor = pci_get_vendor(dev); 936 devid = pci_get_device(dev); 937 revid = pci_get_revid(dev); 938 sdevid = pci_get_subdevice(dev); 939 940 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 941 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 942 /* 943 * Only attach to rev. 3 of the Linksys EG1032 adapter. 944 * Rev. 2 is supported by sk(4). 945 */ 946 return (ENXIO); 947 } 948 } 949 950 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 951 if (revid != 0x20) { 952 /* 8139, let rl(4) take care of this device. */ 953 return (ENXIO); 954 } 955 } 956 957 t = re_devs; 958 for (i = 0; i < nitems(re_devs); i++, t++) { 959 if (vendor == t->rl_vid && devid == t->rl_did) { 960 device_set_desc(dev, t->rl_name); 961 return (BUS_PROBE_DEFAULT); 962 } 963 } 964 965 return (ENXIO); 966 } 967 968 /* 969 * Map a single buffer address. 970 */ 971 972 static void 973 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 974 { 975 bus_addr_t *addr; 976 977 if (error) 978 return; 979 980 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 981 addr = arg; 982 *addr = segs->ds_addr; 983 } 984 985 static int 986 re_allocmem(device_t dev, struct rl_softc *sc) 987 { 988 bus_addr_t lowaddr; 989 bus_size_t rx_list_size, tx_list_size; 990 int error; 991 int i; 992 993 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 994 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 995 996 /* 997 * Allocate the parent bus DMA tag appropriate for PCI. 998 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD 999 * register should be set. However some RealTek chips are known 1000 * to be buggy on DAC handling, therefore disable DAC by limiting 1001 * DMA address space to 32bit. PCIe variants of RealTek chips 1002 * may not have the limitation. 1003 */ 1004 lowaddr = BUS_SPACE_MAXADDR; 1005 if ((sc->rl_flags & RL_FLAG_PCIE) == 0) 1006 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1007 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 1008 lowaddr, BUS_SPACE_MAXADDR, NULL, NULL, 1009 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 1010 NULL, NULL, &sc->rl_parent_tag); 1011 if (error) { 1012 device_printf(dev, "could not allocate parent DMA tag\n"); 1013 return (error); 1014 } 1015 1016 /* 1017 * Allocate map for TX mbufs. 1018 */ 1019 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 1020 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1021 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 1022 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 1023 if (error) { 1024 device_printf(dev, "could not allocate TX DMA tag\n"); 1025 return (error); 1026 } 1027 1028 /* 1029 * Allocate map for RX mbufs. 1030 */ 1031 1032 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 1033 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 1034 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1035 MJUM9BYTES, 1, MJUM9BYTES, 0, NULL, NULL, 1036 &sc->rl_ldata.rl_jrx_mtag); 1037 if (error) { 1038 device_printf(dev, 1039 "could not allocate jumbo RX DMA tag\n"); 1040 return (error); 1041 } 1042 } 1043 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 1044 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1045 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 1046 if (error) { 1047 device_printf(dev, "could not allocate RX DMA tag\n"); 1048 return (error); 1049 } 1050 1051 /* 1052 * Allocate map for TX descriptor list. 1053 */ 1054 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1055 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1056 NULL, tx_list_size, 1, tx_list_size, 0, 1057 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1058 if (error) { 1059 device_printf(dev, "could not allocate TX DMA ring tag\n"); 1060 return (error); 1061 } 1062 1063 /* Allocate DMA'able memory for the TX ring */ 1064 1065 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1066 (void **)&sc->rl_ldata.rl_tx_list, 1067 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1068 &sc->rl_ldata.rl_tx_list_map); 1069 if (error) { 1070 device_printf(dev, "could not allocate TX DMA ring\n"); 1071 return (error); 1072 } 1073 1074 /* Load the map for the TX ring. */ 1075 1076 sc->rl_ldata.rl_tx_list_addr = 0; 1077 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1078 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1079 tx_list_size, re_dma_map_addr, 1080 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1081 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 1082 device_printf(dev, "could not load TX DMA ring\n"); 1083 return (ENOMEM); 1084 } 1085 1086 /* Create DMA maps for TX buffers */ 1087 1088 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1089 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1090 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1091 if (error) { 1092 device_printf(dev, "could not create DMA map for TX\n"); 1093 return (error); 1094 } 1095 } 1096 1097 /* 1098 * Allocate map for RX descriptor list. 1099 */ 1100 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1101 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1102 NULL, rx_list_size, 1, rx_list_size, 0, 1103 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1104 if (error) { 1105 device_printf(dev, "could not create RX DMA ring tag\n"); 1106 return (error); 1107 } 1108 1109 /* Allocate DMA'able memory for the RX ring */ 1110 1111 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1112 (void **)&sc->rl_ldata.rl_rx_list, 1113 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1114 &sc->rl_ldata.rl_rx_list_map); 1115 if (error) { 1116 device_printf(dev, "could not allocate RX DMA ring\n"); 1117 return (error); 1118 } 1119 1120 /* Load the map for the RX ring. */ 1121 1122 sc->rl_ldata.rl_rx_list_addr = 0; 1123 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1124 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1125 rx_list_size, re_dma_map_addr, 1126 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1127 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1128 device_printf(dev, "could not load RX DMA ring\n"); 1129 return (ENOMEM); 1130 } 1131 1132 /* Create DMA maps for RX buffers */ 1133 1134 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 1135 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0, 1136 &sc->rl_ldata.rl_jrx_sparemap); 1137 if (error) { 1138 device_printf(dev, 1139 "could not create spare DMA map for jumbo RX\n"); 1140 return (error); 1141 } 1142 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1143 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0, 1144 &sc->rl_ldata.rl_jrx_desc[i].rx_dmamap); 1145 if (error) { 1146 device_printf(dev, 1147 "could not create DMA map for jumbo RX\n"); 1148 return (error); 1149 } 1150 } 1151 } 1152 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1153 &sc->rl_ldata.rl_rx_sparemap); 1154 if (error) { 1155 device_printf(dev, "could not create spare DMA map for RX\n"); 1156 return (error); 1157 } 1158 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1159 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1160 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1161 if (error) { 1162 device_printf(dev, "could not create DMA map for RX\n"); 1163 return (error); 1164 } 1165 } 1166 1167 /* Create DMA map for statistics. */ 1168 error = bus_dma_tag_create(sc->rl_parent_tag, RL_DUMP_ALIGN, 0, 1169 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1170 sizeof(struct rl_stats), 1, sizeof(struct rl_stats), 0, NULL, NULL, 1171 &sc->rl_ldata.rl_stag); 1172 if (error) { 1173 device_printf(dev, "could not create statistics DMA tag\n"); 1174 return (error); 1175 } 1176 /* Allocate DMA'able memory for statistics. */ 1177 error = bus_dmamem_alloc(sc->rl_ldata.rl_stag, 1178 (void **)&sc->rl_ldata.rl_stats, 1179 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1180 &sc->rl_ldata.rl_smap); 1181 if (error) { 1182 device_printf(dev, 1183 "could not allocate statistics DMA memory\n"); 1184 return (error); 1185 } 1186 /* Load the map for statistics. */ 1187 sc->rl_ldata.rl_stats_addr = 0; 1188 error = bus_dmamap_load(sc->rl_ldata.rl_stag, sc->rl_ldata.rl_smap, 1189 sc->rl_ldata.rl_stats, sizeof(struct rl_stats), re_dma_map_addr, 1190 &sc->rl_ldata.rl_stats_addr, BUS_DMA_NOWAIT); 1191 if (error != 0 || sc->rl_ldata.rl_stats_addr == 0) { 1192 device_printf(dev, "could not load statistics DMA memory\n"); 1193 return (ENOMEM); 1194 } 1195 1196 return (0); 1197 } 1198 1199 /* 1200 * Attach the interface. Allocate softc structures, do ifmedia 1201 * setup and ethernet/BPF attach. 1202 */ 1203 static int 1204 re_attach(device_t dev) 1205 { 1206 u_char eaddr[ETHER_ADDR_LEN]; 1207 u_int16_t as[ETHER_ADDR_LEN / 2]; 1208 struct rl_softc *sc; 1209 struct ifnet *ifp; 1210 const struct rl_hwrev *hw_rev; 1211 int capmask, error = 0, hwrev, i, msic, msixc, 1212 phy, reg, rid; 1213 u_int32_t cap, ctl; 1214 u_int16_t devid, re_did = 0; 1215 uint8_t cfg; 1216 1217 sc = device_get_softc(dev); 1218 sc->rl_dev = dev; 1219 1220 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1221 MTX_DEF); 1222 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1223 1224 /* 1225 * Map control/status registers. 1226 */ 1227 pci_enable_busmaster(dev); 1228 1229 devid = pci_get_device(dev); 1230 /* 1231 * Prefer memory space register mapping over IO space. 1232 * Because RTL8169SC does not seem to work when memory mapping 1233 * is used always activate io mapping. 1234 */ 1235 if (devid == RT_DEVICEID_8169SC) 1236 prefer_iomap = 1; 1237 if (prefer_iomap == 0) { 1238 sc->rl_res_id = PCIR_BAR(1); 1239 sc->rl_res_type = SYS_RES_MEMORY; 1240 /* RTL8168/8101E seems to use different BARs. */ 1241 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E) 1242 sc->rl_res_id = PCIR_BAR(2); 1243 } else { 1244 sc->rl_res_id = PCIR_BAR(0); 1245 sc->rl_res_type = SYS_RES_IOPORT; 1246 } 1247 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1248 &sc->rl_res_id, RF_ACTIVE); 1249 if (sc->rl_res == NULL && prefer_iomap == 0) { 1250 sc->rl_res_id = PCIR_BAR(0); 1251 sc->rl_res_type = SYS_RES_IOPORT; 1252 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1253 &sc->rl_res_id, RF_ACTIVE); 1254 } 1255 if (sc->rl_res == NULL) { 1256 device_printf(dev, "couldn't map ports/memory\n"); 1257 error = ENXIO; 1258 goto fail; 1259 } 1260 1261 sc->rl_btag = rman_get_bustag(sc->rl_res); 1262 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1263 1264 msic = pci_msi_count(dev); 1265 msixc = pci_msix_count(dev); 1266 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 1267 sc->rl_flags |= RL_FLAG_PCIE; 1268 sc->rl_expcap = reg; 1269 } 1270 if (bootverbose) { 1271 device_printf(dev, "MSI count : %d\n", msic); 1272 device_printf(dev, "MSI-X count : %d\n", msixc); 1273 } 1274 if (msix_disable > 0) 1275 msixc = 0; 1276 if (msi_disable > 0) 1277 msic = 0; 1278 /* Prefer MSI-X to MSI. */ 1279 if (msixc > 0) { 1280 msixc = RL_MSI_MESSAGES; 1281 rid = PCIR_BAR(4); 1282 sc->rl_res_pba = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1283 &rid, RF_ACTIVE); 1284 if (sc->rl_res_pba == NULL) { 1285 device_printf(sc->rl_dev, 1286 "could not allocate MSI-X PBA resource\n"); 1287 } 1288 if (sc->rl_res_pba != NULL && 1289 pci_alloc_msix(dev, &msixc) == 0) { 1290 if (msixc == RL_MSI_MESSAGES) { 1291 device_printf(dev, "Using %d MSI-X message\n", 1292 msixc); 1293 sc->rl_flags |= RL_FLAG_MSIX; 1294 } else 1295 pci_release_msi(dev); 1296 } 1297 if ((sc->rl_flags & RL_FLAG_MSIX) == 0) { 1298 if (sc->rl_res_pba != NULL) 1299 bus_release_resource(dev, SYS_RES_MEMORY, rid, 1300 sc->rl_res_pba); 1301 sc->rl_res_pba = NULL; 1302 msixc = 0; 1303 } 1304 } 1305 /* Prefer MSI to INTx. */ 1306 if (msixc == 0 && msic > 0) { 1307 msic = RL_MSI_MESSAGES; 1308 if (pci_alloc_msi(dev, &msic) == 0) { 1309 if (msic == RL_MSI_MESSAGES) { 1310 device_printf(dev, "Using %d MSI message\n", 1311 msic); 1312 sc->rl_flags |= RL_FLAG_MSI; 1313 /* Explicitly set MSI enable bit. */ 1314 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1315 cfg = CSR_READ_1(sc, RL_CFG2); 1316 cfg |= RL_CFG2_MSI; 1317 CSR_WRITE_1(sc, RL_CFG2, cfg); 1318 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1319 } else 1320 pci_release_msi(dev); 1321 } 1322 if ((sc->rl_flags & RL_FLAG_MSI) == 0) 1323 msic = 0; 1324 } 1325 1326 /* Allocate interrupt */ 1327 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) { 1328 rid = 0; 1329 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1330 RF_SHAREABLE | RF_ACTIVE); 1331 if (sc->rl_irq[0] == NULL) { 1332 device_printf(dev, "couldn't allocate IRQ resources\n"); 1333 error = ENXIO; 1334 goto fail; 1335 } 1336 } else { 1337 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1338 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1339 SYS_RES_IRQ, &rid, RF_ACTIVE); 1340 if (sc->rl_irq[i] == NULL) { 1341 device_printf(dev, 1342 "couldn't allocate IRQ resources for " 1343 "message %d\n", rid); 1344 error = ENXIO; 1345 goto fail; 1346 } 1347 } 1348 } 1349 1350 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1351 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1352 cfg = CSR_READ_1(sc, RL_CFG2); 1353 if ((cfg & RL_CFG2_MSI) != 0) { 1354 device_printf(dev, "turning off MSI enable bit.\n"); 1355 cfg &= ~RL_CFG2_MSI; 1356 CSR_WRITE_1(sc, RL_CFG2, cfg); 1357 } 1358 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1359 } 1360 1361 /* Disable ASPM L0S/L1. */ 1362 if (sc->rl_expcap != 0) { 1363 cap = pci_read_config(dev, sc->rl_expcap + 1364 PCIER_LINK_CAP, 2); 1365 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { 1366 ctl = pci_read_config(dev, sc->rl_expcap + 1367 PCIER_LINK_CTL, 2); 1368 if ((ctl & PCIEM_LINK_CTL_ASPMC) != 0) { 1369 ctl &= ~PCIEM_LINK_CTL_ASPMC; 1370 pci_write_config(dev, sc->rl_expcap + 1371 PCIER_LINK_CTL, ctl, 2); 1372 device_printf(dev, "ASPM disabled\n"); 1373 } 1374 } else 1375 device_printf(dev, "no ASPM capability\n"); 1376 } 1377 1378 hw_rev = re_hwrevs; 1379 hwrev = CSR_READ_4(sc, RL_TXCFG); 1380 switch (hwrev & 0x70000000) { 1381 case 0x00000000: 1382 case 0x10000000: 1383 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000); 1384 hwrev &= (RL_TXCFG_HWREV | 0x80000000); 1385 break; 1386 default: 1387 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000); 1388 sc->rl_macrev = hwrev & 0x00700000; 1389 hwrev &= RL_TXCFG_HWREV; 1390 break; 1391 } 1392 device_printf(dev, "MAC rev. 0x%08x\n", sc->rl_macrev); 1393 while (hw_rev->rl_desc != NULL) { 1394 if (hw_rev->rl_rev == hwrev) { 1395 sc->rl_type = hw_rev->rl_type; 1396 sc->rl_hwrev = hw_rev; 1397 break; 1398 } 1399 hw_rev++; 1400 } 1401 if (hw_rev->rl_desc == NULL) { 1402 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev); 1403 error = ENXIO; 1404 goto fail; 1405 } 1406 1407 switch (hw_rev->rl_rev) { 1408 case RL_HWREV_8139CPLUS: 1409 sc->rl_flags |= RL_FLAG_FASTETHER | RL_FLAG_AUTOPAD; 1410 break; 1411 case RL_HWREV_8100E: 1412 case RL_HWREV_8101E: 1413 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_FASTETHER; 1414 break; 1415 case RL_HWREV_8102E: 1416 case RL_HWREV_8102EL: 1417 case RL_HWREV_8102EL_SPIN1: 1418 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1419 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | 1420 RL_FLAG_AUTOPAD; 1421 break; 1422 case RL_HWREV_8103E: 1423 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1424 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | 1425 RL_FLAG_AUTOPAD | RL_FLAG_MACSLEEP; 1426 break; 1427 case RL_HWREV_8401E: 1428 case RL_HWREV_8105E: 1429 case RL_HWREV_8105E_SPIN1: 1430 case RL_HWREV_8106E: 1431 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1432 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1433 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD; 1434 break; 1435 case RL_HWREV_8402: 1436 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1437 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1438 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | 1439 RL_FLAG_CMDSTOP_WAIT_TXQ; 1440 break; 1441 case RL_HWREV_8168B_SPIN1: 1442 case RL_HWREV_8168B_SPIN2: 1443 sc->rl_flags |= RL_FLAG_WOLRXENB; 1444 /* FALLTHROUGH */ 1445 case RL_HWREV_8168B_SPIN3: 1446 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT; 1447 break; 1448 case RL_HWREV_8168C_SPIN2: 1449 sc->rl_flags |= RL_FLAG_MACSLEEP; 1450 /* FALLTHROUGH */ 1451 case RL_HWREV_8168C: 1452 if (sc->rl_macrev == 0x00200000) 1453 sc->rl_flags |= RL_FLAG_MACSLEEP; 1454 /* FALLTHROUGH */ 1455 case RL_HWREV_8168CP: 1456 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1457 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1458 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK; 1459 break; 1460 case RL_HWREV_8168D: 1461 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1462 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1463 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1464 RL_FLAG_WOL_MANLINK; 1465 break; 1466 case RL_HWREV_8168DP: 1467 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1468 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_AUTOPAD | 1469 RL_FLAG_JUMBOV2 | RL_FLAG_WAIT_TXPOLL | RL_FLAG_WOL_MANLINK; 1470 break; 1471 case RL_HWREV_8168E: 1472 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1473 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1474 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1475 RL_FLAG_WOL_MANLINK; 1476 break; 1477 case RL_HWREV_8168E_VL: 1478 case RL_HWREV_8168F: 1479 sc->rl_flags |= RL_FLAG_EARLYOFF; 1480 /* FALLTHROUGH */ 1481 case RL_HWREV_8411: 1482 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1483 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1484 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1485 RL_FLAG_CMDSTOP_WAIT_TXQ | RL_FLAG_WOL_MANLINK; 1486 break; 1487 case RL_HWREV_8168EP: 1488 case RL_HWREV_8168G: 1489 case RL_HWREV_8411B: 1490 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1491 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1492 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1493 RL_FLAG_CMDSTOP_WAIT_TXQ | RL_FLAG_WOL_MANLINK | 1494 RL_FLAG_8168G_PLUS; 1495 break; 1496 case RL_HWREV_8168GU: 1497 case RL_HWREV_8168H: 1498 if (pci_get_device(dev) == RT_DEVICEID_8101E) { 1499 /* RTL8106E(US), RTL8107E */ 1500 sc->rl_flags |= RL_FLAG_FASTETHER; 1501 } else 1502 sc->rl_flags |= RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK; 1503 1504 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1505 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1506 RL_FLAG_AUTOPAD | RL_FLAG_CMDSTOP_WAIT_TXQ | 1507 RL_FLAG_8168G_PLUS; 1508 break; 1509 case RL_HWREV_8169_8110SB: 1510 case RL_HWREV_8169_8110SBL: 1511 case RL_HWREV_8169_8110SC: 1512 case RL_HWREV_8169_8110SCE: 1513 sc->rl_flags |= RL_FLAG_PHYWAKE; 1514 /* FALLTHROUGH */ 1515 case RL_HWREV_8169: 1516 case RL_HWREV_8169S: 1517 case RL_HWREV_8110S: 1518 sc->rl_flags |= RL_FLAG_MACRESET; 1519 break; 1520 default: 1521 break; 1522 } 1523 1524 if (sc->rl_hwrev->rl_rev == RL_HWREV_8139CPLUS) { 1525 sc->rl_cfg0 = RL_8139_CFG0; 1526 sc->rl_cfg1 = RL_8139_CFG1; 1527 sc->rl_cfg2 = 0; 1528 sc->rl_cfg3 = RL_8139_CFG3; 1529 sc->rl_cfg4 = RL_8139_CFG4; 1530 sc->rl_cfg5 = RL_8139_CFG5; 1531 } else { 1532 sc->rl_cfg0 = RL_CFG0; 1533 sc->rl_cfg1 = RL_CFG1; 1534 sc->rl_cfg2 = RL_CFG2; 1535 sc->rl_cfg3 = RL_CFG3; 1536 sc->rl_cfg4 = RL_CFG4; 1537 sc->rl_cfg5 = RL_CFG5; 1538 } 1539 1540 /* Reset the adapter. */ 1541 RL_LOCK(sc); 1542 re_reset(sc); 1543 RL_UNLOCK(sc); 1544 1545 /* Enable PME. */ 1546 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1547 cfg = CSR_READ_1(sc, sc->rl_cfg1); 1548 cfg |= RL_CFG1_PME; 1549 CSR_WRITE_1(sc, sc->rl_cfg1, cfg); 1550 cfg = CSR_READ_1(sc, sc->rl_cfg5); 1551 cfg &= RL_CFG5_PME_STS; 1552 CSR_WRITE_1(sc, sc->rl_cfg5, cfg); 1553 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1554 1555 if ((sc->rl_flags & RL_FLAG_PAR) != 0) { 1556 /* 1557 * XXX Should have a better way to extract station 1558 * address from EEPROM. 1559 */ 1560 for (i = 0; i < ETHER_ADDR_LEN; i++) 1561 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1562 } else { 1563 sc->rl_eewidth = RL_9356_ADDR_LEN; 1564 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1565 if (re_did != 0x8129) 1566 sc->rl_eewidth = RL_9346_ADDR_LEN; 1567 1568 /* 1569 * Get station address from the EEPROM. 1570 */ 1571 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1572 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1573 as[i] = le16toh(as[i]); 1574 bcopy(as, eaddr, ETHER_ADDR_LEN); 1575 } 1576 1577 if (sc->rl_type == RL_8169) { 1578 /* Set RX length mask and number of descriptors. */ 1579 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1580 sc->rl_txstart = RL_GTXSTART; 1581 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1582 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1583 } else { 1584 /* Set RX length mask and number of descriptors. */ 1585 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1586 sc->rl_txstart = RL_TXSTART; 1587 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1588 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1589 } 1590 1591 error = re_allocmem(dev, sc); 1592 if (error) 1593 goto fail; 1594 re_add_sysctls(sc); 1595 1596 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1597 if (ifp == NULL) { 1598 device_printf(dev, "can not if_alloc()\n"); 1599 error = ENOSPC; 1600 goto fail; 1601 } 1602 1603 /* Take controller out of deep sleep mode. */ 1604 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 1605 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 1606 CSR_WRITE_1(sc, RL_GPIO, 1607 CSR_READ_1(sc, RL_GPIO) | 0x01); 1608 else 1609 CSR_WRITE_1(sc, RL_GPIO, 1610 CSR_READ_1(sc, RL_GPIO) & ~0x01); 1611 } 1612 1613 /* Take PHY out of power down mode. */ 1614 if ((sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) { 1615 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80); 1616 if (hw_rev->rl_rev == RL_HWREV_8401E) 1617 CSR_WRITE_1(sc, 0xD1, CSR_READ_1(sc, 0xD1) & ~0x08); 1618 } 1619 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) { 1620 re_gmii_writereg(dev, 1, 0x1f, 0); 1621 re_gmii_writereg(dev, 1, 0x0e, 0); 1622 } 1623 1624 ifp->if_softc = sc; 1625 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1626 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1627 ifp->if_ioctl = re_ioctl; 1628 ifp->if_start = re_start; 1629 /* 1630 * RTL8168/8111C generates wrong IP checksummed frame if the 1631 * packet has IP options so disable TX checksum offloading. 1632 */ 1633 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168C || 1634 sc->rl_hwrev->rl_rev == RL_HWREV_8168C_SPIN2 || 1635 sc->rl_hwrev->rl_rev == RL_HWREV_8168CP) { 1636 ifp->if_hwassist = 0; 1637 ifp->if_capabilities = IFCAP_RXCSUM | IFCAP_TSO4; 1638 } else { 1639 ifp->if_hwassist = CSUM_IP | CSUM_TCP | CSUM_UDP; 1640 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 1641 } 1642 ifp->if_hwassist |= CSUM_TSO; 1643 ifp->if_capenable = ifp->if_capabilities; 1644 ifp->if_init = re_init; 1645 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1646 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1647 IFQ_SET_READY(&ifp->if_snd); 1648 1649 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1650 1651 #define RE_PHYAD_INTERNAL 0 1652 1653 /* Do MII setup. */ 1654 phy = RE_PHYAD_INTERNAL; 1655 if (sc->rl_type == RL_8169) 1656 phy = 1; 1657 capmask = BMSR_DEFCAPMASK; 1658 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0) 1659 capmask &= ~BMSR_EXTSTAT; 1660 error = mii_attach(dev, &sc->rl_miibus, ifp, re_ifmedia_upd, 1661 re_ifmedia_sts, capmask, phy, MII_OFFSET_ANY, MIIF_DOPAUSE); 1662 if (error != 0) { 1663 device_printf(dev, "attaching PHYs failed\n"); 1664 goto fail; 1665 } 1666 1667 /* 1668 * Call MI attach routine. 1669 */ 1670 ether_ifattach(ifp, eaddr); 1671 1672 /* VLAN capability setup */ 1673 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1674 if (ifp->if_capabilities & IFCAP_HWCSUM) 1675 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1676 /* Enable WOL if PM is supported. */ 1677 if (pci_find_cap(sc->rl_dev, PCIY_PMG, ®) == 0) 1678 ifp->if_capabilities |= IFCAP_WOL; 1679 ifp->if_capenable = ifp->if_capabilities; 1680 ifp->if_capenable &= ~(IFCAP_WOL_UCAST | IFCAP_WOL_MCAST); 1681 /* 1682 * Don't enable TSO by default. It is known to generate 1683 * corrupted TCP segments(bad TCP options) under certain 1684 * circumstances. 1685 */ 1686 ifp->if_hwassist &= ~CSUM_TSO; 1687 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO); 1688 #ifdef DEVICE_POLLING 1689 ifp->if_capabilities |= IFCAP_POLLING; 1690 #endif 1691 /* 1692 * Tell the upper layer(s) we support long frames. 1693 * Must appear after the call to ether_ifattach() because 1694 * ether_ifattach() sets ifi_hdrlen to the default value. 1695 */ 1696 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 1697 1698 #ifdef DEV_NETMAP 1699 re_netmap_attach(sc); 1700 #endif /* DEV_NETMAP */ 1701 1702 #ifdef RE_DIAG 1703 /* 1704 * Perform hardware diagnostic on the original RTL8169. 1705 * Some 32-bit cards were incorrectly wired and would 1706 * malfunction if plugged into a 64-bit slot. 1707 */ 1708 if (hwrev == RL_HWREV_8169) { 1709 error = re_diag(sc); 1710 if (error) { 1711 device_printf(dev, 1712 "attach aborted due to hardware diag failure\n"); 1713 ether_ifdetach(ifp); 1714 goto fail; 1715 } 1716 } 1717 #endif 1718 1719 #ifdef RE_TX_MODERATION 1720 intr_filter = 1; 1721 #endif 1722 /* Hook interrupt last to avoid having to lock softc */ 1723 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 && 1724 intr_filter == 0) { 1725 error = bus_setup_intr(dev, sc->rl_irq[0], 1726 INTR_TYPE_NET | INTR_MPSAFE, NULL, re_intr_msi, sc, 1727 &sc->rl_intrhand[0]); 1728 } else { 1729 error = bus_setup_intr(dev, sc->rl_irq[0], 1730 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1731 &sc->rl_intrhand[0]); 1732 } 1733 if (error) { 1734 device_printf(dev, "couldn't set up irq\n"); 1735 ether_ifdetach(ifp); 1736 } 1737 1738 fail: 1739 if (error) 1740 re_detach(dev); 1741 1742 return (error); 1743 } 1744 1745 /* 1746 * Shutdown hardware and free up resources. This can be called any 1747 * time after the mutex has been initialized. It is called in both 1748 * the error case in attach and the normal detach case so it needs 1749 * to be careful about only freeing resources that have actually been 1750 * allocated. 1751 */ 1752 static int 1753 re_detach(device_t dev) 1754 { 1755 struct rl_softc *sc; 1756 struct ifnet *ifp; 1757 int i, rid; 1758 1759 sc = device_get_softc(dev); 1760 ifp = sc->rl_ifp; 1761 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1762 1763 /* These should only be active if attach succeeded */ 1764 if (device_is_attached(dev)) { 1765 #ifdef DEVICE_POLLING 1766 if (ifp->if_capenable & IFCAP_POLLING) 1767 ether_poll_deregister(ifp); 1768 #endif 1769 RL_LOCK(sc); 1770 #if 0 1771 sc->suspended = 1; 1772 #endif 1773 re_stop(sc); 1774 RL_UNLOCK(sc); 1775 callout_drain(&sc->rl_stat_callout); 1776 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1777 /* 1778 * Force off the IFF_UP flag here, in case someone 1779 * still had a BPF descriptor attached to this 1780 * interface. If they do, ether_ifdetach() will cause 1781 * the BPF code to try and clear the promisc mode 1782 * flag, which will bubble down to re_ioctl(), 1783 * which will try to call re_init() again. This will 1784 * turn the NIC back on and restart the MII ticker, 1785 * which will panic the system when the kernel tries 1786 * to invoke the re_tick() function that isn't there 1787 * anymore. 1788 */ 1789 ifp->if_flags &= ~IFF_UP; 1790 ether_ifdetach(ifp); 1791 } 1792 if (sc->rl_miibus) 1793 device_delete_child(dev, sc->rl_miibus); 1794 bus_generic_detach(dev); 1795 1796 /* 1797 * The rest is resource deallocation, so we should already be 1798 * stopped here. 1799 */ 1800 1801 if (sc->rl_intrhand[0] != NULL) { 1802 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]); 1803 sc->rl_intrhand[0] = NULL; 1804 } 1805 if (ifp != NULL) { 1806 #ifdef DEV_NETMAP 1807 netmap_detach(ifp); 1808 #endif /* DEV_NETMAP */ 1809 if_free(ifp); 1810 } 1811 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) 1812 rid = 0; 1813 else 1814 rid = 1; 1815 if (sc->rl_irq[0] != NULL) { 1816 bus_release_resource(dev, SYS_RES_IRQ, rid, sc->rl_irq[0]); 1817 sc->rl_irq[0] = NULL; 1818 } 1819 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0) 1820 pci_release_msi(dev); 1821 if (sc->rl_res_pba) { 1822 rid = PCIR_BAR(4); 1823 bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->rl_res_pba); 1824 } 1825 if (sc->rl_res) 1826 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, 1827 sc->rl_res); 1828 1829 /* Unload and free the RX DMA ring memory and map */ 1830 1831 if (sc->rl_ldata.rl_rx_list_tag) { 1832 if (sc->rl_ldata.rl_rx_list_addr) 1833 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1834 sc->rl_ldata.rl_rx_list_map); 1835 if (sc->rl_ldata.rl_rx_list) 1836 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1837 sc->rl_ldata.rl_rx_list, 1838 sc->rl_ldata.rl_rx_list_map); 1839 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1840 } 1841 1842 /* Unload and free the TX DMA ring memory and map */ 1843 1844 if (sc->rl_ldata.rl_tx_list_tag) { 1845 if (sc->rl_ldata.rl_tx_list_addr) 1846 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1847 sc->rl_ldata.rl_tx_list_map); 1848 if (sc->rl_ldata.rl_tx_list) 1849 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1850 sc->rl_ldata.rl_tx_list, 1851 sc->rl_ldata.rl_tx_list_map); 1852 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1853 } 1854 1855 /* Destroy all the RX and TX buffer maps */ 1856 1857 if (sc->rl_ldata.rl_tx_mtag) { 1858 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1859 if (sc->rl_ldata.rl_tx_desc[i].tx_dmamap) 1860 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1861 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1862 } 1863 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1864 } 1865 if (sc->rl_ldata.rl_rx_mtag) { 1866 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1867 if (sc->rl_ldata.rl_rx_desc[i].rx_dmamap) 1868 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1869 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1870 } 1871 if (sc->rl_ldata.rl_rx_sparemap) 1872 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1873 sc->rl_ldata.rl_rx_sparemap); 1874 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1875 } 1876 if (sc->rl_ldata.rl_jrx_mtag) { 1877 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1878 if (sc->rl_ldata.rl_jrx_desc[i].rx_dmamap) 1879 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag, 1880 sc->rl_ldata.rl_jrx_desc[i].rx_dmamap); 1881 } 1882 if (sc->rl_ldata.rl_jrx_sparemap) 1883 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag, 1884 sc->rl_ldata.rl_jrx_sparemap); 1885 bus_dma_tag_destroy(sc->rl_ldata.rl_jrx_mtag); 1886 } 1887 /* Unload and free the stats buffer and map */ 1888 1889 if (sc->rl_ldata.rl_stag) { 1890 if (sc->rl_ldata.rl_stats_addr) 1891 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1892 sc->rl_ldata.rl_smap); 1893 if (sc->rl_ldata.rl_stats) 1894 bus_dmamem_free(sc->rl_ldata.rl_stag, 1895 sc->rl_ldata.rl_stats, sc->rl_ldata.rl_smap); 1896 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1897 } 1898 1899 if (sc->rl_parent_tag) 1900 bus_dma_tag_destroy(sc->rl_parent_tag); 1901 1902 mtx_destroy(&sc->rl_mtx); 1903 1904 return (0); 1905 } 1906 1907 static __inline void 1908 re_discard_rxbuf(struct rl_softc *sc, int idx) 1909 { 1910 struct rl_desc *desc; 1911 struct rl_rxdesc *rxd; 1912 uint32_t cmdstat; 1913 1914 if (sc->rl_ifp->if_mtu > RL_MTU && 1915 (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) 1916 rxd = &sc->rl_ldata.rl_jrx_desc[idx]; 1917 else 1918 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1919 desc = &sc->rl_ldata.rl_rx_list[idx]; 1920 desc->rl_vlanctl = 0; 1921 cmdstat = rxd->rx_size; 1922 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1923 cmdstat |= RL_RDESC_CMD_EOR; 1924 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1925 } 1926 1927 static int 1928 re_newbuf(struct rl_softc *sc, int idx) 1929 { 1930 struct mbuf *m; 1931 struct rl_rxdesc *rxd; 1932 bus_dma_segment_t segs[1]; 1933 bus_dmamap_t map; 1934 struct rl_desc *desc; 1935 uint32_t cmdstat; 1936 int error, nsegs; 1937 1938 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1939 if (m == NULL) 1940 return (ENOBUFS); 1941 1942 m->m_len = m->m_pkthdr.len = MCLBYTES; 1943 #ifdef RE_FIXUP_RX 1944 /* 1945 * This is part of an evil trick to deal with non-x86 platforms. 1946 * The RealTek chip requires RX buffers to be aligned on 64-bit 1947 * boundaries, but that will hose non-x86 machines. To get around 1948 * this, we leave some empty space at the start of each buffer 1949 * and for non-x86 hosts, we copy the buffer back six bytes 1950 * to achieve word alignment. This is slightly more efficient 1951 * than allocating a new buffer, copying the contents, and 1952 * discarding the old buffer. 1953 */ 1954 m_adj(m, RE_ETHER_ALIGN); 1955 #endif 1956 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1957 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1958 if (error != 0) { 1959 m_freem(m); 1960 return (ENOBUFS); 1961 } 1962 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1963 1964 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1965 if (rxd->rx_m != NULL) { 1966 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1967 BUS_DMASYNC_POSTREAD); 1968 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1969 } 1970 1971 rxd->rx_m = m; 1972 map = rxd->rx_dmamap; 1973 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1974 rxd->rx_size = segs[0].ds_len; 1975 sc->rl_ldata.rl_rx_sparemap = map; 1976 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1977 BUS_DMASYNC_PREREAD); 1978 1979 desc = &sc->rl_ldata.rl_rx_list[idx]; 1980 desc->rl_vlanctl = 0; 1981 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1982 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1983 cmdstat = segs[0].ds_len; 1984 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1985 cmdstat |= RL_RDESC_CMD_EOR; 1986 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1987 1988 return (0); 1989 } 1990 1991 static int 1992 re_jumbo_newbuf(struct rl_softc *sc, int idx) 1993 { 1994 struct mbuf *m; 1995 struct rl_rxdesc *rxd; 1996 bus_dma_segment_t segs[1]; 1997 bus_dmamap_t map; 1998 struct rl_desc *desc; 1999 uint32_t cmdstat; 2000 int error, nsegs; 2001 2002 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 2003 if (m == NULL) 2004 return (ENOBUFS); 2005 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 2006 #ifdef RE_FIXUP_RX 2007 m_adj(m, RE_ETHER_ALIGN); 2008 #endif 2009 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_jrx_mtag, 2010 sc->rl_ldata.rl_jrx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 2011 if (error != 0) { 2012 m_freem(m); 2013 return (ENOBUFS); 2014 } 2015 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 2016 2017 rxd = &sc->rl_ldata.rl_jrx_desc[idx]; 2018 if (rxd->rx_m != NULL) { 2019 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap, 2020 BUS_DMASYNC_POSTREAD); 2021 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap); 2022 } 2023 2024 rxd->rx_m = m; 2025 map = rxd->rx_dmamap; 2026 rxd->rx_dmamap = sc->rl_ldata.rl_jrx_sparemap; 2027 rxd->rx_size = segs[0].ds_len; 2028 sc->rl_ldata.rl_jrx_sparemap = map; 2029 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap, 2030 BUS_DMASYNC_PREREAD); 2031 2032 desc = &sc->rl_ldata.rl_rx_list[idx]; 2033 desc->rl_vlanctl = 0; 2034 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 2035 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 2036 cmdstat = segs[0].ds_len; 2037 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 2038 cmdstat |= RL_RDESC_CMD_EOR; 2039 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 2040 2041 return (0); 2042 } 2043 2044 #ifdef RE_FIXUP_RX 2045 static __inline void 2046 re_fixup_rx(struct mbuf *m) 2047 { 2048 int i; 2049 uint16_t *src, *dst; 2050 2051 src = mtod(m, uint16_t *); 2052 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 2053 2054 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 2055 *dst++ = *src++; 2056 2057 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 2058 } 2059 #endif 2060 2061 static int 2062 re_tx_list_init(struct rl_softc *sc) 2063 { 2064 struct rl_desc *desc; 2065 int i; 2066 2067 RL_LOCK_ASSERT(sc); 2068 2069 bzero(sc->rl_ldata.rl_tx_list, 2070 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 2071 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 2072 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 2073 #ifdef DEV_NETMAP 2074 re_netmap_tx_init(sc); 2075 #endif /* DEV_NETMAP */ 2076 /* Set EOR. */ 2077 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 2078 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 2079 2080 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2081 sc->rl_ldata.rl_tx_list_map, 2082 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2083 2084 sc->rl_ldata.rl_tx_prodidx = 0; 2085 sc->rl_ldata.rl_tx_considx = 0; 2086 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 2087 2088 return (0); 2089 } 2090 2091 static int 2092 re_rx_list_init(struct rl_softc *sc) 2093 { 2094 int error, i; 2095 2096 bzero(sc->rl_ldata.rl_rx_list, 2097 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 2098 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2099 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 2100 if ((error = re_newbuf(sc, i)) != 0) 2101 return (error); 2102 } 2103 #ifdef DEV_NETMAP 2104 re_netmap_rx_init(sc); 2105 #endif /* DEV_NETMAP */ 2106 2107 /* Flush the RX descriptors */ 2108 2109 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2110 sc->rl_ldata.rl_rx_list_map, 2111 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2112 2113 sc->rl_ldata.rl_rx_prodidx = 0; 2114 sc->rl_head = sc->rl_tail = NULL; 2115 sc->rl_int_rx_act = 0; 2116 2117 return (0); 2118 } 2119 2120 static int 2121 re_jrx_list_init(struct rl_softc *sc) 2122 { 2123 int error, i; 2124 2125 bzero(sc->rl_ldata.rl_rx_list, 2126 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 2127 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2128 sc->rl_ldata.rl_jrx_desc[i].rx_m = NULL; 2129 if ((error = re_jumbo_newbuf(sc, i)) != 0) 2130 return (error); 2131 } 2132 2133 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2134 sc->rl_ldata.rl_rx_list_map, 2135 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2136 2137 sc->rl_ldata.rl_rx_prodidx = 0; 2138 sc->rl_head = sc->rl_tail = NULL; 2139 sc->rl_int_rx_act = 0; 2140 2141 return (0); 2142 } 2143 2144 /* 2145 * RX handler for C+ and 8169. For the gigE chips, we support 2146 * the reception of jumbo frames that have been fragmented 2147 * across multiple 2K mbuf cluster buffers. 2148 */ 2149 static int 2150 re_rxeof(struct rl_softc *sc, int *rx_npktsp) 2151 { 2152 struct mbuf *m; 2153 struct ifnet *ifp; 2154 int i, rxerr, total_len; 2155 struct rl_desc *cur_rx; 2156 u_int32_t rxstat, rxvlan; 2157 int jumbo, maxpkt = 16, rx_npkts = 0; 2158 2159 RL_LOCK_ASSERT(sc); 2160 2161 ifp = sc->rl_ifp; 2162 #ifdef DEV_NETMAP 2163 if (netmap_rx_irq(ifp, 0, &rx_npkts)) 2164 return 0; 2165 #endif /* DEV_NETMAP */ 2166 if (ifp->if_mtu > RL_MTU && (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) 2167 jumbo = 1; 2168 else 2169 jumbo = 0; 2170 2171 /* Invalidate the descriptor memory */ 2172 2173 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2174 sc->rl_ldata.rl_rx_list_map, 2175 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2176 2177 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 2178 i = RL_RX_DESC_NXT(sc, i)) { 2179 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2180 break; 2181 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 2182 rxstat = le32toh(cur_rx->rl_cmdstat); 2183 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 2184 break; 2185 total_len = rxstat & sc->rl_rxlenmask; 2186 rxvlan = le32toh(cur_rx->rl_vlanctl); 2187 if (jumbo != 0) 2188 m = sc->rl_ldata.rl_jrx_desc[i].rx_m; 2189 else 2190 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 2191 2192 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 2193 (rxstat & (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) != 2194 (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) { 2195 /* 2196 * RTL8168C or later controllers do not 2197 * support multi-fragment packet. 2198 */ 2199 re_discard_rxbuf(sc, i); 2200 continue; 2201 } else if ((rxstat & RL_RDESC_STAT_EOF) == 0) { 2202 if (re_newbuf(sc, i) != 0) { 2203 /* 2204 * If this is part of a multi-fragment packet, 2205 * discard all the pieces. 2206 */ 2207 if (sc->rl_head != NULL) { 2208 m_freem(sc->rl_head); 2209 sc->rl_head = sc->rl_tail = NULL; 2210 } 2211 re_discard_rxbuf(sc, i); 2212 continue; 2213 } 2214 m->m_len = RE_RX_DESC_BUFLEN; 2215 if (sc->rl_head == NULL) 2216 sc->rl_head = sc->rl_tail = m; 2217 else { 2218 m->m_flags &= ~M_PKTHDR; 2219 sc->rl_tail->m_next = m; 2220 sc->rl_tail = m; 2221 } 2222 continue; 2223 } 2224 2225 /* 2226 * NOTE: for the 8139C+, the frame length field 2227 * is always 12 bits in size, but for the gigE chips, 2228 * it is 13 bits (since the max RX frame length is 16K). 2229 * Unfortunately, all 32 bits in the status word 2230 * were already used, so to make room for the extra 2231 * length bit, RealTek took out the 'frame alignment 2232 * error' bit and shifted the other status bits 2233 * over one slot. The OWN, EOR, FS and LS bits are 2234 * still in the same places. We have already extracted 2235 * the frame length and checked the OWN bit, so rather 2236 * than using an alternate bit mapping, we shift the 2237 * status bits one space to the right so we can evaluate 2238 * them using the 8169 status as though it was in the 2239 * same format as that of the 8139C+. 2240 */ 2241 if (sc->rl_type == RL_8169) 2242 rxstat >>= 1; 2243 2244 /* 2245 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 2246 * set, but if CRC is clear, it will still be a valid frame. 2247 */ 2248 if ((rxstat & RL_RDESC_STAT_RXERRSUM) != 0) { 2249 rxerr = 1; 2250 if ((sc->rl_flags & RL_FLAG_JUMBOV2) == 0 && 2251 total_len > 8191 && 2252 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT) 2253 rxerr = 0; 2254 if (rxerr != 0) { 2255 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2256 /* 2257 * If this is part of a multi-fragment packet, 2258 * discard all the pieces. 2259 */ 2260 if (sc->rl_head != NULL) { 2261 m_freem(sc->rl_head); 2262 sc->rl_head = sc->rl_tail = NULL; 2263 } 2264 re_discard_rxbuf(sc, i); 2265 continue; 2266 } 2267 } 2268 2269 /* 2270 * If allocating a replacement mbuf fails, 2271 * reload the current one. 2272 */ 2273 if (jumbo != 0) 2274 rxerr = re_jumbo_newbuf(sc, i); 2275 else 2276 rxerr = re_newbuf(sc, i); 2277 if (rxerr != 0) { 2278 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2279 if (sc->rl_head != NULL) { 2280 m_freem(sc->rl_head); 2281 sc->rl_head = sc->rl_tail = NULL; 2282 } 2283 re_discard_rxbuf(sc, i); 2284 continue; 2285 } 2286 2287 if (sc->rl_head != NULL) { 2288 if (jumbo != 0) 2289 m->m_len = total_len; 2290 else { 2291 m->m_len = total_len % RE_RX_DESC_BUFLEN; 2292 if (m->m_len == 0) 2293 m->m_len = RE_RX_DESC_BUFLEN; 2294 } 2295 /* 2296 * Special case: if there's 4 bytes or less 2297 * in this buffer, the mbuf can be discarded: 2298 * the last 4 bytes is the CRC, which we don't 2299 * care about anyway. 2300 */ 2301 if (m->m_len <= ETHER_CRC_LEN) { 2302 sc->rl_tail->m_len -= 2303 (ETHER_CRC_LEN - m->m_len); 2304 m_freem(m); 2305 } else { 2306 m->m_len -= ETHER_CRC_LEN; 2307 m->m_flags &= ~M_PKTHDR; 2308 sc->rl_tail->m_next = m; 2309 } 2310 m = sc->rl_head; 2311 sc->rl_head = sc->rl_tail = NULL; 2312 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 2313 } else 2314 m->m_pkthdr.len = m->m_len = 2315 (total_len - ETHER_CRC_LEN); 2316 2317 #ifdef RE_FIXUP_RX 2318 re_fixup_rx(m); 2319 #endif 2320 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 2321 m->m_pkthdr.rcvif = ifp; 2322 2323 /* Do RX checksumming if enabled */ 2324 2325 if (ifp->if_capenable & IFCAP_RXCSUM) { 2326 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2327 /* Check IP header checksum */ 2328 if (rxstat & RL_RDESC_STAT_PROTOID) 2329 m->m_pkthdr.csum_flags |= 2330 CSUM_IP_CHECKED; 2331 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 2332 m->m_pkthdr.csum_flags |= 2333 CSUM_IP_VALID; 2334 2335 /* Check TCP/UDP checksum */ 2336 if ((RL_TCPPKT(rxstat) && 2337 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 2338 (RL_UDPPKT(rxstat) && 2339 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 2340 m->m_pkthdr.csum_flags |= 2341 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2342 m->m_pkthdr.csum_data = 0xffff; 2343 } 2344 } else { 2345 /* 2346 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP 2347 */ 2348 if ((rxstat & RL_RDESC_STAT_PROTOID) && 2349 (rxvlan & RL_RDESC_IPV4)) 2350 m->m_pkthdr.csum_flags |= 2351 CSUM_IP_CHECKED; 2352 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) && 2353 (rxvlan & RL_RDESC_IPV4)) 2354 m->m_pkthdr.csum_flags |= 2355 CSUM_IP_VALID; 2356 if (((rxstat & RL_RDESC_STAT_TCP) && 2357 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 2358 ((rxstat & RL_RDESC_STAT_UDP) && 2359 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 2360 m->m_pkthdr.csum_flags |= 2361 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2362 m->m_pkthdr.csum_data = 0xffff; 2363 } 2364 } 2365 } 2366 maxpkt--; 2367 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 2368 m->m_pkthdr.ether_vtag = 2369 bswap16((rxvlan & RL_RDESC_VLANCTL_DATA)); 2370 m->m_flags |= M_VLANTAG; 2371 } 2372 RL_UNLOCK(sc); 2373 (*ifp->if_input)(ifp, m); 2374 RL_LOCK(sc); 2375 rx_npkts++; 2376 } 2377 2378 /* Flush the RX DMA ring */ 2379 2380 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2381 sc->rl_ldata.rl_rx_list_map, 2382 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2383 2384 sc->rl_ldata.rl_rx_prodidx = i; 2385 2386 if (rx_npktsp != NULL) 2387 *rx_npktsp = rx_npkts; 2388 if (maxpkt) 2389 return (EAGAIN); 2390 2391 return (0); 2392 } 2393 2394 static void 2395 re_txeof(struct rl_softc *sc) 2396 { 2397 struct ifnet *ifp; 2398 struct rl_txdesc *txd; 2399 u_int32_t txstat; 2400 int cons; 2401 2402 cons = sc->rl_ldata.rl_tx_considx; 2403 if (cons == sc->rl_ldata.rl_tx_prodidx) 2404 return; 2405 2406 ifp = sc->rl_ifp; 2407 #ifdef DEV_NETMAP 2408 if (netmap_tx_irq(ifp, 0)) 2409 return; 2410 #endif /* DEV_NETMAP */ 2411 /* Invalidate the TX descriptor list */ 2412 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2413 sc->rl_ldata.rl_tx_list_map, 2414 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2415 2416 for (; cons != sc->rl_ldata.rl_tx_prodidx; 2417 cons = RL_TX_DESC_NXT(sc, cons)) { 2418 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 2419 if (txstat & RL_TDESC_STAT_OWN) 2420 break; 2421 /* 2422 * We only stash mbufs in the last descriptor 2423 * in a fragment chain, which also happens to 2424 * be the only place where the TX status bits 2425 * are valid. 2426 */ 2427 if (txstat & RL_TDESC_CMD_EOF) { 2428 txd = &sc->rl_ldata.rl_tx_desc[cons]; 2429 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2430 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2431 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2432 txd->tx_dmamap); 2433 KASSERT(txd->tx_m != NULL, 2434 ("%s: freeing NULL mbufs!", __func__)); 2435 m_freem(txd->tx_m); 2436 txd->tx_m = NULL; 2437 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 2438 RL_TDESC_STAT_COLCNT)) 2439 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 2440 if (txstat & RL_TDESC_STAT_TXERRSUM) 2441 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2442 else 2443 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 2444 } 2445 sc->rl_ldata.rl_tx_free++; 2446 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2447 } 2448 sc->rl_ldata.rl_tx_considx = cons; 2449 2450 /* No changes made to the TX ring, so no flush needed */ 2451 2452 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 2453 #ifdef RE_TX_MODERATION 2454 /* 2455 * If not all descriptors have been reaped yet, reload 2456 * the timer so that we will eventually get another 2457 * interrupt that will cause us to re-enter this routine. 2458 * This is done in case the transmitter has gone idle. 2459 */ 2460 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2461 #endif 2462 } else 2463 sc->rl_watchdog_timer = 0; 2464 } 2465 2466 static void 2467 re_tick(void *xsc) 2468 { 2469 struct rl_softc *sc; 2470 struct mii_data *mii; 2471 2472 sc = xsc; 2473 2474 RL_LOCK_ASSERT(sc); 2475 2476 mii = device_get_softc(sc->rl_miibus); 2477 mii_tick(mii); 2478 if ((sc->rl_flags & RL_FLAG_LINK) == 0) 2479 re_miibus_statchg(sc->rl_dev); 2480 /* 2481 * Reclaim transmitted frames here. Technically it is not 2482 * necessary to do here but it ensures periodic reclamation 2483 * regardless of Tx completion interrupt which seems to be 2484 * lost on PCIe based controllers under certain situations. 2485 */ 2486 re_txeof(sc); 2487 re_watchdog(sc); 2488 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2489 } 2490 2491 #ifdef DEVICE_POLLING 2492 static int 2493 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2494 { 2495 struct rl_softc *sc = ifp->if_softc; 2496 int rx_npkts = 0; 2497 2498 RL_LOCK(sc); 2499 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2500 rx_npkts = re_poll_locked(ifp, cmd, count); 2501 RL_UNLOCK(sc); 2502 return (rx_npkts); 2503 } 2504 2505 static int 2506 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2507 { 2508 struct rl_softc *sc = ifp->if_softc; 2509 int rx_npkts; 2510 2511 RL_LOCK_ASSERT(sc); 2512 2513 sc->rxcycles = count; 2514 re_rxeof(sc, &rx_npkts); 2515 re_txeof(sc); 2516 2517 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2518 re_start_locked(ifp); 2519 2520 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2521 u_int16_t status; 2522 2523 status = CSR_READ_2(sc, RL_ISR); 2524 if (status == 0xffff) 2525 return (rx_npkts); 2526 if (status) 2527 CSR_WRITE_2(sc, RL_ISR, status); 2528 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2529 (sc->rl_flags & RL_FLAG_PCIE)) 2530 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2531 2532 /* 2533 * XXX check behaviour on receiver stalls. 2534 */ 2535 2536 if (status & RL_ISR_SYSTEM_ERR) { 2537 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2538 re_init_locked(sc); 2539 } 2540 } 2541 return (rx_npkts); 2542 } 2543 #endif /* DEVICE_POLLING */ 2544 2545 static int 2546 re_intr(void *arg) 2547 { 2548 struct rl_softc *sc; 2549 uint16_t status; 2550 2551 sc = arg; 2552 2553 status = CSR_READ_2(sc, RL_ISR); 2554 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2555 return (FILTER_STRAY); 2556 CSR_WRITE_2(sc, RL_IMR, 0); 2557 2558 taskqueue_enqueue(taskqueue_fast, &sc->rl_inttask); 2559 2560 return (FILTER_HANDLED); 2561 } 2562 2563 static void 2564 re_int_task(void *arg, int npending) 2565 { 2566 struct rl_softc *sc; 2567 struct ifnet *ifp; 2568 u_int16_t status; 2569 int rval = 0; 2570 2571 sc = arg; 2572 ifp = sc->rl_ifp; 2573 2574 RL_LOCK(sc); 2575 2576 status = CSR_READ_2(sc, RL_ISR); 2577 CSR_WRITE_2(sc, RL_ISR, status); 2578 2579 if (sc->suspended || 2580 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2581 RL_UNLOCK(sc); 2582 return; 2583 } 2584 2585 #ifdef DEVICE_POLLING 2586 if (ifp->if_capenable & IFCAP_POLLING) { 2587 RL_UNLOCK(sc); 2588 return; 2589 } 2590 #endif 2591 2592 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2593 rval = re_rxeof(sc, NULL); 2594 2595 /* 2596 * Some chips will ignore a second TX request issued 2597 * while an existing transmission is in progress. If 2598 * the transmitter goes idle but there are still 2599 * packets waiting to be sent, we need to restart the 2600 * channel here to flush them out. This only seems to 2601 * be required with the PCIe devices. 2602 */ 2603 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2604 (sc->rl_flags & RL_FLAG_PCIE)) 2605 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2606 if (status & ( 2607 #ifdef RE_TX_MODERATION 2608 RL_ISR_TIMEOUT_EXPIRED| 2609 #else 2610 RL_ISR_TX_OK| 2611 #endif 2612 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2613 re_txeof(sc); 2614 2615 if (status & RL_ISR_SYSTEM_ERR) { 2616 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2617 re_init_locked(sc); 2618 } 2619 2620 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2621 re_start_locked(ifp); 2622 2623 RL_UNLOCK(sc); 2624 2625 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2626 taskqueue_enqueue(taskqueue_fast, &sc->rl_inttask); 2627 return; 2628 } 2629 2630 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2631 } 2632 2633 static void 2634 re_intr_msi(void *xsc) 2635 { 2636 struct rl_softc *sc; 2637 struct ifnet *ifp; 2638 uint16_t intrs, status; 2639 2640 sc = xsc; 2641 RL_LOCK(sc); 2642 2643 ifp = sc->rl_ifp; 2644 #ifdef DEVICE_POLLING 2645 if (ifp->if_capenable & IFCAP_POLLING) { 2646 RL_UNLOCK(sc); 2647 return; 2648 } 2649 #endif 2650 /* Disable interrupts. */ 2651 CSR_WRITE_2(sc, RL_IMR, 0); 2652 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2653 RL_UNLOCK(sc); 2654 return; 2655 } 2656 2657 intrs = RL_INTRS_CPLUS; 2658 status = CSR_READ_2(sc, RL_ISR); 2659 CSR_WRITE_2(sc, RL_ISR, status); 2660 if (sc->rl_int_rx_act > 0) { 2661 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW | 2662 RL_ISR_RX_OVERRUN); 2663 status &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW | 2664 RL_ISR_RX_OVERRUN); 2665 } 2666 2667 if (status & (RL_ISR_TIMEOUT_EXPIRED | RL_ISR_RX_OK | RL_ISR_RX_ERR | 2668 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) { 2669 re_rxeof(sc, NULL); 2670 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2671 if (sc->rl_int_rx_mod != 0 && 2672 (status & (RL_ISR_RX_OK | RL_ISR_RX_ERR | 2673 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) != 0) { 2674 /* Rearm one-shot timer. */ 2675 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2676 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | 2677 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN); 2678 sc->rl_int_rx_act = 1; 2679 } else { 2680 intrs |= RL_ISR_RX_OK | RL_ISR_RX_ERR | 2681 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN; 2682 sc->rl_int_rx_act = 0; 2683 } 2684 } 2685 } 2686 2687 /* 2688 * Some chips will ignore a second TX request issued 2689 * while an existing transmission is in progress. If 2690 * the transmitter goes idle but there are still 2691 * packets waiting to be sent, we need to restart the 2692 * channel here to flush them out. This only seems to 2693 * be required with the PCIe devices. 2694 */ 2695 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2696 (sc->rl_flags & RL_FLAG_PCIE)) 2697 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2698 if (status & (RL_ISR_TX_OK | RL_ISR_TX_ERR | RL_ISR_TX_DESC_UNAVAIL)) 2699 re_txeof(sc); 2700 2701 if (status & RL_ISR_SYSTEM_ERR) { 2702 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2703 re_init_locked(sc); 2704 } 2705 2706 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2707 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2708 re_start_locked(ifp); 2709 CSR_WRITE_2(sc, RL_IMR, intrs); 2710 } 2711 RL_UNLOCK(sc); 2712 } 2713 2714 static int 2715 re_encap(struct rl_softc *sc, struct mbuf **m_head) 2716 { 2717 struct rl_txdesc *txd, *txd_last; 2718 bus_dma_segment_t segs[RL_NTXSEGS]; 2719 bus_dmamap_t map; 2720 struct mbuf *m_new; 2721 struct rl_desc *desc; 2722 int nsegs, prod; 2723 int i, error, ei, si; 2724 int padlen; 2725 uint32_t cmdstat, csum_flags, vlanctl; 2726 2727 RL_LOCK_ASSERT(sc); 2728 M_ASSERTPKTHDR((*m_head)); 2729 2730 /* 2731 * With some of the RealTek chips, using the checksum offload 2732 * support in conjunction with the autopadding feature results 2733 * in the transmission of corrupt frames. For example, if we 2734 * need to send a really small IP fragment that's less than 60 2735 * bytes in size, and IP header checksumming is enabled, the 2736 * resulting ethernet frame that appears on the wire will 2737 * have garbled payload. To work around this, if TX IP checksum 2738 * offload is enabled, we always manually pad short frames out 2739 * to the minimum ethernet frame size. 2740 */ 2741 if ((sc->rl_flags & RL_FLAG_AUTOPAD) == 0 && 2742 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN && 2743 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) { 2744 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2745 if (M_WRITABLE(*m_head) == 0) { 2746 /* Get a writable copy. */ 2747 m_new = m_dup(*m_head, M_NOWAIT); 2748 m_freem(*m_head); 2749 if (m_new == NULL) { 2750 *m_head = NULL; 2751 return (ENOBUFS); 2752 } 2753 *m_head = m_new; 2754 } 2755 if ((*m_head)->m_next != NULL || 2756 M_TRAILINGSPACE(*m_head) < padlen) { 2757 m_new = m_defrag(*m_head, M_NOWAIT); 2758 if (m_new == NULL) { 2759 m_freem(*m_head); 2760 *m_head = NULL; 2761 return (ENOBUFS); 2762 } 2763 } else 2764 m_new = *m_head; 2765 2766 /* 2767 * Manually pad short frames, and zero the pad space 2768 * to avoid leaking data. 2769 */ 2770 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2771 m_new->m_pkthdr.len += padlen; 2772 m_new->m_len = m_new->m_pkthdr.len; 2773 *m_head = m_new; 2774 } 2775 2776 prod = sc->rl_ldata.rl_tx_prodidx; 2777 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2778 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2779 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2780 if (error == EFBIG) { 2781 m_new = m_collapse(*m_head, M_NOWAIT, RL_NTXSEGS); 2782 if (m_new == NULL) { 2783 m_freem(*m_head); 2784 *m_head = NULL; 2785 return (ENOBUFS); 2786 } 2787 *m_head = m_new; 2788 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2789 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2790 if (error != 0) { 2791 m_freem(*m_head); 2792 *m_head = NULL; 2793 return (error); 2794 } 2795 } else if (error != 0) 2796 return (error); 2797 if (nsegs == 0) { 2798 m_freem(*m_head); 2799 *m_head = NULL; 2800 return (EIO); 2801 } 2802 2803 /* Check for number of available descriptors. */ 2804 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2805 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2806 return (ENOBUFS); 2807 } 2808 2809 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2810 BUS_DMASYNC_PREWRITE); 2811 2812 /* 2813 * Set up checksum offload. Note: checksum offload bits must 2814 * appear in all descriptors of a multi-descriptor transmit 2815 * attempt. This is according to testing done with an 8169 2816 * chip. This is a requirement. 2817 */ 2818 vlanctl = 0; 2819 csum_flags = 0; 2820 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2821 if ((sc->rl_flags & RL_FLAG_DESCV2) != 0) { 2822 csum_flags |= RL_TDESC_CMD_LGSEND; 2823 vlanctl |= ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2824 RL_TDESC_CMD_MSSVALV2_SHIFT); 2825 } else { 2826 csum_flags |= RL_TDESC_CMD_LGSEND | 2827 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2828 RL_TDESC_CMD_MSSVAL_SHIFT); 2829 } 2830 } else { 2831 /* 2832 * Unconditionally enable IP checksum if TCP or UDP 2833 * checksum is required. Otherwise, TCP/UDP checksum 2834 * doesn't make effects. 2835 */ 2836 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) { 2837 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2838 csum_flags |= RL_TDESC_CMD_IPCSUM; 2839 if (((*m_head)->m_pkthdr.csum_flags & 2840 CSUM_TCP) != 0) 2841 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2842 if (((*m_head)->m_pkthdr.csum_flags & 2843 CSUM_UDP) != 0) 2844 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2845 } else { 2846 vlanctl |= RL_TDESC_CMD_IPCSUMV2; 2847 if (((*m_head)->m_pkthdr.csum_flags & 2848 CSUM_TCP) != 0) 2849 vlanctl |= RL_TDESC_CMD_TCPCSUMV2; 2850 if (((*m_head)->m_pkthdr.csum_flags & 2851 CSUM_UDP) != 0) 2852 vlanctl |= RL_TDESC_CMD_UDPCSUMV2; 2853 } 2854 } 2855 } 2856 2857 /* 2858 * Set up hardware VLAN tagging. Note: vlan tag info must 2859 * appear in all descriptors of a multi-descriptor 2860 * transmission attempt. 2861 */ 2862 if ((*m_head)->m_flags & M_VLANTAG) 2863 vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) | 2864 RL_TDESC_VLANCTL_TAG; 2865 2866 si = prod; 2867 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2868 desc = &sc->rl_ldata.rl_tx_list[prod]; 2869 desc->rl_vlanctl = htole32(vlanctl); 2870 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2871 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2872 cmdstat = segs[i].ds_len; 2873 if (i != 0) 2874 cmdstat |= RL_TDESC_CMD_OWN; 2875 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2876 cmdstat |= RL_TDESC_CMD_EOR; 2877 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2878 sc->rl_ldata.rl_tx_free--; 2879 } 2880 /* Update producer index. */ 2881 sc->rl_ldata.rl_tx_prodidx = prod; 2882 2883 /* Set EOF on the last descriptor. */ 2884 ei = RL_TX_DESC_PRV(sc, prod); 2885 desc = &sc->rl_ldata.rl_tx_list[ei]; 2886 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2887 2888 desc = &sc->rl_ldata.rl_tx_list[si]; 2889 /* Set SOF and transfer ownership of packet to the chip. */ 2890 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2891 2892 /* 2893 * Insure that the map for this transmission 2894 * is placed at the array index of the last descriptor 2895 * in this chain. (Swap last and first dmamaps.) 2896 */ 2897 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2898 map = txd->tx_dmamap; 2899 txd->tx_dmamap = txd_last->tx_dmamap; 2900 txd_last->tx_dmamap = map; 2901 txd_last->tx_m = *m_head; 2902 2903 return (0); 2904 } 2905 2906 static void 2907 re_start(struct ifnet *ifp) 2908 { 2909 struct rl_softc *sc; 2910 2911 sc = ifp->if_softc; 2912 RL_LOCK(sc); 2913 re_start_locked(ifp); 2914 RL_UNLOCK(sc); 2915 } 2916 2917 /* 2918 * Main transmit routine for C+ and gigE NICs. 2919 */ 2920 static void 2921 re_start_locked(struct ifnet *ifp) 2922 { 2923 struct rl_softc *sc; 2924 struct mbuf *m_head; 2925 int queued; 2926 2927 sc = ifp->if_softc; 2928 2929 #ifdef DEV_NETMAP 2930 /* XXX is this necessary ? */ 2931 if (ifp->if_capenable & IFCAP_NETMAP) { 2932 struct netmap_kring *kring = &NA(ifp)->tx_rings[0]; 2933 if (sc->rl_ldata.rl_tx_prodidx != kring->nr_hwcur) { 2934 /* kick the tx unit */ 2935 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2936 #ifdef RE_TX_MODERATION 2937 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2938 #endif 2939 sc->rl_watchdog_timer = 5; 2940 } 2941 return; 2942 } 2943 #endif /* DEV_NETMAP */ 2944 2945 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2946 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) 2947 return; 2948 2949 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2950 sc->rl_ldata.rl_tx_free > 1;) { 2951 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2952 if (m_head == NULL) 2953 break; 2954 2955 if (re_encap(sc, &m_head) != 0) { 2956 if (m_head == NULL) 2957 break; 2958 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2959 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2960 break; 2961 } 2962 2963 /* 2964 * If there's a BPF listener, bounce a copy of this frame 2965 * to him. 2966 */ 2967 ETHER_BPF_MTAP(ifp, m_head); 2968 2969 queued++; 2970 } 2971 2972 if (queued == 0) { 2973 #ifdef RE_TX_MODERATION 2974 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2975 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2976 #endif 2977 return; 2978 } 2979 2980 /* Flush the TX descriptors */ 2981 2982 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2983 sc->rl_ldata.rl_tx_list_map, 2984 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2985 2986 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2987 2988 #ifdef RE_TX_MODERATION 2989 /* 2990 * Use the countdown timer for interrupt moderation. 2991 * 'TX done' interrupts are disabled. Instead, we reset the 2992 * countdown timer, which will begin counting until it hits 2993 * the value in the TIMERINT register, and then trigger an 2994 * interrupt. Each time we write to the TIMERCNT register, 2995 * the timer count is reset to 0. 2996 */ 2997 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2998 #endif 2999 3000 /* 3001 * Set a timeout in case the chip goes out to lunch. 3002 */ 3003 sc->rl_watchdog_timer = 5; 3004 } 3005 3006 static void 3007 re_set_jumbo(struct rl_softc *sc, int jumbo) 3008 { 3009 3010 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168E_VL) { 3011 pci_set_max_read_req(sc->rl_dev, 4096); 3012 return; 3013 } 3014 3015 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 3016 if (jumbo != 0) { 3017 CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) | 3018 RL_CFG3_JUMBO_EN0); 3019 switch (sc->rl_hwrev->rl_rev) { 3020 case RL_HWREV_8168DP: 3021 break; 3022 case RL_HWREV_8168E: 3023 CSR_WRITE_1(sc, sc->rl_cfg4, 3024 CSR_READ_1(sc, sc->rl_cfg4) | 0x01); 3025 break; 3026 default: 3027 CSR_WRITE_1(sc, sc->rl_cfg4, 3028 CSR_READ_1(sc, sc->rl_cfg4) | RL_CFG4_JUMBO_EN1); 3029 } 3030 } else { 3031 CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) & 3032 ~RL_CFG3_JUMBO_EN0); 3033 switch (sc->rl_hwrev->rl_rev) { 3034 case RL_HWREV_8168DP: 3035 break; 3036 case RL_HWREV_8168E: 3037 CSR_WRITE_1(sc, sc->rl_cfg4, 3038 CSR_READ_1(sc, sc->rl_cfg4) & ~0x01); 3039 break; 3040 default: 3041 CSR_WRITE_1(sc, sc->rl_cfg4, 3042 CSR_READ_1(sc, sc->rl_cfg4) & ~RL_CFG4_JUMBO_EN1); 3043 } 3044 } 3045 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3046 3047 switch (sc->rl_hwrev->rl_rev) { 3048 case RL_HWREV_8168DP: 3049 pci_set_max_read_req(sc->rl_dev, 4096); 3050 break; 3051 default: 3052 if (jumbo != 0) 3053 pci_set_max_read_req(sc->rl_dev, 512); 3054 else 3055 pci_set_max_read_req(sc->rl_dev, 4096); 3056 } 3057 } 3058 3059 static void 3060 re_init(void *xsc) 3061 { 3062 struct rl_softc *sc = xsc; 3063 3064 RL_LOCK(sc); 3065 re_init_locked(sc); 3066 RL_UNLOCK(sc); 3067 } 3068 3069 static void 3070 re_init_locked(struct rl_softc *sc) 3071 { 3072 struct ifnet *ifp = sc->rl_ifp; 3073 struct mii_data *mii; 3074 uint32_t reg; 3075 uint16_t cfg; 3076 union { 3077 uint32_t align_dummy; 3078 u_char eaddr[ETHER_ADDR_LEN]; 3079 } eaddr; 3080 3081 RL_LOCK_ASSERT(sc); 3082 3083 mii = device_get_softc(sc->rl_miibus); 3084 3085 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3086 return; 3087 3088 /* 3089 * Cancel pending I/O and free all RX/TX buffers. 3090 */ 3091 re_stop(sc); 3092 3093 /* Put controller into known state. */ 3094 re_reset(sc); 3095 3096 /* 3097 * For C+ mode, initialize the RX descriptors and mbufs. 3098 */ 3099 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3100 if (ifp->if_mtu > RL_MTU) { 3101 if (re_jrx_list_init(sc) != 0) { 3102 device_printf(sc->rl_dev, 3103 "no memory for jumbo RX buffers\n"); 3104 re_stop(sc); 3105 return; 3106 } 3107 /* Disable checksum offloading for jumbo frames. */ 3108 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_TSO4); 3109 ifp->if_hwassist &= ~(RE_CSUM_FEATURES | CSUM_TSO); 3110 } else { 3111 if (re_rx_list_init(sc) != 0) { 3112 device_printf(sc->rl_dev, 3113 "no memory for RX buffers\n"); 3114 re_stop(sc); 3115 return; 3116 } 3117 } 3118 re_set_jumbo(sc, ifp->if_mtu > RL_MTU); 3119 } else { 3120 if (re_rx_list_init(sc) != 0) { 3121 device_printf(sc->rl_dev, "no memory for RX buffers\n"); 3122 re_stop(sc); 3123 return; 3124 } 3125 if ((sc->rl_flags & RL_FLAG_PCIE) != 0 && 3126 pci_get_device(sc->rl_dev) != RT_DEVICEID_8101E) { 3127 if (ifp->if_mtu > RL_MTU) 3128 pci_set_max_read_req(sc->rl_dev, 512); 3129 else 3130 pci_set_max_read_req(sc->rl_dev, 4096); 3131 } 3132 } 3133 re_tx_list_init(sc); 3134 3135 /* 3136 * Enable C+ RX and TX mode, as well as VLAN stripping and 3137 * RX checksum offload. We must configure the C+ register 3138 * before all others. 3139 */ 3140 cfg = RL_CPLUSCMD_PCI_MRW; 3141 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 3142 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 3143 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3144 cfg |= RL_CPLUSCMD_VLANSTRIP; 3145 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) { 3146 cfg |= RL_CPLUSCMD_MACSTAT_DIS; 3147 /* XXX magic. */ 3148 cfg |= 0x0001; 3149 } else 3150 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB; 3151 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg); 3152 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SC || 3153 sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) { 3154 reg = 0x000fff00; 3155 if ((CSR_READ_1(sc, sc->rl_cfg2) & RL_CFG2_PCI66MHZ) != 0) 3156 reg |= 0x000000ff; 3157 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) 3158 reg |= 0x00f00000; 3159 CSR_WRITE_4(sc, 0x7c, reg); 3160 /* Disable interrupt mitigation. */ 3161 CSR_WRITE_2(sc, 0xe2, 0); 3162 } 3163 /* 3164 * Disable TSO if interface MTU size is greater than MSS 3165 * allowed in controller. 3166 */ 3167 if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) { 3168 ifp->if_capenable &= ~IFCAP_TSO4; 3169 ifp->if_hwassist &= ~CSUM_TSO; 3170 } 3171 3172 /* 3173 * Init our MAC address. Even though the chipset 3174 * documentation doesn't mention it, we need to enter "Config 3175 * register write enable" mode to modify the ID registers. 3176 */ 3177 /* Copy MAC address on stack to align. */ 3178 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 3179 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 3180 CSR_WRITE_4(sc, RL_IDR0, 3181 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 3182 CSR_WRITE_4(sc, RL_IDR4, 3183 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 3184 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3185 3186 /* 3187 * Load the addresses of the RX and TX lists into the chip. 3188 */ 3189 3190 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 3191 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 3192 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 3193 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 3194 3195 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 3196 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 3197 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 3198 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 3199 3200 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0) { 3201 /* Disable RXDV gate. */ 3202 CSR_WRITE_4(sc, RL_MISC, CSR_READ_4(sc, RL_MISC) & 3203 ~0x00080000); 3204 } 3205 3206 /* 3207 * Enable transmit and receive for pre-RTL8168G controllers. 3208 * RX/TX MACs should be enabled before RX/TX configuration. 3209 */ 3210 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) == 0) 3211 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB | RL_CMD_RX_ENB); 3212 3213 /* 3214 * Set the initial TX configuration. 3215 */ 3216 if (sc->rl_testmode) { 3217 if (sc->rl_type == RL_8169) 3218 CSR_WRITE_4(sc, RL_TXCFG, 3219 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 3220 else 3221 CSR_WRITE_4(sc, RL_TXCFG, 3222 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 3223 } else 3224 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 3225 3226 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 3227 3228 /* 3229 * Set the initial RX configuration. 3230 */ 3231 re_set_rxmode(sc); 3232 3233 /* Configure interrupt moderation. */ 3234 if (sc->rl_type == RL_8169) { 3235 /* Magic from vendor. */ 3236 CSR_WRITE_2(sc, RL_INTRMOD, 0x5100); 3237 } 3238 3239 /* 3240 * Enable transmit and receive for RTL8168G and later controllers. 3241 * RX/TX MACs should be enabled after RX/TX configuration. 3242 */ 3243 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0) 3244 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB | RL_CMD_RX_ENB); 3245 3246 #ifdef DEVICE_POLLING 3247 /* 3248 * Disable interrupts if we are polling. 3249 */ 3250 if (ifp->if_capenable & IFCAP_POLLING) 3251 CSR_WRITE_2(sc, RL_IMR, 0); 3252 else /* otherwise ... */ 3253 #endif 3254 3255 /* 3256 * Enable interrupts. 3257 */ 3258 if (sc->rl_testmode) 3259 CSR_WRITE_2(sc, RL_IMR, 0); 3260 else 3261 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 3262 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 3263 3264 /* Set initial TX threshold */ 3265 sc->rl_txthresh = RL_TX_THRESH_INIT; 3266 3267 /* Start RX/TX process. */ 3268 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 3269 3270 /* 3271 * Initialize the timer interrupt register so that 3272 * a timer interrupt will be generated once the timer 3273 * reaches a certain number of ticks. The timer is 3274 * reloaded on each transmit. 3275 */ 3276 #ifdef RE_TX_MODERATION 3277 /* 3278 * Use timer interrupt register to moderate TX interrupt 3279 * moderation, which dramatically improves TX frame rate. 3280 */ 3281 if (sc->rl_type == RL_8169) 3282 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 3283 else 3284 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 3285 #else 3286 /* 3287 * Use timer interrupt register to moderate RX interrupt 3288 * moderation. 3289 */ 3290 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 && 3291 intr_filter == 0) { 3292 if (sc->rl_type == RL_8169) 3293 CSR_WRITE_4(sc, RL_TIMERINT_8169, 3294 RL_USECS(sc->rl_int_rx_mod)); 3295 } else { 3296 if (sc->rl_type == RL_8169) 3297 CSR_WRITE_4(sc, RL_TIMERINT_8169, RL_USECS(0)); 3298 } 3299 #endif 3300 3301 /* 3302 * For 8169 gigE NICs, set the max allowed RX packet 3303 * size so we can receive jumbo frames. 3304 */ 3305 if (sc->rl_type == RL_8169) { 3306 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3307 /* 3308 * For controllers that use new jumbo frame scheme, 3309 * set maximum size of jumbo frame depending on 3310 * controller revisions. 3311 */ 3312 if (ifp->if_mtu > RL_MTU) 3313 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 3314 sc->rl_hwrev->rl_max_mtu + 3315 ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN + 3316 ETHER_CRC_LEN); 3317 else 3318 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 3319 RE_RX_DESC_BUFLEN); 3320 } else if ((sc->rl_flags & RL_FLAG_PCIE) != 0 && 3321 sc->rl_hwrev->rl_max_mtu == RL_MTU) { 3322 /* RTL810x has no jumbo frame support. */ 3323 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, RE_RX_DESC_BUFLEN); 3324 } else 3325 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 3326 } 3327 3328 if (sc->rl_testmode) 3329 return; 3330 3331 CSR_WRITE_1(sc, sc->rl_cfg1, CSR_READ_1(sc, sc->rl_cfg1) | 3332 RL_CFG1_DRVLOAD); 3333 3334 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3335 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3336 3337 sc->rl_flags &= ~RL_FLAG_LINK; 3338 mii_mediachg(mii); 3339 3340 sc->rl_watchdog_timer = 0; 3341 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 3342 } 3343 3344 /* 3345 * Set media options. 3346 */ 3347 static int 3348 re_ifmedia_upd(struct ifnet *ifp) 3349 { 3350 struct rl_softc *sc; 3351 struct mii_data *mii; 3352 int error; 3353 3354 sc = ifp->if_softc; 3355 mii = device_get_softc(sc->rl_miibus); 3356 RL_LOCK(sc); 3357 error = mii_mediachg(mii); 3358 RL_UNLOCK(sc); 3359 3360 return (error); 3361 } 3362 3363 /* 3364 * Report current media status. 3365 */ 3366 static void 3367 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3368 { 3369 struct rl_softc *sc; 3370 struct mii_data *mii; 3371 3372 sc = ifp->if_softc; 3373 mii = device_get_softc(sc->rl_miibus); 3374 3375 RL_LOCK(sc); 3376 mii_pollstat(mii); 3377 ifmr->ifm_active = mii->mii_media_active; 3378 ifmr->ifm_status = mii->mii_media_status; 3379 RL_UNLOCK(sc); 3380 } 3381 3382 static int 3383 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3384 { 3385 struct rl_softc *sc = ifp->if_softc; 3386 struct ifreq *ifr = (struct ifreq *) data; 3387 struct mii_data *mii; 3388 int error = 0; 3389 3390 switch (command) { 3391 case SIOCSIFMTU: 3392 if (ifr->ifr_mtu < ETHERMIN || 3393 ifr->ifr_mtu > sc->rl_hwrev->rl_max_mtu || 3394 ((sc->rl_flags & RL_FLAG_FASTETHER) != 0 && 3395 ifr->ifr_mtu > RL_MTU)) { 3396 error = EINVAL; 3397 break; 3398 } 3399 RL_LOCK(sc); 3400 if (ifp->if_mtu != ifr->ifr_mtu) { 3401 ifp->if_mtu = ifr->ifr_mtu; 3402 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 3403 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3404 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3405 re_init_locked(sc); 3406 } 3407 if (ifp->if_mtu > RL_TSO_MTU && 3408 (ifp->if_capenable & IFCAP_TSO4) != 0) { 3409 ifp->if_capenable &= ~(IFCAP_TSO4 | 3410 IFCAP_VLAN_HWTSO); 3411 ifp->if_hwassist &= ~CSUM_TSO; 3412 } 3413 VLAN_CAPABILITIES(ifp); 3414 } 3415 RL_UNLOCK(sc); 3416 break; 3417 case SIOCSIFFLAGS: 3418 RL_LOCK(sc); 3419 if ((ifp->if_flags & IFF_UP) != 0) { 3420 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3421 if (((ifp->if_flags ^ sc->rl_if_flags) 3422 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 3423 re_set_rxmode(sc); 3424 } else 3425 re_init_locked(sc); 3426 } else { 3427 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3428 re_stop(sc); 3429 } 3430 sc->rl_if_flags = ifp->if_flags; 3431 RL_UNLOCK(sc); 3432 break; 3433 case SIOCADDMULTI: 3434 case SIOCDELMULTI: 3435 RL_LOCK(sc); 3436 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3437 re_set_rxmode(sc); 3438 RL_UNLOCK(sc); 3439 break; 3440 case SIOCGIFMEDIA: 3441 case SIOCSIFMEDIA: 3442 mii = device_get_softc(sc->rl_miibus); 3443 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3444 break; 3445 case SIOCSIFCAP: 3446 { 3447 int mask, reinit; 3448 3449 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3450 reinit = 0; 3451 #ifdef DEVICE_POLLING 3452 if (mask & IFCAP_POLLING) { 3453 if (ifr->ifr_reqcap & IFCAP_POLLING) { 3454 error = ether_poll_register(re_poll, ifp); 3455 if (error) 3456 return (error); 3457 RL_LOCK(sc); 3458 /* Disable interrupts */ 3459 CSR_WRITE_2(sc, RL_IMR, 0x0000); 3460 ifp->if_capenable |= IFCAP_POLLING; 3461 RL_UNLOCK(sc); 3462 } else { 3463 error = ether_poll_deregister(ifp); 3464 /* Enable interrupts. */ 3465 RL_LOCK(sc); 3466 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 3467 ifp->if_capenable &= ~IFCAP_POLLING; 3468 RL_UNLOCK(sc); 3469 } 3470 } 3471 #endif /* DEVICE_POLLING */ 3472 RL_LOCK(sc); 3473 if ((mask & IFCAP_TXCSUM) != 0 && 3474 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 3475 ifp->if_capenable ^= IFCAP_TXCSUM; 3476 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 3477 ifp->if_hwassist |= RE_CSUM_FEATURES; 3478 else 3479 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 3480 reinit = 1; 3481 } 3482 if ((mask & IFCAP_RXCSUM) != 0 && 3483 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 3484 ifp->if_capenable ^= IFCAP_RXCSUM; 3485 reinit = 1; 3486 } 3487 if ((mask & IFCAP_TSO4) != 0 && 3488 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 3489 ifp->if_capenable ^= IFCAP_TSO4; 3490 if ((IFCAP_TSO4 & ifp->if_capenable) != 0) 3491 ifp->if_hwassist |= CSUM_TSO; 3492 else 3493 ifp->if_hwassist &= ~CSUM_TSO; 3494 if (ifp->if_mtu > RL_TSO_MTU && 3495 (ifp->if_capenable & IFCAP_TSO4) != 0) { 3496 ifp->if_capenable &= ~IFCAP_TSO4; 3497 ifp->if_hwassist &= ~CSUM_TSO; 3498 } 3499 } 3500 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 3501 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 3502 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 3503 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3504 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 3505 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 3506 /* TSO over VLAN requires VLAN hardware tagging. */ 3507 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 3508 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 3509 reinit = 1; 3510 } 3511 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 3512 (mask & (IFCAP_HWCSUM | IFCAP_TSO4 | 3513 IFCAP_VLAN_HWTSO)) != 0) 3514 reinit = 1; 3515 if ((mask & IFCAP_WOL) != 0 && 3516 (ifp->if_capabilities & IFCAP_WOL) != 0) { 3517 if ((mask & IFCAP_WOL_UCAST) != 0) 3518 ifp->if_capenable ^= IFCAP_WOL_UCAST; 3519 if ((mask & IFCAP_WOL_MCAST) != 0) 3520 ifp->if_capenable ^= IFCAP_WOL_MCAST; 3521 if ((mask & IFCAP_WOL_MAGIC) != 0) 3522 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 3523 } 3524 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) { 3525 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3526 re_init_locked(sc); 3527 } 3528 RL_UNLOCK(sc); 3529 VLAN_CAPABILITIES(ifp); 3530 } 3531 break; 3532 default: 3533 error = ether_ioctl(ifp, command, data); 3534 break; 3535 } 3536 3537 return (error); 3538 } 3539 3540 static void 3541 re_watchdog(struct rl_softc *sc) 3542 { 3543 struct ifnet *ifp; 3544 3545 RL_LOCK_ASSERT(sc); 3546 3547 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 3548 return; 3549 3550 ifp = sc->rl_ifp; 3551 re_txeof(sc); 3552 if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) { 3553 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 3554 "-- recovering\n"); 3555 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3556 re_start_locked(ifp); 3557 return; 3558 } 3559 3560 if_printf(ifp, "watchdog timeout\n"); 3561 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3562 3563 re_rxeof(sc, NULL); 3564 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3565 re_init_locked(sc); 3566 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3567 re_start_locked(ifp); 3568 } 3569 3570 /* 3571 * Stop the adapter and free any mbufs allocated to the 3572 * RX and TX lists. 3573 */ 3574 static void 3575 re_stop(struct rl_softc *sc) 3576 { 3577 int i; 3578 struct ifnet *ifp; 3579 struct rl_txdesc *txd; 3580 struct rl_rxdesc *rxd; 3581 3582 RL_LOCK_ASSERT(sc); 3583 3584 ifp = sc->rl_ifp; 3585 3586 sc->rl_watchdog_timer = 0; 3587 callout_stop(&sc->rl_stat_callout); 3588 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3589 3590 /* 3591 * Disable accepting frames to put RX MAC into idle state. 3592 * Otherwise it's possible to get frames while stop command 3593 * execution is in progress and controller can DMA the frame 3594 * to already freed RX buffer during that period. 3595 */ 3596 CSR_WRITE_4(sc, RL_RXCFG, CSR_READ_4(sc, RL_RXCFG) & 3597 ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_MULTI | 3598 RL_RXCFG_RX_BROAD)); 3599 3600 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0) { 3601 /* Enable RXDV gate. */ 3602 CSR_WRITE_4(sc, RL_MISC, CSR_READ_4(sc, RL_MISC) | 3603 0x00080000); 3604 } 3605 3606 if ((sc->rl_flags & RL_FLAG_WAIT_TXPOLL) != 0) { 3607 for (i = RL_TIMEOUT; i > 0; i--) { 3608 if ((CSR_READ_1(sc, sc->rl_txstart) & 3609 RL_TXSTART_START) == 0) 3610 break; 3611 DELAY(20); 3612 } 3613 if (i == 0) 3614 device_printf(sc->rl_dev, 3615 "stopping TX poll timed out!\n"); 3616 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 3617 } else if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0) { 3618 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB | 3619 RL_CMD_RX_ENB); 3620 if ((sc->rl_flags & RL_FLAG_CMDSTOP_WAIT_TXQ) != 0) { 3621 for (i = RL_TIMEOUT; i > 0; i--) { 3622 if ((CSR_READ_4(sc, RL_TXCFG) & 3623 RL_TXCFG_QUEUE_EMPTY) != 0) 3624 break; 3625 DELAY(100); 3626 } 3627 if (i == 0) 3628 device_printf(sc->rl_dev, 3629 "stopping TXQ timed out!\n"); 3630 } 3631 } else 3632 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 3633 DELAY(1000); 3634 CSR_WRITE_2(sc, RL_IMR, 0x0000); 3635 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 3636 3637 if (sc->rl_head != NULL) { 3638 m_freem(sc->rl_head); 3639 sc->rl_head = sc->rl_tail = NULL; 3640 } 3641 3642 /* Free the TX list buffers. */ 3643 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 3644 txd = &sc->rl_ldata.rl_tx_desc[i]; 3645 if (txd->tx_m != NULL) { 3646 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 3647 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3648 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 3649 txd->tx_dmamap); 3650 m_freem(txd->tx_m); 3651 txd->tx_m = NULL; 3652 } 3653 } 3654 3655 /* Free the RX list buffers. */ 3656 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 3657 rxd = &sc->rl_ldata.rl_rx_desc[i]; 3658 if (rxd->rx_m != NULL) { 3659 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 3660 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3661 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 3662 rxd->rx_dmamap); 3663 m_freem(rxd->rx_m); 3664 rxd->rx_m = NULL; 3665 } 3666 } 3667 3668 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3669 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 3670 rxd = &sc->rl_ldata.rl_jrx_desc[i]; 3671 if (rxd->rx_m != NULL) { 3672 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, 3673 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3674 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, 3675 rxd->rx_dmamap); 3676 m_freem(rxd->rx_m); 3677 rxd->rx_m = NULL; 3678 } 3679 } 3680 } 3681 } 3682 3683 /* 3684 * Device suspend routine. Stop the interface and save some PCI 3685 * settings in case the BIOS doesn't restore them properly on 3686 * resume. 3687 */ 3688 static int 3689 re_suspend(device_t dev) 3690 { 3691 struct rl_softc *sc; 3692 3693 sc = device_get_softc(dev); 3694 3695 RL_LOCK(sc); 3696 re_stop(sc); 3697 re_setwol(sc); 3698 sc->suspended = 1; 3699 RL_UNLOCK(sc); 3700 3701 return (0); 3702 } 3703 3704 /* 3705 * Device resume routine. Restore some PCI settings in case the BIOS 3706 * doesn't, re-enable busmastering, and restart the interface if 3707 * appropriate. 3708 */ 3709 static int 3710 re_resume(device_t dev) 3711 { 3712 struct rl_softc *sc; 3713 struct ifnet *ifp; 3714 3715 sc = device_get_softc(dev); 3716 3717 RL_LOCK(sc); 3718 3719 ifp = sc->rl_ifp; 3720 /* Take controller out of sleep mode. */ 3721 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3722 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3723 CSR_WRITE_1(sc, RL_GPIO, 3724 CSR_READ_1(sc, RL_GPIO) | 0x01); 3725 } 3726 3727 /* 3728 * Clear WOL matching such that normal Rx filtering 3729 * wouldn't interfere with WOL patterns. 3730 */ 3731 re_clrwol(sc); 3732 3733 /* reinitialize interface if necessary */ 3734 if (ifp->if_flags & IFF_UP) 3735 re_init_locked(sc); 3736 3737 sc->suspended = 0; 3738 RL_UNLOCK(sc); 3739 3740 return (0); 3741 } 3742 3743 /* 3744 * Stop all chip I/O so that the kernel's probe routines don't 3745 * get confused by errant DMAs when rebooting. 3746 */ 3747 static int 3748 re_shutdown(device_t dev) 3749 { 3750 struct rl_softc *sc; 3751 3752 sc = device_get_softc(dev); 3753 3754 RL_LOCK(sc); 3755 re_stop(sc); 3756 /* 3757 * Mark interface as down since otherwise we will panic if 3758 * interrupt comes in later on, which can happen in some 3759 * cases. 3760 */ 3761 sc->rl_ifp->if_flags &= ~IFF_UP; 3762 re_setwol(sc); 3763 RL_UNLOCK(sc); 3764 3765 return (0); 3766 } 3767 3768 static void 3769 re_set_linkspeed(struct rl_softc *sc) 3770 { 3771 struct mii_softc *miisc; 3772 struct mii_data *mii; 3773 int aneg, i, phyno; 3774 3775 RL_LOCK_ASSERT(sc); 3776 3777 mii = device_get_softc(sc->rl_miibus); 3778 mii_pollstat(mii); 3779 aneg = 0; 3780 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 3781 (IFM_ACTIVE | IFM_AVALID)) { 3782 switch IFM_SUBTYPE(mii->mii_media_active) { 3783 case IFM_10_T: 3784 case IFM_100_TX: 3785 return; 3786 case IFM_1000_T: 3787 aneg++; 3788 break; 3789 default: 3790 break; 3791 } 3792 } 3793 miisc = LIST_FIRST(&mii->mii_phys); 3794 phyno = miisc->mii_phy; 3795 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 3796 PHY_RESET(miisc); 3797 re_miibus_writereg(sc->rl_dev, phyno, MII_100T2CR, 0); 3798 re_miibus_writereg(sc->rl_dev, phyno, 3799 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 3800 re_miibus_writereg(sc->rl_dev, phyno, 3801 MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 3802 DELAY(1000); 3803 if (aneg != 0) { 3804 /* 3805 * Poll link state until re(4) get a 10/100Mbps link. 3806 */ 3807 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 3808 mii_pollstat(mii); 3809 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 3810 == (IFM_ACTIVE | IFM_AVALID)) { 3811 switch (IFM_SUBTYPE(mii->mii_media_active)) { 3812 case IFM_10_T: 3813 case IFM_100_TX: 3814 return; 3815 default: 3816 break; 3817 } 3818 } 3819 RL_UNLOCK(sc); 3820 pause("relnk", hz); 3821 RL_LOCK(sc); 3822 } 3823 if (i == MII_ANEGTICKS_GIGE) 3824 device_printf(sc->rl_dev, 3825 "establishing a link failed, WOL may not work!"); 3826 } 3827 /* 3828 * No link, force MAC to have 100Mbps, full-duplex link. 3829 * MAC does not require reprogramming on resolved speed/duplex, 3830 * so this is just for completeness. 3831 */ 3832 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 3833 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 3834 } 3835 3836 static void 3837 re_setwol(struct rl_softc *sc) 3838 { 3839 struct ifnet *ifp; 3840 int pmc; 3841 uint16_t pmstat; 3842 uint8_t v; 3843 3844 RL_LOCK_ASSERT(sc); 3845 3846 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3847 return; 3848 3849 ifp = sc->rl_ifp; 3850 /* Put controller into sleep mode. */ 3851 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3852 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3853 CSR_WRITE_1(sc, RL_GPIO, 3854 CSR_READ_1(sc, RL_GPIO) & ~0x01); 3855 } 3856 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 3857 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0) { 3858 /* Disable RXDV gate. */ 3859 CSR_WRITE_4(sc, RL_MISC, CSR_READ_4(sc, RL_MISC) & 3860 ~0x00080000); 3861 } 3862 re_set_rxmode(sc); 3863 if ((sc->rl_flags & RL_FLAG_WOL_MANLINK) != 0) 3864 re_set_linkspeed(sc); 3865 if ((sc->rl_flags & RL_FLAG_WOLRXENB) != 0) 3866 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB); 3867 } 3868 /* Enable config register write. */ 3869 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3870 3871 /* Enable PME. */ 3872 v = CSR_READ_1(sc, sc->rl_cfg1); 3873 v &= ~RL_CFG1_PME; 3874 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3875 v |= RL_CFG1_PME; 3876 CSR_WRITE_1(sc, sc->rl_cfg1, v); 3877 3878 v = CSR_READ_1(sc, sc->rl_cfg3); 3879 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3880 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3881 v |= RL_CFG3_WOL_MAGIC; 3882 CSR_WRITE_1(sc, sc->rl_cfg3, v); 3883 3884 v = CSR_READ_1(sc, sc->rl_cfg5); 3885 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST | 3886 RL_CFG5_WOL_LANWAKE); 3887 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 3888 v |= RL_CFG5_WOL_UCAST; 3889 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 3890 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 3891 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3892 v |= RL_CFG5_WOL_LANWAKE; 3893 CSR_WRITE_1(sc, sc->rl_cfg5, v); 3894 3895 /* Config register write done. */ 3896 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3897 3898 if ((ifp->if_capenable & IFCAP_WOL) == 0 && 3899 (sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) 3900 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) & ~0x80); 3901 /* 3902 * It seems that hardware resets its link speed to 100Mbps in 3903 * power down mode so switching to 100Mbps in driver is not 3904 * needed. 3905 */ 3906 3907 /* Request PME if WOL is requested. */ 3908 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 3909 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3910 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3911 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3912 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 3913 } 3914 3915 static void 3916 re_clrwol(struct rl_softc *sc) 3917 { 3918 int pmc; 3919 uint8_t v; 3920 3921 RL_LOCK_ASSERT(sc); 3922 3923 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3924 return; 3925 3926 /* Enable config register write. */ 3927 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3928 3929 v = CSR_READ_1(sc, sc->rl_cfg3); 3930 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3931 CSR_WRITE_1(sc, sc->rl_cfg3, v); 3932 3933 /* Config register write done. */ 3934 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3935 3936 v = CSR_READ_1(sc, sc->rl_cfg5); 3937 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3938 v &= ~RL_CFG5_WOL_LANWAKE; 3939 CSR_WRITE_1(sc, sc->rl_cfg5, v); 3940 } 3941 3942 static void 3943 re_add_sysctls(struct rl_softc *sc) 3944 { 3945 struct sysctl_ctx_list *ctx; 3946 struct sysctl_oid_list *children; 3947 int error; 3948 3949 ctx = device_get_sysctl_ctx(sc->rl_dev); 3950 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev)); 3951 3952 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "stats", 3953 CTLTYPE_INT | CTLFLAG_RW, sc, 0, re_sysctl_stats, "I", 3954 "Statistics Information"); 3955 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) 3956 return; 3957 3958 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "int_rx_mod", 3959 CTLTYPE_INT | CTLFLAG_RW, &sc->rl_int_rx_mod, 0, 3960 sysctl_hw_re_int_mod, "I", "re RX interrupt moderation"); 3961 /* Pull in device tunables. */ 3962 sc->rl_int_rx_mod = RL_TIMER_DEFAULT; 3963 error = resource_int_value(device_get_name(sc->rl_dev), 3964 device_get_unit(sc->rl_dev), "int_rx_mod", &sc->rl_int_rx_mod); 3965 if (error == 0) { 3966 if (sc->rl_int_rx_mod < RL_TIMER_MIN || 3967 sc->rl_int_rx_mod > RL_TIMER_MAX) { 3968 device_printf(sc->rl_dev, "int_rx_mod value out of " 3969 "range; using default: %d\n", 3970 RL_TIMER_DEFAULT); 3971 sc->rl_int_rx_mod = RL_TIMER_DEFAULT; 3972 } 3973 } 3974 } 3975 3976 static int 3977 re_sysctl_stats(SYSCTL_HANDLER_ARGS) 3978 { 3979 struct rl_softc *sc; 3980 struct rl_stats *stats; 3981 int error, i, result; 3982 3983 result = -1; 3984 error = sysctl_handle_int(oidp, &result, 0, req); 3985 if (error || req->newptr == NULL) 3986 return (error); 3987 3988 if (result == 1) { 3989 sc = (struct rl_softc *)arg1; 3990 RL_LOCK(sc); 3991 if ((sc->rl_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 3992 RL_UNLOCK(sc); 3993 goto done; 3994 } 3995 bus_dmamap_sync(sc->rl_ldata.rl_stag, 3996 sc->rl_ldata.rl_smap, BUS_DMASYNC_PREREAD); 3997 CSR_WRITE_4(sc, RL_DUMPSTATS_HI, 3998 RL_ADDR_HI(sc->rl_ldata.rl_stats_addr)); 3999 CSR_WRITE_4(sc, RL_DUMPSTATS_LO, 4000 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr)); 4001 CSR_WRITE_4(sc, RL_DUMPSTATS_LO, 4002 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr | 4003 RL_DUMPSTATS_START)); 4004 for (i = RL_TIMEOUT; i > 0; i--) { 4005 if ((CSR_READ_4(sc, RL_DUMPSTATS_LO) & 4006 RL_DUMPSTATS_START) == 0) 4007 break; 4008 DELAY(1000); 4009 } 4010 bus_dmamap_sync(sc->rl_ldata.rl_stag, 4011 sc->rl_ldata.rl_smap, BUS_DMASYNC_POSTREAD); 4012 RL_UNLOCK(sc); 4013 if (i == 0) { 4014 device_printf(sc->rl_dev, 4015 "DUMP statistics request timed out\n"); 4016 return (ETIMEDOUT); 4017 } 4018 done: 4019 stats = sc->rl_ldata.rl_stats; 4020 printf("%s statistics:\n", device_get_nameunit(sc->rl_dev)); 4021 printf("Tx frames : %ju\n", 4022 (uintmax_t)le64toh(stats->rl_tx_pkts)); 4023 printf("Rx frames : %ju\n", 4024 (uintmax_t)le64toh(stats->rl_rx_pkts)); 4025 printf("Tx errors : %ju\n", 4026 (uintmax_t)le64toh(stats->rl_tx_errs)); 4027 printf("Rx errors : %u\n", 4028 le32toh(stats->rl_rx_errs)); 4029 printf("Rx missed frames : %u\n", 4030 (uint32_t)le16toh(stats->rl_missed_pkts)); 4031 printf("Rx frame alignment errs : %u\n", 4032 (uint32_t)le16toh(stats->rl_rx_framealign_errs)); 4033 printf("Tx single collisions : %u\n", 4034 le32toh(stats->rl_tx_onecoll)); 4035 printf("Tx multiple collisions : %u\n", 4036 le32toh(stats->rl_tx_multicolls)); 4037 printf("Rx unicast frames : %ju\n", 4038 (uintmax_t)le64toh(stats->rl_rx_ucasts)); 4039 printf("Rx broadcast frames : %ju\n", 4040 (uintmax_t)le64toh(stats->rl_rx_bcasts)); 4041 printf("Rx multicast frames : %u\n", 4042 le32toh(stats->rl_rx_mcasts)); 4043 printf("Tx aborts : %u\n", 4044 (uint32_t)le16toh(stats->rl_tx_aborts)); 4045 printf("Tx underruns : %u\n", 4046 (uint32_t)le16toh(stats->rl_rx_underruns)); 4047 } 4048 4049 return (error); 4050 } 4051 4052 static int 4053 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4054 { 4055 int error, value; 4056 4057 if (arg1 == NULL) 4058 return (EINVAL); 4059 value = *(int *)arg1; 4060 error = sysctl_handle_int(oidp, &value, 0, req); 4061 if (error || req->newptr == NULL) 4062 return (error); 4063 if (value < low || value > high) 4064 return (EINVAL); 4065 *(int *)arg1 = value; 4066 4067 return (0); 4068 } 4069 4070 static int 4071 sysctl_hw_re_int_mod(SYSCTL_HANDLER_ARGS) 4072 { 4073 4074 return (sysctl_int_range(oidp, arg1, arg2, req, RL_TIMER_MIN, 4075 RL_TIMER_MAX)); 4076 } 4077