1 /*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44 /* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S 48 * and the RTL8110S. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111 #include <sys/param.h> 112 #include <sys/endian.h> 113 #include <sys/systm.h> 114 #include <sys/sockio.h> 115 #include <sys/mbuf.h> 116 #include <sys/malloc.h> 117 #include <sys/module.h> 118 #include <sys/kernel.h> 119 #include <sys/socket.h> 120 121 #include <net/if.h> 122 #include <net/if_arp.h> 123 #include <net/ethernet.h> 124 #include <net/if_dl.h> 125 #include <net/if_media.h> 126 #include <net/if_vlan_var.h> 127 128 #include <net/bpf.h> 129 130 #include <machine/bus_pio.h> 131 #include <machine/bus_memio.h> 132 #include <machine/bus.h> 133 #include <machine/resource.h> 134 #include <sys/bus.h> 135 #include <sys/rman.h> 136 137 #include <dev/mii/mii.h> 138 #include <dev/mii/miivar.h> 139 140 #include <dev/pci/pcireg.h> 141 #include <dev/pci/pcivar.h> 142 143 MODULE_DEPEND(re, pci, 1, 1, 1); 144 MODULE_DEPEND(re, ether, 1, 1, 1); 145 MODULE_DEPEND(re, miibus, 1, 1, 1); 146 147 /* "controller miibus0" required. See GENERIC if you get errors here. */ 148 #include "miibus_if.h" 149 150 /* 151 * Default to using PIO access for this driver. 152 */ 153 #define RE_USEIOSPACE 154 155 #include <pci/if_rlreg.h> 156 157 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 158 159 /* 160 * Various supported device vendors/types and their names. 161 */ 162 static struct rl_type re_devs[] = { 163 { RT_VENDORID, RT_DEVICEID_8139, RL_HWREV_8139CPLUS, 164 "RealTek 8139C+ 10/100BaseTX" }, 165 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169, 166 "RealTek 8169 Gigabit Ethernet" }, 167 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169S, 168 "RealTek 8169S Single-chip Gigabit Ethernet" }, 169 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169SB, 170 "RealTek 8169SB Single-chip Gigabit Ethernet" }, 171 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8110S, 172 "RealTek 8110S Single-chip Gigabit Ethernet" }, 173 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, RL_HWREV_8169S, 174 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 175 { 0, 0, 0, NULL } 176 }; 177 178 static struct rl_hwrev re_hwrevs[] = { 179 { RL_HWREV_8139, RL_8139, "" }, 180 { RL_HWREV_8139A, RL_8139, "A" }, 181 { RL_HWREV_8139AG, RL_8139, "A-G" }, 182 { RL_HWREV_8139B, RL_8139, "B" }, 183 { RL_HWREV_8130, RL_8139, "8130" }, 184 { RL_HWREV_8139C, RL_8139, "C" }, 185 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 186 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 187 { RL_HWREV_8169, RL_8169, "8169"}, 188 { RL_HWREV_8169S, RL_8169, "8169S"}, 189 { RL_HWREV_8169SB, RL_8169, "8169SB"}, 190 { RL_HWREV_8110S, RL_8169, "8110S"}, 191 { RL_HWREV_8100, RL_8139, "8100"}, 192 { RL_HWREV_8101, RL_8139, "8101"}, 193 { 0, 0, NULL } 194 }; 195 196 static int re_probe (device_t); 197 static int re_attach (device_t); 198 static int re_detach (device_t); 199 200 static int re_encap (struct rl_softc *, struct mbuf **, int *); 201 202 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 203 static void re_dma_map_desc (void *, bus_dma_segment_t *, int, 204 bus_size_t, int); 205 static int re_allocmem (device_t, struct rl_softc *); 206 static int re_newbuf (struct rl_softc *, int, struct mbuf *); 207 static int re_rx_list_init (struct rl_softc *); 208 static int re_tx_list_init (struct rl_softc *); 209 #ifdef RE_FIXUP_RX 210 static __inline void re_fixup_rx 211 (struct mbuf *); 212 #endif 213 static void re_rxeof (struct rl_softc *); 214 static void re_txeof (struct rl_softc *); 215 #ifdef DEVICE_POLLING 216 static void re_poll (struct ifnet *, enum poll_cmd, int); 217 static void re_poll_locked (struct ifnet *, enum poll_cmd, int); 218 #endif 219 static void re_intr (void *); 220 static void re_tick (void *); 221 static void re_tick_locked (struct rl_softc *); 222 static void re_start (struct ifnet *); 223 static void re_start_locked (struct ifnet *); 224 static int re_ioctl (struct ifnet *, u_long, caddr_t); 225 static void re_init (void *); 226 static void re_init_locked (struct rl_softc *); 227 static void re_stop (struct rl_softc *); 228 static void re_watchdog (struct ifnet *); 229 static int re_suspend (device_t); 230 static int re_resume (device_t); 231 static void re_shutdown (device_t); 232 static int re_ifmedia_upd (struct ifnet *); 233 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 234 235 static void re_eeprom_putbyte (struct rl_softc *, int); 236 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 237 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int, int); 238 static int re_gmii_readreg (device_t, int, int); 239 static int re_gmii_writereg (device_t, int, int, int); 240 241 static int re_miibus_readreg (device_t, int, int); 242 static int re_miibus_writereg (device_t, int, int, int); 243 static void re_miibus_statchg (device_t); 244 245 static void re_setmulti (struct rl_softc *); 246 static void re_reset (struct rl_softc *); 247 248 static int re_diag (struct rl_softc *); 249 250 #ifdef RE_USEIOSPACE 251 #define RL_RES SYS_RES_IOPORT 252 #define RL_RID RL_PCI_LOIO 253 #else 254 #define RL_RES SYS_RES_MEMORY 255 #define RL_RID RL_PCI_LOMEM 256 #endif 257 258 static device_method_t re_methods[] = { 259 /* Device interface */ 260 DEVMETHOD(device_probe, re_probe), 261 DEVMETHOD(device_attach, re_attach), 262 DEVMETHOD(device_detach, re_detach), 263 DEVMETHOD(device_suspend, re_suspend), 264 DEVMETHOD(device_resume, re_resume), 265 DEVMETHOD(device_shutdown, re_shutdown), 266 267 /* bus interface */ 268 DEVMETHOD(bus_print_child, bus_generic_print_child), 269 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 270 271 /* MII interface */ 272 DEVMETHOD(miibus_readreg, re_miibus_readreg), 273 DEVMETHOD(miibus_writereg, re_miibus_writereg), 274 DEVMETHOD(miibus_statchg, re_miibus_statchg), 275 276 { 0, 0 } 277 }; 278 279 static driver_t re_driver = { 280 "re", 281 re_methods, 282 sizeof(struct rl_softc) 283 }; 284 285 static devclass_t re_devclass; 286 287 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 288 DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0); 289 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 290 291 #define EE_SET(x) \ 292 CSR_WRITE_1(sc, RL_EECMD, \ 293 CSR_READ_1(sc, RL_EECMD) | x) 294 295 #define EE_CLR(x) \ 296 CSR_WRITE_1(sc, RL_EECMD, \ 297 CSR_READ_1(sc, RL_EECMD) & ~x) 298 299 /* 300 * Send a read command and address to the EEPROM, check for ACK. 301 */ 302 static void 303 re_eeprom_putbyte(sc, addr) 304 struct rl_softc *sc; 305 int addr; 306 { 307 register int d, i; 308 309 d = addr | sc->rl_eecmd_read; 310 311 /* 312 * Feed in each bit and strobe the clock. 313 */ 314 for (i = 0x400; i; i >>= 1) { 315 if (d & i) { 316 EE_SET(RL_EE_DATAIN); 317 } else { 318 EE_CLR(RL_EE_DATAIN); 319 } 320 DELAY(100); 321 EE_SET(RL_EE_CLK); 322 DELAY(150); 323 EE_CLR(RL_EE_CLK); 324 DELAY(100); 325 } 326 } 327 328 /* 329 * Read a word of data stored in the EEPROM at address 'addr.' 330 */ 331 static void 332 re_eeprom_getword(sc, addr, dest) 333 struct rl_softc *sc; 334 int addr; 335 u_int16_t *dest; 336 { 337 register int i; 338 u_int16_t word = 0; 339 340 /* Enter EEPROM access mode. */ 341 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 342 343 /* 344 * Send address of word we want to read. 345 */ 346 re_eeprom_putbyte(sc, addr); 347 348 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 349 350 /* 351 * Start reading bits from EEPROM. 352 */ 353 for (i = 0x8000; i; i >>= 1) { 354 EE_SET(RL_EE_CLK); 355 DELAY(100); 356 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 357 word |= i; 358 EE_CLR(RL_EE_CLK); 359 DELAY(100); 360 } 361 362 /* Turn off EEPROM access mode. */ 363 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 364 365 *dest = word; 366 } 367 368 /* 369 * Read a sequence of words from the EEPROM. 370 */ 371 static void 372 re_read_eeprom(sc, dest, off, cnt, swap) 373 struct rl_softc *sc; 374 caddr_t dest; 375 int off; 376 int cnt; 377 int swap; 378 { 379 int i; 380 u_int16_t word = 0, *ptr; 381 382 for (i = 0; i < cnt; i++) { 383 re_eeprom_getword(sc, off + i, &word); 384 ptr = (u_int16_t *)(dest + (i * 2)); 385 if (swap) 386 *ptr = ntohs(word); 387 else 388 *ptr = word; 389 } 390 } 391 392 static int 393 re_gmii_readreg(dev, phy, reg) 394 device_t dev; 395 int phy, reg; 396 { 397 struct rl_softc *sc; 398 u_int32_t rval; 399 int i; 400 401 if (phy != 1) 402 return (0); 403 404 sc = device_get_softc(dev); 405 406 /* Let the rgephy driver read the GMEDIASTAT register */ 407 408 if (reg == RL_GMEDIASTAT) { 409 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 410 return (rval); 411 } 412 413 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 414 DELAY(1000); 415 416 for (i = 0; i < RL_TIMEOUT; i++) { 417 rval = CSR_READ_4(sc, RL_PHYAR); 418 if (rval & RL_PHYAR_BUSY) 419 break; 420 DELAY(100); 421 } 422 423 if (i == RL_TIMEOUT) { 424 printf ("re%d: PHY read failed\n", sc->rl_unit); 425 return (0); 426 } 427 428 return (rval & RL_PHYAR_PHYDATA); 429 } 430 431 static int 432 re_gmii_writereg(dev, phy, reg, data) 433 device_t dev; 434 int phy, reg, data; 435 { 436 struct rl_softc *sc; 437 u_int32_t rval; 438 int i; 439 440 sc = device_get_softc(dev); 441 442 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 443 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 444 DELAY(1000); 445 446 for (i = 0; i < RL_TIMEOUT; i++) { 447 rval = CSR_READ_4(sc, RL_PHYAR); 448 if (!(rval & RL_PHYAR_BUSY)) 449 break; 450 DELAY(100); 451 } 452 453 if (i == RL_TIMEOUT) { 454 printf ("re%d: PHY write failed\n", sc->rl_unit); 455 return (0); 456 } 457 458 return (0); 459 } 460 461 static int 462 re_miibus_readreg(dev, phy, reg) 463 device_t dev; 464 int phy, reg; 465 { 466 struct rl_softc *sc; 467 u_int16_t rval = 0; 468 u_int16_t re8139_reg = 0; 469 470 sc = device_get_softc(dev); 471 472 if (sc->rl_type == RL_8169) { 473 rval = re_gmii_readreg(dev, phy, reg); 474 return (rval); 475 } 476 477 /* Pretend the internal PHY is only at address 0 */ 478 if (phy) { 479 return (0); 480 } 481 switch (reg) { 482 case MII_BMCR: 483 re8139_reg = RL_BMCR; 484 break; 485 case MII_BMSR: 486 re8139_reg = RL_BMSR; 487 break; 488 case MII_ANAR: 489 re8139_reg = RL_ANAR; 490 break; 491 case MII_ANER: 492 re8139_reg = RL_ANER; 493 break; 494 case MII_ANLPAR: 495 re8139_reg = RL_LPAR; 496 break; 497 case MII_PHYIDR1: 498 case MII_PHYIDR2: 499 return (0); 500 /* 501 * Allow the rlphy driver to read the media status 502 * register. If we have a link partner which does not 503 * support NWAY, this is the register which will tell 504 * us the results of parallel detection. 505 */ 506 case RL_MEDIASTAT: 507 rval = CSR_READ_1(sc, RL_MEDIASTAT); 508 return (rval); 509 default: 510 printf("re%d: bad phy register\n", sc->rl_unit); 511 return (0); 512 } 513 rval = CSR_READ_2(sc, re8139_reg); 514 return (rval); 515 } 516 517 static int 518 re_miibus_writereg(dev, phy, reg, data) 519 device_t dev; 520 int phy, reg, data; 521 { 522 struct rl_softc *sc; 523 u_int16_t re8139_reg = 0; 524 int rval = 0; 525 526 sc = device_get_softc(dev); 527 528 if (sc->rl_type == RL_8169) { 529 rval = re_gmii_writereg(dev, phy, reg, data); 530 return (rval); 531 } 532 533 /* Pretend the internal PHY is only at address 0 */ 534 if (phy) 535 return (0); 536 537 switch (reg) { 538 case MII_BMCR: 539 re8139_reg = RL_BMCR; 540 break; 541 case MII_BMSR: 542 re8139_reg = RL_BMSR; 543 break; 544 case MII_ANAR: 545 re8139_reg = RL_ANAR; 546 break; 547 case MII_ANER: 548 re8139_reg = RL_ANER; 549 break; 550 case MII_ANLPAR: 551 re8139_reg = RL_LPAR; 552 break; 553 case MII_PHYIDR1: 554 case MII_PHYIDR2: 555 return (0); 556 break; 557 default: 558 printf("re%d: bad phy register\n", sc->rl_unit); 559 return (0); 560 } 561 CSR_WRITE_2(sc, re8139_reg, data); 562 return (0); 563 } 564 565 static void 566 re_miibus_statchg(dev) 567 device_t dev; 568 { 569 570 } 571 572 /* 573 * Program the 64-bit multicast hash filter. 574 */ 575 static void 576 re_setmulti(sc) 577 struct rl_softc *sc; 578 { 579 struct ifnet *ifp; 580 int h = 0; 581 u_int32_t hashes[2] = { 0, 0 }; 582 struct ifmultiaddr *ifma; 583 u_int32_t rxfilt; 584 int mcnt = 0; 585 586 RL_LOCK_ASSERT(sc); 587 588 ifp = &sc->arpcom.ac_if; 589 590 rxfilt = CSR_READ_4(sc, RL_RXCFG); 591 592 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 593 rxfilt |= RL_RXCFG_RX_MULTI; 594 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 595 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 596 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 597 return; 598 } 599 600 /* first, zot all the existing hash bits */ 601 CSR_WRITE_4(sc, RL_MAR0, 0); 602 CSR_WRITE_4(sc, RL_MAR4, 0); 603 604 /* now program new ones */ 605 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 606 if (ifma->ifma_addr->sa_family != AF_LINK) 607 continue; 608 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 609 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 610 if (h < 32) 611 hashes[0] |= (1 << h); 612 else 613 hashes[1] |= (1 << (h - 32)); 614 mcnt++; 615 } 616 617 if (mcnt) 618 rxfilt |= RL_RXCFG_RX_MULTI; 619 else 620 rxfilt &= ~RL_RXCFG_RX_MULTI; 621 622 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 623 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 624 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 625 } 626 627 static void 628 re_reset(sc) 629 struct rl_softc *sc; 630 { 631 register int i; 632 633 RL_LOCK_ASSERT(sc); 634 635 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 636 637 for (i = 0; i < RL_TIMEOUT; i++) { 638 DELAY(10); 639 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 640 break; 641 } 642 if (i == RL_TIMEOUT) 643 printf("re%d: reset never completed!\n", sc->rl_unit); 644 645 CSR_WRITE_1(sc, 0x82, 1); 646 } 647 648 /* 649 * The following routine is designed to test for a defect on some 650 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 651 * lines connected to the bus, however for a 32-bit only card, they 652 * should be pulled high. The result of this defect is that the 653 * NIC will not work right if you plug it into a 64-bit slot: DMA 654 * operations will be done with 64-bit transfers, which will fail 655 * because the 64-bit data lines aren't connected. 656 * 657 * There's no way to work around this (short of talking a soldering 658 * iron to the board), however we can detect it. The method we use 659 * here is to put the NIC into digital loopback mode, set the receiver 660 * to promiscuous mode, and then try to send a frame. We then compare 661 * the frame data we sent to what was received. If the data matches, 662 * then the NIC is working correctly, otherwise we know the user has 663 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 664 * slot. In the latter case, there's no way the NIC can work correctly, 665 * so we print out a message on the console and abort the device attach. 666 */ 667 668 static int 669 re_diag(sc) 670 struct rl_softc *sc; 671 { 672 struct ifnet *ifp = &sc->arpcom.ac_if; 673 struct mbuf *m0; 674 struct ether_header *eh; 675 struct rl_desc *cur_rx; 676 u_int16_t status; 677 u_int32_t rxstat; 678 int total_len, i, error = 0; 679 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 680 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 681 682 /* Allocate a single mbuf */ 683 MGETHDR(m0, M_DONTWAIT, MT_DATA); 684 if (m0 == NULL) 685 return (ENOBUFS); 686 687 RL_LOCK(sc); 688 689 /* 690 * Initialize the NIC in test mode. This sets the chip up 691 * so that it can send and receive frames, but performs the 692 * following special functions: 693 * - Puts receiver in promiscuous mode 694 * - Enables digital loopback mode 695 * - Leaves interrupts turned off 696 */ 697 698 ifp->if_flags |= IFF_PROMISC; 699 sc->rl_testmode = 1; 700 re_init_locked(sc); 701 re_stop(sc); 702 DELAY(100000); 703 re_init_locked(sc); 704 705 /* Put some data in the mbuf */ 706 707 eh = mtod(m0, struct ether_header *); 708 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 709 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 710 eh->ether_type = htons(ETHERTYPE_IP); 711 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 712 713 /* 714 * Queue the packet, start transmission. 715 * Note: IF_HANDOFF() ultimately calls re_start() for us. 716 */ 717 718 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 719 RL_UNLOCK(sc); 720 /* XXX: re_diag must not be called when in ALTQ mode */ 721 IF_HANDOFF(&ifp->if_snd, m0, ifp); 722 RL_LOCK(sc); 723 m0 = NULL; 724 725 /* Wait for it to propagate through the chip */ 726 727 DELAY(100000); 728 for (i = 0; i < RL_TIMEOUT; i++) { 729 status = CSR_READ_2(sc, RL_ISR); 730 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 731 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 732 break; 733 DELAY(10); 734 } 735 736 if (i == RL_TIMEOUT) { 737 printf("re%d: diagnostic failed, failed to receive packet " 738 "in loopback mode\n", sc->rl_unit); 739 error = EIO; 740 goto done; 741 } 742 743 /* 744 * The packet should have been dumped into the first 745 * entry in the RX DMA ring. Grab it from there. 746 */ 747 748 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 749 sc->rl_ldata.rl_rx_list_map, 750 BUS_DMASYNC_POSTREAD); 751 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 752 sc->rl_ldata.rl_rx_dmamap[0], 753 BUS_DMASYNC_POSTWRITE); 754 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 755 sc->rl_ldata.rl_rx_dmamap[0]); 756 757 m0 = sc->rl_ldata.rl_rx_mbuf[0]; 758 sc->rl_ldata.rl_rx_mbuf[0] = NULL; 759 eh = mtod(m0, struct ether_header *); 760 761 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 762 total_len = RL_RXBYTES(cur_rx); 763 rxstat = le32toh(cur_rx->rl_cmdstat); 764 765 if (total_len != ETHER_MIN_LEN) { 766 printf("re%d: diagnostic failed, received short packet\n", 767 sc->rl_unit); 768 error = EIO; 769 goto done; 770 } 771 772 /* Test that the received packet data matches what we sent. */ 773 774 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 775 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 776 ntohs(eh->ether_type) != ETHERTYPE_IP) { 777 printf("re%d: WARNING, DMA FAILURE!\n", sc->rl_unit); 778 printf("re%d: expected TX data: %6D/%6D/0x%x\n", sc->rl_unit, 779 dst, ":", src, ":", ETHERTYPE_IP); 780 printf("re%d: received RX data: %6D/%6D/0x%x\n", sc->rl_unit, 781 eh->ether_dhost, ":", eh->ether_shost, ":", 782 ntohs(eh->ether_type)); 783 printf("re%d: You may have a defective 32-bit NIC plugged " 784 "into a 64-bit PCI slot.\n", sc->rl_unit); 785 printf("re%d: Please re-install the NIC in a 32-bit slot " 786 "for proper operation.\n", sc->rl_unit); 787 printf("re%d: Read the re(4) man page for more details.\n", 788 sc->rl_unit); 789 error = EIO; 790 } 791 792 done: 793 /* Turn interface off, release resources */ 794 795 sc->rl_testmode = 0; 796 ifp->if_flags &= ~IFF_PROMISC; 797 re_stop(sc); 798 if (m0 != NULL) 799 m_freem(m0); 800 801 RL_UNLOCK(sc); 802 803 return (error); 804 } 805 806 /* 807 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 808 * IDs against our list and return a device name if we find a match. 809 */ 810 static int 811 re_probe(dev) 812 device_t dev; 813 { 814 struct rl_type *t; 815 struct rl_softc *sc; 816 int rid; 817 u_int32_t hwrev; 818 819 t = re_devs; 820 sc = device_get_softc(dev); 821 822 while (t->rl_name != NULL) { 823 if ((pci_get_vendor(dev) == t->rl_vid) && 824 (pci_get_device(dev) == t->rl_did)) { 825 826 /* 827 * Temporarily map the I/O space 828 * so we can read the chip ID register. 829 */ 830 rid = RL_RID; 831 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 832 RF_ACTIVE); 833 if (sc->rl_res == NULL) { 834 device_printf(dev, 835 "couldn't map ports/memory\n"); 836 return (ENXIO); 837 } 838 sc->rl_btag = rman_get_bustag(sc->rl_res); 839 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 840 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 841 bus_release_resource(dev, RL_RES, 842 RL_RID, sc->rl_res); 843 if (t->rl_basetype == hwrev) { 844 device_set_desc(dev, t->rl_name); 845 return (BUS_PROBE_DEFAULT); 846 } 847 } 848 t++; 849 } 850 851 return (ENXIO); 852 } 853 854 /* 855 * This routine takes the segment list provided as the result of 856 * a bus_dma_map_load() operation and assigns the addresses/lengths 857 * to RealTek DMA descriptors. This can be called either by the RX 858 * code or the TX code. In the RX case, we'll probably wind up mapping 859 * at most one segment. For the TX case, there could be any number of 860 * segments since TX packets may span multiple mbufs. In either case, 861 * if the number of segments is larger than the rl_maxsegs limit 862 * specified by the caller, we abort the mapping operation. Sadly, 863 * whoever designed the buffer mapping API did not provide a way to 864 * return an error from here, so we have to fake it a bit. 865 */ 866 867 static void 868 re_dma_map_desc(arg, segs, nseg, mapsize, error) 869 void *arg; 870 bus_dma_segment_t *segs; 871 int nseg; 872 bus_size_t mapsize; 873 int error; 874 { 875 struct rl_dmaload_arg *ctx; 876 struct rl_desc *d = NULL; 877 int i = 0, idx; 878 879 if (error) 880 return; 881 882 ctx = arg; 883 884 /* Signal error to caller if there's too many segments */ 885 if (nseg > ctx->rl_maxsegs) { 886 ctx->rl_maxsegs = 0; 887 return; 888 } 889 890 /* 891 * Map the segment array into descriptors. Note that we set the 892 * start-of-frame and end-of-frame markers for either TX or RX, but 893 * they really only have meaning in the TX case. (In the RX case, 894 * it's the chip that tells us where packets begin and end.) 895 * We also keep track of the end of the ring and set the 896 * end-of-ring bits as needed, and we set the ownership bits 897 * in all except the very first descriptor. (The caller will 898 * set this descriptor later when it start transmission or 899 * reception.) 900 */ 901 idx = ctx->rl_idx; 902 for (;;) { 903 u_int32_t cmdstat; 904 d = &ctx->rl_ring[idx]; 905 if (le32toh(d->rl_cmdstat) & RL_RDESC_STAT_OWN) { 906 ctx->rl_maxsegs = 0; 907 return; 908 } 909 cmdstat = segs[i].ds_len; 910 d->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 911 d->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 912 if (i == 0) 913 cmdstat |= RL_TDESC_CMD_SOF; 914 else 915 cmdstat |= RL_TDESC_CMD_OWN; 916 if (idx == (RL_RX_DESC_CNT - 1)) 917 cmdstat |= RL_TDESC_CMD_EOR; 918 d->rl_cmdstat = htole32(cmdstat | ctx->rl_flags); 919 i++; 920 if (i == nseg) 921 break; 922 RL_DESC_INC(idx); 923 } 924 925 d->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 926 ctx->rl_maxsegs = nseg; 927 ctx->rl_idx = idx; 928 } 929 930 /* 931 * Map a single buffer address. 932 */ 933 934 static void 935 re_dma_map_addr(arg, segs, nseg, error) 936 void *arg; 937 bus_dma_segment_t *segs; 938 int nseg; 939 int error; 940 { 941 u_int32_t *addr; 942 943 if (error) 944 return; 945 946 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 947 addr = arg; 948 *addr = segs->ds_addr; 949 } 950 951 static int 952 re_allocmem(dev, sc) 953 device_t dev; 954 struct rl_softc *sc; 955 { 956 int error; 957 int nseg; 958 int i; 959 960 /* 961 * Allocate map for RX mbufs. 962 */ 963 nseg = 32; 964 error = bus_dma_tag_create(sc->rl_parent_tag, ETHER_ALIGN, 0, 965 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 966 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 967 NULL, NULL, &sc->rl_ldata.rl_mtag); 968 if (error) { 969 device_printf(dev, "could not allocate dma tag\n"); 970 return (ENOMEM); 971 } 972 973 /* 974 * Allocate map for TX descriptor list. 975 */ 976 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 977 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 978 NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 979 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 980 if (error) { 981 device_printf(dev, "could not allocate dma tag\n"); 982 return (ENOMEM); 983 } 984 985 /* Allocate DMA'able memory for the TX ring */ 986 987 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 988 (void **)&sc->rl_ldata.rl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 989 &sc->rl_ldata.rl_tx_list_map); 990 if (error) 991 return (ENOMEM); 992 993 /* Load the map for the TX ring. */ 994 995 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 996 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 997 RL_TX_LIST_SZ, re_dma_map_addr, 998 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 999 1000 /* Create DMA maps for TX buffers */ 1001 1002 for (i = 0; i < RL_TX_DESC_CNT; i++) { 1003 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1004 &sc->rl_ldata.rl_tx_dmamap[i]); 1005 if (error) { 1006 device_printf(dev, "can't create DMA map for TX\n"); 1007 return (ENOMEM); 1008 } 1009 } 1010 1011 /* 1012 * Allocate map for RX descriptor list. 1013 */ 1014 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1015 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1016 NULL, RL_RX_LIST_SZ, 1, RL_RX_LIST_SZ, BUS_DMA_ALLOCNOW, 1017 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1018 if (error) { 1019 device_printf(dev, "could not allocate dma tag\n"); 1020 return (ENOMEM); 1021 } 1022 1023 /* Allocate DMA'able memory for the RX ring */ 1024 1025 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1026 (void **)&sc->rl_ldata.rl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1027 &sc->rl_ldata.rl_rx_list_map); 1028 if (error) 1029 return (ENOMEM); 1030 1031 /* Load the map for the RX ring. */ 1032 1033 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1034 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1035 RL_RX_LIST_SZ, re_dma_map_addr, 1036 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1037 1038 /* Create DMA maps for RX buffers */ 1039 1040 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1041 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1042 &sc->rl_ldata.rl_rx_dmamap[i]); 1043 if (error) { 1044 device_printf(dev, "can't create DMA map for RX\n"); 1045 return (ENOMEM); 1046 } 1047 } 1048 1049 return (0); 1050 } 1051 1052 /* 1053 * Attach the interface. Allocate softc structures, do ifmedia 1054 * setup and ethernet/BPF attach. 1055 */ 1056 static int 1057 re_attach(dev) 1058 device_t dev; 1059 { 1060 u_char eaddr[ETHER_ADDR_LEN]; 1061 u_int16_t as[3]; 1062 struct rl_softc *sc; 1063 struct ifnet *ifp; 1064 struct rl_hwrev *hw_rev; 1065 int hwrev; 1066 u_int16_t re_did = 0; 1067 int unit, error = 0, rid, i; 1068 1069 sc = device_get_softc(dev); 1070 unit = device_get_unit(dev); 1071 1072 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1073 MTX_DEF); 1074 /* 1075 * Map control/status registers. 1076 */ 1077 pci_enable_busmaster(dev); 1078 1079 rid = RL_RID; 1080 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 1081 RF_ACTIVE); 1082 1083 if (sc->rl_res == NULL) { 1084 printf ("re%d: couldn't map ports/memory\n", unit); 1085 error = ENXIO; 1086 goto fail; 1087 } 1088 1089 sc->rl_btag = rman_get_bustag(sc->rl_res); 1090 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1091 1092 /* Allocate interrupt */ 1093 rid = 0; 1094 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1095 RF_SHAREABLE | RF_ACTIVE); 1096 1097 if (sc->rl_irq == NULL) { 1098 printf("re%d: couldn't map interrupt\n", unit); 1099 error = ENXIO; 1100 goto fail; 1101 } 1102 1103 /* Reset the adapter. */ 1104 RL_LOCK(sc); 1105 re_reset(sc); 1106 RL_UNLOCK(sc); 1107 1108 hw_rev = re_hwrevs; 1109 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 1110 while (hw_rev->rl_desc != NULL) { 1111 if (hw_rev->rl_rev == hwrev) { 1112 sc->rl_type = hw_rev->rl_type; 1113 break; 1114 } 1115 hw_rev++; 1116 } 1117 1118 if (sc->rl_type == RL_8169) { 1119 1120 /* Set RX length mask */ 1121 1122 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1123 1124 /* Force station address autoload from the EEPROM */ 1125 1126 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_AUTOLOAD); 1127 for (i = 0; i < RL_TIMEOUT; i++) { 1128 if (!(CSR_READ_1(sc, RL_EECMD) & RL_EEMODE_AUTOLOAD)) 1129 break; 1130 DELAY(100); 1131 } 1132 if (i == RL_TIMEOUT) 1133 printf ("re%d: eeprom autoload timed out\n", unit); 1134 1135 for (i = 0; i < ETHER_ADDR_LEN; i++) 1136 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1137 } else { 1138 1139 /* Set RX length mask */ 1140 1141 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1142 1143 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 1144 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1, 0); 1145 if (re_did != 0x8129) 1146 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 1147 1148 /* 1149 * Get station address from the EEPROM. 1150 */ 1151 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0); 1152 for (i = 0; i < 3; i++) { 1153 eaddr[(i * 2) + 0] = as[i] & 0xff; 1154 eaddr[(i * 2) + 1] = as[i] >> 8; 1155 } 1156 } 1157 1158 sc->rl_unit = unit; 1159 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1160 1161 /* 1162 * Allocate the parent bus DMA tag appropriate for PCI. 1163 */ 1164 #define RL_NSEG_NEW 32 1165 error = bus_dma_tag_create(NULL, /* parent */ 1166 1, 0, /* alignment, boundary */ 1167 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1168 BUS_SPACE_MAXADDR, /* highaddr */ 1169 NULL, NULL, /* filter, filterarg */ 1170 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 1171 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1172 BUS_DMA_ALLOCNOW, /* flags */ 1173 NULL, NULL, /* lockfunc, lockarg */ 1174 &sc->rl_parent_tag); 1175 if (error) 1176 goto fail; 1177 1178 error = re_allocmem(dev, sc); 1179 1180 if (error) 1181 goto fail; 1182 1183 /* Do MII setup */ 1184 if (mii_phy_probe(dev, &sc->rl_miibus, 1185 re_ifmedia_upd, re_ifmedia_sts)) { 1186 printf("re%d: MII without any phy!\n", sc->rl_unit); 1187 error = ENXIO; 1188 goto fail; 1189 } 1190 1191 ifp = &sc->arpcom.ac_if; 1192 ifp->if_softc = sc; 1193 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1194 ifp->if_mtu = ETHERMTU; 1195 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1196 ifp->if_ioctl = re_ioctl; 1197 ifp->if_capabilities = IFCAP_VLAN_MTU; 1198 ifp->if_start = re_start; 1199 ifp->if_hwassist = /*RE_CSUM_FEATURES*/0; 1200 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1201 #ifdef DEVICE_POLLING 1202 ifp->if_capabilities |= IFCAP_POLLING; 1203 #endif 1204 ifp->if_watchdog = re_watchdog; 1205 ifp->if_init = re_init; 1206 if (sc->rl_type == RL_8169) 1207 ifp->if_baudrate = 1000000000; 1208 else 1209 ifp->if_baudrate = 100000000; 1210 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1211 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1212 IFQ_SET_READY(&ifp->if_snd); 1213 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM; 1214 1215 callout_handle_init(&sc->rl_stat_ch); 1216 1217 /* 1218 * Call MI attach routine. 1219 */ 1220 ether_ifattach(ifp, eaddr); 1221 1222 /* Perform hardware diagnostic. */ 1223 error = re_diag(sc); 1224 1225 if (error) { 1226 printf("re%d: attach aborted due to hardware diag failure\n", 1227 unit); 1228 ether_ifdetach(ifp); 1229 goto fail; 1230 } 1231 1232 /* Hook interrupt last to avoid having to lock softc */ 1233 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET | INTR_MPSAFE, 1234 re_intr, sc, &sc->rl_intrhand); 1235 if (error) { 1236 printf("re%d: couldn't set up irq\n", unit); 1237 ether_ifdetach(ifp); 1238 } 1239 1240 fail: 1241 if (error) 1242 re_detach(dev); 1243 1244 return (error); 1245 } 1246 1247 /* 1248 * Shutdown hardware and free up resources. This can be called any 1249 * time after the mutex has been initialized. It is called in both 1250 * the error case in attach and the normal detach case so it needs 1251 * to be careful about only freeing resources that have actually been 1252 * allocated. 1253 */ 1254 static int 1255 re_detach(dev) 1256 device_t dev; 1257 { 1258 struct rl_softc *sc; 1259 struct ifnet *ifp; 1260 int i; 1261 int attached; 1262 1263 sc = device_get_softc(dev); 1264 ifp = &sc->arpcom.ac_if; 1265 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1266 1267 attached = device_is_attached(dev); 1268 /* These should only be active if attach succeeded */ 1269 if (attached) 1270 ether_ifdetach(ifp); 1271 1272 RL_LOCK(sc); 1273 #if 0 1274 sc->suspended = 1; 1275 #endif 1276 1277 /* These should only be active if attach succeeded */ 1278 if (attached) { 1279 re_stop(sc); 1280 /* 1281 * Force off the IFF_UP flag here, in case someone 1282 * still had a BPF descriptor attached to this 1283 * interface. If they do, ether_ifdetach() will cause 1284 * the BPF code to try and clear the promisc mode 1285 * flag, which will bubble down to re_ioctl(), 1286 * which will try to call re_init() again. This will 1287 * turn the NIC back on and restart the MII ticker, 1288 * which will panic the system when the kernel tries 1289 * to invoke the re_tick() function that isn't there 1290 * anymore. 1291 */ 1292 ifp->if_flags &= ~IFF_UP; 1293 } 1294 if (sc->rl_miibus) 1295 device_delete_child(dev, sc->rl_miibus); 1296 bus_generic_detach(dev); 1297 1298 /* 1299 * The rest is resource deallocation, so we should already be 1300 * stopped here. 1301 */ 1302 RL_UNLOCK(sc); 1303 1304 if (sc->rl_intrhand) 1305 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1306 if (sc->rl_irq) 1307 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1308 if (sc->rl_res) 1309 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1310 1311 1312 /* Unload and free the RX DMA ring memory and map */ 1313 1314 if (sc->rl_ldata.rl_rx_list_tag) { 1315 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1316 sc->rl_ldata.rl_rx_list_map); 1317 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1318 sc->rl_ldata.rl_rx_list, 1319 sc->rl_ldata.rl_rx_list_map); 1320 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1321 } 1322 1323 /* Unload and free the TX DMA ring memory and map */ 1324 1325 if (sc->rl_ldata.rl_tx_list_tag) { 1326 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1327 sc->rl_ldata.rl_tx_list_map); 1328 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1329 sc->rl_ldata.rl_tx_list, 1330 sc->rl_ldata.rl_tx_list_map); 1331 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1332 } 1333 1334 /* Destroy all the RX and TX buffer maps */ 1335 1336 if (sc->rl_ldata.rl_mtag) { 1337 for (i = 0; i < RL_TX_DESC_CNT; i++) 1338 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1339 sc->rl_ldata.rl_tx_dmamap[i]); 1340 for (i = 0; i < RL_RX_DESC_CNT; i++) 1341 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1342 sc->rl_ldata.rl_rx_dmamap[i]); 1343 bus_dma_tag_destroy(sc->rl_ldata.rl_mtag); 1344 } 1345 1346 /* Unload and free the stats buffer and map */ 1347 1348 if (sc->rl_ldata.rl_stag) { 1349 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1350 sc->rl_ldata.rl_rx_list_map); 1351 bus_dmamem_free(sc->rl_ldata.rl_stag, 1352 sc->rl_ldata.rl_stats, 1353 sc->rl_ldata.rl_smap); 1354 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1355 } 1356 1357 if (sc->rl_parent_tag) 1358 bus_dma_tag_destroy(sc->rl_parent_tag); 1359 1360 mtx_destroy(&sc->rl_mtx); 1361 1362 return (0); 1363 } 1364 1365 static int 1366 re_newbuf(sc, idx, m) 1367 struct rl_softc *sc; 1368 int idx; 1369 struct mbuf *m; 1370 { 1371 struct rl_dmaload_arg arg; 1372 struct mbuf *n = NULL; 1373 int error; 1374 1375 if (m == NULL) { 1376 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1377 if (n == NULL) 1378 return (ENOBUFS); 1379 m = n; 1380 } else 1381 m->m_data = m->m_ext.ext_buf; 1382 1383 m->m_len = m->m_pkthdr.len = MCLBYTES; 1384 #ifdef RE_FIXUP_RX 1385 /* 1386 * This is part of an evil trick to deal with non-x86 platforms. 1387 * The RealTek chip requires RX buffers to be aligned on 64-bit 1388 * boundaries, but that will hose non-x86 machines. To get around 1389 * this, we leave some empty space at the start of each buffer 1390 * and for non-x86 hosts, we copy the buffer back six bytes 1391 * to achieve word alignment. This is slightly more efficient 1392 * than allocating a new buffer, copying the contents, and 1393 * discarding the old buffer. 1394 */ 1395 m_adj(m, RE_ETHER_ALIGN); 1396 #endif 1397 arg.sc = sc; 1398 arg.rl_idx = idx; 1399 arg.rl_maxsegs = 1; 1400 arg.rl_flags = 0; 1401 arg.rl_ring = sc->rl_ldata.rl_rx_list; 1402 1403 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, 1404 sc->rl_ldata.rl_rx_dmamap[idx], m, re_dma_map_desc, 1405 &arg, BUS_DMA_NOWAIT); 1406 if (error || arg.rl_maxsegs != 1) { 1407 if (n != NULL) 1408 m_freem(n); 1409 return (ENOMEM); 1410 } 1411 1412 sc->rl_ldata.rl_rx_list[idx].rl_cmdstat |= htole32(RL_RDESC_CMD_OWN); 1413 sc->rl_ldata.rl_rx_mbuf[idx] = m; 1414 1415 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1416 sc->rl_ldata.rl_rx_dmamap[idx], 1417 BUS_DMASYNC_PREREAD); 1418 1419 return (0); 1420 } 1421 1422 #ifdef RE_FIXUP_RX 1423 static __inline void 1424 re_fixup_rx(m) 1425 struct mbuf *m; 1426 { 1427 int i; 1428 uint16_t *src, *dst; 1429 1430 src = mtod(m, uint16_t *); 1431 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1432 1433 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1434 *dst++ = *src++; 1435 1436 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1437 1438 return; 1439 } 1440 #endif 1441 1442 static int 1443 re_tx_list_init(sc) 1444 struct rl_softc *sc; 1445 { 1446 1447 RL_LOCK_ASSERT(sc); 1448 1449 bzero ((char *)sc->rl_ldata.rl_tx_list, RL_TX_LIST_SZ); 1450 bzero ((char *)&sc->rl_ldata.rl_tx_mbuf, 1451 (RL_TX_DESC_CNT * sizeof(struct mbuf *))); 1452 1453 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1454 sc->rl_ldata.rl_tx_list_map, BUS_DMASYNC_PREWRITE); 1455 sc->rl_ldata.rl_tx_prodidx = 0; 1456 sc->rl_ldata.rl_tx_considx = 0; 1457 sc->rl_ldata.rl_tx_free = RL_TX_DESC_CNT; 1458 1459 return (0); 1460 } 1461 1462 static int 1463 re_rx_list_init(sc) 1464 struct rl_softc *sc; 1465 { 1466 int i; 1467 1468 bzero ((char *)sc->rl_ldata.rl_rx_list, RL_RX_LIST_SZ); 1469 bzero ((char *)&sc->rl_ldata.rl_rx_mbuf, 1470 (RL_RX_DESC_CNT * sizeof(struct mbuf *))); 1471 1472 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1473 if (re_newbuf(sc, i, NULL) == ENOBUFS) 1474 return (ENOBUFS); 1475 } 1476 1477 /* Flush the RX descriptors */ 1478 1479 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1480 sc->rl_ldata.rl_rx_list_map, 1481 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1482 1483 sc->rl_ldata.rl_rx_prodidx = 0; 1484 sc->rl_head = sc->rl_tail = NULL; 1485 1486 return (0); 1487 } 1488 1489 /* 1490 * RX handler for C+ and 8169. For the gigE chips, we support 1491 * the reception of jumbo frames that have been fragmented 1492 * across multiple 2K mbuf cluster buffers. 1493 */ 1494 static void 1495 re_rxeof(sc) 1496 struct rl_softc *sc; 1497 { 1498 struct mbuf *m; 1499 struct ifnet *ifp; 1500 int i, total_len; 1501 struct rl_desc *cur_rx; 1502 u_int32_t rxstat, rxvlan; 1503 1504 RL_LOCK_ASSERT(sc); 1505 1506 ifp = &sc->arpcom.ac_if; 1507 i = sc->rl_ldata.rl_rx_prodidx; 1508 1509 /* Invalidate the descriptor memory */ 1510 1511 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1512 sc->rl_ldata.rl_rx_list_map, 1513 BUS_DMASYNC_POSTREAD); 1514 1515 while (!RL_OWN(&sc->rl_ldata.rl_rx_list[i])) { 1516 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1517 m = sc->rl_ldata.rl_rx_mbuf[i]; 1518 total_len = RL_RXBYTES(cur_rx); 1519 rxstat = le32toh(cur_rx->rl_cmdstat); 1520 rxvlan = le32toh(cur_rx->rl_vlanctl); 1521 1522 /* Invalidate the RX mbuf and unload its map */ 1523 1524 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1525 sc->rl_ldata.rl_rx_dmamap[i], 1526 BUS_DMASYNC_POSTWRITE); 1527 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1528 sc->rl_ldata.rl_rx_dmamap[i]); 1529 1530 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1531 m->m_len = RE_RX_DESC_BUFLEN; 1532 if (sc->rl_head == NULL) 1533 sc->rl_head = sc->rl_tail = m; 1534 else { 1535 m->m_flags &= ~M_PKTHDR; 1536 sc->rl_tail->m_next = m; 1537 sc->rl_tail = m; 1538 } 1539 re_newbuf(sc, i, NULL); 1540 RL_DESC_INC(i); 1541 continue; 1542 } 1543 1544 /* 1545 * NOTE: for the 8139C+, the frame length field 1546 * is always 12 bits in size, but for the gigE chips, 1547 * it is 13 bits (since the max RX frame length is 16K). 1548 * Unfortunately, all 32 bits in the status word 1549 * were already used, so to make room for the extra 1550 * length bit, RealTek took out the 'frame alignment 1551 * error' bit and shifted the other status bits 1552 * over one slot. The OWN, EOR, FS and LS bits are 1553 * still in the same places. We have already extracted 1554 * the frame length and checked the OWN bit, so rather 1555 * than using an alternate bit mapping, we shift the 1556 * status bits one space to the right so we can evaluate 1557 * them using the 8169 status as though it was in the 1558 * same format as that of the 8139C+. 1559 */ 1560 if (sc->rl_type == RL_8169) 1561 rxstat >>= 1; 1562 1563 /* 1564 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 1565 * set, but if CRC is clear, it will still be a valid frame. 1566 */ 1567 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 && 1568 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) { 1569 ifp->if_ierrors++; 1570 /* 1571 * If this is part of a multi-fragment packet, 1572 * discard all the pieces. 1573 */ 1574 if (sc->rl_head != NULL) { 1575 m_freem(sc->rl_head); 1576 sc->rl_head = sc->rl_tail = NULL; 1577 } 1578 re_newbuf(sc, i, m); 1579 RL_DESC_INC(i); 1580 continue; 1581 } 1582 1583 /* 1584 * If allocating a replacement mbuf fails, 1585 * reload the current one. 1586 */ 1587 1588 if (re_newbuf(sc, i, NULL)) { 1589 ifp->if_ierrors++; 1590 if (sc->rl_head != NULL) { 1591 m_freem(sc->rl_head); 1592 sc->rl_head = sc->rl_tail = NULL; 1593 } 1594 re_newbuf(sc, i, m); 1595 RL_DESC_INC(i); 1596 continue; 1597 } 1598 1599 RL_DESC_INC(i); 1600 1601 if (sc->rl_head != NULL) { 1602 m->m_len = total_len % RE_RX_DESC_BUFLEN; 1603 if (m->m_len == 0) 1604 m->m_len = RE_RX_DESC_BUFLEN; 1605 /* 1606 * Special case: if there's 4 bytes or less 1607 * in this buffer, the mbuf can be discarded: 1608 * the last 4 bytes is the CRC, which we don't 1609 * care about anyway. 1610 */ 1611 if (m->m_len <= ETHER_CRC_LEN) { 1612 sc->rl_tail->m_len -= 1613 (ETHER_CRC_LEN - m->m_len); 1614 m_freem(m); 1615 } else { 1616 m->m_len -= ETHER_CRC_LEN; 1617 m->m_flags &= ~M_PKTHDR; 1618 sc->rl_tail->m_next = m; 1619 } 1620 m = sc->rl_head; 1621 sc->rl_head = sc->rl_tail = NULL; 1622 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1623 } else 1624 m->m_pkthdr.len = m->m_len = 1625 (total_len - ETHER_CRC_LEN); 1626 1627 #ifdef RE_FIXUP_RX 1628 re_fixup_rx(m); 1629 #endif 1630 ifp->if_ipackets++; 1631 m->m_pkthdr.rcvif = ifp; 1632 1633 /* Do RX checksumming if enabled */ 1634 1635 if (ifp->if_capenable & IFCAP_RXCSUM) { 1636 1637 /* Check IP header checksum */ 1638 if (rxstat & RL_RDESC_STAT_PROTOID) 1639 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1640 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1641 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1642 1643 /* Check TCP/UDP checksum */ 1644 if ((RL_TCPPKT(rxstat) && 1645 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1646 (RL_UDPPKT(rxstat) && 1647 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1648 m->m_pkthdr.csum_flags |= 1649 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1650 m->m_pkthdr.csum_data = 0xffff; 1651 } 1652 } 1653 1654 if (rxvlan & RL_RDESC_VLANCTL_TAG) 1655 VLAN_INPUT_TAG(ifp, m, 1656 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)), continue); 1657 RL_UNLOCK(sc); 1658 (*ifp->if_input)(ifp, m); 1659 RL_LOCK(sc); 1660 } 1661 1662 /* Flush the RX DMA ring */ 1663 1664 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1665 sc->rl_ldata.rl_rx_list_map, 1666 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1667 1668 sc->rl_ldata.rl_rx_prodidx = i; 1669 } 1670 1671 static void 1672 re_txeof(sc) 1673 struct rl_softc *sc; 1674 { 1675 struct ifnet *ifp; 1676 u_int32_t txstat; 1677 int idx; 1678 1679 ifp = &sc->arpcom.ac_if; 1680 idx = sc->rl_ldata.rl_tx_considx; 1681 1682 /* Invalidate the TX descriptor list */ 1683 1684 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1685 sc->rl_ldata.rl_tx_list_map, 1686 BUS_DMASYNC_POSTREAD); 1687 1688 while (idx != sc->rl_ldata.rl_tx_prodidx) { 1689 1690 txstat = le32toh(sc->rl_ldata.rl_tx_list[idx].rl_cmdstat); 1691 if (txstat & RL_TDESC_CMD_OWN) 1692 break; 1693 1694 /* 1695 * We only stash mbufs in the last descriptor 1696 * in a fragment chain, which also happens to 1697 * be the only place where the TX status bits 1698 * are valid. 1699 */ 1700 1701 if (txstat & RL_TDESC_CMD_EOF) { 1702 m_freem(sc->rl_ldata.rl_tx_mbuf[idx]); 1703 sc->rl_ldata.rl_tx_mbuf[idx] = NULL; 1704 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1705 sc->rl_ldata.rl_tx_dmamap[idx]); 1706 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 1707 RL_TDESC_STAT_COLCNT)) 1708 ifp->if_collisions++; 1709 if (txstat & RL_TDESC_STAT_TXERRSUM) 1710 ifp->if_oerrors++; 1711 else 1712 ifp->if_opackets++; 1713 } 1714 sc->rl_ldata.rl_tx_free++; 1715 RL_DESC_INC(idx); 1716 } 1717 1718 /* No changes made to the TX ring, so no flush needed */ 1719 1720 if (idx != sc->rl_ldata.rl_tx_considx) { 1721 sc->rl_ldata.rl_tx_considx = idx; 1722 ifp->if_flags &= ~IFF_OACTIVE; 1723 ifp->if_timer = 0; 1724 } 1725 1726 /* 1727 * If not all descriptors have been released reaped yet, 1728 * reload the timer so that we will eventually get another 1729 * interrupt that will cause us to re-enter this routine. 1730 * This is done in case the transmitter has gone idle. 1731 */ 1732 if (sc->rl_ldata.rl_tx_free != RL_TX_DESC_CNT) 1733 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 1734 } 1735 1736 static void 1737 re_tick(xsc) 1738 void *xsc; 1739 { 1740 struct rl_softc *sc; 1741 1742 sc = xsc; 1743 RL_LOCK(sc); 1744 re_tick_locked(sc); 1745 RL_UNLOCK(sc); 1746 } 1747 1748 static void 1749 re_tick_locked(sc) 1750 struct rl_softc *sc; 1751 { 1752 struct mii_data *mii; 1753 1754 RL_LOCK_ASSERT(sc); 1755 1756 mii = device_get_softc(sc->rl_miibus); 1757 1758 mii_tick(mii); 1759 1760 sc->rl_stat_ch = timeout(re_tick, sc, hz); 1761 } 1762 1763 #ifdef DEVICE_POLLING 1764 static void 1765 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1766 { 1767 struct rl_softc *sc = ifp->if_softc; 1768 1769 RL_LOCK(sc); 1770 re_poll_locked(ifp, cmd, count); 1771 RL_UNLOCK(sc); 1772 } 1773 1774 static void 1775 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1776 { 1777 struct rl_softc *sc = ifp->if_softc; 1778 1779 RL_LOCK_ASSERT(sc); 1780 1781 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1782 ether_poll_deregister(ifp); 1783 cmd = POLL_DEREGISTER; 1784 } 1785 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1786 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 1787 return; 1788 } 1789 1790 sc->rxcycles = count; 1791 re_rxeof(sc); 1792 re_txeof(sc); 1793 1794 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1795 re_start_locked(ifp); 1796 1797 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1798 u_int16_t status; 1799 1800 status = CSR_READ_2(sc, RL_ISR); 1801 if (status == 0xffff) 1802 return; 1803 if (status) 1804 CSR_WRITE_2(sc, RL_ISR, status); 1805 1806 /* 1807 * XXX check behaviour on receiver stalls. 1808 */ 1809 1810 if (status & RL_ISR_SYSTEM_ERR) { 1811 re_reset(sc); 1812 re_init_locked(sc); 1813 } 1814 } 1815 } 1816 #endif /* DEVICE_POLLING */ 1817 1818 static void 1819 re_intr(arg) 1820 void *arg; 1821 { 1822 struct rl_softc *sc; 1823 struct ifnet *ifp; 1824 u_int16_t status; 1825 1826 sc = arg; 1827 1828 RL_LOCK(sc); 1829 1830 ifp = &sc->arpcom.ac_if; 1831 1832 if (sc->suspended || !(ifp->if_flags & IFF_UP)) 1833 goto done_locked; 1834 1835 #ifdef DEVICE_POLLING 1836 if (ifp->if_flags & IFF_POLLING) 1837 goto done_locked; 1838 if ((ifp->if_capenable & IFCAP_POLLING) && 1839 ether_poll_register(re_poll, ifp)) { /* ok, disable interrupts */ 1840 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1841 re_poll_locked(ifp, 0, 1); 1842 goto done_locked; 1843 } 1844 #endif /* DEVICE_POLLING */ 1845 1846 for (;;) { 1847 1848 status = CSR_READ_2(sc, RL_ISR); 1849 /* If the card has gone away the read returns 0xffff. */ 1850 if (status == 0xffff) 1851 break; 1852 if (status) 1853 CSR_WRITE_2(sc, RL_ISR, status); 1854 1855 if ((status & RL_INTRS_CPLUS) == 0) 1856 break; 1857 1858 if ((status & RL_ISR_RX_OK) || 1859 (status & RL_ISR_RX_ERR)) 1860 re_rxeof(sc); 1861 1862 if ((status & RL_ISR_TIMEOUT_EXPIRED) || 1863 (status & RL_ISR_TX_ERR) || 1864 (status & RL_ISR_TX_DESC_UNAVAIL)) 1865 re_txeof(sc); 1866 1867 if (status & RL_ISR_SYSTEM_ERR) { 1868 re_reset(sc); 1869 re_init_locked(sc); 1870 } 1871 1872 if (status & RL_ISR_LINKCHG) { 1873 untimeout(re_tick, sc, sc->rl_stat_ch); 1874 re_tick_locked(sc); 1875 } 1876 } 1877 1878 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1879 re_start_locked(ifp); 1880 1881 done_locked: 1882 RL_UNLOCK(sc); 1883 } 1884 1885 static int 1886 re_encap(sc, m_head, idx) 1887 struct rl_softc *sc; 1888 struct mbuf **m_head; 1889 int *idx; 1890 { 1891 struct mbuf *m_new = NULL; 1892 struct rl_dmaload_arg arg; 1893 bus_dmamap_t map; 1894 int error; 1895 struct m_tag *mtag; 1896 1897 RL_LOCK_ASSERT(sc); 1898 1899 if (sc->rl_ldata.rl_tx_free <= 4) 1900 return (EFBIG); 1901 1902 /* 1903 * Set up checksum offload. Note: checksum offload bits must 1904 * appear in all descriptors of a multi-descriptor transmit 1905 * attempt. This is according to testing done with an 8169 1906 * chip. This is a requirement. 1907 */ 1908 1909 arg.rl_flags = 0; 1910 1911 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) 1912 arg.rl_flags |= RL_TDESC_CMD_IPCSUM; 1913 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) 1914 arg.rl_flags |= RL_TDESC_CMD_TCPCSUM; 1915 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) 1916 arg.rl_flags |= RL_TDESC_CMD_UDPCSUM; 1917 1918 arg.sc = sc; 1919 arg.rl_idx = *idx; 1920 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 1921 if (arg.rl_maxsegs > 4) 1922 arg.rl_maxsegs -= 4; 1923 arg.rl_ring = sc->rl_ldata.rl_tx_list; 1924 1925 map = sc->rl_ldata.rl_tx_dmamap[*idx]; 1926 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 1927 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1928 1929 if (error && error != EFBIG) { 1930 printf("re%d: can't map mbuf (error %d)\n", sc->rl_unit, error); 1931 return (ENOBUFS); 1932 } 1933 1934 /* Too many segments to map, coalesce into a single mbuf */ 1935 1936 if (error || arg.rl_maxsegs == 0) { 1937 m_new = m_defrag(*m_head, M_DONTWAIT); 1938 if (m_new == NULL) 1939 return (ENOBUFS); 1940 else 1941 *m_head = m_new; 1942 1943 arg.sc = sc; 1944 arg.rl_idx = *idx; 1945 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 1946 arg.rl_ring = sc->rl_ldata.rl_tx_list; 1947 1948 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 1949 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1950 if (error) { 1951 printf("re%d: can't map mbuf (error %d)\n", 1952 sc->rl_unit, error); 1953 return (EFBIG); 1954 } 1955 } 1956 1957 /* 1958 * Insure that the map for this transmission 1959 * is placed at the array index of the last descriptor 1960 * in this chain. (Swap last and first dmamaps.) 1961 */ 1962 sc->rl_ldata.rl_tx_dmamap[*idx] = 1963 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx]; 1964 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx] = map; 1965 1966 sc->rl_ldata.rl_tx_mbuf[arg.rl_idx] = *m_head; 1967 sc->rl_ldata.rl_tx_free -= arg.rl_maxsegs; 1968 1969 /* 1970 * Set up hardware VLAN tagging. Note: vlan tag info must 1971 * appear in the first descriptor of a multi-descriptor 1972 * transmission attempt. 1973 */ 1974 1975 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, *m_head); 1976 if (mtag != NULL) 1977 sc->rl_ldata.rl_tx_list[*idx].rl_vlanctl = 1978 htole32(htons(VLAN_TAG_VALUE(mtag)) | RL_TDESC_VLANCTL_TAG); 1979 1980 /* Transfer ownership of packet to the chip. */ 1981 1982 sc->rl_ldata.rl_tx_list[arg.rl_idx].rl_cmdstat |= 1983 htole32(RL_TDESC_CMD_OWN); 1984 if (*idx != arg.rl_idx) 1985 sc->rl_ldata.rl_tx_list[*idx].rl_cmdstat |= 1986 htole32(RL_TDESC_CMD_OWN); 1987 1988 RL_DESC_INC(arg.rl_idx); 1989 *idx = arg.rl_idx; 1990 1991 return (0); 1992 } 1993 1994 static void 1995 re_start(ifp) 1996 struct ifnet *ifp; 1997 { 1998 struct rl_softc *sc; 1999 2000 sc = ifp->if_softc; 2001 RL_LOCK(sc); 2002 re_start_locked(ifp); 2003 RL_UNLOCK(sc); 2004 } 2005 2006 /* 2007 * Main transmit routine for C+ and gigE NICs. 2008 */ 2009 static void 2010 re_start_locked(ifp) 2011 struct ifnet *ifp; 2012 { 2013 struct rl_softc *sc; 2014 struct mbuf *m_head = NULL; 2015 int idx, queued = 0; 2016 2017 sc = ifp->if_softc; 2018 2019 RL_LOCK_ASSERT(sc); 2020 2021 idx = sc->rl_ldata.rl_tx_prodidx; 2022 2023 while (sc->rl_ldata.rl_tx_mbuf[idx] == NULL) { 2024 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2025 if (m_head == NULL) 2026 break; 2027 2028 if (re_encap(sc, &m_head, &idx)) { 2029 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2030 ifp->if_flags |= IFF_OACTIVE; 2031 break; 2032 } 2033 2034 /* 2035 * If there's a BPF listener, bounce a copy of this frame 2036 * to him. 2037 */ 2038 BPF_MTAP(ifp, m_head); 2039 2040 queued++; 2041 } 2042 2043 if (queued == 0) 2044 return; 2045 2046 /* Flush the TX descriptors */ 2047 2048 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2049 sc->rl_ldata.rl_tx_list_map, 2050 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2051 2052 sc->rl_ldata.rl_tx_prodidx = idx; 2053 2054 /* 2055 * RealTek put the TX poll request register in a different 2056 * location on the 8169 gigE chip. I don't know why. 2057 */ 2058 2059 if (sc->rl_type == RL_8169) 2060 CSR_WRITE_2(sc, RL_GTXSTART, RL_TXSTART_START); 2061 else 2062 CSR_WRITE_2(sc, RL_TXSTART, RL_TXSTART_START); 2063 2064 /* 2065 * Use the countdown timer for interrupt moderation. 2066 * 'TX done' interrupts are disabled. Instead, we reset the 2067 * countdown timer, which will begin counting until it hits 2068 * the value in the TIMERINT register, and then trigger an 2069 * interrupt. Each time we write to the TIMERCNT register, 2070 * the timer count is reset to 0. 2071 */ 2072 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2073 2074 /* 2075 * Set a timeout in case the chip goes out to lunch. 2076 */ 2077 ifp->if_timer = 5; 2078 } 2079 2080 static void 2081 re_init(xsc) 2082 void *xsc; 2083 { 2084 struct rl_softc *sc = xsc; 2085 2086 RL_LOCK(sc); 2087 re_init_locked(sc); 2088 RL_UNLOCK(sc); 2089 } 2090 2091 static void 2092 re_init_locked(sc) 2093 struct rl_softc *sc; 2094 { 2095 struct ifnet *ifp = &sc->arpcom.ac_if; 2096 struct mii_data *mii; 2097 u_int32_t rxcfg = 0; 2098 2099 RL_LOCK_ASSERT(sc); 2100 2101 mii = device_get_softc(sc->rl_miibus); 2102 2103 /* 2104 * Cancel pending I/O and free all RX/TX buffers. 2105 */ 2106 re_stop(sc); 2107 2108 /* 2109 * Enable C+ RX and TX mode, as well as VLAN stripping and 2110 * RX checksum offload. We must configure the C+ register 2111 * before all others. 2112 */ 2113 CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB| 2114 RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW| 2115 RL_CPLUSCMD_VLANSTRIP| 2116 (ifp->if_capenable & IFCAP_RXCSUM ? 2117 RL_CPLUSCMD_RXCSUM_ENB : 0)); 2118 2119 /* 2120 * Init our MAC address. Even though the chipset 2121 * documentation doesn't mention it, we need to enter "Config 2122 * register write enable" mode to modify the ID registers. 2123 */ 2124 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2125 CSR_WRITE_STREAM_4(sc, RL_IDR0, 2126 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 2127 CSR_WRITE_STREAM_4(sc, RL_IDR4, 2128 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 2129 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2130 2131 /* 2132 * For C+ mode, initialize the RX descriptors and mbufs. 2133 */ 2134 re_rx_list_init(sc); 2135 re_tx_list_init(sc); 2136 2137 /* 2138 * Enable transmit and receive. 2139 */ 2140 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2141 2142 /* 2143 * Set the initial TX and RX configuration. 2144 */ 2145 if (sc->rl_testmode) { 2146 if (sc->rl_type == RL_8169) 2147 CSR_WRITE_4(sc, RL_TXCFG, 2148 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2149 else 2150 CSR_WRITE_4(sc, RL_TXCFG, 2151 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2152 } else 2153 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2154 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 2155 2156 /* Set the individual bit to receive frames for this host only. */ 2157 rxcfg = CSR_READ_4(sc, RL_RXCFG); 2158 rxcfg |= RL_RXCFG_RX_INDIV; 2159 2160 /* If we want promiscuous mode, set the allframes bit. */ 2161 if (ifp->if_flags & IFF_PROMISC) 2162 rxcfg |= RL_RXCFG_RX_ALLPHYS; 2163 else 2164 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 2165 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2166 2167 /* 2168 * Set capture broadcast bit to capture broadcast frames. 2169 */ 2170 if (ifp->if_flags & IFF_BROADCAST) 2171 rxcfg |= RL_RXCFG_RX_BROAD; 2172 else 2173 rxcfg &= ~RL_RXCFG_RX_BROAD; 2174 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2175 2176 /* 2177 * Program the multicast filter, if necessary. 2178 */ 2179 re_setmulti(sc); 2180 2181 #ifdef DEVICE_POLLING 2182 /* 2183 * Disable interrupts if we are polling. 2184 */ 2185 if (ifp->if_flags & IFF_POLLING) 2186 CSR_WRITE_2(sc, RL_IMR, 0); 2187 else /* otherwise ... */ 2188 #endif /* DEVICE_POLLING */ 2189 /* 2190 * Enable interrupts. 2191 */ 2192 if (sc->rl_testmode) 2193 CSR_WRITE_2(sc, RL_IMR, 0); 2194 else 2195 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2196 2197 /* Set initial TX threshold */ 2198 sc->rl_txthresh = RL_TX_THRESH_INIT; 2199 2200 /* Start RX/TX process. */ 2201 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2202 #ifdef notdef 2203 /* Enable receiver and transmitter. */ 2204 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2205 #endif 2206 /* 2207 * Load the addresses of the RX and TX lists into the chip. 2208 */ 2209 2210 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2211 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2212 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2213 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2214 2215 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2216 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2217 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2218 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2219 2220 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2221 2222 /* 2223 * Initialize the timer interrupt register so that 2224 * a timer interrupt will be generated once the timer 2225 * reaches a certain number of ticks. The timer is 2226 * reloaded on each transmit. This gives us TX interrupt 2227 * moderation, which dramatically improves TX frame rate. 2228 */ 2229 if (sc->rl_type == RL_8169) 2230 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2231 else 2232 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2233 2234 /* 2235 * For 8169 gigE NICs, set the max allowed RX packet 2236 * size so we can receive jumbo frames. 2237 */ 2238 if (sc->rl_type == RL_8169) 2239 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2240 2241 if (sc->rl_testmode) 2242 return; 2243 2244 mii_mediachg(mii); 2245 2246 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 2247 2248 ifp->if_flags |= IFF_RUNNING; 2249 ifp->if_flags &= ~IFF_OACTIVE; 2250 2251 sc->rl_stat_ch = timeout(re_tick, sc, hz); 2252 } 2253 2254 /* 2255 * Set media options. 2256 */ 2257 static int 2258 re_ifmedia_upd(ifp) 2259 struct ifnet *ifp; 2260 { 2261 struct rl_softc *sc; 2262 struct mii_data *mii; 2263 2264 sc = ifp->if_softc; 2265 mii = device_get_softc(sc->rl_miibus); 2266 mii_mediachg(mii); 2267 2268 return (0); 2269 } 2270 2271 /* 2272 * Report current media status. 2273 */ 2274 static void 2275 re_ifmedia_sts(ifp, ifmr) 2276 struct ifnet *ifp; 2277 struct ifmediareq *ifmr; 2278 { 2279 struct rl_softc *sc; 2280 struct mii_data *mii; 2281 2282 sc = ifp->if_softc; 2283 mii = device_get_softc(sc->rl_miibus); 2284 2285 mii_pollstat(mii); 2286 ifmr->ifm_active = mii->mii_media_active; 2287 ifmr->ifm_status = mii->mii_media_status; 2288 } 2289 2290 static int 2291 re_ioctl(ifp, command, data) 2292 struct ifnet *ifp; 2293 u_long command; 2294 caddr_t data; 2295 { 2296 struct rl_softc *sc = ifp->if_softc; 2297 struct ifreq *ifr = (struct ifreq *) data; 2298 struct mii_data *mii; 2299 int error = 0; 2300 2301 switch (command) { 2302 case SIOCSIFMTU: 2303 if (ifr->ifr_mtu > RL_JUMBO_MTU) 2304 error = EINVAL; 2305 ifp->if_mtu = ifr->ifr_mtu; 2306 break; 2307 case SIOCSIFFLAGS: 2308 RL_LOCK(sc); 2309 if (ifp->if_flags & IFF_UP) 2310 re_init_locked(sc); 2311 else if (ifp->if_flags & IFF_RUNNING) 2312 re_stop(sc); 2313 RL_UNLOCK(sc); 2314 error = 0; 2315 break; 2316 case SIOCADDMULTI: 2317 case SIOCDELMULTI: 2318 RL_LOCK(sc); 2319 re_setmulti(sc); 2320 RL_UNLOCK(sc); 2321 error = 0; 2322 break; 2323 case SIOCGIFMEDIA: 2324 case SIOCSIFMEDIA: 2325 mii = device_get_softc(sc->rl_miibus); 2326 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2327 break; 2328 case SIOCSIFCAP: 2329 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_POLLING); 2330 ifp->if_capenable |= 2331 ifr->ifr_reqcap & (IFCAP_HWCSUM | IFCAP_POLLING); 2332 if (ifp->if_capenable & IFCAP_TXCSUM) 2333 ifp->if_hwassist = RE_CSUM_FEATURES; 2334 else 2335 ifp->if_hwassist = 0; 2336 if (ifp->if_flags & IFF_RUNNING) 2337 re_init(sc); 2338 break; 2339 default: 2340 error = ether_ioctl(ifp, command, data); 2341 break; 2342 } 2343 2344 return (error); 2345 } 2346 2347 static void 2348 re_watchdog(ifp) 2349 struct ifnet *ifp; 2350 { 2351 struct rl_softc *sc; 2352 2353 sc = ifp->if_softc; 2354 RL_LOCK(sc); 2355 printf("re%d: watchdog timeout\n", sc->rl_unit); 2356 ifp->if_oerrors++; 2357 2358 re_txeof(sc); 2359 re_rxeof(sc); 2360 re_init_locked(sc); 2361 2362 RL_UNLOCK(sc); 2363 } 2364 2365 /* 2366 * Stop the adapter and free any mbufs allocated to the 2367 * RX and TX lists. 2368 */ 2369 static void 2370 re_stop(sc) 2371 struct rl_softc *sc; 2372 { 2373 register int i; 2374 struct ifnet *ifp; 2375 2376 RL_LOCK_ASSERT(sc); 2377 2378 ifp = &sc->arpcom.ac_if; 2379 ifp->if_timer = 0; 2380 2381 untimeout(re_tick, sc, sc->rl_stat_ch); 2382 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2383 #ifdef DEVICE_POLLING 2384 ether_poll_deregister(ifp); 2385 #endif /* DEVICE_POLLING */ 2386 2387 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2388 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2389 2390 if (sc->rl_head != NULL) { 2391 m_freem(sc->rl_head); 2392 sc->rl_head = sc->rl_tail = NULL; 2393 } 2394 2395 /* Free the TX list buffers. */ 2396 2397 for (i = 0; i < RL_TX_DESC_CNT; i++) { 2398 if (sc->rl_ldata.rl_tx_mbuf[i] != NULL) { 2399 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2400 sc->rl_ldata.rl_tx_dmamap[i]); 2401 m_freem(sc->rl_ldata.rl_tx_mbuf[i]); 2402 sc->rl_ldata.rl_tx_mbuf[i] = NULL; 2403 } 2404 } 2405 2406 /* Free the RX list buffers. */ 2407 2408 for (i = 0; i < RL_RX_DESC_CNT; i++) { 2409 if (sc->rl_ldata.rl_rx_mbuf[i] != NULL) { 2410 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2411 sc->rl_ldata.rl_rx_dmamap[i]); 2412 m_freem(sc->rl_ldata.rl_rx_mbuf[i]); 2413 sc->rl_ldata.rl_rx_mbuf[i] = NULL; 2414 } 2415 } 2416 } 2417 2418 /* 2419 * Device suspend routine. Stop the interface and save some PCI 2420 * settings in case the BIOS doesn't restore them properly on 2421 * resume. 2422 */ 2423 static int 2424 re_suspend(dev) 2425 device_t dev; 2426 { 2427 struct rl_softc *sc; 2428 2429 sc = device_get_softc(dev); 2430 2431 RL_LOCK(sc); 2432 re_stop(sc); 2433 sc->suspended = 1; 2434 RL_UNLOCK(sc); 2435 2436 return (0); 2437 } 2438 2439 /* 2440 * Device resume routine. Restore some PCI settings in case the BIOS 2441 * doesn't, re-enable busmastering, and restart the interface if 2442 * appropriate. 2443 */ 2444 static int 2445 re_resume(dev) 2446 device_t dev; 2447 { 2448 struct rl_softc *sc; 2449 struct ifnet *ifp; 2450 2451 sc = device_get_softc(dev); 2452 2453 RL_LOCK(sc); 2454 2455 ifp = &sc->arpcom.ac_if; 2456 2457 /* reinitialize interface if necessary */ 2458 if (ifp->if_flags & IFF_UP) 2459 re_init_locked(sc); 2460 2461 sc->suspended = 0; 2462 RL_UNLOCK(sc); 2463 2464 return (0); 2465 } 2466 2467 /* 2468 * Stop all chip I/O so that the kernel's probe routines don't 2469 * get confused by errant DMAs when rebooting. 2470 */ 2471 static void 2472 re_shutdown(dev) 2473 device_t dev; 2474 { 2475 struct rl_softc *sc; 2476 2477 sc = device_get_softc(dev); 2478 2479 RL_LOCK(sc); 2480 re_stop(sc); 2481 RL_UNLOCK(sc); 2482 } 2483