1 /*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44 /* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111 #ifdef HAVE_KERNEL_OPTION_HEADERS 112 #include "opt_device_polling.h" 113 #endif 114 115 #include <sys/param.h> 116 #include <sys/endian.h> 117 #include <sys/systm.h> 118 #include <sys/sockio.h> 119 #include <sys/mbuf.h> 120 #include <sys/malloc.h> 121 #include <sys/module.h> 122 #include <sys/kernel.h> 123 #include <sys/socket.h> 124 #include <sys/lock.h> 125 #include <sys/mutex.h> 126 #include <sys/taskqueue.h> 127 128 #include <net/if.h> 129 #include <net/if_arp.h> 130 #include <net/ethernet.h> 131 #include <net/if_dl.h> 132 #include <net/if_media.h> 133 #include <net/if_types.h> 134 #include <net/if_vlan_var.h> 135 136 #include <net/bpf.h> 137 138 #include <machine/bus.h> 139 #include <machine/resource.h> 140 #include <sys/bus.h> 141 #include <sys/rman.h> 142 143 #include <dev/mii/mii.h> 144 #include <dev/mii/miivar.h> 145 146 #include <dev/pci/pcireg.h> 147 #include <dev/pci/pcivar.h> 148 149 #include <pci/if_rlreg.h> 150 151 MODULE_DEPEND(re, pci, 1, 1, 1); 152 MODULE_DEPEND(re, ether, 1, 1, 1); 153 MODULE_DEPEND(re, miibus, 1, 1, 1); 154 155 /* "device miibus" required. See GENERIC if you get errors here. */ 156 #include "miibus_if.h" 157 158 /* Tunables. */ 159 static int msi_disable = 0; 160 TUNABLE_INT("hw.re.msi_disable", &msi_disable); 161 static int prefer_iomap = 0; 162 TUNABLE_INT("hw.re.prefer_iomap", &prefer_iomap); 163 164 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 165 166 /* 167 * Various supported device vendors/types and their names. 168 */ 169 static struct rl_type re_devs[] = { 170 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0, 171 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 172 { RT_VENDORID, RT_DEVICEID_8139, 0, 173 "RealTek 8139C+ 10/100BaseTX" }, 174 { RT_VENDORID, RT_DEVICEID_8101E, 0, 175 "RealTek 8101E/8102E/8102EL PCIe 10/100baseTX" }, 176 { RT_VENDORID, RT_DEVICEID_8168, 0, 177 "RealTek 8168/8168B/8168C/8168CP/8168D/8111B/8111C/8111CP PCIe " 178 "Gigabit Ethernet" }, 179 { RT_VENDORID, RT_DEVICEID_8169, 0, 180 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" }, 181 { RT_VENDORID, RT_DEVICEID_8169SC, 0, 182 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 183 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0, 184 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 185 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0, 186 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 187 { USR_VENDORID, USR_DEVICEID_997902, 0, 188 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 189 }; 190 191 static struct rl_hwrev re_hwrevs[] = { 192 { RL_HWREV_8139, RL_8139, "" }, 193 { RL_HWREV_8139A, RL_8139, "A" }, 194 { RL_HWREV_8139AG, RL_8139, "A-G" }, 195 { RL_HWREV_8139B, RL_8139, "B" }, 196 { RL_HWREV_8130, RL_8139, "8130" }, 197 { RL_HWREV_8139C, RL_8139, "C" }, 198 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 199 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 200 { RL_HWREV_8168_SPIN1, RL_8169, "8168"}, 201 { RL_HWREV_8169, RL_8169, "8169"}, 202 { RL_HWREV_8169S, RL_8169, "8169S"}, 203 { RL_HWREV_8110S, RL_8169, "8110S"}, 204 { RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB"}, 205 { RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC"}, 206 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL"}, 207 { RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC"}, 208 { RL_HWREV_8100, RL_8139, "8100"}, 209 { RL_HWREV_8101, RL_8139, "8101"}, 210 { RL_HWREV_8100E, RL_8169, "8100E"}, 211 { RL_HWREV_8101E, RL_8169, "8101E"}, 212 { RL_HWREV_8102E, RL_8169, "8102E"}, 213 { RL_HWREV_8102EL, RL_8169, "8102EL"}, 214 { RL_HWREV_8168_SPIN2, RL_8169, "8168"}, 215 { RL_HWREV_8168_SPIN3, RL_8169, "8168"}, 216 { RL_HWREV_8168C, RL_8169, "8168C/8111C"}, 217 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C"}, 218 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP"}, 219 { RL_HWREV_8168D, RL_8169, "8168D"}, 220 { 0, 0, NULL } 221 }; 222 223 static int re_probe (device_t); 224 static int re_attach (device_t); 225 static int re_detach (device_t); 226 227 static int re_encap (struct rl_softc *, struct mbuf **); 228 229 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 230 static int re_allocmem (device_t, struct rl_softc *); 231 static __inline void re_discard_rxbuf 232 (struct rl_softc *, int); 233 static int re_newbuf (struct rl_softc *, int); 234 static int re_rx_list_init (struct rl_softc *); 235 static int re_tx_list_init (struct rl_softc *); 236 #ifdef RE_FIXUP_RX 237 static __inline void re_fixup_rx 238 (struct mbuf *); 239 #endif 240 static int re_rxeof (struct rl_softc *); 241 static void re_txeof (struct rl_softc *); 242 #ifdef DEVICE_POLLING 243 static void re_poll (struct ifnet *, enum poll_cmd, int); 244 static void re_poll_locked (struct ifnet *, enum poll_cmd, int); 245 #endif 246 static int re_intr (void *); 247 static void re_tick (void *); 248 static void re_tx_task (void *, int); 249 static void re_int_task (void *, int); 250 static void re_start (struct ifnet *); 251 static int re_ioctl (struct ifnet *, u_long, caddr_t); 252 static void re_init (void *); 253 static void re_init_locked (struct rl_softc *); 254 static void re_stop (struct rl_softc *); 255 static void re_watchdog (struct rl_softc *); 256 static int re_suspend (device_t); 257 static int re_resume (device_t); 258 static int re_shutdown (device_t); 259 static int re_ifmedia_upd (struct ifnet *); 260 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 261 262 static void re_eeprom_putbyte (struct rl_softc *, int); 263 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 264 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 265 static int re_gmii_readreg (device_t, int, int); 266 static int re_gmii_writereg (device_t, int, int, int); 267 268 static int re_miibus_readreg (device_t, int, int); 269 static int re_miibus_writereg (device_t, int, int, int); 270 static void re_miibus_statchg (device_t); 271 272 static void re_set_rxmode (struct rl_softc *); 273 static void re_reset (struct rl_softc *); 274 static void re_setwol (struct rl_softc *); 275 static void re_clrwol (struct rl_softc *); 276 277 #ifdef RE_DIAG 278 static int re_diag (struct rl_softc *); 279 #endif 280 281 static device_method_t re_methods[] = { 282 /* Device interface */ 283 DEVMETHOD(device_probe, re_probe), 284 DEVMETHOD(device_attach, re_attach), 285 DEVMETHOD(device_detach, re_detach), 286 DEVMETHOD(device_suspend, re_suspend), 287 DEVMETHOD(device_resume, re_resume), 288 DEVMETHOD(device_shutdown, re_shutdown), 289 290 /* bus interface */ 291 DEVMETHOD(bus_print_child, bus_generic_print_child), 292 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 293 294 /* MII interface */ 295 DEVMETHOD(miibus_readreg, re_miibus_readreg), 296 DEVMETHOD(miibus_writereg, re_miibus_writereg), 297 DEVMETHOD(miibus_statchg, re_miibus_statchg), 298 299 { 0, 0 } 300 }; 301 302 static driver_t re_driver = { 303 "re", 304 re_methods, 305 sizeof(struct rl_softc) 306 }; 307 308 static devclass_t re_devclass; 309 310 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 311 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 312 313 #define EE_SET(x) \ 314 CSR_WRITE_1(sc, RL_EECMD, \ 315 CSR_READ_1(sc, RL_EECMD) | x) 316 317 #define EE_CLR(x) \ 318 CSR_WRITE_1(sc, RL_EECMD, \ 319 CSR_READ_1(sc, RL_EECMD) & ~x) 320 321 /* 322 * Send a read command and address to the EEPROM, check for ACK. 323 */ 324 static void 325 re_eeprom_putbyte(struct rl_softc *sc, int addr) 326 { 327 int d, i; 328 329 d = addr | (RL_9346_READ << sc->rl_eewidth); 330 331 /* 332 * Feed in each bit and strobe the clock. 333 */ 334 335 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 336 if (d & i) { 337 EE_SET(RL_EE_DATAIN); 338 } else { 339 EE_CLR(RL_EE_DATAIN); 340 } 341 DELAY(100); 342 EE_SET(RL_EE_CLK); 343 DELAY(150); 344 EE_CLR(RL_EE_CLK); 345 DELAY(100); 346 } 347 } 348 349 /* 350 * Read a word of data stored in the EEPROM at address 'addr.' 351 */ 352 static void 353 re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest) 354 { 355 int i; 356 u_int16_t word = 0; 357 358 /* 359 * Send address of word we want to read. 360 */ 361 re_eeprom_putbyte(sc, addr); 362 363 /* 364 * Start reading bits from EEPROM. 365 */ 366 for (i = 0x8000; i; i >>= 1) { 367 EE_SET(RL_EE_CLK); 368 DELAY(100); 369 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 370 word |= i; 371 EE_CLR(RL_EE_CLK); 372 DELAY(100); 373 } 374 375 *dest = word; 376 } 377 378 /* 379 * Read a sequence of words from the EEPROM. 380 */ 381 static void 382 re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt) 383 { 384 int i; 385 u_int16_t word = 0, *ptr; 386 387 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 388 389 DELAY(100); 390 391 for (i = 0; i < cnt; i++) { 392 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 393 re_eeprom_getword(sc, off + i, &word); 394 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 395 ptr = (u_int16_t *)(dest + (i * 2)); 396 *ptr = word; 397 } 398 399 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 400 } 401 402 static int 403 re_gmii_readreg(device_t dev, int phy, int reg) 404 { 405 struct rl_softc *sc; 406 u_int32_t rval; 407 int i; 408 409 if (phy != 1) 410 return (0); 411 412 sc = device_get_softc(dev); 413 414 /* Let the rgephy driver read the GMEDIASTAT register */ 415 416 if (reg == RL_GMEDIASTAT) { 417 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 418 return (rval); 419 } 420 421 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 422 DELAY(1000); 423 424 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 425 rval = CSR_READ_4(sc, RL_PHYAR); 426 if (rval & RL_PHYAR_BUSY) 427 break; 428 DELAY(100); 429 } 430 431 if (i == RL_PHY_TIMEOUT) { 432 device_printf(sc->rl_dev, "PHY read failed\n"); 433 return (0); 434 } 435 436 return (rval & RL_PHYAR_PHYDATA); 437 } 438 439 static int 440 re_gmii_writereg(device_t dev, int phy, int reg, int data) 441 { 442 struct rl_softc *sc; 443 u_int32_t rval; 444 int i; 445 446 sc = device_get_softc(dev); 447 448 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 449 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 450 DELAY(1000); 451 452 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 453 rval = CSR_READ_4(sc, RL_PHYAR); 454 if (!(rval & RL_PHYAR_BUSY)) 455 break; 456 DELAY(100); 457 } 458 459 if (i == RL_PHY_TIMEOUT) { 460 device_printf(sc->rl_dev, "PHY write failed\n"); 461 return (0); 462 } 463 464 return (0); 465 } 466 467 static int 468 re_miibus_readreg(device_t dev, int phy, int reg) 469 { 470 struct rl_softc *sc; 471 u_int16_t rval = 0; 472 u_int16_t re8139_reg = 0; 473 474 sc = device_get_softc(dev); 475 476 if (sc->rl_type == RL_8169) { 477 rval = re_gmii_readreg(dev, phy, reg); 478 return (rval); 479 } 480 481 /* Pretend the internal PHY is only at address 0 */ 482 if (phy) { 483 return (0); 484 } 485 switch (reg) { 486 case MII_BMCR: 487 re8139_reg = RL_BMCR; 488 break; 489 case MII_BMSR: 490 re8139_reg = RL_BMSR; 491 break; 492 case MII_ANAR: 493 re8139_reg = RL_ANAR; 494 break; 495 case MII_ANER: 496 re8139_reg = RL_ANER; 497 break; 498 case MII_ANLPAR: 499 re8139_reg = RL_LPAR; 500 break; 501 case MII_PHYIDR1: 502 case MII_PHYIDR2: 503 return (0); 504 /* 505 * Allow the rlphy driver to read the media status 506 * register. If we have a link partner which does not 507 * support NWAY, this is the register which will tell 508 * us the results of parallel detection. 509 */ 510 case RL_MEDIASTAT: 511 rval = CSR_READ_1(sc, RL_MEDIASTAT); 512 return (rval); 513 default: 514 device_printf(sc->rl_dev, "bad phy register\n"); 515 return (0); 516 } 517 rval = CSR_READ_2(sc, re8139_reg); 518 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 519 /* 8139C+ has different bit layout. */ 520 rval &= ~(BMCR_LOOP | BMCR_ISO); 521 } 522 return (rval); 523 } 524 525 static int 526 re_miibus_writereg(device_t dev, int phy, int reg, int data) 527 { 528 struct rl_softc *sc; 529 u_int16_t re8139_reg = 0; 530 int rval = 0; 531 532 sc = device_get_softc(dev); 533 534 if (sc->rl_type == RL_8169) { 535 rval = re_gmii_writereg(dev, phy, reg, data); 536 return (rval); 537 } 538 539 /* Pretend the internal PHY is only at address 0 */ 540 if (phy) 541 return (0); 542 543 switch (reg) { 544 case MII_BMCR: 545 re8139_reg = RL_BMCR; 546 if (sc->rl_type == RL_8139CPLUS) { 547 /* 8139C+ has different bit layout. */ 548 data &= ~(BMCR_LOOP | BMCR_ISO); 549 } 550 break; 551 case MII_BMSR: 552 re8139_reg = RL_BMSR; 553 break; 554 case MII_ANAR: 555 re8139_reg = RL_ANAR; 556 break; 557 case MII_ANER: 558 re8139_reg = RL_ANER; 559 break; 560 case MII_ANLPAR: 561 re8139_reg = RL_LPAR; 562 break; 563 case MII_PHYIDR1: 564 case MII_PHYIDR2: 565 return (0); 566 break; 567 default: 568 device_printf(sc->rl_dev, "bad phy register\n"); 569 return (0); 570 } 571 CSR_WRITE_2(sc, re8139_reg, data); 572 return (0); 573 } 574 575 static void 576 re_miibus_statchg(device_t dev) 577 { 578 struct rl_softc *sc; 579 struct ifnet *ifp; 580 struct mii_data *mii; 581 582 sc = device_get_softc(dev); 583 mii = device_get_softc(sc->rl_miibus); 584 ifp = sc->rl_ifp; 585 if (mii == NULL || ifp == NULL || 586 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 587 return; 588 589 sc->rl_flags &= ~RL_FLAG_LINK; 590 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 591 (IFM_ACTIVE | IFM_AVALID)) { 592 switch (IFM_SUBTYPE(mii->mii_media_active)) { 593 case IFM_10_T: 594 case IFM_100_TX: 595 sc->rl_flags |= RL_FLAG_LINK; 596 break; 597 case IFM_1000_T: 598 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0) 599 break; 600 sc->rl_flags |= RL_FLAG_LINK; 601 break; 602 default: 603 break; 604 } 605 } 606 /* 607 * RealTek controllers does not provide any interface to 608 * Tx/Rx MACs for resolved speed, duplex and flow-control 609 * parameters. 610 */ 611 } 612 613 /* 614 * Set the RX configuration and 64-bit multicast hash filter. 615 */ 616 static void 617 re_set_rxmode(struct rl_softc *sc) 618 { 619 struct ifnet *ifp; 620 struct ifmultiaddr *ifma; 621 uint32_t hashes[2] = { 0, 0 }; 622 uint32_t h, rxfilt; 623 624 RL_LOCK_ASSERT(sc); 625 626 ifp = sc->rl_ifp; 627 628 rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD; 629 630 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 631 if (ifp->if_flags & IFF_PROMISC) 632 rxfilt |= RL_RXCFG_RX_ALLPHYS; 633 /* 634 * Unlike other hardwares, we have to explicitly set 635 * RL_RXCFG_RX_MULTI to receive multicast frames in 636 * promiscuous mode. 637 */ 638 rxfilt |= RL_RXCFG_RX_MULTI; 639 hashes[0] = hashes[1] = 0xffffffff; 640 goto done; 641 } 642 643 IF_ADDR_LOCK(ifp); 644 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 645 if (ifma->ifma_addr->sa_family != AF_LINK) 646 continue; 647 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 648 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 649 if (h < 32) 650 hashes[0] |= (1 << h); 651 else 652 hashes[1] |= (1 << (h - 32)); 653 } 654 IF_ADDR_UNLOCK(ifp); 655 656 if (hashes[0] != 0 || hashes[1] != 0) { 657 /* 658 * For some unfathomable reason, RealTek decided to 659 * reverse the order of the multicast hash registers 660 * in the PCI Express parts. This means we have to 661 * write the hash pattern in reverse order for those 662 * devices. 663 */ 664 if ((sc->rl_flags & RL_FLAG_PCIE) != 0) { 665 h = bswap32(hashes[0]); 666 hashes[0] = bswap32(hashes[1]); 667 hashes[1] = h; 668 } 669 rxfilt |= RL_RXCFG_RX_MULTI; 670 } 671 672 done: 673 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 674 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 675 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 676 } 677 678 static void 679 re_reset(struct rl_softc *sc) 680 { 681 int i; 682 683 RL_LOCK_ASSERT(sc); 684 685 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 686 687 for (i = 0; i < RL_TIMEOUT; i++) { 688 DELAY(10); 689 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 690 break; 691 } 692 if (i == RL_TIMEOUT) 693 device_printf(sc->rl_dev, "reset never completed!\n"); 694 695 if ((sc->rl_flags & RL_FLAG_MACRESET) != 0) 696 CSR_WRITE_1(sc, 0x82, 1); 697 if (sc->rl_hwrev == RL_HWREV_8169S) 698 re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0); 699 } 700 701 #ifdef RE_DIAG 702 703 /* 704 * The following routine is designed to test for a defect on some 705 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 706 * lines connected to the bus, however for a 32-bit only card, they 707 * should be pulled high. The result of this defect is that the 708 * NIC will not work right if you plug it into a 64-bit slot: DMA 709 * operations will be done with 64-bit transfers, which will fail 710 * because the 64-bit data lines aren't connected. 711 * 712 * There's no way to work around this (short of talking a soldering 713 * iron to the board), however we can detect it. The method we use 714 * here is to put the NIC into digital loopback mode, set the receiver 715 * to promiscuous mode, and then try to send a frame. We then compare 716 * the frame data we sent to what was received. If the data matches, 717 * then the NIC is working correctly, otherwise we know the user has 718 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 719 * slot. In the latter case, there's no way the NIC can work correctly, 720 * so we print out a message on the console and abort the device attach. 721 */ 722 723 static int 724 re_diag(struct rl_softc *sc) 725 { 726 struct ifnet *ifp = sc->rl_ifp; 727 struct mbuf *m0; 728 struct ether_header *eh; 729 struct rl_desc *cur_rx; 730 u_int16_t status; 731 u_int32_t rxstat; 732 int total_len, i, error = 0, phyaddr; 733 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 734 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 735 736 /* Allocate a single mbuf */ 737 MGETHDR(m0, M_DONTWAIT, MT_DATA); 738 if (m0 == NULL) 739 return (ENOBUFS); 740 741 RL_LOCK(sc); 742 743 /* 744 * Initialize the NIC in test mode. This sets the chip up 745 * so that it can send and receive frames, but performs the 746 * following special functions: 747 * - Puts receiver in promiscuous mode 748 * - Enables digital loopback mode 749 * - Leaves interrupts turned off 750 */ 751 752 ifp->if_flags |= IFF_PROMISC; 753 sc->rl_testmode = 1; 754 re_init_locked(sc); 755 sc->rl_flags |= RL_FLAG_LINK; 756 if (sc->rl_type == RL_8169) 757 phyaddr = 1; 758 else 759 phyaddr = 0; 760 761 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 762 for (i = 0; i < RL_TIMEOUT; i++) { 763 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 764 if (!(status & BMCR_RESET)) 765 break; 766 } 767 768 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 769 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 770 771 DELAY(100000); 772 773 /* Put some data in the mbuf */ 774 775 eh = mtod(m0, struct ether_header *); 776 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 777 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 778 eh->ether_type = htons(ETHERTYPE_IP); 779 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 780 781 /* 782 * Queue the packet, start transmission. 783 * Note: IF_HANDOFF() ultimately calls re_start() for us. 784 */ 785 786 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 787 RL_UNLOCK(sc); 788 /* XXX: re_diag must not be called when in ALTQ mode */ 789 IF_HANDOFF(&ifp->if_snd, m0, ifp); 790 RL_LOCK(sc); 791 m0 = NULL; 792 793 /* Wait for it to propagate through the chip */ 794 795 DELAY(100000); 796 for (i = 0; i < RL_TIMEOUT; i++) { 797 status = CSR_READ_2(sc, RL_ISR); 798 CSR_WRITE_2(sc, RL_ISR, status); 799 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 800 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 801 break; 802 DELAY(10); 803 } 804 805 if (i == RL_TIMEOUT) { 806 device_printf(sc->rl_dev, 807 "diagnostic failed, failed to receive packet in" 808 " loopback mode\n"); 809 error = EIO; 810 goto done; 811 } 812 813 /* 814 * The packet should have been dumped into the first 815 * entry in the RX DMA ring. Grab it from there. 816 */ 817 818 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 819 sc->rl_ldata.rl_rx_list_map, 820 BUS_DMASYNC_POSTREAD); 821 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 822 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 823 BUS_DMASYNC_POSTREAD); 824 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 825 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 826 827 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 828 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 829 eh = mtod(m0, struct ether_header *); 830 831 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 832 total_len = RL_RXBYTES(cur_rx); 833 rxstat = le32toh(cur_rx->rl_cmdstat); 834 835 if (total_len != ETHER_MIN_LEN) { 836 device_printf(sc->rl_dev, 837 "diagnostic failed, received short packet\n"); 838 error = EIO; 839 goto done; 840 } 841 842 /* Test that the received packet data matches what we sent. */ 843 844 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 845 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 846 ntohs(eh->ether_type) != ETHERTYPE_IP) { 847 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 848 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 849 dst, ":", src, ":", ETHERTYPE_IP); 850 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 851 eh->ether_dhost, ":", eh->ether_shost, ":", 852 ntohs(eh->ether_type)); 853 device_printf(sc->rl_dev, "You may have a defective 32-bit " 854 "NIC plugged into a 64-bit PCI slot.\n"); 855 device_printf(sc->rl_dev, "Please re-install the NIC in a " 856 "32-bit slot for proper operation.\n"); 857 device_printf(sc->rl_dev, "Read the re(4) man page for more " 858 "details.\n"); 859 error = EIO; 860 } 861 862 done: 863 /* Turn interface off, release resources */ 864 865 sc->rl_testmode = 0; 866 sc->rl_flags &= ~RL_FLAG_LINK; 867 ifp->if_flags &= ~IFF_PROMISC; 868 re_stop(sc); 869 if (m0 != NULL) 870 m_freem(m0); 871 872 RL_UNLOCK(sc); 873 874 return (error); 875 } 876 877 #endif 878 879 /* 880 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 881 * IDs against our list and return a device name if we find a match. 882 */ 883 static int 884 re_probe(device_t dev) 885 { 886 struct rl_type *t; 887 uint16_t devid, vendor; 888 uint16_t revid, sdevid; 889 int i; 890 891 vendor = pci_get_vendor(dev); 892 devid = pci_get_device(dev); 893 revid = pci_get_revid(dev); 894 sdevid = pci_get_subdevice(dev); 895 896 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 897 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 898 /* 899 * Only attach to rev. 3 of the Linksys EG1032 adapter. 900 * Rev. 2 is supported by sk(4). 901 */ 902 return (ENXIO); 903 } 904 } 905 906 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 907 if (revid != 0x20) { 908 /* 8139, let rl(4) take care of this device. */ 909 return (ENXIO); 910 } 911 } 912 913 t = re_devs; 914 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) { 915 if (vendor == t->rl_vid && devid == t->rl_did) { 916 device_set_desc(dev, t->rl_name); 917 return (BUS_PROBE_DEFAULT); 918 } 919 } 920 921 return (ENXIO); 922 } 923 924 /* 925 * Map a single buffer address. 926 */ 927 928 static void 929 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 930 { 931 bus_addr_t *addr; 932 933 if (error) 934 return; 935 936 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 937 addr = arg; 938 *addr = segs->ds_addr; 939 } 940 941 static int 942 re_allocmem(device_t dev, struct rl_softc *sc) 943 { 944 bus_size_t rx_list_size, tx_list_size; 945 int error; 946 int i; 947 948 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 949 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 950 951 /* 952 * Allocate the parent bus DMA tag appropriate for PCI. 953 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD 954 * register should be set. However some RealTek chips are known 955 * to be buggy on DAC handling, therefore disable DAC by limiting 956 * DMA address space to 32bit. PCIe variants of RealTek chips 957 * may not have the limitation but I took safer path. 958 */ 959 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 960 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 961 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 962 NULL, NULL, &sc->rl_parent_tag); 963 if (error) { 964 device_printf(dev, "could not allocate parent DMA tag\n"); 965 return (error); 966 } 967 968 /* 969 * Allocate map for TX mbufs. 970 */ 971 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 972 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 973 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 974 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 975 if (error) { 976 device_printf(dev, "could not allocate TX DMA tag\n"); 977 return (error); 978 } 979 980 /* 981 * Allocate map for RX mbufs. 982 */ 983 984 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 985 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 986 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 987 if (error) { 988 device_printf(dev, "could not allocate RX DMA tag\n"); 989 return (error); 990 } 991 992 /* 993 * Allocate map for TX descriptor list. 994 */ 995 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 996 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 997 NULL, tx_list_size, 1, tx_list_size, 0, 998 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 999 if (error) { 1000 device_printf(dev, "could not allocate TX DMA ring tag\n"); 1001 return (error); 1002 } 1003 1004 /* Allocate DMA'able memory for the TX ring */ 1005 1006 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1007 (void **)&sc->rl_ldata.rl_tx_list, 1008 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1009 &sc->rl_ldata.rl_tx_list_map); 1010 if (error) { 1011 device_printf(dev, "could not allocate TX DMA ring\n"); 1012 return (error); 1013 } 1014 1015 /* Load the map for the TX ring. */ 1016 1017 sc->rl_ldata.rl_tx_list_addr = 0; 1018 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1019 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1020 tx_list_size, re_dma_map_addr, 1021 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1022 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 1023 device_printf(dev, "could not load TX DMA ring\n"); 1024 return (ENOMEM); 1025 } 1026 1027 /* Create DMA maps for TX buffers */ 1028 1029 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1030 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1031 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1032 if (error) { 1033 device_printf(dev, "could not create DMA map for TX\n"); 1034 return (error); 1035 } 1036 } 1037 1038 /* 1039 * Allocate map for RX descriptor list. 1040 */ 1041 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1042 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1043 NULL, rx_list_size, 1, rx_list_size, 0, 1044 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1045 if (error) { 1046 device_printf(dev, "could not create RX DMA ring tag\n"); 1047 return (error); 1048 } 1049 1050 /* Allocate DMA'able memory for the RX ring */ 1051 1052 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1053 (void **)&sc->rl_ldata.rl_rx_list, 1054 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1055 &sc->rl_ldata.rl_rx_list_map); 1056 if (error) { 1057 device_printf(dev, "could not allocate RX DMA ring\n"); 1058 return (error); 1059 } 1060 1061 /* Load the map for the RX ring. */ 1062 1063 sc->rl_ldata.rl_rx_list_addr = 0; 1064 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1065 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1066 rx_list_size, re_dma_map_addr, 1067 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1068 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1069 device_printf(dev, "could not load RX DMA ring\n"); 1070 return (ENOMEM); 1071 } 1072 1073 /* Create DMA maps for RX buffers */ 1074 1075 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1076 &sc->rl_ldata.rl_rx_sparemap); 1077 if (error) { 1078 device_printf(dev, "could not create spare DMA map for RX\n"); 1079 return (error); 1080 } 1081 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1082 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1083 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1084 if (error) { 1085 device_printf(dev, "could not create DMA map for RX\n"); 1086 return (error); 1087 } 1088 } 1089 1090 return (0); 1091 } 1092 1093 /* 1094 * Attach the interface. Allocate softc structures, do ifmedia 1095 * setup and ethernet/BPF attach. 1096 */ 1097 static int 1098 re_attach(device_t dev) 1099 { 1100 u_char eaddr[ETHER_ADDR_LEN]; 1101 u_int16_t as[ETHER_ADDR_LEN / 2]; 1102 struct rl_softc *sc; 1103 struct ifnet *ifp; 1104 struct rl_hwrev *hw_rev; 1105 int hwrev; 1106 u_int16_t devid, re_did = 0; 1107 int error = 0, rid, i; 1108 int msic, reg; 1109 uint8_t cfg; 1110 1111 sc = device_get_softc(dev); 1112 sc->rl_dev = dev; 1113 1114 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1115 MTX_DEF); 1116 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1117 1118 /* 1119 * Map control/status registers. 1120 */ 1121 pci_enable_busmaster(dev); 1122 1123 devid = pci_get_device(dev); 1124 /* 1125 * Prefer memory space register mapping over IO space. 1126 * Because RTL8169SC does not seem to work when memory mapping 1127 * is used always activate io mapping. 1128 */ 1129 if (devid == RT_DEVICEID_8169SC) 1130 prefer_iomap = 1; 1131 if (prefer_iomap == 0) { 1132 sc->rl_res_id = PCIR_BAR(1); 1133 sc->rl_res_type = SYS_RES_MEMORY; 1134 /* RTL8168/8101E seems to use different BARs. */ 1135 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E) 1136 sc->rl_res_id = PCIR_BAR(2); 1137 } else { 1138 sc->rl_res_id = PCIR_BAR(0); 1139 sc->rl_res_type = SYS_RES_IOPORT; 1140 } 1141 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1142 &sc->rl_res_id, RF_ACTIVE); 1143 if (sc->rl_res == NULL && prefer_iomap == 0) { 1144 sc->rl_res_id = PCIR_BAR(0); 1145 sc->rl_res_type = SYS_RES_IOPORT; 1146 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1147 &sc->rl_res_id, RF_ACTIVE); 1148 } 1149 if (sc->rl_res == NULL) { 1150 device_printf(dev, "couldn't map ports/memory\n"); 1151 error = ENXIO; 1152 goto fail; 1153 } 1154 1155 sc->rl_btag = rman_get_bustag(sc->rl_res); 1156 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1157 1158 msic = 0; 1159 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 1160 sc->rl_flags |= RL_FLAG_PCIE; 1161 msic = pci_msi_count(dev); 1162 if (bootverbose) 1163 device_printf(dev, "MSI count : %d\n", msic); 1164 } 1165 if (msic > 0 && msi_disable == 0) { 1166 msic = 1; 1167 if (pci_alloc_msi(dev, &msic) == 0) { 1168 if (msic == RL_MSI_MESSAGES) { 1169 device_printf(dev, "Using %d MSI messages\n", 1170 msic); 1171 sc->rl_flags |= RL_FLAG_MSI; 1172 /* Explicitly set MSI enable bit. */ 1173 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1174 cfg = CSR_READ_1(sc, RL_CFG2); 1175 cfg |= RL_CFG2_MSI; 1176 CSR_WRITE_1(sc, RL_CFG2, cfg); 1177 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1178 } else 1179 pci_release_msi(dev); 1180 } 1181 } 1182 1183 /* Allocate interrupt */ 1184 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1185 rid = 0; 1186 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1187 RF_SHAREABLE | RF_ACTIVE); 1188 if (sc->rl_irq[0] == NULL) { 1189 device_printf(dev, "couldn't allocate IRQ resources\n"); 1190 error = ENXIO; 1191 goto fail; 1192 } 1193 } else { 1194 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1195 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1196 SYS_RES_IRQ, &rid, RF_ACTIVE); 1197 if (sc->rl_irq[i] == NULL) { 1198 device_printf(dev, 1199 "couldn't llocate IRQ resources for " 1200 "message %d\n", rid); 1201 error = ENXIO; 1202 goto fail; 1203 } 1204 } 1205 } 1206 1207 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1208 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1209 cfg = CSR_READ_1(sc, RL_CFG2); 1210 if ((cfg & RL_CFG2_MSI) != 0) { 1211 device_printf(dev, "turning off MSI enable bit.\n"); 1212 cfg &= ~RL_CFG2_MSI; 1213 CSR_WRITE_1(sc, RL_CFG2, cfg); 1214 } 1215 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1216 } 1217 1218 /* Reset the adapter. */ 1219 RL_LOCK(sc); 1220 re_reset(sc); 1221 RL_UNLOCK(sc); 1222 1223 hw_rev = re_hwrevs; 1224 hwrev = CSR_READ_4(sc, RL_TXCFG); 1225 switch (hwrev & 0x70000000) { 1226 case 0x00000000: 1227 case 0x10000000: 1228 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000); 1229 hwrev &= (RL_TXCFG_HWREV | 0x80000000); 1230 break; 1231 default: 1232 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000); 1233 hwrev &= RL_TXCFG_HWREV; 1234 break; 1235 } 1236 device_printf(dev, "MAC rev. 0x%08x\n", hwrev & 0x00700000); 1237 while (hw_rev->rl_desc != NULL) { 1238 if (hw_rev->rl_rev == hwrev) { 1239 sc->rl_type = hw_rev->rl_type; 1240 sc->rl_hwrev = hw_rev->rl_rev; 1241 break; 1242 } 1243 hw_rev++; 1244 } 1245 if (hw_rev->rl_desc == NULL) { 1246 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev); 1247 error = ENXIO; 1248 goto fail; 1249 } 1250 1251 switch (hw_rev->rl_rev) { 1252 case RL_HWREV_8139CPLUS: 1253 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_FASTETHER; 1254 break; 1255 case RL_HWREV_8100E: 1256 case RL_HWREV_8101E: 1257 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_PHYWAKE | 1258 RL_FLAG_FASTETHER; 1259 break; 1260 case RL_HWREV_8102E: 1261 case RL_HWREV_8102EL: 1262 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_PHYWAKE | 1263 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1264 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP; 1265 break; 1266 case RL_HWREV_8168_SPIN1: 1267 case RL_HWREV_8168_SPIN2: 1268 sc->rl_flags |= RL_FLAG_WOLRXENB; 1269 /* FALLTHROUGH */ 1270 case RL_HWREV_8168_SPIN3: 1271 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT; 1272 break; 1273 case RL_HWREV_8168C_SPIN2: 1274 sc->rl_flags |= RL_FLAG_MACSLEEP; 1275 /* FALLTHROUGH */ 1276 case RL_HWREV_8168C: 1277 if ((hwrev & 0x00700000) == 0x00200000) 1278 sc->rl_flags |= RL_FLAG_MACSLEEP; 1279 /* FALLTHROUGH */ 1280 case RL_HWREV_8168CP: 1281 case RL_HWREV_8168D: 1282 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1283 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP; 1284 /* 1285 * These controllers support jumbo frame but it seems 1286 * that enabling it requires touching additional magic 1287 * registers. Depending on MAC revisions some 1288 * controllers need to disable checksum offload. So 1289 * disable jumbo frame until I have better idea what 1290 * it really requires to make it support. 1291 * RTL8168C/CP : supports up to 6KB jumbo frame. 1292 * RTL8111C/CP : supports up to 9KB jumbo frame. 1293 */ 1294 sc->rl_flags |= RL_FLAG_NOJUMBO; 1295 break; 1296 case RL_HWREV_8169_8110SB: 1297 case RL_HWREV_8169_8110SBL: 1298 case RL_HWREV_8169_8110SC: 1299 case RL_HWREV_8169_8110SCE: 1300 sc->rl_flags |= RL_FLAG_PHYWAKE; 1301 /* FALLTHROUGH */ 1302 case RL_HWREV_8169: 1303 case RL_HWREV_8169S: 1304 case RL_HWREV_8110S: 1305 sc->rl_flags |= RL_FLAG_MACRESET; 1306 break; 1307 default: 1308 break; 1309 } 1310 1311 /* Enable PME. */ 1312 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1313 cfg = CSR_READ_1(sc, RL_CFG1); 1314 cfg |= RL_CFG1_PME; 1315 CSR_WRITE_1(sc, RL_CFG1, cfg); 1316 cfg = CSR_READ_1(sc, RL_CFG5); 1317 cfg &= RL_CFG5_PME_STS; 1318 CSR_WRITE_1(sc, RL_CFG5, cfg); 1319 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1320 1321 if ((sc->rl_flags & RL_FLAG_PAR) != 0) { 1322 /* 1323 * XXX Should have a better way to extract station 1324 * address from EEPROM. 1325 */ 1326 for (i = 0; i < ETHER_ADDR_LEN; i++) 1327 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1328 } else { 1329 sc->rl_eewidth = RL_9356_ADDR_LEN; 1330 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1331 if (re_did != 0x8129) 1332 sc->rl_eewidth = RL_9346_ADDR_LEN; 1333 1334 /* 1335 * Get station address from the EEPROM. 1336 */ 1337 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1338 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1339 as[i] = le16toh(as[i]); 1340 bcopy(as, eaddr, sizeof(eaddr)); 1341 } 1342 1343 if (sc->rl_type == RL_8169) { 1344 /* Set RX length mask and number of descriptors. */ 1345 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1346 sc->rl_txstart = RL_GTXSTART; 1347 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1348 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1349 } else { 1350 /* Set RX length mask and number of descriptors. */ 1351 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1352 sc->rl_txstart = RL_TXSTART; 1353 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1354 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1355 } 1356 1357 error = re_allocmem(dev, sc); 1358 if (error) 1359 goto fail; 1360 1361 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1362 if (ifp == NULL) { 1363 device_printf(dev, "can not if_alloc()\n"); 1364 error = ENOSPC; 1365 goto fail; 1366 } 1367 1368 /* Take controller out of deep sleep mode. */ 1369 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 1370 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 1371 CSR_WRITE_1(sc, RL_GPIO, 1372 CSR_READ_1(sc, RL_GPIO) | 0x01); 1373 else 1374 CSR_WRITE_1(sc, RL_GPIO, 1375 CSR_READ_1(sc, RL_GPIO) & ~0x01); 1376 } 1377 1378 /* Take PHY out of power down mode. */ 1379 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) { 1380 re_gmii_writereg(dev, 1, 0x1f, 0); 1381 re_gmii_writereg(dev, 1, 0x0e, 0); 1382 } 1383 1384 /* Do MII setup */ 1385 if (mii_phy_probe(dev, &sc->rl_miibus, 1386 re_ifmedia_upd, re_ifmedia_sts)) { 1387 device_printf(dev, "MII without any phy!\n"); 1388 error = ENXIO; 1389 goto fail; 1390 } 1391 1392 ifp->if_softc = sc; 1393 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1394 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1395 ifp->if_ioctl = re_ioctl; 1396 ifp->if_start = re_start; 1397 ifp->if_hwassist = RE_CSUM_FEATURES; 1398 ifp->if_capabilities = IFCAP_HWCSUM; 1399 ifp->if_capenable = ifp->if_capabilities; 1400 ifp->if_init = re_init; 1401 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1402 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1403 IFQ_SET_READY(&ifp->if_snd); 1404 1405 TASK_INIT(&sc->rl_txtask, 1, re_tx_task, ifp); 1406 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1407 1408 /* 1409 * XXX 1410 * Still have no idea how to make TSO work on 8168C, 8168CP, 1411 * 8111C and 8111CP. 1412 */ 1413 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 1414 ifp->if_hwassist |= CSUM_TSO; 1415 ifp->if_capabilities |= IFCAP_TSO4; 1416 } 1417 1418 /* 1419 * Call MI attach routine. 1420 */ 1421 ether_ifattach(ifp, eaddr); 1422 1423 /* VLAN capability setup */ 1424 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1425 if (ifp->if_capabilities & IFCAP_HWCSUM) 1426 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1427 /* Enable WOL if PM is supported. */ 1428 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, ®) == 0) 1429 ifp->if_capabilities |= IFCAP_WOL; 1430 ifp->if_capenable = ifp->if_capabilities; 1431 /* 1432 * Don't enable TSO by default. Under certain 1433 * circumtances the controller generated corrupted 1434 * packets in TSO size. 1435 */ 1436 ifp->if_hwassist &= ~CSUM_TSO; 1437 ifp->if_capenable &= ~IFCAP_TSO4; 1438 #ifdef DEVICE_POLLING 1439 ifp->if_capabilities |= IFCAP_POLLING; 1440 #endif 1441 /* 1442 * Tell the upper layer(s) we support long frames. 1443 * Must appear after the call to ether_ifattach() because 1444 * ether_ifattach() sets ifi_hdrlen to the default value. 1445 */ 1446 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1447 1448 #ifdef RE_DIAG 1449 /* 1450 * Perform hardware diagnostic on the original RTL8169. 1451 * Some 32-bit cards were incorrectly wired and would 1452 * malfunction if plugged into a 64-bit slot. 1453 */ 1454 1455 if (hwrev == RL_HWREV_8169) { 1456 error = re_diag(sc); 1457 if (error) { 1458 device_printf(dev, 1459 "attach aborted due to hardware diag failure\n"); 1460 ether_ifdetach(ifp); 1461 goto fail; 1462 } 1463 } 1464 #endif 1465 1466 /* Hook interrupt last to avoid having to lock softc */ 1467 if ((sc->rl_flags & RL_FLAG_MSI) == 0) 1468 error = bus_setup_intr(dev, sc->rl_irq[0], 1469 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1470 &sc->rl_intrhand[0]); 1471 else { 1472 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1473 error = bus_setup_intr(dev, sc->rl_irq[i], 1474 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1475 &sc->rl_intrhand[i]); 1476 if (error != 0) 1477 break; 1478 } 1479 } 1480 if (error) { 1481 device_printf(dev, "couldn't set up irq\n"); 1482 ether_ifdetach(ifp); 1483 } 1484 1485 fail: 1486 1487 if (error) 1488 re_detach(dev); 1489 1490 return (error); 1491 } 1492 1493 /* 1494 * Shutdown hardware and free up resources. This can be called any 1495 * time after the mutex has been initialized. It is called in both 1496 * the error case in attach and the normal detach case so it needs 1497 * to be careful about only freeing resources that have actually been 1498 * allocated. 1499 */ 1500 static int 1501 re_detach(device_t dev) 1502 { 1503 struct rl_softc *sc; 1504 struct ifnet *ifp; 1505 int i, rid; 1506 1507 sc = device_get_softc(dev); 1508 ifp = sc->rl_ifp; 1509 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1510 1511 /* These should only be active if attach succeeded */ 1512 if (device_is_attached(dev)) { 1513 #ifdef DEVICE_POLLING 1514 if (ifp->if_capenable & IFCAP_POLLING) 1515 ether_poll_deregister(ifp); 1516 #endif 1517 RL_LOCK(sc); 1518 #if 0 1519 sc->suspended = 1; 1520 #endif 1521 re_stop(sc); 1522 RL_UNLOCK(sc); 1523 callout_drain(&sc->rl_stat_callout); 1524 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1525 taskqueue_drain(taskqueue_fast, &sc->rl_txtask); 1526 /* 1527 * Force off the IFF_UP flag here, in case someone 1528 * still had a BPF descriptor attached to this 1529 * interface. If they do, ether_ifdetach() will cause 1530 * the BPF code to try and clear the promisc mode 1531 * flag, which will bubble down to re_ioctl(), 1532 * which will try to call re_init() again. This will 1533 * turn the NIC back on and restart the MII ticker, 1534 * which will panic the system when the kernel tries 1535 * to invoke the re_tick() function that isn't there 1536 * anymore. 1537 */ 1538 ifp->if_flags &= ~IFF_UP; 1539 ether_ifdetach(ifp); 1540 } 1541 if (sc->rl_miibus) 1542 device_delete_child(dev, sc->rl_miibus); 1543 bus_generic_detach(dev); 1544 1545 /* 1546 * The rest is resource deallocation, so we should already be 1547 * stopped here. 1548 */ 1549 1550 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1551 if (sc->rl_intrhand[i] != NULL) { 1552 bus_teardown_intr(dev, sc->rl_irq[i], 1553 sc->rl_intrhand[i]); 1554 sc->rl_intrhand[i] = NULL; 1555 } 1556 } 1557 if (ifp != NULL) 1558 if_free(ifp); 1559 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1560 if (sc->rl_irq[0] != NULL) { 1561 bus_release_resource(dev, SYS_RES_IRQ, 0, 1562 sc->rl_irq[0]); 1563 sc->rl_irq[0] = NULL; 1564 } 1565 } else { 1566 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1567 if (sc->rl_irq[i] != NULL) { 1568 bus_release_resource(dev, SYS_RES_IRQ, rid, 1569 sc->rl_irq[i]); 1570 sc->rl_irq[i] = NULL; 1571 } 1572 } 1573 pci_release_msi(dev); 1574 } 1575 if (sc->rl_res) 1576 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, 1577 sc->rl_res); 1578 1579 /* Unload and free the RX DMA ring memory and map */ 1580 1581 if (sc->rl_ldata.rl_rx_list_tag) { 1582 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1583 sc->rl_ldata.rl_rx_list_map); 1584 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1585 sc->rl_ldata.rl_rx_list, 1586 sc->rl_ldata.rl_rx_list_map); 1587 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1588 } 1589 1590 /* Unload and free the TX DMA ring memory and map */ 1591 1592 if (sc->rl_ldata.rl_tx_list_tag) { 1593 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1594 sc->rl_ldata.rl_tx_list_map); 1595 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1596 sc->rl_ldata.rl_tx_list, 1597 sc->rl_ldata.rl_tx_list_map); 1598 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1599 } 1600 1601 /* Destroy all the RX and TX buffer maps */ 1602 1603 if (sc->rl_ldata.rl_tx_mtag) { 1604 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1605 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1606 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1607 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1608 } 1609 if (sc->rl_ldata.rl_rx_mtag) { 1610 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) 1611 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1612 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1613 if (sc->rl_ldata.rl_rx_sparemap) 1614 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1615 sc->rl_ldata.rl_rx_sparemap); 1616 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1617 } 1618 1619 /* Unload and free the stats buffer and map */ 1620 1621 if (sc->rl_ldata.rl_stag) { 1622 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1623 sc->rl_ldata.rl_rx_list_map); 1624 bus_dmamem_free(sc->rl_ldata.rl_stag, 1625 sc->rl_ldata.rl_stats, 1626 sc->rl_ldata.rl_smap); 1627 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1628 } 1629 1630 if (sc->rl_parent_tag) 1631 bus_dma_tag_destroy(sc->rl_parent_tag); 1632 1633 mtx_destroy(&sc->rl_mtx); 1634 1635 return (0); 1636 } 1637 1638 static __inline void 1639 re_discard_rxbuf(struct rl_softc *sc, int idx) 1640 { 1641 struct rl_desc *desc; 1642 struct rl_rxdesc *rxd; 1643 uint32_t cmdstat; 1644 1645 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1646 desc = &sc->rl_ldata.rl_rx_list[idx]; 1647 desc->rl_vlanctl = 0; 1648 cmdstat = rxd->rx_size; 1649 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1650 cmdstat |= RL_RDESC_CMD_EOR; 1651 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1652 } 1653 1654 static int 1655 re_newbuf(struct rl_softc *sc, int idx) 1656 { 1657 struct mbuf *m; 1658 struct rl_rxdesc *rxd; 1659 bus_dma_segment_t segs[1]; 1660 bus_dmamap_t map; 1661 struct rl_desc *desc; 1662 uint32_t cmdstat; 1663 int error, nsegs; 1664 1665 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1666 if (m == NULL) 1667 return (ENOBUFS); 1668 1669 m->m_len = m->m_pkthdr.len = MCLBYTES; 1670 #ifdef RE_FIXUP_RX 1671 /* 1672 * This is part of an evil trick to deal with non-x86 platforms. 1673 * The RealTek chip requires RX buffers to be aligned on 64-bit 1674 * boundaries, but that will hose non-x86 machines. To get around 1675 * this, we leave some empty space at the start of each buffer 1676 * and for non-x86 hosts, we copy the buffer back six bytes 1677 * to achieve word alignment. This is slightly more efficient 1678 * than allocating a new buffer, copying the contents, and 1679 * discarding the old buffer. 1680 */ 1681 m_adj(m, RE_ETHER_ALIGN); 1682 #endif 1683 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1684 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1685 if (error != 0) { 1686 m_freem(m); 1687 return (ENOBUFS); 1688 } 1689 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1690 1691 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1692 if (rxd->rx_m != NULL) { 1693 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1694 BUS_DMASYNC_POSTREAD); 1695 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1696 } 1697 1698 rxd->rx_m = m; 1699 map = rxd->rx_dmamap; 1700 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1701 rxd->rx_size = segs[0].ds_len; 1702 sc->rl_ldata.rl_rx_sparemap = map; 1703 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1704 BUS_DMASYNC_PREREAD); 1705 1706 desc = &sc->rl_ldata.rl_rx_list[idx]; 1707 desc->rl_vlanctl = 0; 1708 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1709 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1710 cmdstat = segs[0].ds_len; 1711 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1712 cmdstat |= RL_RDESC_CMD_EOR; 1713 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1714 1715 return (0); 1716 } 1717 1718 #ifdef RE_FIXUP_RX 1719 static __inline void 1720 re_fixup_rx(struct mbuf *m) 1721 { 1722 int i; 1723 uint16_t *src, *dst; 1724 1725 src = mtod(m, uint16_t *); 1726 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1727 1728 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1729 *dst++ = *src++; 1730 1731 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1732 } 1733 #endif 1734 1735 static int 1736 re_tx_list_init(struct rl_softc *sc) 1737 { 1738 struct rl_desc *desc; 1739 int i; 1740 1741 RL_LOCK_ASSERT(sc); 1742 1743 bzero(sc->rl_ldata.rl_tx_list, 1744 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 1745 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1746 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 1747 /* Set EOR. */ 1748 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 1749 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 1750 1751 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1752 sc->rl_ldata.rl_tx_list_map, 1753 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1754 1755 sc->rl_ldata.rl_tx_prodidx = 0; 1756 sc->rl_ldata.rl_tx_considx = 0; 1757 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 1758 1759 return (0); 1760 } 1761 1762 static int 1763 re_rx_list_init(struct rl_softc *sc) 1764 { 1765 int error, i; 1766 1767 bzero(sc->rl_ldata.rl_rx_list, 1768 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 1769 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1770 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 1771 if ((error = re_newbuf(sc, i)) != 0) 1772 return (error); 1773 } 1774 1775 /* Flush the RX descriptors */ 1776 1777 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1778 sc->rl_ldata.rl_rx_list_map, 1779 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1780 1781 sc->rl_ldata.rl_rx_prodidx = 0; 1782 sc->rl_head = sc->rl_tail = NULL; 1783 1784 return (0); 1785 } 1786 1787 /* 1788 * RX handler for C+ and 8169. For the gigE chips, we support 1789 * the reception of jumbo frames that have been fragmented 1790 * across multiple 2K mbuf cluster buffers. 1791 */ 1792 static int 1793 re_rxeof(struct rl_softc *sc) 1794 { 1795 struct mbuf *m; 1796 struct ifnet *ifp; 1797 int i, total_len; 1798 struct rl_desc *cur_rx; 1799 u_int32_t rxstat, rxvlan; 1800 int maxpkt = 16; 1801 1802 RL_LOCK_ASSERT(sc); 1803 1804 ifp = sc->rl_ifp; 1805 1806 /* Invalidate the descriptor memory */ 1807 1808 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1809 sc->rl_ldata.rl_rx_list_map, 1810 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1811 1812 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 1813 i = RL_RX_DESC_NXT(sc, i)) { 1814 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1815 rxstat = le32toh(cur_rx->rl_cmdstat); 1816 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 1817 break; 1818 total_len = rxstat & sc->rl_rxlenmask; 1819 rxvlan = le32toh(cur_rx->rl_vlanctl); 1820 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 1821 1822 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1823 if (re_newbuf(sc, i) != 0) { 1824 /* 1825 * If this is part of a multi-fragment packet, 1826 * discard all the pieces. 1827 */ 1828 if (sc->rl_head != NULL) { 1829 m_freem(sc->rl_head); 1830 sc->rl_head = sc->rl_tail = NULL; 1831 } 1832 re_discard_rxbuf(sc, i); 1833 continue; 1834 } 1835 m->m_len = RE_RX_DESC_BUFLEN; 1836 if (sc->rl_head == NULL) 1837 sc->rl_head = sc->rl_tail = m; 1838 else { 1839 m->m_flags &= ~M_PKTHDR; 1840 sc->rl_tail->m_next = m; 1841 sc->rl_tail = m; 1842 } 1843 continue; 1844 } 1845 1846 /* 1847 * NOTE: for the 8139C+, the frame length field 1848 * is always 12 bits in size, but for the gigE chips, 1849 * it is 13 bits (since the max RX frame length is 16K). 1850 * Unfortunately, all 32 bits in the status word 1851 * were already used, so to make room for the extra 1852 * length bit, RealTek took out the 'frame alignment 1853 * error' bit and shifted the other status bits 1854 * over one slot. The OWN, EOR, FS and LS bits are 1855 * still in the same places. We have already extracted 1856 * the frame length and checked the OWN bit, so rather 1857 * than using an alternate bit mapping, we shift the 1858 * status bits one space to the right so we can evaluate 1859 * them using the 8169 status as though it was in the 1860 * same format as that of the 8139C+. 1861 */ 1862 if (sc->rl_type == RL_8169) 1863 rxstat >>= 1; 1864 1865 /* 1866 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 1867 * set, but if CRC is clear, it will still be a valid frame. 1868 */ 1869 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 && 1870 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) { 1871 ifp->if_ierrors++; 1872 /* 1873 * If this is part of a multi-fragment packet, 1874 * discard all the pieces. 1875 */ 1876 if (sc->rl_head != NULL) { 1877 m_freem(sc->rl_head); 1878 sc->rl_head = sc->rl_tail = NULL; 1879 } 1880 re_discard_rxbuf(sc, i); 1881 continue; 1882 } 1883 1884 /* 1885 * If allocating a replacement mbuf fails, 1886 * reload the current one. 1887 */ 1888 1889 if (re_newbuf(sc, i) != 0) { 1890 ifp->if_iqdrops++; 1891 if (sc->rl_head != NULL) { 1892 m_freem(sc->rl_head); 1893 sc->rl_head = sc->rl_tail = NULL; 1894 } 1895 re_discard_rxbuf(sc, i); 1896 continue; 1897 } 1898 1899 if (sc->rl_head != NULL) { 1900 m->m_len = total_len % RE_RX_DESC_BUFLEN; 1901 if (m->m_len == 0) 1902 m->m_len = RE_RX_DESC_BUFLEN; 1903 /* 1904 * Special case: if there's 4 bytes or less 1905 * in this buffer, the mbuf can be discarded: 1906 * the last 4 bytes is the CRC, which we don't 1907 * care about anyway. 1908 */ 1909 if (m->m_len <= ETHER_CRC_LEN) { 1910 sc->rl_tail->m_len -= 1911 (ETHER_CRC_LEN - m->m_len); 1912 m_freem(m); 1913 } else { 1914 m->m_len -= ETHER_CRC_LEN; 1915 m->m_flags &= ~M_PKTHDR; 1916 sc->rl_tail->m_next = m; 1917 } 1918 m = sc->rl_head; 1919 sc->rl_head = sc->rl_tail = NULL; 1920 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1921 } else 1922 m->m_pkthdr.len = m->m_len = 1923 (total_len - ETHER_CRC_LEN); 1924 1925 #ifdef RE_FIXUP_RX 1926 re_fixup_rx(m); 1927 #endif 1928 ifp->if_ipackets++; 1929 m->m_pkthdr.rcvif = ifp; 1930 1931 /* Do RX checksumming if enabled */ 1932 1933 if (ifp->if_capenable & IFCAP_RXCSUM) { 1934 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 1935 /* Check IP header checksum */ 1936 if (rxstat & RL_RDESC_STAT_PROTOID) 1937 m->m_pkthdr.csum_flags |= 1938 CSUM_IP_CHECKED; 1939 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1940 m->m_pkthdr.csum_flags |= 1941 CSUM_IP_VALID; 1942 1943 /* Check TCP/UDP checksum */ 1944 if ((RL_TCPPKT(rxstat) && 1945 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1946 (RL_UDPPKT(rxstat) && 1947 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1948 m->m_pkthdr.csum_flags |= 1949 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1950 m->m_pkthdr.csum_data = 0xffff; 1951 } 1952 } else { 1953 /* 1954 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP 1955 */ 1956 if ((rxstat & RL_RDESC_STAT_PROTOID) && 1957 (rxvlan & RL_RDESC_IPV4)) 1958 m->m_pkthdr.csum_flags |= 1959 CSUM_IP_CHECKED; 1960 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) && 1961 (rxvlan & RL_RDESC_IPV4)) 1962 m->m_pkthdr.csum_flags |= 1963 CSUM_IP_VALID; 1964 if (((rxstat & RL_RDESC_STAT_TCP) && 1965 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1966 ((rxstat & RL_RDESC_STAT_UDP) && 1967 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1968 m->m_pkthdr.csum_flags |= 1969 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1970 m->m_pkthdr.csum_data = 0xffff; 1971 } 1972 } 1973 } 1974 maxpkt--; 1975 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 1976 m->m_pkthdr.ether_vtag = 1977 bswap16((rxvlan & RL_RDESC_VLANCTL_DATA)); 1978 m->m_flags |= M_VLANTAG; 1979 } 1980 RL_UNLOCK(sc); 1981 (*ifp->if_input)(ifp, m); 1982 RL_LOCK(sc); 1983 } 1984 1985 /* Flush the RX DMA ring */ 1986 1987 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1988 sc->rl_ldata.rl_rx_list_map, 1989 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1990 1991 sc->rl_ldata.rl_rx_prodidx = i; 1992 1993 if (maxpkt) 1994 return(EAGAIN); 1995 1996 return(0); 1997 } 1998 1999 static void 2000 re_txeof(struct rl_softc *sc) 2001 { 2002 struct ifnet *ifp; 2003 struct rl_txdesc *txd; 2004 u_int32_t txstat; 2005 int cons; 2006 2007 cons = sc->rl_ldata.rl_tx_considx; 2008 if (cons == sc->rl_ldata.rl_tx_prodidx) 2009 return; 2010 2011 ifp = sc->rl_ifp; 2012 /* Invalidate the TX descriptor list */ 2013 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2014 sc->rl_ldata.rl_tx_list_map, 2015 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2016 2017 for (; cons != sc->rl_ldata.rl_tx_prodidx; 2018 cons = RL_TX_DESC_NXT(sc, cons)) { 2019 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 2020 if (txstat & RL_TDESC_STAT_OWN) 2021 break; 2022 /* 2023 * We only stash mbufs in the last descriptor 2024 * in a fragment chain, which also happens to 2025 * be the only place where the TX status bits 2026 * are valid. 2027 */ 2028 if (txstat & RL_TDESC_CMD_EOF) { 2029 txd = &sc->rl_ldata.rl_tx_desc[cons]; 2030 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2031 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2032 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2033 txd->tx_dmamap); 2034 KASSERT(txd->tx_m != NULL, 2035 ("%s: freeing NULL mbufs!", __func__)); 2036 m_freem(txd->tx_m); 2037 txd->tx_m = NULL; 2038 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 2039 RL_TDESC_STAT_COLCNT)) 2040 ifp->if_collisions++; 2041 if (txstat & RL_TDESC_STAT_TXERRSUM) 2042 ifp->if_oerrors++; 2043 else 2044 ifp->if_opackets++; 2045 } 2046 sc->rl_ldata.rl_tx_free++; 2047 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2048 } 2049 sc->rl_ldata.rl_tx_considx = cons; 2050 2051 /* No changes made to the TX ring, so no flush needed */ 2052 2053 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 2054 #ifdef RE_TX_MODERATION 2055 /* 2056 * If not all descriptors have been reaped yet, reload 2057 * the timer so that we will eventually get another 2058 * interrupt that will cause us to re-enter this routine. 2059 * This is done in case the transmitter has gone idle. 2060 */ 2061 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2062 #endif 2063 } else 2064 sc->rl_watchdog_timer = 0; 2065 } 2066 2067 static void 2068 re_tick(void *xsc) 2069 { 2070 struct rl_softc *sc; 2071 struct mii_data *mii; 2072 2073 sc = xsc; 2074 2075 RL_LOCK_ASSERT(sc); 2076 2077 mii = device_get_softc(sc->rl_miibus); 2078 mii_tick(mii); 2079 if ((sc->rl_flags & RL_FLAG_LINK) == 0) 2080 re_miibus_statchg(sc->rl_dev); 2081 /* 2082 * Reclaim transmitted frames here. Technically it is not 2083 * necessary to do here but it ensures periodic reclamation 2084 * regardless of Tx completion interrupt which seems to be 2085 * lost on PCIe based controllers under certain situations. 2086 */ 2087 re_txeof(sc); 2088 re_watchdog(sc); 2089 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2090 } 2091 2092 #ifdef DEVICE_POLLING 2093 static void 2094 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2095 { 2096 struct rl_softc *sc = ifp->if_softc; 2097 2098 RL_LOCK(sc); 2099 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2100 re_poll_locked(ifp, cmd, count); 2101 RL_UNLOCK(sc); 2102 } 2103 2104 static void 2105 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2106 { 2107 struct rl_softc *sc = ifp->if_softc; 2108 2109 RL_LOCK_ASSERT(sc); 2110 2111 sc->rxcycles = count; 2112 re_rxeof(sc); 2113 re_txeof(sc); 2114 2115 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2116 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2117 2118 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2119 u_int16_t status; 2120 2121 status = CSR_READ_2(sc, RL_ISR); 2122 if (status == 0xffff) 2123 return; 2124 if (status) 2125 CSR_WRITE_2(sc, RL_ISR, status); 2126 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2127 (sc->rl_flags & RL_FLAG_PCIE)) 2128 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2129 2130 /* 2131 * XXX check behaviour on receiver stalls. 2132 */ 2133 2134 if (status & RL_ISR_SYSTEM_ERR) 2135 re_init_locked(sc); 2136 } 2137 } 2138 #endif /* DEVICE_POLLING */ 2139 2140 static int 2141 re_intr(void *arg) 2142 { 2143 struct rl_softc *sc; 2144 uint16_t status; 2145 2146 sc = arg; 2147 2148 status = CSR_READ_2(sc, RL_ISR); 2149 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2150 return (FILTER_STRAY); 2151 CSR_WRITE_2(sc, RL_IMR, 0); 2152 2153 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2154 2155 return (FILTER_HANDLED); 2156 } 2157 2158 static void 2159 re_int_task(void *arg, int npending) 2160 { 2161 struct rl_softc *sc; 2162 struct ifnet *ifp; 2163 u_int16_t status; 2164 int rval = 0; 2165 2166 sc = arg; 2167 ifp = sc->rl_ifp; 2168 2169 RL_LOCK(sc); 2170 2171 status = CSR_READ_2(sc, RL_ISR); 2172 CSR_WRITE_2(sc, RL_ISR, status); 2173 2174 if (sc->suspended || 2175 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2176 RL_UNLOCK(sc); 2177 return; 2178 } 2179 2180 #ifdef DEVICE_POLLING 2181 if (ifp->if_capenable & IFCAP_POLLING) { 2182 RL_UNLOCK(sc); 2183 return; 2184 } 2185 #endif 2186 2187 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2188 rval = re_rxeof(sc); 2189 2190 /* 2191 * Some chips will ignore a second TX request issued 2192 * while an existing transmission is in progress. If 2193 * the transmitter goes idle but there are still 2194 * packets waiting to be sent, we need to restart the 2195 * channel here to flush them out. This only seems to 2196 * be required with the PCIe devices. 2197 */ 2198 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2199 (sc->rl_flags & RL_FLAG_PCIE)) 2200 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2201 if (status & ( 2202 #ifdef RE_TX_MODERATION 2203 RL_ISR_TIMEOUT_EXPIRED| 2204 #else 2205 RL_ISR_TX_OK| 2206 #endif 2207 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2208 re_txeof(sc); 2209 2210 if (status & RL_ISR_SYSTEM_ERR) 2211 re_init_locked(sc); 2212 2213 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2214 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2215 2216 RL_UNLOCK(sc); 2217 2218 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2219 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2220 return; 2221 } 2222 2223 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2224 } 2225 2226 static int 2227 re_encap(struct rl_softc *sc, struct mbuf **m_head) 2228 { 2229 struct rl_txdesc *txd, *txd_last; 2230 bus_dma_segment_t segs[RL_NTXSEGS]; 2231 bus_dmamap_t map; 2232 struct mbuf *m_new; 2233 struct rl_desc *desc; 2234 int nsegs, prod; 2235 int i, error, ei, si; 2236 int padlen; 2237 uint32_t cmdstat, csum_flags, vlanctl; 2238 2239 RL_LOCK_ASSERT(sc); 2240 M_ASSERTPKTHDR((*m_head)); 2241 2242 /* 2243 * With some of the RealTek chips, using the checksum offload 2244 * support in conjunction with the autopadding feature results 2245 * in the transmission of corrupt frames. For example, if we 2246 * need to send a really small IP fragment that's less than 60 2247 * bytes in size, and IP header checksumming is enabled, the 2248 * resulting ethernet frame that appears on the wire will 2249 * have garbled payload. To work around this, if TX IP checksum 2250 * offload is enabled, we always manually pad short frames out 2251 * to the minimum ethernet frame size. 2252 */ 2253 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0 && 2254 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN && 2255 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) { 2256 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2257 if (M_WRITABLE(*m_head) == 0) { 2258 /* Get a writable copy. */ 2259 m_new = m_dup(*m_head, M_DONTWAIT); 2260 m_freem(*m_head); 2261 if (m_new == NULL) { 2262 *m_head = NULL; 2263 return (ENOBUFS); 2264 } 2265 *m_head = m_new; 2266 } 2267 if ((*m_head)->m_next != NULL || 2268 M_TRAILINGSPACE(*m_head) < padlen) { 2269 m_new = m_defrag(*m_head, M_DONTWAIT); 2270 if (m_new == NULL) { 2271 m_freem(*m_head); 2272 *m_head = NULL; 2273 return (ENOBUFS); 2274 } 2275 } else 2276 m_new = *m_head; 2277 2278 /* 2279 * Manually pad short frames, and zero the pad space 2280 * to avoid leaking data. 2281 */ 2282 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2283 m_new->m_pkthdr.len += padlen; 2284 m_new->m_len = m_new->m_pkthdr.len; 2285 *m_head = m_new; 2286 } 2287 2288 prod = sc->rl_ldata.rl_tx_prodidx; 2289 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2290 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2291 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2292 if (error == EFBIG) { 2293 m_new = m_collapse(*m_head, M_DONTWAIT, RL_NTXSEGS); 2294 if (m_new == NULL) { 2295 m_freem(*m_head); 2296 *m_head = NULL; 2297 return (ENOBUFS); 2298 } 2299 *m_head = m_new; 2300 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2301 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2302 if (error != 0) { 2303 m_freem(*m_head); 2304 *m_head = NULL; 2305 return (error); 2306 } 2307 } else if (error != 0) 2308 return (error); 2309 if (nsegs == 0) { 2310 m_freem(*m_head); 2311 *m_head = NULL; 2312 return (EIO); 2313 } 2314 2315 /* Check for number of available descriptors. */ 2316 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2317 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2318 return (ENOBUFS); 2319 } 2320 2321 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2322 BUS_DMASYNC_PREWRITE); 2323 2324 /* 2325 * Set up checksum offload. Note: checksum offload bits must 2326 * appear in all descriptors of a multi-descriptor transmit 2327 * attempt. This is according to testing done with an 8169 2328 * chip. This is a requirement. 2329 */ 2330 vlanctl = 0; 2331 csum_flags = 0; 2332 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) 2333 csum_flags = RL_TDESC_CMD_LGSEND | 2334 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2335 RL_TDESC_CMD_MSSVAL_SHIFT); 2336 else { 2337 /* 2338 * Unconditionally enable IP checksum if TCP or UDP 2339 * checksum is required. Otherwise, TCP/UDP checksum 2340 * does't make effects. 2341 */ 2342 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) { 2343 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2344 csum_flags |= RL_TDESC_CMD_IPCSUM; 2345 if (((*m_head)->m_pkthdr.csum_flags & 2346 CSUM_TCP) != 0) 2347 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2348 if (((*m_head)->m_pkthdr.csum_flags & 2349 CSUM_UDP) != 0) 2350 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2351 } else { 2352 vlanctl |= RL_TDESC_CMD_IPCSUMV2; 2353 if (((*m_head)->m_pkthdr.csum_flags & 2354 CSUM_TCP) != 0) 2355 vlanctl |= RL_TDESC_CMD_TCPCSUMV2; 2356 if (((*m_head)->m_pkthdr.csum_flags & 2357 CSUM_UDP) != 0) 2358 vlanctl |= RL_TDESC_CMD_UDPCSUMV2; 2359 } 2360 } 2361 } 2362 2363 /* 2364 * Set up hardware VLAN tagging. Note: vlan tag info must 2365 * appear in all descriptors of a multi-descriptor 2366 * transmission attempt. 2367 */ 2368 if ((*m_head)->m_flags & M_VLANTAG) 2369 vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) | 2370 RL_TDESC_VLANCTL_TAG; 2371 2372 si = prod; 2373 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2374 desc = &sc->rl_ldata.rl_tx_list[prod]; 2375 desc->rl_vlanctl = htole32(vlanctl); 2376 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2377 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2378 cmdstat = segs[i].ds_len; 2379 if (i != 0) 2380 cmdstat |= RL_TDESC_CMD_OWN; 2381 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2382 cmdstat |= RL_TDESC_CMD_EOR; 2383 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2384 sc->rl_ldata.rl_tx_free--; 2385 } 2386 /* Update producer index. */ 2387 sc->rl_ldata.rl_tx_prodidx = prod; 2388 2389 /* Set EOF on the last descriptor. */ 2390 ei = RL_TX_DESC_PRV(sc, prod); 2391 desc = &sc->rl_ldata.rl_tx_list[ei]; 2392 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2393 2394 desc = &sc->rl_ldata.rl_tx_list[si]; 2395 /* Set SOF and transfer ownership of packet to the chip. */ 2396 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2397 2398 /* 2399 * Insure that the map for this transmission 2400 * is placed at the array index of the last descriptor 2401 * in this chain. (Swap last and first dmamaps.) 2402 */ 2403 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2404 map = txd->tx_dmamap; 2405 txd->tx_dmamap = txd_last->tx_dmamap; 2406 txd_last->tx_dmamap = map; 2407 txd_last->tx_m = *m_head; 2408 2409 return (0); 2410 } 2411 2412 static void 2413 re_tx_task(void *arg, int npending) 2414 { 2415 struct ifnet *ifp; 2416 2417 ifp = arg; 2418 re_start(ifp); 2419 } 2420 2421 /* 2422 * Main transmit routine for C+ and gigE NICs. 2423 */ 2424 static void 2425 re_start(struct ifnet *ifp) 2426 { 2427 struct rl_softc *sc; 2428 struct mbuf *m_head; 2429 int queued; 2430 2431 sc = ifp->if_softc; 2432 2433 RL_LOCK(sc); 2434 2435 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2436 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) { 2437 RL_UNLOCK(sc); 2438 return; 2439 } 2440 2441 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2442 sc->rl_ldata.rl_tx_free > 1;) { 2443 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2444 if (m_head == NULL) 2445 break; 2446 2447 if (re_encap(sc, &m_head) != 0) { 2448 if (m_head == NULL) 2449 break; 2450 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2451 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2452 break; 2453 } 2454 2455 /* 2456 * If there's a BPF listener, bounce a copy of this frame 2457 * to him. 2458 */ 2459 ETHER_BPF_MTAP(ifp, m_head); 2460 2461 queued++; 2462 } 2463 2464 if (queued == 0) { 2465 #ifdef RE_TX_MODERATION 2466 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2467 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2468 #endif 2469 RL_UNLOCK(sc); 2470 return; 2471 } 2472 2473 /* Flush the TX descriptors */ 2474 2475 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2476 sc->rl_ldata.rl_tx_list_map, 2477 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2478 2479 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2480 2481 #ifdef RE_TX_MODERATION 2482 /* 2483 * Use the countdown timer for interrupt moderation. 2484 * 'TX done' interrupts are disabled. Instead, we reset the 2485 * countdown timer, which will begin counting until it hits 2486 * the value in the TIMERINT register, and then trigger an 2487 * interrupt. Each time we write to the TIMERCNT register, 2488 * the timer count is reset to 0. 2489 */ 2490 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2491 #endif 2492 2493 /* 2494 * Set a timeout in case the chip goes out to lunch. 2495 */ 2496 sc->rl_watchdog_timer = 5; 2497 2498 RL_UNLOCK(sc); 2499 } 2500 2501 static void 2502 re_init(void *xsc) 2503 { 2504 struct rl_softc *sc = xsc; 2505 2506 RL_LOCK(sc); 2507 re_init_locked(sc); 2508 RL_UNLOCK(sc); 2509 } 2510 2511 static void 2512 re_init_locked(struct rl_softc *sc) 2513 { 2514 struct ifnet *ifp = sc->rl_ifp; 2515 struct mii_data *mii; 2516 uint32_t reg; 2517 uint16_t cfg; 2518 union { 2519 uint32_t align_dummy; 2520 u_char eaddr[ETHER_ADDR_LEN]; 2521 } eaddr; 2522 2523 RL_LOCK_ASSERT(sc); 2524 2525 mii = device_get_softc(sc->rl_miibus); 2526 2527 /* 2528 * Cancel pending I/O and free all RX/TX buffers. 2529 */ 2530 re_stop(sc); 2531 2532 /* Put controller into known state. */ 2533 re_reset(sc); 2534 2535 /* 2536 * Enable C+ RX and TX mode, as well as VLAN stripping and 2537 * RX checksum offload. We must configure the C+ register 2538 * before all others. 2539 */ 2540 cfg = RL_CPLUSCMD_PCI_MRW; 2541 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2542 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 2543 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2544 cfg |= RL_CPLUSCMD_VLANSTRIP; 2545 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) { 2546 cfg |= RL_CPLUSCMD_MACSTAT_DIS; 2547 /* XXX magic. */ 2548 cfg |= 0x0001; 2549 } else 2550 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB; 2551 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg); 2552 if (sc->rl_hwrev == RL_HWREV_8169_8110SC || 2553 sc->rl_hwrev == RL_HWREV_8169_8110SCE) { 2554 reg = 0x000fff00; 2555 if ((CSR_READ_1(sc, RL_CFG2) & RL_CFG2_PCI66MHZ) != 0) 2556 reg |= 0x000000ff; 2557 if (sc->rl_hwrev == RL_HWREV_8169_8110SCE) 2558 reg |= 0x00f00000; 2559 CSR_WRITE_4(sc, 0x7c, reg); 2560 /* Disable interrupt mitigation. */ 2561 CSR_WRITE_2(sc, 0xe2, 0); 2562 } 2563 /* 2564 * Disable TSO if interface MTU size is greater than MSS 2565 * allowed in controller. 2566 */ 2567 if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) { 2568 ifp->if_capenable &= ~IFCAP_TSO4; 2569 ifp->if_hwassist &= ~CSUM_TSO; 2570 } 2571 2572 /* 2573 * Init our MAC address. Even though the chipset 2574 * documentation doesn't mention it, we need to enter "Config 2575 * register write enable" mode to modify the ID registers. 2576 */ 2577 /* Copy MAC address on stack to align. */ 2578 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 2579 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2580 CSR_WRITE_4(sc, RL_IDR0, 2581 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 2582 CSR_WRITE_4(sc, RL_IDR4, 2583 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 2584 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2585 2586 /* 2587 * For C+ mode, initialize the RX descriptors and mbufs. 2588 */ 2589 re_rx_list_init(sc); 2590 re_tx_list_init(sc); 2591 2592 /* 2593 * Load the addresses of the RX and TX lists into the chip. 2594 */ 2595 2596 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2597 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2598 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2599 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2600 2601 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2602 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2603 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2604 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2605 2606 /* 2607 * Enable transmit and receive. 2608 */ 2609 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2610 2611 /* 2612 * Set the initial TX configuration. 2613 */ 2614 if (sc->rl_testmode) { 2615 if (sc->rl_type == RL_8169) 2616 CSR_WRITE_4(sc, RL_TXCFG, 2617 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2618 else 2619 CSR_WRITE_4(sc, RL_TXCFG, 2620 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2621 } else 2622 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2623 2624 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2625 2626 /* 2627 * Set the initial RX configuration. 2628 */ 2629 re_set_rxmode(sc); 2630 2631 #ifdef DEVICE_POLLING 2632 /* 2633 * Disable interrupts if we are polling. 2634 */ 2635 if (ifp->if_capenable & IFCAP_POLLING) 2636 CSR_WRITE_2(sc, RL_IMR, 0); 2637 else /* otherwise ... */ 2638 #endif 2639 2640 /* 2641 * Enable interrupts. 2642 */ 2643 if (sc->rl_testmode) 2644 CSR_WRITE_2(sc, RL_IMR, 0); 2645 else 2646 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2647 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 2648 2649 /* Set initial TX threshold */ 2650 sc->rl_txthresh = RL_TX_THRESH_INIT; 2651 2652 /* Start RX/TX process. */ 2653 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2654 #ifdef notdef 2655 /* Enable receiver and transmitter. */ 2656 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2657 #endif 2658 2659 #ifdef RE_TX_MODERATION 2660 /* 2661 * Initialize the timer interrupt register so that 2662 * a timer interrupt will be generated once the timer 2663 * reaches a certain number of ticks. The timer is 2664 * reloaded on each transmit. This gives us TX interrupt 2665 * moderation, which dramatically improves TX frame rate. 2666 */ 2667 if (sc->rl_type == RL_8169) 2668 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2669 else 2670 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2671 #endif 2672 2673 /* 2674 * For 8169 gigE NICs, set the max allowed RX packet 2675 * size so we can receive jumbo frames. 2676 */ 2677 if (sc->rl_type == RL_8169) 2678 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2679 2680 if (sc->rl_testmode) 2681 return; 2682 2683 mii_mediachg(mii); 2684 2685 CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD); 2686 2687 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2688 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2689 2690 sc->rl_flags &= ~RL_FLAG_LINK; 2691 sc->rl_watchdog_timer = 0; 2692 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2693 } 2694 2695 /* 2696 * Set media options. 2697 */ 2698 static int 2699 re_ifmedia_upd(struct ifnet *ifp) 2700 { 2701 struct rl_softc *sc; 2702 struct mii_data *mii; 2703 int error; 2704 2705 sc = ifp->if_softc; 2706 mii = device_get_softc(sc->rl_miibus); 2707 RL_LOCK(sc); 2708 error = mii_mediachg(mii); 2709 RL_UNLOCK(sc); 2710 2711 return (error); 2712 } 2713 2714 /* 2715 * Report current media status. 2716 */ 2717 static void 2718 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2719 { 2720 struct rl_softc *sc; 2721 struct mii_data *mii; 2722 2723 sc = ifp->if_softc; 2724 mii = device_get_softc(sc->rl_miibus); 2725 2726 RL_LOCK(sc); 2727 mii_pollstat(mii); 2728 RL_UNLOCK(sc); 2729 ifmr->ifm_active = mii->mii_media_active; 2730 ifmr->ifm_status = mii->mii_media_status; 2731 } 2732 2733 static int 2734 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2735 { 2736 struct rl_softc *sc = ifp->if_softc; 2737 struct ifreq *ifr = (struct ifreq *) data; 2738 struct mii_data *mii; 2739 int error = 0; 2740 2741 switch (command) { 2742 case SIOCSIFMTU: 2743 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > RL_JUMBO_MTU) { 2744 error = EINVAL; 2745 break; 2746 } 2747 if ((sc->rl_flags & RL_FLAG_NOJUMBO) != 0 && 2748 ifr->ifr_mtu > RL_MAX_FRAMELEN) { 2749 error = EINVAL; 2750 break; 2751 } 2752 RL_LOCK(sc); 2753 if (ifp->if_mtu != ifr->ifr_mtu) 2754 ifp->if_mtu = ifr->ifr_mtu; 2755 if (ifp->if_mtu > RL_TSO_MTU && 2756 (ifp->if_capenable & IFCAP_TSO4) != 0) { 2757 ifp->if_capenable &= ~IFCAP_TSO4; 2758 ifp->if_hwassist &= ~CSUM_TSO; 2759 } 2760 RL_UNLOCK(sc); 2761 break; 2762 case SIOCSIFFLAGS: 2763 RL_LOCK(sc); 2764 if ((ifp->if_flags & IFF_UP) != 0) { 2765 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2766 if (((ifp->if_flags ^ sc->rl_if_flags) 2767 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2768 re_set_rxmode(sc); 2769 } else 2770 re_init_locked(sc); 2771 } else { 2772 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2773 re_stop(sc); 2774 } 2775 sc->rl_if_flags = ifp->if_flags; 2776 RL_UNLOCK(sc); 2777 break; 2778 case SIOCADDMULTI: 2779 case SIOCDELMULTI: 2780 RL_LOCK(sc); 2781 re_set_rxmode(sc); 2782 RL_UNLOCK(sc); 2783 break; 2784 case SIOCGIFMEDIA: 2785 case SIOCSIFMEDIA: 2786 mii = device_get_softc(sc->rl_miibus); 2787 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2788 break; 2789 case SIOCSIFCAP: 2790 { 2791 int mask, reinit; 2792 2793 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2794 reinit = 0; 2795 #ifdef DEVICE_POLLING 2796 if (mask & IFCAP_POLLING) { 2797 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2798 error = ether_poll_register(re_poll, ifp); 2799 if (error) 2800 return(error); 2801 RL_LOCK(sc); 2802 /* Disable interrupts */ 2803 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2804 ifp->if_capenable |= IFCAP_POLLING; 2805 RL_UNLOCK(sc); 2806 } else { 2807 error = ether_poll_deregister(ifp); 2808 /* Enable interrupts. */ 2809 RL_LOCK(sc); 2810 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2811 ifp->if_capenable &= ~IFCAP_POLLING; 2812 RL_UNLOCK(sc); 2813 } 2814 } 2815 #endif /* DEVICE_POLLING */ 2816 if (mask & IFCAP_HWCSUM) { 2817 ifp->if_capenable ^= IFCAP_HWCSUM; 2818 if (ifp->if_capenable & IFCAP_TXCSUM) 2819 ifp->if_hwassist |= RE_CSUM_FEATURES; 2820 else 2821 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 2822 reinit = 1; 2823 } 2824 if (mask & IFCAP_VLAN_HWTAGGING) { 2825 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2826 reinit = 1; 2827 } 2828 if (mask & IFCAP_TSO4) { 2829 ifp->if_capenable ^= IFCAP_TSO4; 2830 if ((IFCAP_TSO4 & ifp->if_capenable) && 2831 (IFCAP_TSO4 & ifp->if_capabilities)) 2832 ifp->if_hwassist |= CSUM_TSO; 2833 else 2834 ifp->if_hwassist &= ~CSUM_TSO; 2835 if (ifp->if_mtu > RL_TSO_MTU && 2836 (ifp->if_capenable & IFCAP_TSO4) != 0) { 2837 ifp->if_capenable &= ~IFCAP_TSO4; 2838 ifp->if_hwassist &= ~CSUM_TSO; 2839 } 2840 } 2841 if ((mask & IFCAP_WOL) != 0 && 2842 (ifp->if_capabilities & IFCAP_WOL) != 0) { 2843 if ((mask & IFCAP_WOL_UCAST) != 0) 2844 ifp->if_capenable ^= IFCAP_WOL_UCAST; 2845 if ((mask & IFCAP_WOL_MCAST) != 0) 2846 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2847 if ((mask & IFCAP_WOL_MAGIC) != 0) 2848 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2849 } 2850 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) 2851 re_init(sc); 2852 VLAN_CAPABILITIES(ifp); 2853 } 2854 break; 2855 default: 2856 error = ether_ioctl(ifp, command, data); 2857 break; 2858 } 2859 2860 return (error); 2861 } 2862 2863 static void 2864 re_watchdog(struct rl_softc *sc) 2865 { 2866 struct ifnet *ifp; 2867 2868 RL_LOCK_ASSERT(sc); 2869 2870 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 2871 return; 2872 2873 ifp = sc->rl_ifp; 2874 re_txeof(sc); 2875 if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) { 2876 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 2877 "-- recovering\n"); 2878 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2879 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2880 return; 2881 } 2882 2883 if_printf(ifp, "watchdog timeout\n"); 2884 ifp->if_oerrors++; 2885 2886 re_rxeof(sc); 2887 re_init_locked(sc); 2888 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2889 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2890 } 2891 2892 /* 2893 * Stop the adapter and free any mbufs allocated to the 2894 * RX and TX lists. 2895 */ 2896 static void 2897 re_stop(struct rl_softc *sc) 2898 { 2899 int i; 2900 struct ifnet *ifp; 2901 struct rl_txdesc *txd; 2902 struct rl_rxdesc *rxd; 2903 2904 RL_LOCK_ASSERT(sc); 2905 2906 ifp = sc->rl_ifp; 2907 2908 sc->rl_watchdog_timer = 0; 2909 callout_stop(&sc->rl_stat_callout); 2910 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2911 2912 if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0) 2913 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB | 2914 RL_CMD_RX_ENB); 2915 else 2916 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2917 DELAY(1000); 2918 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2919 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 2920 2921 if (sc->rl_head != NULL) { 2922 m_freem(sc->rl_head); 2923 sc->rl_head = sc->rl_tail = NULL; 2924 } 2925 2926 /* Free the TX list buffers. */ 2927 2928 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 2929 txd = &sc->rl_ldata.rl_tx_desc[i]; 2930 if (txd->tx_m != NULL) { 2931 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2932 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2933 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2934 txd->tx_dmamap); 2935 m_freem(txd->tx_m); 2936 txd->tx_m = NULL; 2937 } 2938 } 2939 2940 /* Free the RX list buffers. */ 2941 2942 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2943 rxd = &sc->rl_ldata.rl_rx_desc[i]; 2944 if (rxd->rx_m != NULL) { 2945 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2946 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2947 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 2948 rxd->rx_dmamap); 2949 m_freem(rxd->rx_m); 2950 rxd->rx_m = NULL; 2951 } 2952 } 2953 } 2954 2955 /* 2956 * Device suspend routine. Stop the interface and save some PCI 2957 * settings in case the BIOS doesn't restore them properly on 2958 * resume. 2959 */ 2960 static int 2961 re_suspend(device_t dev) 2962 { 2963 struct rl_softc *sc; 2964 2965 sc = device_get_softc(dev); 2966 2967 RL_LOCK(sc); 2968 re_stop(sc); 2969 re_setwol(sc); 2970 sc->suspended = 1; 2971 RL_UNLOCK(sc); 2972 2973 return (0); 2974 } 2975 2976 /* 2977 * Device resume routine. Restore some PCI settings in case the BIOS 2978 * doesn't, re-enable busmastering, and restart the interface if 2979 * appropriate. 2980 */ 2981 static int 2982 re_resume(device_t dev) 2983 { 2984 struct rl_softc *sc; 2985 struct ifnet *ifp; 2986 2987 sc = device_get_softc(dev); 2988 2989 RL_LOCK(sc); 2990 2991 ifp = sc->rl_ifp; 2992 /* Take controller out of sleep mode. */ 2993 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 2994 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 2995 CSR_WRITE_1(sc, RL_GPIO, 2996 CSR_READ_1(sc, RL_GPIO) | 0x01); 2997 } 2998 2999 /* reinitialize interface if necessary */ 3000 if (ifp->if_flags & IFF_UP) 3001 re_init_locked(sc); 3002 3003 /* 3004 * Clear WOL matching such that normal Rx filtering 3005 * wouldn't interfere with WOL patterns. 3006 */ 3007 re_clrwol(sc); 3008 sc->suspended = 0; 3009 RL_UNLOCK(sc); 3010 3011 return (0); 3012 } 3013 3014 /* 3015 * Stop all chip I/O so that the kernel's probe routines don't 3016 * get confused by errant DMAs when rebooting. 3017 */ 3018 static int 3019 re_shutdown(device_t dev) 3020 { 3021 struct rl_softc *sc; 3022 3023 sc = device_get_softc(dev); 3024 3025 RL_LOCK(sc); 3026 re_stop(sc); 3027 /* 3028 * Mark interface as down since otherwise we will panic if 3029 * interrupt comes in later on, which can happen in some 3030 * cases. 3031 */ 3032 sc->rl_ifp->if_flags &= ~IFF_UP; 3033 re_setwol(sc); 3034 RL_UNLOCK(sc); 3035 3036 return (0); 3037 } 3038 3039 static void 3040 re_setwol(struct rl_softc *sc) 3041 { 3042 struct ifnet *ifp; 3043 int pmc; 3044 uint16_t pmstat; 3045 uint8_t v; 3046 3047 RL_LOCK_ASSERT(sc); 3048 3049 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3050 return; 3051 3052 ifp = sc->rl_ifp; 3053 /* Put controller into sleep mode. */ 3054 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3055 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3056 CSR_WRITE_1(sc, RL_GPIO, 3057 CSR_READ_1(sc, RL_GPIO) & ~0x01); 3058 } 3059 if ((ifp->if_capenable & IFCAP_WOL) != 0 && 3060 (sc->rl_flags & RL_FLAG_WOLRXENB) != 0) 3061 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB); 3062 /* Enable config register write. */ 3063 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3064 3065 /* Enable PME. */ 3066 v = CSR_READ_1(sc, RL_CFG1); 3067 v &= ~RL_CFG1_PME; 3068 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3069 v |= RL_CFG1_PME; 3070 CSR_WRITE_1(sc, RL_CFG1, v); 3071 3072 v = CSR_READ_1(sc, RL_CFG3); 3073 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3074 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3075 v |= RL_CFG3_WOL_MAGIC; 3076 CSR_WRITE_1(sc, RL_CFG3, v); 3077 3078 /* Config register write done. */ 3079 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3080 3081 v = CSR_READ_1(sc, RL_CFG5); 3082 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3083 v &= ~RL_CFG5_WOL_LANWAKE; 3084 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 3085 v |= RL_CFG5_WOL_UCAST; 3086 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 3087 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 3088 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3089 v |= RL_CFG5_WOL_LANWAKE; 3090 CSR_WRITE_1(sc, RL_CFG5, v); 3091 3092 /* 3093 * It seems that hardware resets its link speed to 100Mbps in 3094 * power down mode so switching to 100Mbps in driver is not 3095 * needed. 3096 */ 3097 3098 /* Request PME if WOL is requested. */ 3099 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 3100 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3101 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3102 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3103 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 3104 } 3105 3106 static void 3107 re_clrwol(struct rl_softc *sc) 3108 { 3109 int pmc; 3110 uint8_t v; 3111 3112 RL_LOCK_ASSERT(sc); 3113 3114 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3115 return; 3116 3117 /* Enable config register write. */ 3118 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3119 3120 v = CSR_READ_1(sc, RL_CFG3); 3121 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3122 CSR_WRITE_1(sc, RL_CFG3, v); 3123 3124 /* Config register write done. */ 3125 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3126 3127 v = CSR_READ_1(sc, RL_CFG5); 3128 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3129 v &= ~RL_CFG5_WOL_LANWAKE; 3130 CSR_WRITE_1(sc, RL_CFG5, v); 3131 } 3132