1 /*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44 /* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111 #ifdef HAVE_KERNEL_OPTION_HEADERS 112 #include "opt_device_polling.h" 113 #endif 114 115 #include <sys/param.h> 116 #include <sys/endian.h> 117 #include <sys/systm.h> 118 #include <sys/sockio.h> 119 #include <sys/mbuf.h> 120 #include <sys/malloc.h> 121 #include <sys/module.h> 122 #include <sys/kernel.h> 123 #include <sys/socket.h> 124 #include <sys/lock.h> 125 #include <sys/mutex.h> 126 #include <sys/taskqueue.h> 127 128 #include <net/if.h> 129 #include <net/if_arp.h> 130 #include <net/ethernet.h> 131 #include <net/if_dl.h> 132 #include <net/if_media.h> 133 #include <net/if_types.h> 134 #include <net/if_vlan_var.h> 135 136 #include <net/bpf.h> 137 138 #include <machine/bus.h> 139 #include <machine/resource.h> 140 #include <sys/bus.h> 141 #include <sys/rman.h> 142 143 #include <dev/mii/mii.h> 144 #include <dev/mii/miivar.h> 145 146 #include <dev/pci/pcireg.h> 147 #include <dev/pci/pcivar.h> 148 149 #include <pci/if_rlreg.h> 150 151 MODULE_DEPEND(re, pci, 1, 1, 1); 152 MODULE_DEPEND(re, ether, 1, 1, 1); 153 MODULE_DEPEND(re, miibus, 1, 1, 1); 154 155 /* "device miibus" required. See GENERIC if you get errors here. */ 156 #include "miibus_if.h" 157 158 /* Tunables. */ 159 static int msi_disable = 0; 160 TUNABLE_INT("hw.re.msi_disable", &msi_disable); 161 162 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 163 164 /* 165 * Various supported device vendors/types and their names. 166 */ 167 static struct rl_type re_devs[] = { 168 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0, 169 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 170 { RT_VENDORID, RT_DEVICEID_8139, 0, 171 "RealTek 8139C+ 10/100BaseTX" }, 172 { RT_VENDORID, RT_DEVICEID_8101E, 0, 173 "RealTek 8101E/8102E/8102EL PCIe 10/100baseTX" }, 174 { RT_VENDORID, RT_DEVICEID_8168, 0, 175 "RealTek 8168/8168B/8168C/8168CP/8168D/8111B/8111C/8111CP PCIe " 176 "Gigabit Ethernet" }, 177 { RT_VENDORID, RT_DEVICEID_8169, 0, 178 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" }, 179 { RT_VENDORID, RT_DEVICEID_8169SC, 0, 180 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 181 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0, 182 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 183 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0, 184 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 185 { USR_VENDORID, USR_DEVICEID_997902, 0, 186 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 187 }; 188 189 static struct rl_hwrev re_hwrevs[] = { 190 { RL_HWREV_8139, RL_8139, "" }, 191 { RL_HWREV_8139A, RL_8139, "A" }, 192 { RL_HWREV_8139AG, RL_8139, "A-G" }, 193 { RL_HWREV_8139B, RL_8139, "B" }, 194 { RL_HWREV_8130, RL_8139, "8130" }, 195 { RL_HWREV_8139C, RL_8139, "C" }, 196 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 197 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 198 { RL_HWREV_8168_SPIN1, RL_8169, "8168"}, 199 { RL_HWREV_8169, RL_8169, "8169"}, 200 { RL_HWREV_8169S, RL_8169, "8169S"}, 201 { RL_HWREV_8110S, RL_8169, "8110S"}, 202 { RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB"}, 203 { RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC"}, 204 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL"}, 205 { RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC"}, 206 { RL_HWREV_8100, RL_8139, "8100"}, 207 { RL_HWREV_8101, RL_8139, "8101"}, 208 { RL_HWREV_8100E, RL_8169, "8100E"}, 209 { RL_HWREV_8101E, RL_8169, "8101E"}, 210 { RL_HWREV_8102E, RL_8169, "8102E"}, 211 { RL_HWREV_8102EL, RL_8169, "8102EL"}, 212 { RL_HWREV_8168_SPIN2, RL_8169, "8168"}, 213 { RL_HWREV_8168_SPIN3, RL_8169, "8168"}, 214 { RL_HWREV_8168C, RL_8169, "8168C/8111C"}, 215 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C"}, 216 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP"}, 217 { RL_HWREV_8168D, RL_8169, "8168D"}, 218 { 0, 0, NULL } 219 }; 220 221 static int re_probe (device_t); 222 static int re_attach (device_t); 223 static int re_detach (device_t); 224 225 static int re_encap (struct rl_softc *, struct mbuf **); 226 227 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 228 static int re_allocmem (device_t, struct rl_softc *); 229 static __inline void re_discard_rxbuf 230 (struct rl_softc *, int); 231 static int re_newbuf (struct rl_softc *, int); 232 static int re_rx_list_init (struct rl_softc *); 233 static int re_tx_list_init (struct rl_softc *); 234 #ifdef RE_FIXUP_RX 235 static __inline void re_fixup_rx 236 (struct mbuf *); 237 #endif 238 static int re_rxeof (struct rl_softc *); 239 static void re_txeof (struct rl_softc *); 240 #ifdef DEVICE_POLLING 241 static void re_poll (struct ifnet *, enum poll_cmd, int); 242 static void re_poll_locked (struct ifnet *, enum poll_cmd, int); 243 #endif 244 static int re_intr (void *); 245 static void re_tick (void *); 246 static void re_tx_task (void *, int); 247 static void re_int_task (void *, int); 248 static void re_start (struct ifnet *); 249 static int re_ioctl (struct ifnet *, u_long, caddr_t); 250 static void re_init (void *); 251 static void re_init_locked (struct rl_softc *); 252 static void re_stop (struct rl_softc *); 253 static void re_watchdog (struct rl_softc *); 254 static int re_suspend (device_t); 255 static int re_resume (device_t); 256 static int re_shutdown (device_t); 257 static int re_ifmedia_upd (struct ifnet *); 258 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 259 260 static void re_eeprom_putbyte (struct rl_softc *, int); 261 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 262 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 263 static int re_gmii_readreg (device_t, int, int); 264 static int re_gmii_writereg (device_t, int, int, int); 265 266 static int re_miibus_readreg (device_t, int, int); 267 static int re_miibus_writereg (device_t, int, int, int); 268 static void re_miibus_statchg (device_t); 269 270 static void re_set_rxmode (struct rl_softc *); 271 static void re_reset (struct rl_softc *); 272 static void re_setwol (struct rl_softc *); 273 static void re_clrwol (struct rl_softc *); 274 275 #ifdef RE_DIAG 276 static int re_diag (struct rl_softc *); 277 #endif 278 279 static device_method_t re_methods[] = { 280 /* Device interface */ 281 DEVMETHOD(device_probe, re_probe), 282 DEVMETHOD(device_attach, re_attach), 283 DEVMETHOD(device_detach, re_detach), 284 DEVMETHOD(device_suspend, re_suspend), 285 DEVMETHOD(device_resume, re_resume), 286 DEVMETHOD(device_shutdown, re_shutdown), 287 288 /* bus interface */ 289 DEVMETHOD(bus_print_child, bus_generic_print_child), 290 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 291 292 /* MII interface */ 293 DEVMETHOD(miibus_readreg, re_miibus_readreg), 294 DEVMETHOD(miibus_writereg, re_miibus_writereg), 295 DEVMETHOD(miibus_statchg, re_miibus_statchg), 296 297 { 0, 0 } 298 }; 299 300 static driver_t re_driver = { 301 "re", 302 re_methods, 303 sizeof(struct rl_softc) 304 }; 305 306 static devclass_t re_devclass; 307 308 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 309 DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0); 310 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 311 312 #define EE_SET(x) \ 313 CSR_WRITE_1(sc, RL_EECMD, \ 314 CSR_READ_1(sc, RL_EECMD) | x) 315 316 #define EE_CLR(x) \ 317 CSR_WRITE_1(sc, RL_EECMD, \ 318 CSR_READ_1(sc, RL_EECMD) & ~x) 319 320 /* 321 * Send a read command and address to the EEPROM, check for ACK. 322 */ 323 static void 324 re_eeprom_putbyte(struct rl_softc *sc, int addr) 325 { 326 int d, i; 327 328 d = addr | (RL_9346_READ << sc->rl_eewidth); 329 330 /* 331 * Feed in each bit and strobe the clock. 332 */ 333 334 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 335 if (d & i) { 336 EE_SET(RL_EE_DATAIN); 337 } else { 338 EE_CLR(RL_EE_DATAIN); 339 } 340 DELAY(100); 341 EE_SET(RL_EE_CLK); 342 DELAY(150); 343 EE_CLR(RL_EE_CLK); 344 DELAY(100); 345 } 346 } 347 348 /* 349 * Read a word of data stored in the EEPROM at address 'addr.' 350 */ 351 static void 352 re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest) 353 { 354 int i; 355 u_int16_t word = 0; 356 357 /* 358 * Send address of word we want to read. 359 */ 360 re_eeprom_putbyte(sc, addr); 361 362 /* 363 * Start reading bits from EEPROM. 364 */ 365 for (i = 0x8000; i; i >>= 1) { 366 EE_SET(RL_EE_CLK); 367 DELAY(100); 368 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 369 word |= i; 370 EE_CLR(RL_EE_CLK); 371 DELAY(100); 372 } 373 374 *dest = word; 375 } 376 377 /* 378 * Read a sequence of words from the EEPROM. 379 */ 380 static void 381 re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt) 382 { 383 int i; 384 u_int16_t word = 0, *ptr; 385 386 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 387 388 DELAY(100); 389 390 for (i = 0; i < cnt; i++) { 391 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 392 re_eeprom_getword(sc, off + i, &word); 393 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 394 ptr = (u_int16_t *)(dest + (i * 2)); 395 *ptr = word; 396 } 397 398 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 399 } 400 401 static int 402 re_gmii_readreg(device_t dev, int phy, int reg) 403 { 404 struct rl_softc *sc; 405 u_int32_t rval; 406 int i; 407 408 if (phy != 1) 409 return (0); 410 411 sc = device_get_softc(dev); 412 413 /* Let the rgephy driver read the GMEDIASTAT register */ 414 415 if (reg == RL_GMEDIASTAT) { 416 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 417 return (rval); 418 } 419 420 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 421 422 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 423 rval = CSR_READ_4(sc, RL_PHYAR); 424 if (rval & RL_PHYAR_BUSY) 425 break; 426 DELAY(100); 427 } 428 429 if (i == RL_PHY_TIMEOUT) { 430 device_printf(sc->rl_dev, "PHY read failed\n"); 431 return (0); 432 } 433 434 return (rval & RL_PHYAR_PHYDATA); 435 } 436 437 static int 438 re_gmii_writereg(device_t dev, int phy, int reg, int data) 439 { 440 struct rl_softc *sc; 441 u_int32_t rval; 442 int i; 443 444 sc = device_get_softc(dev); 445 446 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 447 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 448 449 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 450 rval = CSR_READ_4(sc, RL_PHYAR); 451 if (!(rval & RL_PHYAR_BUSY)) 452 break; 453 DELAY(100); 454 } 455 456 if (i == RL_PHY_TIMEOUT) { 457 device_printf(sc->rl_dev, "PHY write failed\n"); 458 return (0); 459 } 460 461 return (0); 462 } 463 464 static int 465 re_miibus_readreg(device_t dev, int phy, int reg) 466 { 467 struct rl_softc *sc; 468 u_int16_t rval = 0; 469 u_int16_t re8139_reg = 0; 470 471 sc = device_get_softc(dev); 472 473 if (sc->rl_type == RL_8169) { 474 rval = re_gmii_readreg(dev, phy, reg); 475 return (rval); 476 } 477 478 /* Pretend the internal PHY is only at address 0 */ 479 if (phy) { 480 return (0); 481 } 482 switch (reg) { 483 case MII_BMCR: 484 re8139_reg = RL_BMCR; 485 break; 486 case MII_BMSR: 487 re8139_reg = RL_BMSR; 488 break; 489 case MII_ANAR: 490 re8139_reg = RL_ANAR; 491 break; 492 case MII_ANER: 493 re8139_reg = RL_ANER; 494 break; 495 case MII_ANLPAR: 496 re8139_reg = RL_LPAR; 497 break; 498 case MII_PHYIDR1: 499 case MII_PHYIDR2: 500 return (0); 501 /* 502 * Allow the rlphy driver to read the media status 503 * register. If we have a link partner which does not 504 * support NWAY, this is the register which will tell 505 * us the results of parallel detection. 506 */ 507 case RL_MEDIASTAT: 508 rval = CSR_READ_1(sc, RL_MEDIASTAT); 509 return (rval); 510 default: 511 device_printf(sc->rl_dev, "bad phy register\n"); 512 return (0); 513 } 514 rval = CSR_READ_2(sc, re8139_reg); 515 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 516 /* 8139C+ has different bit layout. */ 517 rval &= ~(BMCR_LOOP | BMCR_ISO); 518 } 519 return (rval); 520 } 521 522 static int 523 re_miibus_writereg(device_t dev, int phy, int reg, int data) 524 { 525 struct rl_softc *sc; 526 u_int16_t re8139_reg = 0; 527 int rval = 0; 528 529 sc = device_get_softc(dev); 530 531 if (sc->rl_type == RL_8169) { 532 rval = re_gmii_writereg(dev, phy, reg, data); 533 return (rval); 534 } 535 536 /* Pretend the internal PHY is only at address 0 */ 537 if (phy) 538 return (0); 539 540 switch (reg) { 541 case MII_BMCR: 542 re8139_reg = RL_BMCR; 543 if (sc->rl_type == RL_8139CPLUS) { 544 /* 8139C+ has different bit layout. */ 545 data &= ~(BMCR_LOOP | BMCR_ISO); 546 } 547 break; 548 case MII_BMSR: 549 re8139_reg = RL_BMSR; 550 break; 551 case MII_ANAR: 552 re8139_reg = RL_ANAR; 553 break; 554 case MII_ANER: 555 re8139_reg = RL_ANER; 556 break; 557 case MII_ANLPAR: 558 re8139_reg = RL_LPAR; 559 break; 560 case MII_PHYIDR1: 561 case MII_PHYIDR2: 562 return (0); 563 break; 564 default: 565 device_printf(sc->rl_dev, "bad phy register\n"); 566 return (0); 567 } 568 CSR_WRITE_2(sc, re8139_reg, data); 569 return (0); 570 } 571 572 static void 573 re_miibus_statchg(device_t dev) 574 { 575 struct rl_softc *sc; 576 struct ifnet *ifp; 577 struct mii_data *mii; 578 579 sc = device_get_softc(dev); 580 mii = device_get_softc(sc->rl_miibus); 581 ifp = sc->rl_ifp; 582 if (mii == NULL || ifp == NULL || 583 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 584 return; 585 586 sc->rl_flags &= ~RL_FLAG_LINK; 587 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 588 (IFM_ACTIVE | IFM_AVALID)) { 589 switch (IFM_SUBTYPE(mii->mii_media_active)) { 590 case IFM_10_T: 591 case IFM_100_TX: 592 sc->rl_flags |= RL_FLAG_LINK; 593 break; 594 case IFM_1000_T: 595 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0) 596 break; 597 sc->rl_flags |= RL_FLAG_LINK; 598 break; 599 default: 600 break; 601 } 602 } 603 /* 604 * RealTek controllers does not provide any interface to 605 * Tx/Rx MACs for resolved speed, duplex and flow-control 606 * parameters. 607 */ 608 } 609 610 /* 611 * Set the RX configuration and 64-bit multicast hash filter. 612 */ 613 static void 614 re_set_rxmode(struct rl_softc *sc) 615 { 616 struct ifnet *ifp; 617 struct ifmultiaddr *ifma; 618 uint32_t hashes[2] = { 0, 0 }; 619 uint32_t h, rxfilt; 620 621 RL_LOCK_ASSERT(sc); 622 623 ifp = sc->rl_ifp; 624 625 rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD; 626 627 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 628 if (ifp->if_flags & IFF_PROMISC) 629 rxfilt |= RL_RXCFG_RX_ALLPHYS; 630 /* 631 * Unlike other hardwares, we have to explicitly set 632 * RL_RXCFG_RX_MULTI to receive multicast frames in 633 * promiscuous mode. 634 */ 635 rxfilt |= RL_RXCFG_RX_MULTI; 636 hashes[0] = hashes[1] = 0xffffffff; 637 goto done; 638 } 639 640 IF_ADDR_LOCK(ifp); 641 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 642 if (ifma->ifma_addr->sa_family != AF_LINK) 643 continue; 644 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 645 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 646 if (h < 32) 647 hashes[0] |= (1 << h); 648 else 649 hashes[1] |= (1 << (h - 32)); 650 } 651 IF_ADDR_UNLOCK(ifp); 652 653 if (hashes[0] != 0 || hashes[1] != 0) { 654 /* 655 * For some unfathomable reason, RealTek decided to 656 * reverse the order of the multicast hash registers 657 * in the PCI Express parts. This means we have to 658 * write the hash pattern in reverse order for those 659 * devices. 660 */ 661 if ((sc->rl_flags & RL_FLAG_PCIE) != 0) { 662 h = bswap32(hashes[0]); 663 hashes[0] = bswap32(hashes[1]); 664 hashes[1] = h; 665 } 666 rxfilt |= RL_RXCFG_RX_MULTI; 667 } 668 669 done: 670 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 671 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 672 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 673 } 674 675 static void 676 re_reset(struct rl_softc *sc) 677 { 678 int i; 679 680 RL_LOCK_ASSERT(sc); 681 682 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 683 684 for (i = 0; i < RL_TIMEOUT; i++) { 685 DELAY(10); 686 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 687 break; 688 } 689 if (i == RL_TIMEOUT) 690 device_printf(sc->rl_dev, "reset never completed!\n"); 691 692 if ((sc->rl_flags & RL_FLAG_MACRESET) != 0) 693 CSR_WRITE_1(sc, 0x82, 1); 694 if (sc->rl_hwrev == RL_HWREV_8169S) 695 re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0); 696 } 697 698 #ifdef RE_DIAG 699 700 /* 701 * The following routine is designed to test for a defect on some 702 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 703 * lines connected to the bus, however for a 32-bit only card, they 704 * should be pulled high. The result of this defect is that the 705 * NIC will not work right if you plug it into a 64-bit slot: DMA 706 * operations will be done with 64-bit transfers, which will fail 707 * because the 64-bit data lines aren't connected. 708 * 709 * There's no way to work around this (short of talking a soldering 710 * iron to the board), however we can detect it. The method we use 711 * here is to put the NIC into digital loopback mode, set the receiver 712 * to promiscuous mode, and then try to send a frame. We then compare 713 * the frame data we sent to what was received. If the data matches, 714 * then the NIC is working correctly, otherwise we know the user has 715 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 716 * slot. In the latter case, there's no way the NIC can work correctly, 717 * so we print out a message on the console and abort the device attach. 718 */ 719 720 static int 721 re_diag(struct rl_softc *sc) 722 { 723 struct ifnet *ifp = sc->rl_ifp; 724 struct mbuf *m0; 725 struct ether_header *eh; 726 struct rl_desc *cur_rx; 727 u_int16_t status; 728 u_int32_t rxstat; 729 int total_len, i, error = 0, phyaddr; 730 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 731 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 732 733 /* Allocate a single mbuf */ 734 MGETHDR(m0, M_DONTWAIT, MT_DATA); 735 if (m0 == NULL) 736 return (ENOBUFS); 737 738 RL_LOCK(sc); 739 740 /* 741 * Initialize the NIC in test mode. This sets the chip up 742 * so that it can send and receive frames, but performs the 743 * following special functions: 744 * - Puts receiver in promiscuous mode 745 * - Enables digital loopback mode 746 * - Leaves interrupts turned off 747 */ 748 749 ifp->if_flags |= IFF_PROMISC; 750 sc->rl_testmode = 1; 751 re_init_locked(sc); 752 sc->rl_flags |= RL_FLAG_LINK; 753 if (sc->rl_type == RL_8169) 754 phyaddr = 1; 755 else 756 phyaddr = 0; 757 758 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 759 for (i = 0; i < RL_TIMEOUT; i++) { 760 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 761 if (!(status & BMCR_RESET)) 762 break; 763 } 764 765 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 766 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 767 768 DELAY(100000); 769 770 /* Put some data in the mbuf */ 771 772 eh = mtod(m0, struct ether_header *); 773 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 774 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 775 eh->ether_type = htons(ETHERTYPE_IP); 776 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 777 778 /* 779 * Queue the packet, start transmission. 780 * Note: IF_HANDOFF() ultimately calls re_start() for us. 781 */ 782 783 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 784 RL_UNLOCK(sc); 785 /* XXX: re_diag must not be called when in ALTQ mode */ 786 IF_HANDOFF(&ifp->if_snd, m0, ifp); 787 RL_LOCK(sc); 788 m0 = NULL; 789 790 /* Wait for it to propagate through the chip */ 791 792 DELAY(100000); 793 for (i = 0; i < RL_TIMEOUT; i++) { 794 status = CSR_READ_2(sc, RL_ISR); 795 CSR_WRITE_2(sc, RL_ISR, status); 796 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 797 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 798 break; 799 DELAY(10); 800 } 801 802 if (i == RL_TIMEOUT) { 803 device_printf(sc->rl_dev, 804 "diagnostic failed, failed to receive packet in" 805 " loopback mode\n"); 806 error = EIO; 807 goto done; 808 } 809 810 /* 811 * The packet should have been dumped into the first 812 * entry in the RX DMA ring. Grab it from there. 813 */ 814 815 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 816 sc->rl_ldata.rl_rx_list_map, 817 BUS_DMASYNC_POSTREAD); 818 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 819 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 820 BUS_DMASYNC_POSTREAD); 821 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 822 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 823 824 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 825 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 826 eh = mtod(m0, struct ether_header *); 827 828 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 829 total_len = RL_RXBYTES(cur_rx); 830 rxstat = le32toh(cur_rx->rl_cmdstat); 831 832 if (total_len != ETHER_MIN_LEN) { 833 device_printf(sc->rl_dev, 834 "diagnostic failed, received short packet\n"); 835 error = EIO; 836 goto done; 837 } 838 839 /* Test that the received packet data matches what we sent. */ 840 841 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 842 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 843 ntohs(eh->ether_type) != ETHERTYPE_IP) { 844 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 845 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 846 dst, ":", src, ":", ETHERTYPE_IP); 847 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 848 eh->ether_dhost, ":", eh->ether_shost, ":", 849 ntohs(eh->ether_type)); 850 device_printf(sc->rl_dev, "You may have a defective 32-bit " 851 "NIC plugged into a 64-bit PCI slot.\n"); 852 device_printf(sc->rl_dev, "Please re-install the NIC in a " 853 "32-bit slot for proper operation.\n"); 854 device_printf(sc->rl_dev, "Read the re(4) man page for more " 855 "details.\n"); 856 error = EIO; 857 } 858 859 done: 860 /* Turn interface off, release resources */ 861 862 sc->rl_testmode = 0; 863 sc->rl_flags &= ~RL_FLAG_LINK; 864 ifp->if_flags &= ~IFF_PROMISC; 865 re_stop(sc); 866 if (m0 != NULL) 867 m_freem(m0); 868 869 RL_UNLOCK(sc); 870 871 return (error); 872 } 873 874 #endif 875 876 /* 877 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 878 * IDs against our list and return a device name if we find a match. 879 */ 880 static int 881 re_probe(device_t dev) 882 { 883 struct rl_type *t; 884 uint16_t devid, vendor; 885 uint16_t revid, sdevid; 886 int i; 887 888 vendor = pci_get_vendor(dev); 889 devid = pci_get_device(dev); 890 revid = pci_get_revid(dev); 891 sdevid = pci_get_subdevice(dev); 892 893 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 894 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 895 /* 896 * Only attach to rev. 3 of the Linksys EG1032 adapter. 897 * Rev. 2 is supported by sk(4). 898 */ 899 return (ENXIO); 900 } 901 } 902 903 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 904 if (revid != 0x20) { 905 /* 8139, let rl(4) take care of this device. */ 906 return (ENXIO); 907 } 908 } 909 910 t = re_devs; 911 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) { 912 if (vendor == t->rl_vid && devid == t->rl_did) { 913 device_set_desc(dev, t->rl_name); 914 return (BUS_PROBE_DEFAULT); 915 } 916 } 917 918 return (ENXIO); 919 } 920 921 /* 922 * Map a single buffer address. 923 */ 924 925 static void 926 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 927 { 928 bus_addr_t *addr; 929 930 if (error) 931 return; 932 933 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 934 addr = arg; 935 *addr = segs->ds_addr; 936 } 937 938 static int 939 re_allocmem(device_t dev, struct rl_softc *sc) 940 { 941 bus_size_t rx_list_size, tx_list_size; 942 int error; 943 int i; 944 945 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 946 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 947 948 /* 949 * Allocate the parent bus DMA tag appropriate for PCI. 950 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD 951 * register should be set. However some RealTek chips are known 952 * to be buggy on DAC handling, therefore disable DAC by limiting 953 * DMA address space to 32bit. PCIe variants of RealTek chips 954 * may not have the limitation but I took safer path. 955 */ 956 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 957 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 958 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 959 NULL, NULL, &sc->rl_parent_tag); 960 if (error) { 961 device_printf(dev, "could not allocate parent DMA tag\n"); 962 return (error); 963 } 964 965 /* 966 * Allocate map for TX mbufs. 967 */ 968 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 969 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 970 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 971 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 972 if (error) { 973 device_printf(dev, "could not allocate TX DMA tag\n"); 974 return (error); 975 } 976 977 /* 978 * Allocate map for RX mbufs. 979 */ 980 981 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 982 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 983 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 984 if (error) { 985 device_printf(dev, "could not allocate RX DMA tag\n"); 986 return (error); 987 } 988 989 /* 990 * Allocate map for TX descriptor list. 991 */ 992 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 993 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 994 NULL, tx_list_size, 1, tx_list_size, 0, 995 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 996 if (error) { 997 device_printf(dev, "could not allocate TX DMA ring tag\n"); 998 return (error); 999 } 1000 1001 /* Allocate DMA'able memory for the TX ring */ 1002 1003 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1004 (void **)&sc->rl_ldata.rl_tx_list, 1005 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1006 &sc->rl_ldata.rl_tx_list_map); 1007 if (error) { 1008 device_printf(dev, "could not allocate TX DMA ring\n"); 1009 return (error); 1010 } 1011 1012 /* Load the map for the TX ring. */ 1013 1014 sc->rl_ldata.rl_tx_list_addr = 0; 1015 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1016 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1017 tx_list_size, re_dma_map_addr, 1018 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1019 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 1020 device_printf(dev, "could not load TX DMA ring\n"); 1021 return (ENOMEM); 1022 } 1023 1024 /* Create DMA maps for TX buffers */ 1025 1026 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1027 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1028 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1029 if (error) { 1030 device_printf(dev, "could not create DMA map for TX\n"); 1031 return (error); 1032 } 1033 } 1034 1035 /* 1036 * Allocate map for RX descriptor list. 1037 */ 1038 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1039 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1040 NULL, rx_list_size, 1, rx_list_size, 0, 1041 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1042 if (error) { 1043 device_printf(dev, "could not create RX DMA ring tag\n"); 1044 return (error); 1045 } 1046 1047 /* Allocate DMA'able memory for the RX ring */ 1048 1049 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1050 (void **)&sc->rl_ldata.rl_rx_list, 1051 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1052 &sc->rl_ldata.rl_rx_list_map); 1053 if (error) { 1054 device_printf(dev, "could not allocate RX DMA ring\n"); 1055 return (error); 1056 } 1057 1058 /* Load the map for the RX ring. */ 1059 1060 sc->rl_ldata.rl_rx_list_addr = 0; 1061 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1062 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1063 rx_list_size, re_dma_map_addr, 1064 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1065 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1066 device_printf(dev, "could not load RX DMA ring\n"); 1067 return (ENOMEM); 1068 } 1069 1070 /* Create DMA maps for RX buffers */ 1071 1072 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1073 &sc->rl_ldata.rl_rx_sparemap); 1074 if (error) { 1075 device_printf(dev, "could not create spare DMA map for RX\n"); 1076 return (error); 1077 } 1078 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1079 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1080 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1081 if (error) { 1082 device_printf(dev, "could not create DMA map for RX\n"); 1083 return (error); 1084 } 1085 } 1086 1087 return (0); 1088 } 1089 1090 /* 1091 * Attach the interface. Allocate softc structures, do ifmedia 1092 * setup and ethernet/BPF attach. 1093 */ 1094 static int 1095 re_attach(device_t dev) 1096 { 1097 u_char eaddr[ETHER_ADDR_LEN]; 1098 u_int16_t as[ETHER_ADDR_LEN / 2]; 1099 struct rl_softc *sc; 1100 struct ifnet *ifp; 1101 struct rl_hwrev *hw_rev; 1102 int hwrev; 1103 u_int16_t devid, re_did = 0; 1104 int error = 0, rid, i; 1105 int msic, reg; 1106 uint8_t cfg; 1107 1108 sc = device_get_softc(dev); 1109 sc->rl_dev = dev; 1110 1111 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1112 MTX_DEF); 1113 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1114 1115 /* 1116 * Map control/status registers. 1117 */ 1118 pci_enable_busmaster(dev); 1119 1120 devid = pci_get_device(dev); 1121 /* Prefer memory space register mapping over IO space. */ 1122 sc->rl_res_id = PCIR_BAR(1); 1123 sc->rl_res_type = SYS_RES_MEMORY; 1124 /* RTL8168/8101E seems to use different BARs. */ 1125 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E) 1126 sc->rl_res_id = PCIR_BAR(2); 1127 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1128 &sc->rl_res_id, RF_ACTIVE); 1129 1130 if (sc->rl_res == NULL) { 1131 sc->rl_res_id = PCIR_BAR(0); 1132 sc->rl_res_type = SYS_RES_IOPORT; 1133 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1134 &sc->rl_res_id, RF_ACTIVE); 1135 if (sc->rl_res == NULL) { 1136 device_printf(dev, "couldn't map ports/memory\n"); 1137 error = ENXIO; 1138 goto fail; 1139 } 1140 } 1141 1142 sc->rl_btag = rman_get_bustag(sc->rl_res); 1143 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1144 1145 msic = 0; 1146 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 1147 sc->rl_flags |= RL_FLAG_PCIE; 1148 msic = pci_msi_count(dev); 1149 if (bootverbose) 1150 device_printf(dev, "MSI count : %d\n", msic); 1151 } 1152 if (msic > 0 && msi_disable == 0) { 1153 msic = 1; 1154 if (pci_alloc_msi(dev, &msic) == 0) { 1155 if (msic == RL_MSI_MESSAGES) { 1156 device_printf(dev, "Using %d MSI messages\n", 1157 msic); 1158 sc->rl_flags |= RL_FLAG_MSI; 1159 /* Explicitly set MSI enable bit. */ 1160 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1161 cfg = CSR_READ_1(sc, RL_CFG2); 1162 cfg |= RL_CFG2_MSI; 1163 CSR_WRITE_1(sc, RL_CFG2, cfg); 1164 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1165 } else 1166 pci_release_msi(dev); 1167 } 1168 } 1169 1170 /* Allocate interrupt */ 1171 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1172 rid = 0; 1173 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1174 RF_SHAREABLE | RF_ACTIVE); 1175 if (sc->rl_irq[0] == NULL) { 1176 device_printf(dev, "couldn't allocate IRQ resources\n"); 1177 error = ENXIO; 1178 goto fail; 1179 } 1180 } else { 1181 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1182 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1183 SYS_RES_IRQ, &rid, RF_ACTIVE); 1184 if (sc->rl_irq[i] == NULL) { 1185 device_printf(dev, 1186 "couldn't llocate IRQ resources for " 1187 "message %d\n", rid); 1188 error = ENXIO; 1189 goto fail; 1190 } 1191 } 1192 } 1193 1194 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1195 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1196 cfg = CSR_READ_1(sc, RL_CFG2); 1197 if ((cfg & RL_CFG2_MSI) != 0) { 1198 device_printf(dev, "turning off MSI enable bit.\n"); 1199 cfg &= ~RL_CFG2_MSI; 1200 CSR_WRITE_1(sc, RL_CFG2, cfg); 1201 } 1202 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1203 } 1204 1205 /* Reset the adapter. */ 1206 RL_LOCK(sc); 1207 re_reset(sc); 1208 RL_UNLOCK(sc); 1209 1210 hw_rev = re_hwrevs; 1211 hwrev = CSR_READ_4(sc, RL_TXCFG); 1212 switch (hwrev & 0x70000000) { 1213 case 0x00000000: 1214 case 0x10000000: 1215 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000); 1216 hwrev &= (RL_TXCFG_HWREV | 0x80000000); 1217 break; 1218 default: 1219 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000); 1220 hwrev &= RL_TXCFG_HWREV; 1221 break; 1222 } 1223 device_printf(dev, "MAC rev. 0x%08x\n", hwrev & 0x00700000); 1224 while (hw_rev->rl_desc != NULL) { 1225 if (hw_rev->rl_rev == hwrev) { 1226 sc->rl_type = hw_rev->rl_type; 1227 sc->rl_hwrev = hw_rev->rl_rev; 1228 break; 1229 } 1230 hw_rev++; 1231 } 1232 if (hw_rev->rl_desc == NULL) { 1233 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev); 1234 error = ENXIO; 1235 goto fail; 1236 } 1237 1238 switch (hw_rev->rl_rev) { 1239 case RL_HWREV_8139CPLUS: 1240 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_FASTETHER; 1241 break; 1242 case RL_HWREV_8100E: 1243 case RL_HWREV_8101E: 1244 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_PHYWAKE | 1245 RL_FLAG_FASTETHER; 1246 break; 1247 case RL_HWREV_8102E: 1248 case RL_HWREV_8102EL: 1249 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_PHYWAKE | 1250 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1251 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP; 1252 break; 1253 case RL_HWREV_8168_SPIN1: 1254 case RL_HWREV_8168_SPIN2: 1255 sc->rl_flags |= RL_FLAG_WOLRXENB; 1256 /* FALLTHROUGH */ 1257 case RL_HWREV_8168_SPIN3: 1258 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT; 1259 break; 1260 case RL_HWREV_8168C_SPIN2: 1261 sc->rl_flags |= RL_FLAG_MACSLEEP; 1262 /* FALLTHROUGH */ 1263 case RL_HWREV_8168C: 1264 if ((hwrev & 0x00700000) == 0x00200000) 1265 sc->rl_flags |= RL_FLAG_MACSLEEP; 1266 /* FALLTHROUGH */ 1267 case RL_HWREV_8168CP: 1268 case RL_HWREV_8168D: 1269 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1270 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP; 1271 /* 1272 * These controllers support jumbo frame but it seems 1273 * that enabling it requires touching additional magic 1274 * registers. Depending on MAC revisions some 1275 * controllers need to disable checksum offload. So 1276 * disable jumbo frame until I have better idea what 1277 * it really requires to make it support. 1278 * RTL8168C/CP : supports up to 6KB jumbo frame. 1279 * RTL8111C/CP : supports up to 9KB jumbo frame. 1280 */ 1281 sc->rl_flags |= RL_FLAG_NOJUMBO; 1282 break; 1283 case RL_HWREV_8169_8110SB: 1284 case RL_HWREV_8169_8110SBL: 1285 case RL_HWREV_8169_8110SC: 1286 case RL_HWREV_8169_8110SCE: 1287 sc->rl_flags |= RL_FLAG_PHYWAKE; 1288 /* FALLTHROUGH */ 1289 case RL_HWREV_8169: 1290 case RL_HWREV_8169S: 1291 case RL_HWREV_8110S: 1292 sc->rl_flags |= RL_FLAG_MACRESET; 1293 break; 1294 default: 1295 break; 1296 } 1297 1298 /* Enable PME. */ 1299 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1300 cfg = CSR_READ_1(sc, RL_CFG1); 1301 cfg |= RL_CFG1_PME; 1302 CSR_WRITE_1(sc, RL_CFG1, cfg); 1303 cfg = CSR_READ_1(sc, RL_CFG5); 1304 cfg &= RL_CFG5_PME_STS; 1305 CSR_WRITE_1(sc, RL_CFG5, cfg); 1306 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1307 1308 if ((sc->rl_flags & RL_FLAG_PAR) != 0) { 1309 /* 1310 * XXX Should have a better way to extract station 1311 * address from EEPROM. 1312 */ 1313 for (i = 0; i < ETHER_ADDR_LEN; i++) 1314 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1315 } else { 1316 sc->rl_eewidth = RL_9356_ADDR_LEN; 1317 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1318 if (re_did != 0x8129) 1319 sc->rl_eewidth = RL_9346_ADDR_LEN; 1320 1321 /* 1322 * Get station address from the EEPROM. 1323 */ 1324 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1325 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1326 as[i] = le16toh(as[i]); 1327 bcopy(as, eaddr, sizeof(eaddr)); 1328 } 1329 1330 if (sc->rl_type == RL_8169) { 1331 /* Set RX length mask and number of descriptors. */ 1332 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1333 sc->rl_txstart = RL_GTXSTART; 1334 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1335 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1336 } else { 1337 /* Set RX length mask and number of descriptors. */ 1338 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1339 sc->rl_txstart = RL_TXSTART; 1340 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1341 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1342 } 1343 1344 error = re_allocmem(dev, sc); 1345 if (error) 1346 goto fail; 1347 1348 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1349 if (ifp == NULL) { 1350 device_printf(dev, "can not if_alloc()\n"); 1351 error = ENOSPC; 1352 goto fail; 1353 } 1354 1355 /* Take controller out of deep sleep mode. */ 1356 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 1357 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 1358 CSR_WRITE_1(sc, RL_GPIO, 1359 CSR_READ_1(sc, RL_GPIO) | 0x01); 1360 else 1361 CSR_WRITE_1(sc, RL_GPIO, 1362 CSR_READ_1(sc, RL_GPIO) & ~0x01); 1363 } 1364 1365 /* Take PHY out of power down mode. */ 1366 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) { 1367 re_gmii_writereg(dev, 1, 0x1f, 0); 1368 re_gmii_writereg(dev, 1, 0x0e, 0); 1369 } 1370 1371 /* Do MII setup */ 1372 if (mii_phy_probe(dev, &sc->rl_miibus, 1373 re_ifmedia_upd, re_ifmedia_sts)) { 1374 device_printf(dev, "MII without any phy!\n"); 1375 error = ENXIO; 1376 goto fail; 1377 } 1378 1379 ifp->if_softc = sc; 1380 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1381 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1382 ifp->if_ioctl = re_ioctl; 1383 ifp->if_start = re_start; 1384 ifp->if_hwassist = RE_CSUM_FEATURES; 1385 ifp->if_capabilities = IFCAP_HWCSUM; 1386 ifp->if_capenable = ifp->if_capabilities; 1387 ifp->if_init = re_init; 1388 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1389 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1390 IFQ_SET_READY(&ifp->if_snd); 1391 1392 TASK_INIT(&sc->rl_txtask, 1, re_tx_task, ifp); 1393 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1394 1395 /* 1396 * XXX 1397 * Still have no idea how to make TSO work on 8168C, 8168CP, 1398 * 8111C and 8111CP. 1399 */ 1400 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 1401 ifp->if_hwassist |= CSUM_TSO; 1402 ifp->if_capabilities |= IFCAP_TSO4; 1403 } 1404 1405 /* 1406 * Call MI attach routine. 1407 */ 1408 ether_ifattach(ifp, eaddr); 1409 1410 /* VLAN capability setup */ 1411 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1412 if (ifp->if_capabilities & IFCAP_HWCSUM) 1413 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1414 /* Enable WOL if PM is supported. */ 1415 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, ®) == 0) 1416 ifp->if_capabilities |= IFCAP_WOL; 1417 ifp->if_capenable = ifp->if_capabilities; 1418 /* 1419 * Don't enable TSO by default. Under certain 1420 * circumtances the controller generated corrupted 1421 * packets in TSO size. 1422 */ 1423 ifp->if_hwassist &= ~CSUM_TSO; 1424 ifp->if_capenable &= ~IFCAP_TSO4; 1425 #ifdef DEVICE_POLLING 1426 ifp->if_capabilities |= IFCAP_POLLING; 1427 #endif 1428 /* 1429 * Tell the upper layer(s) we support long frames. 1430 * Must appear after the call to ether_ifattach() because 1431 * ether_ifattach() sets ifi_hdrlen to the default value. 1432 */ 1433 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1434 1435 #ifdef RE_DIAG 1436 /* 1437 * Perform hardware diagnostic on the original RTL8169. 1438 * Some 32-bit cards were incorrectly wired and would 1439 * malfunction if plugged into a 64-bit slot. 1440 */ 1441 1442 if (hwrev == RL_HWREV_8169) { 1443 error = re_diag(sc); 1444 if (error) { 1445 device_printf(dev, 1446 "attach aborted due to hardware diag failure\n"); 1447 ether_ifdetach(ifp); 1448 goto fail; 1449 } 1450 } 1451 #endif 1452 1453 /* Hook interrupt last to avoid having to lock softc */ 1454 if ((sc->rl_flags & RL_FLAG_MSI) == 0) 1455 error = bus_setup_intr(dev, sc->rl_irq[0], 1456 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1457 &sc->rl_intrhand[0]); 1458 else { 1459 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1460 error = bus_setup_intr(dev, sc->rl_irq[i], 1461 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1462 &sc->rl_intrhand[i]); 1463 if (error != 0) 1464 break; 1465 } 1466 } 1467 if (error) { 1468 device_printf(dev, "couldn't set up irq\n"); 1469 ether_ifdetach(ifp); 1470 } 1471 1472 fail: 1473 1474 if (error) 1475 re_detach(dev); 1476 1477 return (error); 1478 } 1479 1480 /* 1481 * Shutdown hardware and free up resources. This can be called any 1482 * time after the mutex has been initialized. It is called in both 1483 * the error case in attach and the normal detach case so it needs 1484 * to be careful about only freeing resources that have actually been 1485 * allocated. 1486 */ 1487 static int 1488 re_detach(device_t dev) 1489 { 1490 struct rl_softc *sc; 1491 struct ifnet *ifp; 1492 int i, rid; 1493 1494 sc = device_get_softc(dev); 1495 ifp = sc->rl_ifp; 1496 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1497 1498 /* These should only be active if attach succeeded */ 1499 if (device_is_attached(dev)) { 1500 #ifdef DEVICE_POLLING 1501 if (ifp->if_capenable & IFCAP_POLLING) 1502 ether_poll_deregister(ifp); 1503 #endif 1504 RL_LOCK(sc); 1505 #if 0 1506 sc->suspended = 1; 1507 #endif 1508 re_stop(sc); 1509 RL_UNLOCK(sc); 1510 callout_drain(&sc->rl_stat_callout); 1511 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1512 taskqueue_drain(taskqueue_fast, &sc->rl_txtask); 1513 /* 1514 * Force off the IFF_UP flag here, in case someone 1515 * still had a BPF descriptor attached to this 1516 * interface. If they do, ether_ifdetach() will cause 1517 * the BPF code to try and clear the promisc mode 1518 * flag, which will bubble down to re_ioctl(), 1519 * which will try to call re_init() again. This will 1520 * turn the NIC back on and restart the MII ticker, 1521 * which will panic the system when the kernel tries 1522 * to invoke the re_tick() function that isn't there 1523 * anymore. 1524 */ 1525 ifp->if_flags &= ~IFF_UP; 1526 ether_ifdetach(ifp); 1527 } 1528 if (sc->rl_miibus) 1529 device_delete_child(dev, sc->rl_miibus); 1530 bus_generic_detach(dev); 1531 1532 /* 1533 * The rest is resource deallocation, so we should already be 1534 * stopped here. 1535 */ 1536 1537 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1538 if (sc->rl_intrhand[i] != NULL) { 1539 bus_teardown_intr(dev, sc->rl_irq[i], 1540 sc->rl_intrhand[i]); 1541 sc->rl_intrhand[i] = NULL; 1542 } 1543 } 1544 if (ifp != NULL) 1545 if_free(ifp); 1546 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1547 if (sc->rl_irq[0] != NULL) { 1548 bus_release_resource(dev, SYS_RES_IRQ, 0, 1549 sc->rl_irq[0]); 1550 sc->rl_irq[0] = NULL; 1551 } 1552 } else { 1553 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1554 if (sc->rl_irq[i] != NULL) { 1555 bus_release_resource(dev, SYS_RES_IRQ, rid, 1556 sc->rl_irq[i]); 1557 sc->rl_irq[i] = NULL; 1558 } 1559 } 1560 pci_release_msi(dev); 1561 } 1562 if (sc->rl_res) 1563 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, 1564 sc->rl_res); 1565 1566 /* Unload and free the RX DMA ring memory and map */ 1567 1568 if (sc->rl_ldata.rl_rx_list_tag) { 1569 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1570 sc->rl_ldata.rl_rx_list_map); 1571 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1572 sc->rl_ldata.rl_rx_list, 1573 sc->rl_ldata.rl_rx_list_map); 1574 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1575 } 1576 1577 /* Unload and free the TX DMA ring memory and map */ 1578 1579 if (sc->rl_ldata.rl_tx_list_tag) { 1580 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1581 sc->rl_ldata.rl_tx_list_map); 1582 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1583 sc->rl_ldata.rl_tx_list, 1584 sc->rl_ldata.rl_tx_list_map); 1585 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1586 } 1587 1588 /* Destroy all the RX and TX buffer maps */ 1589 1590 if (sc->rl_ldata.rl_tx_mtag) { 1591 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1592 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1593 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1594 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1595 } 1596 if (sc->rl_ldata.rl_rx_mtag) { 1597 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) 1598 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1599 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1600 if (sc->rl_ldata.rl_rx_sparemap) 1601 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1602 sc->rl_ldata.rl_rx_sparemap); 1603 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1604 } 1605 1606 /* Unload and free the stats buffer and map */ 1607 1608 if (sc->rl_ldata.rl_stag) { 1609 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1610 sc->rl_ldata.rl_rx_list_map); 1611 bus_dmamem_free(sc->rl_ldata.rl_stag, 1612 sc->rl_ldata.rl_stats, 1613 sc->rl_ldata.rl_smap); 1614 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1615 } 1616 1617 if (sc->rl_parent_tag) 1618 bus_dma_tag_destroy(sc->rl_parent_tag); 1619 1620 mtx_destroy(&sc->rl_mtx); 1621 1622 return (0); 1623 } 1624 1625 static __inline void 1626 re_discard_rxbuf(struct rl_softc *sc, int idx) 1627 { 1628 struct rl_desc *desc; 1629 struct rl_rxdesc *rxd; 1630 uint32_t cmdstat; 1631 1632 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1633 desc = &sc->rl_ldata.rl_rx_list[idx]; 1634 desc->rl_vlanctl = 0; 1635 cmdstat = rxd->rx_size; 1636 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1637 cmdstat |= RL_RDESC_CMD_EOR; 1638 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1639 } 1640 1641 static int 1642 re_newbuf(struct rl_softc *sc, int idx) 1643 { 1644 struct mbuf *m; 1645 struct rl_rxdesc *rxd; 1646 bus_dma_segment_t segs[1]; 1647 bus_dmamap_t map; 1648 struct rl_desc *desc; 1649 uint32_t cmdstat; 1650 int error, nsegs; 1651 1652 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1653 if (m == NULL) 1654 return (ENOBUFS); 1655 1656 m->m_len = m->m_pkthdr.len = MCLBYTES; 1657 #ifdef RE_FIXUP_RX 1658 /* 1659 * This is part of an evil trick to deal with non-x86 platforms. 1660 * The RealTek chip requires RX buffers to be aligned on 64-bit 1661 * boundaries, but that will hose non-x86 machines. To get around 1662 * this, we leave some empty space at the start of each buffer 1663 * and for non-x86 hosts, we copy the buffer back six bytes 1664 * to achieve word alignment. This is slightly more efficient 1665 * than allocating a new buffer, copying the contents, and 1666 * discarding the old buffer. 1667 */ 1668 m_adj(m, RE_ETHER_ALIGN); 1669 #endif 1670 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1671 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1672 if (error != 0) { 1673 m_freem(m); 1674 return (ENOBUFS); 1675 } 1676 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1677 1678 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1679 if (rxd->rx_m != NULL) { 1680 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1681 BUS_DMASYNC_POSTREAD); 1682 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1683 } 1684 1685 rxd->rx_m = m; 1686 map = rxd->rx_dmamap; 1687 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1688 rxd->rx_size = segs[0].ds_len; 1689 sc->rl_ldata.rl_rx_sparemap = map; 1690 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1691 BUS_DMASYNC_PREREAD); 1692 1693 desc = &sc->rl_ldata.rl_rx_list[idx]; 1694 desc->rl_vlanctl = 0; 1695 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1696 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1697 cmdstat = segs[0].ds_len; 1698 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1699 cmdstat |= RL_RDESC_CMD_EOR; 1700 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1701 1702 return (0); 1703 } 1704 1705 #ifdef RE_FIXUP_RX 1706 static __inline void 1707 re_fixup_rx(struct mbuf *m) 1708 { 1709 int i; 1710 uint16_t *src, *dst; 1711 1712 src = mtod(m, uint16_t *); 1713 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1714 1715 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1716 *dst++ = *src++; 1717 1718 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1719 } 1720 #endif 1721 1722 static int 1723 re_tx_list_init(struct rl_softc *sc) 1724 { 1725 struct rl_desc *desc; 1726 int i; 1727 1728 RL_LOCK_ASSERT(sc); 1729 1730 bzero(sc->rl_ldata.rl_tx_list, 1731 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 1732 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1733 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 1734 /* Set EOR. */ 1735 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 1736 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 1737 1738 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1739 sc->rl_ldata.rl_tx_list_map, 1740 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1741 1742 sc->rl_ldata.rl_tx_prodidx = 0; 1743 sc->rl_ldata.rl_tx_considx = 0; 1744 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 1745 1746 return (0); 1747 } 1748 1749 static int 1750 re_rx_list_init(struct rl_softc *sc) 1751 { 1752 int error, i; 1753 1754 bzero(sc->rl_ldata.rl_rx_list, 1755 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 1756 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1757 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 1758 if ((error = re_newbuf(sc, i)) != 0) 1759 return (error); 1760 } 1761 1762 /* Flush the RX descriptors */ 1763 1764 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1765 sc->rl_ldata.rl_rx_list_map, 1766 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1767 1768 sc->rl_ldata.rl_rx_prodidx = 0; 1769 sc->rl_head = sc->rl_tail = NULL; 1770 1771 return (0); 1772 } 1773 1774 /* 1775 * RX handler for C+ and 8169. For the gigE chips, we support 1776 * the reception of jumbo frames that have been fragmented 1777 * across multiple 2K mbuf cluster buffers. 1778 */ 1779 static int 1780 re_rxeof(struct rl_softc *sc) 1781 { 1782 struct mbuf *m; 1783 struct ifnet *ifp; 1784 int i, total_len; 1785 struct rl_desc *cur_rx; 1786 u_int32_t rxstat, rxvlan; 1787 int maxpkt = 16; 1788 1789 RL_LOCK_ASSERT(sc); 1790 1791 ifp = sc->rl_ifp; 1792 1793 /* Invalidate the descriptor memory */ 1794 1795 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1796 sc->rl_ldata.rl_rx_list_map, 1797 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1798 1799 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 1800 i = RL_RX_DESC_NXT(sc, i)) { 1801 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1802 rxstat = le32toh(cur_rx->rl_cmdstat); 1803 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 1804 break; 1805 total_len = rxstat & sc->rl_rxlenmask; 1806 rxvlan = le32toh(cur_rx->rl_vlanctl); 1807 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 1808 1809 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1810 if (re_newbuf(sc, i) != 0) { 1811 /* 1812 * If this is part of a multi-fragment packet, 1813 * discard all the pieces. 1814 */ 1815 if (sc->rl_head != NULL) { 1816 m_freem(sc->rl_head); 1817 sc->rl_head = sc->rl_tail = NULL; 1818 } 1819 re_discard_rxbuf(sc, i); 1820 continue; 1821 } 1822 m->m_len = RE_RX_DESC_BUFLEN; 1823 if (sc->rl_head == NULL) 1824 sc->rl_head = sc->rl_tail = m; 1825 else { 1826 m->m_flags &= ~M_PKTHDR; 1827 sc->rl_tail->m_next = m; 1828 sc->rl_tail = m; 1829 } 1830 continue; 1831 } 1832 1833 /* 1834 * NOTE: for the 8139C+, the frame length field 1835 * is always 12 bits in size, but for the gigE chips, 1836 * it is 13 bits (since the max RX frame length is 16K). 1837 * Unfortunately, all 32 bits in the status word 1838 * were already used, so to make room for the extra 1839 * length bit, RealTek took out the 'frame alignment 1840 * error' bit and shifted the other status bits 1841 * over one slot. The OWN, EOR, FS and LS bits are 1842 * still in the same places. We have already extracted 1843 * the frame length and checked the OWN bit, so rather 1844 * than using an alternate bit mapping, we shift the 1845 * status bits one space to the right so we can evaluate 1846 * them using the 8169 status as though it was in the 1847 * same format as that of the 8139C+. 1848 */ 1849 if (sc->rl_type == RL_8169) 1850 rxstat >>= 1; 1851 1852 /* 1853 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 1854 * set, but if CRC is clear, it will still be a valid frame. 1855 */ 1856 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 && 1857 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) { 1858 ifp->if_ierrors++; 1859 /* 1860 * If this is part of a multi-fragment packet, 1861 * discard all the pieces. 1862 */ 1863 if (sc->rl_head != NULL) { 1864 m_freem(sc->rl_head); 1865 sc->rl_head = sc->rl_tail = NULL; 1866 } 1867 re_discard_rxbuf(sc, i); 1868 continue; 1869 } 1870 1871 /* 1872 * If allocating a replacement mbuf fails, 1873 * reload the current one. 1874 */ 1875 1876 if (re_newbuf(sc, i) != 0) { 1877 ifp->if_iqdrops++; 1878 if (sc->rl_head != NULL) { 1879 m_freem(sc->rl_head); 1880 sc->rl_head = sc->rl_tail = NULL; 1881 } 1882 re_discard_rxbuf(sc, i); 1883 continue; 1884 } 1885 1886 if (sc->rl_head != NULL) { 1887 m->m_len = total_len % RE_RX_DESC_BUFLEN; 1888 if (m->m_len == 0) 1889 m->m_len = RE_RX_DESC_BUFLEN; 1890 /* 1891 * Special case: if there's 4 bytes or less 1892 * in this buffer, the mbuf can be discarded: 1893 * the last 4 bytes is the CRC, which we don't 1894 * care about anyway. 1895 */ 1896 if (m->m_len <= ETHER_CRC_LEN) { 1897 sc->rl_tail->m_len -= 1898 (ETHER_CRC_LEN - m->m_len); 1899 m_freem(m); 1900 } else { 1901 m->m_len -= ETHER_CRC_LEN; 1902 m->m_flags &= ~M_PKTHDR; 1903 sc->rl_tail->m_next = m; 1904 } 1905 m = sc->rl_head; 1906 sc->rl_head = sc->rl_tail = NULL; 1907 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1908 } else 1909 m->m_pkthdr.len = m->m_len = 1910 (total_len - ETHER_CRC_LEN); 1911 1912 #ifdef RE_FIXUP_RX 1913 re_fixup_rx(m); 1914 #endif 1915 ifp->if_ipackets++; 1916 m->m_pkthdr.rcvif = ifp; 1917 1918 /* Do RX checksumming if enabled */ 1919 1920 if (ifp->if_capenable & IFCAP_RXCSUM) { 1921 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 1922 /* Check IP header checksum */ 1923 if (rxstat & RL_RDESC_STAT_PROTOID) 1924 m->m_pkthdr.csum_flags |= 1925 CSUM_IP_CHECKED; 1926 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1927 m->m_pkthdr.csum_flags |= 1928 CSUM_IP_VALID; 1929 1930 /* Check TCP/UDP checksum */ 1931 if ((RL_TCPPKT(rxstat) && 1932 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1933 (RL_UDPPKT(rxstat) && 1934 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1935 m->m_pkthdr.csum_flags |= 1936 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1937 m->m_pkthdr.csum_data = 0xffff; 1938 } 1939 } else { 1940 /* 1941 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP 1942 */ 1943 if ((rxstat & RL_RDESC_STAT_PROTOID) && 1944 (rxvlan & RL_RDESC_IPV4)) 1945 m->m_pkthdr.csum_flags |= 1946 CSUM_IP_CHECKED; 1947 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) && 1948 (rxvlan & RL_RDESC_IPV4)) 1949 m->m_pkthdr.csum_flags |= 1950 CSUM_IP_VALID; 1951 if (((rxstat & RL_RDESC_STAT_TCP) && 1952 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1953 ((rxstat & RL_RDESC_STAT_UDP) && 1954 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1955 m->m_pkthdr.csum_flags |= 1956 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1957 m->m_pkthdr.csum_data = 0xffff; 1958 } 1959 } 1960 } 1961 maxpkt--; 1962 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 1963 m->m_pkthdr.ether_vtag = 1964 bswap16((rxvlan & RL_RDESC_VLANCTL_DATA)); 1965 m->m_flags |= M_VLANTAG; 1966 } 1967 RL_UNLOCK(sc); 1968 (*ifp->if_input)(ifp, m); 1969 RL_LOCK(sc); 1970 } 1971 1972 /* Flush the RX DMA ring */ 1973 1974 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1975 sc->rl_ldata.rl_rx_list_map, 1976 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1977 1978 sc->rl_ldata.rl_rx_prodidx = i; 1979 1980 if (maxpkt) 1981 return(EAGAIN); 1982 1983 return(0); 1984 } 1985 1986 static void 1987 re_txeof(struct rl_softc *sc) 1988 { 1989 struct ifnet *ifp; 1990 struct rl_txdesc *txd; 1991 u_int32_t txstat; 1992 int cons; 1993 1994 cons = sc->rl_ldata.rl_tx_considx; 1995 if (cons == sc->rl_ldata.rl_tx_prodidx) 1996 return; 1997 1998 ifp = sc->rl_ifp; 1999 /* Invalidate the TX descriptor list */ 2000 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2001 sc->rl_ldata.rl_tx_list_map, 2002 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2003 2004 for (; cons != sc->rl_ldata.rl_tx_prodidx; 2005 cons = RL_TX_DESC_NXT(sc, cons)) { 2006 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 2007 if (txstat & RL_TDESC_STAT_OWN) 2008 break; 2009 /* 2010 * We only stash mbufs in the last descriptor 2011 * in a fragment chain, which also happens to 2012 * be the only place where the TX status bits 2013 * are valid. 2014 */ 2015 if (txstat & RL_TDESC_CMD_EOF) { 2016 txd = &sc->rl_ldata.rl_tx_desc[cons]; 2017 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2018 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2019 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2020 txd->tx_dmamap); 2021 KASSERT(txd->tx_m != NULL, 2022 ("%s: freeing NULL mbufs!", __func__)); 2023 m_freem(txd->tx_m); 2024 txd->tx_m = NULL; 2025 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 2026 RL_TDESC_STAT_COLCNT)) 2027 ifp->if_collisions++; 2028 if (txstat & RL_TDESC_STAT_TXERRSUM) 2029 ifp->if_oerrors++; 2030 else 2031 ifp->if_opackets++; 2032 } 2033 sc->rl_ldata.rl_tx_free++; 2034 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2035 } 2036 sc->rl_ldata.rl_tx_considx = cons; 2037 2038 /* No changes made to the TX ring, so no flush needed */ 2039 2040 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 2041 #ifdef RE_TX_MODERATION 2042 /* 2043 * If not all descriptors have been reaped yet, reload 2044 * the timer so that we will eventually get another 2045 * interrupt that will cause us to re-enter this routine. 2046 * This is done in case the transmitter has gone idle. 2047 */ 2048 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2049 #endif 2050 } else 2051 sc->rl_watchdog_timer = 0; 2052 } 2053 2054 static void 2055 re_tick(void *xsc) 2056 { 2057 struct rl_softc *sc; 2058 struct mii_data *mii; 2059 2060 sc = xsc; 2061 2062 RL_LOCK_ASSERT(sc); 2063 2064 mii = device_get_softc(sc->rl_miibus); 2065 mii_tick(mii); 2066 if ((sc->rl_flags & RL_FLAG_LINK) == 0) 2067 re_miibus_statchg(sc->rl_dev); 2068 /* 2069 * Reclaim transmitted frames here. Technically it is not 2070 * necessary to do here but it ensures periodic reclamation 2071 * regardless of Tx completion interrupt which seems to be 2072 * lost on PCIe based controllers under certain situations. 2073 */ 2074 re_txeof(sc); 2075 re_watchdog(sc); 2076 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2077 } 2078 2079 #ifdef DEVICE_POLLING 2080 static void 2081 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2082 { 2083 struct rl_softc *sc = ifp->if_softc; 2084 2085 RL_LOCK(sc); 2086 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2087 re_poll_locked(ifp, cmd, count); 2088 RL_UNLOCK(sc); 2089 } 2090 2091 static void 2092 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2093 { 2094 struct rl_softc *sc = ifp->if_softc; 2095 2096 RL_LOCK_ASSERT(sc); 2097 2098 sc->rxcycles = count; 2099 re_rxeof(sc); 2100 re_txeof(sc); 2101 2102 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2103 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2104 2105 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2106 u_int16_t status; 2107 2108 status = CSR_READ_2(sc, RL_ISR); 2109 if (status == 0xffff) 2110 return; 2111 if (status) 2112 CSR_WRITE_2(sc, RL_ISR, status); 2113 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2114 (sc->rl_flags & RL_FLAG_PCIE)) 2115 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2116 2117 /* 2118 * XXX check behaviour on receiver stalls. 2119 */ 2120 2121 if (status & RL_ISR_SYSTEM_ERR) 2122 re_init_locked(sc); 2123 } 2124 } 2125 #endif /* DEVICE_POLLING */ 2126 2127 static int 2128 re_intr(void *arg) 2129 { 2130 struct rl_softc *sc; 2131 uint16_t status; 2132 2133 sc = arg; 2134 2135 status = CSR_READ_2(sc, RL_ISR); 2136 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2137 return (FILTER_STRAY); 2138 CSR_WRITE_2(sc, RL_IMR, 0); 2139 2140 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2141 2142 return (FILTER_HANDLED); 2143 } 2144 2145 static void 2146 re_int_task(void *arg, int npending) 2147 { 2148 struct rl_softc *sc; 2149 struct ifnet *ifp; 2150 u_int16_t status; 2151 int rval = 0; 2152 2153 sc = arg; 2154 ifp = sc->rl_ifp; 2155 2156 RL_LOCK(sc); 2157 2158 status = CSR_READ_2(sc, RL_ISR); 2159 CSR_WRITE_2(sc, RL_ISR, status); 2160 2161 if (sc->suspended || 2162 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2163 RL_UNLOCK(sc); 2164 return; 2165 } 2166 2167 #ifdef DEVICE_POLLING 2168 if (ifp->if_capenable & IFCAP_POLLING) { 2169 RL_UNLOCK(sc); 2170 return; 2171 } 2172 #endif 2173 2174 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2175 rval = re_rxeof(sc); 2176 2177 /* 2178 * Some chips will ignore a second TX request issued 2179 * while an existing transmission is in progress. If 2180 * the transmitter goes idle but there are still 2181 * packets waiting to be sent, we need to restart the 2182 * channel here to flush them out. This only seems to 2183 * be required with the PCIe devices. 2184 */ 2185 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2186 (sc->rl_flags & RL_FLAG_PCIE)) 2187 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2188 if (status & ( 2189 #ifdef RE_TX_MODERATION 2190 RL_ISR_TIMEOUT_EXPIRED| 2191 #else 2192 RL_ISR_TX_OK| 2193 #endif 2194 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2195 re_txeof(sc); 2196 2197 if (status & RL_ISR_SYSTEM_ERR) 2198 re_init_locked(sc); 2199 2200 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2201 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2202 2203 RL_UNLOCK(sc); 2204 2205 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2206 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2207 return; 2208 } 2209 2210 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2211 } 2212 2213 static int 2214 re_encap(struct rl_softc *sc, struct mbuf **m_head) 2215 { 2216 struct rl_txdesc *txd, *txd_last; 2217 bus_dma_segment_t segs[RL_NTXSEGS]; 2218 bus_dmamap_t map; 2219 struct mbuf *m_new; 2220 struct rl_desc *desc; 2221 int nsegs, prod; 2222 int i, error, ei, si; 2223 int padlen; 2224 uint32_t cmdstat, csum_flags, vlanctl; 2225 2226 RL_LOCK_ASSERT(sc); 2227 M_ASSERTPKTHDR((*m_head)); 2228 2229 /* 2230 * With some of the RealTek chips, using the checksum offload 2231 * support in conjunction with the autopadding feature results 2232 * in the transmission of corrupt frames. For example, if we 2233 * need to send a really small IP fragment that's less than 60 2234 * bytes in size, and IP header checksumming is enabled, the 2235 * resulting ethernet frame that appears on the wire will 2236 * have garbled payload. To work around this, if TX IP checksum 2237 * offload is enabled, we always manually pad short frames out 2238 * to the minimum ethernet frame size. 2239 */ 2240 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0 && 2241 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN && 2242 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) { 2243 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2244 if (M_WRITABLE(*m_head) == 0) { 2245 /* Get a writable copy. */ 2246 m_new = m_dup(*m_head, M_DONTWAIT); 2247 m_freem(*m_head); 2248 if (m_new == NULL) { 2249 *m_head = NULL; 2250 return (ENOBUFS); 2251 } 2252 *m_head = m_new; 2253 } 2254 if ((*m_head)->m_next != NULL || 2255 M_TRAILINGSPACE(*m_head) < padlen) { 2256 m_new = m_defrag(*m_head, M_DONTWAIT); 2257 if (m_new == NULL) { 2258 m_freem(*m_head); 2259 *m_head = NULL; 2260 return (ENOBUFS); 2261 } 2262 } else 2263 m_new = *m_head; 2264 2265 /* 2266 * Manually pad short frames, and zero the pad space 2267 * to avoid leaking data. 2268 */ 2269 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2270 m_new->m_pkthdr.len += padlen; 2271 m_new->m_len = m_new->m_pkthdr.len; 2272 *m_head = m_new; 2273 } 2274 2275 prod = sc->rl_ldata.rl_tx_prodidx; 2276 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2277 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2278 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2279 if (error == EFBIG) { 2280 m_new = m_collapse(*m_head, M_DONTWAIT, RL_NTXSEGS); 2281 if (m_new == NULL) { 2282 m_freem(*m_head); 2283 *m_head = NULL; 2284 return (ENOBUFS); 2285 } 2286 *m_head = m_new; 2287 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2288 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2289 if (error != 0) { 2290 m_freem(*m_head); 2291 *m_head = NULL; 2292 return (error); 2293 } 2294 } else if (error != 0) 2295 return (error); 2296 if (nsegs == 0) { 2297 m_freem(*m_head); 2298 *m_head = NULL; 2299 return (EIO); 2300 } 2301 2302 /* Check for number of available descriptors. */ 2303 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2304 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2305 return (ENOBUFS); 2306 } 2307 2308 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2309 BUS_DMASYNC_PREWRITE); 2310 2311 /* 2312 * Set up checksum offload. Note: checksum offload bits must 2313 * appear in all descriptors of a multi-descriptor transmit 2314 * attempt. This is according to testing done with an 8169 2315 * chip. This is a requirement. 2316 */ 2317 vlanctl = 0; 2318 csum_flags = 0; 2319 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) 2320 csum_flags = RL_TDESC_CMD_LGSEND | 2321 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2322 RL_TDESC_CMD_MSSVAL_SHIFT); 2323 else { 2324 /* 2325 * Unconditionally enable IP checksum if TCP or UDP 2326 * checksum is required. Otherwise, TCP/UDP checksum 2327 * does't make effects. 2328 */ 2329 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) { 2330 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2331 csum_flags |= RL_TDESC_CMD_IPCSUM; 2332 if (((*m_head)->m_pkthdr.csum_flags & 2333 CSUM_TCP) != 0) 2334 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2335 if (((*m_head)->m_pkthdr.csum_flags & 2336 CSUM_UDP) != 0) 2337 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2338 } else { 2339 vlanctl |= RL_TDESC_CMD_IPCSUMV2; 2340 if (((*m_head)->m_pkthdr.csum_flags & 2341 CSUM_TCP) != 0) 2342 vlanctl |= RL_TDESC_CMD_TCPCSUMV2; 2343 if (((*m_head)->m_pkthdr.csum_flags & 2344 CSUM_UDP) != 0) 2345 vlanctl |= RL_TDESC_CMD_UDPCSUMV2; 2346 } 2347 } 2348 } 2349 2350 /* 2351 * Set up hardware VLAN tagging. Note: vlan tag info must 2352 * appear in all descriptors of a multi-descriptor 2353 * transmission attempt. 2354 */ 2355 if ((*m_head)->m_flags & M_VLANTAG) 2356 vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) | 2357 RL_TDESC_VLANCTL_TAG; 2358 2359 si = prod; 2360 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2361 desc = &sc->rl_ldata.rl_tx_list[prod]; 2362 desc->rl_vlanctl = htole32(vlanctl); 2363 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2364 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2365 cmdstat = segs[i].ds_len; 2366 if (i != 0) 2367 cmdstat |= RL_TDESC_CMD_OWN; 2368 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2369 cmdstat |= RL_TDESC_CMD_EOR; 2370 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2371 sc->rl_ldata.rl_tx_free--; 2372 } 2373 /* Update producer index. */ 2374 sc->rl_ldata.rl_tx_prodidx = prod; 2375 2376 /* Set EOF on the last descriptor. */ 2377 ei = RL_TX_DESC_PRV(sc, prod); 2378 desc = &sc->rl_ldata.rl_tx_list[ei]; 2379 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2380 2381 desc = &sc->rl_ldata.rl_tx_list[si]; 2382 /* Set SOF and transfer ownership of packet to the chip. */ 2383 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2384 2385 /* 2386 * Insure that the map for this transmission 2387 * is placed at the array index of the last descriptor 2388 * in this chain. (Swap last and first dmamaps.) 2389 */ 2390 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2391 map = txd->tx_dmamap; 2392 txd->tx_dmamap = txd_last->tx_dmamap; 2393 txd_last->tx_dmamap = map; 2394 txd_last->tx_m = *m_head; 2395 2396 return (0); 2397 } 2398 2399 static void 2400 re_tx_task(void *arg, int npending) 2401 { 2402 struct ifnet *ifp; 2403 2404 ifp = arg; 2405 re_start(ifp); 2406 } 2407 2408 /* 2409 * Main transmit routine for C+ and gigE NICs. 2410 */ 2411 static void 2412 re_start(struct ifnet *ifp) 2413 { 2414 struct rl_softc *sc; 2415 struct mbuf *m_head; 2416 int queued; 2417 2418 sc = ifp->if_softc; 2419 2420 RL_LOCK(sc); 2421 2422 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2423 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) { 2424 RL_UNLOCK(sc); 2425 return; 2426 } 2427 2428 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2429 sc->rl_ldata.rl_tx_free > 1;) { 2430 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2431 if (m_head == NULL) 2432 break; 2433 2434 if (re_encap(sc, &m_head) != 0) { 2435 if (m_head == NULL) 2436 break; 2437 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2438 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2439 break; 2440 } 2441 2442 /* 2443 * If there's a BPF listener, bounce a copy of this frame 2444 * to him. 2445 */ 2446 ETHER_BPF_MTAP(ifp, m_head); 2447 2448 queued++; 2449 } 2450 2451 if (queued == 0) { 2452 #ifdef RE_TX_MODERATION 2453 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2454 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2455 #endif 2456 RL_UNLOCK(sc); 2457 return; 2458 } 2459 2460 /* Flush the TX descriptors */ 2461 2462 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2463 sc->rl_ldata.rl_tx_list_map, 2464 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2465 2466 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2467 2468 #ifdef RE_TX_MODERATION 2469 /* 2470 * Use the countdown timer for interrupt moderation. 2471 * 'TX done' interrupts are disabled. Instead, we reset the 2472 * countdown timer, which will begin counting until it hits 2473 * the value in the TIMERINT register, and then trigger an 2474 * interrupt. Each time we write to the TIMERCNT register, 2475 * the timer count is reset to 0. 2476 */ 2477 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2478 #endif 2479 2480 /* 2481 * Set a timeout in case the chip goes out to lunch. 2482 */ 2483 sc->rl_watchdog_timer = 5; 2484 2485 RL_UNLOCK(sc); 2486 } 2487 2488 static void 2489 re_init(void *xsc) 2490 { 2491 struct rl_softc *sc = xsc; 2492 2493 RL_LOCK(sc); 2494 re_init_locked(sc); 2495 RL_UNLOCK(sc); 2496 } 2497 2498 static void 2499 re_init_locked(struct rl_softc *sc) 2500 { 2501 struct ifnet *ifp = sc->rl_ifp; 2502 struct mii_data *mii; 2503 uint32_t reg; 2504 uint16_t cfg; 2505 union { 2506 uint32_t align_dummy; 2507 u_char eaddr[ETHER_ADDR_LEN]; 2508 } eaddr; 2509 2510 RL_LOCK_ASSERT(sc); 2511 2512 mii = device_get_softc(sc->rl_miibus); 2513 2514 /* 2515 * Cancel pending I/O and free all RX/TX buffers. 2516 */ 2517 re_stop(sc); 2518 2519 /* Put controller into known state. */ 2520 re_reset(sc); 2521 2522 /* 2523 * Enable C+ RX and TX mode, as well as VLAN stripping and 2524 * RX checksum offload. We must configure the C+ register 2525 * before all others. 2526 */ 2527 cfg = RL_CPLUSCMD_PCI_MRW; 2528 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2529 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 2530 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2531 cfg |= RL_CPLUSCMD_VLANSTRIP; 2532 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) { 2533 cfg |= RL_CPLUSCMD_MACSTAT_DIS; 2534 /* XXX magic. */ 2535 cfg |= 0x0001; 2536 } else 2537 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB; 2538 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg); 2539 if (sc->rl_hwrev == RL_HWREV_8169_8110SC || 2540 sc->rl_hwrev == RL_HWREV_8169_8110SCE) { 2541 reg = 0x000fff00; 2542 if ((CSR_READ_1(sc, RL_CFG2) & RL_CFG2_PCI66MHZ) != 0) 2543 reg |= 0x000000ff; 2544 if (sc->rl_hwrev == RL_HWREV_8169_8110SCE) 2545 reg |= 0x00f00000; 2546 CSR_WRITE_4(sc, 0x7c, reg); 2547 /* Disable interrupt mitigation. */ 2548 CSR_WRITE_2(sc, 0xe2, 0); 2549 } 2550 /* 2551 * Disable TSO if interface MTU size is greater than MSS 2552 * allowed in controller. 2553 */ 2554 if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) { 2555 ifp->if_capenable &= ~IFCAP_TSO4; 2556 ifp->if_hwassist &= ~CSUM_TSO; 2557 } 2558 2559 /* 2560 * Init our MAC address. Even though the chipset 2561 * documentation doesn't mention it, we need to enter "Config 2562 * register write enable" mode to modify the ID registers. 2563 */ 2564 /* Copy MAC address on stack to align. */ 2565 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 2566 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2567 CSR_WRITE_4(sc, RL_IDR0, 2568 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 2569 CSR_WRITE_4(sc, RL_IDR4, 2570 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 2571 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2572 2573 /* 2574 * For C+ mode, initialize the RX descriptors and mbufs. 2575 */ 2576 re_rx_list_init(sc); 2577 re_tx_list_init(sc); 2578 2579 /* 2580 * Load the addresses of the RX and TX lists into the chip. 2581 */ 2582 2583 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2584 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2585 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2586 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2587 2588 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2589 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2590 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2591 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2592 2593 /* 2594 * Enable transmit and receive. 2595 */ 2596 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2597 2598 /* 2599 * Set the initial TX configuration. 2600 */ 2601 if (sc->rl_testmode) { 2602 if (sc->rl_type == RL_8169) 2603 CSR_WRITE_4(sc, RL_TXCFG, 2604 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2605 else 2606 CSR_WRITE_4(sc, RL_TXCFG, 2607 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2608 } else 2609 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2610 2611 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2612 2613 /* 2614 * Set the initial RX configuration. 2615 */ 2616 re_set_rxmode(sc); 2617 2618 #ifdef DEVICE_POLLING 2619 /* 2620 * Disable interrupts if we are polling. 2621 */ 2622 if (ifp->if_capenable & IFCAP_POLLING) 2623 CSR_WRITE_2(sc, RL_IMR, 0); 2624 else /* otherwise ... */ 2625 #endif 2626 2627 /* 2628 * Enable interrupts. 2629 */ 2630 if (sc->rl_testmode) 2631 CSR_WRITE_2(sc, RL_IMR, 0); 2632 else 2633 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2634 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 2635 2636 /* Set initial TX threshold */ 2637 sc->rl_txthresh = RL_TX_THRESH_INIT; 2638 2639 /* Start RX/TX process. */ 2640 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2641 #ifdef notdef 2642 /* Enable receiver and transmitter. */ 2643 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2644 #endif 2645 2646 #ifdef RE_TX_MODERATION 2647 /* 2648 * Initialize the timer interrupt register so that 2649 * a timer interrupt will be generated once the timer 2650 * reaches a certain number of ticks. The timer is 2651 * reloaded on each transmit. This gives us TX interrupt 2652 * moderation, which dramatically improves TX frame rate. 2653 */ 2654 if (sc->rl_type == RL_8169) 2655 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2656 else 2657 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2658 #endif 2659 2660 /* 2661 * For 8169 gigE NICs, set the max allowed RX packet 2662 * size so we can receive jumbo frames. 2663 */ 2664 if (sc->rl_type == RL_8169) 2665 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2666 2667 if (sc->rl_testmode) 2668 return; 2669 2670 mii_mediachg(mii); 2671 2672 CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD); 2673 2674 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2675 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2676 2677 sc->rl_flags &= ~RL_FLAG_LINK; 2678 sc->rl_watchdog_timer = 0; 2679 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2680 } 2681 2682 /* 2683 * Set media options. 2684 */ 2685 static int 2686 re_ifmedia_upd(struct ifnet *ifp) 2687 { 2688 struct rl_softc *sc; 2689 struct mii_data *mii; 2690 int error; 2691 2692 sc = ifp->if_softc; 2693 mii = device_get_softc(sc->rl_miibus); 2694 RL_LOCK(sc); 2695 error = mii_mediachg(mii); 2696 RL_UNLOCK(sc); 2697 2698 return (error); 2699 } 2700 2701 /* 2702 * Report current media status. 2703 */ 2704 static void 2705 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2706 { 2707 struct rl_softc *sc; 2708 struct mii_data *mii; 2709 2710 sc = ifp->if_softc; 2711 mii = device_get_softc(sc->rl_miibus); 2712 2713 RL_LOCK(sc); 2714 mii_pollstat(mii); 2715 RL_UNLOCK(sc); 2716 ifmr->ifm_active = mii->mii_media_active; 2717 ifmr->ifm_status = mii->mii_media_status; 2718 } 2719 2720 static int 2721 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2722 { 2723 struct rl_softc *sc = ifp->if_softc; 2724 struct ifreq *ifr = (struct ifreq *) data; 2725 struct mii_data *mii; 2726 int error = 0; 2727 2728 switch (command) { 2729 case SIOCSIFMTU: 2730 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > RL_JUMBO_MTU) { 2731 error = EINVAL; 2732 break; 2733 } 2734 if ((sc->rl_flags & RL_FLAG_NOJUMBO) != 0 && 2735 ifr->ifr_mtu > RL_MAX_FRAMELEN) { 2736 error = EINVAL; 2737 break; 2738 } 2739 RL_LOCK(sc); 2740 if (ifp->if_mtu != ifr->ifr_mtu) 2741 ifp->if_mtu = ifr->ifr_mtu; 2742 if (ifp->if_mtu > RL_TSO_MTU && 2743 (ifp->if_capenable & IFCAP_TSO4) != 0) { 2744 ifp->if_capenable &= ~IFCAP_TSO4; 2745 ifp->if_hwassist &= ~CSUM_TSO; 2746 } 2747 RL_UNLOCK(sc); 2748 break; 2749 case SIOCSIFFLAGS: 2750 RL_LOCK(sc); 2751 if ((ifp->if_flags & IFF_UP) != 0) { 2752 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2753 if (((ifp->if_flags ^ sc->rl_if_flags) 2754 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2755 re_set_rxmode(sc); 2756 } else 2757 re_init_locked(sc); 2758 } else { 2759 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2760 re_stop(sc); 2761 } 2762 sc->rl_if_flags = ifp->if_flags; 2763 RL_UNLOCK(sc); 2764 break; 2765 case SIOCADDMULTI: 2766 case SIOCDELMULTI: 2767 RL_LOCK(sc); 2768 re_set_rxmode(sc); 2769 RL_UNLOCK(sc); 2770 break; 2771 case SIOCGIFMEDIA: 2772 case SIOCSIFMEDIA: 2773 mii = device_get_softc(sc->rl_miibus); 2774 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2775 break; 2776 case SIOCSIFCAP: 2777 { 2778 int mask, reinit; 2779 2780 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2781 reinit = 0; 2782 #ifdef DEVICE_POLLING 2783 if (mask & IFCAP_POLLING) { 2784 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2785 error = ether_poll_register(re_poll, ifp); 2786 if (error) 2787 return(error); 2788 RL_LOCK(sc); 2789 /* Disable interrupts */ 2790 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2791 ifp->if_capenable |= IFCAP_POLLING; 2792 RL_UNLOCK(sc); 2793 } else { 2794 error = ether_poll_deregister(ifp); 2795 /* Enable interrupts. */ 2796 RL_LOCK(sc); 2797 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2798 ifp->if_capenable &= ~IFCAP_POLLING; 2799 RL_UNLOCK(sc); 2800 } 2801 } 2802 #endif /* DEVICE_POLLING */ 2803 if (mask & IFCAP_HWCSUM) { 2804 ifp->if_capenable ^= IFCAP_HWCSUM; 2805 if (ifp->if_capenable & IFCAP_TXCSUM) 2806 ifp->if_hwassist |= RE_CSUM_FEATURES; 2807 else 2808 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 2809 reinit = 1; 2810 } 2811 if (mask & IFCAP_VLAN_HWTAGGING) { 2812 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2813 reinit = 1; 2814 } 2815 if (mask & IFCAP_TSO4) { 2816 ifp->if_capenable ^= IFCAP_TSO4; 2817 if ((IFCAP_TSO4 & ifp->if_capenable) && 2818 (IFCAP_TSO4 & ifp->if_capabilities)) 2819 ifp->if_hwassist |= CSUM_TSO; 2820 else 2821 ifp->if_hwassist &= ~CSUM_TSO; 2822 if (ifp->if_mtu > RL_TSO_MTU && 2823 (ifp->if_capenable & IFCAP_TSO4) != 0) { 2824 ifp->if_capenable &= ~IFCAP_TSO4; 2825 ifp->if_hwassist &= ~CSUM_TSO; 2826 } 2827 } 2828 if ((mask & IFCAP_WOL) != 0 && 2829 (ifp->if_capabilities & IFCAP_WOL) != 0) { 2830 if ((mask & IFCAP_WOL_UCAST) != 0) 2831 ifp->if_capenable ^= IFCAP_WOL_UCAST; 2832 if ((mask & IFCAP_WOL_MCAST) != 0) 2833 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2834 if ((mask & IFCAP_WOL_MAGIC) != 0) 2835 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2836 } 2837 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) 2838 re_init(sc); 2839 VLAN_CAPABILITIES(ifp); 2840 } 2841 break; 2842 default: 2843 error = ether_ioctl(ifp, command, data); 2844 break; 2845 } 2846 2847 return (error); 2848 } 2849 2850 static void 2851 re_watchdog(struct rl_softc *sc) 2852 { 2853 struct ifnet *ifp; 2854 2855 RL_LOCK_ASSERT(sc); 2856 2857 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 2858 return; 2859 2860 ifp = sc->rl_ifp; 2861 re_txeof(sc); 2862 if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) { 2863 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 2864 "-- recovering\n"); 2865 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2866 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2867 return; 2868 } 2869 2870 if_printf(ifp, "watchdog timeout\n"); 2871 ifp->if_oerrors++; 2872 2873 re_rxeof(sc); 2874 re_init_locked(sc); 2875 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2876 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2877 } 2878 2879 /* 2880 * Stop the adapter and free any mbufs allocated to the 2881 * RX and TX lists. 2882 */ 2883 static void 2884 re_stop(struct rl_softc *sc) 2885 { 2886 int i; 2887 struct ifnet *ifp; 2888 struct rl_txdesc *txd; 2889 struct rl_rxdesc *rxd; 2890 2891 RL_LOCK_ASSERT(sc); 2892 2893 ifp = sc->rl_ifp; 2894 2895 sc->rl_watchdog_timer = 0; 2896 callout_stop(&sc->rl_stat_callout); 2897 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2898 2899 if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0) 2900 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB | 2901 RL_CMD_RX_ENB); 2902 else 2903 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2904 DELAY(1000); 2905 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2906 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 2907 2908 if (sc->rl_head != NULL) { 2909 m_freem(sc->rl_head); 2910 sc->rl_head = sc->rl_tail = NULL; 2911 } 2912 2913 /* Free the TX list buffers. */ 2914 2915 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 2916 txd = &sc->rl_ldata.rl_tx_desc[i]; 2917 if (txd->tx_m != NULL) { 2918 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2919 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2920 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2921 txd->tx_dmamap); 2922 m_freem(txd->tx_m); 2923 txd->tx_m = NULL; 2924 } 2925 } 2926 2927 /* Free the RX list buffers. */ 2928 2929 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2930 rxd = &sc->rl_ldata.rl_rx_desc[i]; 2931 if (rxd->rx_m != NULL) { 2932 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2933 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2934 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 2935 rxd->rx_dmamap); 2936 m_freem(rxd->rx_m); 2937 rxd->rx_m = NULL; 2938 } 2939 } 2940 } 2941 2942 /* 2943 * Device suspend routine. Stop the interface and save some PCI 2944 * settings in case the BIOS doesn't restore them properly on 2945 * resume. 2946 */ 2947 static int 2948 re_suspend(device_t dev) 2949 { 2950 struct rl_softc *sc; 2951 2952 sc = device_get_softc(dev); 2953 2954 RL_LOCK(sc); 2955 re_stop(sc); 2956 re_setwol(sc); 2957 sc->suspended = 1; 2958 RL_UNLOCK(sc); 2959 2960 return (0); 2961 } 2962 2963 /* 2964 * Device resume routine. Restore some PCI settings in case the BIOS 2965 * doesn't, re-enable busmastering, and restart the interface if 2966 * appropriate. 2967 */ 2968 static int 2969 re_resume(device_t dev) 2970 { 2971 struct rl_softc *sc; 2972 struct ifnet *ifp; 2973 2974 sc = device_get_softc(dev); 2975 2976 RL_LOCK(sc); 2977 2978 ifp = sc->rl_ifp; 2979 /* Take controller out of sleep mode. */ 2980 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 2981 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 2982 CSR_WRITE_1(sc, RL_GPIO, 2983 CSR_READ_1(sc, RL_GPIO) | 0x01); 2984 } 2985 2986 /* reinitialize interface if necessary */ 2987 if (ifp->if_flags & IFF_UP) 2988 re_init_locked(sc); 2989 2990 /* 2991 * Clear WOL matching such that normal Rx filtering 2992 * wouldn't interfere with WOL patterns. 2993 */ 2994 re_clrwol(sc); 2995 sc->suspended = 0; 2996 RL_UNLOCK(sc); 2997 2998 return (0); 2999 } 3000 3001 /* 3002 * Stop all chip I/O so that the kernel's probe routines don't 3003 * get confused by errant DMAs when rebooting. 3004 */ 3005 static int 3006 re_shutdown(device_t dev) 3007 { 3008 struct rl_softc *sc; 3009 3010 sc = device_get_softc(dev); 3011 3012 RL_LOCK(sc); 3013 re_stop(sc); 3014 /* 3015 * Mark interface as down since otherwise we will panic if 3016 * interrupt comes in later on, which can happen in some 3017 * cases. 3018 */ 3019 sc->rl_ifp->if_flags &= ~IFF_UP; 3020 re_setwol(sc); 3021 RL_UNLOCK(sc); 3022 3023 return (0); 3024 } 3025 3026 static void 3027 re_setwol(struct rl_softc *sc) 3028 { 3029 struct ifnet *ifp; 3030 int pmc; 3031 uint16_t pmstat; 3032 uint8_t v; 3033 3034 RL_LOCK_ASSERT(sc); 3035 3036 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3037 return; 3038 3039 ifp = sc->rl_ifp; 3040 /* Put controller into sleep mode. */ 3041 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3042 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3043 CSR_WRITE_1(sc, RL_GPIO, 3044 CSR_READ_1(sc, RL_GPIO) & ~0x01); 3045 } 3046 if ((ifp->if_capenable & IFCAP_WOL) != 0 && 3047 (sc->rl_flags & RL_FLAG_WOLRXENB) != 0) 3048 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB); 3049 /* Enable config register write. */ 3050 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3051 3052 /* Enable PME. */ 3053 v = CSR_READ_1(sc, RL_CFG1); 3054 v &= ~RL_CFG1_PME; 3055 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3056 v |= RL_CFG1_PME; 3057 CSR_WRITE_1(sc, RL_CFG1, v); 3058 3059 v = CSR_READ_1(sc, RL_CFG3); 3060 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3061 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3062 v |= RL_CFG3_WOL_MAGIC; 3063 CSR_WRITE_1(sc, RL_CFG3, v); 3064 3065 /* Config register write done. */ 3066 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3067 3068 v = CSR_READ_1(sc, RL_CFG5); 3069 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3070 v &= ~RL_CFG5_WOL_LANWAKE; 3071 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 3072 v |= RL_CFG5_WOL_UCAST; 3073 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 3074 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 3075 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3076 v |= RL_CFG5_WOL_LANWAKE; 3077 CSR_WRITE_1(sc, RL_CFG5, v); 3078 3079 /* 3080 * It seems that hardware resets its link speed to 100Mbps in 3081 * power down mode so switching to 100Mbps in driver is not 3082 * needed. 3083 */ 3084 3085 /* Request PME if WOL is requested. */ 3086 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 3087 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3088 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3089 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3090 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 3091 } 3092 3093 static void 3094 re_clrwol(struct rl_softc *sc) 3095 { 3096 int pmc; 3097 uint8_t v; 3098 3099 RL_LOCK_ASSERT(sc); 3100 3101 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3102 return; 3103 3104 /* Enable config register write. */ 3105 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3106 3107 v = CSR_READ_1(sc, RL_CFG3); 3108 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3109 CSR_WRITE_1(sc, RL_CFG3, v); 3110 3111 /* Config register write done. */ 3112 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3113 3114 v = CSR_READ_1(sc, RL_CFG5); 3115 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3116 v &= ~RL_CFG5_WOL_LANWAKE; 3117 CSR_WRITE_1(sc, RL_CFG5, v); 3118 } 3119