1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 1997, 1998-2003 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __FBSDID("$FreeBSD$"); 37 38 /* 39 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 40 * 41 * Written by Bill Paul <wpaul@windriver.com> 42 * Senior Networking Software Engineer 43 * Wind River Systems 44 */ 45 46 /* 47 * This driver is designed to support RealTek's next generation of 48 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 49 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 50 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 51 * 52 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 53 * with the older 8139 family, however it also supports a special 54 * C+ mode of operation that provides several new performance enhancing 55 * features. These include: 56 * 57 * o Descriptor based DMA mechanism. Each descriptor represents 58 * a single packet fragment. Data buffers may be aligned on 59 * any byte boundary. 60 * 61 * o 64-bit DMA 62 * 63 * o TCP/IP checksum offload for both RX and TX 64 * 65 * o High and normal priority transmit DMA rings 66 * 67 * o VLAN tag insertion and extraction 68 * 69 * o TCP large send (segmentation offload) 70 * 71 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 72 * programming API is fairly straightforward. The RX filtering, EEPROM 73 * access and PHY access is the same as it is on the older 8139 series 74 * chips. 75 * 76 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 77 * same programming API and feature set as the 8139C+ with the following 78 * differences and additions: 79 * 80 * o 1000Mbps mode 81 * 82 * o Jumbo frames 83 * 84 * o GMII and TBI ports/registers for interfacing with copper 85 * or fiber PHYs 86 * 87 * o RX and TX DMA rings can have up to 1024 descriptors 88 * (the 8139C+ allows a maximum of 64) 89 * 90 * o Slight differences in register layout from the 8139C+ 91 * 92 * The TX start and timer interrupt registers are at different locations 93 * on the 8169 than they are on the 8139C+. Also, the status word in the 94 * RX descriptor has a slightly different bit layout. The 8169 does not 95 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 96 * copper gigE PHY. 97 * 98 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 99 * (the 'S' stands for 'single-chip'). These devices have the same 100 * programming API as the older 8169, but also have some vendor-specific 101 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 102 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 103 * 104 * This driver takes advantage of the RX and TX checksum offload and 105 * VLAN tag insertion/extraction features. It also implements TX 106 * interrupt moderation using the timer interrupt registers, which 107 * significantly reduces TX interrupt load. There is also support 108 * for jumbo frames, however the 8169/8169S/8110S can not transmit 109 * jumbo frames larger than 7440, so the max MTU possible with this 110 * driver is 7422 bytes. 111 */ 112 113 #ifdef HAVE_KERNEL_OPTION_HEADERS 114 #include "opt_device_polling.h" 115 #endif 116 117 #include <sys/param.h> 118 #include <sys/endian.h> 119 #include <sys/systm.h> 120 #include <sys/sockio.h> 121 #include <sys/mbuf.h> 122 #include <sys/malloc.h> 123 #include <sys/module.h> 124 #include <sys/kernel.h> 125 #include <sys/socket.h> 126 #include <sys/lock.h> 127 #include <sys/mutex.h> 128 #include <sys/sysctl.h> 129 #include <sys/taskqueue.h> 130 131 #include <net/debugnet.h> 132 #include <net/if.h> 133 #include <net/if_var.h> 134 #include <net/if_arp.h> 135 #include <net/ethernet.h> 136 #include <net/if_dl.h> 137 #include <net/if_media.h> 138 #include <net/if_types.h> 139 #include <net/if_vlan_var.h> 140 141 #include <net/bpf.h> 142 143 #include <machine/bus.h> 144 #include <machine/resource.h> 145 #include <sys/bus.h> 146 #include <sys/rman.h> 147 148 #include <dev/mii/mii.h> 149 #include <dev/mii/miivar.h> 150 151 #include <dev/pci/pcireg.h> 152 #include <dev/pci/pcivar.h> 153 154 #include <dev/rl/if_rlreg.h> 155 156 MODULE_DEPEND(re, pci, 1, 1, 1); 157 MODULE_DEPEND(re, ether, 1, 1, 1); 158 MODULE_DEPEND(re, miibus, 1, 1, 1); 159 160 /* "device miibus" required. See GENERIC if you get errors here. */ 161 #include "miibus_if.h" 162 163 /* Tunables. */ 164 static int intr_filter = 0; 165 TUNABLE_INT("hw.re.intr_filter", &intr_filter); 166 static int msi_disable = 0; 167 TUNABLE_INT("hw.re.msi_disable", &msi_disable); 168 static int msix_disable = 0; 169 TUNABLE_INT("hw.re.msix_disable", &msix_disable); 170 static int prefer_iomap = 0; 171 TUNABLE_INT("hw.re.prefer_iomap", &prefer_iomap); 172 173 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 174 175 /* 176 * Various supported device vendors/types and their names. 177 */ 178 static const struct rl_type re_devs[] = { 179 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0, 180 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 181 { DLINK_VENDORID, DLINK_DEVICEID_530T_REVC, 0, 182 "D-Link DGE-530(T) Gigabit Ethernet Adapter" }, 183 { RT_VENDORID, RT_DEVICEID_8139, 0, 184 "RealTek 8139C+ 10/100BaseTX" }, 185 { RT_VENDORID, RT_DEVICEID_8101E, 0, 186 "RealTek 810xE PCIe 10/100baseTX" }, 187 { RT_VENDORID, RT_DEVICEID_8168, 0, 188 "RealTek 8168/8111 B/C/CP/D/DP/E/F/G PCIe Gigabit Ethernet" }, 189 { RT_VENDORID, RT_DEVICEID_8161, 0, 190 "RealTek 8168 Gigabit Ethernet" }, 191 { NCUBE_VENDORID, RT_DEVICEID_8168, 0, 192 "TP-Link TG-3468 v2 (RTL8168) Gigabit Ethernet" }, 193 { RT_VENDORID, RT_DEVICEID_8169, 0, 194 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" }, 195 { RT_VENDORID, RT_DEVICEID_8169SC, 0, 196 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 197 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0, 198 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 199 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0, 200 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 201 { USR_VENDORID, USR_DEVICEID_997902, 0, 202 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 203 }; 204 205 static const struct rl_hwrev re_hwrevs[] = { 206 { RL_HWREV_8139, RL_8139, "", RL_MTU }, 207 { RL_HWREV_8139A, RL_8139, "A", RL_MTU }, 208 { RL_HWREV_8139AG, RL_8139, "A-G", RL_MTU }, 209 { RL_HWREV_8139B, RL_8139, "B", RL_MTU }, 210 { RL_HWREV_8130, RL_8139, "8130", RL_MTU }, 211 { RL_HWREV_8139C, RL_8139, "C", RL_MTU }, 212 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C", RL_MTU }, 213 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+", RL_MTU }, 214 { RL_HWREV_8168B_SPIN1, RL_8169, "8168", RL_JUMBO_MTU }, 215 { RL_HWREV_8169, RL_8169, "8169", RL_JUMBO_MTU }, 216 { RL_HWREV_8169S, RL_8169, "8169S", RL_JUMBO_MTU }, 217 { RL_HWREV_8110S, RL_8169, "8110S", RL_JUMBO_MTU }, 218 { RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB", RL_JUMBO_MTU }, 219 { RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU }, 220 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL", RL_JUMBO_MTU }, 221 { RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU }, 222 { RL_HWREV_8100, RL_8139, "8100", RL_MTU }, 223 { RL_HWREV_8101, RL_8139, "8101", RL_MTU }, 224 { RL_HWREV_8100E, RL_8169, "8100E", RL_MTU }, 225 { RL_HWREV_8101E, RL_8169, "8101E", RL_MTU }, 226 { RL_HWREV_8102E, RL_8169, "8102E", RL_MTU }, 227 { RL_HWREV_8102EL, RL_8169, "8102EL", RL_MTU }, 228 { RL_HWREV_8102EL_SPIN1, RL_8169, "8102EL", RL_MTU }, 229 { RL_HWREV_8103E, RL_8169, "8103E", RL_MTU }, 230 { RL_HWREV_8401E, RL_8169, "8401E", RL_MTU }, 231 { RL_HWREV_8402, RL_8169, "8402", RL_MTU }, 232 { RL_HWREV_8105E, RL_8169, "8105E", RL_MTU }, 233 { RL_HWREV_8105E_SPIN1, RL_8169, "8105E", RL_MTU }, 234 { RL_HWREV_8106E, RL_8169, "8106E", RL_MTU }, 235 { RL_HWREV_8168B_SPIN2, RL_8169, "8168", RL_JUMBO_MTU }, 236 { RL_HWREV_8168B_SPIN3, RL_8169, "8168", RL_JUMBO_MTU }, 237 { RL_HWREV_8168C, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K }, 238 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K }, 239 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP", RL_JUMBO_MTU_6K }, 240 { RL_HWREV_8168D, RL_8169, "8168D/8111D", RL_JUMBO_MTU_9K }, 241 { RL_HWREV_8168DP, RL_8169, "8168DP/8111DP", RL_JUMBO_MTU_9K }, 242 { RL_HWREV_8168E, RL_8169, "8168E/8111E", RL_JUMBO_MTU_9K}, 243 { RL_HWREV_8168E_VL, RL_8169, "8168E/8111E-VL", RL_JUMBO_MTU_6K}, 244 { RL_HWREV_8168EP, RL_8169, "8168EP/8111EP", RL_JUMBO_MTU_9K}, 245 { RL_HWREV_8168F, RL_8169, "8168F/8111F", RL_JUMBO_MTU_9K}, 246 { RL_HWREV_8168G, RL_8169, "8168G/8111G", RL_JUMBO_MTU_9K}, 247 { RL_HWREV_8168GU, RL_8169, "8168GU/8111GU", RL_JUMBO_MTU_9K}, 248 { RL_HWREV_8168H, RL_8169, "8168H/8111H", RL_JUMBO_MTU_9K}, 249 { RL_HWREV_8411, RL_8169, "8411", RL_JUMBO_MTU_9K}, 250 { RL_HWREV_8411B, RL_8169, "8411B", RL_JUMBO_MTU_9K}, 251 { 0, 0, NULL, 0 } 252 }; 253 254 static int re_probe (device_t); 255 static int re_attach (device_t); 256 static int re_detach (device_t); 257 258 static int re_encap (struct rl_softc *, struct mbuf **); 259 260 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 261 static int re_allocmem (device_t, struct rl_softc *); 262 static __inline void re_discard_rxbuf 263 (struct rl_softc *, int); 264 static int re_newbuf (struct rl_softc *, int); 265 static int re_jumbo_newbuf (struct rl_softc *, int); 266 static int re_rx_list_init (struct rl_softc *); 267 static int re_jrx_list_init (struct rl_softc *); 268 static int re_tx_list_init (struct rl_softc *); 269 #ifdef RE_FIXUP_RX 270 static __inline void re_fixup_rx 271 (struct mbuf *); 272 #endif 273 static int re_rxeof (struct rl_softc *, int *); 274 static void re_txeof (struct rl_softc *); 275 #ifdef DEVICE_POLLING 276 static int re_poll (if_t, enum poll_cmd, int); 277 static int re_poll_locked (if_t, enum poll_cmd, int); 278 #endif 279 static int re_intr (void *); 280 static void re_intr_msi (void *); 281 static void re_tick (void *); 282 static void re_int_task (void *, int); 283 static void re_start (if_t); 284 static void re_start_locked (if_t); 285 static void re_start_tx (struct rl_softc *); 286 static int re_ioctl (if_t, u_long, caddr_t); 287 static void re_init (void *); 288 static void re_init_locked (struct rl_softc *); 289 static void re_stop (struct rl_softc *); 290 static void re_watchdog (struct rl_softc *); 291 static int re_suspend (device_t); 292 static int re_resume (device_t); 293 static int re_shutdown (device_t); 294 static int re_ifmedia_upd (if_t); 295 static void re_ifmedia_sts (if_t, struct ifmediareq *); 296 297 static void re_eeprom_putbyte (struct rl_softc *, int); 298 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 299 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 300 static int re_gmii_readreg (device_t, int, int); 301 static int re_gmii_writereg (device_t, int, int, int); 302 303 static int re_miibus_readreg (device_t, int, int); 304 static int re_miibus_writereg (device_t, int, int, int); 305 static void re_miibus_statchg (device_t); 306 307 static void re_set_jumbo (struct rl_softc *, int); 308 static void re_set_rxmode (struct rl_softc *); 309 static void re_reset (struct rl_softc *); 310 static void re_setwol (struct rl_softc *); 311 static void re_clrwol (struct rl_softc *); 312 static void re_set_linkspeed (struct rl_softc *); 313 314 DEBUGNET_DEFINE(re); 315 316 #ifdef DEV_NETMAP /* see ixgbe.c for details */ 317 #include <dev/netmap/if_re_netmap.h> 318 MODULE_DEPEND(re, netmap, 1, 1, 1); 319 #endif /* !DEV_NETMAP */ 320 321 #ifdef RE_DIAG 322 static int re_diag (struct rl_softc *); 323 #endif 324 325 static void re_add_sysctls (struct rl_softc *); 326 static int re_sysctl_stats (SYSCTL_HANDLER_ARGS); 327 static int sysctl_int_range (SYSCTL_HANDLER_ARGS, int, int); 328 static int sysctl_hw_re_int_mod (SYSCTL_HANDLER_ARGS); 329 330 static device_method_t re_methods[] = { 331 /* Device interface */ 332 DEVMETHOD(device_probe, re_probe), 333 DEVMETHOD(device_attach, re_attach), 334 DEVMETHOD(device_detach, re_detach), 335 DEVMETHOD(device_suspend, re_suspend), 336 DEVMETHOD(device_resume, re_resume), 337 DEVMETHOD(device_shutdown, re_shutdown), 338 339 /* MII interface */ 340 DEVMETHOD(miibus_readreg, re_miibus_readreg), 341 DEVMETHOD(miibus_writereg, re_miibus_writereg), 342 DEVMETHOD(miibus_statchg, re_miibus_statchg), 343 344 DEVMETHOD_END 345 }; 346 347 static driver_t re_driver = { 348 "re", 349 re_methods, 350 sizeof(struct rl_softc) 351 }; 352 353 DRIVER_MODULE(re, pci, re_driver, 0, 0); 354 DRIVER_MODULE(miibus, re, miibus_driver, 0, 0); 355 356 #define EE_SET(x) \ 357 CSR_WRITE_1(sc, RL_EECMD, \ 358 CSR_READ_1(sc, RL_EECMD) | x) 359 360 #define EE_CLR(x) \ 361 CSR_WRITE_1(sc, RL_EECMD, \ 362 CSR_READ_1(sc, RL_EECMD) & ~x) 363 364 /* 365 * Send a read command and address to the EEPROM, check for ACK. 366 */ 367 static void 368 re_eeprom_putbyte(struct rl_softc *sc, int addr) 369 { 370 int d, i; 371 372 d = addr | (RL_9346_READ << sc->rl_eewidth); 373 374 /* 375 * Feed in each bit and strobe the clock. 376 */ 377 378 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 379 if (d & i) { 380 EE_SET(RL_EE_DATAIN); 381 } else { 382 EE_CLR(RL_EE_DATAIN); 383 } 384 DELAY(100); 385 EE_SET(RL_EE_CLK); 386 DELAY(150); 387 EE_CLR(RL_EE_CLK); 388 DELAY(100); 389 } 390 } 391 392 /* 393 * Read a word of data stored in the EEPROM at address 'addr.' 394 */ 395 static void 396 re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest) 397 { 398 int i; 399 u_int16_t word = 0; 400 401 /* 402 * Send address of word we want to read. 403 */ 404 re_eeprom_putbyte(sc, addr); 405 406 /* 407 * Start reading bits from EEPROM. 408 */ 409 for (i = 0x8000; i; i >>= 1) { 410 EE_SET(RL_EE_CLK); 411 DELAY(100); 412 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 413 word |= i; 414 EE_CLR(RL_EE_CLK); 415 DELAY(100); 416 } 417 418 *dest = word; 419 } 420 421 /* 422 * Read a sequence of words from the EEPROM. 423 */ 424 static void 425 re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt) 426 { 427 int i; 428 u_int16_t word = 0, *ptr; 429 430 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 431 432 DELAY(100); 433 434 for (i = 0; i < cnt; i++) { 435 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 436 re_eeprom_getword(sc, off + i, &word); 437 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 438 ptr = (u_int16_t *)(dest + (i * 2)); 439 *ptr = word; 440 } 441 442 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 443 } 444 445 static int 446 re_gmii_readreg(device_t dev, int phy, int reg) 447 { 448 struct rl_softc *sc; 449 u_int32_t rval; 450 int i; 451 452 sc = device_get_softc(dev); 453 454 /* Let the rgephy driver read the GMEDIASTAT register */ 455 456 if (reg == RL_GMEDIASTAT) { 457 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 458 return (rval); 459 } 460 461 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 462 463 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 464 rval = CSR_READ_4(sc, RL_PHYAR); 465 if (rval & RL_PHYAR_BUSY) 466 break; 467 DELAY(25); 468 } 469 470 if (i == RL_PHY_TIMEOUT) { 471 device_printf(sc->rl_dev, "PHY read failed\n"); 472 return (0); 473 } 474 475 /* 476 * Controller requires a 20us delay to process next MDIO request. 477 */ 478 DELAY(20); 479 480 return (rval & RL_PHYAR_PHYDATA); 481 } 482 483 static int 484 re_gmii_writereg(device_t dev, int phy, int reg, int data) 485 { 486 struct rl_softc *sc; 487 u_int32_t rval; 488 int i; 489 490 sc = device_get_softc(dev); 491 492 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 493 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 494 495 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 496 rval = CSR_READ_4(sc, RL_PHYAR); 497 if (!(rval & RL_PHYAR_BUSY)) 498 break; 499 DELAY(25); 500 } 501 502 if (i == RL_PHY_TIMEOUT) { 503 device_printf(sc->rl_dev, "PHY write failed\n"); 504 return (0); 505 } 506 507 /* 508 * Controller requires a 20us delay to process next MDIO request. 509 */ 510 DELAY(20); 511 512 return (0); 513 } 514 515 static int 516 re_miibus_readreg(device_t dev, int phy, int reg) 517 { 518 struct rl_softc *sc; 519 u_int16_t rval = 0; 520 u_int16_t re8139_reg = 0; 521 522 sc = device_get_softc(dev); 523 524 if (sc->rl_type == RL_8169) { 525 rval = re_gmii_readreg(dev, phy, reg); 526 return (rval); 527 } 528 529 switch (reg) { 530 case MII_BMCR: 531 re8139_reg = RL_BMCR; 532 break; 533 case MII_BMSR: 534 re8139_reg = RL_BMSR; 535 break; 536 case MII_ANAR: 537 re8139_reg = RL_ANAR; 538 break; 539 case MII_ANER: 540 re8139_reg = RL_ANER; 541 break; 542 case MII_ANLPAR: 543 re8139_reg = RL_LPAR; 544 break; 545 case MII_PHYIDR1: 546 case MII_PHYIDR2: 547 return (0); 548 /* 549 * Allow the rlphy driver to read the media status 550 * register. If we have a link partner which does not 551 * support NWAY, this is the register which will tell 552 * us the results of parallel detection. 553 */ 554 case RL_MEDIASTAT: 555 rval = CSR_READ_1(sc, RL_MEDIASTAT); 556 return (rval); 557 default: 558 device_printf(sc->rl_dev, "bad phy register\n"); 559 return (0); 560 } 561 rval = CSR_READ_2(sc, re8139_reg); 562 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 563 /* 8139C+ has different bit layout. */ 564 rval &= ~(BMCR_LOOP | BMCR_ISO); 565 } 566 return (rval); 567 } 568 569 static int 570 re_miibus_writereg(device_t dev, int phy, int reg, int data) 571 { 572 struct rl_softc *sc; 573 u_int16_t re8139_reg = 0; 574 int rval = 0; 575 576 sc = device_get_softc(dev); 577 578 if (sc->rl_type == RL_8169) { 579 rval = re_gmii_writereg(dev, phy, reg, data); 580 return (rval); 581 } 582 583 switch (reg) { 584 case MII_BMCR: 585 re8139_reg = RL_BMCR; 586 if (sc->rl_type == RL_8139CPLUS) { 587 /* 8139C+ has different bit layout. */ 588 data &= ~(BMCR_LOOP | BMCR_ISO); 589 } 590 break; 591 case MII_BMSR: 592 re8139_reg = RL_BMSR; 593 break; 594 case MII_ANAR: 595 re8139_reg = RL_ANAR; 596 break; 597 case MII_ANER: 598 re8139_reg = RL_ANER; 599 break; 600 case MII_ANLPAR: 601 re8139_reg = RL_LPAR; 602 break; 603 case MII_PHYIDR1: 604 case MII_PHYIDR2: 605 return (0); 606 break; 607 default: 608 device_printf(sc->rl_dev, "bad phy register\n"); 609 return (0); 610 } 611 CSR_WRITE_2(sc, re8139_reg, data); 612 return (0); 613 } 614 615 static void 616 re_miibus_statchg(device_t dev) 617 { 618 struct rl_softc *sc; 619 if_t ifp; 620 struct mii_data *mii; 621 622 sc = device_get_softc(dev); 623 mii = device_get_softc(sc->rl_miibus); 624 ifp = sc->rl_ifp; 625 if (mii == NULL || ifp == NULL || 626 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 627 return; 628 629 sc->rl_flags &= ~RL_FLAG_LINK; 630 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 631 (IFM_ACTIVE | IFM_AVALID)) { 632 switch (IFM_SUBTYPE(mii->mii_media_active)) { 633 case IFM_10_T: 634 case IFM_100_TX: 635 sc->rl_flags |= RL_FLAG_LINK; 636 break; 637 case IFM_1000_T: 638 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0) 639 break; 640 sc->rl_flags |= RL_FLAG_LINK; 641 break; 642 default: 643 break; 644 } 645 } 646 /* 647 * RealTek controllers do not provide any interface to the RX/TX 648 * MACs for resolved speed, duplex and flow-control parameters. 649 */ 650 } 651 652 static u_int 653 re_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 654 { 655 uint32_t h, *hashes = arg; 656 657 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26; 658 if (h < 32) 659 hashes[0] |= (1 << h); 660 else 661 hashes[1] |= (1 << (h - 32)); 662 663 return (1); 664 } 665 666 /* 667 * Set the RX configuration and 64-bit multicast hash filter. 668 */ 669 static void 670 re_set_rxmode(struct rl_softc *sc) 671 { 672 if_t ifp; 673 uint32_t h, hashes[2] = { 0, 0 }; 674 uint32_t rxfilt; 675 676 RL_LOCK_ASSERT(sc); 677 678 ifp = sc->rl_ifp; 679 680 rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD; 681 if ((sc->rl_flags & RL_FLAG_EARLYOFF) != 0) 682 rxfilt |= RL_RXCFG_EARLYOFF; 683 else if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0) 684 rxfilt |= RL_RXCFG_EARLYOFFV2; 685 686 if (if_getflags(ifp) & (IFF_ALLMULTI | IFF_PROMISC)) { 687 if (if_getflags(ifp) & IFF_PROMISC) 688 rxfilt |= RL_RXCFG_RX_ALLPHYS; 689 /* 690 * Unlike other hardwares, we have to explicitly set 691 * RL_RXCFG_RX_MULTI to receive multicast frames in 692 * promiscuous mode. 693 */ 694 rxfilt |= RL_RXCFG_RX_MULTI; 695 hashes[0] = hashes[1] = 0xffffffff; 696 goto done; 697 } 698 699 if_foreach_llmaddr(ifp, re_hash_maddr, hashes); 700 701 if (hashes[0] != 0 || hashes[1] != 0) { 702 /* 703 * For some unfathomable reason, RealTek decided to 704 * reverse the order of the multicast hash registers 705 * in the PCI Express parts. This means we have to 706 * write the hash pattern in reverse order for those 707 * devices. 708 */ 709 if ((sc->rl_flags & RL_FLAG_PCIE) != 0) { 710 h = bswap32(hashes[0]); 711 hashes[0] = bswap32(hashes[1]); 712 hashes[1] = h; 713 } 714 rxfilt |= RL_RXCFG_RX_MULTI; 715 } 716 717 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168F) { 718 /* Disable multicast filtering due to silicon bug. */ 719 hashes[0] = 0xffffffff; 720 hashes[1] = 0xffffffff; 721 } 722 723 done: 724 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 725 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 726 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 727 } 728 729 static void 730 re_reset(struct rl_softc *sc) 731 { 732 int i; 733 734 RL_LOCK_ASSERT(sc); 735 736 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 737 738 for (i = 0; i < RL_TIMEOUT; i++) { 739 DELAY(10); 740 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 741 break; 742 } 743 if (i == RL_TIMEOUT) 744 device_printf(sc->rl_dev, "reset never completed!\n"); 745 746 if ((sc->rl_flags & RL_FLAG_MACRESET) != 0) 747 CSR_WRITE_1(sc, 0x82, 1); 748 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169S) 749 re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0); 750 } 751 752 #ifdef RE_DIAG 753 754 /* 755 * The following routine is designed to test for a defect on some 756 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 757 * lines connected to the bus, however for a 32-bit only card, they 758 * should be pulled high. The result of this defect is that the 759 * NIC will not work right if you plug it into a 64-bit slot: DMA 760 * operations will be done with 64-bit transfers, which will fail 761 * because the 64-bit data lines aren't connected. 762 * 763 * There's no way to work around this (short of talking a soldering 764 * iron to the board), however we can detect it. The method we use 765 * here is to put the NIC into digital loopback mode, set the receiver 766 * to promiscuous mode, and then try to send a frame. We then compare 767 * the frame data we sent to what was received. If the data matches, 768 * then the NIC is working correctly, otherwise we know the user has 769 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 770 * slot. In the latter case, there's no way the NIC can work correctly, 771 * so we print out a message on the console and abort the device attach. 772 */ 773 774 static int 775 re_diag(struct rl_softc *sc) 776 { 777 if_t ifp = sc->rl_ifp; 778 struct mbuf *m0; 779 struct ether_header *eh; 780 struct rl_desc *cur_rx; 781 u_int16_t status; 782 u_int32_t rxstat; 783 int total_len, i, error = 0, phyaddr; 784 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 785 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 786 787 /* Allocate a single mbuf */ 788 MGETHDR(m0, M_NOWAIT, MT_DATA); 789 if (m0 == NULL) 790 return (ENOBUFS); 791 792 RL_LOCK(sc); 793 794 /* 795 * Initialize the NIC in test mode. This sets the chip up 796 * so that it can send and receive frames, but performs the 797 * following special functions: 798 * - Puts receiver in promiscuous mode 799 * - Enables digital loopback mode 800 * - Leaves interrupts turned off 801 */ 802 803 if_setflagbit(ifp, IFF_PROMISC, 0); 804 sc->rl_testmode = 1; 805 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 806 re_init_locked(sc); 807 sc->rl_flags |= RL_FLAG_LINK; 808 if (sc->rl_type == RL_8169) 809 phyaddr = 1; 810 else 811 phyaddr = 0; 812 813 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 814 for (i = 0; i < RL_TIMEOUT; i++) { 815 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 816 if (!(status & BMCR_RESET)) 817 break; 818 } 819 820 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 821 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 822 823 DELAY(100000); 824 825 /* Put some data in the mbuf */ 826 827 eh = mtod(m0, struct ether_header *); 828 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 829 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 830 eh->ether_type = htons(ETHERTYPE_IP); 831 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 832 833 /* 834 * Queue the packet, start transmission. 835 * Note: IF_HANDOFF() ultimately calls re_start() for us. 836 */ 837 838 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 839 RL_UNLOCK(sc); 840 /* XXX: re_diag must not be called when in ALTQ mode */ 841 if_handoff(ifp, m0, ifp); 842 RL_LOCK(sc); 843 m0 = NULL; 844 845 /* Wait for it to propagate through the chip */ 846 847 DELAY(100000); 848 for (i = 0; i < RL_TIMEOUT; i++) { 849 status = CSR_READ_2(sc, RL_ISR); 850 CSR_WRITE_2(sc, RL_ISR, status); 851 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 852 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 853 break; 854 DELAY(10); 855 } 856 857 if (i == RL_TIMEOUT) { 858 device_printf(sc->rl_dev, 859 "diagnostic failed, failed to receive packet in" 860 " loopback mode\n"); 861 error = EIO; 862 goto done; 863 } 864 865 /* 866 * The packet should have been dumped into the first 867 * entry in the RX DMA ring. Grab it from there. 868 */ 869 870 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 871 sc->rl_ldata.rl_rx_list_map, 872 BUS_DMASYNC_POSTREAD); 873 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 874 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 875 BUS_DMASYNC_POSTREAD); 876 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 877 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 878 879 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 880 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 881 eh = mtod(m0, struct ether_header *); 882 883 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 884 total_len = RL_RXBYTES(cur_rx); 885 rxstat = le32toh(cur_rx->rl_cmdstat); 886 887 if (total_len != ETHER_MIN_LEN) { 888 device_printf(sc->rl_dev, 889 "diagnostic failed, received short packet\n"); 890 error = EIO; 891 goto done; 892 } 893 894 /* Test that the received packet data matches what we sent. */ 895 896 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 897 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 898 ntohs(eh->ether_type) != ETHERTYPE_IP) { 899 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 900 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 901 dst, ":", src, ":", ETHERTYPE_IP); 902 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 903 eh->ether_dhost, ":", eh->ether_shost, ":", 904 ntohs(eh->ether_type)); 905 device_printf(sc->rl_dev, "You may have a defective 32-bit " 906 "NIC plugged into a 64-bit PCI slot.\n"); 907 device_printf(sc->rl_dev, "Please re-install the NIC in a " 908 "32-bit slot for proper operation.\n"); 909 device_printf(sc->rl_dev, "Read the re(4) man page for more " 910 "details.\n"); 911 error = EIO; 912 } 913 914 done: 915 /* Turn interface off, release resources */ 916 917 sc->rl_testmode = 0; 918 sc->rl_flags &= ~RL_FLAG_LINK; 919 if_setflagbit(ifp, 0, IFF_PROMISC); 920 re_stop(sc); 921 if (m0 != NULL) 922 m_freem(m0); 923 924 RL_UNLOCK(sc); 925 926 return (error); 927 } 928 929 #endif 930 931 /* 932 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 933 * IDs against our list and return a device name if we find a match. 934 */ 935 static int 936 re_probe(device_t dev) 937 { 938 const struct rl_type *t; 939 uint16_t devid, vendor; 940 uint16_t revid, sdevid; 941 int i; 942 943 vendor = pci_get_vendor(dev); 944 devid = pci_get_device(dev); 945 revid = pci_get_revid(dev); 946 sdevid = pci_get_subdevice(dev); 947 948 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 949 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 950 /* 951 * Only attach to rev. 3 of the Linksys EG1032 adapter. 952 * Rev. 2 is supported by sk(4). 953 */ 954 return (ENXIO); 955 } 956 } 957 958 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 959 if (revid != 0x20) { 960 /* 8139, let rl(4) take care of this device. */ 961 return (ENXIO); 962 } 963 } 964 965 t = re_devs; 966 for (i = 0; i < nitems(re_devs); i++, t++) { 967 if (vendor == t->rl_vid && devid == t->rl_did) { 968 device_set_desc(dev, t->rl_name); 969 return (BUS_PROBE_DEFAULT); 970 } 971 } 972 973 return (ENXIO); 974 } 975 976 /* 977 * Map a single buffer address. 978 */ 979 980 static void 981 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 982 { 983 bus_addr_t *addr; 984 985 if (error) 986 return; 987 988 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 989 addr = arg; 990 *addr = segs->ds_addr; 991 } 992 993 static int 994 re_allocmem(device_t dev, struct rl_softc *sc) 995 { 996 bus_addr_t lowaddr; 997 bus_size_t rx_list_size, tx_list_size; 998 int error; 999 int i; 1000 1001 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 1002 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 1003 1004 /* 1005 * Allocate the parent bus DMA tag appropriate for PCI. 1006 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD 1007 * register should be set. However some RealTek chips are known 1008 * to be buggy on DAC handling, therefore disable DAC by limiting 1009 * DMA address space to 32bit. PCIe variants of RealTek chips 1010 * may not have the limitation. 1011 */ 1012 lowaddr = BUS_SPACE_MAXADDR; 1013 if ((sc->rl_flags & RL_FLAG_PCIE) == 0) 1014 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1015 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 1016 lowaddr, BUS_SPACE_MAXADDR, NULL, NULL, 1017 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 1018 NULL, NULL, &sc->rl_parent_tag); 1019 if (error) { 1020 device_printf(dev, "could not allocate parent DMA tag\n"); 1021 return (error); 1022 } 1023 1024 /* 1025 * Allocate map for TX mbufs. 1026 */ 1027 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 1028 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1029 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 1030 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 1031 if (error) { 1032 device_printf(dev, "could not allocate TX DMA tag\n"); 1033 return (error); 1034 } 1035 1036 /* 1037 * Allocate map for RX mbufs. 1038 */ 1039 1040 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 1041 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 1042 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1043 MJUM9BYTES, 1, MJUM9BYTES, 0, NULL, NULL, 1044 &sc->rl_ldata.rl_jrx_mtag); 1045 if (error) { 1046 device_printf(dev, 1047 "could not allocate jumbo RX DMA tag\n"); 1048 return (error); 1049 } 1050 } 1051 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 1052 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1053 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 1054 if (error) { 1055 device_printf(dev, "could not allocate RX DMA tag\n"); 1056 return (error); 1057 } 1058 1059 /* 1060 * Allocate map for TX descriptor list. 1061 */ 1062 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1063 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1064 NULL, tx_list_size, 1, tx_list_size, 0, 1065 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1066 if (error) { 1067 device_printf(dev, "could not allocate TX DMA ring tag\n"); 1068 return (error); 1069 } 1070 1071 /* Allocate DMA'able memory for the TX ring */ 1072 1073 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1074 (void **)&sc->rl_ldata.rl_tx_list, 1075 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1076 &sc->rl_ldata.rl_tx_list_map); 1077 if (error) { 1078 device_printf(dev, "could not allocate TX DMA ring\n"); 1079 return (error); 1080 } 1081 1082 /* Load the map for the TX ring. */ 1083 1084 sc->rl_ldata.rl_tx_list_addr = 0; 1085 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1086 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1087 tx_list_size, re_dma_map_addr, 1088 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1089 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 1090 device_printf(dev, "could not load TX DMA ring\n"); 1091 return (ENOMEM); 1092 } 1093 1094 /* Create DMA maps for TX buffers */ 1095 1096 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1097 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1098 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1099 if (error) { 1100 device_printf(dev, "could not create DMA map for TX\n"); 1101 return (error); 1102 } 1103 } 1104 1105 /* 1106 * Allocate map for RX descriptor list. 1107 */ 1108 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1109 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1110 NULL, rx_list_size, 1, rx_list_size, 0, 1111 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1112 if (error) { 1113 device_printf(dev, "could not create RX DMA ring tag\n"); 1114 return (error); 1115 } 1116 1117 /* Allocate DMA'able memory for the RX ring */ 1118 1119 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1120 (void **)&sc->rl_ldata.rl_rx_list, 1121 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1122 &sc->rl_ldata.rl_rx_list_map); 1123 if (error) { 1124 device_printf(dev, "could not allocate RX DMA ring\n"); 1125 return (error); 1126 } 1127 1128 /* Load the map for the RX ring. */ 1129 1130 sc->rl_ldata.rl_rx_list_addr = 0; 1131 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1132 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1133 rx_list_size, re_dma_map_addr, 1134 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1135 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1136 device_printf(dev, "could not load RX DMA ring\n"); 1137 return (ENOMEM); 1138 } 1139 1140 /* Create DMA maps for RX buffers */ 1141 1142 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 1143 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0, 1144 &sc->rl_ldata.rl_jrx_sparemap); 1145 if (error) { 1146 device_printf(dev, 1147 "could not create spare DMA map for jumbo RX\n"); 1148 return (error); 1149 } 1150 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1151 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0, 1152 &sc->rl_ldata.rl_jrx_desc[i].rx_dmamap); 1153 if (error) { 1154 device_printf(dev, 1155 "could not create DMA map for jumbo RX\n"); 1156 return (error); 1157 } 1158 } 1159 } 1160 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1161 &sc->rl_ldata.rl_rx_sparemap); 1162 if (error) { 1163 device_printf(dev, "could not create spare DMA map for RX\n"); 1164 return (error); 1165 } 1166 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1167 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1168 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1169 if (error) { 1170 device_printf(dev, "could not create DMA map for RX\n"); 1171 return (error); 1172 } 1173 } 1174 1175 /* Create DMA map for statistics. */ 1176 error = bus_dma_tag_create(sc->rl_parent_tag, RL_DUMP_ALIGN, 0, 1177 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1178 sizeof(struct rl_stats), 1, sizeof(struct rl_stats), 0, NULL, NULL, 1179 &sc->rl_ldata.rl_stag); 1180 if (error) { 1181 device_printf(dev, "could not create statistics DMA tag\n"); 1182 return (error); 1183 } 1184 /* Allocate DMA'able memory for statistics. */ 1185 error = bus_dmamem_alloc(sc->rl_ldata.rl_stag, 1186 (void **)&sc->rl_ldata.rl_stats, 1187 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1188 &sc->rl_ldata.rl_smap); 1189 if (error) { 1190 device_printf(dev, 1191 "could not allocate statistics DMA memory\n"); 1192 return (error); 1193 } 1194 /* Load the map for statistics. */ 1195 sc->rl_ldata.rl_stats_addr = 0; 1196 error = bus_dmamap_load(sc->rl_ldata.rl_stag, sc->rl_ldata.rl_smap, 1197 sc->rl_ldata.rl_stats, sizeof(struct rl_stats), re_dma_map_addr, 1198 &sc->rl_ldata.rl_stats_addr, BUS_DMA_NOWAIT); 1199 if (error != 0 || sc->rl_ldata.rl_stats_addr == 0) { 1200 device_printf(dev, "could not load statistics DMA memory\n"); 1201 return (ENOMEM); 1202 } 1203 1204 return (0); 1205 } 1206 1207 /* 1208 * Attach the interface. Allocate softc structures, do ifmedia 1209 * setup and ethernet/BPF attach. 1210 */ 1211 static int 1212 re_attach(device_t dev) 1213 { 1214 u_char eaddr[ETHER_ADDR_LEN]; 1215 u_int16_t as[ETHER_ADDR_LEN / 2]; 1216 struct rl_softc *sc; 1217 if_t ifp; 1218 const struct rl_hwrev *hw_rev; 1219 int capmask, error = 0, hwrev, i, msic, msixc, 1220 phy, reg, rid; 1221 u_int32_t cap, ctl; 1222 u_int16_t devid, re_did = 0; 1223 uint8_t cfg; 1224 1225 sc = device_get_softc(dev); 1226 sc->rl_dev = dev; 1227 1228 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1229 MTX_DEF); 1230 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1231 1232 /* 1233 * Map control/status registers. 1234 */ 1235 pci_enable_busmaster(dev); 1236 1237 devid = pci_get_device(dev); 1238 /* 1239 * Prefer memory space register mapping over IO space. 1240 * Because RTL8169SC does not seem to work when memory mapping 1241 * is used always activate io mapping. 1242 */ 1243 if (devid == RT_DEVICEID_8169SC) 1244 prefer_iomap = 1; 1245 if (prefer_iomap == 0) { 1246 sc->rl_res_id = PCIR_BAR(1); 1247 sc->rl_res_type = SYS_RES_MEMORY; 1248 /* RTL8168/8101E seems to use different BARs. */ 1249 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E) 1250 sc->rl_res_id = PCIR_BAR(2); 1251 } else { 1252 sc->rl_res_id = PCIR_BAR(0); 1253 sc->rl_res_type = SYS_RES_IOPORT; 1254 } 1255 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1256 &sc->rl_res_id, RF_ACTIVE); 1257 if (sc->rl_res == NULL && prefer_iomap == 0) { 1258 sc->rl_res_id = PCIR_BAR(0); 1259 sc->rl_res_type = SYS_RES_IOPORT; 1260 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1261 &sc->rl_res_id, RF_ACTIVE); 1262 } 1263 if (sc->rl_res == NULL) { 1264 device_printf(dev, "couldn't map ports/memory\n"); 1265 error = ENXIO; 1266 goto fail; 1267 } 1268 1269 sc->rl_btag = rman_get_bustag(sc->rl_res); 1270 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1271 1272 msic = pci_msi_count(dev); 1273 msixc = pci_msix_count(dev); 1274 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 1275 sc->rl_flags |= RL_FLAG_PCIE; 1276 sc->rl_expcap = reg; 1277 } 1278 if (bootverbose) { 1279 device_printf(dev, "MSI count : %d\n", msic); 1280 device_printf(dev, "MSI-X count : %d\n", msixc); 1281 } 1282 if (msix_disable > 0) 1283 msixc = 0; 1284 if (msi_disable > 0) 1285 msic = 0; 1286 /* Prefer MSI-X to MSI. */ 1287 if (msixc > 0) { 1288 msixc = RL_MSI_MESSAGES; 1289 rid = PCIR_BAR(4); 1290 sc->rl_res_pba = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1291 &rid, RF_ACTIVE); 1292 if (sc->rl_res_pba == NULL) { 1293 device_printf(sc->rl_dev, 1294 "could not allocate MSI-X PBA resource\n"); 1295 } 1296 if (sc->rl_res_pba != NULL && 1297 pci_alloc_msix(dev, &msixc) == 0) { 1298 if (msixc == RL_MSI_MESSAGES) { 1299 device_printf(dev, "Using %d MSI-X message\n", 1300 msixc); 1301 sc->rl_flags |= RL_FLAG_MSIX; 1302 } else 1303 pci_release_msi(dev); 1304 } 1305 if ((sc->rl_flags & RL_FLAG_MSIX) == 0) { 1306 if (sc->rl_res_pba != NULL) 1307 bus_release_resource(dev, SYS_RES_MEMORY, rid, 1308 sc->rl_res_pba); 1309 sc->rl_res_pba = NULL; 1310 msixc = 0; 1311 } 1312 } 1313 /* Prefer MSI to INTx. */ 1314 if (msixc == 0 && msic > 0) { 1315 msic = RL_MSI_MESSAGES; 1316 if (pci_alloc_msi(dev, &msic) == 0) { 1317 if (msic == RL_MSI_MESSAGES) { 1318 device_printf(dev, "Using %d MSI message\n", 1319 msic); 1320 sc->rl_flags |= RL_FLAG_MSI; 1321 /* Explicitly set MSI enable bit. */ 1322 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1323 cfg = CSR_READ_1(sc, RL_CFG2); 1324 cfg |= RL_CFG2_MSI; 1325 CSR_WRITE_1(sc, RL_CFG2, cfg); 1326 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1327 } else 1328 pci_release_msi(dev); 1329 } 1330 if ((sc->rl_flags & RL_FLAG_MSI) == 0) 1331 msic = 0; 1332 } 1333 1334 /* Allocate interrupt */ 1335 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) { 1336 rid = 0; 1337 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1338 RF_SHAREABLE | RF_ACTIVE); 1339 if (sc->rl_irq[0] == NULL) { 1340 device_printf(dev, "couldn't allocate IRQ resources\n"); 1341 error = ENXIO; 1342 goto fail; 1343 } 1344 } else { 1345 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1346 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1347 SYS_RES_IRQ, &rid, RF_ACTIVE); 1348 if (sc->rl_irq[i] == NULL) { 1349 device_printf(dev, 1350 "couldn't allocate IRQ resources for " 1351 "message %d\n", rid); 1352 error = ENXIO; 1353 goto fail; 1354 } 1355 } 1356 } 1357 1358 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1359 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1360 cfg = CSR_READ_1(sc, RL_CFG2); 1361 if ((cfg & RL_CFG2_MSI) != 0) { 1362 device_printf(dev, "turning off MSI enable bit.\n"); 1363 cfg &= ~RL_CFG2_MSI; 1364 CSR_WRITE_1(sc, RL_CFG2, cfg); 1365 } 1366 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1367 } 1368 1369 /* Disable ASPM L0S/L1 and CLKREQ. */ 1370 if (sc->rl_expcap != 0) { 1371 cap = pci_read_config(dev, sc->rl_expcap + 1372 PCIER_LINK_CAP, 2); 1373 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { 1374 ctl = pci_read_config(dev, sc->rl_expcap + 1375 PCIER_LINK_CTL, 2); 1376 if ((ctl & (PCIEM_LINK_CTL_ECPM | 1377 PCIEM_LINK_CTL_ASPMC))!= 0) { 1378 ctl &= ~(PCIEM_LINK_CTL_ECPM | 1379 PCIEM_LINK_CTL_ASPMC); 1380 pci_write_config(dev, sc->rl_expcap + 1381 PCIER_LINK_CTL, ctl, 2); 1382 device_printf(dev, "ASPM disabled\n"); 1383 } 1384 } else 1385 device_printf(dev, "no ASPM capability\n"); 1386 } 1387 1388 hw_rev = re_hwrevs; 1389 hwrev = CSR_READ_4(sc, RL_TXCFG); 1390 switch (hwrev & 0x70000000) { 1391 case 0x00000000: 1392 case 0x10000000: 1393 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000); 1394 hwrev &= (RL_TXCFG_HWREV | 0x80000000); 1395 break; 1396 default: 1397 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000); 1398 sc->rl_macrev = hwrev & 0x00700000; 1399 hwrev &= RL_TXCFG_HWREV; 1400 break; 1401 } 1402 device_printf(dev, "MAC rev. 0x%08x\n", sc->rl_macrev); 1403 while (hw_rev->rl_desc != NULL) { 1404 if (hw_rev->rl_rev == hwrev) { 1405 sc->rl_type = hw_rev->rl_type; 1406 sc->rl_hwrev = hw_rev; 1407 break; 1408 } 1409 hw_rev++; 1410 } 1411 if (hw_rev->rl_desc == NULL) { 1412 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev); 1413 error = ENXIO; 1414 goto fail; 1415 } 1416 1417 switch (hw_rev->rl_rev) { 1418 case RL_HWREV_8139CPLUS: 1419 sc->rl_flags |= RL_FLAG_FASTETHER | RL_FLAG_AUTOPAD; 1420 break; 1421 case RL_HWREV_8100E: 1422 case RL_HWREV_8101E: 1423 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_FASTETHER; 1424 break; 1425 case RL_HWREV_8102E: 1426 case RL_HWREV_8102EL: 1427 case RL_HWREV_8102EL_SPIN1: 1428 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1429 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | 1430 RL_FLAG_AUTOPAD; 1431 break; 1432 case RL_HWREV_8103E: 1433 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1434 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | 1435 RL_FLAG_AUTOPAD | RL_FLAG_MACSLEEP; 1436 break; 1437 case RL_HWREV_8401E: 1438 case RL_HWREV_8105E: 1439 case RL_HWREV_8105E_SPIN1: 1440 case RL_HWREV_8106E: 1441 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1442 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1443 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD; 1444 break; 1445 case RL_HWREV_8402: 1446 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1447 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1448 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | 1449 RL_FLAG_CMDSTOP_WAIT_TXQ; 1450 break; 1451 case RL_HWREV_8168B_SPIN1: 1452 case RL_HWREV_8168B_SPIN2: 1453 sc->rl_flags |= RL_FLAG_WOLRXENB; 1454 /* FALLTHROUGH */ 1455 case RL_HWREV_8168B_SPIN3: 1456 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT; 1457 break; 1458 case RL_HWREV_8168C_SPIN2: 1459 sc->rl_flags |= RL_FLAG_MACSLEEP; 1460 /* FALLTHROUGH */ 1461 case RL_HWREV_8168C: 1462 if (sc->rl_macrev == 0x00200000) 1463 sc->rl_flags |= RL_FLAG_MACSLEEP; 1464 /* FALLTHROUGH */ 1465 case RL_HWREV_8168CP: 1466 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1467 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1468 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK; 1469 break; 1470 case RL_HWREV_8168D: 1471 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1472 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1473 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1474 RL_FLAG_WOL_MANLINK; 1475 break; 1476 case RL_HWREV_8168DP: 1477 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1478 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_AUTOPAD | 1479 RL_FLAG_JUMBOV2 | RL_FLAG_WAIT_TXPOLL | RL_FLAG_WOL_MANLINK; 1480 break; 1481 case RL_HWREV_8168E: 1482 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1483 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1484 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1485 RL_FLAG_WOL_MANLINK; 1486 break; 1487 case RL_HWREV_8168E_VL: 1488 case RL_HWREV_8168F: 1489 sc->rl_flags |= RL_FLAG_EARLYOFF; 1490 /* FALLTHROUGH */ 1491 case RL_HWREV_8411: 1492 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1493 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1494 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1495 RL_FLAG_CMDSTOP_WAIT_TXQ | RL_FLAG_WOL_MANLINK; 1496 break; 1497 case RL_HWREV_8168EP: 1498 case RL_HWREV_8168G: 1499 case RL_HWREV_8411B: 1500 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1501 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1502 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1503 RL_FLAG_CMDSTOP_WAIT_TXQ | RL_FLAG_WOL_MANLINK | 1504 RL_FLAG_8168G_PLUS; 1505 break; 1506 case RL_HWREV_8168GU: 1507 case RL_HWREV_8168H: 1508 if (pci_get_device(dev) == RT_DEVICEID_8101E) { 1509 /* RTL8106E(US), RTL8107E */ 1510 sc->rl_flags |= RL_FLAG_FASTETHER; 1511 } else 1512 sc->rl_flags |= RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK; 1513 1514 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1515 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1516 RL_FLAG_AUTOPAD | RL_FLAG_CMDSTOP_WAIT_TXQ | 1517 RL_FLAG_8168G_PLUS; 1518 break; 1519 case RL_HWREV_8169_8110SB: 1520 case RL_HWREV_8169_8110SBL: 1521 case RL_HWREV_8169_8110SC: 1522 case RL_HWREV_8169_8110SCE: 1523 sc->rl_flags |= RL_FLAG_PHYWAKE; 1524 /* FALLTHROUGH */ 1525 case RL_HWREV_8169: 1526 case RL_HWREV_8169S: 1527 case RL_HWREV_8110S: 1528 sc->rl_flags |= RL_FLAG_MACRESET; 1529 break; 1530 default: 1531 break; 1532 } 1533 1534 if (sc->rl_hwrev->rl_rev == RL_HWREV_8139CPLUS) { 1535 sc->rl_cfg0 = RL_8139_CFG0; 1536 sc->rl_cfg1 = RL_8139_CFG1; 1537 sc->rl_cfg2 = 0; 1538 sc->rl_cfg3 = RL_8139_CFG3; 1539 sc->rl_cfg4 = RL_8139_CFG4; 1540 sc->rl_cfg5 = RL_8139_CFG5; 1541 } else { 1542 sc->rl_cfg0 = RL_CFG0; 1543 sc->rl_cfg1 = RL_CFG1; 1544 sc->rl_cfg2 = RL_CFG2; 1545 sc->rl_cfg3 = RL_CFG3; 1546 sc->rl_cfg4 = RL_CFG4; 1547 sc->rl_cfg5 = RL_CFG5; 1548 } 1549 1550 /* Reset the adapter. */ 1551 RL_LOCK(sc); 1552 re_reset(sc); 1553 RL_UNLOCK(sc); 1554 1555 /* Enable PME. */ 1556 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1557 cfg = CSR_READ_1(sc, sc->rl_cfg1); 1558 cfg |= RL_CFG1_PME; 1559 CSR_WRITE_1(sc, sc->rl_cfg1, cfg); 1560 cfg = CSR_READ_1(sc, sc->rl_cfg5); 1561 cfg &= RL_CFG5_PME_STS; 1562 CSR_WRITE_1(sc, sc->rl_cfg5, cfg); 1563 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1564 1565 if ((sc->rl_flags & RL_FLAG_PAR) != 0) { 1566 /* 1567 * XXX Should have a better way to extract station 1568 * address from EEPROM. 1569 */ 1570 for (i = 0; i < ETHER_ADDR_LEN; i++) 1571 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1572 } else { 1573 sc->rl_eewidth = RL_9356_ADDR_LEN; 1574 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1575 if (re_did != 0x8129) 1576 sc->rl_eewidth = RL_9346_ADDR_LEN; 1577 1578 /* 1579 * Get station address from the EEPROM. 1580 */ 1581 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1582 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1583 as[i] = le16toh(as[i]); 1584 bcopy(as, eaddr, ETHER_ADDR_LEN); 1585 } 1586 1587 if (sc->rl_type == RL_8169) { 1588 /* Set RX length mask and number of descriptors. */ 1589 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1590 sc->rl_txstart = RL_GTXSTART; 1591 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1592 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1593 } else { 1594 /* Set RX length mask and number of descriptors. */ 1595 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1596 sc->rl_txstart = RL_TXSTART; 1597 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1598 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1599 } 1600 1601 error = re_allocmem(dev, sc); 1602 if (error) 1603 goto fail; 1604 re_add_sysctls(sc); 1605 1606 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1607 if (ifp == NULL) { 1608 device_printf(dev, "can not if_alloc()\n"); 1609 error = ENOSPC; 1610 goto fail; 1611 } 1612 1613 /* Take controller out of deep sleep mode. */ 1614 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 1615 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 1616 CSR_WRITE_1(sc, RL_GPIO, 1617 CSR_READ_1(sc, RL_GPIO) | 0x01); 1618 else 1619 CSR_WRITE_1(sc, RL_GPIO, 1620 CSR_READ_1(sc, RL_GPIO) & ~0x01); 1621 } 1622 1623 /* Take PHY out of power down mode. */ 1624 if ((sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) { 1625 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80); 1626 if (hw_rev->rl_rev == RL_HWREV_8401E) 1627 CSR_WRITE_1(sc, 0xD1, CSR_READ_1(sc, 0xD1) & ~0x08); 1628 } 1629 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) { 1630 re_gmii_writereg(dev, 1, 0x1f, 0); 1631 re_gmii_writereg(dev, 1, 0x0e, 0); 1632 } 1633 1634 if_setsoftc(ifp, sc); 1635 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1636 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 1637 if_setioctlfn(ifp, re_ioctl); 1638 if_setstartfn(ifp, re_start); 1639 /* 1640 * RTL8168/8111C generates wrong IP checksummed frame if the 1641 * packet has IP options so disable TX checksum offloading. 1642 */ 1643 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168C || 1644 sc->rl_hwrev->rl_rev == RL_HWREV_8168C_SPIN2 || 1645 sc->rl_hwrev->rl_rev == RL_HWREV_8168CP) { 1646 if_sethwassist(ifp, 0); 1647 if_setcapabilities(ifp, IFCAP_RXCSUM | IFCAP_TSO4); 1648 } else { 1649 if_sethwassist(ifp, CSUM_IP | CSUM_TCP | CSUM_UDP); 1650 if_setcapabilities(ifp, IFCAP_HWCSUM | IFCAP_TSO4); 1651 } 1652 if_sethwassistbits(ifp, CSUM_TSO, 0); 1653 if_setcapenable(ifp, if_getcapabilities(ifp)); 1654 if_setinitfn(ifp, re_init); 1655 if_setsendqlen(ifp, RL_IFQ_MAXLEN); 1656 if_setsendqlen(ifp, RL_IFQ_MAXLEN); 1657 if_setsendqready(ifp); 1658 1659 NET_TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1660 1661 #define RE_PHYAD_INTERNAL 0 1662 1663 /* Do MII setup. */ 1664 phy = RE_PHYAD_INTERNAL; 1665 if (sc->rl_type == RL_8169) 1666 phy = 1; 1667 capmask = BMSR_DEFCAPMASK; 1668 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0) 1669 capmask &= ~BMSR_EXTSTAT; 1670 error = mii_attach(dev, &sc->rl_miibus, ifp, re_ifmedia_upd, 1671 re_ifmedia_sts, capmask, phy, MII_OFFSET_ANY, MIIF_DOPAUSE); 1672 if (error != 0) { 1673 device_printf(dev, "attaching PHYs failed\n"); 1674 goto fail; 1675 } 1676 1677 /* If address was not found, create one based on the hostid and name. */ 1678 if (ETHER_IS_ZERO(eaddr)) { 1679 ether_gen_addr(ifp, (struct ether_addr *)eaddr); 1680 } 1681 1682 /* 1683 * Call MI attach routine. 1684 */ 1685 ether_ifattach(ifp, eaddr); 1686 1687 /* VLAN capability setup */ 1688 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING, 0); 1689 if (if_getcapabilities(ifp) & IFCAP_HWCSUM) 1690 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM, 0); 1691 /* Enable WOL if PM is supported. */ 1692 if (pci_find_cap(sc->rl_dev, PCIY_PMG, ®) == 0) 1693 if_setcapabilitiesbit(ifp, IFCAP_WOL, 0); 1694 if_setcapenable(ifp, if_getcapabilities(ifp)); 1695 if_setcapenablebit(ifp, 0, (IFCAP_WOL_UCAST | IFCAP_WOL_MCAST)); 1696 /* 1697 * Don't enable TSO by default. It is known to generate 1698 * corrupted TCP segments(bad TCP options) under certain 1699 * circumstances. 1700 */ 1701 if_sethwassistbits(ifp, 0, CSUM_TSO); 1702 if_setcapenablebit(ifp, 0, (IFCAP_TSO4 | IFCAP_VLAN_HWTSO)); 1703 #ifdef DEVICE_POLLING 1704 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0); 1705 #endif 1706 /* 1707 * Tell the upper layer(s) we support long frames. 1708 * Must appear after the call to ether_ifattach() because 1709 * ether_ifattach() sets ifi_hdrlen to the default value. 1710 */ 1711 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 1712 1713 #ifdef DEV_NETMAP 1714 re_netmap_attach(sc); 1715 #endif /* DEV_NETMAP */ 1716 1717 #ifdef RE_DIAG 1718 /* 1719 * Perform hardware diagnostic on the original RTL8169. 1720 * Some 32-bit cards were incorrectly wired and would 1721 * malfunction if plugged into a 64-bit slot. 1722 */ 1723 if (hwrev == RL_HWREV_8169) { 1724 error = re_diag(sc); 1725 if (error) { 1726 device_printf(dev, 1727 "attach aborted due to hardware diag failure\n"); 1728 ether_ifdetach(ifp); 1729 goto fail; 1730 } 1731 } 1732 #endif 1733 1734 #ifdef RE_TX_MODERATION 1735 intr_filter = 1; 1736 #endif 1737 /* Hook interrupt last to avoid having to lock softc */ 1738 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 && 1739 intr_filter == 0) { 1740 error = bus_setup_intr(dev, sc->rl_irq[0], 1741 INTR_TYPE_NET | INTR_MPSAFE, NULL, re_intr_msi, sc, 1742 &sc->rl_intrhand[0]); 1743 } else { 1744 error = bus_setup_intr(dev, sc->rl_irq[0], 1745 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1746 &sc->rl_intrhand[0]); 1747 } 1748 if (error) { 1749 device_printf(dev, "couldn't set up irq\n"); 1750 ether_ifdetach(ifp); 1751 goto fail; 1752 } 1753 1754 DEBUGNET_SET(ifp, re); 1755 1756 fail: 1757 if (error) 1758 re_detach(dev); 1759 1760 return (error); 1761 } 1762 1763 /* 1764 * Shutdown hardware and free up resources. This can be called any 1765 * time after the mutex has been initialized. It is called in both 1766 * the error case in attach and the normal detach case so it needs 1767 * to be careful about only freeing resources that have actually been 1768 * allocated. 1769 */ 1770 static int 1771 re_detach(device_t dev) 1772 { 1773 struct rl_softc *sc; 1774 if_t ifp; 1775 int i, rid; 1776 1777 sc = device_get_softc(dev); 1778 ifp = sc->rl_ifp; 1779 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1780 1781 /* These should only be active if attach succeeded */ 1782 if (device_is_attached(dev)) { 1783 #ifdef DEVICE_POLLING 1784 if (if_getcapenable(ifp) & IFCAP_POLLING) 1785 ether_poll_deregister(ifp); 1786 #endif 1787 RL_LOCK(sc); 1788 #if 0 1789 sc->suspended = 1; 1790 #endif 1791 re_stop(sc); 1792 RL_UNLOCK(sc); 1793 callout_drain(&sc->rl_stat_callout); 1794 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1795 /* 1796 * Force off the IFF_UP flag here, in case someone 1797 * still had a BPF descriptor attached to this 1798 * interface. If they do, ether_ifdetach() will cause 1799 * the BPF code to try and clear the promisc mode 1800 * flag, which will bubble down to re_ioctl(), 1801 * which will try to call re_init() again. This will 1802 * turn the NIC back on and restart the MII ticker, 1803 * which will panic the system when the kernel tries 1804 * to invoke the re_tick() function that isn't there 1805 * anymore. 1806 */ 1807 if_setflagbits(ifp, 0, IFF_UP); 1808 ether_ifdetach(ifp); 1809 } 1810 if (sc->rl_miibus) 1811 device_delete_child(dev, sc->rl_miibus); 1812 bus_generic_detach(dev); 1813 1814 /* 1815 * The rest is resource deallocation, so we should already be 1816 * stopped here. 1817 */ 1818 1819 if (sc->rl_intrhand[0] != NULL) { 1820 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]); 1821 sc->rl_intrhand[0] = NULL; 1822 } 1823 if (ifp != NULL) { 1824 #ifdef DEV_NETMAP 1825 netmap_detach(ifp); 1826 #endif /* DEV_NETMAP */ 1827 if_free(ifp); 1828 } 1829 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) 1830 rid = 0; 1831 else 1832 rid = 1; 1833 if (sc->rl_irq[0] != NULL) { 1834 bus_release_resource(dev, SYS_RES_IRQ, rid, sc->rl_irq[0]); 1835 sc->rl_irq[0] = NULL; 1836 } 1837 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0) 1838 pci_release_msi(dev); 1839 if (sc->rl_res_pba) { 1840 rid = PCIR_BAR(4); 1841 bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->rl_res_pba); 1842 } 1843 if (sc->rl_res) 1844 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, 1845 sc->rl_res); 1846 1847 /* Unload and free the RX DMA ring memory and map */ 1848 1849 if (sc->rl_ldata.rl_rx_list_tag) { 1850 if (sc->rl_ldata.rl_rx_list_addr) 1851 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1852 sc->rl_ldata.rl_rx_list_map); 1853 if (sc->rl_ldata.rl_rx_list) 1854 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1855 sc->rl_ldata.rl_rx_list, 1856 sc->rl_ldata.rl_rx_list_map); 1857 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1858 } 1859 1860 /* Unload and free the TX DMA ring memory and map */ 1861 1862 if (sc->rl_ldata.rl_tx_list_tag) { 1863 if (sc->rl_ldata.rl_tx_list_addr) 1864 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1865 sc->rl_ldata.rl_tx_list_map); 1866 if (sc->rl_ldata.rl_tx_list) 1867 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1868 sc->rl_ldata.rl_tx_list, 1869 sc->rl_ldata.rl_tx_list_map); 1870 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1871 } 1872 1873 /* Destroy all the RX and TX buffer maps */ 1874 1875 if (sc->rl_ldata.rl_tx_mtag) { 1876 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1877 if (sc->rl_ldata.rl_tx_desc[i].tx_dmamap) 1878 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1879 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1880 } 1881 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1882 } 1883 if (sc->rl_ldata.rl_rx_mtag) { 1884 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1885 if (sc->rl_ldata.rl_rx_desc[i].rx_dmamap) 1886 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1887 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1888 } 1889 if (sc->rl_ldata.rl_rx_sparemap) 1890 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1891 sc->rl_ldata.rl_rx_sparemap); 1892 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1893 } 1894 if (sc->rl_ldata.rl_jrx_mtag) { 1895 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1896 if (sc->rl_ldata.rl_jrx_desc[i].rx_dmamap) 1897 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag, 1898 sc->rl_ldata.rl_jrx_desc[i].rx_dmamap); 1899 } 1900 if (sc->rl_ldata.rl_jrx_sparemap) 1901 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag, 1902 sc->rl_ldata.rl_jrx_sparemap); 1903 bus_dma_tag_destroy(sc->rl_ldata.rl_jrx_mtag); 1904 } 1905 /* Unload and free the stats buffer and map */ 1906 1907 if (sc->rl_ldata.rl_stag) { 1908 if (sc->rl_ldata.rl_stats_addr) 1909 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1910 sc->rl_ldata.rl_smap); 1911 if (sc->rl_ldata.rl_stats) 1912 bus_dmamem_free(sc->rl_ldata.rl_stag, 1913 sc->rl_ldata.rl_stats, sc->rl_ldata.rl_smap); 1914 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1915 } 1916 1917 if (sc->rl_parent_tag) 1918 bus_dma_tag_destroy(sc->rl_parent_tag); 1919 1920 mtx_destroy(&sc->rl_mtx); 1921 1922 return (0); 1923 } 1924 1925 static __inline void 1926 re_discard_rxbuf(struct rl_softc *sc, int idx) 1927 { 1928 struct rl_desc *desc; 1929 struct rl_rxdesc *rxd; 1930 uint32_t cmdstat; 1931 1932 if (if_getmtu(sc->rl_ifp) > RL_MTU && 1933 (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) 1934 rxd = &sc->rl_ldata.rl_jrx_desc[idx]; 1935 else 1936 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1937 desc = &sc->rl_ldata.rl_rx_list[idx]; 1938 desc->rl_vlanctl = 0; 1939 cmdstat = rxd->rx_size; 1940 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1941 cmdstat |= RL_RDESC_CMD_EOR; 1942 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1943 } 1944 1945 static int 1946 re_newbuf(struct rl_softc *sc, int idx) 1947 { 1948 struct mbuf *m; 1949 struct rl_rxdesc *rxd; 1950 bus_dma_segment_t segs[1]; 1951 bus_dmamap_t map; 1952 struct rl_desc *desc; 1953 uint32_t cmdstat; 1954 int error, nsegs; 1955 1956 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1957 if (m == NULL) 1958 return (ENOBUFS); 1959 1960 m->m_len = m->m_pkthdr.len = MCLBYTES; 1961 #ifdef RE_FIXUP_RX 1962 /* 1963 * This is part of an evil trick to deal with non-x86 platforms. 1964 * The RealTek chip requires RX buffers to be aligned on 64-bit 1965 * boundaries, but that will hose non-x86 machines. To get around 1966 * this, we leave some empty space at the start of each buffer 1967 * and for non-x86 hosts, we copy the buffer back six bytes 1968 * to achieve word alignment. This is slightly more efficient 1969 * than allocating a new buffer, copying the contents, and 1970 * discarding the old buffer. 1971 */ 1972 m_adj(m, RE_ETHER_ALIGN); 1973 #endif 1974 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1975 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1976 if (error != 0) { 1977 m_freem(m); 1978 return (ENOBUFS); 1979 } 1980 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1981 1982 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1983 if (rxd->rx_m != NULL) { 1984 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1985 BUS_DMASYNC_POSTREAD); 1986 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1987 } 1988 1989 rxd->rx_m = m; 1990 map = rxd->rx_dmamap; 1991 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1992 rxd->rx_size = segs[0].ds_len; 1993 sc->rl_ldata.rl_rx_sparemap = map; 1994 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1995 BUS_DMASYNC_PREREAD); 1996 1997 desc = &sc->rl_ldata.rl_rx_list[idx]; 1998 desc->rl_vlanctl = 0; 1999 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 2000 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 2001 cmdstat = segs[0].ds_len; 2002 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 2003 cmdstat |= RL_RDESC_CMD_EOR; 2004 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 2005 2006 return (0); 2007 } 2008 2009 static int 2010 re_jumbo_newbuf(struct rl_softc *sc, int idx) 2011 { 2012 struct mbuf *m; 2013 struct rl_rxdesc *rxd; 2014 bus_dma_segment_t segs[1]; 2015 bus_dmamap_t map; 2016 struct rl_desc *desc; 2017 uint32_t cmdstat; 2018 int error, nsegs; 2019 2020 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 2021 if (m == NULL) 2022 return (ENOBUFS); 2023 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 2024 #ifdef RE_FIXUP_RX 2025 m_adj(m, RE_ETHER_ALIGN); 2026 #endif 2027 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_jrx_mtag, 2028 sc->rl_ldata.rl_jrx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 2029 if (error != 0) { 2030 m_freem(m); 2031 return (ENOBUFS); 2032 } 2033 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 2034 2035 rxd = &sc->rl_ldata.rl_jrx_desc[idx]; 2036 if (rxd->rx_m != NULL) { 2037 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap, 2038 BUS_DMASYNC_POSTREAD); 2039 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap); 2040 } 2041 2042 rxd->rx_m = m; 2043 map = rxd->rx_dmamap; 2044 rxd->rx_dmamap = sc->rl_ldata.rl_jrx_sparemap; 2045 rxd->rx_size = segs[0].ds_len; 2046 sc->rl_ldata.rl_jrx_sparemap = map; 2047 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap, 2048 BUS_DMASYNC_PREREAD); 2049 2050 desc = &sc->rl_ldata.rl_rx_list[idx]; 2051 desc->rl_vlanctl = 0; 2052 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 2053 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 2054 cmdstat = segs[0].ds_len; 2055 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 2056 cmdstat |= RL_RDESC_CMD_EOR; 2057 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 2058 2059 return (0); 2060 } 2061 2062 #ifdef RE_FIXUP_RX 2063 static __inline void 2064 re_fixup_rx(struct mbuf *m) 2065 { 2066 int i; 2067 uint16_t *src, *dst; 2068 2069 src = mtod(m, uint16_t *); 2070 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 2071 2072 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 2073 *dst++ = *src++; 2074 2075 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 2076 } 2077 #endif 2078 2079 static int 2080 re_tx_list_init(struct rl_softc *sc) 2081 { 2082 struct rl_desc *desc; 2083 int i; 2084 2085 RL_LOCK_ASSERT(sc); 2086 2087 bzero(sc->rl_ldata.rl_tx_list, 2088 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 2089 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 2090 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 2091 #ifdef DEV_NETMAP 2092 re_netmap_tx_init(sc); 2093 #endif /* DEV_NETMAP */ 2094 /* Set EOR. */ 2095 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 2096 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 2097 2098 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2099 sc->rl_ldata.rl_tx_list_map, 2100 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2101 2102 sc->rl_ldata.rl_tx_prodidx = 0; 2103 sc->rl_ldata.rl_tx_considx = 0; 2104 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 2105 2106 return (0); 2107 } 2108 2109 static int 2110 re_rx_list_init(struct rl_softc *sc) 2111 { 2112 int error, i; 2113 2114 bzero(sc->rl_ldata.rl_rx_list, 2115 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 2116 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2117 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 2118 if ((error = re_newbuf(sc, i)) != 0) 2119 return (error); 2120 } 2121 #ifdef DEV_NETMAP 2122 re_netmap_rx_init(sc); 2123 #endif /* DEV_NETMAP */ 2124 2125 /* Flush the RX descriptors */ 2126 2127 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2128 sc->rl_ldata.rl_rx_list_map, 2129 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2130 2131 sc->rl_ldata.rl_rx_prodidx = 0; 2132 sc->rl_head = sc->rl_tail = NULL; 2133 sc->rl_int_rx_act = 0; 2134 2135 return (0); 2136 } 2137 2138 static int 2139 re_jrx_list_init(struct rl_softc *sc) 2140 { 2141 int error, i; 2142 2143 bzero(sc->rl_ldata.rl_rx_list, 2144 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 2145 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2146 sc->rl_ldata.rl_jrx_desc[i].rx_m = NULL; 2147 if ((error = re_jumbo_newbuf(sc, i)) != 0) 2148 return (error); 2149 } 2150 2151 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2152 sc->rl_ldata.rl_rx_list_map, 2153 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2154 2155 sc->rl_ldata.rl_rx_prodidx = 0; 2156 sc->rl_head = sc->rl_tail = NULL; 2157 sc->rl_int_rx_act = 0; 2158 2159 return (0); 2160 } 2161 2162 /* 2163 * RX handler for C+ and 8169. For the gigE chips, we support 2164 * the reception of jumbo frames that have been fragmented 2165 * across multiple 2K mbuf cluster buffers. 2166 */ 2167 static int 2168 re_rxeof(struct rl_softc *sc, int *rx_npktsp) 2169 { 2170 struct mbuf *m; 2171 if_t ifp; 2172 int i, rxerr, total_len; 2173 struct rl_desc *cur_rx; 2174 u_int32_t rxstat, rxvlan; 2175 int jumbo, maxpkt = 16, rx_npkts = 0; 2176 2177 RL_LOCK_ASSERT(sc); 2178 2179 ifp = sc->rl_ifp; 2180 #ifdef DEV_NETMAP 2181 if (netmap_rx_irq(ifp, 0, &rx_npkts)) 2182 return 0; 2183 #endif /* DEV_NETMAP */ 2184 if (if_getmtu(ifp) > RL_MTU && (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) 2185 jumbo = 1; 2186 else 2187 jumbo = 0; 2188 2189 /* Invalidate the descriptor memory */ 2190 2191 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2192 sc->rl_ldata.rl_rx_list_map, 2193 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2194 2195 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 2196 i = RL_RX_DESC_NXT(sc, i)) { 2197 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 2198 break; 2199 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 2200 rxstat = le32toh(cur_rx->rl_cmdstat); 2201 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 2202 break; 2203 total_len = rxstat & sc->rl_rxlenmask; 2204 rxvlan = le32toh(cur_rx->rl_vlanctl); 2205 if (jumbo != 0) 2206 m = sc->rl_ldata.rl_jrx_desc[i].rx_m; 2207 else 2208 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 2209 2210 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 2211 (rxstat & (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) != 2212 (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) { 2213 /* 2214 * RTL8168C or later controllers do not 2215 * support multi-fragment packet. 2216 */ 2217 re_discard_rxbuf(sc, i); 2218 continue; 2219 } else if ((rxstat & RL_RDESC_STAT_EOF) == 0) { 2220 if (re_newbuf(sc, i) != 0) { 2221 /* 2222 * If this is part of a multi-fragment packet, 2223 * discard all the pieces. 2224 */ 2225 if (sc->rl_head != NULL) { 2226 m_freem(sc->rl_head); 2227 sc->rl_head = sc->rl_tail = NULL; 2228 } 2229 re_discard_rxbuf(sc, i); 2230 continue; 2231 } 2232 m->m_len = RE_RX_DESC_BUFLEN; 2233 if (sc->rl_head == NULL) 2234 sc->rl_head = sc->rl_tail = m; 2235 else { 2236 m->m_flags &= ~M_PKTHDR; 2237 sc->rl_tail->m_next = m; 2238 sc->rl_tail = m; 2239 } 2240 continue; 2241 } 2242 2243 /* 2244 * NOTE: for the 8139C+, the frame length field 2245 * is always 12 bits in size, but for the gigE chips, 2246 * it is 13 bits (since the max RX frame length is 16K). 2247 * Unfortunately, all 32 bits in the status word 2248 * were already used, so to make room for the extra 2249 * length bit, RealTek took out the 'frame alignment 2250 * error' bit and shifted the other status bits 2251 * over one slot. The OWN, EOR, FS and LS bits are 2252 * still in the same places. We have already extracted 2253 * the frame length and checked the OWN bit, so rather 2254 * than using an alternate bit mapping, we shift the 2255 * status bits one space to the right so we can evaluate 2256 * them using the 8169 status as though it was in the 2257 * same format as that of the 8139C+. 2258 */ 2259 if (sc->rl_type == RL_8169) 2260 rxstat >>= 1; 2261 2262 /* 2263 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 2264 * set, but if CRC is clear, it will still be a valid frame. 2265 */ 2266 if ((rxstat & RL_RDESC_STAT_RXERRSUM) != 0) { 2267 rxerr = 1; 2268 if ((sc->rl_flags & RL_FLAG_JUMBOV2) == 0 && 2269 total_len > 8191 && 2270 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT) 2271 rxerr = 0; 2272 if (rxerr != 0) { 2273 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2274 /* 2275 * If this is part of a multi-fragment packet, 2276 * discard all the pieces. 2277 */ 2278 if (sc->rl_head != NULL) { 2279 m_freem(sc->rl_head); 2280 sc->rl_head = sc->rl_tail = NULL; 2281 } 2282 re_discard_rxbuf(sc, i); 2283 continue; 2284 } 2285 } 2286 2287 /* 2288 * If allocating a replacement mbuf fails, 2289 * reload the current one. 2290 */ 2291 if (jumbo != 0) 2292 rxerr = re_jumbo_newbuf(sc, i); 2293 else 2294 rxerr = re_newbuf(sc, i); 2295 if (rxerr != 0) { 2296 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2297 if (sc->rl_head != NULL) { 2298 m_freem(sc->rl_head); 2299 sc->rl_head = sc->rl_tail = NULL; 2300 } 2301 re_discard_rxbuf(sc, i); 2302 continue; 2303 } 2304 2305 if (sc->rl_head != NULL) { 2306 if (jumbo != 0) 2307 m->m_len = total_len; 2308 else { 2309 m->m_len = total_len % RE_RX_DESC_BUFLEN; 2310 if (m->m_len == 0) 2311 m->m_len = RE_RX_DESC_BUFLEN; 2312 } 2313 /* 2314 * Special case: if there's 4 bytes or less 2315 * in this buffer, the mbuf can be discarded: 2316 * the last 4 bytes is the CRC, which we don't 2317 * care about anyway. 2318 */ 2319 if (m->m_len <= ETHER_CRC_LEN) { 2320 sc->rl_tail->m_len -= 2321 (ETHER_CRC_LEN - m->m_len); 2322 m_freem(m); 2323 } else { 2324 m->m_len -= ETHER_CRC_LEN; 2325 m->m_flags &= ~M_PKTHDR; 2326 sc->rl_tail->m_next = m; 2327 } 2328 m = sc->rl_head; 2329 sc->rl_head = sc->rl_tail = NULL; 2330 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 2331 } else 2332 m->m_pkthdr.len = m->m_len = 2333 (total_len - ETHER_CRC_LEN); 2334 2335 #ifdef RE_FIXUP_RX 2336 re_fixup_rx(m); 2337 #endif 2338 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 2339 m->m_pkthdr.rcvif = ifp; 2340 2341 /* Do RX checksumming if enabled */ 2342 2343 if (if_getcapenable(ifp) & IFCAP_RXCSUM) { 2344 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2345 /* Check IP header checksum */ 2346 if (rxstat & RL_RDESC_STAT_PROTOID) 2347 m->m_pkthdr.csum_flags |= 2348 CSUM_IP_CHECKED; 2349 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 2350 m->m_pkthdr.csum_flags |= 2351 CSUM_IP_VALID; 2352 2353 /* Check TCP/UDP checksum */ 2354 if ((RL_TCPPKT(rxstat) && 2355 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 2356 (RL_UDPPKT(rxstat) && 2357 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 2358 m->m_pkthdr.csum_flags |= 2359 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2360 m->m_pkthdr.csum_data = 0xffff; 2361 } 2362 } else { 2363 /* 2364 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP 2365 */ 2366 if ((rxstat & RL_RDESC_STAT_PROTOID) && 2367 (rxvlan & RL_RDESC_IPV4)) 2368 m->m_pkthdr.csum_flags |= 2369 CSUM_IP_CHECKED; 2370 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) && 2371 (rxvlan & RL_RDESC_IPV4)) 2372 m->m_pkthdr.csum_flags |= 2373 CSUM_IP_VALID; 2374 if (((rxstat & RL_RDESC_STAT_TCP) && 2375 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 2376 ((rxstat & RL_RDESC_STAT_UDP) && 2377 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 2378 m->m_pkthdr.csum_flags |= 2379 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2380 m->m_pkthdr.csum_data = 0xffff; 2381 } 2382 } 2383 } 2384 maxpkt--; 2385 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 2386 m->m_pkthdr.ether_vtag = 2387 bswap16((rxvlan & RL_RDESC_VLANCTL_DATA)); 2388 m->m_flags |= M_VLANTAG; 2389 } 2390 RL_UNLOCK(sc); 2391 if_input(ifp, m); 2392 RL_LOCK(sc); 2393 rx_npkts++; 2394 } 2395 2396 /* Flush the RX DMA ring */ 2397 2398 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2399 sc->rl_ldata.rl_rx_list_map, 2400 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2401 2402 sc->rl_ldata.rl_rx_prodidx = i; 2403 2404 if (rx_npktsp != NULL) 2405 *rx_npktsp = rx_npkts; 2406 if (maxpkt) 2407 return (EAGAIN); 2408 2409 return (0); 2410 } 2411 2412 static void 2413 re_txeof(struct rl_softc *sc) 2414 { 2415 if_t ifp; 2416 struct rl_txdesc *txd; 2417 u_int32_t txstat; 2418 int cons; 2419 2420 cons = sc->rl_ldata.rl_tx_considx; 2421 if (cons == sc->rl_ldata.rl_tx_prodidx) 2422 return; 2423 2424 ifp = sc->rl_ifp; 2425 #ifdef DEV_NETMAP 2426 if (netmap_tx_irq(ifp, 0)) 2427 return; 2428 #endif /* DEV_NETMAP */ 2429 /* Invalidate the TX descriptor list */ 2430 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2431 sc->rl_ldata.rl_tx_list_map, 2432 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2433 2434 for (; cons != sc->rl_ldata.rl_tx_prodidx; 2435 cons = RL_TX_DESC_NXT(sc, cons)) { 2436 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 2437 if (txstat & RL_TDESC_STAT_OWN) 2438 break; 2439 /* 2440 * We only stash mbufs in the last descriptor 2441 * in a fragment chain, which also happens to 2442 * be the only place where the TX status bits 2443 * are valid. 2444 */ 2445 if (txstat & RL_TDESC_CMD_EOF) { 2446 txd = &sc->rl_ldata.rl_tx_desc[cons]; 2447 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2448 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2449 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2450 txd->tx_dmamap); 2451 KASSERT(txd->tx_m != NULL, 2452 ("%s: freeing NULL mbufs!", __func__)); 2453 m_freem(txd->tx_m); 2454 txd->tx_m = NULL; 2455 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 2456 RL_TDESC_STAT_COLCNT)) 2457 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 2458 if (txstat & RL_TDESC_STAT_TXERRSUM) 2459 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2460 else 2461 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 2462 } 2463 sc->rl_ldata.rl_tx_free++; 2464 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2465 } 2466 sc->rl_ldata.rl_tx_considx = cons; 2467 2468 /* No changes made to the TX ring, so no flush needed */ 2469 2470 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 2471 #ifdef RE_TX_MODERATION 2472 /* 2473 * If not all descriptors have been reaped yet, reload 2474 * the timer so that we will eventually get another 2475 * interrupt that will cause us to re-enter this routine. 2476 * This is done in case the transmitter has gone idle. 2477 */ 2478 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2479 #endif 2480 } else 2481 sc->rl_watchdog_timer = 0; 2482 } 2483 2484 static void 2485 re_tick(void *xsc) 2486 { 2487 struct rl_softc *sc; 2488 struct mii_data *mii; 2489 2490 sc = xsc; 2491 2492 RL_LOCK_ASSERT(sc); 2493 2494 mii = device_get_softc(sc->rl_miibus); 2495 mii_tick(mii); 2496 if ((sc->rl_flags & RL_FLAG_LINK) == 0) 2497 re_miibus_statchg(sc->rl_dev); 2498 /* 2499 * Reclaim transmitted frames here. Technically it is not 2500 * necessary to do here but it ensures periodic reclamation 2501 * regardless of Tx completion interrupt which seems to be 2502 * lost on PCIe based controllers under certain situations. 2503 */ 2504 re_txeof(sc); 2505 re_watchdog(sc); 2506 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2507 } 2508 2509 #ifdef DEVICE_POLLING 2510 static int 2511 re_poll(if_t ifp, enum poll_cmd cmd, int count) 2512 { 2513 struct rl_softc *sc = if_getsoftc(ifp); 2514 int rx_npkts = 0; 2515 2516 RL_LOCK(sc); 2517 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 2518 rx_npkts = re_poll_locked(ifp, cmd, count); 2519 RL_UNLOCK(sc); 2520 return (rx_npkts); 2521 } 2522 2523 static int 2524 re_poll_locked(if_t ifp, enum poll_cmd cmd, int count) 2525 { 2526 struct rl_softc *sc = if_getsoftc(ifp); 2527 int rx_npkts; 2528 2529 RL_LOCK_ASSERT(sc); 2530 2531 sc->rxcycles = count; 2532 re_rxeof(sc, &rx_npkts); 2533 re_txeof(sc); 2534 2535 if (!if_sendq_empty(ifp)) 2536 re_start_locked(ifp); 2537 2538 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2539 u_int16_t status; 2540 2541 status = CSR_READ_2(sc, RL_ISR); 2542 if (status == 0xffff) 2543 return (rx_npkts); 2544 if (status) 2545 CSR_WRITE_2(sc, RL_ISR, status); 2546 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2547 (sc->rl_flags & RL_FLAG_PCIE)) 2548 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2549 2550 /* 2551 * XXX check behaviour on receiver stalls. 2552 */ 2553 2554 if (status & RL_ISR_SYSTEM_ERR) { 2555 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2556 re_init_locked(sc); 2557 } 2558 } 2559 return (rx_npkts); 2560 } 2561 #endif /* DEVICE_POLLING */ 2562 2563 static int 2564 re_intr(void *arg) 2565 { 2566 struct rl_softc *sc; 2567 uint16_t status; 2568 2569 sc = arg; 2570 2571 status = CSR_READ_2(sc, RL_ISR); 2572 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2573 return (FILTER_STRAY); 2574 CSR_WRITE_2(sc, RL_IMR, 0); 2575 2576 taskqueue_enqueue(taskqueue_fast, &sc->rl_inttask); 2577 2578 return (FILTER_HANDLED); 2579 } 2580 2581 static void 2582 re_int_task(void *arg, int npending) 2583 { 2584 struct rl_softc *sc; 2585 if_t ifp; 2586 u_int16_t status; 2587 int rval = 0; 2588 2589 sc = arg; 2590 ifp = sc->rl_ifp; 2591 2592 RL_LOCK(sc); 2593 2594 status = CSR_READ_2(sc, RL_ISR); 2595 CSR_WRITE_2(sc, RL_ISR, status); 2596 2597 if (sc->suspended || 2598 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 2599 RL_UNLOCK(sc); 2600 return; 2601 } 2602 2603 #ifdef DEVICE_POLLING 2604 if (if_getcapenable(ifp) & IFCAP_POLLING) { 2605 RL_UNLOCK(sc); 2606 return; 2607 } 2608 #endif 2609 2610 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2611 rval = re_rxeof(sc, NULL); 2612 2613 /* 2614 * Some chips will ignore a second TX request issued 2615 * while an existing transmission is in progress. If 2616 * the transmitter goes idle but there are still 2617 * packets waiting to be sent, we need to restart the 2618 * channel here to flush them out. This only seems to 2619 * be required with the PCIe devices. 2620 */ 2621 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2622 (sc->rl_flags & RL_FLAG_PCIE)) 2623 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2624 if (status & ( 2625 #ifdef RE_TX_MODERATION 2626 RL_ISR_TIMEOUT_EXPIRED| 2627 #else 2628 RL_ISR_TX_OK| 2629 #endif 2630 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2631 re_txeof(sc); 2632 2633 if (status & RL_ISR_SYSTEM_ERR) { 2634 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2635 re_init_locked(sc); 2636 } 2637 2638 if (!if_sendq_empty(ifp)) 2639 re_start_locked(ifp); 2640 2641 RL_UNLOCK(sc); 2642 2643 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2644 taskqueue_enqueue(taskqueue_fast, &sc->rl_inttask); 2645 return; 2646 } 2647 2648 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2649 } 2650 2651 static void 2652 re_intr_msi(void *xsc) 2653 { 2654 struct rl_softc *sc; 2655 if_t ifp; 2656 uint16_t intrs, status; 2657 2658 sc = xsc; 2659 RL_LOCK(sc); 2660 2661 ifp = sc->rl_ifp; 2662 #ifdef DEVICE_POLLING 2663 if (if_getcapenable(ifp) & IFCAP_POLLING) { 2664 RL_UNLOCK(sc); 2665 return; 2666 } 2667 #endif 2668 /* Disable interrupts. */ 2669 CSR_WRITE_2(sc, RL_IMR, 0); 2670 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 2671 RL_UNLOCK(sc); 2672 return; 2673 } 2674 2675 intrs = RL_INTRS_CPLUS; 2676 status = CSR_READ_2(sc, RL_ISR); 2677 CSR_WRITE_2(sc, RL_ISR, status); 2678 if (sc->rl_int_rx_act > 0) { 2679 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW | 2680 RL_ISR_RX_OVERRUN); 2681 status &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW | 2682 RL_ISR_RX_OVERRUN); 2683 } 2684 2685 if (status & (RL_ISR_TIMEOUT_EXPIRED | RL_ISR_RX_OK | RL_ISR_RX_ERR | 2686 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) { 2687 re_rxeof(sc, NULL); 2688 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2689 if (sc->rl_int_rx_mod != 0 && 2690 (status & (RL_ISR_RX_OK | RL_ISR_RX_ERR | 2691 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) != 0) { 2692 /* Rearm one-shot timer. */ 2693 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2694 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | 2695 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN); 2696 sc->rl_int_rx_act = 1; 2697 } else { 2698 intrs |= RL_ISR_RX_OK | RL_ISR_RX_ERR | 2699 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN; 2700 sc->rl_int_rx_act = 0; 2701 } 2702 } 2703 } 2704 2705 /* 2706 * Some chips will ignore a second TX request issued 2707 * while an existing transmission is in progress. If 2708 * the transmitter goes idle but there are still 2709 * packets waiting to be sent, we need to restart the 2710 * channel here to flush them out. This only seems to 2711 * be required with the PCIe devices. 2712 */ 2713 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2714 (sc->rl_flags & RL_FLAG_PCIE)) 2715 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2716 if (status & (RL_ISR_TX_OK | RL_ISR_TX_ERR | RL_ISR_TX_DESC_UNAVAIL)) 2717 re_txeof(sc); 2718 2719 if (status & RL_ISR_SYSTEM_ERR) { 2720 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2721 re_init_locked(sc); 2722 } 2723 2724 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2725 if (!if_sendq_empty(ifp)) 2726 re_start_locked(ifp); 2727 CSR_WRITE_2(sc, RL_IMR, intrs); 2728 } 2729 RL_UNLOCK(sc); 2730 } 2731 2732 static int 2733 re_encap(struct rl_softc *sc, struct mbuf **m_head) 2734 { 2735 struct rl_txdesc *txd, *txd_last; 2736 bus_dma_segment_t segs[RL_NTXSEGS]; 2737 bus_dmamap_t map; 2738 struct mbuf *m_new; 2739 struct rl_desc *desc; 2740 int nsegs, prod; 2741 int i, error, ei, si; 2742 int padlen; 2743 uint32_t cmdstat, csum_flags, vlanctl; 2744 2745 RL_LOCK_ASSERT(sc); 2746 M_ASSERTPKTHDR((*m_head)); 2747 2748 /* 2749 * With some of the RealTek chips, using the checksum offload 2750 * support in conjunction with the autopadding feature results 2751 * in the transmission of corrupt frames. For example, if we 2752 * need to send a really small IP fragment that's less than 60 2753 * bytes in size, and IP header checksumming is enabled, the 2754 * resulting ethernet frame that appears on the wire will 2755 * have garbled payload. To work around this, if TX IP checksum 2756 * offload is enabled, we always manually pad short frames out 2757 * to the minimum ethernet frame size. 2758 */ 2759 if ((sc->rl_flags & RL_FLAG_AUTOPAD) == 0 && 2760 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN && 2761 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) { 2762 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2763 if (M_WRITABLE(*m_head) == 0) { 2764 /* Get a writable copy. */ 2765 m_new = m_dup(*m_head, M_NOWAIT); 2766 m_freem(*m_head); 2767 if (m_new == NULL) { 2768 *m_head = NULL; 2769 return (ENOBUFS); 2770 } 2771 *m_head = m_new; 2772 } 2773 if ((*m_head)->m_next != NULL || 2774 M_TRAILINGSPACE(*m_head) < padlen) { 2775 m_new = m_defrag(*m_head, M_NOWAIT); 2776 if (m_new == NULL) { 2777 m_freem(*m_head); 2778 *m_head = NULL; 2779 return (ENOBUFS); 2780 } 2781 } else 2782 m_new = *m_head; 2783 2784 /* 2785 * Manually pad short frames, and zero the pad space 2786 * to avoid leaking data. 2787 */ 2788 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2789 m_new->m_pkthdr.len += padlen; 2790 m_new->m_len = m_new->m_pkthdr.len; 2791 *m_head = m_new; 2792 } 2793 2794 prod = sc->rl_ldata.rl_tx_prodidx; 2795 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2796 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2797 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2798 if (error == EFBIG) { 2799 m_new = m_collapse(*m_head, M_NOWAIT, RL_NTXSEGS); 2800 if (m_new == NULL) { 2801 m_freem(*m_head); 2802 *m_head = NULL; 2803 return (ENOBUFS); 2804 } 2805 *m_head = m_new; 2806 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2807 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2808 if (error != 0) { 2809 m_freem(*m_head); 2810 *m_head = NULL; 2811 return (error); 2812 } 2813 } else if (error != 0) 2814 return (error); 2815 if (nsegs == 0) { 2816 m_freem(*m_head); 2817 *m_head = NULL; 2818 return (EIO); 2819 } 2820 2821 /* Check for number of available descriptors. */ 2822 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2823 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2824 return (ENOBUFS); 2825 } 2826 2827 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2828 BUS_DMASYNC_PREWRITE); 2829 2830 /* 2831 * Set up checksum offload. Note: checksum offload bits must 2832 * appear in all descriptors of a multi-descriptor transmit 2833 * attempt. This is according to testing done with an 8169 2834 * chip. This is a requirement. 2835 */ 2836 vlanctl = 0; 2837 csum_flags = 0; 2838 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2839 if ((sc->rl_flags & RL_FLAG_DESCV2) != 0) { 2840 csum_flags |= RL_TDESC_CMD_LGSEND; 2841 vlanctl |= ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2842 RL_TDESC_CMD_MSSVALV2_SHIFT); 2843 } else { 2844 csum_flags |= RL_TDESC_CMD_LGSEND | 2845 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2846 RL_TDESC_CMD_MSSVAL_SHIFT); 2847 } 2848 } else { 2849 /* 2850 * Unconditionally enable IP checksum if TCP or UDP 2851 * checksum is required. Otherwise, TCP/UDP checksum 2852 * doesn't make effects. 2853 */ 2854 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) { 2855 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2856 csum_flags |= RL_TDESC_CMD_IPCSUM; 2857 if (((*m_head)->m_pkthdr.csum_flags & 2858 CSUM_TCP) != 0) 2859 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2860 if (((*m_head)->m_pkthdr.csum_flags & 2861 CSUM_UDP) != 0) 2862 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2863 } else { 2864 vlanctl |= RL_TDESC_CMD_IPCSUMV2; 2865 if (((*m_head)->m_pkthdr.csum_flags & 2866 CSUM_TCP) != 0) 2867 vlanctl |= RL_TDESC_CMD_TCPCSUMV2; 2868 if (((*m_head)->m_pkthdr.csum_flags & 2869 CSUM_UDP) != 0) 2870 vlanctl |= RL_TDESC_CMD_UDPCSUMV2; 2871 } 2872 } 2873 } 2874 2875 /* 2876 * Set up hardware VLAN tagging. Note: vlan tag info must 2877 * appear in all descriptors of a multi-descriptor 2878 * transmission attempt. 2879 */ 2880 if ((*m_head)->m_flags & M_VLANTAG) 2881 vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) | 2882 RL_TDESC_VLANCTL_TAG; 2883 2884 si = prod; 2885 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2886 desc = &sc->rl_ldata.rl_tx_list[prod]; 2887 desc->rl_vlanctl = htole32(vlanctl); 2888 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2889 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2890 cmdstat = segs[i].ds_len; 2891 if (i != 0) 2892 cmdstat |= RL_TDESC_CMD_OWN; 2893 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2894 cmdstat |= RL_TDESC_CMD_EOR; 2895 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2896 sc->rl_ldata.rl_tx_free--; 2897 } 2898 /* Update producer index. */ 2899 sc->rl_ldata.rl_tx_prodidx = prod; 2900 2901 /* Set EOF on the last descriptor. */ 2902 ei = RL_TX_DESC_PRV(sc, prod); 2903 desc = &sc->rl_ldata.rl_tx_list[ei]; 2904 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2905 2906 desc = &sc->rl_ldata.rl_tx_list[si]; 2907 /* Set SOF and transfer ownership of packet to the chip. */ 2908 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2909 2910 /* 2911 * Insure that the map for this transmission 2912 * is placed at the array index of the last descriptor 2913 * in this chain. (Swap last and first dmamaps.) 2914 */ 2915 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2916 map = txd->tx_dmamap; 2917 txd->tx_dmamap = txd_last->tx_dmamap; 2918 txd_last->tx_dmamap = map; 2919 txd_last->tx_m = *m_head; 2920 2921 return (0); 2922 } 2923 2924 static void 2925 re_start(if_t ifp) 2926 { 2927 struct rl_softc *sc; 2928 2929 sc = if_getsoftc(ifp); 2930 RL_LOCK(sc); 2931 re_start_locked(ifp); 2932 RL_UNLOCK(sc); 2933 } 2934 2935 /* 2936 * Main transmit routine for C+ and gigE NICs. 2937 */ 2938 static void 2939 re_start_locked(if_t ifp) 2940 { 2941 struct rl_softc *sc; 2942 struct mbuf *m_head; 2943 int queued; 2944 2945 sc = if_getsoftc(ifp); 2946 2947 #ifdef DEV_NETMAP 2948 /* XXX is this necessary ? */ 2949 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 2950 struct netmap_kring *kring = NA(ifp)->tx_rings[0]; 2951 if (sc->rl_ldata.rl_tx_prodidx != kring->nr_hwcur) { 2952 /* kick the tx unit */ 2953 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2954 #ifdef RE_TX_MODERATION 2955 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2956 #endif 2957 sc->rl_watchdog_timer = 5; 2958 } 2959 return; 2960 } 2961 #endif /* DEV_NETMAP */ 2962 2963 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2964 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) 2965 return; 2966 2967 for (queued = 0; !if_sendq_empty(ifp) && 2968 sc->rl_ldata.rl_tx_free > 1;) { 2969 m_head = if_dequeue(ifp); 2970 if (m_head == NULL) 2971 break; 2972 2973 if (re_encap(sc, &m_head) != 0) { 2974 if (m_head == NULL) 2975 break; 2976 if_sendq_prepend(ifp, m_head); 2977 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 2978 break; 2979 } 2980 2981 /* 2982 * If there's a BPF listener, bounce a copy of this frame 2983 * to him. 2984 */ 2985 ETHER_BPF_MTAP(ifp, m_head); 2986 2987 queued++; 2988 } 2989 2990 if (queued == 0) { 2991 #ifdef RE_TX_MODERATION 2992 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2993 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2994 #endif 2995 return; 2996 } 2997 2998 re_start_tx(sc); 2999 } 3000 3001 static void 3002 re_start_tx(struct rl_softc *sc) 3003 { 3004 3005 /* Flush the TX descriptors */ 3006 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 3007 sc->rl_ldata.rl_tx_list_map, 3008 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 3009 3010 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 3011 3012 #ifdef RE_TX_MODERATION 3013 /* 3014 * Use the countdown timer for interrupt moderation. 3015 * 'TX done' interrupts are disabled. Instead, we reset the 3016 * countdown timer, which will begin counting until it hits 3017 * the value in the TIMERINT register, and then trigger an 3018 * interrupt. Each time we write to the TIMERCNT register, 3019 * the timer count is reset to 0. 3020 */ 3021 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 3022 #endif 3023 3024 /* 3025 * Set a timeout in case the chip goes out to lunch. 3026 */ 3027 sc->rl_watchdog_timer = 5; 3028 } 3029 3030 static void 3031 re_set_jumbo(struct rl_softc *sc, int jumbo) 3032 { 3033 3034 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168E_VL) { 3035 pci_set_max_read_req(sc->rl_dev, 4096); 3036 return; 3037 } 3038 3039 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 3040 if (jumbo != 0) { 3041 CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) | 3042 RL_CFG3_JUMBO_EN0); 3043 switch (sc->rl_hwrev->rl_rev) { 3044 case RL_HWREV_8168DP: 3045 break; 3046 case RL_HWREV_8168E: 3047 CSR_WRITE_1(sc, sc->rl_cfg4, 3048 CSR_READ_1(sc, sc->rl_cfg4) | 0x01); 3049 break; 3050 default: 3051 CSR_WRITE_1(sc, sc->rl_cfg4, 3052 CSR_READ_1(sc, sc->rl_cfg4) | RL_CFG4_JUMBO_EN1); 3053 } 3054 } else { 3055 CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) & 3056 ~RL_CFG3_JUMBO_EN0); 3057 switch (sc->rl_hwrev->rl_rev) { 3058 case RL_HWREV_8168DP: 3059 break; 3060 case RL_HWREV_8168E: 3061 CSR_WRITE_1(sc, sc->rl_cfg4, 3062 CSR_READ_1(sc, sc->rl_cfg4) & ~0x01); 3063 break; 3064 default: 3065 CSR_WRITE_1(sc, sc->rl_cfg4, 3066 CSR_READ_1(sc, sc->rl_cfg4) & ~RL_CFG4_JUMBO_EN1); 3067 } 3068 } 3069 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3070 3071 switch (sc->rl_hwrev->rl_rev) { 3072 case RL_HWREV_8168DP: 3073 pci_set_max_read_req(sc->rl_dev, 4096); 3074 break; 3075 default: 3076 if (jumbo != 0) 3077 pci_set_max_read_req(sc->rl_dev, 512); 3078 else 3079 pci_set_max_read_req(sc->rl_dev, 4096); 3080 } 3081 } 3082 3083 static void 3084 re_init(void *xsc) 3085 { 3086 struct rl_softc *sc = xsc; 3087 3088 RL_LOCK(sc); 3089 re_init_locked(sc); 3090 RL_UNLOCK(sc); 3091 } 3092 3093 static void 3094 re_init_locked(struct rl_softc *sc) 3095 { 3096 if_t ifp = sc->rl_ifp; 3097 struct mii_data *mii; 3098 uint32_t reg; 3099 uint16_t cfg; 3100 uint32_t idr[2]; 3101 3102 RL_LOCK_ASSERT(sc); 3103 3104 mii = device_get_softc(sc->rl_miibus); 3105 3106 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 3107 return; 3108 3109 /* 3110 * Cancel pending I/O and free all RX/TX buffers. 3111 */ 3112 re_stop(sc); 3113 3114 /* Put controller into known state. */ 3115 re_reset(sc); 3116 3117 /* 3118 * For C+ mode, initialize the RX descriptors and mbufs. 3119 */ 3120 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3121 if (if_getmtu(ifp) > RL_MTU) { 3122 if (re_jrx_list_init(sc) != 0) { 3123 device_printf(sc->rl_dev, 3124 "no memory for jumbo RX buffers\n"); 3125 re_stop(sc); 3126 return; 3127 } 3128 /* Disable checksum offloading for jumbo frames. */ 3129 if_setcapenablebit(ifp, 0, (IFCAP_HWCSUM | IFCAP_TSO4)); 3130 if_sethwassistbits(ifp, 0, (RE_CSUM_FEATURES | CSUM_TSO)); 3131 } else { 3132 if (re_rx_list_init(sc) != 0) { 3133 device_printf(sc->rl_dev, 3134 "no memory for RX buffers\n"); 3135 re_stop(sc); 3136 return; 3137 } 3138 } 3139 re_set_jumbo(sc, if_getmtu(ifp) > RL_MTU); 3140 } else { 3141 if (re_rx_list_init(sc) != 0) { 3142 device_printf(sc->rl_dev, "no memory for RX buffers\n"); 3143 re_stop(sc); 3144 return; 3145 } 3146 if ((sc->rl_flags & RL_FLAG_PCIE) != 0 && 3147 pci_get_device(sc->rl_dev) != RT_DEVICEID_8101E) { 3148 if (if_getmtu(ifp) > RL_MTU) 3149 pci_set_max_read_req(sc->rl_dev, 512); 3150 else 3151 pci_set_max_read_req(sc->rl_dev, 4096); 3152 } 3153 } 3154 re_tx_list_init(sc); 3155 3156 /* 3157 * Enable C+ RX and TX mode, as well as VLAN stripping and 3158 * RX checksum offload. We must configure the C+ register 3159 * before all others. 3160 */ 3161 cfg = RL_CPLUSCMD_PCI_MRW; 3162 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 3163 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 3164 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 3165 cfg |= RL_CPLUSCMD_VLANSTRIP; 3166 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) { 3167 cfg |= RL_CPLUSCMD_MACSTAT_DIS; 3168 /* XXX magic. */ 3169 cfg |= 0x0001; 3170 } else 3171 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB; 3172 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg); 3173 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SC || 3174 sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) { 3175 reg = 0x000fff00; 3176 if ((CSR_READ_1(sc, sc->rl_cfg2) & RL_CFG2_PCI66MHZ) != 0) 3177 reg |= 0x000000ff; 3178 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) 3179 reg |= 0x00f00000; 3180 CSR_WRITE_4(sc, 0x7c, reg); 3181 /* Disable interrupt mitigation. */ 3182 CSR_WRITE_2(sc, 0xe2, 0); 3183 } 3184 /* 3185 * Disable TSO if interface MTU size is greater than MSS 3186 * allowed in controller. 3187 */ 3188 if (if_getmtu(ifp) > RL_TSO_MTU && (if_getcapenable(ifp) & IFCAP_TSO4) != 0) { 3189 if_setcapenablebit(ifp, 0, IFCAP_TSO4); 3190 if_sethwassistbits(ifp, 0, CSUM_TSO); 3191 } 3192 3193 /* 3194 * Init our MAC address. Even though the chipset 3195 * documentation doesn't mention it, we need to enter "Config 3196 * register write enable" mode to modify the ID registers. 3197 */ 3198 /* Copy MAC address on stack to align. */ 3199 bzero(idr, sizeof(idr)); 3200 bcopy(if_getlladdr(ifp), idr, ETHER_ADDR_LEN); 3201 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 3202 CSR_WRITE_4(sc, RL_IDR0, htole32(idr[0])); 3203 CSR_WRITE_4(sc, RL_IDR4, htole32(idr[1])); 3204 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3205 3206 /* 3207 * Load the addresses of the RX and TX lists into the chip. 3208 */ 3209 3210 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 3211 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 3212 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 3213 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 3214 3215 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 3216 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 3217 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 3218 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 3219 3220 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0) { 3221 /* Disable RXDV gate. */ 3222 CSR_WRITE_4(sc, RL_MISC, CSR_READ_4(sc, RL_MISC) & 3223 ~0x00080000); 3224 } 3225 3226 /* 3227 * Enable transmit and receive for pre-RTL8168G controllers. 3228 * RX/TX MACs should be enabled before RX/TX configuration. 3229 */ 3230 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) == 0) 3231 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB | RL_CMD_RX_ENB); 3232 3233 /* 3234 * Set the initial TX configuration. 3235 */ 3236 if (sc->rl_testmode) { 3237 if (sc->rl_type == RL_8169) 3238 CSR_WRITE_4(sc, RL_TXCFG, 3239 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 3240 else 3241 CSR_WRITE_4(sc, RL_TXCFG, 3242 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 3243 } else 3244 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 3245 3246 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 3247 3248 /* 3249 * Set the initial RX configuration. 3250 */ 3251 re_set_rxmode(sc); 3252 3253 /* Configure interrupt moderation. */ 3254 if (sc->rl_type == RL_8169) { 3255 /* Magic from vendor. */ 3256 CSR_WRITE_2(sc, RL_INTRMOD, 0x5100); 3257 } 3258 3259 /* 3260 * Enable transmit and receive for RTL8168G and later controllers. 3261 * RX/TX MACs should be enabled after RX/TX configuration. 3262 */ 3263 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0) 3264 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB | RL_CMD_RX_ENB); 3265 3266 #ifdef DEVICE_POLLING 3267 /* 3268 * Disable interrupts if we are polling. 3269 */ 3270 if (if_getcapenable(ifp) & IFCAP_POLLING) 3271 CSR_WRITE_2(sc, RL_IMR, 0); 3272 else /* otherwise ... */ 3273 #endif 3274 3275 /* 3276 * Enable interrupts. 3277 */ 3278 if (sc->rl_testmode) 3279 CSR_WRITE_2(sc, RL_IMR, 0); 3280 else 3281 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 3282 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 3283 3284 /* Set initial TX threshold */ 3285 sc->rl_txthresh = RL_TX_THRESH_INIT; 3286 3287 /* Start RX/TX process. */ 3288 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 3289 3290 /* 3291 * Initialize the timer interrupt register so that 3292 * a timer interrupt will be generated once the timer 3293 * reaches a certain number of ticks. The timer is 3294 * reloaded on each transmit. 3295 */ 3296 #ifdef RE_TX_MODERATION 3297 /* 3298 * Use timer interrupt register to moderate TX interrupt 3299 * moderation, which dramatically improves TX frame rate. 3300 */ 3301 if (sc->rl_type == RL_8169) 3302 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 3303 else 3304 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 3305 #else 3306 /* 3307 * Use timer interrupt register to moderate RX interrupt 3308 * moderation. 3309 */ 3310 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 && 3311 intr_filter == 0) { 3312 if (sc->rl_type == RL_8169) 3313 CSR_WRITE_4(sc, RL_TIMERINT_8169, 3314 RL_USECS(sc->rl_int_rx_mod)); 3315 } else { 3316 if (sc->rl_type == RL_8169) 3317 CSR_WRITE_4(sc, RL_TIMERINT_8169, RL_USECS(0)); 3318 } 3319 #endif 3320 3321 /* 3322 * For 8169 gigE NICs, set the max allowed RX packet 3323 * size so we can receive jumbo frames. 3324 */ 3325 if (sc->rl_type == RL_8169) { 3326 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3327 /* 3328 * For controllers that use new jumbo frame scheme, 3329 * set maximum size of jumbo frame depending on 3330 * controller revisions. 3331 */ 3332 if (if_getmtu(ifp) > RL_MTU) 3333 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 3334 sc->rl_hwrev->rl_max_mtu + 3335 ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN + 3336 ETHER_CRC_LEN); 3337 else 3338 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 3339 RE_RX_DESC_BUFLEN); 3340 } else if ((sc->rl_flags & RL_FLAG_PCIE) != 0 && 3341 sc->rl_hwrev->rl_max_mtu == RL_MTU) { 3342 /* RTL810x has no jumbo frame support. */ 3343 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, RE_RX_DESC_BUFLEN); 3344 } else 3345 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 3346 } 3347 3348 if (sc->rl_testmode) 3349 return; 3350 3351 CSR_WRITE_1(sc, sc->rl_cfg1, CSR_READ_1(sc, sc->rl_cfg1) | 3352 RL_CFG1_DRVLOAD); 3353 3354 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 3355 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 3356 3357 sc->rl_flags &= ~RL_FLAG_LINK; 3358 mii_mediachg(mii); 3359 3360 sc->rl_watchdog_timer = 0; 3361 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 3362 3363 #ifdef DEV_NETMAP 3364 netmap_enable_all_rings(ifp); 3365 #endif /* DEV_NETMAP */ 3366 } 3367 3368 /* 3369 * Set media options. 3370 */ 3371 static int 3372 re_ifmedia_upd(if_t ifp) 3373 { 3374 struct rl_softc *sc; 3375 struct mii_data *mii; 3376 int error; 3377 3378 sc = if_getsoftc(ifp); 3379 mii = device_get_softc(sc->rl_miibus); 3380 RL_LOCK(sc); 3381 error = mii_mediachg(mii); 3382 RL_UNLOCK(sc); 3383 3384 return (error); 3385 } 3386 3387 /* 3388 * Report current media status. 3389 */ 3390 static void 3391 re_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 3392 { 3393 struct rl_softc *sc; 3394 struct mii_data *mii; 3395 3396 sc = if_getsoftc(ifp); 3397 mii = device_get_softc(sc->rl_miibus); 3398 3399 RL_LOCK(sc); 3400 mii_pollstat(mii); 3401 ifmr->ifm_active = mii->mii_media_active; 3402 ifmr->ifm_status = mii->mii_media_status; 3403 RL_UNLOCK(sc); 3404 } 3405 3406 static int 3407 re_ioctl(if_t ifp, u_long command, caddr_t data) 3408 { 3409 struct rl_softc *sc = if_getsoftc(ifp); 3410 struct ifreq *ifr = (struct ifreq *) data; 3411 struct mii_data *mii; 3412 int error = 0; 3413 3414 switch (command) { 3415 case SIOCSIFMTU: 3416 if (ifr->ifr_mtu < ETHERMIN || 3417 ifr->ifr_mtu > sc->rl_hwrev->rl_max_mtu || 3418 ((sc->rl_flags & RL_FLAG_FASTETHER) != 0 && 3419 ifr->ifr_mtu > RL_MTU)) { 3420 error = EINVAL; 3421 break; 3422 } 3423 RL_LOCK(sc); 3424 if (if_getmtu(ifp) != ifr->ifr_mtu) { 3425 if_setmtu(ifp, ifr->ifr_mtu); 3426 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 3427 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 3428 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3429 re_init_locked(sc); 3430 } 3431 if (if_getmtu(ifp) > RL_TSO_MTU && 3432 (if_getcapenable(ifp) & IFCAP_TSO4) != 0) { 3433 if_setcapenablebit(ifp, 0, 3434 IFCAP_TSO4 | IFCAP_VLAN_HWTSO); 3435 if_sethwassistbits(ifp, 0, CSUM_TSO); 3436 } 3437 VLAN_CAPABILITIES(ifp); 3438 } 3439 RL_UNLOCK(sc); 3440 break; 3441 case SIOCSIFFLAGS: 3442 RL_LOCK(sc); 3443 if ((if_getflags(ifp) & IFF_UP) != 0) { 3444 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 3445 if (((if_getflags(ifp) ^ sc->rl_if_flags) 3446 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 3447 re_set_rxmode(sc); 3448 } else 3449 re_init_locked(sc); 3450 } else { 3451 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 3452 re_stop(sc); 3453 } 3454 sc->rl_if_flags = if_getflags(ifp); 3455 RL_UNLOCK(sc); 3456 break; 3457 case SIOCADDMULTI: 3458 case SIOCDELMULTI: 3459 RL_LOCK(sc); 3460 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 3461 re_set_rxmode(sc); 3462 RL_UNLOCK(sc); 3463 break; 3464 case SIOCGIFMEDIA: 3465 case SIOCSIFMEDIA: 3466 mii = device_get_softc(sc->rl_miibus); 3467 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3468 break; 3469 case SIOCSIFCAP: 3470 { 3471 int mask, reinit; 3472 3473 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 3474 reinit = 0; 3475 #ifdef DEVICE_POLLING 3476 if (mask & IFCAP_POLLING) { 3477 if (ifr->ifr_reqcap & IFCAP_POLLING) { 3478 error = ether_poll_register(re_poll, ifp); 3479 if (error) 3480 return (error); 3481 RL_LOCK(sc); 3482 /* Disable interrupts */ 3483 CSR_WRITE_2(sc, RL_IMR, 0x0000); 3484 if_setcapenablebit(ifp, IFCAP_POLLING, 0); 3485 RL_UNLOCK(sc); 3486 } else { 3487 error = ether_poll_deregister(ifp); 3488 /* Enable interrupts. */ 3489 RL_LOCK(sc); 3490 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 3491 if_setcapenablebit(ifp, 0, IFCAP_POLLING); 3492 RL_UNLOCK(sc); 3493 } 3494 } 3495 #endif /* DEVICE_POLLING */ 3496 RL_LOCK(sc); 3497 if ((mask & IFCAP_TXCSUM) != 0 && 3498 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { 3499 if_togglecapenable(ifp, IFCAP_TXCSUM); 3500 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 3501 if_sethwassistbits(ifp, RE_CSUM_FEATURES, 0); 3502 else 3503 if_sethwassistbits(ifp, 0, RE_CSUM_FEATURES); 3504 reinit = 1; 3505 } 3506 if ((mask & IFCAP_RXCSUM) != 0 && 3507 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) { 3508 if_togglecapenable(ifp, IFCAP_RXCSUM); 3509 reinit = 1; 3510 } 3511 if ((mask & IFCAP_TSO4) != 0 && 3512 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) { 3513 if_togglecapenable(ifp, IFCAP_TSO4); 3514 if ((IFCAP_TSO4 & if_getcapenable(ifp)) != 0) 3515 if_sethwassistbits(ifp, CSUM_TSO, 0); 3516 else 3517 if_sethwassistbits(ifp, 0, CSUM_TSO); 3518 if (if_getmtu(ifp) > RL_TSO_MTU && 3519 (if_getcapenable(ifp) & IFCAP_TSO4) != 0) { 3520 if_setcapenablebit(ifp, 0, IFCAP_TSO4); 3521 if_sethwassistbits(ifp, 0, CSUM_TSO); 3522 } 3523 } 3524 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 3525 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0) 3526 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 3527 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3528 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 3529 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 3530 /* TSO over VLAN requires VLAN hardware tagging. */ 3531 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0) 3532 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO); 3533 reinit = 1; 3534 } 3535 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 3536 (mask & (IFCAP_HWCSUM | IFCAP_TSO4 | 3537 IFCAP_VLAN_HWTSO)) != 0) 3538 reinit = 1; 3539 if ((mask & IFCAP_WOL) != 0 && 3540 (if_getcapabilities(ifp) & IFCAP_WOL) != 0) { 3541 if ((mask & IFCAP_WOL_UCAST) != 0) 3542 if_togglecapenable(ifp, IFCAP_WOL_UCAST); 3543 if ((mask & IFCAP_WOL_MCAST) != 0) 3544 if_togglecapenable(ifp, IFCAP_WOL_MCAST); 3545 if ((mask & IFCAP_WOL_MAGIC) != 0) 3546 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 3547 } 3548 if (reinit && if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3549 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3550 re_init_locked(sc); 3551 } 3552 RL_UNLOCK(sc); 3553 VLAN_CAPABILITIES(ifp); 3554 } 3555 break; 3556 default: 3557 error = ether_ioctl(ifp, command, data); 3558 break; 3559 } 3560 3561 return (error); 3562 } 3563 3564 static void 3565 re_watchdog(struct rl_softc *sc) 3566 { 3567 if_t ifp; 3568 3569 RL_LOCK_ASSERT(sc); 3570 3571 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 3572 return; 3573 3574 ifp = sc->rl_ifp; 3575 re_txeof(sc); 3576 if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) { 3577 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 3578 "-- recovering\n"); 3579 if (!if_sendq_empty(ifp)) 3580 re_start_locked(ifp); 3581 return; 3582 } 3583 3584 if_printf(ifp, "watchdog timeout\n"); 3585 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3586 3587 re_rxeof(sc, NULL); 3588 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3589 re_init_locked(sc); 3590 if (!if_sendq_empty(ifp)) 3591 re_start_locked(ifp); 3592 } 3593 3594 /* 3595 * Stop the adapter and free any mbufs allocated to the 3596 * RX and TX lists. 3597 */ 3598 static void 3599 re_stop(struct rl_softc *sc) 3600 { 3601 int i; 3602 if_t ifp; 3603 struct rl_txdesc *txd; 3604 struct rl_rxdesc *rxd; 3605 3606 RL_LOCK_ASSERT(sc); 3607 3608 ifp = sc->rl_ifp; 3609 3610 sc->rl_watchdog_timer = 0; 3611 callout_stop(&sc->rl_stat_callout); 3612 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 3613 3614 #ifdef DEV_NETMAP 3615 netmap_disable_all_rings(ifp); 3616 #endif /* DEV_NETMAP */ 3617 3618 /* 3619 * Disable accepting frames to put RX MAC into idle state. 3620 * Otherwise it's possible to get frames while stop command 3621 * execution is in progress and controller can DMA the frame 3622 * to already freed RX buffer during that period. 3623 */ 3624 CSR_WRITE_4(sc, RL_RXCFG, CSR_READ_4(sc, RL_RXCFG) & 3625 ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_MULTI | 3626 RL_RXCFG_RX_BROAD)); 3627 3628 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0) { 3629 /* Enable RXDV gate. */ 3630 CSR_WRITE_4(sc, RL_MISC, CSR_READ_4(sc, RL_MISC) | 3631 0x00080000); 3632 } 3633 3634 if ((sc->rl_flags & RL_FLAG_WAIT_TXPOLL) != 0) { 3635 for (i = RL_TIMEOUT; i > 0; i--) { 3636 if ((CSR_READ_1(sc, sc->rl_txstart) & 3637 RL_TXSTART_START) == 0) 3638 break; 3639 DELAY(20); 3640 } 3641 if (i == 0) 3642 device_printf(sc->rl_dev, 3643 "stopping TX poll timed out!\n"); 3644 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 3645 } else if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0) { 3646 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB | 3647 RL_CMD_RX_ENB); 3648 if ((sc->rl_flags & RL_FLAG_CMDSTOP_WAIT_TXQ) != 0) { 3649 for (i = RL_TIMEOUT; i > 0; i--) { 3650 if ((CSR_READ_4(sc, RL_TXCFG) & 3651 RL_TXCFG_QUEUE_EMPTY) != 0) 3652 break; 3653 DELAY(100); 3654 } 3655 if (i == 0) 3656 device_printf(sc->rl_dev, 3657 "stopping TXQ timed out!\n"); 3658 } 3659 } else 3660 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 3661 DELAY(1000); 3662 CSR_WRITE_2(sc, RL_IMR, 0x0000); 3663 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 3664 3665 if (sc->rl_head != NULL) { 3666 m_freem(sc->rl_head); 3667 sc->rl_head = sc->rl_tail = NULL; 3668 } 3669 3670 /* Free the TX list buffers. */ 3671 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 3672 txd = &sc->rl_ldata.rl_tx_desc[i]; 3673 if (txd->tx_m != NULL) { 3674 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 3675 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3676 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 3677 txd->tx_dmamap); 3678 m_freem(txd->tx_m); 3679 txd->tx_m = NULL; 3680 } 3681 } 3682 3683 /* Free the RX list buffers. */ 3684 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 3685 rxd = &sc->rl_ldata.rl_rx_desc[i]; 3686 if (rxd->rx_m != NULL) { 3687 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 3688 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3689 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 3690 rxd->rx_dmamap); 3691 m_freem(rxd->rx_m); 3692 rxd->rx_m = NULL; 3693 } 3694 } 3695 3696 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3697 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 3698 rxd = &sc->rl_ldata.rl_jrx_desc[i]; 3699 if (rxd->rx_m != NULL) { 3700 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, 3701 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3702 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, 3703 rxd->rx_dmamap); 3704 m_freem(rxd->rx_m); 3705 rxd->rx_m = NULL; 3706 } 3707 } 3708 } 3709 } 3710 3711 /* 3712 * Device suspend routine. Stop the interface and save some PCI 3713 * settings in case the BIOS doesn't restore them properly on 3714 * resume. 3715 */ 3716 static int 3717 re_suspend(device_t dev) 3718 { 3719 struct rl_softc *sc; 3720 3721 sc = device_get_softc(dev); 3722 3723 RL_LOCK(sc); 3724 re_stop(sc); 3725 re_setwol(sc); 3726 sc->suspended = 1; 3727 RL_UNLOCK(sc); 3728 3729 return (0); 3730 } 3731 3732 /* 3733 * Device resume routine. Restore some PCI settings in case the BIOS 3734 * doesn't, re-enable busmastering, and restart the interface if 3735 * appropriate. 3736 */ 3737 static int 3738 re_resume(device_t dev) 3739 { 3740 struct rl_softc *sc; 3741 if_t ifp; 3742 3743 sc = device_get_softc(dev); 3744 3745 RL_LOCK(sc); 3746 3747 ifp = sc->rl_ifp; 3748 /* Take controller out of sleep mode. */ 3749 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3750 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3751 CSR_WRITE_1(sc, RL_GPIO, 3752 CSR_READ_1(sc, RL_GPIO) | 0x01); 3753 } 3754 3755 /* 3756 * Clear WOL matching such that normal Rx filtering 3757 * wouldn't interfere with WOL patterns. 3758 */ 3759 re_clrwol(sc); 3760 3761 /* reinitialize interface if necessary */ 3762 if (if_getflags(ifp) & IFF_UP) 3763 re_init_locked(sc); 3764 3765 sc->suspended = 0; 3766 RL_UNLOCK(sc); 3767 3768 return (0); 3769 } 3770 3771 /* 3772 * Stop all chip I/O so that the kernel's probe routines don't 3773 * get confused by errant DMAs when rebooting. 3774 */ 3775 static int 3776 re_shutdown(device_t dev) 3777 { 3778 struct rl_softc *sc; 3779 3780 sc = device_get_softc(dev); 3781 3782 RL_LOCK(sc); 3783 re_stop(sc); 3784 /* 3785 * Mark interface as down since otherwise we will panic if 3786 * interrupt comes in later on, which can happen in some 3787 * cases. 3788 */ 3789 if_setflagbits(sc->rl_ifp, 0, IFF_UP); 3790 re_setwol(sc); 3791 RL_UNLOCK(sc); 3792 3793 return (0); 3794 } 3795 3796 static void 3797 re_set_linkspeed(struct rl_softc *sc) 3798 { 3799 struct mii_softc *miisc; 3800 struct mii_data *mii; 3801 int aneg, i, phyno; 3802 3803 RL_LOCK_ASSERT(sc); 3804 3805 mii = device_get_softc(sc->rl_miibus); 3806 mii_pollstat(mii); 3807 aneg = 0; 3808 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 3809 (IFM_ACTIVE | IFM_AVALID)) { 3810 switch IFM_SUBTYPE(mii->mii_media_active) { 3811 case IFM_10_T: 3812 case IFM_100_TX: 3813 return; 3814 case IFM_1000_T: 3815 aneg++; 3816 break; 3817 default: 3818 break; 3819 } 3820 } 3821 miisc = LIST_FIRST(&mii->mii_phys); 3822 phyno = miisc->mii_phy; 3823 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 3824 PHY_RESET(miisc); 3825 re_miibus_writereg(sc->rl_dev, phyno, MII_100T2CR, 0); 3826 re_miibus_writereg(sc->rl_dev, phyno, 3827 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 3828 re_miibus_writereg(sc->rl_dev, phyno, 3829 MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 3830 DELAY(1000); 3831 if (aneg != 0) { 3832 /* 3833 * Poll link state until re(4) get a 10/100Mbps link. 3834 */ 3835 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 3836 mii_pollstat(mii); 3837 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 3838 == (IFM_ACTIVE | IFM_AVALID)) { 3839 switch (IFM_SUBTYPE(mii->mii_media_active)) { 3840 case IFM_10_T: 3841 case IFM_100_TX: 3842 return; 3843 default: 3844 break; 3845 } 3846 } 3847 RL_UNLOCK(sc); 3848 pause("relnk", hz); 3849 RL_LOCK(sc); 3850 } 3851 if (i == MII_ANEGTICKS_GIGE) 3852 device_printf(sc->rl_dev, 3853 "establishing a link failed, WOL may not work!"); 3854 } 3855 /* 3856 * No link, force MAC to have 100Mbps, full-duplex link. 3857 * MAC does not require reprogramming on resolved speed/duplex, 3858 * so this is just for completeness. 3859 */ 3860 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 3861 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 3862 } 3863 3864 static void 3865 re_setwol(struct rl_softc *sc) 3866 { 3867 if_t ifp; 3868 int pmc; 3869 uint16_t pmstat; 3870 uint8_t v; 3871 3872 RL_LOCK_ASSERT(sc); 3873 3874 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3875 return; 3876 3877 ifp = sc->rl_ifp; 3878 /* Put controller into sleep mode. */ 3879 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3880 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3881 CSR_WRITE_1(sc, RL_GPIO, 3882 CSR_READ_1(sc, RL_GPIO) & ~0x01); 3883 } 3884 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) { 3885 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0) { 3886 /* Disable RXDV gate. */ 3887 CSR_WRITE_4(sc, RL_MISC, CSR_READ_4(sc, RL_MISC) & 3888 ~0x00080000); 3889 } 3890 re_set_rxmode(sc); 3891 if ((sc->rl_flags & RL_FLAG_WOL_MANLINK) != 0) 3892 re_set_linkspeed(sc); 3893 if ((sc->rl_flags & RL_FLAG_WOLRXENB) != 0) 3894 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB); 3895 } 3896 /* Enable config register write. */ 3897 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3898 3899 /* Enable PME. */ 3900 v = CSR_READ_1(sc, sc->rl_cfg1); 3901 v &= ~RL_CFG1_PME; 3902 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 3903 v |= RL_CFG1_PME; 3904 CSR_WRITE_1(sc, sc->rl_cfg1, v); 3905 3906 v = CSR_READ_1(sc, sc->rl_cfg3); 3907 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3908 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 3909 v |= RL_CFG3_WOL_MAGIC; 3910 CSR_WRITE_1(sc, sc->rl_cfg3, v); 3911 3912 v = CSR_READ_1(sc, sc->rl_cfg5); 3913 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST | 3914 RL_CFG5_WOL_LANWAKE); 3915 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) != 0) 3916 v |= RL_CFG5_WOL_UCAST; 3917 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0) 3918 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 3919 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 3920 v |= RL_CFG5_WOL_LANWAKE; 3921 CSR_WRITE_1(sc, sc->rl_cfg5, v); 3922 3923 /* Config register write done. */ 3924 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3925 3926 if ((if_getcapenable(ifp) & IFCAP_WOL) == 0 && 3927 (sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) 3928 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) & ~0x80); 3929 /* 3930 * It seems that hardware resets its link speed to 100Mbps in 3931 * power down mode so switching to 100Mbps in driver is not 3932 * needed. 3933 */ 3934 3935 /* Request PME if WOL is requested. */ 3936 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 3937 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3938 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 3939 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3940 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 3941 } 3942 3943 static void 3944 re_clrwol(struct rl_softc *sc) 3945 { 3946 int pmc; 3947 uint8_t v; 3948 3949 RL_LOCK_ASSERT(sc); 3950 3951 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3952 return; 3953 3954 /* Enable config register write. */ 3955 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3956 3957 v = CSR_READ_1(sc, sc->rl_cfg3); 3958 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3959 CSR_WRITE_1(sc, sc->rl_cfg3, v); 3960 3961 /* Config register write done. */ 3962 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3963 3964 v = CSR_READ_1(sc, sc->rl_cfg5); 3965 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3966 v &= ~RL_CFG5_WOL_LANWAKE; 3967 CSR_WRITE_1(sc, sc->rl_cfg5, v); 3968 } 3969 3970 static void 3971 re_add_sysctls(struct rl_softc *sc) 3972 { 3973 struct sysctl_ctx_list *ctx; 3974 struct sysctl_oid_list *children; 3975 int error; 3976 3977 ctx = device_get_sysctl_ctx(sc->rl_dev); 3978 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev)); 3979 3980 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "stats", 3981 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 3982 re_sysctl_stats, "I", "Statistics Information"); 3983 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) 3984 return; 3985 3986 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "int_rx_mod", 3987 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 3988 &sc->rl_int_rx_mod, 0, sysctl_hw_re_int_mod, "I", 3989 "re RX interrupt moderation"); 3990 /* Pull in device tunables. */ 3991 sc->rl_int_rx_mod = RL_TIMER_DEFAULT; 3992 error = resource_int_value(device_get_name(sc->rl_dev), 3993 device_get_unit(sc->rl_dev), "int_rx_mod", &sc->rl_int_rx_mod); 3994 if (error == 0) { 3995 if (sc->rl_int_rx_mod < RL_TIMER_MIN || 3996 sc->rl_int_rx_mod > RL_TIMER_MAX) { 3997 device_printf(sc->rl_dev, "int_rx_mod value out of " 3998 "range; using default: %d\n", 3999 RL_TIMER_DEFAULT); 4000 sc->rl_int_rx_mod = RL_TIMER_DEFAULT; 4001 } 4002 } 4003 } 4004 4005 static int 4006 re_sysctl_stats(SYSCTL_HANDLER_ARGS) 4007 { 4008 struct rl_softc *sc; 4009 struct rl_stats *stats; 4010 int error, i, result; 4011 4012 result = -1; 4013 error = sysctl_handle_int(oidp, &result, 0, req); 4014 if (error || req->newptr == NULL) 4015 return (error); 4016 4017 if (result == 1) { 4018 sc = (struct rl_softc *)arg1; 4019 RL_LOCK(sc); 4020 if ((if_getdrvflags(sc->rl_ifp) & IFF_DRV_RUNNING) == 0) { 4021 RL_UNLOCK(sc); 4022 goto done; 4023 } 4024 bus_dmamap_sync(sc->rl_ldata.rl_stag, 4025 sc->rl_ldata.rl_smap, BUS_DMASYNC_PREREAD); 4026 CSR_WRITE_4(sc, RL_DUMPSTATS_HI, 4027 RL_ADDR_HI(sc->rl_ldata.rl_stats_addr)); 4028 CSR_WRITE_4(sc, RL_DUMPSTATS_LO, 4029 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr)); 4030 CSR_WRITE_4(sc, RL_DUMPSTATS_LO, 4031 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr | 4032 RL_DUMPSTATS_START)); 4033 for (i = RL_TIMEOUT; i > 0; i--) { 4034 if ((CSR_READ_4(sc, RL_DUMPSTATS_LO) & 4035 RL_DUMPSTATS_START) == 0) 4036 break; 4037 DELAY(1000); 4038 } 4039 bus_dmamap_sync(sc->rl_ldata.rl_stag, 4040 sc->rl_ldata.rl_smap, BUS_DMASYNC_POSTREAD); 4041 RL_UNLOCK(sc); 4042 if (i == 0) { 4043 device_printf(sc->rl_dev, 4044 "DUMP statistics request timed out\n"); 4045 return (ETIMEDOUT); 4046 } 4047 done: 4048 stats = sc->rl_ldata.rl_stats; 4049 printf("%s statistics:\n", device_get_nameunit(sc->rl_dev)); 4050 printf("Tx frames : %ju\n", 4051 (uintmax_t)le64toh(stats->rl_tx_pkts)); 4052 printf("Rx frames : %ju\n", 4053 (uintmax_t)le64toh(stats->rl_rx_pkts)); 4054 printf("Tx errors : %ju\n", 4055 (uintmax_t)le64toh(stats->rl_tx_errs)); 4056 printf("Rx errors : %u\n", 4057 le32toh(stats->rl_rx_errs)); 4058 printf("Rx missed frames : %u\n", 4059 (uint32_t)le16toh(stats->rl_missed_pkts)); 4060 printf("Rx frame alignment errs : %u\n", 4061 (uint32_t)le16toh(stats->rl_rx_framealign_errs)); 4062 printf("Tx single collisions : %u\n", 4063 le32toh(stats->rl_tx_onecoll)); 4064 printf("Tx multiple collisions : %u\n", 4065 le32toh(stats->rl_tx_multicolls)); 4066 printf("Rx unicast frames : %ju\n", 4067 (uintmax_t)le64toh(stats->rl_rx_ucasts)); 4068 printf("Rx broadcast frames : %ju\n", 4069 (uintmax_t)le64toh(stats->rl_rx_bcasts)); 4070 printf("Rx multicast frames : %u\n", 4071 le32toh(stats->rl_rx_mcasts)); 4072 printf("Tx aborts : %u\n", 4073 (uint32_t)le16toh(stats->rl_tx_aborts)); 4074 printf("Tx underruns : %u\n", 4075 (uint32_t)le16toh(stats->rl_rx_underruns)); 4076 } 4077 4078 return (error); 4079 } 4080 4081 static int 4082 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4083 { 4084 int error, value; 4085 4086 if (arg1 == NULL) 4087 return (EINVAL); 4088 value = *(int *)arg1; 4089 error = sysctl_handle_int(oidp, &value, 0, req); 4090 if (error || req->newptr == NULL) 4091 return (error); 4092 if (value < low || value > high) 4093 return (EINVAL); 4094 *(int *)arg1 = value; 4095 4096 return (0); 4097 } 4098 4099 static int 4100 sysctl_hw_re_int_mod(SYSCTL_HANDLER_ARGS) 4101 { 4102 4103 return (sysctl_int_range(oidp, arg1, arg2, req, RL_TIMER_MIN, 4104 RL_TIMER_MAX)); 4105 } 4106 4107 #ifdef DEBUGNET 4108 static void 4109 re_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 4110 { 4111 struct rl_softc *sc; 4112 4113 sc = if_getsoftc(ifp); 4114 RL_LOCK(sc); 4115 *nrxr = sc->rl_ldata.rl_rx_desc_cnt; 4116 *ncl = DEBUGNET_MAX_IN_FLIGHT; 4117 *clsize = (if_getmtu(ifp) > RL_MTU && 4118 (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) ? MJUM9BYTES : MCLBYTES; 4119 RL_UNLOCK(sc); 4120 } 4121 4122 static void 4123 re_debugnet_event(if_t ifp __unused, enum debugnet_ev event __unused) 4124 { 4125 } 4126 4127 static int 4128 re_debugnet_transmit(if_t ifp, struct mbuf *m) 4129 { 4130 struct rl_softc *sc; 4131 int error; 4132 4133 sc = if_getsoftc(ifp); 4134 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 4135 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) 4136 return (EBUSY); 4137 4138 error = re_encap(sc, &m); 4139 if (error == 0) 4140 re_start_tx(sc); 4141 return (error); 4142 } 4143 4144 static int 4145 re_debugnet_poll(if_t ifp, int count) 4146 { 4147 struct rl_softc *sc; 4148 int error; 4149 4150 sc = if_getsoftc(ifp); 4151 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0 || 4152 (sc->rl_flags & RL_FLAG_LINK) == 0) 4153 return (EBUSY); 4154 4155 re_txeof(sc); 4156 error = re_rxeof(sc, NULL); 4157 if (error != 0 && error != EAGAIN) 4158 return (error); 4159 return (0); 4160 } 4161 #endif /* DEBUGNET */ 4162