1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 1997, 1998-2003 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 /* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44 /* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111 #ifdef HAVE_KERNEL_OPTION_HEADERS 112 #include "opt_device_polling.h" 113 #endif 114 115 #include <sys/param.h> 116 #include <sys/endian.h> 117 #include <sys/systm.h> 118 #include <sys/sockio.h> 119 #include <sys/mbuf.h> 120 #include <sys/malloc.h> 121 #include <sys/module.h> 122 #include <sys/kernel.h> 123 #include <sys/socket.h> 124 #include <sys/lock.h> 125 #include <sys/mutex.h> 126 #include <sys/sysctl.h> 127 #include <sys/taskqueue.h> 128 129 #include <net/debugnet.h> 130 #include <net/if.h> 131 #include <net/if_var.h> 132 #include <net/if_arp.h> 133 #include <net/ethernet.h> 134 #include <net/if_dl.h> 135 #include <net/if_media.h> 136 #include <net/if_types.h> 137 #include <net/if_vlan_var.h> 138 139 #include <net/bpf.h> 140 141 #include <machine/bus.h> 142 #include <machine/resource.h> 143 #include <sys/bus.h> 144 #include <sys/rman.h> 145 146 #include <dev/mii/mii.h> 147 #include <dev/mii/miivar.h> 148 149 #include <dev/pci/pcireg.h> 150 #include <dev/pci/pcivar.h> 151 152 #include <dev/rl/if_rlreg.h> 153 154 MODULE_DEPEND(re, pci, 1, 1, 1); 155 MODULE_DEPEND(re, ether, 1, 1, 1); 156 MODULE_DEPEND(re, miibus, 1, 1, 1); 157 158 /* "device miibus" required. See GENERIC if you get errors here. */ 159 #include "miibus_if.h" 160 161 /* Tunables. */ 162 static int intr_filter = 0; 163 TUNABLE_INT("hw.re.intr_filter", &intr_filter); 164 static int msi_disable = 0; 165 TUNABLE_INT("hw.re.msi_disable", &msi_disable); 166 static int msix_disable = 0; 167 TUNABLE_INT("hw.re.msix_disable", &msix_disable); 168 static int prefer_iomap = 0; 169 TUNABLE_INT("hw.re.prefer_iomap", &prefer_iomap); 170 171 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 172 173 /* 174 * Various supported device vendors/types and their names. 175 */ 176 static const struct rl_type re_devs[] = { 177 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0, 178 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 179 { DLINK_VENDORID, DLINK_DEVICEID_530T_REVC, 0, 180 "D-Link DGE-530(T) Gigabit Ethernet Adapter" }, 181 { RT_VENDORID, RT_DEVICEID_2600, 0, 182 "RealTek Killer E2600 Gigabit Ethernet Controller" }, 183 { RT_VENDORID, RT_DEVICEID_8139, 0, 184 "RealTek 8139C+ 10/100BaseTX" }, 185 { RT_VENDORID, RT_DEVICEID_8101E, 0, 186 "RealTek 810xE PCIe 10/100baseTX" }, 187 { RT_VENDORID, RT_DEVICEID_8168, 0, 188 "RealTek 8168/8111 B/C/CP/D/DP/E/F/G PCIe Gigabit Ethernet" }, 189 { RT_VENDORID, RT_DEVICEID_8161, 0, 190 "RealTek 8168 Gigabit Ethernet" }, 191 { NCUBE_VENDORID, RT_DEVICEID_8168, 0, 192 "TP-Link TG-3468 v2 (RTL8168) Gigabit Ethernet" }, 193 { RT_VENDORID, RT_DEVICEID_8169, 0, 194 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" }, 195 { RT_VENDORID, RT_DEVICEID_8169SC, 0, 196 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 197 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0, 198 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 199 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0, 200 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 201 { USR_VENDORID, USR_DEVICEID_997902, 0, 202 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 203 }; 204 205 static const struct rl_hwrev re_hwrevs[] = { 206 { RL_HWREV_8139, RL_8139, "", RL_MTU }, 207 { RL_HWREV_8139A, RL_8139, "A", RL_MTU }, 208 { RL_HWREV_8139AG, RL_8139, "A-G", RL_MTU }, 209 { RL_HWREV_8139B, RL_8139, "B", RL_MTU }, 210 { RL_HWREV_8130, RL_8139, "8130", RL_MTU }, 211 { RL_HWREV_8139C, RL_8139, "C", RL_MTU }, 212 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C", RL_MTU }, 213 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+", RL_MTU }, 214 { RL_HWREV_8168B_SPIN1, RL_8169, "8168", RL_JUMBO_MTU }, 215 { RL_HWREV_8169, RL_8169, "8169", RL_JUMBO_MTU }, 216 { RL_HWREV_8169S, RL_8169, "8169S", RL_JUMBO_MTU }, 217 { RL_HWREV_8110S, RL_8169, "8110S", RL_JUMBO_MTU }, 218 { RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB", RL_JUMBO_MTU }, 219 { RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU }, 220 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL", RL_JUMBO_MTU }, 221 { RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU }, 222 { RL_HWREV_8100, RL_8139, "8100", RL_MTU }, 223 { RL_HWREV_8101, RL_8139, "8101", RL_MTU }, 224 { RL_HWREV_8100E, RL_8169, "8100E", RL_MTU }, 225 { RL_HWREV_8101E, RL_8169, "8101E", RL_MTU }, 226 { RL_HWREV_8102E, RL_8169, "8102E", RL_MTU }, 227 { RL_HWREV_8102EL, RL_8169, "8102EL", RL_MTU }, 228 { RL_HWREV_8102EL_SPIN1, RL_8169, "8102EL", RL_MTU }, 229 { RL_HWREV_8103E, RL_8169, "8103E", RL_MTU }, 230 { RL_HWREV_8401E, RL_8169, "8401E", RL_MTU }, 231 { RL_HWREV_8402, RL_8169, "8402", RL_MTU }, 232 { RL_HWREV_8105E, RL_8169, "8105E", RL_MTU }, 233 { RL_HWREV_8105E_SPIN1, RL_8169, "8105E", RL_MTU }, 234 { RL_HWREV_8106E, RL_8169, "8106E", RL_MTU }, 235 { RL_HWREV_8168B_SPIN2, RL_8169, "8168", RL_JUMBO_MTU }, 236 { RL_HWREV_8168B_SPIN3, RL_8169, "8168", RL_JUMBO_MTU }, 237 { RL_HWREV_8168C, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K }, 238 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K }, 239 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP", RL_JUMBO_MTU_6K }, 240 { RL_HWREV_8168D, RL_8169, "8168D/8111D", RL_JUMBO_MTU_9K }, 241 { RL_HWREV_8168DP, RL_8169, "8168DP/8111DP", RL_JUMBO_MTU_9K }, 242 { RL_HWREV_8168E, RL_8169, "8168E/8111E", RL_JUMBO_MTU_9K}, 243 { RL_HWREV_8168E_VL, RL_8169, "8168E/8111E-VL", RL_JUMBO_MTU_6K}, 244 { RL_HWREV_8168EP, RL_8169, "8168EP/8111EP", RL_JUMBO_MTU_9K}, 245 { RL_HWREV_8168F, RL_8169, "8168F/8111F", RL_JUMBO_MTU_9K}, 246 { RL_HWREV_8168FP, RL_8169, "8168FP/8111FP", RL_JUMBO_MTU_9K}, 247 { RL_HWREV_8168G, RL_8169, "8168G/8111G", RL_JUMBO_MTU_9K}, 248 { RL_HWREV_8168GU, RL_8169, "8168GU/8111GU", RL_JUMBO_MTU_9K}, 249 { RL_HWREV_8168H, RL_8169, "8168H/8111H", RL_JUMBO_MTU_9K}, 250 { RL_HWREV_8411, RL_8169, "8411", RL_JUMBO_MTU_9K}, 251 { RL_HWREV_8411B, RL_8169, "8411B", RL_JUMBO_MTU_9K}, 252 { 0, 0, NULL, 0 } 253 }; 254 255 static int re_probe (device_t); 256 static int re_attach (device_t); 257 static int re_detach (device_t); 258 259 static int re_encap (struct rl_softc *, struct mbuf **); 260 261 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 262 static int re_allocmem (device_t, struct rl_softc *); 263 static __inline void re_discard_rxbuf 264 (struct rl_softc *, int); 265 static int re_newbuf (struct rl_softc *, int); 266 static int re_jumbo_newbuf (struct rl_softc *, int); 267 static int re_rx_list_init (struct rl_softc *); 268 static int re_jrx_list_init (struct rl_softc *); 269 static int re_tx_list_init (struct rl_softc *); 270 #ifdef RE_FIXUP_RX 271 static __inline void re_fixup_rx 272 (struct mbuf *); 273 #endif 274 static int re_rxeof (struct rl_softc *, int *); 275 static void re_txeof (struct rl_softc *); 276 #ifdef DEVICE_POLLING 277 static int re_poll (if_t, enum poll_cmd, int); 278 static int re_poll_locked (if_t, enum poll_cmd, int); 279 #endif 280 static int re_intr (void *); 281 static void re_intr_msi (void *); 282 static void re_tick (void *); 283 static void re_int_task (void *, int); 284 static void re_start (if_t); 285 static void re_start_locked (if_t); 286 static void re_start_tx (struct rl_softc *); 287 static int re_ioctl (if_t, u_long, caddr_t); 288 static void re_init (void *); 289 static void re_init_locked (struct rl_softc *); 290 static void re_stop (struct rl_softc *); 291 static void re_watchdog (struct rl_softc *); 292 static int re_suspend (device_t); 293 static int re_resume (device_t); 294 static int re_shutdown (device_t); 295 static int re_ifmedia_upd (if_t); 296 static void re_ifmedia_sts (if_t, struct ifmediareq *); 297 298 static void re_eeprom_putbyte (struct rl_softc *, int); 299 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 300 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 301 static int re_gmii_readreg (device_t, int, int); 302 static int re_gmii_writereg (device_t, int, int, int); 303 304 static int re_miibus_readreg (device_t, int, int); 305 static int re_miibus_writereg (device_t, int, int, int); 306 static void re_miibus_statchg (device_t); 307 308 static void re_set_jumbo (struct rl_softc *, int); 309 static void re_set_rxmode (struct rl_softc *); 310 static void re_reset (struct rl_softc *); 311 static void re_setwol (struct rl_softc *); 312 static void re_clrwol (struct rl_softc *); 313 static void re_set_linkspeed (struct rl_softc *); 314 315 DEBUGNET_DEFINE(re); 316 317 #ifdef DEV_NETMAP /* see ixgbe.c for details */ 318 #include <dev/netmap/if_re_netmap.h> 319 MODULE_DEPEND(re, netmap, 1, 1, 1); 320 #endif /* !DEV_NETMAP */ 321 322 #ifdef RE_DIAG 323 static int re_diag (struct rl_softc *); 324 #endif 325 326 static void re_add_sysctls (struct rl_softc *); 327 static int re_sysctl_stats (SYSCTL_HANDLER_ARGS); 328 static int sysctl_int_range (SYSCTL_HANDLER_ARGS, int, int); 329 static int sysctl_hw_re_int_mod (SYSCTL_HANDLER_ARGS); 330 331 static device_method_t re_methods[] = { 332 /* Device interface */ 333 DEVMETHOD(device_probe, re_probe), 334 DEVMETHOD(device_attach, re_attach), 335 DEVMETHOD(device_detach, re_detach), 336 DEVMETHOD(device_suspend, re_suspend), 337 DEVMETHOD(device_resume, re_resume), 338 DEVMETHOD(device_shutdown, re_shutdown), 339 340 /* MII interface */ 341 DEVMETHOD(miibus_readreg, re_miibus_readreg), 342 DEVMETHOD(miibus_writereg, re_miibus_writereg), 343 DEVMETHOD(miibus_statchg, re_miibus_statchg), 344 345 DEVMETHOD_END 346 }; 347 348 static driver_t re_driver = { 349 "re", 350 re_methods, 351 sizeof(struct rl_softc) 352 }; 353 354 DRIVER_MODULE(re, pci, re_driver, 0, 0); 355 DRIVER_MODULE(miibus, re, miibus_driver, 0, 0); 356 MODULE_PNP_INFO("U16:vendor;U16:device;U32:#;D:#", pci, re, re_devs, 357 nitems(re_devs) - 1); 358 359 #define EE_SET(x) \ 360 CSR_WRITE_1(sc, RL_EECMD, \ 361 CSR_READ_1(sc, RL_EECMD) | x) 362 363 #define EE_CLR(x) \ 364 CSR_WRITE_1(sc, RL_EECMD, \ 365 CSR_READ_1(sc, RL_EECMD) & ~x) 366 367 /* 368 * Send a read command and address to the EEPROM, check for ACK. 369 */ 370 static void 371 re_eeprom_putbyte(struct rl_softc *sc, int addr) 372 { 373 int d, i; 374 375 d = addr | (RL_9346_READ << sc->rl_eewidth); 376 377 /* 378 * Feed in each bit and strobe the clock. 379 */ 380 381 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 382 if (d & i) { 383 EE_SET(RL_EE_DATAIN); 384 } else { 385 EE_CLR(RL_EE_DATAIN); 386 } 387 DELAY(100); 388 EE_SET(RL_EE_CLK); 389 DELAY(150); 390 EE_CLR(RL_EE_CLK); 391 DELAY(100); 392 } 393 } 394 395 /* 396 * Read a word of data stored in the EEPROM at address 'addr.' 397 */ 398 static void 399 re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest) 400 { 401 int i; 402 u_int16_t word = 0; 403 404 /* 405 * Send address of word we want to read. 406 */ 407 re_eeprom_putbyte(sc, addr); 408 409 /* 410 * Start reading bits from EEPROM. 411 */ 412 for (i = 0x8000; i; i >>= 1) { 413 EE_SET(RL_EE_CLK); 414 DELAY(100); 415 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 416 word |= i; 417 EE_CLR(RL_EE_CLK); 418 DELAY(100); 419 } 420 421 *dest = word; 422 } 423 424 /* 425 * Read a sequence of words from the EEPROM. 426 */ 427 static void 428 re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt) 429 { 430 int i; 431 u_int16_t word = 0, *ptr; 432 433 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 434 435 DELAY(100); 436 437 for (i = 0; i < cnt; i++) { 438 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 439 re_eeprom_getword(sc, off + i, &word); 440 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 441 ptr = (u_int16_t *)(dest + (i * 2)); 442 *ptr = word; 443 } 444 445 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 446 } 447 448 static int 449 re_gmii_readreg(device_t dev, int phy, int reg) 450 { 451 struct rl_softc *sc; 452 u_int32_t rval; 453 int i; 454 455 sc = device_get_softc(dev); 456 457 /* Let the rgephy driver read the GMEDIASTAT register */ 458 459 if (reg == RL_GMEDIASTAT) { 460 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 461 return (rval); 462 } 463 464 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 465 466 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 467 rval = CSR_READ_4(sc, RL_PHYAR); 468 if (rval & RL_PHYAR_BUSY) 469 break; 470 DELAY(25); 471 } 472 473 if (i == RL_PHY_TIMEOUT) { 474 device_printf(sc->rl_dev, "PHY read failed\n"); 475 return (0); 476 } 477 478 /* 479 * Controller requires a 20us delay to process next MDIO request. 480 */ 481 DELAY(20); 482 483 return (rval & RL_PHYAR_PHYDATA); 484 } 485 486 static int 487 re_gmii_writereg(device_t dev, int phy, int reg, int data) 488 { 489 struct rl_softc *sc; 490 u_int32_t rval; 491 int i; 492 493 sc = device_get_softc(dev); 494 495 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 496 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 497 498 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 499 rval = CSR_READ_4(sc, RL_PHYAR); 500 if (!(rval & RL_PHYAR_BUSY)) 501 break; 502 DELAY(25); 503 } 504 505 if (i == RL_PHY_TIMEOUT) { 506 device_printf(sc->rl_dev, "PHY write failed\n"); 507 return (0); 508 } 509 510 /* 511 * Controller requires a 20us delay to process next MDIO request. 512 */ 513 DELAY(20); 514 515 return (0); 516 } 517 518 static int 519 re_miibus_readreg(device_t dev, int phy, int reg) 520 { 521 struct rl_softc *sc; 522 u_int16_t rval = 0; 523 u_int16_t re8139_reg = 0; 524 525 sc = device_get_softc(dev); 526 527 if (sc->rl_type == RL_8169) { 528 rval = re_gmii_readreg(dev, phy, reg); 529 return (rval); 530 } 531 532 switch (reg) { 533 case MII_BMCR: 534 re8139_reg = RL_BMCR; 535 break; 536 case MII_BMSR: 537 re8139_reg = RL_BMSR; 538 break; 539 case MII_ANAR: 540 re8139_reg = RL_ANAR; 541 break; 542 case MII_ANER: 543 re8139_reg = RL_ANER; 544 break; 545 case MII_ANLPAR: 546 re8139_reg = RL_LPAR; 547 break; 548 case MII_PHYIDR1: 549 case MII_PHYIDR2: 550 return (0); 551 /* 552 * Allow the rlphy driver to read the media status 553 * register. If we have a link partner which does not 554 * support NWAY, this is the register which will tell 555 * us the results of parallel detection. 556 */ 557 case RL_MEDIASTAT: 558 rval = CSR_READ_1(sc, RL_MEDIASTAT); 559 return (rval); 560 default: 561 device_printf(sc->rl_dev, "bad phy register\n"); 562 return (0); 563 } 564 rval = CSR_READ_2(sc, re8139_reg); 565 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 566 /* 8139C+ has different bit layout. */ 567 rval &= ~(BMCR_LOOP | BMCR_ISO); 568 } 569 return (rval); 570 } 571 572 static int 573 re_miibus_writereg(device_t dev, int phy, int reg, int data) 574 { 575 struct rl_softc *sc; 576 u_int16_t re8139_reg = 0; 577 int rval = 0; 578 579 sc = device_get_softc(dev); 580 581 if (sc->rl_type == RL_8169) { 582 rval = re_gmii_writereg(dev, phy, reg, data); 583 return (rval); 584 } 585 586 switch (reg) { 587 case MII_BMCR: 588 re8139_reg = RL_BMCR; 589 if (sc->rl_type == RL_8139CPLUS) { 590 /* 8139C+ has different bit layout. */ 591 data &= ~(BMCR_LOOP | BMCR_ISO); 592 } 593 break; 594 case MII_BMSR: 595 re8139_reg = RL_BMSR; 596 break; 597 case MII_ANAR: 598 re8139_reg = RL_ANAR; 599 break; 600 case MII_ANER: 601 re8139_reg = RL_ANER; 602 break; 603 case MII_ANLPAR: 604 re8139_reg = RL_LPAR; 605 break; 606 case MII_PHYIDR1: 607 case MII_PHYIDR2: 608 return (0); 609 break; 610 default: 611 device_printf(sc->rl_dev, "bad phy register\n"); 612 return (0); 613 } 614 CSR_WRITE_2(sc, re8139_reg, data); 615 return (0); 616 } 617 618 static void 619 re_miibus_statchg(device_t dev) 620 { 621 struct rl_softc *sc; 622 if_t ifp; 623 struct mii_data *mii; 624 625 sc = device_get_softc(dev); 626 mii = device_get_softc(sc->rl_miibus); 627 ifp = sc->rl_ifp; 628 if (mii == NULL || ifp == NULL || 629 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 630 return; 631 632 sc->rl_flags &= ~RL_FLAG_LINK; 633 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 634 (IFM_ACTIVE | IFM_AVALID)) { 635 switch (IFM_SUBTYPE(mii->mii_media_active)) { 636 case IFM_10_T: 637 case IFM_100_TX: 638 sc->rl_flags |= RL_FLAG_LINK; 639 break; 640 case IFM_1000_T: 641 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0) 642 break; 643 sc->rl_flags |= RL_FLAG_LINK; 644 break; 645 default: 646 break; 647 } 648 } 649 /* 650 * RealTek controllers do not provide any interface to the RX/TX 651 * MACs for resolved speed, duplex and flow-control parameters. 652 */ 653 } 654 655 static u_int 656 re_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 657 { 658 uint32_t h, *hashes = arg; 659 660 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26; 661 if (h < 32) 662 hashes[0] |= (1 << h); 663 else 664 hashes[1] |= (1 << (h - 32)); 665 666 return (1); 667 } 668 669 /* 670 * Set the RX configuration and 64-bit multicast hash filter. 671 */ 672 static void 673 re_set_rxmode(struct rl_softc *sc) 674 { 675 if_t ifp; 676 uint32_t h, hashes[2] = { 0, 0 }; 677 uint32_t rxfilt; 678 679 RL_LOCK_ASSERT(sc); 680 681 ifp = sc->rl_ifp; 682 683 rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD; 684 if ((sc->rl_flags & RL_FLAG_EARLYOFF) != 0) 685 rxfilt |= RL_RXCFG_EARLYOFF; 686 else if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0) 687 rxfilt |= RL_RXCFG_EARLYOFFV2; 688 689 if (if_getflags(ifp) & (IFF_ALLMULTI | IFF_PROMISC)) { 690 if (if_getflags(ifp) & IFF_PROMISC) 691 rxfilt |= RL_RXCFG_RX_ALLPHYS; 692 /* 693 * Unlike other hardwares, we have to explicitly set 694 * RL_RXCFG_RX_MULTI to receive multicast frames in 695 * promiscuous mode. 696 */ 697 rxfilt |= RL_RXCFG_RX_MULTI; 698 hashes[0] = hashes[1] = 0xffffffff; 699 goto done; 700 } 701 702 if_foreach_llmaddr(ifp, re_hash_maddr, hashes); 703 704 if (hashes[0] != 0 || hashes[1] != 0) { 705 /* 706 * For some unfathomable reason, RealTek decided to 707 * reverse the order of the multicast hash registers 708 * in the PCI Express parts. This means we have to 709 * write the hash pattern in reverse order for those 710 * devices. 711 */ 712 if ((sc->rl_flags & RL_FLAG_PCIE) != 0) { 713 h = bswap32(hashes[0]); 714 hashes[0] = bswap32(hashes[1]); 715 hashes[1] = h; 716 } 717 rxfilt |= RL_RXCFG_RX_MULTI; 718 } 719 720 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168F) { 721 /* Disable multicast filtering due to silicon bug. */ 722 hashes[0] = 0xffffffff; 723 hashes[1] = 0xffffffff; 724 } 725 726 done: 727 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 728 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 729 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 730 } 731 732 static void 733 re_reset(struct rl_softc *sc) 734 { 735 int i; 736 737 RL_LOCK_ASSERT(sc); 738 739 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 740 741 for (i = 0; i < RL_TIMEOUT; i++) { 742 DELAY(10); 743 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 744 break; 745 } 746 if (i == RL_TIMEOUT) 747 device_printf(sc->rl_dev, "reset never completed!\n"); 748 749 if ((sc->rl_flags & RL_FLAG_MACRESET) != 0) 750 CSR_WRITE_1(sc, 0x82, 1); 751 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169S) 752 re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0); 753 } 754 755 #ifdef RE_DIAG 756 757 /* 758 * The following routine is designed to test for a defect on some 759 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 760 * lines connected to the bus, however for a 32-bit only card, they 761 * should be pulled high. The result of this defect is that the 762 * NIC will not work right if you plug it into a 64-bit slot: DMA 763 * operations will be done with 64-bit transfers, which will fail 764 * because the 64-bit data lines aren't connected. 765 * 766 * There's no way to work around this (short of talking a soldering 767 * iron to the board), however we can detect it. The method we use 768 * here is to put the NIC into digital loopback mode, set the receiver 769 * to promiscuous mode, and then try to send a frame. We then compare 770 * the frame data we sent to what was received. If the data matches, 771 * then the NIC is working correctly, otherwise we know the user has 772 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 773 * slot. In the latter case, there's no way the NIC can work correctly, 774 * so we print out a message on the console and abort the device attach. 775 */ 776 777 static int 778 re_diag(struct rl_softc *sc) 779 { 780 if_t ifp = sc->rl_ifp; 781 struct mbuf *m0; 782 struct ether_header *eh; 783 struct rl_desc *cur_rx; 784 u_int16_t status; 785 u_int32_t rxstat; 786 int total_len, i, error = 0, phyaddr; 787 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 788 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 789 790 /* Allocate a single mbuf */ 791 MGETHDR(m0, M_NOWAIT, MT_DATA); 792 if (m0 == NULL) 793 return (ENOBUFS); 794 795 RL_LOCK(sc); 796 797 /* 798 * Initialize the NIC in test mode. This sets the chip up 799 * so that it can send and receive frames, but performs the 800 * following special functions: 801 * - Puts receiver in promiscuous mode 802 * - Enables digital loopback mode 803 * - Leaves interrupts turned off 804 */ 805 806 if_setflagbit(ifp, IFF_PROMISC, 0); 807 sc->rl_testmode = 1; 808 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 809 re_init_locked(sc); 810 sc->rl_flags |= RL_FLAG_LINK; 811 if (sc->rl_type == RL_8169) 812 phyaddr = 1; 813 else 814 phyaddr = 0; 815 816 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 817 for (i = 0; i < RL_TIMEOUT; i++) { 818 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 819 if (!(status & BMCR_RESET)) 820 break; 821 } 822 823 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 824 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 825 826 DELAY(100000); 827 828 /* Put some data in the mbuf */ 829 830 eh = mtod(m0, struct ether_header *); 831 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 832 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 833 eh->ether_type = htons(ETHERTYPE_IP); 834 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 835 836 /* 837 * Queue the packet, start transmission. 838 * Note: IF_HANDOFF() ultimately calls re_start() for us. 839 */ 840 841 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 842 RL_UNLOCK(sc); 843 /* XXX: re_diag must not be called when in ALTQ mode */ 844 if_handoff(ifp, m0, ifp); 845 RL_LOCK(sc); 846 m0 = NULL; 847 848 /* Wait for it to propagate through the chip */ 849 850 DELAY(100000); 851 for (i = 0; i < RL_TIMEOUT; i++) { 852 status = CSR_READ_2(sc, RL_ISR); 853 CSR_WRITE_2(sc, RL_ISR, status); 854 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 855 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 856 break; 857 DELAY(10); 858 } 859 860 if (i == RL_TIMEOUT) { 861 device_printf(sc->rl_dev, 862 "diagnostic failed, failed to receive packet in" 863 " loopback mode\n"); 864 error = EIO; 865 goto done; 866 } 867 868 /* 869 * The packet should have been dumped into the first 870 * entry in the RX DMA ring. Grab it from there. 871 */ 872 873 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 874 sc->rl_ldata.rl_rx_list_map, 875 BUS_DMASYNC_POSTREAD); 876 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 877 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 878 BUS_DMASYNC_POSTREAD); 879 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 880 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 881 882 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 883 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 884 eh = mtod(m0, struct ether_header *); 885 886 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 887 total_len = RL_RXBYTES(cur_rx); 888 rxstat = le32toh(cur_rx->rl_cmdstat); 889 890 if (total_len != ETHER_MIN_LEN) { 891 device_printf(sc->rl_dev, 892 "diagnostic failed, received short packet\n"); 893 error = EIO; 894 goto done; 895 } 896 897 /* Test that the received packet data matches what we sent. */ 898 899 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 900 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 901 ntohs(eh->ether_type) != ETHERTYPE_IP) { 902 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 903 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 904 dst, ":", src, ":", ETHERTYPE_IP); 905 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 906 eh->ether_dhost, ":", eh->ether_shost, ":", 907 ntohs(eh->ether_type)); 908 device_printf(sc->rl_dev, "You may have a defective 32-bit " 909 "NIC plugged into a 64-bit PCI slot.\n"); 910 device_printf(sc->rl_dev, "Please re-install the NIC in a " 911 "32-bit slot for proper operation.\n"); 912 device_printf(sc->rl_dev, "Read the re(4) man page for more " 913 "details.\n"); 914 error = EIO; 915 } 916 917 done: 918 /* Turn interface off, release resources */ 919 920 sc->rl_testmode = 0; 921 sc->rl_flags &= ~RL_FLAG_LINK; 922 if_setflagbit(ifp, 0, IFF_PROMISC); 923 re_stop(sc); 924 if (m0 != NULL) 925 m_freem(m0); 926 927 RL_UNLOCK(sc); 928 929 return (error); 930 } 931 932 #endif 933 934 /* 935 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 936 * IDs against our list and return a device name if we find a match. 937 */ 938 static int 939 re_probe(device_t dev) 940 { 941 const struct rl_type *t; 942 uint16_t devid, vendor; 943 uint16_t revid, sdevid; 944 int i; 945 946 vendor = pci_get_vendor(dev); 947 devid = pci_get_device(dev); 948 revid = pci_get_revid(dev); 949 sdevid = pci_get_subdevice(dev); 950 951 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 952 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 953 /* 954 * Only attach to rev. 3 of the Linksys EG1032 adapter. 955 * Rev. 2 is supported by sk(4). 956 */ 957 return (ENXIO); 958 } 959 } 960 961 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 962 if (revid != 0x20) { 963 /* 8139, let rl(4) take care of this device. */ 964 return (ENXIO); 965 } 966 } 967 968 t = re_devs; 969 for (i = 0; i < nitems(re_devs); i++, t++) { 970 if (vendor == t->rl_vid && devid == t->rl_did) { 971 device_set_desc(dev, t->rl_name); 972 return (BUS_PROBE_DEFAULT); 973 } 974 } 975 976 return (ENXIO); 977 } 978 979 /* 980 * Map a single buffer address. 981 */ 982 983 static void 984 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 985 { 986 bus_addr_t *addr; 987 988 if (error) 989 return; 990 991 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 992 addr = arg; 993 *addr = segs->ds_addr; 994 } 995 996 static int 997 re_allocmem(device_t dev, struct rl_softc *sc) 998 { 999 bus_addr_t lowaddr; 1000 bus_size_t rx_list_size, tx_list_size; 1001 int error; 1002 int i; 1003 1004 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 1005 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 1006 1007 /* 1008 * Allocate the parent bus DMA tag appropriate for PCI. 1009 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD 1010 * register should be set. However some RealTek chips are known 1011 * to be buggy on DAC handling, therefore disable DAC by limiting 1012 * DMA address space to 32bit. PCIe variants of RealTek chips 1013 * may not have the limitation. 1014 */ 1015 lowaddr = BUS_SPACE_MAXADDR; 1016 if ((sc->rl_flags & RL_FLAG_PCIE) == 0) 1017 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1018 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 1019 lowaddr, BUS_SPACE_MAXADDR, NULL, NULL, 1020 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 1021 NULL, NULL, &sc->rl_parent_tag); 1022 if (error) { 1023 device_printf(dev, "could not allocate parent DMA tag\n"); 1024 return (error); 1025 } 1026 1027 /* 1028 * Allocate map for TX mbufs. 1029 */ 1030 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 1031 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1032 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 1033 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 1034 if (error) { 1035 device_printf(dev, "could not allocate TX DMA tag\n"); 1036 return (error); 1037 } 1038 1039 /* 1040 * Allocate map for RX mbufs. 1041 */ 1042 1043 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 1044 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 1045 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1046 MJUM9BYTES, 1, MJUM9BYTES, 0, NULL, NULL, 1047 &sc->rl_ldata.rl_jrx_mtag); 1048 if (error) { 1049 device_printf(dev, 1050 "could not allocate jumbo RX DMA tag\n"); 1051 return (error); 1052 } 1053 } 1054 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 1055 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1056 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 1057 if (error) { 1058 device_printf(dev, "could not allocate RX DMA tag\n"); 1059 return (error); 1060 } 1061 1062 /* 1063 * Allocate map for TX descriptor list. 1064 */ 1065 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1066 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1067 NULL, tx_list_size, 1, tx_list_size, 0, 1068 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1069 if (error) { 1070 device_printf(dev, "could not allocate TX DMA ring tag\n"); 1071 return (error); 1072 } 1073 1074 /* Allocate DMA'able memory for the TX ring */ 1075 1076 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1077 (void **)&sc->rl_ldata.rl_tx_list, 1078 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1079 &sc->rl_ldata.rl_tx_list_map); 1080 if (error) { 1081 device_printf(dev, "could not allocate TX DMA ring\n"); 1082 return (error); 1083 } 1084 1085 /* Load the map for the TX ring. */ 1086 1087 sc->rl_ldata.rl_tx_list_addr = 0; 1088 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1089 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1090 tx_list_size, re_dma_map_addr, 1091 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1092 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 1093 device_printf(dev, "could not load TX DMA ring\n"); 1094 return (ENOMEM); 1095 } 1096 1097 /* Create DMA maps for TX buffers */ 1098 1099 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1100 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1101 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1102 if (error) { 1103 device_printf(dev, "could not create DMA map for TX\n"); 1104 return (error); 1105 } 1106 } 1107 1108 /* 1109 * Allocate map for RX descriptor list. 1110 */ 1111 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1112 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1113 NULL, rx_list_size, 1, rx_list_size, 0, 1114 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1115 if (error) { 1116 device_printf(dev, "could not create RX DMA ring tag\n"); 1117 return (error); 1118 } 1119 1120 /* Allocate DMA'able memory for the RX ring */ 1121 1122 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1123 (void **)&sc->rl_ldata.rl_rx_list, 1124 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1125 &sc->rl_ldata.rl_rx_list_map); 1126 if (error) { 1127 device_printf(dev, "could not allocate RX DMA ring\n"); 1128 return (error); 1129 } 1130 1131 /* Load the map for the RX ring. */ 1132 1133 sc->rl_ldata.rl_rx_list_addr = 0; 1134 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1135 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1136 rx_list_size, re_dma_map_addr, 1137 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1138 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1139 device_printf(dev, "could not load RX DMA ring\n"); 1140 return (ENOMEM); 1141 } 1142 1143 /* Create DMA maps for RX buffers */ 1144 1145 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 1146 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0, 1147 &sc->rl_ldata.rl_jrx_sparemap); 1148 if (error) { 1149 device_printf(dev, 1150 "could not create spare DMA map for jumbo RX\n"); 1151 return (error); 1152 } 1153 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1154 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0, 1155 &sc->rl_ldata.rl_jrx_desc[i].rx_dmamap); 1156 if (error) { 1157 device_printf(dev, 1158 "could not create DMA map for jumbo RX\n"); 1159 return (error); 1160 } 1161 } 1162 } 1163 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1164 &sc->rl_ldata.rl_rx_sparemap); 1165 if (error) { 1166 device_printf(dev, "could not create spare DMA map for RX\n"); 1167 return (error); 1168 } 1169 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1170 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1171 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1172 if (error) { 1173 device_printf(dev, "could not create DMA map for RX\n"); 1174 return (error); 1175 } 1176 } 1177 1178 /* Create DMA map for statistics. */ 1179 error = bus_dma_tag_create(sc->rl_parent_tag, RL_DUMP_ALIGN, 0, 1180 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1181 sizeof(struct rl_stats), 1, sizeof(struct rl_stats), 0, NULL, NULL, 1182 &sc->rl_ldata.rl_stag); 1183 if (error) { 1184 device_printf(dev, "could not create statistics DMA tag\n"); 1185 return (error); 1186 } 1187 /* Allocate DMA'able memory for statistics. */ 1188 error = bus_dmamem_alloc(sc->rl_ldata.rl_stag, 1189 (void **)&sc->rl_ldata.rl_stats, 1190 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1191 &sc->rl_ldata.rl_smap); 1192 if (error) { 1193 device_printf(dev, 1194 "could not allocate statistics DMA memory\n"); 1195 return (error); 1196 } 1197 /* Load the map for statistics. */ 1198 sc->rl_ldata.rl_stats_addr = 0; 1199 error = bus_dmamap_load(sc->rl_ldata.rl_stag, sc->rl_ldata.rl_smap, 1200 sc->rl_ldata.rl_stats, sizeof(struct rl_stats), re_dma_map_addr, 1201 &sc->rl_ldata.rl_stats_addr, BUS_DMA_NOWAIT); 1202 if (error != 0 || sc->rl_ldata.rl_stats_addr == 0) { 1203 device_printf(dev, "could not load statistics DMA memory\n"); 1204 return (ENOMEM); 1205 } 1206 1207 return (0); 1208 } 1209 1210 /* 1211 * Attach the interface. Allocate softc structures, do ifmedia 1212 * setup and ethernet/BPF attach. 1213 */ 1214 static int 1215 re_attach(device_t dev) 1216 { 1217 u_char eaddr[ETHER_ADDR_LEN]; 1218 u_int16_t as[ETHER_ADDR_LEN / 2]; 1219 struct rl_softc *sc; 1220 if_t ifp; 1221 const struct rl_hwrev *hw_rev; 1222 int capmask, error = 0, hwrev, i, msic, msixc, 1223 phy, reg, rid; 1224 u_int32_t cap, ctl; 1225 u_int16_t devid, re_did = 0; 1226 uint8_t cfg; 1227 1228 sc = device_get_softc(dev); 1229 sc->rl_dev = dev; 1230 1231 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1232 MTX_DEF); 1233 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1234 1235 /* 1236 * Map control/status registers. 1237 */ 1238 pci_enable_busmaster(dev); 1239 1240 devid = pci_get_device(dev); 1241 /* 1242 * Prefer memory space register mapping over IO space. 1243 * Because RTL8169SC does not seem to work when memory mapping 1244 * is used always activate io mapping. 1245 */ 1246 if (devid == RT_DEVICEID_8169SC) 1247 prefer_iomap = 1; 1248 if (prefer_iomap == 0) { 1249 sc->rl_res_id = PCIR_BAR(1); 1250 sc->rl_res_type = SYS_RES_MEMORY; 1251 /* RTL8168/8101E seems to use different BARs. */ 1252 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E) 1253 sc->rl_res_id = PCIR_BAR(2); 1254 } else { 1255 sc->rl_res_id = PCIR_BAR(0); 1256 sc->rl_res_type = SYS_RES_IOPORT; 1257 } 1258 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1259 &sc->rl_res_id, RF_ACTIVE); 1260 if (sc->rl_res == NULL && prefer_iomap == 0) { 1261 sc->rl_res_id = PCIR_BAR(0); 1262 sc->rl_res_type = SYS_RES_IOPORT; 1263 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1264 &sc->rl_res_id, RF_ACTIVE); 1265 } 1266 if (sc->rl_res == NULL) { 1267 device_printf(dev, "couldn't map ports/memory\n"); 1268 error = ENXIO; 1269 goto fail; 1270 } 1271 1272 sc->rl_btag = rman_get_bustag(sc->rl_res); 1273 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1274 1275 msic = pci_msi_count(dev); 1276 msixc = pci_msix_count(dev); 1277 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 1278 sc->rl_flags |= RL_FLAG_PCIE; 1279 sc->rl_expcap = reg; 1280 } 1281 if (bootverbose) { 1282 device_printf(dev, "MSI count : %d\n", msic); 1283 device_printf(dev, "MSI-X count : %d\n", msixc); 1284 } 1285 if (msix_disable > 0) 1286 msixc = 0; 1287 if (msi_disable > 0) 1288 msic = 0; 1289 /* Prefer MSI-X to MSI. */ 1290 if (msixc > 0) { 1291 msixc = RL_MSI_MESSAGES; 1292 rid = PCIR_BAR(4); 1293 sc->rl_res_pba = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1294 &rid, RF_ACTIVE); 1295 if (sc->rl_res_pba == NULL) { 1296 device_printf(sc->rl_dev, 1297 "could not allocate MSI-X PBA resource\n"); 1298 } 1299 if (sc->rl_res_pba != NULL && 1300 pci_alloc_msix(dev, &msixc) == 0) { 1301 if (msixc == RL_MSI_MESSAGES) { 1302 device_printf(dev, "Using %d MSI-X message\n", 1303 msixc); 1304 sc->rl_flags |= RL_FLAG_MSIX; 1305 } else 1306 pci_release_msi(dev); 1307 } 1308 if ((sc->rl_flags & RL_FLAG_MSIX) == 0) { 1309 if (sc->rl_res_pba != NULL) 1310 bus_release_resource(dev, SYS_RES_MEMORY, rid, 1311 sc->rl_res_pba); 1312 sc->rl_res_pba = NULL; 1313 msixc = 0; 1314 } 1315 } 1316 /* Prefer MSI to INTx. */ 1317 if (msixc == 0 && msic > 0) { 1318 msic = RL_MSI_MESSAGES; 1319 if (pci_alloc_msi(dev, &msic) == 0) { 1320 if (msic == RL_MSI_MESSAGES) { 1321 device_printf(dev, "Using %d MSI message\n", 1322 msic); 1323 sc->rl_flags |= RL_FLAG_MSI; 1324 /* Explicitly set MSI enable bit. */ 1325 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1326 cfg = CSR_READ_1(sc, RL_CFG2); 1327 cfg |= RL_CFG2_MSI; 1328 CSR_WRITE_1(sc, RL_CFG2, cfg); 1329 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1330 } else 1331 pci_release_msi(dev); 1332 } 1333 if ((sc->rl_flags & RL_FLAG_MSI) == 0) 1334 msic = 0; 1335 } 1336 1337 /* Allocate interrupt */ 1338 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) { 1339 rid = 0; 1340 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1341 RF_SHAREABLE | RF_ACTIVE); 1342 if (sc->rl_irq[0] == NULL) { 1343 device_printf(dev, "couldn't allocate IRQ resources\n"); 1344 error = ENXIO; 1345 goto fail; 1346 } 1347 } else { 1348 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1349 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1350 SYS_RES_IRQ, &rid, RF_ACTIVE); 1351 if (sc->rl_irq[i] == NULL) { 1352 device_printf(dev, 1353 "couldn't allocate IRQ resources for " 1354 "message %d\n", rid); 1355 error = ENXIO; 1356 goto fail; 1357 } 1358 } 1359 } 1360 1361 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1362 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1363 cfg = CSR_READ_1(sc, RL_CFG2); 1364 if ((cfg & RL_CFG2_MSI) != 0) { 1365 device_printf(dev, "turning off MSI enable bit.\n"); 1366 cfg &= ~RL_CFG2_MSI; 1367 CSR_WRITE_1(sc, RL_CFG2, cfg); 1368 } 1369 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1370 } 1371 1372 /* Disable ASPM L0S/L1 and CLKREQ. */ 1373 if (sc->rl_expcap != 0) { 1374 cap = pci_read_config(dev, sc->rl_expcap + 1375 PCIER_LINK_CAP, 2); 1376 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { 1377 ctl = pci_read_config(dev, sc->rl_expcap + 1378 PCIER_LINK_CTL, 2); 1379 if ((ctl & (PCIEM_LINK_CTL_ECPM | 1380 PCIEM_LINK_CTL_ASPMC))!= 0) { 1381 ctl &= ~(PCIEM_LINK_CTL_ECPM | 1382 PCIEM_LINK_CTL_ASPMC); 1383 pci_write_config(dev, sc->rl_expcap + 1384 PCIER_LINK_CTL, ctl, 2); 1385 device_printf(dev, "ASPM disabled\n"); 1386 } 1387 } else 1388 device_printf(dev, "no ASPM capability\n"); 1389 } 1390 1391 hw_rev = re_hwrevs; 1392 hwrev = CSR_READ_4(sc, RL_TXCFG); 1393 switch (hwrev & 0x70000000) { 1394 case 0x00000000: 1395 case 0x10000000: 1396 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000); 1397 hwrev &= (RL_TXCFG_HWREV | 0x80000000); 1398 break; 1399 default: 1400 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000); 1401 sc->rl_macrev = hwrev & 0x00700000; 1402 hwrev &= RL_TXCFG_HWREV; 1403 break; 1404 } 1405 device_printf(dev, "MAC rev. 0x%08x\n", sc->rl_macrev); 1406 while (hw_rev->rl_desc != NULL) { 1407 if (hw_rev->rl_rev == hwrev) { 1408 sc->rl_type = hw_rev->rl_type; 1409 sc->rl_hwrev = hw_rev; 1410 break; 1411 } 1412 hw_rev++; 1413 } 1414 if (hw_rev->rl_desc == NULL) { 1415 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev); 1416 error = ENXIO; 1417 goto fail; 1418 } 1419 1420 switch (hw_rev->rl_rev) { 1421 case RL_HWREV_8139CPLUS: 1422 sc->rl_flags |= RL_FLAG_FASTETHER | RL_FLAG_AUTOPAD; 1423 break; 1424 case RL_HWREV_8100E: 1425 case RL_HWREV_8101E: 1426 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_FASTETHER; 1427 break; 1428 case RL_HWREV_8102E: 1429 case RL_HWREV_8102EL: 1430 case RL_HWREV_8102EL_SPIN1: 1431 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1432 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | 1433 RL_FLAG_AUTOPAD; 1434 break; 1435 case RL_HWREV_8103E: 1436 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1437 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | 1438 RL_FLAG_AUTOPAD | RL_FLAG_MACSLEEP; 1439 break; 1440 case RL_HWREV_8401E: 1441 case RL_HWREV_8105E: 1442 case RL_HWREV_8105E_SPIN1: 1443 case RL_HWREV_8106E: 1444 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1445 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1446 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD; 1447 break; 1448 case RL_HWREV_8402: 1449 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1450 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1451 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | 1452 RL_FLAG_CMDSTOP_WAIT_TXQ; 1453 break; 1454 case RL_HWREV_8168B_SPIN1: 1455 case RL_HWREV_8168B_SPIN2: 1456 sc->rl_flags |= RL_FLAG_WOLRXENB; 1457 /* FALLTHROUGH */ 1458 case RL_HWREV_8168B_SPIN3: 1459 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT; 1460 break; 1461 case RL_HWREV_8168C_SPIN2: 1462 sc->rl_flags |= RL_FLAG_MACSLEEP; 1463 /* FALLTHROUGH */ 1464 case RL_HWREV_8168C: 1465 if (sc->rl_macrev == 0x00200000) 1466 sc->rl_flags |= RL_FLAG_MACSLEEP; 1467 /* FALLTHROUGH */ 1468 case RL_HWREV_8168CP: 1469 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1470 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1471 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK; 1472 break; 1473 case RL_HWREV_8168D: 1474 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1475 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1476 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1477 RL_FLAG_WOL_MANLINK; 1478 break; 1479 case RL_HWREV_8168DP: 1480 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1481 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_AUTOPAD | 1482 RL_FLAG_JUMBOV2 | RL_FLAG_WAIT_TXPOLL | RL_FLAG_WOL_MANLINK; 1483 break; 1484 case RL_HWREV_8168E: 1485 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1486 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1487 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1488 RL_FLAG_WOL_MANLINK; 1489 break; 1490 case RL_HWREV_8168E_VL: 1491 case RL_HWREV_8168F: 1492 sc->rl_flags |= RL_FLAG_EARLYOFF; 1493 /* FALLTHROUGH */ 1494 case RL_HWREV_8411: 1495 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1496 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1497 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1498 RL_FLAG_CMDSTOP_WAIT_TXQ | RL_FLAG_WOL_MANLINK; 1499 break; 1500 case RL_HWREV_8168EP: 1501 case RL_HWREV_8168FP: 1502 case RL_HWREV_8168G: 1503 case RL_HWREV_8411B: 1504 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1505 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1506 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1507 RL_FLAG_CMDSTOP_WAIT_TXQ | RL_FLAG_WOL_MANLINK | 1508 RL_FLAG_8168G_PLUS; 1509 break; 1510 case RL_HWREV_8168GU: 1511 case RL_HWREV_8168H: 1512 if (pci_get_device(dev) == RT_DEVICEID_8101E) { 1513 /* RTL8106E(US), RTL8107E */ 1514 sc->rl_flags |= RL_FLAG_FASTETHER; 1515 } else 1516 sc->rl_flags |= RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK; 1517 1518 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1519 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1520 RL_FLAG_AUTOPAD | RL_FLAG_CMDSTOP_WAIT_TXQ | 1521 RL_FLAG_8168G_PLUS; 1522 break; 1523 case RL_HWREV_8169_8110SB: 1524 case RL_HWREV_8169_8110SBL: 1525 case RL_HWREV_8169_8110SC: 1526 case RL_HWREV_8169_8110SCE: 1527 sc->rl_flags |= RL_FLAG_PHYWAKE; 1528 /* FALLTHROUGH */ 1529 case RL_HWREV_8169: 1530 case RL_HWREV_8169S: 1531 case RL_HWREV_8110S: 1532 sc->rl_flags |= RL_FLAG_MACRESET; 1533 break; 1534 default: 1535 break; 1536 } 1537 1538 if (sc->rl_hwrev->rl_rev == RL_HWREV_8139CPLUS) { 1539 sc->rl_cfg0 = RL_8139_CFG0; 1540 sc->rl_cfg1 = RL_8139_CFG1; 1541 sc->rl_cfg2 = 0; 1542 sc->rl_cfg3 = RL_8139_CFG3; 1543 sc->rl_cfg4 = RL_8139_CFG4; 1544 sc->rl_cfg5 = RL_8139_CFG5; 1545 } else { 1546 sc->rl_cfg0 = RL_CFG0; 1547 sc->rl_cfg1 = RL_CFG1; 1548 sc->rl_cfg2 = RL_CFG2; 1549 sc->rl_cfg3 = RL_CFG3; 1550 sc->rl_cfg4 = RL_CFG4; 1551 sc->rl_cfg5 = RL_CFG5; 1552 } 1553 1554 /* Reset the adapter. */ 1555 RL_LOCK(sc); 1556 re_reset(sc); 1557 RL_UNLOCK(sc); 1558 1559 /* Enable PME. */ 1560 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1561 cfg = CSR_READ_1(sc, sc->rl_cfg1); 1562 cfg |= RL_CFG1_PME; 1563 CSR_WRITE_1(sc, sc->rl_cfg1, cfg); 1564 cfg = CSR_READ_1(sc, sc->rl_cfg5); 1565 cfg &= RL_CFG5_PME_STS; 1566 CSR_WRITE_1(sc, sc->rl_cfg5, cfg); 1567 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1568 1569 if ((sc->rl_flags & RL_FLAG_PAR) != 0) { 1570 /* 1571 * XXX Should have a better way to extract station 1572 * address from EEPROM. 1573 */ 1574 for (i = 0; i < ETHER_ADDR_LEN; i++) 1575 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1576 } else { 1577 sc->rl_eewidth = RL_9356_ADDR_LEN; 1578 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1579 if (re_did != 0x8129) 1580 sc->rl_eewidth = RL_9346_ADDR_LEN; 1581 1582 /* 1583 * Get station address from the EEPROM. 1584 */ 1585 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1586 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1587 as[i] = le16toh(as[i]); 1588 bcopy(as, eaddr, ETHER_ADDR_LEN); 1589 } 1590 1591 if (sc->rl_type == RL_8169) { 1592 /* Set RX length mask and number of descriptors. */ 1593 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1594 sc->rl_txstart = RL_GTXSTART; 1595 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1596 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1597 } else { 1598 /* Set RX length mask and number of descriptors. */ 1599 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1600 sc->rl_txstart = RL_TXSTART; 1601 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1602 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1603 } 1604 1605 error = re_allocmem(dev, sc); 1606 if (error) 1607 goto fail; 1608 re_add_sysctls(sc); 1609 1610 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1611 1612 /* Take controller out of deep sleep mode. */ 1613 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 1614 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 1615 CSR_WRITE_1(sc, RL_GPIO, 1616 CSR_READ_1(sc, RL_GPIO) | 0x01); 1617 else 1618 CSR_WRITE_1(sc, RL_GPIO, 1619 CSR_READ_1(sc, RL_GPIO) & ~0x01); 1620 } 1621 1622 /* Take PHY out of power down mode. */ 1623 if ((sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) { 1624 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80); 1625 if (hw_rev->rl_rev == RL_HWREV_8401E) 1626 CSR_WRITE_1(sc, 0xD1, CSR_READ_1(sc, 0xD1) & ~0x08); 1627 } 1628 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) { 1629 re_gmii_writereg(dev, 1, 0x1f, 0); 1630 re_gmii_writereg(dev, 1, 0x0e, 0); 1631 } 1632 1633 if_setsoftc(ifp, sc); 1634 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1635 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 1636 if_setioctlfn(ifp, re_ioctl); 1637 if_setstartfn(ifp, re_start); 1638 /* 1639 * RTL8168/8111C generates wrong IP checksummed frame if the 1640 * packet has IP options so disable TX checksum offloading. 1641 */ 1642 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168C || 1643 sc->rl_hwrev->rl_rev == RL_HWREV_8168C_SPIN2 || 1644 sc->rl_hwrev->rl_rev == RL_HWREV_8168CP) { 1645 if_sethwassist(ifp, 0); 1646 if_setcapabilities(ifp, IFCAP_RXCSUM | IFCAP_TSO4); 1647 } else { 1648 if_sethwassist(ifp, CSUM_IP | CSUM_TCP | CSUM_UDP); 1649 if_setcapabilities(ifp, IFCAP_HWCSUM | IFCAP_TSO4); 1650 } 1651 if_sethwassistbits(ifp, CSUM_TSO, 0); 1652 if_setcapenable(ifp, if_getcapabilities(ifp)); 1653 if_setinitfn(ifp, re_init); 1654 if_setsendqlen(ifp, RL_IFQ_MAXLEN); 1655 if_setsendqready(ifp); 1656 1657 NET_TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1658 1659 #define RE_PHYAD_INTERNAL 0 1660 1661 /* Do MII setup. */ 1662 phy = RE_PHYAD_INTERNAL; 1663 if (sc->rl_type == RL_8169) 1664 phy = 1; 1665 capmask = BMSR_DEFCAPMASK; 1666 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0) 1667 capmask &= ~BMSR_EXTSTAT; 1668 error = mii_attach(dev, &sc->rl_miibus, ifp, re_ifmedia_upd, 1669 re_ifmedia_sts, capmask, phy, MII_OFFSET_ANY, MIIF_DOPAUSE); 1670 if (error != 0) { 1671 device_printf(dev, "attaching PHYs failed\n"); 1672 goto fail; 1673 } 1674 1675 /* If address was not found, create one based on the hostid and name. */ 1676 if (ETHER_IS_ZERO(eaddr)) { 1677 ether_gen_addr(ifp, (struct ether_addr *)eaddr); 1678 } 1679 1680 /* 1681 * Call MI attach routine. 1682 */ 1683 ether_ifattach(ifp, eaddr); 1684 1685 /* VLAN capability setup */ 1686 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING, 0); 1687 if (if_getcapabilities(ifp) & IFCAP_HWCSUM) 1688 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM, 0); 1689 /* Enable WOL if PM is supported. */ 1690 if (pci_has_pm(sc->rl_dev)) 1691 if_setcapabilitiesbit(ifp, IFCAP_WOL, 0); 1692 if_setcapenable(ifp, if_getcapabilities(ifp)); 1693 if_setcapenablebit(ifp, 0, (IFCAP_WOL_UCAST | IFCAP_WOL_MCAST)); 1694 /* 1695 * Don't enable TSO by default. It is known to generate 1696 * corrupted TCP segments(bad TCP options) under certain 1697 * circumstances. 1698 */ 1699 if_sethwassistbits(ifp, 0, CSUM_TSO); 1700 if_setcapenablebit(ifp, 0, (IFCAP_TSO4 | IFCAP_VLAN_HWTSO)); 1701 #ifdef DEVICE_POLLING 1702 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0); 1703 #endif 1704 /* 1705 * Tell the upper layer(s) we support long frames. 1706 * Must appear after the call to ether_ifattach() because 1707 * ether_ifattach() sets ifi_hdrlen to the default value. 1708 */ 1709 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 1710 1711 #ifdef DEV_NETMAP 1712 re_netmap_attach(sc); 1713 #endif /* DEV_NETMAP */ 1714 1715 #ifdef RE_DIAG 1716 /* 1717 * Perform hardware diagnostic on the original RTL8169. 1718 * Some 32-bit cards were incorrectly wired and would 1719 * malfunction if plugged into a 64-bit slot. 1720 */ 1721 if (hwrev == RL_HWREV_8169) { 1722 error = re_diag(sc); 1723 if (error) { 1724 device_printf(dev, 1725 "attach aborted due to hardware diag failure\n"); 1726 ether_ifdetach(ifp); 1727 goto fail; 1728 } 1729 } 1730 #endif 1731 1732 #ifdef RE_TX_MODERATION 1733 intr_filter = 1; 1734 #endif 1735 /* Hook interrupt last to avoid having to lock softc */ 1736 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 && 1737 intr_filter == 0) { 1738 error = bus_setup_intr(dev, sc->rl_irq[0], 1739 INTR_TYPE_NET | INTR_MPSAFE, NULL, re_intr_msi, sc, 1740 &sc->rl_intrhand[0]); 1741 } else { 1742 error = bus_setup_intr(dev, sc->rl_irq[0], 1743 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1744 &sc->rl_intrhand[0]); 1745 } 1746 if (error) { 1747 device_printf(dev, "couldn't set up irq\n"); 1748 ether_ifdetach(ifp); 1749 goto fail; 1750 } 1751 1752 DEBUGNET_SET(ifp, re); 1753 1754 fail: 1755 if (error) 1756 re_detach(dev); 1757 1758 return (error); 1759 } 1760 1761 /* 1762 * Shutdown hardware and free up resources. This can be called any 1763 * time after the mutex has been initialized. It is called in both 1764 * the error case in attach and the normal detach case so it needs 1765 * to be careful about only freeing resources that have actually been 1766 * allocated. 1767 */ 1768 static int 1769 re_detach(device_t dev) 1770 { 1771 struct rl_softc *sc; 1772 if_t ifp; 1773 int i, rid; 1774 1775 sc = device_get_softc(dev); 1776 ifp = sc->rl_ifp; 1777 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1778 1779 /* These should only be active if attach succeeded */ 1780 if (device_is_attached(dev)) { 1781 #ifdef DEVICE_POLLING 1782 if (if_getcapenable(ifp) & IFCAP_POLLING) 1783 ether_poll_deregister(ifp); 1784 #endif 1785 RL_LOCK(sc); 1786 #if 0 1787 sc->suspended = 1; 1788 #endif 1789 re_stop(sc); 1790 RL_UNLOCK(sc); 1791 callout_drain(&sc->rl_stat_callout); 1792 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1793 /* 1794 * Force off the IFF_UP flag here, in case someone 1795 * still had a BPF descriptor attached to this 1796 * interface. If they do, ether_ifdetach() will cause 1797 * the BPF code to try and clear the promisc mode 1798 * flag, which will bubble down to re_ioctl(), 1799 * which will try to call re_init() again. This will 1800 * turn the NIC back on and restart the MII ticker, 1801 * which will panic the system when the kernel tries 1802 * to invoke the re_tick() function that isn't there 1803 * anymore. 1804 */ 1805 if_setflagbits(ifp, 0, IFF_UP); 1806 ether_ifdetach(ifp); 1807 } 1808 bus_generic_detach(dev); 1809 1810 /* 1811 * The rest is resource deallocation, so we should already be 1812 * stopped here. 1813 */ 1814 1815 if (sc->rl_intrhand[0] != NULL) { 1816 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]); 1817 sc->rl_intrhand[0] = NULL; 1818 } 1819 if (ifp != NULL) { 1820 #ifdef DEV_NETMAP 1821 netmap_detach(ifp); 1822 #endif /* DEV_NETMAP */ 1823 if_free(ifp); 1824 } 1825 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) 1826 rid = 0; 1827 else 1828 rid = 1; 1829 if (sc->rl_irq[0] != NULL) { 1830 bus_release_resource(dev, SYS_RES_IRQ, rid, sc->rl_irq[0]); 1831 sc->rl_irq[0] = NULL; 1832 } 1833 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0) 1834 pci_release_msi(dev); 1835 if (sc->rl_res_pba) { 1836 rid = PCIR_BAR(4); 1837 bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->rl_res_pba); 1838 } 1839 if (sc->rl_res) 1840 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, 1841 sc->rl_res); 1842 1843 /* Unload and free the RX DMA ring memory and map */ 1844 1845 if (sc->rl_ldata.rl_rx_list_tag) { 1846 if (sc->rl_ldata.rl_rx_list_addr) 1847 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1848 sc->rl_ldata.rl_rx_list_map); 1849 if (sc->rl_ldata.rl_rx_list) 1850 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1851 sc->rl_ldata.rl_rx_list, 1852 sc->rl_ldata.rl_rx_list_map); 1853 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1854 } 1855 1856 /* Unload and free the TX DMA ring memory and map */ 1857 1858 if (sc->rl_ldata.rl_tx_list_tag) { 1859 if (sc->rl_ldata.rl_tx_list_addr) 1860 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1861 sc->rl_ldata.rl_tx_list_map); 1862 if (sc->rl_ldata.rl_tx_list) 1863 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1864 sc->rl_ldata.rl_tx_list, 1865 sc->rl_ldata.rl_tx_list_map); 1866 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1867 } 1868 1869 /* Destroy all the RX and TX buffer maps */ 1870 1871 if (sc->rl_ldata.rl_tx_mtag) { 1872 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1873 if (sc->rl_ldata.rl_tx_desc[i].tx_dmamap) 1874 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1875 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1876 } 1877 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1878 } 1879 if (sc->rl_ldata.rl_rx_mtag) { 1880 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1881 if (sc->rl_ldata.rl_rx_desc[i].rx_dmamap) 1882 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1883 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1884 } 1885 if (sc->rl_ldata.rl_rx_sparemap) 1886 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1887 sc->rl_ldata.rl_rx_sparemap); 1888 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1889 } 1890 if (sc->rl_ldata.rl_jrx_mtag) { 1891 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1892 if (sc->rl_ldata.rl_jrx_desc[i].rx_dmamap) 1893 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag, 1894 sc->rl_ldata.rl_jrx_desc[i].rx_dmamap); 1895 } 1896 if (sc->rl_ldata.rl_jrx_sparemap) 1897 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag, 1898 sc->rl_ldata.rl_jrx_sparemap); 1899 bus_dma_tag_destroy(sc->rl_ldata.rl_jrx_mtag); 1900 } 1901 /* Unload and free the stats buffer and map */ 1902 1903 if (sc->rl_ldata.rl_stag) { 1904 if (sc->rl_ldata.rl_stats_addr) 1905 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1906 sc->rl_ldata.rl_smap); 1907 if (sc->rl_ldata.rl_stats) 1908 bus_dmamem_free(sc->rl_ldata.rl_stag, 1909 sc->rl_ldata.rl_stats, sc->rl_ldata.rl_smap); 1910 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1911 } 1912 1913 if (sc->rl_parent_tag) 1914 bus_dma_tag_destroy(sc->rl_parent_tag); 1915 1916 mtx_destroy(&sc->rl_mtx); 1917 1918 return (0); 1919 } 1920 1921 static __inline void 1922 re_discard_rxbuf(struct rl_softc *sc, int idx) 1923 { 1924 struct rl_desc *desc; 1925 struct rl_rxdesc *rxd; 1926 uint32_t cmdstat; 1927 1928 if (if_getmtu(sc->rl_ifp) > RL_MTU && 1929 (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) 1930 rxd = &sc->rl_ldata.rl_jrx_desc[idx]; 1931 else 1932 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1933 desc = &sc->rl_ldata.rl_rx_list[idx]; 1934 desc->rl_vlanctl = 0; 1935 cmdstat = rxd->rx_size; 1936 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1937 cmdstat |= RL_RDESC_CMD_EOR; 1938 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1939 } 1940 1941 static int 1942 re_newbuf(struct rl_softc *sc, int idx) 1943 { 1944 struct mbuf *m; 1945 struct rl_rxdesc *rxd; 1946 bus_dma_segment_t segs[1]; 1947 bus_dmamap_t map; 1948 struct rl_desc *desc; 1949 uint32_t cmdstat; 1950 int error, nsegs; 1951 1952 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1953 if (m == NULL) 1954 return (ENOBUFS); 1955 1956 m->m_len = m->m_pkthdr.len = MCLBYTES; 1957 #ifdef RE_FIXUP_RX 1958 /* 1959 * This is part of an evil trick to deal with non-x86 platforms. 1960 * The RealTek chip requires RX buffers to be aligned on 64-bit 1961 * boundaries, but that will hose non-x86 machines. To get around 1962 * this, we leave some empty space at the start of each buffer 1963 * and for non-x86 hosts, we copy the buffer back six bytes 1964 * to achieve word alignment. This is slightly more efficient 1965 * than allocating a new buffer, copying the contents, and 1966 * discarding the old buffer. 1967 */ 1968 m_adj(m, RE_ETHER_ALIGN); 1969 #endif 1970 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1971 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1972 if (error != 0) { 1973 m_freem(m); 1974 return (ENOBUFS); 1975 } 1976 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1977 1978 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1979 if (rxd->rx_m != NULL) { 1980 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1981 BUS_DMASYNC_POSTREAD); 1982 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1983 } 1984 1985 rxd->rx_m = m; 1986 map = rxd->rx_dmamap; 1987 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1988 rxd->rx_size = segs[0].ds_len; 1989 sc->rl_ldata.rl_rx_sparemap = map; 1990 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1991 BUS_DMASYNC_PREREAD); 1992 1993 desc = &sc->rl_ldata.rl_rx_list[idx]; 1994 desc->rl_vlanctl = 0; 1995 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1996 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1997 cmdstat = segs[0].ds_len; 1998 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1999 cmdstat |= RL_RDESC_CMD_EOR; 2000 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 2001 2002 return (0); 2003 } 2004 2005 static int 2006 re_jumbo_newbuf(struct rl_softc *sc, int idx) 2007 { 2008 struct mbuf *m; 2009 struct rl_rxdesc *rxd; 2010 bus_dma_segment_t segs[1]; 2011 bus_dmamap_t map; 2012 struct rl_desc *desc; 2013 uint32_t cmdstat; 2014 int error, nsegs; 2015 2016 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 2017 if (m == NULL) 2018 return (ENOBUFS); 2019 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 2020 #ifdef RE_FIXUP_RX 2021 m_adj(m, RE_ETHER_ALIGN); 2022 #endif 2023 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_jrx_mtag, 2024 sc->rl_ldata.rl_jrx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 2025 if (error != 0) { 2026 m_freem(m); 2027 return (ENOBUFS); 2028 } 2029 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 2030 2031 rxd = &sc->rl_ldata.rl_jrx_desc[idx]; 2032 if (rxd->rx_m != NULL) { 2033 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap, 2034 BUS_DMASYNC_POSTREAD); 2035 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap); 2036 } 2037 2038 rxd->rx_m = m; 2039 map = rxd->rx_dmamap; 2040 rxd->rx_dmamap = sc->rl_ldata.rl_jrx_sparemap; 2041 rxd->rx_size = segs[0].ds_len; 2042 sc->rl_ldata.rl_jrx_sparemap = map; 2043 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap, 2044 BUS_DMASYNC_PREREAD); 2045 2046 desc = &sc->rl_ldata.rl_rx_list[idx]; 2047 desc->rl_vlanctl = 0; 2048 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 2049 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 2050 cmdstat = segs[0].ds_len; 2051 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 2052 cmdstat |= RL_RDESC_CMD_EOR; 2053 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 2054 2055 return (0); 2056 } 2057 2058 #ifdef RE_FIXUP_RX 2059 static __inline void 2060 re_fixup_rx(struct mbuf *m) 2061 { 2062 int i; 2063 uint16_t *src, *dst; 2064 2065 src = mtod(m, uint16_t *); 2066 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 2067 2068 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 2069 *dst++ = *src++; 2070 2071 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 2072 } 2073 #endif 2074 2075 static int 2076 re_tx_list_init(struct rl_softc *sc) 2077 { 2078 struct rl_desc *desc; 2079 int i; 2080 2081 RL_LOCK_ASSERT(sc); 2082 2083 bzero(sc->rl_ldata.rl_tx_list, 2084 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 2085 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 2086 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 2087 #ifdef DEV_NETMAP 2088 re_netmap_tx_init(sc); 2089 #endif /* DEV_NETMAP */ 2090 /* Set EOR. */ 2091 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 2092 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 2093 2094 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2095 sc->rl_ldata.rl_tx_list_map, 2096 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2097 2098 sc->rl_ldata.rl_tx_prodidx = 0; 2099 sc->rl_ldata.rl_tx_considx = 0; 2100 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 2101 2102 return (0); 2103 } 2104 2105 static int 2106 re_rx_list_init(struct rl_softc *sc) 2107 { 2108 int error, i; 2109 2110 bzero(sc->rl_ldata.rl_rx_list, 2111 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 2112 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2113 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 2114 if ((error = re_newbuf(sc, i)) != 0) 2115 return (error); 2116 } 2117 #ifdef DEV_NETMAP 2118 re_netmap_rx_init(sc); 2119 #endif /* DEV_NETMAP */ 2120 2121 /* Flush the RX descriptors */ 2122 2123 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2124 sc->rl_ldata.rl_rx_list_map, 2125 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2126 2127 sc->rl_ldata.rl_rx_prodidx = 0; 2128 sc->rl_head = sc->rl_tail = NULL; 2129 sc->rl_int_rx_act = 0; 2130 2131 return (0); 2132 } 2133 2134 static int 2135 re_jrx_list_init(struct rl_softc *sc) 2136 { 2137 int error, i; 2138 2139 bzero(sc->rl_ldata.rl_rx_list, 2140 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 2141 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2142 sc->rl_ldata.rl_jrx_desc[i].rx_m = NULL; 2143 if ((error = re_jumbo_newbuf(sc, i)) != 0) 2144 return (error); 2145 } 2146 2147 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2148 sc->rl_ldata.rl_rx_list_map, 2149 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2150 2151 sc->rl_ldata.rl_rx_prodidx = 0; 2152 sc->rl_head = sc->rl_tail = NULL; 2153 sc->rl_int_rx_act = 0; 2154 2155 return (0); 2156 } 2157 2158 /* 2159 * RX handler for C+ and 8169. For the gigE chips, we support 2160 * the reception of jumbo frames that have been fragmented 2161 * across multiple 2K mbuf cluster buffers. 2162 */ 2163 static int 2164 re_rxeof(struct rl_softc *sc, int *rx_npktsp) 2165 { 2166 struct mbuf *m; 2167 if_t ifp; 2168 int i, rxerr, total_len; 2169 struct rl_desc *cur_rx; 2170 u_int32_t rxstat, rxvlan; 2171 int jumbo, maxpkt = 16, rx_npkts = 0; 2172 2173 RL_LOCK_ASSERT(sc); 2174 2175 ifp = sc->rl_ifp; 2176 #ifdef DEV_NETMAP 2177 if (netmap_rx_irq(ifp, 0, &rx_npkts)) 2178 return 0; 2179 #endif /* DEV_NETMAP */ 2180 if (if_getmtu(ifp) > RL_MTU && (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) 2181 jumbo = 1; 2182 else 2183 jumbo = 0; 2184 2185 /* Invalidate the descriptor memory */ 2186 2187 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2188 sc->rl_ldata.rl_rx_list_map, 2189 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2190 2191 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 2192 i = RL_RX_DESC_NXT(sc, i)) { 2193 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 2194 break; 2195 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 2196 rxstat = le32toh(cur_rx->rl_cmdstat); 2197 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 2198 break; 2199 total_len = rxstat & sc->rl_rxlenmask; 2200 rxvlan = le32toh(cur_rx->rl_vlanctl); 2201 if (jumbo != 0) 2202 m = sc->rl_ldata.rl_jrx_desc[i].rx_m; 2203 else 2204 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 2205 2206 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 2207 (rxstat & (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) != 2208 (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) { 2209 /* 2210 * RTL8168C or later controllers do not 2211 * support multi-fragment packet. 2212 */ 2213 re_discard_rxbuf(sc, i); 2214 continue; 2215 } else if ((rxstat & RL_RDESC_STAT_EOF) == 0) { 2216 if (re_newbuf(sc, i) != 0) { 2217 /* 2218 * If this is part of a multi-fragment packet, 2219 * discard all the pieces. 2220 */ 2221 if (sc->rl_head != NULL) { 2222 m_freem(sc->rl_head); 2223 sc->rl_head = sc->rl_tail = NULL; 2224 } 2225 re_discard_rxbuf(sc, i); 2226 continue; 2227 } 2228 m->m_len = RE_RX_DESC_BUFLEN; 2229 if (sc->rl_head == NULL) 2230 sc->rl_head = sc->rl_tail = m; 2231 else { 2232 m->m_flags &= ~M_PKTHDR; 2233 sc->rl_tail->m_next = m; 2234 sc->rl_tail = m; 2235 } 2236 continue; 2237 } 2238 2239 /* 2240 * NOTE: for the 8139C+, the frame length field 2241 * is always 12 bits in size, but for the gigE chips, 2242 * it is 13 bits (since the max RX frame length is 16K). 2243 * Unfortunately, all 32 bits in the status word 2244 * were already used, so to make room for the extra 2245 * length bit, RealTek took out the 'frame alignment 2246 * error' bit and shifted the other status bits 2247 * over one slot. The OWN, EOR, FS and LS bits are 2248 * still in the same places. We have already extracted 2249 * the frame length and checked the OWN bit, so rather 2250 * than using an alternate bit mapping, we shift the 2251 * status bits one space to the right so we can evaluate 2252 * them using the 8169 status as though it was in the 2253 * same format as that of the 8139C+. 2254 */ 2255 if (sc->rl_type == RL_8169) 2256 rxstat >>= 1; 2257 2258 /* 2259 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 2260 * set, but if CRC is clear, it will still be a valid frame. 2261 */ 2262 if ((rxstat & RL_RDESC_STAT_RXERRSUM) != 0) { 2263 rxerr = 1; 2264 if ((sc->rl_flags & RL_FLAG_JUMBOV2) == 0 && 2265 total_len > 8191 && 2266 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT) 2267 rxerr = 0; 2268 if (rxerr != 0) { 2269 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2270 /* 2271 * If this is part of a multi-fragment packet, 2272 * discard all the pieces. 2273 */ 2274 if (sc->rl_head != NULL) { 2275 m_freem(sc->rl_head); 2276 sc->rl_head = sc->rl_tail = NULL; 2277 } 2278 re_discard_rxbuf(sc, i); 2279 continue; 2280 } 2281 } 2282 2283 /* 2284 * If allocating a replacement mbuf fails, 2285 * reload the current one. 2286 */ 2287 if (jumbo != 0) 2288 rxerr = re_jumbo_newbuf(sc, i); 2289 else 2290 rxerr = re_newbuf(sc, i); 2291 if (rxerr != 0) { 2292 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2293 if (sc->rl_head != NULL) { 2294 m_freem(sc->rl_head); 2295 sc->rl_head = sc->rl_tail = NULL; 2296 } 2297 re_discard_rxbuf(sc, i); 2298 continue; 2299 } 2300 2301 if (sc->rl_head != NULL) { 2302 if (jumbo != 0) 2303 m->m_len = total_len; 2304 else { 2305 m->m_len = total_len % RE_RX_DESC_BUFLEN; 2306 if (m->m_len == 0) 2307 m->m_len = RE_RX_DESC_BUFLEN; 2308 } 2309 /* 2310 * Special case: if there's 4 bytes or less 2311 * in this buffer, the mbuf can be discarded: 2312 * the last 4 bytes is the CRC, which we don't 2313 * care about anyway. 2314 */ 2315 if (m->m_len <= ETHER_CRC_LEN) { 2316 sc->rl_tail->m_len -= 2317 (ETHER_CRC_LEN - m->m_len); 2318 m_freem(m); 2319 } else { 2320 m->m_len -= ETHER_CRC_LEN; 2321 m->m_flags &= ~M_PKTHDR; 2322 sc->rl_tail->m_next = m; 2323 } 2324 m = sc->rl_head; 2325 sc->rl_head = sc->rl_tail = NULL; 2326 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 2327 } else 2328 m->m_pkthdr.len = m->m_len = 2329 (total_len - ETHER_CRC_LEN); 2330 2331 #ifdef RE_FIXUP_RX 2332 re_fixup_rx(m); 2333 #endif 2334 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 2335 m->m_pkthdr.rcvif = ifp; 2336 2337 /* Do RX checksumming if enabled */ 2338 2339 if (if_getcapenable(ifp) & IFCAP_RXCSUM) { 2340 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2341 /* Check IP header checksum */ 2342 if (rxstat & RL_RDESC_STAT_PROTOID) 2343 m->m_pkthdr.csum_flags |= 2344 CSUM_IP_CHECKED; 2345 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 2346 m->m_pkthdr.csum_flags |= 2347 CSUM_IP_VALID; 2348 2349 /* Check TCP/UDP checksum */ 2350 if ((RL_TCPPKT(rxstat) && 2351 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 2352 (RL_UDPPKT(rxstat) && 2353 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 2354 m->m_pkthdr.csum_flags |= 2355 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2356 m->m_pkthdr.csum_data = 0xffff; 2357 } 2358 } else { 2359 /* 2360 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP 2361 */ 2362 if ((rxstat & RL_RDESC_STAT_PROTOID) && 2363 (rxvlan & RL_RDESC_IPV4)) 2364 m->m_pkthdr.csum_flags |= 2365 CSUM_IP_CHECKED; 2366 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) && 2367 (rxvlan & RL_RDESC_IPV4)) 2368 m->m_pkthdr.csum_flags |= 2369 CSUM_IP_VALID; 2370 if (((rxstat & RL_RDESC_STAT_TCP) && 2371 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 2372 ((rxstat & RL_RDESC_STAT_UDP) && 2373 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 2374 m->m_pkthdr.csum_flags |= 2375 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2376 m->m_pkthdr.csum_data = 0xffff; 2377 } 2378 } 2379 } 2380 maxpkt--; 2381 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 2382 m->m_pkthdr.ether_vtag = 2383 bswap16((rxvlan & RL_RDESC_VLANCTL_DATA)); 2384 m->m_flags |= M_VLANTAG; 2385 } 2386 RL_UNLOCK(sc); 2387 if_input(ifp, m); 2388 RL_LOCK(sc); 2389 rx_npkts++; 2390 } 2391 2392 /* Flush the RX DMA ring */ 2393 2394 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2395 sc->rl_ldata.rl_rx_list_map, 2396 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2397 2398 sc->rl_ldata.rl_rx_prodidx = i; 2399 2400 if (rx_npktsp != NULL) 2401 *rx_npktsp = rx_npkts; 2402 if (maxpkt) 2403 return (EAGAIN); 2404 2405 return (0); 2406 } 2407 2408 static void 2409 re_txeof(struct rl_softc *sc) 2410 { 2411 if_t ifp; 2412 struct rl_txdesc *txd; 2413 u_int32_t txstat; 2414 int cons; 2415 2416 cons = sc->rl_ldata.rl_tx_considx; 2417 if (cons == sc->rl_ldata.rl_tx_prodidx) 2418 return; 2419 2420 ifp = sc->rl_ifp; 2421 #ifdef DEV_NETMAP 2422 if (netmap_tx_irq(ifp, 0)) 2423 return; 2424 #endif /* DEV_NETMAP */ 2425 /* Invalidate the TX descriptor list */ 2426 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2427 sc->rl_ldata.rl_tx_list_map, 2428 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2429 2430 for (; cons != sc->rl_ldata.rl_tx_prodidx; 2431 cons = RL_TX_DESC_NXT(sc, cons)) { 2432 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 2433 if (txstat & RL_TDESC_STAT_OWN) 2434 break; 2435 /* 2436 * We only stash mbufs in the last descriptor 2437 * in a fragment chain, which also happens to 2438 * be the only place where the TX status bits 2439 * are valid. 2440 */ 2441 if (txstat & RL_TDESC_CMD_EOF) { 2442 txd = &sc->rl_ldata.rl_tx_desc[cons]; 2443 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2444 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2445 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2446 txd->tx_dmamap); 2447 KASSERT(txd->tx_m != NULL, 2448 ("%s: freeing NULL mbufs!", __func__)); 2449 m_freem(txd->tx_m); 2450 txd->tx_m = NULL; 2451 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 2452 RL_TDESC_STAT_COLCNT)) 2453 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 2454 if (txstat & RL_TDESC_STAT_TXERRSUM) 2455 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2456 else 2457 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 2458 } 2459 sc->rl_ldata.rl_tx_free++; 2460 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2461 } 2462 sc->rl_ldata.rl_tx_considx = cons; 2463 2464 /* No changes made to the TX ring, so no flush needed */ 2465 2466 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 2467 #ifdef RE_TX_MODERATION 2468 /* 2469 * If not all descriptors have been reaped yet, reload 2470 * the timer so that we will eventually get another 2471 * interrupt that will cause us to re-enter this routine. 2472 * This is done in case the transmitter has gone idle. 2473 */ 2474 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2475 #endif 2476 } else 2477 sc->rl_watchdog_timer = 0; 2478 } 2479 2480 static void 2481 re_tick(void *xsc) 2482 { 2483 struct rl_softc *sc; 2484 struct mii_data *mii; 2485 2486 sc = xsc; 2487 2488 RL_LOCK_ASSERT(sc); 2489 2490 mii = device_get_softc(sc->rl_miibus); 2491 mii_tick(mii); 2492 if ((sc->rl_flags & RL_FLAG_LINK) == 0) 2493 re_miibus_statchg(sc->rl_dev); 2494 /* 2495 * Reclaim transmitted frames here. Technically it is not 2496 * necessary to do here but it ensures periodic reclamation 2497 * regardless of Tx completion interrupt which seems to be 2498 * lost on PCIe based controllers under certain situations. 2499 */ 2500 re_txeof(sc); 2501 re_watchdog(sc); 2502 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2503 } 2504 2505 #ifdef DEVICE_POLLING 2506 static int 2507 re_poll(if_t ifp, enum poll_cmd cmd, int count) 2508 { 2509 struct rl_softc *sc = if_getsoftc(ifp); 2510 int rx_npkts = 0; 2511 2512 RL_LOCK(sc); 2513 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 2514 rx_npkts = re_poll_locked(ifp, cmd, count); 2515 RL_UNLOCK(sc); 2516 return (rx_npkts); 2517 } 2518 2519 static int 2520 re_poll_locked(if_t ifp, enum poll_cmd cmd, int count) 2521 { 2522 struct rl_softc *sc = if_getsoftc(ifp); 2523 int rx_npkts; 2524 2525 RL_LOCK_ASSERT(sc); 2526 2527 sc->rxcycles = count; 2528 re_rxeof(sc, &rx_npkts); 2529 re_txeof(sc); 2530 2531 if (!if_sendq_empty(ifp)) 2532 re_start_locked(ifp); 2533 2534 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2535 u_int16_t status; 2536 2537 status = CSR_READ_2(sc, RL_ISR); 2538 if (status == 0xffff) 2539 return (rx_npkts); 2540 if (status) 2541 CSR_WRITE_2(sc, RL_ISR, status); 2542 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2543 (sc->rl_flags & RL_FLAG_PCIE)) 2544 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2545 2546 /* 2547 * XXX check behaviour on receiver stalls. 2548 */ 2549 2550 if (status & RL_ISR_SYSTEM_ERR) { 2551 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2552 re_init_locked(sc); 2553 } 2554 } 2555 return (rx_npkts); 2556 } 2557 #endif /* DEVICE_POLLING */ 2558 2559 static int 2560 re_intr(void *arg) 2561 { 2562 struct rl_softc *sc; 2563 uint16_t status; 2564 2565 sc = arg; 2566 2567 status = CSR_READ_2(sc, RL_ISR); 2568 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2569 return (FILTER_STRAY); 2570 CSR_WRITE_2(sc, RL_IMR, 0); 2571 2572 taskqueue_enqueue(taskqueue_fast, &sc->rl_inttask); 2573 2574 return (FILTER_HANDLED); 2575 } 2576 2577 static void 2578 re_int_task(void *arg, int npending) 2579 { 2580 struct rl_softc *sc; 2581 if_t ifp; 2582 u_int16_t status; 2583 int rval = 0; 2584 2585 sc = arg; 2586 ifp = sc->rl_ifp; 2587 2588 RL_LOCK(sc); 2589 2590 status = CSR_READ_2(sc, RL_ISR); 2591 CSR_WRITE_2(sc, RL_ISR, status); 2592 2593 if (sc->suspended || 2594 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 2595 RL_UNLOCK(sc); 2596 return; 2597 } 2598 2599 #ifdef DEVICE_POLLING 2600 if (if_getcapenable(ifp) & IFCAP_POLLING) { 2601 RL_UNLOCK(sc); 2602 return; 2603 } 2604 #endif 2605 2606 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2607 rval = re_rxeof(sc, NULL); 2608 2609 /* 2610 * Some chips will ignore a second TX request issued 2611 * while an existing transmission is in progress. If 2612 * the transmitter goes idle but there are still 2613 * packets waiting to be sent, we need to restart the 2614 * channel here to flush them out. This only seems to 2615 * be required with the PCIe devices. 2616 */ 2617 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2618 (sc->rl_flags & RL_FLAG_PCIE)) 2619 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2620 if (status & ( 2621 #ifdef RE_TX_MODERATION 2622 RL_ISR_TIMEOUT_EXPIRED| 2623 #else 2624 RL_ISR_TX_OK| 2625 #endif 2626 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2627 re_txeof(sc); 2628 2629 if (status & RL_ISR_SYSTEM_ERR) { 2630 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2631 re_init_locked(sc); 2632 } 2633 2634 if (!if_sendq_empty(ifp)) 2635 re_start_locked(ifp); 2636 2637 RL_UNLOCK(sc); 2638 2639 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2640 taskqueue_enqueue(taskqueue_fast, &sc->rl_inttask); 2641 return; 2642 } 2643 2644 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2645 } 2646 2647 static void 2648 re_intr_msi(void *xsc) 2649 { 2650 struct rl_softc *sc; 2651 if_t ifp; 2652 uint16_t intrs, status; 2653 2654 sc = xsc; 2655 RL_LOCK(sc); 2656 2657 ifp = sc->rl_ifp; 2658 #ifdef DEVICE_POLLING 2659 if (if_getcapenable(ifp) & IFCAP_POLLING) { 2660 RL_UNLOCK(sc); 2661 return; 2662 } 2663 #endif 2664 /* Disable interrupts. */ 2665 CSR_WRITE_2(sc, RL_IMR, 0); 2666 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 2667 RL_UNLOCK(sc); 2668 return; 2669 } 2670 2671 intrs = RL_INTRS_CPLUS; 2672 status = CSR_READ_2(sc, RL_ISR); 2673 CSR_WRITE_2(sc, RL_ISR, status); 2674 if (sc->rl_int_rx_act > 0) { 2675 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW | 2676 RL_ISR_RX_OVERRUN); 2677 status &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW | 2678 RL_ISR_RX_OVERRUN); 2679 } 2680 2681 if (status & (RL_ISR_TIMEOUT_EXPIRED | RL_ISR_RX_OK | RL_ISR_RX_ERR | 2682 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) { 2683 re_rxeof(sc, NULL); 2684 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2685 if (sc->rl_int_rx_mod != 0 && 2686 (status & (RL_ISR_RX_OK | RL_ISR_RX_ERR | 2687 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) != 0) { 2688 /* Rearm one-shot timer. */ 2689 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2690 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | 2691 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN); 2692 sc->rl_int_rx_act = 1; 2693 } else { 2694 intrs |= RL_ISR_RX_OK | RL_ISR_RX_ERR | 2695 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN; 2696 sc->rl_int_rx_act = 0; 2697 } 2698 } 2699 } 2700 2701 /* 2702 * Some chips will ignore a second TX request issued 2703 * while an existing transmission is in progress. If 2704 * the transmitter goes idle but there are still 2705 * packets waiting to be sent, we need to restart the 2706 * channel here to flush them out. This only seems to 2707 * be required with the PCIe devices. 2708 */ 2709 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2710 (sc->rl_flags & RL_FLAG_PCIE)) 2711 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2712 if (status & (RL_ISR_TX_OK | RL_ISR_TX_ERR | RL_ISR_TX_DESC_UNAVAIL)) 2713 re_txeof(sc); 2714 2715 if (status & RL_ISR_SYSTEM_ERR) { 2716 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2717 re_init_locked(sc); 2718 } 2719 2720 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2721 if (!if_sendq_empty(ifp)) 2722 re_start_locked(ifp); 2723 CSR_WRITE_2(sc, RL_IMR, intrs); 2724 } 2725 RL_UNLOCK(sc); 2726 } 2727 2728 static int 2729 re_encap(struct rl_softc *sc, struct mbuf **m_head) 2730 { 2731 struct rl_txdesc *txd, *txd_last; 2732 bus_dma_segment_t segs[RL_NTXSEGS]; 2733 bus_dmamap_t map; 2734 struct mbuf *m_new; 2735 struct rl_desc *desc; 2736 int nsegs, prod; 2737 int i, error, ei, si; 2738 int padlen; 2739 uint32_t cmdstat, csum_flags, vlanctl; 2740 2741 RL_LOCK_ASSERT(sc); 2742 M_ASSERTPKTHDR((*m_head)); 2743 2744 /* 2745 * With some of the RealTek chips, using the checksum offload 2746 * support in conjunction with the autopadding feature results 2747 * in the transmission of corrupt frames. For example, if we 2748 * need to send a really small IP fragment that's less than 60 2749 * bytes in size, and IP header checksumming is enabled, the 2750 * resulting ethernet frame that appears on the wire will 2751 * have garbled payload. To work around this, if TX IP checksum 2752 * offload is enabled, we always manually pad short frames out 2753 * to the minimum ethernet frame size. 2754 */ 2755 if ((sc->rl_flags & RL_FLAG_AUTOPAD) == 0 && 2756 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN && 2757 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) { 2758 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2759 if (M_WRITABLE(*m_head) == 0) { 2760 /* Get a writable copy. */ 2761 m_new = m_dup(*m_head, M_NOWAIT); 2762 m_freem(*m_head); 2763 if (m_new == NULL) { 2764 *m_head = NULL; 2765 return (ENOBUFS); 2766 } 2767 *m_head = m_new; 2768 } 2769 if ((*m_head)->m_next != NULL || 2770 M_TRAILINGSPACE(*m_head) < padlen) { 2771 m_new = m_defrag(*m_head, M_NOWAIT); 2772 if (m_new == NULL) { 2773 m_freem(*m_head); 2774 *m_head = NULL; 2775 return (ENOBUFS); 2776 } 2777 } else 2778 m_new = *m_head; 2779 2780 /* 2781 * Manually pad short frames, and zero the pad space 2782 * to avoid leaking data. 2783 */ 2784 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2785 m_new->m_pkthdr.len += padlen; 2786 m_new->m_len = m_new->m_pkthdr.len; 2787 *m_head = m_new; 2788 } 2789 2790 prod = sc->rl_ldata.rl_tx_prodidx; 2791 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2792 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2793 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2794 if (error == EFBIG) { 2795 m_new = m_collapse(*m_head, M_NOWAIT, RL_NTXSEGS); 2796 if (m_new == NULL) { 2797 m_freem(*m_head); 2798 *m_head = NULL; 2799 return (ENOBUFS); 2800 } 2801 *m_head = m_new; 2802 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2803 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2804 if (error != 0) { 2805 m_freem(*m_head); 2806 *m_head = NULL; 2807 return (error); 2808 } 2809 } else if (error != 0) 2810 return (error); 2811 if (nsegs == 0) { 2812 m_freem(*m_head); 2813 *m_head = NULL; 2814 return (EIO); 2815 } 2816 2817 /* Check for number of available descriptors. */ 2818 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2819 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2820 return (ENOBUFS); 2821 } 2822 2823 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2824 BUS_DMASYNC_PREWRITE); 2825 2826 /* 2827 * Set up checksum offload. Note: checksum offload bits must 2828 * appear in all descriptors of a multi-descriptor transmit 2829 * attempt. This is according to testing done with an 8169 2830 * chip. This is a requirement. 2831 */ 2832 vlanctl = 0; 2833 csum_flags = 0; 2834 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2835 if ((sc->rl_flags & RL_FLAG_DESCV2) != 0) { 2836 csum_flags |= RL_TDESC_CMD_LGSEND; 2837 vlanctl |= ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2838 RL_TDESC_CMD_MSSVALV2_SHIFT); 2839 } else { 2840 csum_flags |= RL_TDESC_CMD_LGSEND | 2841 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2842 RL_TDESC_CMD_MSSVAL_SHIFT); 2843 } 2844 } else { 2845 /* 2846 * Unconditionally enable IP checksum if TCP or UDP 2847 * checksum is required. Otherwise, TCP/UDP checksum 2848 * doesn't make effects. 2849 */ 2850 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) { 2851 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2852 csum_flags |= RL_TDESC_CMD_IPCSUM; 2853 if (((*m_head)->m_pkthdr.csum_flags & 2854 CSUM_TCP) != 0) 2855 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2856 if (((*m_head)->m_pkthdr.csum_flags & 2857 CSUM_UDP) != 0) 2858 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2859 } else { 2860 vlanctl |= RL_TDESC_CMD_IPCSUMV2; 2861 if (((*m_head)->m_pkthdr.csum_flags & 2862 CSUM_TCP) != 0) 2863 vlanctl |= RL_TDESC_CMD_TCPCSUMV2; 2864 if (((*m_head)->m_pkthdr.csum_flags & 2865 CSUM_UDP) != 0) 2866 vlanctl |= RL_TDESC_CMD_UDPCSUMV2; 2867 } 2868 } 2869 } 2870 2871 /* 2872 * Set up hardware VLAN tagging. Note: vlan tag info must 2873 * appear in all descriptors of a multi-descriptor 2874 * transmission attempt. 2875 */ 2876 if ((*m_head)->m_flags & M_VLANTAG) 2877 vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) | 2878 RL_TDESC_VLANCTL_TAG; 2879 2880 si = prod; 2881 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2882 desc = &sc->rl_ldata.rl_tx_list[prod]; 2883 desc->rl_vlanctl = htole32(vlanctl); 2884 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2885 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2886 cmdstat = segs[i].ds_len; 2887 if (i != 0) 2888 cmdstat |= RL_TDESC_CMD_OWN; 2889 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2890 cmdstat |= RL_TDESC_CMD_EOR; 2891 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2892 sc->rl_ldata.rl_tx_free--; 2893 } 2894 /* Update producer index. */ 2895 sc->rl_ldata.rl_tx_prodidx = prod; 2896 2897 /* Set EOF on the last descriptor. */ 2898 ei = RL_TX_DESC_PRV(sc, prod); 2899 desc = &sc->rl_ldata.rl_tx_list[ei]; 2900 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2901 2902 desc = &sc->rl_ldata.rl_tx_list[si]; 2903 /* Set SOF and transfer ownership of packet to the chip. */ 2904 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2905 2906 /* 2907 * Insure that the map for this transmission 2908 * is placed at the array index of the last descriptor 2909 * in this chain. (Swap last and first dmamaps.) 2910 */ 2911 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2912 map = txd->tx_dmamap; 2913 txd->tx_dmamap = txd_last->tx_dmamap; 2914 txd_last->tx_dmamap = map; 2915 txd_last->tx_m = *m_head; 2916 2917 return (0); 2918 } 2919 2920 static void 2921 re_start(if_t ifp) 2922 { 2923 struct rl_softc *sc; 2924 2925 sc = if_getsoftc(ifp); 2926 RL_LOCK(sc); 2927 re_start_locked(ifp); 2928 RL_UNLOCK(sc); 2929 } 2930 2931 /* 2932 * Main transmit routine for C+ and gigE NICs. 2933 */ 2934 static void 2935 re_start_locked(if_t ifp) 2936 { 2937 struct rl_softc *sc; 2938 struct mbuf *m_head; 2939 int queued; 2940 2941 sc = if_getsoftc(ifp); 2942 2943 #ifdef DEV_NETMAP 2944 /* XXX is this necessary ? */ 2945 if (if_getcapenable(ifp) & IFCAP_NETMAP) { 2946 struct netmap_kring *kring = NA(ifp)->tx_rings[0]; 2947 if (sc->rl_ldata.rl_tx_prodidx != kring->nr_hwcur) { 2948 /* kick the tx unit */ 2949 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2950 #ifdef RE_TX_MODERATION 2951 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2952 #endif 2953 sc->rl_watchdog_timer = 5; 2954 } 2955 return; 2956 } 2957 #endif /* DEV_NETMAP */ 2958 2959 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2960 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) 2961 return; 2962 2963 for (queued = 0; !if_sendq_empty(ifp) && 2964 sc->rl_ldata.rl_tx_free > 1;) { 2965 m_head = if_dequeue(ifp); 2966 if (m_head == NULL) 2967 break; 2968 2969 if (re_encap(sc, &m_head) != 0) { 2970 if (m_head == NULL) 2971 break; 2972 if_sendq_prepend(ifp, m_head); 2973 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 2974 break; 2975 } 2976 2977 /* 2978 * If there's a BPF listener, bounce a copy of this frame 2979 * to him. 2980 */ 2981 ETHER_BPF_MTAP(ifp, m_head); 2982 2983 queued++; 2984 } 2985 2986 if (queued == 0) { 2987 #ifdef RE_TX_MODERATION 2988 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2989 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2990 #endif 2991 return; 2992 } 2993 2994 re_start_tx(sc); 2995 } 2996 2997 static void 2998 re_start_tx(struct rl_softc *sc) 2999 { 3000 3001 /* Flush the TX descriptors */ 3002 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 3003 sc->rl_ldata.rl_tx_list_map, 3004 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 3005 3006 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 3007 3008 #ifdef RE_TX_MODERATION 3009 /* 3010 * Use the countdown timer for interrupt moderation. 3011 * 'TX done' interrupts are disabled. Instead, we reset the 3012 * countdown timer, which will begin counting until it hits 3013 * the value in the TIMERINT register, and then trigger an 3014 * interrupt. Each time we write to the TIMERCNT register, 3015 * the timer count is reset to 0. 3016 */ 3017 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 3018 #endif 3019 3020 /* 3021 * Set a timeout in case the chip goes out to lunch. 3022 */ 3023 sc->rl_watchdog_timer = 5; 3024 } 3025 3026 static void 3027 re_set_jumbo(struct rl_softc *sc, int jumbo) 3028 { 3029 3030 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168E_VL) { 3031 pci_set_max_read_req(sc->rl_dev, 4096); 3032 return; 3033 } 3034 3035 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 3036 if (jumbo != 0) { 3037 CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) | 3038 RL_CFG3_JUMBO_EN0); 3039 switch (sc->rl_hwrev->rl_rev) { 3040 case RL_HWREV_8168DP: 3041 break; 3042 case RL_HWREV_8168E: 3043 CSR_WRITE_1(sc, sc->rl_cfg4, 3044 CSR_READ_1(sc, sc->rl_cfg4) | 0x01); 3045 break; 3046 default: 3047 CSR_WRITE_1(sc, sc->rl_cfg4, 3048 CSR_READ_1(sc, sc->rl_cfg4) | RL_CFG4_JUMBO_EN1); 3049 } 3050 } else { 3051 CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) & 3052 ~RL_CFG3_JUMBO_EN0); 3053 switch (sc->rl_hwrev->rl_rev) { 3054 case RL_HWREV_8168DP: 3055 break; 3056 case RL_HWREV_8168E: 3057 CSR_WRITE_1(sc, sc->rl_cfg4, 3058 CSR_READ_1(sc, sc->rl_cfg4) & ~0x01); 3059 break; 3060 default: 3061 CSR_WRITE_1(sc, sc->rl_cfg4, 3062 CSR_READ_1(sc, sc->rl_cfg4) & ~RL_CFG4_JUMBO_EN1); 3063 } 3064 } 3065 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3066 3067 switch (sc->rl_hwrev->rl_rev) { 3068 case RL_HWREV_8168DP: 3069 pci_set_max_read_req(sc->rl_dev, 4096); 3070 break; 3071 default: 3072 if (jumbo != 0) 3073 pci_set_max_read_req(sc->rl_dev, 512); 3074 else 3075 pci_set_max_read_req(sc->rl_dev, 4096); 3076 } 3077 } 3078 3079 static void 3080 re_init(void *xsc) 3081 { 3082 struct rl_softc *sc = xsc; 3083 3084 RL_LOCK(sc); 3085 re_init_locked(sc); 3086 RL_UNLOCK(sc); 3087 } 3088 3089 static void 3090 re_init_locked(struct rl_softc *sc) 3091 { 3092 if_t ifp = sc->rl_ifp; 3093 struct mii_data *mii; 3094 uint32_t reg; 3095 uint16_t cfg; 3096 uint32_t idr[2]; 3097 3098 RL_LOCK_ASSERT(sc); 3099 3100 mii = device_get_softc(sc->rl_miibus); 3101 3102 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 3103 return; 3104 3105 /* 3106 * Cancel pending I/O and free all RX/TX buffers. 3107 */ 3108 re_stop(sc); 3109 3110 /* Put controller into known state. */ 3111 re_reset(sc); 3112 3113 /* 3114 * For C+ mode, initialize the RX descriptors and mbufs. 3115 */ 3116 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3117 if (if_getmtu(ifp) > RL_MTU) { 3118 if (re_jrx_list_init(sc) != 0) { 3119 device_printf(sc->rl_dev, 3120 "no memory for jumbo RX buffers\n"); 3121 re_stop(sc); 3122 return; 3123 } 3124 /* Disable checksum offloading for jumbo frames. */ 3125 if_setcapenablebit(ifp, 0, (IFCAP_HWCSUM | IFCAP_TSO4)); 3126 if_sethwassistbits(ifp, 0, (RE_CSUM_FEATURES | CSUM_TSO)); 3127 } else { 3128 if (re_rx_list_init(sc) != 0) { 3129 device_printf(sc->rl_dev, 3130 "no memory for RX buffers\n"); 3131 re_stop(sc); 3132 return; 3133 } 3134 } 3135 re_set_jumbo(sc, if_getmtu(ifp) > RL_MTU); 3136 } else { 3137 if (re_rx_list_init(sc) != 0) { 3138 device_printf(sc->rl_dev, "no memory for RX buffers\n"); 3139 re_stop(sc); 3140 return; 3141 } 3142 if ((sc->rl_flags & RL_FLAG_PCIE) != 0 && 3143 pci_get_device(sc->rl_dev) != RT_DEVICEID_8101E) { 3144 if (if_getmtu(ifp) > RL_MTU) 3145 pci_set_max_read_req(sc->rl_dev, 512); 3146 else 3147 pci_set_max_read_req(sc->rl_dev, 4096); 3148 } 3149 } 3150 re_tx_list_init(sc); 3151 3152 /* 3153 * Enable C+ RX and TX mode, as well as VLAN stripping and 3154 * RX checksum offload. We must configure the C+ register 3155 * before all others. 3156 */ 3157 cfg = RL_CPLUSCMD_PCI_MRW; 3158 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 3159 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 3160 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 3161 cfg |= RL_CPLUSCMD_VLANSTRIP; 3162 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) { 3163 cfg |= RL_CPLUSCMD_MACSTAT_DIS; 3164 /* XXX magic. */ 3165 cfg |= 0x0001; 3166 } else 3167 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB; 3168 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg); 3169 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SC || 3170 sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) { 3171 reg = 0x000fff00; 3172 if ((CSR_READ_1(sc, sc->rl_cfg2) & RL_CFG2_PCI66MHZ) != 0) 3173 reg |= 0x000000ff; 3174 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) 3175 reg |= 0x00f00000; 3176 CSR_WRITE_4(sc, 0x7c, reg); 3177 /* Disable interrupt mitigation. */ 3178 CSR_WRITE_2(sc, 0xe2, 0); 3179 } 3180 /* 3181 * Disable TSO if interface MTU size is greater than MSS 3182 * allowed in controller. 3183 */ 3184 if (if_getmtu(ifp) > RL_TSO_MTU && (if_getcapenable(ifp) & IFCAP_TSO4) != 0) { 3185 if_setcapenablebit(ifp, 0, IFCAP_TSO4); 3186 if_sethwassistbits(ifp, 0, CSUM_TSO); 3187 } 3188 3189 /* 3190 * Init our MAC address. Even though the chipset 3191 * documentation doesn't mention it, we need to enter "Config 3192 * register write enable" mode to modify the ID registers. 3193 */ 3194 /* Copy MAC address on stack to align. */ 3195 bzero(idr, sizeof(idr)); 3196 bcopy(if_getlladdr(ifp), idr, ETHER_ADDR_LEN); 3197 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 3198 CSR_WRITE_4(sc, RL_IDR0, htole32(idr[0])); 3199 CSR_WRITE_4(sc, RL_IDR4, htole32(idr[1])); 3200 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3201 3202 /* 3203 * Load the addresses of the RX and TX lists into the chip. 3204 */ 3205 3206 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 3207 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 3208 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 3209 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 3210 3211 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 3212 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 3213 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 3214 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 3215 3216 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0) { 3217 /* Disable RXDV gate. */ 3218 CSR_WRITE_4(sc, RL_MISC, CSR_READ_4(sc, RL_MISC) & 3219 ~0x00080000); 3220 } 3221 3222 /* 3223 * Enable transmit and receive for pre-RTL8168G controllers. 3224 * RX/TX MACs should be enabled before RX/TX configuration. 3225 */ 3226 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) == 0) 3227 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB | RL_CMD_RX_ENB); 3228 3229 /* 3230 * Set the initial TX configuration. 3231 */ 3232 if (sc->rl_testmode) { 3233 if (sc->rl_type == RL_8169) 3234 CSR_WRITE_4(sc, RL_TXCFG, 3235 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 3236 else 3237 CSR_WRITE_4(sc, RL_TXCFG, 3238 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 3239 } else 3240 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 3241 3242 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 3243 3244 /* 3245 * Set the initial RX configuration. 3246 */ 3247 re_set_rxmode(sc); 3248 3249 /* Configure interrupt moderation. */ 3250 if (sc->rl_type == RL_8169) { 3251 /* Magic from vendor. */ 3252 CSR_WRITE_2(sc, RL_INTRMOD, 0x5100); 3253 } 3254 3255 /* 3256 * Enable transmit and receive for RTL8168G and later controllers. 3257 * RX/TX MACs should be enabled after RX/TX configuration. 3258 */ 3259 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0) 3260 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB | RL_CMD_RX_ENB); 3261 3262 #ifdef DEVICE_POLLING 3263 /* 3264 * Disable interrupts if we are polling. 3265 */ 3266 if (if_getcapenable(ifp) & IFCAP_POLLING) 3267 CSR_WRITE_2(sc, RL_IMR, 0); 3268 else /* otherwise ... */ 3269 #endif 3270 3271 /* 3272 * Enable interrupts. 3273 */ 3274 if (sc->rl_testmode) 3275 CSR_WRITE_2(sc, RL_IMR, 0); 3276 else 3277 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 3278 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 3279 3280 /* Set initial TX threshold */ 3281 sc->rl_txthresh = RL_TX_THRESH_INIT; 3282 3283 /* Start RX/TX process. */ 3284 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 3285 3286 /* 3287 * Initialize the timer interrupt register so that 3288 * a timer interrupt will be generated once the timer 3289 * reaches a certain number of ticks. The timer is 3290 * reloaded on each transmit. 3291 */ 3292 #ifdef RE_TX_MODERATION 3293 /* 3294 * Use timer interrupt register to moderate TX interrupt 3295 * moderation, which dramatically improves TX frame rate. 3296 */ 3297 if (sc->rl_type == RL_8169) 3298 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 3299 else 3300 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 3301 #else 3302 /* 3303 * Use timer interrupt register to moderate RX interrupt 3304 * moderation. 3305 */ 3306 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 && 3307 intr_filter == 0) { 3308 if (sc->rl_type == RL_8169) 3309 CSR_WRITE_4(sc, RL_TIMERINT_8169, 3310 RL_USECS(sc->rl_int_rx_mod)); 3311 } else { 3312 if (sc->rl_type == RL_8169) 3313 CSR_WRITE_4(sc, RL_TIMERINT_8169, RL_USECS(0)); 3314 } 3315 #endif 3316 3317 /* 3318 * For 8169 gigE NICs, set the max allowed RX packet 3319 * size so we can receive jumbo frames. 3320 */ 3321 if (sc->rl_type == RL_8169) { 3322 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3323 /* 3324 * For controllers that use new jumbo frame scheme, 3325 * set maximum size of jumbo frame depending on 3326 * controller revisions. 3327 */ 3328 if (if_getmtu(ifp) > RL_MTU) 3329 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 3330 sc->rl_hwrev->rl_max_mtu + 3331 ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN + 3332 ETHER_CRC_LEN); 3333 else 3334 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 3335 RE_RX_DESC_BUFLEN); 3336 } else if ((sc->rl_flags & RL_FLAG_PCIE) != 0 && 3337 sc->rl_hwrev->rl_max_mtu == RL_MTU) { 3338 /* RTL810x has no jumbo frame support. */ 3339 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, RE_RX_DESC_BUFLEN); 3340 } else 3341 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 3342 } 3343 3344 if (sc->rl_testmode) 3345 return; 3346 3347 CSR_WRITE_1(sc, sc->rl_cfg1, CSR_READ_1(sc, sc->rl_cfg1) | 3348 RL_CFG1_DRVLOAD); 3349 3350 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 3351 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 3352 3353 sc->rl_flags &= ~RL_FLAG_LINK; 3354 mii_mediachg(mii); 3355 3356 sc->rl_watchdog_timer = 0; 3357 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 3358 3359 #ifdef DEV_NETMAP 3360 netmap_enable_all_rings(ifp); 3361 #endif /* DEV_NETMAP */ 3362 } 3363 3364 /* 3365 * Set media options. 3366 */ 3367 static int 3368 re_ifmedia_upd(if_t ifp) 3369 { 3370 struct rl_softc *sc; 3371 struct mii_data *mii; 3372 int error; 3373 3374 sc = if_getsoftc(ifp); 3375 mii = device_get_softc(sc->rl_miibus); 3376 RL_LOCK(sc); 3377 error = mii_mediachg(mii); 3378 RL_UNLOCK(sc); 3379 3380 return (error); 3381 } 3382 3383 /* 3384 * Report current media status. 3385 */ 3386 static void 3387 re_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 3388 { 3389 struct rl_softc *sc; 3390 struct mii_data *mii; 3391 3392 sc = if_getsoftc(ifp); 3393 mii = device_get_softc(sc->rl_miibus); 3394 3395 RL_LOCK(sc); 3396 mii_pollstat(mii); 3397 ifmr->ifm_active = mii->mii_media_active; 3398 ifmr->ifm_status = mii->mii_media_status; 3399 RL_UNLOCK(sc); 3400 } 3401 3402 static int 3403 re_ioctl(if_t ifp, u_long command, caddr_t data) 3404 { 3405 struct rl_softc *sc = if_getsoftc(ifp); 3406 struct ifreq *ifr = (struct ifreq *) data; 3407 struct mii_data *mii; 3408 int error = 0; 3409 3410 switch (command) { 3411 case SIOCSIFMTU: 3412 if (ifr->ifr_mtu < ETHERMIN || 3413 ifr->ifr_mtu > sc->rl_hwrev->rl_max_mtu || 3414 ((sc->rl_flags & RL_FLAG_FASTETHER) != 0 && 3415 ifr->ifr_mtu > RL_MTU)) { 3416 error = EINVAL; 3417 break; 3418 } 3419 RL_LOCK(sc); 3420 if (if_getmtu(ifp) != ifr->ifr_mtu) { 3421 if_setmtu(ifp, ifr->ifr_mtu); 3422 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 3423 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 3424 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3425 re_init_locked(sc); 3426 } 3427 if (if_getmtu(ifp) > RL_TSO_MTU && 3428 (if_getcapenable(ifp) & IFCAP_TSO4) != 0) { 3429 if_setcapenablebit(ifp, 0, 3430 IFCAP_TSO4 | IFCAP_VLAN_HWTSO); 3431 if_sethwassistbits(ifp, 0, CSUM_TSO); 3432 } 3433 VLAN_CAPABILITIES(ifp); 3434 } 3435 RL_UNLOCK(sc); 3436 break; 3437 case SIOCSIFFLAGS: 3438 RL_LOCK(sc); 3439 if ((if_getflags(ifp) & IFF_UP) != 0) { 3440 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 3441 if (((if_getflags(ifp) ^ sc->rl_if_flags) 3442 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 3443 re_set_rxmode(sc); 3444 } else 3445 re_init_locked(sc); 3446 } else { 3447 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 3448 re_stop(sc); 3449 } 3450 sc->rl_if_flags = if_getflags(ifp); 3451 RL_UNLOCK(sc); 3452 break; 3453 case SIOCADDMULTI: 3454 case SIOCDELMULTI: 3455 RL_LOCK(sc); 3456 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 3457 re_set_rxmode(sc); 3458 RL_UNLOCK(sc); 3459 break; 3460 case SIOCGIFMEDIA: 3461 case SIOCSIFMEDIA: 3462 mii = device_get_softc(sc->rl_miibus); 3463 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3464 break; 3465 case SIOCSIFCAP: 3466 { 3467 int mask, reinit; 3468 3469 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 3470 reinit = 0; 3471 #ifdef DEVICE_POLLING 3472 if (mask & IFCAP_POLLING) { 3473 if (ifr->ifr_reqcap & IFCAP_POLLING) { 3474 error = ether_poll_register(re_poll, ifp); 3475 if (error) 3476 return (error); 3477 RL_LOCK(sc); 3478 /* Disable interrupts */ 3479 CSR_WRITE_2(sc, RL_IMR, 0x0000); 3480 if_setcapenablebit(ifp, IFCAP_POLLING, 0); 3481 RL_UNLOCK(sc); 3482 } else { 3483 error = ether_poll_deregister(ifp); 3484 /* Enable interrupts. */ 3485 RL_LOCK(sc); 3486 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 3487 if_setcapenablebit(ifp, 0, IFCAP_POLLING); 3488 RL_UNLOCK(sc); 3489 } 3490 } 3491 #endif /* DEVICE_POLLING */ 3492 RL_LOCK(sc); 3493 if ((mask & IFCAP_TXCSUM) != 0 && 3494 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { 3495 if_togglecapenable(ifp, IFCAP_TXCSUM); 3496 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 3497 if_sethwassistbits(ifp, RE_CSUM_FEATURES, 0); 3498 else 3499 if_sethwassistbits(ifp, 0, RE_CSUM_FEATURES); 3500 reinit = 1; 3501 } 3502 if ((mask & IFCAP_RXCSUM) != 0 && 3503 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) { 3504 if_togglecapenable(ifp, IFCAP_RXCSUM); 3505 reinit = 1; 3506 } 3507 if ((mask & IFCAP_TSO4) != 0 && 3508 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) { 3509 if_togglecapenable(ifp, IFCAP_TSO4); 3510 if ((IFCAP_TSO4 & if_getcapenable(ifp)) != 0) 3511 if_sethwassistbits(ifp, CSUM_TSO, 0); 3512 else 3513 if_sethwassistbits(ifp, 0, CSUM_TSO); 3514 if (if_getmtu(ifp) > RL_TSO_MTU && 3515 (if_getcapenable(ifp) & IFCAP_TSO4) != 0) { 3516 if_setcapenablebit(ifp, 0, IFCAP_TSO4); 3517 if_sethwassistbits(ifp, 0, CSUM_TSO); 3518 } 3519 } 3520 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 3521 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0) 3522 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 3523 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3524 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 3525 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 3526 /* TSO over VLAN requires VLAN hardware tagging. */ 3527 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0) 3528 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO); 3529 reinit = 1; 3530 } 3531 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 3532 (mask & (IFCAP_HWCSUM | IFCAP_TSO4 | 3533 IFCAP_VLAN_HWTSO)) != 0) 3534 reinit = 1; 3535 if ((mask & IFCAP_WOL) != 0 && 3536 (if_getcapabilities(ifp) & IFCAP_WOL) != 0) { 3537 if ((mask & IFCAP_WOL_UCAST) != 0) 3538 if_togglecapenable(ifp, IFCAP_WOL_UCAST); 3539 if ((mask & IFCAP_WOL_MCAST) != 0) 3540 if_togglecapenable(ifp, IFCAP_WOL_MCAST); 3541 if ((mask & IFCAP_WOL_MAGIC) != 0) 3542 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 3543 } 3544 if (reinit && if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 3545 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3546 re_init_locked(sc); 3547 } 3548 RL_UNLOCK(sc); 3549 VLAN_CAPABILITIES(ifp); 3550 } 3551 break; 3552 default: 3553 error = ether_ioctl(ifp, command, data); 3554 break; 3555 } 3556 3557 return (error); 3558 } 3559 3560 static void 3561 re_watchdog(struct rl_softc *sc) 3562 { 3563 struct epoch_tracker et; 3564 if_t ifp; 3565 3566 RL_LOCK_ASSERT(sc); 3567 3568 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 3569 return; 3570 3571 ifp = sc->rl_ifp; 3572 re_txeof(sc); 3573 if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) { 3574 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 3575 "-- recovering\n"); 3576 if (!if_sendq_empty(ifp)) 3577 re_start_locked(ifp); 3578 return; 3579 } 3580 3581 if_printf(ifp, "watchdog timeout\n"); 3582 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3583 3584 NET_EPOCH_ENTER(et); 3585 re_rxeof(sc, NULL); 3586 NET_EPOCH_EXIT(et); 3587 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 3588 re_init_locked(sc); 3589 if (!if_sendq_empty(ifp)) 3590 re_start_locked(ifp); 3591 } 3592 3593 /* 3594 * Stop the adapter and free any mbufs allocated to the 3595 * RX and TX lists. 3596 */ 3597 static void 3598 re_stop(struct rl_softc *sc) 3599 { 3600 int i; 3601 if_t ifp; 3602 struct rl_txdesc *txd; 3603 struct rl_rxdesc *rxd; 3604 3605 RL_LOCK_ASSERT(sc); 3606 3607 ifp = sc->rl_ifp; 3608 3609 sc->rl_watchdog_timer = 0; 3610 callout_stop(&sc->rl_stat_callout); 3611 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 3612 3613 #ifdef DEV_NETMAP 3614 netmap_disable_all_rings(ifp); 3615 #endif /* DEV_NETMAP */ 3616 3617 /* 3618 * Disable accepting frames to put RX MAC into idle state. 3619 * Otherwise it's possible to get frames while stop command 3620 * execution is in progress and controller can DMA the frame 3621 * to already freed RX buffer during that period. 3622 */ 3623 CSR_WRITE_4(sc, RL_RXCFG, CSR_READ_4(sc, RL_RXCFG) & 3624 ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_MULTI | 3625 RL_RXCFG_RX_BROAD)); 3626 3627 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0) { 3628 /* Enable RXDV gate. */ 3629 CSR_WRITE_4(sc, RL_MISC, CSR_READ_4(sc, RL_MISC) | 3630 0x00080000); 3631 } 3632 3633 if ((sc->rl_flags & RL_FLAG_WAIT_TXPOLL) != 0) { 3634 for (i = RL_TIMEOUT; i > 0; i--) { 3635 if ((CSR_READ_1(sc, sc->rl_txstart) & 3636 RL_TXSTART_START) == 0) 3637 break; 3638 DELAY(20); 3639 } 3640 if (i == 0) 3641 device_printf(sc->rl_dev, 3642 "stopping TX poll timed out!\n"); 3643 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 3644 } else if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0) { 3645 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB | 3646 RL_CMD_RX_ENB); 3647 if ((sc->rl_flags & RL_FLAG_CMDSTOP_WAIT_TXQ) != 0) { 3648 for (i = RL_TIMEOUT; i > 0; i--) { 3649 if ((CSR_READ_4(sc, RL_TXCFG) & 3650 RL_TXCFG_QUEUE_EMPTY) != 0) 3651 break; 3652 DELAY(100); 3653 } 3654 if (i == 0) 3655 device_printf(sc->rl_dev, 3656 "stopping TXQ timed out!\n"); 3657 } 3658 } else 3659 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 3660 DELAY(1000); 3661 CSR_WRITE_2(sc, RL_IMR, 0x0000); 3662 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 3663 3664 if (sc->rl_head != NULL) { 3665 m_freem(sc->rl_head); 3666 sc->rl_head = sc->rl_tail = NULL; 3667 } 3668 3669 /* Free the TX list buffers. */ 3670 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 3671 txd = &sc->rl_ldata.rl_tx_desc[i]; 3672 if (txd->tx_m != NULL) { 3673 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 3674 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3675 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 3676 txd->tx_dmamap); 3677 m_freem(txd->tx_m); 3678 txd->tx_m = NULL; 3679 } 3680 } 3681 3682 /* Free the RX list buffers. */ 3683 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 3684 rxd = &sc->rl_ldata.rl_rx_desc[i]; 3685 if (rxd->rx_m != NULL) { 3686 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 3687 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3688 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 3689 rxd->rx_dmamap); 3690 m_freem(rxd->rx_m); 3691 rxd->rx_m = NULL; 3692 } 3693 } 3694 3695 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3696 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 3697 rxd = &sc->rl_ldata.rl_jrx_desc[i]; 3698 if (rxd->rx_m != NULL) { 3699 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, 3700 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3701 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, 3702 rxd->rx_dmamap); 3703 m_freem(rxd->rx_m); 3704 rxd->rx_m = NULL; 3705 } 3706 } 3707 } 3708 } 3709 3710 /* 3711 * Device suspend routine. Stop the interface and save some PCI 3712 * settings in case the BIOS doesn't restore them properly on 3713 * resume. 3714 */ 3715 static int 3716 re_suspend(device_t dev) 3717 { 3718 struct rl_softc *sc; 3719 3720 sc = device_get_softc(dev); 3721 3722 RL_LOCK(sc); 3723 re_stop(sc); 3724 re_setwol(sc); 3725 sc->suspended = 1; 3726 RL_UNLOCK(sc); 3727 3728 return (0); 3729 } 3730 3731 /* 3732 * Device resume routine. Restore some PCI settings in case the BIOS 3733 * doesn't, re-enable busmastering, and restart the interface if 3734 * appropriate. 3735 */ 3736 static int 3737 re_resume(device_t dev) 3738 { 3739 struct rl_softc *sc; 3740 if_t ifp; 3741 3742 sc = device_get_softc(dev); 3743 3744 RL_LOCK(sc); 3745 3746 ifp = sc->rl_ifp; 3747 /* Take controller out of sleep mode. */ 3748 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3749 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3750 CSR_WRITE_1(sc, RL_GPIO, 3751 CSR_READ_1(sc, RL_GPIO) | 0x01); 3752 } 3753 3754 /* 3755 * Clear WOL matching such that normal Rx filtering 3756 * wouldn't interfere with WOL patterns. 3757 */ 3758 re_clrwol(sc); 3759 3760 /* reinitialize interface if necessary */ 3761 if (if_getflags(ifp) & IFF_UP) 3762 re_init_locked(sc); 3763 3764 sc->suspended = 0; 3765 RL_UNLOCK(sc); 3766 3767 return (0); 3768 } 3769 3770 /* 3771 * Stop all chip I/O so that the kernel's probe routines don't 3772 * get confused by errant DMAs when rebooting. 3773 */ 3774 static int 3775 re_shutdown(device_t dev) 3776 { 3777 struct rl_softc *sc; 3778 3779 sc = device_get_softc(dev); 3780 3781 RL_LOCK(sc); 3782 re_stop(sc); 3783 /* 3784 * Mark interface as down since otherwise we will panic if 3785 * interrupt comes in later on, which can happen in some 3786 * cases. 3787 */ 3788 if_setflagbits(sc->rl_ifp, 0, IFF_UP); 3789 re_setwol(sc); 3790 RL_UNLOCK(sc); 3791 3792 return (0); 3793 } 3794 3795 static void 3796 re_set_linkspeed(struct rl_softc *sc) 3797 { 3798 struct mii_softc *miisc; 3799 struct mii_data *mii; 3800 int aneg, i, phyno; 3801 3802 RL_LOCK_ASSERT(sc); 3803 3804 mii = device_get_softc(sc->rl_miibus); 3805 mii_pollstat(mii); 3806 aneg = 0; 3807 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 3808 (IFM_ACTIVE | IFM_AVALID)) { 3809 switch IFM_SUBTYPE(mii->mii_media_active) { 3810 case IFM_10_T: 3811 case IFM_100_TX: 3812 return; 3813 case IFM_1000_T: 3814 aneg++; 3815 break; 3816 default: 3817 break; 3818 } 3819 } 3820 miisc = LIST_FIRST(&mii->mii_phys); 3821 phyno = miisc->mii_phy; 3822 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 3823 PHY_RESET(miisc); 3824 re_miibus_writereg(sc->rl_dev, phyno, MII_100T2CR, 0); 3825 re_miibus_writereg(sc->rl_dev, phyno, 3826 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 3827 re_miibus_writereg(sc->rl_dev, phyno, 3828 MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 3829 DELAY(1000); 3830 if (aneg != 0) { 3831 /* 3832 * Poll link state until re(4) get a 10/100Mbps link. 3833 */ 3834 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 3835 mii_pollstat(mii); 3836 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 3837 == (IFM_ACTIVE | IFM_AVALID)) { 3838 switch (IFM_SUBTYPE(mii->mii_media_active)) { 3839 case IFM_10_T: 3840 case IFM_100_TX: 3841 return; 3842 default: 3843 break; 3844 } 3845 } 3846 RL_UNLOCK(sc); 3847 pause("relnk", hz); 3848 RL_LOCK(sc); 3849 } 3850 if (i == MII_ANEGTICKS_GIGE) 3851 device_printf(sc->rl_dev, 3852 "establishing a link failed, WOL may not work!"); 3853 } 3854 /* 3855 * No link, force MAC to have 100Mbps, full-duplex link. 3856 * MAC does not require reprogramming on resolved speed/duplex, 3857 * so this is just for completeness. 3858 */ 3859 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 3860 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 3861 } 3862 3863 static void 3864 re_setwol(struct rl_softc *sc) 3865 { 3866 if_t ifp; 3867 uint8_t v; 3868 3869 RL_LOCK_ASSERT(sc); 3870 3871 if (!pci_has_pm(sc->rl_dev)) 3872 return; 3873 3874 ifp = sc->rl_ifp; 3875 /* Put controller into sleep mode. */ 3876 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3877 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3878 CSR_WRITE_1(sc, RL_GPIO, 3879 CSR_READ_1(sc, RL_GPIO) & ~0x01); 3880 } 3881 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) { 3882 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0) { 3883 /* Disable RXDV gate. */ 3884 CSR_WRITE_4(sc, RL_MISC, CSR_READ_4(sc, RL_MISC) & 3885 ~0x00080000); 3886 } 3887 re_set_rxmode(sc); 3888 if ((sc->rl_flags & RL_FLAG_WOL_MANLINK) != 0) 3889 re_set_linkspeed(sc); 3890 if ((sc->rl_flags & RL_FLAG_WOLRXENB) != 0) 3891 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB); 3892 } 3893 /* Enable config register write. */ 3894 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3895 3896 /* Enable PME. */ 3897 v = CSR_READ_1(sc, sc->rl_cfg1); 3898 v &= ~RL_CFG1_PME; 3899 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 3900 v |= RL_CFG1_PME; 3901 CSR_WRITE_1(sc, sc->rl_cfg1, v); 3902 3903 v = CSR_READ_1(sc, sc->rl_cfg3); 3904 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3905 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 3906 v |= RL_CFG3_WOL_MAGIC; 3907 CSR_WRITE_1(sc, sc->rl_cfg3, v); 3908 3909 v = CSR_READ_1(sc, sc->rl_cfg5); 3910 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST | 3911 RL_CFG5_WOL_LANWAKE); 3912 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) != 0) 3913 v |= RL_CFG5_WOL_UCAST; 3914 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0) 3915 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 3916 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 3917 v |= RL_CFG5_WOL_LANWAKE; 3918 CSR_WRITE_1(sc, sc->rl_cfg5, v); 3919 3920 /* Config register write done. */ 3921 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3922 3923 if ((if_getcapenable(ifp) & IFCAP_WOL) == 0 && 3924 (sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) 3925 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) & ~0x80); 3926 /* 3927 * It seems that hardware resets its link speed to 100Mbps in 3928 * power down mode so switching to 100Mbps in driver is not 3929 * needed. 3930 */ 3931 3932 /* Request PME if WOL is requested. */ 3933 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 3934 pci_enable_pme(sc->rl_dev); 3935 } 3936 3937 static void 3938 re_clrwol(struct rl_softc *sc) 3939 { 3940 uint8_t v; 3941 3942 RL_LOCK_ASSERT(sc); 3943 3944 if (!pci_has_pm(sc->rl_dev)) 3945 return; 3946 3947 /* Enable config register write. */ 3948 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3949 3950 v = CSR_READ_1(sc, sc->rl_cfg3); 3951 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3952 CSR_WRITE_1(sc, sc->rl_cfg3, v); 3953 3954 /* Config register write done. */ 3955 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3956 3957 v = CSR_READ_1(sc, sc->rl_cfg5); 3958 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3959 v &= ~RL_CFG5_WOL_LANWAKE; 3960 CSR_WRITE_1(sc, sc->rl_cfg5, v); 3961 } 3962 3963 static void 3964 re_add_sysctls(struct rl_softc *sc) 3965 { 3966 struct sysctl_ctx_list *ctx; 3967 struct sysctl_oid_list *children; 3968 int error; 3969 3970 ctx = device_get_sysctl_ctx(sc->rl_dev); 3971 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev)); 3972 3973 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "stats", 3974 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, sc, 0, 3975 re_sysctl_stats, "I", "Statistics Information"); 3976 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) 3977 return; 3978 3979 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "int_rx_mod", 3980 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 3981 &sc->rl_int_rx_mod, 0, sysctl_hw_re_int_mod, "I", 3982 "re RX interrupt moderation"); 3983 /* Pull in device tunables. */ 3984 sc->rl_int_rx_mod = RL_TIMER_DEFAULT; 3985 error = resource_int_value(device_get_name(sc->rl_dev), 3986 device_get_unit(sc->rl_dev), "int_rx_mod", &sc->rl_int_rx_mod); 3987 if (error == 0) { 3988 if (sc->rl_int_rx_mod < RL_TIMER_MIN || 3989 sc->rl_int_rx_mod > RL_TIMER_MAX) { 3990 device_printf(sc->rl_dev, "int_rx_mod value out of " 3991 "range; using default: %d\n", 3992 RL_TIMER_DEFAULT); 3993 sc->rl_int_rx_mod = RL_TIMER_DEFAULT; 3994 } 3995 } 3996 } 3997 3998 static int 3999 re_sysctl_stats(SYSCTL_HANDLER_ARGS) 4000 { 4001 struct rl_softc *sc; 4002 struct rl_stats *stats; 4003 int error, i, result; 4004 4005 result = -1; 4006 error = sysctl_handle_int(oidp, &result, 0, req); 4007 if (error || req->newptr == NULL) 4008 return (error); 4009 4010 if (result == 1) { 4011 sc = (struct rl_softc *)arg1; 4012 RL_LOCK(sc); 4013 if ((if_getdrvflags(sc->rl_ifp) & IFF_DRV_RUNNING) == 0) { 4014 RL_UNLOCK(sc); 4015 goto done; 4016 } 4017 bus_dmamap_sync(sc->rl_ldata.rl_stag, 4018 sc->rl_ldata.rl_smap, BUS_DMASYNC_PREREAD); 4019 CSR_WRITE_4(sc, RL_DUMPSTATS_HI, 4020 RL_ADDR_HI(sc->rl_ldata.rl_stats_addr)); 4021 CSR_WRITE_4(sc, RL_DUMPSTATS_LO, 4022 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr)); 4023 CSR_WRITE_4(sc, RL_DUMPSTATS_LO, 4024 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr | 4025 RL_DUMPSTATS_START)); 4026 for (i = RL_TIMEOUT; i > 0; i--) { 4027 if ((CSR_READ_4(sc, RL_DUMPSTATS_LO) & 4028 RL_DUMPSTATS_START) == 0) 4029 break; 4030 DELAY(1000); 4031 } 4032 bus_dmamap_sync(sc->rl_ldata.rl_stag, 4033 sc->rl_ldata.rl_smap, BUS_DMASYNC_POSTREAD); 4034 RL_UNLOCK(sc); 4035 if (i == 0) { 4036 device_printf(sc->rl_dev, 4037 "DUMP statistics request timed out\n"); 4038 return (ETIMEDOUT); 4039 } 4040 done: 4041 stats = sc->rl_ldata.rl_stats; 4042 printf("%s statistics:\n", device_get_nameunit(sc->rl_dev)); 4043 printf("Tx frames : %ju\n", 4044 (uintmax_t)le64toh(stats->rl_tx_pkts)); 4045 printf("Rx frames : %ju\n", 4046 (uintmax_t)le64toh(stats->rl_rx_pkts)); 4047 printf("Tx errors : %ju\n", 4048 (uintmax_t)le64toh(stats->rl_tx_errs)); 4049 printf("Rx errors : %u\n", 4050 le32toh(stats->rl_rx_errs)); 4051 printf("Rx missed frames : %u\n", 4052 (uint32_t)le16toh(stats->rl_missed_pkts)); 4053 printf("Rx frame alignment errs : %u\n", 4054 (uint32_t)le16toh(stats->rl_rx_framealign_errs)); 4055 printf("Tx single collisions : %u\n", 4056 le32toh(stats->rl_tx_onecoll)); 4057 printf("Tx multiple collisions : %u\n", 4058 le32toh(stats->rl_tx_multicolls)); 4059 printf("Rx unicast frames : %ju\n", 4060 (uintmax_t)le64toh(stats->rl_rx_ucasts)); 4061 printf("Rx broadcast frames : %ju\n", 4062 (uintmax_t)le64toh(stats->rl_rx_bcasts)); 4063 printf("Rx multicast frames : %u\n", 4064 le32toh(stats->rl_rx_mcasts)); 4065 printf("Tx aborts : %u\n", 4066 (uint32_t)le16toh(stats->rl_tx_aborts)); 4067 printf("Tx underruns : %u\n", 4068 (uint32_t)le16toh(stats->rl_rx_underruns)); 4069 } 4070 4071 return (error); 4072 } 4073 4074 static int 4075 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4076 { 4077 int error, value; 4078 4079 if (arg1 == NULL) 4080 return (EINVAL); 4081 value = *(int *)arg1; 4082 error = sysctl_handle_int(oidp, &value, 0, req); 4083 if (error || req->newptr == NULL) 4084 return (error); 4085 if (value < low || value > high) 4086 return (EINVAL); 4087 *(int *)arg1 = value; 4088 4089 return (0); 4090 } 4091 4092 static int 4093 sysctl_hw_re_int_mod(SYSCTL_HANDLER_ARGS) 4094 { 4095 4096 return (sysctl_int_range(oidp, arg1, arg2, req, RL_TIMER_MIN, 4097 RL_TIMER_MAX)); 4098 } 4099 4100 #ifdef DEBUGNET 4101 static void 4102 re_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize) 4103 { 4104 struct rl_softc *sc; 4105 4106 sc = if_getsoftc(ifp); 4107 RL_LOCK(sc); 4108 *nrxr = sc->rl_ldata.rl_rx_desc_cnt; 4109 *ncl = DEBUGNET_MAX_IN_FLIGHT; 4110 *clsize = (if_getmtu(ifp) > RL_MTU && 4111 (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) ? MJUM9BYTES : MCLBYTES; 4112 RL_UNLOCK(sc); 4113 } 4114 4115 static void 4116 re_debugnet_event(if_t ifp __unused, enum debugnet_ev event __unused) 4117 { 4118 } 4119 4120 static int 4121 re_debugnet_transmit(if_t ifp, struct mbuf *m) 4122 { 4123 struct rl_softc *sc; 4124 int error; 4125 4126 sc = if_getsoftc(ifp); 4127 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 4128 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) 4129 return (EBUSY); 4130 4131 error = re_encap(sc, &m); 4132 if (error == 0) 4133 re_start_tx(sc); 4134 return (error); 4135 } 4136 4137 static int 4138 re_debugnet_poll(if_t ifp, int count) 4139 { 4140 struct rl_softc *sc; 4141 int error; 4142 4143 sc = if_getsoftc(ifp); 4144 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0 || 4145 (sc->rl_flags & RL_FLAG_LINK) == 0) 4146 return (EBUSY); 4147 4148 re_txeof(sc); 4149 error = re_rxeof(sc, NULL); 4150 if (error != 0 && error != EAGAIN) 4151 return (error); 4152 return (0); 4153 } 4154 #endif /* DEBUGNET */ 4155