1 /*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44 /* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S 48 * and the RTL8110S. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111 #ifdef HAVE_KERNEL_OPTION_HEADERS 112 #include "opt_device_polling.h" 113 #endif 114 115 #include <sys/param.h> 116 #include <sys/endian.h> 117 #include <sys/systm.h> 118 #include <sys/sockio.h> 119 #include <sys/mbuf.h> 120 #include <sys/malloc.h> 121 #include <sys/module.h> 122 #include <sys/kernel.h> 123 #include <sys/socket.h> 124 125 #include <net/if.h> 126 #include <net/if_arp.h> 127 #include <net/ethernet.h> 128 #include <net/if_dl.h> 129 #include <net/if_media.h> 130 #include <net/if_types.h> 131 #include <net/if_vlan_var.h> 132 133 #include <net/bpf.h> 134 135 #include <machine/bus.h> 136 #include <machine/resource.h> 137 #include <sys/bus.h> 138 #include <sys/rman.h> 139 140 #include <dev/mii/mii.h> 141 #include <dev/mii/miivar.h> 142 143 #include <dev/pci/pcireg.h> 144 #include <dev/pci/pcivar.h> 145 146 MODULE_DEPEND(re, pci, 1, 1, 1); 147 MODULE_DEPEND(re, ether, 1, 1, 1); 148 MODULE_DEPEND(re, miibus, 1, 1, 1); 149 150 /* "device miibus" required. See GENERIC if you get errors here. */ 151 #include "miibus_if.h" 152 153 /* 154 * Default to using PIO access for this driver. 155 */ 156 #define RE_USEIOSPACE 157 158 #include <pci/if_rlreg.h> 159 160 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 161 162 /* 163 * Various supported device vendors/types and their names. 164 */ 165 static struct rl_type re_devs[] = { 166 { DLINK_VENDORID, DLINK_DEVICEID_528T, RL_HWREV_8169S, 167 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 168 { RT_VENDORID, RT_DEVICEID_8139, RL_HWREV_8139CPLUS, 169 "RealTek 8139C+ 10/100BaseTX" }, 170 { RT_VENDORID, RT_DEVICEID_8168, RL_HWREV_8168, 171 "Realtek 8168B/8111B Gigabit Ethernet" }, 172 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169, 173 "RealTek 8169 Gigabit Ethernet" }, 174 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169S, 175 "RealTek 8169S Single-chip Gigabit Ethernet" }, 176 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169SB, 177 "RealTek 8169SB Single-chip Gigabit Ethernet" }, 178 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8110S, 179 "RealTek 8110S Single-chip Gigabit Ethernet" }, 180 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, RL_HWREV_8169S, 181 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 182 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, RL_HWREV_8169S, 183 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 184 { 0, 0, 0, NULL } 185 }; 186 187 static struct rl_hwrev re_hwrevs[] = { 188 { RL_HWREV_8139, RL_8139, "" }, 189 { RL_HWREV_8139A, RL_8139, "A" }, 190 { RL_HWREV_8139AG, RL_8139, "A-G" }, 191 { RL_HWREV_8139B, RL_8139, "B" }, 192 { RL_HWREV_8130, RL_8139, "8130" }, 193 { RL_HWREV_8139C, RL_8139, "C" }, 194 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 195 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 196 { RL_HWREV_8169, RL_8169, "8169"}, 197 { RL_HWREV_8169S, RL_8169, "8169S"}, 198 { RL_HWREV_8169SB, RL_8169, "8169SB"}, 199 { RL_HWREV_8110S, RL_8169, "8110S"}, 200 { RL_HWREV_8100, RL_8139, "8100"}, 201 { RL_HWREV_8101, RL_8139, "8101"}, 202 { RL_HWREV_8168, RL_8169, "8168/8111B"}, 203 { 0, 0, NULL } 204 }; 205 206 static int re_probe (device_t); 207 static int re_attach (device_t); 208 static int re_detach (device_t); 209 210 static int re_encap (struct rl_softc *, struct mbuf **, int *); 211 212 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 213 static void re_dma_map_desc (void *, bus_dma_segment_t *, int, 214 bus_size_t, int); 215 static int re_allocmem (device_t, struct rl_softc *); 216 static int re_newbuf (struct rl_softc *, int, struct mbuf *); 217 static int re_rx_list_init (struct rl_softc *); 218 static int re_tx_list_init (struct rl_softc *); 219 #ifdef RE_FIXUP_RX 220 static __inline void re_fixup_rx 221 (struct mbuf *); 222 #endif 223 static void re_rxeof (struct rl_softc *); 224 static void re_txeof (struct rl_softc *); 225 #ifdef DEVICE_POLLING 226 static void re_poll (struct ifnet *, enum poll_cmd, int); 227 static void re_poll_locked (struct ifnet *, enum poll_cmd, int); 228 #endif 229 static void re_intr (void *); 230 static void re_tick (void *); 231 static void re_start (struct ifnet *); 232 static void re_start_locked (struct ifnet *); 233 static int re_ioctl (struct ifnet *, u_long, caddr_t); 234 static void re_init (void *); 235 static void re_init_locked (struct rl_softc *); 236 static void re_stop (struct rl_softc *); 237 static void re_watchdog (struct ifnet *); 238 static int re_suspend (device_t); 239 static int re_resume (device_t); 240 static void re_shutdown (device_t); 241 static int re_ifmedia_upd (struct ifnet *); 242 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 243 244 static void re_eeprom_putbyte (struct rl_softc *, int); 245 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 246 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int, int); 247 static int re_gmii_readreg (device_t, int, int); 248 static int re_gmii_writereg (device_t, int, int, int); 249 250 static int re_miibus_readreg (device_t, int, int); 251 static int re_miibus_writereg (device_t, int, int, int); 252 static void re_miibus_statchg (device_t); 253 254 static void re_setmulti (struct rl_softc *); 255 static void re_reset (struct rl_softc *); 256 257 static int re_diag (struct rl_softc *); 258 259 #ifdef RE_USEIOSPACE 260 #define RL_RES SYS_RES_IOPORT 261 #define RL_RID RL_PCI_LOIO 262 #else 263 #define RL_RES SYS_RES_MEMORY 264 #define RL_RID RL_PCI_LOMEM 265 #endif 266 267 static device_method_t re_methods[] = { 268 /* Device interface */ 269 DEVMETHOD(device_probe, re_probe), 270 DEVMETHOD(device_attach, re_attach), 271 DEVMETHOD(device_detach, re_detach), 272 DEVMETHOD(device_suspend, re_suspend), 273 DEVMETHOD(device_resume, re_resume), 274 DEVMETHOD(device_shutdown, re_shutdown), 275 276 /* bus interface */ 277 DEVMETHOD(bus_print_child, bus_generic_print_child), 278 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 279 280 /* MII interface */ 281 DEVMETHOD(miibus_readreg, re_miibus_readreg), 282 DEVMETHOD(miibus_writereg, re_miibus_writereg), 283 DEVMETHOD(miibus_statchg, re_miibus_statchg), 284 285 { 0, 0 } 286 }; 287 288 static driver_t re_driver = { 289 "re", 290 re_methods, 291 sizeof(struct rl_softc) 292 }; 293 294 static devclass_t re_devclass; 295 296 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 297 DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0); 298 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 299 300 #define EE_SET(x) \ 301 CSR_WRITE_1(sc, RL_EECMD, \ 302 CSR_READ_1(sc, RL_EECMD) | x) 303 304 #define EE_CLR(x) \ 305 CSR_WRITE_1(sc, RL_EECMD, \ 306 CSR_READ_1(sc, RL_EECMD) & ~x) 307 308 /* 309 * Send a read command and address to the EEPROM, check for ACK. 310 */ 311 static void 312 re_eeprom_putbyte(sc, addr) 313 struct rl_softc *sc; 314 int addr; 315 { 316 register int d, i; 317 318 d = addr | sc->rl_eecmd_read; 319 320 /* 321 * Feed in each bit and strobe the clock. 322 */ 323 for (i = 0x400; i; i >>= 1) { 324 if (d & i) { 325 EE_SET(RL_EE_DATAIN); 326 } else { 327 EE_CLR(RL_EE_DATAIN); 328 } 329 DELAY(100); 330 EE_SET(RL_EE_CLK); 331 DELAY(150); 332 EE_CLR(RL_EE_CLK); 333 DELAY(100); 334 } 335 } 336 337 /* 338 * Read a word of data stored in the EEPROM at address 'addr.' 339 */ 340 static void 341 re_eeprom_getword(sc, addr, dest) 342 struct rl_softc *sc; 343 int addr; 344 u_int16_t *dest; 345 { 346 register int i; 347 u_int16_t word = 0; 348 349 /* Enter EEPROM access mode. */ 350 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 351 352 /* 353 * Send address of word we want to read. 354 */ 355 re_eeprom_putbyte(sc, addr); 356 357 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 358 359 /* 360 * Start reading bits from EEPROM. 361 */ 362 for (i = 0x8000; i; i >>= 1) { 363 EE_SET(RL_EE_CLK); 364 DELAY(100); 365 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 366 word |= i; 367 EE_CLR(RL_EE_CLK); 368 DELAY(100); 369 } 370 371 /* Turn off EEPROM access mode. */ 372 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 373 374 *dest = word; 375 } 376 377 /* 378 * Read a sequence of words from the EEPROM. 379 */ 380 static void 381 re_read_eeprom(sc, dest, off, cnt, swap) 382 struct rl_softc *sc; 383 caddr_t dest; 384 int off; 385 int cnt; 386 int swap; 387 { 388 int i; 389 u_int16_t word = 0, *ptr; 390 391 for (i = 0; i < cnt; i++) { 392 re_eeprom_getword(sc, off + i, &word); 393 ptr = (u_int16_t *)(dest + (i * 2)); 394 if (swap) 395 *ptr = ntohs(word); 396 else 397 *ptr = word; 398 } 399 } 400 401 static int 402 re_gmii_readreg(dev, phy, reg) 403 device_t dev; 404 int phy, reg; 405 { 406 struct rl_softc *sc; 407 u_int32_t rval; 408 int i; 409 410 if (phy != 1) 411 return (0); 412 413 sc = device_get_softc(dev); 414 415 /* Let the rgephy driver read the GMEDIASTAT register */ 416 417 if (reg == RL_GMEDIASTAT) { 418 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 419 return (rval); 420 } 421 422 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 423 DELAY(1000); 424 425 for (i = 0; i < RL_TIMEOUT; i++) { 426 rval = CSR_READ_4(sc, RL_PHYAR); 427 if (rval & RL_PHYAR_BUSY) 428 break; 429 DELAY(100); 430 } 431 432 if (i == RL_TIMEOUT) { 433 if_printf(sc->rl_ifp, "PHY read failed\n"); 434 return (0); 435 } 436 437 return (rval & RL_PHYAR_PHYDATA); 438 } 439 440 static int 441 re_gmii_writereg(dev, phy, reg, data) 442 device_t dev; 443 int phy, reg, data; 444 { 445 struct rl_softc *sc; 446 u_int32_t rval; 447 int i; 448 449 sc = device_get_softc(dev); 450 451 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 452 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 453 DELAY(1000); 454 455 for (i = 0; i < RL_TIMEOUT; i++) { 456 rval = CSR_READ_4(sc, RL_PHYAR); 457 if (!(rval & RL_PHYAR_BUSY)) 458 break; 459 DELAY(100); 460 } 461 462 if (i == RL_TIMEOUT) { 463 if_printf(sc->rl_ifp, "PHY write failed\n"); 464 return (0); 465 } 466 467 return (0); 468 } 469 470 static int 471 re_miibus_readreg(dev, phy, reg) 472 device_t dev; 473 int phy, reg; 474 { 475 struct rl_softc *sc; 476 u_int16_t rval = 0; 477 u_int16_t re8139_reg = 0; 478 479 sc = device_get_softc(dev); 480 481 if (sc->rl_type == RL_8169) { 482 rval = re_gmii_readreg(dev, phy, reg); 483 return (rval); 484 } 485 486 /* Pretend the internal PHY is only at address 0 */ 487 if (phy) { 488 return (0); 489 } 490 switch (reg) { 491 case MII_BMCR: 492 re8139_reg = RL_BMCR; 493 break; 494 case MII_BMSR: 495 re8139_reg = RL_BMSR; 496 break; 497 case MII_ANAR: 498 re8139_reg = RL_ANAR; 499 break; 500 case MII_ANER: 501 re8139_reg = RL_ANER; 502 break; 503 case MII_ANLPAR: 504 re8139_reg = RL_LPAR; 505 break; 506 case MII_PHYIDR1: 507 case MII_PHYIDR2: 508 return (0); 509 /* 510 * Allow the rlphy driver to read the media status 511 * register. If we have a link partner which does not 512 * support NWAY, this is the register which will tell 513 * us the results of parallel detection. 514 */ 515 case RL_MEDIASTAT: 516 rval = CSR_READ_1(sc, RL_MEDIASTAT); 517 return (rval); 518 default: 519 if_printf(sc->rl_ifp, "bad phy register\n"); 520 return (0); 521 } 522 rval = CSR_READ_2(sc, re8139_reg); 523 return (rval); 524 } 525 526 static int 527 re_miibus_writereg(dev, phy, reg, data) 528 device_t dev; 529 int phy, reg, data; 530 { 531 struct rl_softc *sc; 532 u_int16_t re8139_reg = 0; 533 int rval = 0; 534 535 sc = device_get_softc(dev); 536 537 if (sc->rl_type == RL_8169) { 538 rval = re_gmii_writereg(dev, phy, reg, data); 539 return (rval); 540 } 541 542 /* Pretend the internal PHY is only at address 0 */ 543 if (phy) 544 return (0); 545 546 switch (reg) { 547 case MII_BMCR: 548 re8139_reg = RL_BMCR; 549 break; 550 case MII_BMSR: 551 re8139_reg = RL_BMSR; 552 break; 553 case MII_ANAR: 554 re8139_reg = RL_ANAR; 555 break; 556 case MII_ANER: 557 re8139_reg = RL_ANER; 558 break; 559 case MII_ANLPAR: 560 re8139_reg = RL_LPAR; 561 break; 562 case MII_PHYIDR1: 563 case MII_PHYIDR2: 564 return (0); 565 break; 566 default: 567 if_printf(sc->rl_ifp, "bad phy register\n"); 568 return (0); 569 } 570 CSR_WRITE_2(sc, re8139_reg, data); 571 return (0); 572 } 573 574 static void 575 re_miibus_statchg(dev) 576 device_t dev; 577 { 578 579 } 580 581 /* 582 * Program the 64-bit multicast hash filter. 583 */ 584 static void 585 re_setmulti(sc) 586 struct rl_softc *sc; 587 { 588 struct ifnet *ifp; 589 int h = 0; 590 u_int32_t hashes[2] = { 0, 0 }; 591 struct ifmultiaddr *ifma; 592 u_int32_t rxfilt; 593 int mcnt = 0; 594 595 RL_LOCK_ASSERT(sc); 596 597 ifp = sc->rl_ifp; 598 599 rxfilt = CSR_READ_4(sc, RL_RXCFG); 600 601 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 602 rxfilt |= RL_RXCFG_RX_MULTI; 603 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 604 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 605 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 606 return; 607 } 608 609 /* first, zot all the existing hash bits */ 610 CSR_WRITE_4(sc, RL_MAR0, 0); 611 CSR_WRITE_4(sc, RL_MAR4, 0); 612 613 /* now program new ones */ 614 IF_ADDR_LOCK(ifp); 615 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 616 if (ifma->ifma_addr->sa_family != AF_LINK) 617 continue; 618 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 619 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 620 if (h < 32) 621 hashes[0] |= (1 << h); 622 else 623 hashes[1] |= (1 << (h - 32)); 624 mcnt++; 625 } 626 IF_ADDR_UNLOCK(ifp); 627 628 if (mcnt) 629 rxfilt |= RL_RXCFG_RX_MULTI; 630 else 631 rxfilt &= ~RL_RXCFG_RX_MULTI; 632 633 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 634 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 635 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 636 } 637 638 static void 639 re_reset(sc) 640 struct rl_softc *sc; 641 { 642 register int i; 643 644 RL_LOCK_ASSERT(sc); 645 646 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 647 648 for (i = 0; i < RL_TIMEOUT; i++) { 649 DELAY(10); 650 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 651 break; 652 } 653 if (i == RL_TIMEOUT) 654 if_printf(sc->rl_ifp, "reset never completed!\n"); 655 656 CSR_WRITE_1(sc, 0x82, 1); 657 } 658 659 /* 660 * The following routine is designed to test for a defect on some 661 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 662 * lines connected to the bus, however for a 32-bit only card, they 663 * should be pulled high. The result of this defect is that the 664 * NIC will not work right if you plug it into a 64-bit slot: DMA 665 * operations will be done with 64-bit transfers, which will fail 666 * because the 64-bit data lines aren't connected. 667 * 668 * There's no way to work around this (short of talking a soldering 669 * iron to the board), however we can detect it. The method we use 670 * here is to put the NIC into digital loopback mode, set the receiver 671 * to promiscuous mode, and then try to send a frame. We then compare 672 * the frame data we sent to what was received. If the data matches, 673 * then the NIC is working correctly, otherwise we know the user has 674 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 675 * slot. In the latter case, there's no way the NIC can work correctly, 676 * so we print out a message on the console and abort the device attach. 677 */ 678 679 static int 680 re_diag(sc) 681 struct rl_softc *sc; 682 { 683 struct ifnet *ifp = sc->rl_ifp; 684 struct mbuf *m0; 685 struct ether_header *eh; 686 struct rl_desc *cur_rx; 687 u_int16_t status; 688 u_int32_t rxstat; 689 int total_len, i, error = 0; 690 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 691 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 692 693 /* Allocate a single mbuf */ 694 MGETHDR(m0, M_DONTWAIT, MT_DATA); 695 if (m0 == NULL) 696 return (ENOBUFS); 697 698 RL_LOCK(sc); 699 700 /* 701 * Initialize the NIC in test mode. This sets the chip up 702 * so that it can send and receive frames, but performs the 703 * following special functions: 704 * - Puts receiver in promiscuous mode 705 * - Enables digital loopback mode 706 * - Leaves interrupts turned off 707 */ 708 709 ifp->if_flags |= IFF_PROMISC; 710 sc->rl_testmode = 1; 711 re_init_locked(sc); 712 re_stop(sc); 713 DELAY(100000); 714 re_init_locked(sc); 715 716 /* Put some data in the mbuf */ 717 718 eh = mtod(m0, struct ether_header *); 719 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 720 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 721 eh->ether_type = htons(ETHERTYPE_IP); 722 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 723 724 /* 725 * Queue the packet, start transmission. 726 * Note: IF_HANDOFF() ultimately calls re_start() for us. 727 */ 728 729 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 730 RL_UNLOCK(sc); 731 /* XXX: re_diag must not be called when in ALTQ mode */ 732 IF_HANDOFF(&ifp->if_snd, m0, ifp); 733 RL_LOCK(sc); 734 m0 = NULL; 735 736 /* Wait for it to propagate through the chip */ 737 738 DELAY(100000); 739 for (i = 0; i < RL_TIMEOUT; i++) { 740 status = CSR_READ_2(sc, RL_ISR); 741 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 742 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 743 break; 744 DELAY(10); 745 } 746 747 if (i == RL_TIMEOUT) { 748 if_printf(ifp, "diagnostic failed, failed to receive packet " 749 "in loopback mode\n"); 750 error = EIO; 751 goto done; 752 } 753 754 /* 755 * The packet should have been dumped into the first 756 * entry in the RX DMA ring. Grab it from there. 757 */ 758 759 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 760 sc->rl_ldata.rl_rx_list_map, 761 BUS_DMASYNC_POSTREAD); 762 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 763 sc->rl_ldata.rl_rx_dmamap[0], 764 BUS_DMASYNC_POSTWRITE); 765 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 766 sc->rl_ldata.rl_rx_dmamap[0]); 767 768 m0 = sc->rl_ldata.rl_rx_mbuf[0]; 769 sc->rl_ldata.rl_rx_mbuf[0] = NULL; 770 eh = mtod(m0, struct ether_header *); 771 772 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 773 total_len = RL_RXBYTES(cur_rx); 774 rxstat = le32toh(cur_rx->rl_cmdstat); 775 776 if (total_len != ETHER_MIN_LEN) { 777 if_printf(ifp, "diagnostic failed, received short packet\n"); 778 error = EIO; 779 goto done; 780 } 781 782 /* Test that the received packet data matches what we sent. */ 783 784 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 785 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 786 ntohs(eh->ether_type) != ETHERTYPE_IP) { 787 if_printf(ifp, "WARNING, DMA FAILURE!\n"); 788 if_printf(ifp, "expected TX data: %6D/%6D/0x%x\n", 789 dst, ":", src, ":", ETHERTYPE_IP); 790 if_printf(ifp, "received RX data: %6D/%6D/0x%x\n", 791 eh->ether_dhost, ":", eh->ether_shost, ":", 792 ntohs(eh->ether_type)); 793 if_printf(ifp, "You may have a defective 32-bit NIC plugged " 794 "into a 64-bit PCI slot.\n"); 795 if_printf(ifp, "Please re-install the NIC in a 32-bit slot " 796 "for proper operation.\n"); 797 if_printf(ifp, "Read the re(4) man page for more details.\n"); 798 error = EIO; 799 } 800 801 done: 802 /* Turn interface off, release resources */ 803 804 sc->rl_testmode = 0; 805 ifp->if_flags &= ~IFF_PROMISC; 806 re_stop(sc); 807 if (m0 != NULL) 808 m_freem(m0); 809 810 RL_UNLOCK(sc); 811 812 return (error); 813 } 814 815 /* 816 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 817 * IDs against our list and return a device name if we find a match. 818 */ 819 static int 820 re_probe(dev) 821 device_t dev; 822 { 823 struct rl_type *t; 824 struct rl_softc *sc; 825 int rid; 826 u_int32_t hwrev; 827 828 t = re_devs; 829 sc = device_get_softc(dev); 830 831 while (t->rl_name != NULL) { 832 if ((pci_get_vendor(dev) == t->rl_vid) && 833 (pci_get_device(dev) == t->rl_did)) { 834 /* 835 * Only attach to rev. 3 of the Linksys EG1032 adapter. 836 * Rev. 2 i supported by sk(4). 837 */ 838 if ((t->rl_vid == LINKSYS_VENDORID) && 839 (t->rl_did == LINKSYS_DEVICEID_EG1032) && 840 (pci_get_subdevice(dev) != 841 LINKSYS_SUBDEVICE_EG1032_REV3)) { 842 t++; 843 continue; 844 } 845 846 /* 847 * Temporarily map the I/O space 848 * so we can read the chip ID register. 849 */ 850 rid = RL_RID; 851 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 852 RF_ACTIVE); 853 if (sc->rl_res == NULL) { 854 device_printf(dev, 855 "couldn't map ports/memory\n"); 856 return (ENXIO); 857 } 858 sc->rl_btag = rman_get_bustag(sc->rl_res); 859 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 860 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 861 bus_release_resource(dev, RL_RES, 862 RL_RID, sc->rl_res); 863 if (t->rl_basetype == hwrev) { 864 device_set_desc(dev, t->rl_name); 865 return (BUS_PROBE_DEFAULT); 866 } 867 } 868 t++; 869 } 870 871 return (ENXIO); 872 } 873 874 /* 875 * This routine takes the segment list provided as the result of 876 * a bus_dma_map_load() operation and assigns the addresses/lengths 877 * to RealTek DMA descriptors. This can be called either by the RX 878 * code or the TX code. In the RX case, we'll probably wind up mapping 879 * at most one segment. For the TX case, there could be any number of 880 * segments since TX packets may span multiple mbufs. In either case, 881 * if the number of segments is larger than the rl_maxsegs limit 882 * specified by the caller, we abort the mapping operation. Sadly, 883 * whoever designed the buffer mapping API did not provide a way to 884 * return an error from here, so we have to fake it a bit. 885 */ 886 887 static void 888 re_dma_map_desc(arg, segs, nseg, mapsize, error) 889 void *arg; 890 bus_dma_segment_t *segs; 891 int nseg; 892 bus_size_t mapsize; 893 int error; 894 { 895 struct rl_dmaload_arg *ctx; 896 struct rl_desc *d = NULL; 897 int i = 0, idx; 898 899 if (error) 900 return; 901 902 ctx = arg; 903 904 /* Signal error to caller if there's too many segments */ 905 if (nseg > ctx->rl_maxsegs) { 906 ctx->rl_maxsegs = 0; 907 return; 908 } 909 910 /* 911 * Map the segment array into descriptors. Note that we set the 912 * start-of-frame and end-of-frame markers for either TX or RX, but 913 * they really only have meaning in the TX case. (In the RX case, 914 * it's the chip that tells us where packets begin and end.) 915 * We also keep track of the end of the ring and set the 916 * end-of-ring bits as needed, and we set the ownership bits 917 * in all except the very first descriptor. (The caller will 918 * set this descriptor later when it start transmission or 919 * reception.) 920 */ 921 idx = ctx->rl_idx; 922 for (;;) { 923 u_int32_t cmdstat; 924 d = &ctx->rl_ring[idx]; 925 if (le32toh(d->rl_cmdstat) & RL_RDESC_STAT_OWN) { 926 ctx->rl_maxsegs = 0; 927 return; 928 } 929 cmdstat = segs[i].ds_len; 930 d->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 931 d->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 932 if (i == 0) 933 cmdstat |= RL_TDESC_CMD_SOF; 934 else 935 cmdstat |= RL_TDESC_CMD_OWN; 936 if (idx == (RL_RX_DESC_CNT - 1)) 937 cmdstat |= RL_TDESC_CMD_EOR; 938 d->rl_cmdstat = htole32(cmdstat | ctx->rl_flags); 939 i++; 940 if (i == nseg) 941 break; 942 RL_DESC_INC(idx); 943 } 944 945 d->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 946 ctx->rl_maxsegs = nseg; 947 ctx->rl_idx = idx; 948 } 949 950 /* 951 * Map a single buffer address. 952 */ 953 954 static void 955 re_dma_map_addr(arg, segs, nseg, error) 956 void *arg; 957 bus_dma_segment_t *segs; 958 int nseg; 959 int error; 960 { 961 bus_addr_t *addr; 962 963 if (error) 964 return; 965 966 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 967 addr = arg; 968 *addr = segs->ds_addr; 969 } 970 971 static int 972 re_allocmem(dev, sc) 973 device_t dev; 974 struct rl_softc *sc; 975 { 976 int error; 977 int nseg; 978 int i; 979 980 /* 981 * Allocate map for RX mbufs. 982 */ 983 nseg = 32; 984 error = bus_dma_tag_create(sc->rl_parent_tag, ETHER_ALIGN, 0, 985 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 986 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 987 NULL, NULL, &sc->rl_ldata.rl_mtag); 988 if (error) { 989 device_printf(dev, "could not allocate dma tag\n"); 990 return (ENOMEM); 991 } 992 993 /* 994 * Allocate map for TX descriptor list. 995 */ 996 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 997 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 998 NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 999 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1000 if (error) { 1001 device_printf(dev, "could not allocate dma tag\n"); 1002 return (ENOMEM); 1003 } 1004 1005 /* Allocate DMA'able memory for the TX ring */ 1006 1007 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1008 (void **)&sc->rl_ldata.rl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1009 &sc->rl_ldata.rl_tx_list_map); 1010 if (error) 1011 return (ENOMEM); 1012 1013 /* Load the map for the TX ring. */ 1014 1015 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1016 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1017 RL_TX_LIST_SZ, re_dma_map_addr, 1018 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1019 1020 /* Create DMA maps for TX buffers */ 1021 1022 for (i = 0; i < RL_TX_DESC_CNT; i++) { 1023 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1024 &sc->rl_ldata.rl_tx_dmamap[i]); 1025 if (error) { 1026 device_printf(dev, "can't create DMA map for TX\n"); 1027 return (ENOMEM); 1028 } 1029 } 1030 1031 /* 1032 * Allocate map for RX descriptor list. 1033 */ 1034 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1035 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1036 NULL, RL_RX_LIST_SZ, 1, RL_RX_LIST_SZ, BUS_DMA_ALLOCNOW, 1037 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1038 if (error) { 1039 device_printf(dev, "could not allocate dma tag\n"); 1040 return (ENOMEM); 1041 } 1042 1043 /* Allocate DMA'able memory for the RX ring */ 1044 1045 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1046 (void **)&sc->rl_ldata.rl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1047 &sc->rl_ldata.rl_rx_list_map); 1048 if (error) 1049 return (ENOMEM); 1050 1051 /* Load the map for the RX ring. */ 1052 1053 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1054 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1055 RL_RX_LIST_SZ, re_dma_map_addr, 1056 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1057 1058 /* Create DMA maps for RX buffers */ 1059 1060 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1061 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1062 &sc->rl_ldata.rl_rx_dmamap[i]); 1063 if (error) { 1064 device_printf(dev, "can't create DMA map for RX\n"); 1065 return (ENOMEM); 1066 } 1067 } 1068 1069 return (0); 1070 } 1071 1072 /* 1073 * Attach the interface. Allocate softc structures, do ifmedia 1074 * setup and ethernet/BPF attach. 1075 */ 1076 static int 1077 re_attach(dev) 1078 device_t dev; 1079 { 1080 u_char eaddr[ETHER_ADDR_LEN]; 1081 u_int16_t as[3]; 1082 struct rl_softc *sc; 1083 struct ifnet *ifp; 1084 struct rl_hwrev *hw_rev; 1085 int hwrev; 1086 u_int16_t re_did = 0; 1087 int error = 0, rid, i; 1088 1089 sc = device_get_softc(dev); 1090 1091 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1092 MTX_DEF); 1093 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1094 1095 /* 1096 * Map control/status registers. 1097 */ 1098 pci_enable_busmaster(dev); 1099 1100 rid = RL_RID; 1101 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 1102 RF_ACTIVE); 1103 1104 if (sc->rl_res == NULL) { 1105 device_printf(dev, "couldn't map ports/memory\n"); 1106 error = ENXIO; 1107 goto fail; 1108 } 1109 1110 sc->rl_btag = rman_get_bustag(sc->rl_res); 1111 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1112 1113 /* Allocate interrupt */ 1114 rid = 0; 1115 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1116 RF_SHAREABLE | RF_ACTIVE); 1117 1118 if (sc->rl_irq == NULL) { 1119 device_printf(dev, "couldn't map interrupt\n"); 1120 error = ENXIO; 1121 goto fail; 1122 } 1123 1124 /* Reset the adapter. */ 1125 RL_LOCK(sc); 1126 re_reset(sc); 1127 RL_UNLOCK(sc); 1128 1129 hw_rev = re_hwrevs; 1130 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 1131 while (hw_rev->rl_desc != NULL) { 1132 if (hw_rev->rl_rev == hwrev) { 1133 sc->rl_type = hw_rev->rl_type; 1134 break; 1135 } 1136 hw_rev++; 1137 } 1138 1139 if (sc->rl_type == RL_8169) { 1140 1141 /* Set RX length mask */ 1142 1143 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1144 1145 /* Force station address autoload from the EEPROM */ 1146 1147 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_AUTOLOAD); 1148 for (i = 0; i < RL_TIMEOUT; i++) { 1149 if (!(CSR_READ_1(sc, RL_EECMD) & RL_EEMODE_AUTOLOAD)) 1150 break; 1151 DELAY(100); 1152 } 1153 if (i == RL_TIMEOUT) 1154 device_printf(dev, "eeprom autoload timed out\n"); 1155 1156 for (i = 0; i < ETHER_ADDR_LEN; i++) 1157 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1158 } else { 1159 1160 /* Set RX length mask */ 1161 1162 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1163 1164 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 1165 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1, 0); 1166 if (re_did != 0x8129) 1167 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 1168 1169 /* 1170 * Get station address from the EEPROM. 1171 */ 1172 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0); 1173 for (i = 0; i < 3; i++) { 1174 eaddr[(i * 2) + 0] = as[i] & 0xff; 1175 eaddr[(i * 2) + 1] = as[i] >> 8; 1176 } 1177 } 1178 1179 /* 1180 * Allocate the parent bus DMA tag appropriate for PCI. 1181 */ 1182 #define RL_NSEG_NEW 32 1183 error = bus_dma_tag_create(NULL, /* parent */ 1184 1, 0, /* alignment, boundary */ 1185 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1186 BUS_SPACE_MAXADDR, /* highaddr */ 1187 NULL, NULL, /* filter, filterarg */ 1188 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 1189 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1190 BUS_DMA_ALLOCNOW, /* flags */ 1191 NULL, NULL, /* lockfunc, lockarg */ 1192 &sc->rl_parent_tag); 1193 if (error) 1194 goto fail; 1195 1196 error = re_allocmem(dev, sc); 1197 1198 if (error) 1199 goto fail; 1200 1201 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1202 if (ifp == NULL) { 1203 device_printf(dev, "can not if_alloc()\n"); 1204 error = ENOSPC; 1205 goto fail; 1206 } 1207 1208 /* Do MII setup */ 1209 if (mii_phy_probe(dev, &sc->rl_miibus, 1210 re_ifmedia_upd, re_ifmedia_sts)) { 1211 device_printf(dev, "MII without any phy!\n"); 1212 error = ENXIO; 1213 goto fail; 1214 } 1215 1216 ifp->if_softc = sc; 1217 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1218 ifp->if_mtu = ETHERMTU; 1219 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1220 ifp->if_ioctl = re_ioctl; 1221 ifp->if_capabilities = IFCAP_VLAN_MTU; 1222 ifp->if_start = re_start; 1223 ifp->if_hwassist = /*RE_CSUM_FEATURES*/0; 1224 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1225 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM; 1226 #ifdef DEVICE_POLLING 1227 ifp->if_capabilities |= IFCAP_POLLING; 1228 #endif 1229 ifp->if_watchdog = re_watchdog; 1230 ifp->if_init = re_init; 1231 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1232 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1233 IFQ_SET_READY(&ifp->if_snd); 1234 1235 /* 1236 * Call MI attach routine. 1237 */ 1238 ether_ifattach(ifp, eaddr); 1239 1240 /* Perform hardware diagnostic. */ 1241 error = re_diag(sc); 1242 1243 if (error) { 1244 device_printf(dev, "attach aborted due to hardware diag failure\n"); 1245 ether_ifdetach(ifp); 1246 goto fail; 1247 } 1248 1249 /* Hook interrupt last to avoid having to lock softc */ 1250 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET | INTR_MPSAFE, 1251 re_intr, sc, &sc->rl_intrhand); 1252 if (error) { 1253 device_printf(dev, "couldn't set up irq\n"); 1254 ether_ifdetach(ifp); 1255 } 1256 1257 fail: 1258 if (error) 1259 re_detach(dev); 1260 1261 return (error); 1262 } 1263 1264 /* 1265 * Shutdown hardware and free up resources. This can be called any 1266 * time after the mutex has been initialized. It is called in both 1267 * the error case in attach and the normal detach case so it needs 1268 * to be careful about only freeing resources that have actually been 1269 * allocated. 1270 */ 1271 static int 1272 re_detach(dev) 1273 device_t dev; 1274 { 1275 struct rl_softc *sc; 1276 struct ifnet *ifp; 1277 int i; 1278 1279 sc = device_get_softc(dev); 1280 ifp = sc->rl_ifp; 1281 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1282 1283 #ifdef DEVICE_POLLING 1284 if (ifp->if_capenable & IFCAP_POLLING) 1285 ether_poll_deregister(ifp); 1286 #endif 1287 1288 /* These should only be active if attach succeeded */ 1289 if (device_is_attached(dev)) { 1290 RL_LOCK(sc); 1291 #if 0 1292 sc->suspended = 1; 1293 #endif 1294 re_stop(sc); 1295 RL_UNLOCK(sc); 1296 callout_drain(&sc->rl_stat_callout); 1297 /* 1298 * Force off the IFF_UP flag here, in case someone 1299 * still had a BPF descriptor attached to this 1300 * interface. If they do, ether_ifdetach() will cause 1301 * the BPF code to try and clear the promisc mode 1302 * flag, which will bubble down to re_ioctl(), 1303 * which will try to call re_init() again. This will 1304 * turn the NIC back on and restart the MII ticker, 1305 * which will panic the system when the kernel tries 1306 * to invoke the re_tick() function that isn't there 1307 * anymore. 1308 */ 1309 ifp->if_flags &= ~IFF_UP; 1310 ether_ifdetach(ifp); 1311 } 1312 if (sc->rl_miibus) 1313 device_delete_child(dev, sc->rl_miibus); 1314 bus_generic_detach(dev); 1315 1316 /* 1317 * The rest is resource deallocation, so we should already be 1318 * stopped here. 1319 */ 1320 1321 if (sc->rl_intrhand) 1322 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1323 if (ifp != NULL) 1324 if_free(ifp); 1325 if (sc->rl_irq) 1326 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1327 if (sc->rl_res) 1328 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1329 1330 1331 /* Unload and free the RX DMA ring memory and map */ 1332 1333 if (sc->rl_ldata.rl_rx_list_tag) { 1334 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1335 sc->rl_ldata.rl_rx_list_map); 1336 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1337 sc->rl_ldata.rl_rx_list, 1338 sc->rl_ldata.rl_rx_list_map); 1339 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1340 } 1341 1342 /* Unload and free the TX DMA ring memory and map */ 1343 1344 if (sc->rl_ldata.rl_tx_list_tag) { 1345 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1346 sc->rl_ldata.rl_tx_list_map); 1347 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1348 sc->rl_ldata.rl_tx_list, 1349 sc->rl_ldata.rl_tx_list_map); 1350 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1351 } 1352 1353 /* Destroy all the RX and TX buffer maps */ 1354 1355 if (sc->rl_ldata.rl_mtag) { 1356 for (i = 0; i < RL_TX_DESC_CNT; i++) 1357 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1358 sc->rl_ldata.rl_tx_dmamap[i]); 1359 for (i = 0; i < RL_RX_DESC_CNT; i++) 1360 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1361 sc->rl_ldata.rl_rx_dmamap[i]); 1362 bus_dma_tag_destroy(sc->rl_ldata.rl_mtag); 1363 } 1364 1365 /* Unload and free the stats buffer and map */ 1366 1367 if (sc->rl_ldata.rl_stag) { 1368 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1369 sc->rl_ldata.rl_rx_list_map); 1370 bus_dmamem_free(sc->rl_ldata.rl_stag, 1371 sc->rl_ldata.rl_stats, 1372 sc->rl_ldata.rl_smap); 1373 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1374 } 1375 1376 if (sc->rl_parent_tag) 1377 bus_dma_tag_destroy(sc->rl_parent_tag); 1378 1379 mtx_destroy(&sc->rl_mtx); 1380 1381 return (0); 1382 } 1383 1384 static int 1385 re_newbuf(sc, idx, m) 1386 struct rl_softc *sc; 1387 int idx; 1388 struct mbuf *m; 1389 { 1390 struct rl_dmaload_arg arg; 1391 struct mbuf *n = NULL; 1392 int error; 1393 1394 if (m == NULL) { 1395 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1396 if (n == NULL) 1397 return (ENOBUFS); 1398 m = n; 1399 } else 1400 m->m_data = m->m_ext.ext_buf; 1401 1402 m->m_len = m->m_pkthdr.len = MCLBYTES; 1403 #ifdef RE_FIXUP_RX 1404 /* 1405 * This is part of an evil trick to deal with non-x86 platforms. 1406 * The RealTek chip requires RX buffers to be aligned on 64-bit 1407 * boundaries, but that will hose non-x86 machines. To get around 1408 * this, we leave some empty space at the start of each buffer 1409 * and for non-x86 hosts, we copy the buffer back six bytes 1410 * to achieve word alignment. This is slightly more efficient 1411 * than allocating a new buffer, copying the contents, and 1412 * discarding the old buffer. 1413 */ 1414 m_adj(m, RE_ETHER_ALIGN); 1415 #endif 1416 arg.sc = sc; 1417 arg.rl_idx = idx; 1418 arg.rl_maxsegs = 1; 1419 arg.rl_flags = 0; 1420 arg.rl_ring = sc->rl_ldata.rl_rx_list; 1421 1422 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, 1423 sc->rl_ldata.rl_rx_dmamap[idx], m, re_dma_map_desc, 1424 &arg, BUS_DMA_NOWAIT); 1425 if (error || arg.rl_maxsegs != 1) { 1426 if (n != NULL) 1427 m_freem(n); 1428 return (ENOMEM); 1429 } 1430 1431 sc->rl_ldata.rl_rx_list[idx].rl_cmdstat |= htole32(RL_RDESC_CMD_OWN); 1432 sc->rl_ldata.rl_rx_mbuf[idx] = m; 1433 1434 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1435 sc->rl_ldata.rl_rx_dmamap[idx], 1436 BUS_DMASYNC_PREREAD); 1437 1438 return (0); 1439 } 1440 1441 #ifdef RE_FIXUP_RX 1442 static __inline void 1443 re_fixup_rx(m) 1444 struct mbuf *m; 1445 { 1446 int i; 1447 uint16_t *src, *dst; 1448 1449 src = mtod(m, uint16_t *); 1450 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1451 1452 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1453 *dst++ = *src++; 1454 1455 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1456 1457 return; 1458 } 1459 #endif 1460 1461 static int 1462 re_tx_list_init(sc) 1463 struct rl_softc *sc; 1464 { 1465 1466 RL_LOCK_ASSERT(sc); 1467 1468 bzero ((char *)sc->rl_ldata.rl_tx_list, RL_TX_LIST_SZ); 1469 bzero ((char *)&sc->rl_ldata.rl_tx_mbuf, 1470 (RL_TX_DESC_CNT * sizeof(struct mbuf *))); 1471 1472 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1473 sc->rl_ldata.rl_tx_list_map, BUS_DMASYNC_PREWRITE); 1474 sc->rl_ldata.rl_tx_prodidx = 0; 1475 sc->rl_ldata.rl_tx_considx = 0; 1476 sc->rl_ldata.rl_tx_free = RL_TX_DESC_CNT; 1477 1478 return (0); 1479 } 1480 1481 static int 1482 re_rx_list_init(sc) 1483 struct rl_softc *sc; 1484 { 1485 int i; 1486 1487 bzero ((char *)sc->rl_ldata.rl_rx_list, RL_RX_LIST_SZ); 1488 bzero ((char *)&sc->rl_ldata.rl_rx_mbuf, 1489 (RL_RX_DESC_CNT * sizeof(struct mbuf *))); 1490 1491 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1492 if (re_newbuf(sc, i, NULL) == ENOBUFS) 1493 return (ENOBUFS); 1494 } 1495 1496 /* Flush the RX descriptors */ 1497 1498 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1499 sc->rl_ldata.rl_rx_list_map, 1500 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1501 1502 sc->rl_ldata.rl_rx_prodidx = 0; 1503 sc->rl_head = sc->rl_tail = NULL; 1504 1505 return (0); 1506 } 1507 1508 /* 1509 * RX handler for C+ and 8169. For the gigE chips, we support 1510 * the reception of jumbo frames that have been fragmented 1511 * across multiple 2K mbuf cluster buffers. 1512 */ 1513 static void 1514 re_rxeof(sc) 1515 struct rl_softc *sc; 1516 { 1517 struct mbuf *m; 1518 struct ifnet *ifp; 1519 int i, total_len; 1520 struct rl_desc *cur_rx; 1521 u_int32_t rxstat, rxvlan; 1522 1523 RL_LOCK_ASSERT(sc); 1524 1525 ifp = sc->rl_ifp; 1526 i = sc->rl_ldata.rl_rx_prodidx; 1527 1528 /* Invalidate the descriptor memory */ 1529 1530 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1531 sc->rl_ldata.rl_rx_list_map, 1532 BUS_DMASYNC_POSTREAD); 1533 1534 while (!RL_OWN(&sc->rl_ldata.rl_rx_list[i])) { 1535 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1536 m = sc->rl_ldata.rl_rx_mbuf[i]; 1537 total_len = RL_RXBYTES(cur_rx); 1538 rxstat = le32toh(cur_rx->rl_cmdstat); 1539 rxvlan = le32toh(cur_rx->rl_vlanctl); 1540 1541 /* Invalidate the RX mbuf and unload its map */ 1542 1543 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1544 sc->rl_ldata.rl_rx_dmamap[i], 1545 BUS_DMASYNC_POSTWRITE); 1546 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1547 sc->rl_ldata.rl_rx_dmamap[i]); 1548 1549 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1550 m->m_len = RE_RX_DESC_BUFLEN; 1551 if (sc->rl_head == NULL) 1552 sc->rl_head = sc->rl_tail = m; 1553 else { 1554 m->m_flags &= ~M_PKTHDR; 1555 sc->rl_tail->m_next = m; 1556 sc->rl_tail = m; 1557 } 1558 re_newbuf(sc, i, NULL); 1559 RL_DESC_INC(i); 1560 continue; 1561 } 1562 1563 /* 1564 * NOTE: for the 8139C+, the frame length field 1565 * is always 12 bits in size, but for the gigE chips, 1566 * it is 13 bits (since the max RX frame length is 16K). 1567 * Unfortunately, all 32 bits in the status word 1568 * were already used, so to make room for the extra 1569 * length bit, RealTek took out the 'frame alignment 1570 * error' bit and shifted the other status bits 1571 * over one slot. The OWN, EOR, FS and LS bits are 1572 * still in the same places. We have already extracted 1573 * the frame length and checked the OWN bit, so rather 1574 * than using an alternate bit mapping, we shift the 1575 * status bits one space to the right so we can evaluate 1576 * them using the 8169 status as though it was in the 1577 * same format as that of the 8139C+. 1578 */ 1579 if (sc->rl_type == RL_8169) 1580 rxstat >>= 1; 1581 1582 /* 1583 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 1584 * set, but if CRC is clear, it will still be a valid frame. 1585 */ 1586 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 && 1587 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) { 1588 ifp->if_ierrors++; 1589 /* 1590 * If this is part of a multi-fragment packet, 1591 * discard all the pieces. 1592 */ 1593 if (sc->rl_head != NULL) { 1594 m_freem(sc->rl_head); 1595 sc->rl_head = sc->rl_tail = NULL; 1596 } 1597 re_newbuf(sc, i, m); 1598 RL_DESC_INC(i); 1599 continue; 1600 } 1601 1602 /* 1603 * If allocating a replacement mbuf fails, 1604 * reload the current one. 1605 */ 1606 1607 if (re_newbuf(sc, i, NULL)) { 1608 ifp->if_ierrors++; 1609 if (sc->rl_head != NULL) { 1610 m_freem(sc->rl_head); 1611 sc->rl_head = sc->rl_tail = NULL; 1612 } 1613 re_newbuf(sc, i, m); 1614 RL_DESC_INC(i); 1615 continue; 1616 } 1617 1618 RL_DESC_INC(i); 1619 1620 if (sc->rl_head != NULL) { 1621 m->m_len = total_len % RE_RX_DESC_BUFLEN; 1622 if (m->m_len == 0) 1623 m->m_len = RE_RX_DESC_BUFLEN; 1624 /* 1625 * Special case: if there's 4 bytes or less 1626 * in this buffer, the mbuf can be discarded: 1627 * the last 4 bytes is the CRC, which we don't 1628 * care about anyway. 1629 */ 1630 if (m->m_len <= ETHER_CRC_LEN) { 1631 sc->rl_tail->m_len -= 1632 (ETHER_CRC_LEN - m->m_len); 1633 m_freem(m); 1634 } else { 1635 m->m_len -= ETHER_CRC_LEN; 1636 m->m_flags &= ~M_PKTHDR; 1637 sc->rl_tail->m_next = m; 1638 } 1639 m = sc->rl_head; 1640 sc->rl_head = sc->rl_tail = NULL; 1641 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1642 } else 1643 m->m_pkthdr.len = m->m_len = 1644 (total_len - ETHER_CRC_LEN); 1645 1646 #ifdef RE_FIXUP_RX 1647 re_fixup_rx(m); 1648 #endif 1649 ifp->if_ipackets++; 1650 m->m_pkthdr.rcvif = ifp; 1651 1652 /* Do RX checksumming if enabled */ 1653 1654 if (ifp->if_capenable & IFCAP_RXCSUM) { 1655 1656 /* Check IP header checksum */ 1657 if (rxstat & RL_RDESC_STAT_PROTOID) 1658 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1659 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1660 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1661 1662 /* Check TCP/UDP checksum */ 1663 if ((RL_TCPPKT(rxstat) && 1664 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1665 (RL_UDPPKT(rxstat) && 1666 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1667 m->m_pkthdr.csum_flags |= 1668 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1669 m->m_pkthdr.csum_data = 0xffff; 1670 } 1671 } 1672 1673 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 1674 VLAN_INPUT_TAG(ifp, m, 1675 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA))); 1676 if (m == NULL) 1677 continue; 1678 } 1679 RL_UNLOCK(sc); 1680 (*ifp->if_input)(ifp, m); 1681 RL_LOCK(sc); 1682 } 1683 1684 /* Flush the RX DMA ring */ 1685 1686 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1687 sc->rl_ldata.rl_rx_list_map, 1688 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1689 1690 sc->rl_ldata.rl_rx_prodidx = i; 1691 } 1692 1693 static void 1694 re_txeof(sc) 1695 struct rl_softc *sc; 1696 { 1697 struct ifnet *ifp; 1698 u_int32_t txstat; 1699 int idx; 1700 1701 ifp = sc->rl_ifp; 1702 idx = sc->rl_ldata.rl_tx_considx; 1703 1704 /* Invalidate the TX descriptor list */ 1705 1706 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1707 sc->rl_ldata.rl_tx_list_map, 1708 BUS_DMASYNC_POSTREAD); 1709 1710 while (idx != sc->rl_ldata.rl_tx_prodidx) { 1711 1712 txstat = le32toh(sc->rl_ldata.rl_tx_list[idx].rl_cmdstat); 1713 if (txstat & RL_TDESC_CMD_OWN) 1714 break; 1715 1716 /* 1717 * We only stash mbufs in the last descriptor 1718 * in a fragment chain, which also happens to 1719 * be the only place where the TX status bits 1720 * are valid. 1721 */ 1722 1723 if (txstat & RL_TDESC_CMD_EOF) { 1724 m_freem(sc->rl_ldata.rl_tx_mbuf[idx]); 1725 sc->rl_ldata.rl_tx_mbuf[idx] = NULL; 1726 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1727 sc->rl_ldata.rl_tx_dmamap[idx]); 1728 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 1729 RL_TDESC_STAT_COLCNT)) 1730 ifp->if_collisions++; 1731 if (txstat & RL_TDESC_STAT_TXERRSUM) 1732 ifp->if_oerrors++; 1733 else 1734 ifp->if_opackets++; 1735 } 1736 sc->rl_ldata.rl_tx_free++; 1737 RL_DESC_INC(idx); 1738 } 1739 1740 /* No changes made to the TX ring, so no flush needed */ 1741 1742 if (idx != sc->rl_ldata.rl_tx_considx) { 1743 sc->rl_ldata.rl_tx_considx = idx; 1744 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1745 ifp->if_timer = 0; 1746 } 1747 1748 /* 1749 * If not all descriptors have been released reaped yet, 1750 * reload the timer so that we will eventually get another 1751 * interrupt that will cause us to re-enter this routine. 1752 * This is done in case the transmitter has gone idle. 1753 */ 1754 if (sc->rl_ldata.rl_tx_free != RL_TX_DESC_CNT) 1755 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 1756 } 1757 1758 static void 1759 re_tick(xsc) 1760 void *xsc; 1761 { 1762 struct rl_softc *sc; 1763 struct mii_data *mii; 1764 1765 sc = xsc; 1766 1767 RL_LOCK_ASSERT(sc); 1768 1769 mii = device_get_softc(sc->rl_miibus); 1770 1771 mii_tick(mii); 1772 1773 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 1774 } 1775 1776 #ifdef DEVICE_POLLING 1777 static void 1778 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1779 { 1780 struct rl_softc *sc = ifp->if_softc; 1781 1782 RL_LOCK(sc); 1783 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1784 re_poll_locked(ifp, cmd, count); 1785 RL_UNLOCK(sc); 1786 } 1787 1788 static void 1789 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1790 { 1791 struct rl_softc *sc = ifp->if_softc; 1792 1793 RL_LOCK_ASSERT(sc); 1794 1795 sc->rxcycles = count; 1796 re_rxeof(sc); 1797 re_txeof(sc); 1798 1799 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1800 re_start_locked(ifp); 1801 1802 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1803 u_int16_t status; 1804 1805 status = CSR_READ_2(sc, RL_ISR); 1806 if (status == 0xffff) 1807 return; 1808 if (status) 1809 CSR_WRITE_2(sc, RL_ISR, status); 1810 1811 /* 1812 * XXX check behaviour on receiver stalls. 1813 */ 1814 1815 if (status & RL_ISR_SYSTEM_ERR) { 1816 re_reset(sc); 1817 re_init_locked(sc); 1818 } 1819 } 1820 } 1821 #endif /* DEVICE_POLLING */ 1822 1823 static void 1824 re_intr(arg) 1825 void *arg; 1826 { 1827 struct rl_softc *sc; 1828 struct ifnet *ifp; 1829 u_int16_t status; 1830 1831 sc = arg; 1832 1833 RL_LOCK(sc); 1834 1835 ifp = sc->rl_ifp; 1836 1837 if (sc->suspended || !(ifp->if_flags & IFF_UP)) 1838 goto done_locked; 1839 1840 #ifdef DEVICE_POLLING 1841 if (ifp->if_capenable & IFCAP_POLLING) 1842 goto done_locked; 1843 #endif 1844 1845 for (;;) { 1846 1847 status = CSR_READ_2(sc, RL_ISR); 1848 /* If the card has gone away the read returns 0xffff. */ 1849 if (status == 0xffff) 1850 break; 1851 if (status) 1852 CSR_WRITE_2(sc, RL_ISR, status); 1853 1854 if ((status & RL_INTRS_CPLUS) == 0) 1855 break; 1856 1857 if (((status & RL_ISR_RX_OK) || 1858 (status & RL_ISR_RX_ERR)) && 1859 ifp->if_drv_flags & IFF_DRV_RUNNING) 1860 re_rxeof(sc); 1861 1862 if (((status & RL_ISR_TIMEOUT_EXPIRED) || 1863 (status & RL_ISR_TX_ERR) || 1864 (status & RL_ISR_TX_DESC_UNAVAIL)) && 1865 ifp->if_drv_flags & IFF_DRV_RUNNING) 1866 re_txeof(sc); 1867 1868 if (status & RL_ISR_SYSTEM_ERR) { 1869 re_reset(sc); 1870 re_init_locked(sc); 1871 } 1872 1873 if (status & RL_ISR_LINKCHG) { 1874 callout_stop(&sc->rl_stat_callout); 1875 re_tick(sc); 1876 } 1877 } 1878 1879 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1880 re_start_locked(ifp); 1881 1882 done_locked: 1883 RL_UNLOCK(sc); 1884 } 1885 1886 static int 1887 re_encap(sc, m_head, idx) 1888 struct rl_softc *sc; 1889 struct mbuf **m_head; 1890 int *idx; 1891 { 1892 struct mbuf *m_new = NULL; 1893 struct rl_dmaload_arg arg; 1894 bus_dmamap_t map; 1895 int error; 1896 struct m_tag *mtag; 1897 1898 RL_LOCK_ASSERT(sc); 1899 1900 if (sc->rl_ldata.rl_tx_free <= 4) 1901 return (EFBIG); 1902 1903 /* 1904 * Set up checksum offload. Note: checksum offload bits must 1905 * appear in all descriptors of a multi-descriptor transmit 1906 * attempt. This is according to testing done with an 8169 1907 * chip. This is a requirement. 1908 */ 1909 1910 arg.rl_flags = 0; 1911 1912 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) 1913 arg.rl_flags |= RL_TDESC_CMD_IPCSUM; 1914 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) 1915 arg.rl_flags |= RL_TDESC_CMD_TCPCSUM; 1916 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) 1917 arg.rl_flags |= RL_TDESC_CMD_UDPCSUM; 1918 1919 arg.sc = sc; 1920 arg.rl_idx = *idx; 1921 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 1922 if (arg.rl_maxsegs > 4) 1923 arg.rl_maxsegs -= 4; 1924 arg.rl_ring = sc->rl_ldata.rl_tx_list; 1925 1926 map = sc->rl_ldata.rl_tx_dmamap[*idx]; 1927 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 1928 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1929 1930 if (error && error != EFBIG) { 1931 if_printf(sc->rl_ifp, "can't map mbuf (error %d)\n", error); 1932 return (ENOBUFS); 1933 } 1934 1935 /* Too many segments to map, coalesce into a single mbuf */ 1936 1937 if (error || arg.rl_maxsegs == 0) { 1938 m_new = m_defrag(*m_head, M_DONTWAIT); 1939 if (m_new == NULL) 1940 return (ENOBUFS); 1941 else 1942 *m_head = m_new; 1943 1944 arg.sc = sc; 1945 arg.rl_idx = *idx; 1946 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 1947 arg.rl_ring = sc->rl_ldata.rl_tx_list; 1948 1949 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 1950 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1951 if (error) { 1952 if_printf(sc->rl_ifp, "can't map mbuf (error %d)\n", 1953 error); 1954 return (EFBIG); 1955 } 1956 } 1957 1958 /* 1959 * Insure that the map for this transmission 1960 * is placed at the array index of the last descriptor 1961 * in this chain. (Swap last and first dmamaps.) 1962 */ 1963 sc->rl_ldata.rl_tx_dmamap[*idx] = 1964 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx]; 1965 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx] = map; 1966 1967 sc->rl_ldata.rl_tx_mbuf[arg.rl_idx] = *m_head; 1968 sc->rl_ldata.rl_tx_free -= arg.rl_maxsegs; 1969 1970 /* 1971 * Set up hardware VLAN tagging. Note: vlan tag info must 1972 * appear in the first descriptor of a multi-descriptor 1973 * transmission attempt. 1974 */ 1975 1976 mtag = VLAN_OUTPUT_TAG(sc->rl_ifp, *m_head); 1977 if (mtag != NULL) 1978 sc->rl_ldata.rl_tx_list[*idx].rl_vlanctl = 1979 htole32(htons(VLAN_TAG_VALUE(mtag)) | RL_TDESC_VLANCTL_TAG); 1980 1981 /* Transfer ownership of packet to the chip. */ 1982 1983 sc->rl_ldata.rl_tx_list[arg.rl_idx].rl_cmdstat |= 1984 htole32(RL_TDESC_CMD_OWN); 1985 if (*idx != arg.rl_idx) 1986 sc->rl_ldata.rl_tx_list[*idx].rl_cmdstat |= 1987 htole32(RL_TDESC_CMD_OWN); 1988 1989 RL_DESC_INC(arg.rl_idx); 1990 *idx = arg.rl_idx; 1991 1992 return (0); 1993 } 1994 1995 static void 1996 re_start(ifp) 1997 struct ifnet *ifp; 1998 { 1999 struct rl_softc *sc; 2000 2001 sc = ifp->if_softc; 2002 RL_LOCK(sc); 2003 re_start_locked(ifp); 2004 RL_UNLOCK(sc); 2005 } 2006 2007 /* 2008 * Main transmit routine for C+ and gigE NICs. 2009 */ 2010 static void 2011 re_start_locked(ifp) 2012 struct ifnet *ifp; 2013 { 2014 struct rl_softc *sc; 2015 struct mbuf *m_head = NULL; 2016 int idx, queued = 0; 2017 2018 sc = ifp->if_softc; 2019 2020 RL_LOCK_ASSERT(sc); 2021 2022 idx = sc->rl_ldata.rl_tx_prodidx; 2023 2024 while (sc->rl_ldata.rl_tx_mbuf[idx] == NULL) { 2025 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2026 if (m_head == NULL) 2027 break; 2028 2029 if (re_encap(sc, &m_head, &idx)) { 2030 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2031 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2032 break; 2033 } 2034 2035 /* 2036 * If there's a BPF listener, bounce a copy of this frame 2037 * to him. 2038 */ 2039 BPF_MTAP(ifp, m_head); 2040 2041 queued++; 2042 } 2043 2044 if (queued == 0) 2045 return; 2046 2047 /* Flush the TX descriptors */ 2048 2049 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2050 sc->rl_ldata.rl_tx_list_map, 2051 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2052 2053 sc->rl_ldata.rl_tx_prodidx = idx; 2054 2055 /* 2056 * RealTek put the TX poll request register in a different 2057 * location on the 8169 gigE chip. I don't know why. 2058 */ 2059 2060 if (sc->rl_type == RL_8169) 2061 CSR_WRITE_2(sc, RL_GTXSTART, RL_TXSTART_START); 2062 else 2063 CSR_WRITE_2(sc, RL_TXSTART, RL_TXSTART_START); 2064 2065 /* 2066 * Use the countdown timer for interrupt moderation. 2067 * 'TX done' interrupts are disabled. Instead, we reset the 2068 * countdown timer, which will begin counting until it hits 2069 * the value in the TIMERINT register, and then trigger an 2070 * interrupt. Each time we write to the TIMERCNT register, 2071 * the timer count is reset to 0. 2072 */ 2073 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2074 2075 /* 2076 * Set a timeout in case the chip goes out to lunch. 2077 */ 2078 ifp->if_timer = 5; 2079 } 2080 2081 static void 2082 re_init(xsc) 2083 void *xsc; 2084 { 2085 struct rl_softc *sc = xsc; 2086 2087 RL_LOCK(sc); 2088 re_init_locked(sc); 2089 RL_UNLOCK(sc); 2090 } 2091 2092 static void 2093 re_init_locked(sc) 2094 struct rl_softc *sc; 2095 { 2096 struct ifnet *ifp = sc->rl_ifp; 2097 struct mii_data *mii; 2098 u_int32_t rxcfg = 0; 2099 union { 2100 uint32_t align_dummy; 2101 u_char eaddr[ETHER_ADDR_LEN]; 2102 } eaddr; 2103 2104 RL_LOCK_ASSERT(sc); 2105 2106 mii = device_get_softc(sc->rl_miibus); 2107 2108 /* 2109 * Cancel pending I/O and free all RX/TX buffers. 2110 */ 2111 re_stop(sc); 2112 2113 /* 2114 * Enable C+ RX and TX mode, as well as VLAN stripping and 2115 * RX checksum offload. We must configure the C+ register 2116 * before all others. 2117 */ 2118 CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB| 2119 RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW| 2120 RL_CPLUSCMD_VLANSTRIP| 2121 (ifp->if_capenable & IFCAP_RXCSUM ? 2122 RL_CPLUSCMD_RXCSUM_ENB : 0)); 2123 2124 /* 2125 * Init our MAC address. Even though the chipset 2126 * documentation doesn't mention it, we need to enter "Config 2127 * register write enable" mode to modify the ID registers. 2128 */ 2129 /* Copy MAC address on stack to align. */ 2130 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 2131 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2132 CSR_WRITE_STREAM_4(sc, RL_IDR0, 2133 *(u_int32_t *)(&eaddr.eaddr[0])); 2134 CSR_WRITE_STREAM_4(sc, RL_IDR4, 2135 *(u_int32_t *)(&eaddr.eaddr[4])); 2136 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2137 2138 /* 2139 * For C+ mode, initialize the RX descriptors and mbufs. 2140 */ 2141 re_rx_list_init(sc); 2142 re_tx_list_init(sc); 2143 2144 /* 2145 * Enable transmit and receive. 2146 */ 2147 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2148 2149 /* 2150 * Set the initial TX and RX configuration. 2151 */ 2152 if (sc->rl_testmode) { 2153 if (sc->rl_type == RL_8169) 2154 CSR_WRITE_4(sc, RL_TXCFG, 2155 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2156 else 2157 CSR_WRITE_4(sc, RL_TXCFG, 2158 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2159 } else 2160 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2161 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 2162 2163 /* Set the individual bit to receive frames for this host only. */ 2164 rxcfg = CSR_READ_4(sc, RL_RXCFG); 2165 rxcfg |= RL_RXCFG_RX_INDIV; 2166 2167 /* If we want promiscuous mode, set the allframes bit. */ 2168 if (ifp->if_flags & IFF_PROMISC) 2169 rxcfg |= RL_RXCFG_RX_ALLPHYS; 2170 else 2171 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 2172 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2173 2174 /* 2175 * Set capture broadcast bit to capture broadcast frames. 2176 */ 2177 if (ifp->if_flags & IFF_BROADCAST) 2178 rxcfg |= RL_RXCFG_RX_BROAD; 2179 else 2180 rxcfg &= ~RL_RXCFG_RX_BROAD; 2181 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2182 2183 /* 2184 * Program the multicast filter, if necessary. 2185 */ 2186 re_setmulti(sc); 2187 2188 #ifdef DEVICE_POLLING 2189 /* 2190 * Disable interrupts if we are polling. 2191 */ 2192 if (ifp->if_capenable & IFCAP_POLLING) 2193 CSR_WRITE_2(sc, RL_IMR, 0); 2194 else /* otherwise ... */ 2195 #endif 2196 /* 2197 * Enable interrupts. 2198 */ 2199 if (sc->rl_testmode) 2200 CSR_WRITE_2(sc, RL_IMR, 0); 2201 else 2202 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2203 2204 /* Set initial TX threshold */ 2205 sc->rl_txthresh = RL_TX_THRESH_INIT; 2206 2207 /* Start RX/TX process. */ 2208 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2209 #ifdef notdef 2210 /* Enable receiver and transmitter. */ 2211 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2212 #endif 2213 /* 2214 * Load the addresses of the RX and TX lists into the chip. 2215 */ 2216 2217 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2218 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2219 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2220 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2221 2222 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2223 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2224 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2225 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2226 2227 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2228 2229 /* 2230 * Initialize the timer interrupt register so that 2231 * a timer interrupt will be generated once the timer 2232 * reaches a certain number of ticks. The timer is 2233 * reloaded on each transmit. This gives us TX interrupt 2234 * moderation, which dramatically improves TX frame rate. 2235 */ 2236 if (sc->rl_type == RL_8169) 2237 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2238 else 2239 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2240 2241 /* 2242 * For 8169 gigE NICs, set the max allowed RX packet 2243 * size so we can receive jumbo frames. 2244 */ 2245 if (sc->rl_type == RL_8169) 2246 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2247 2248 if (sc->rl_testmode) 2249 return; 2250 2251 mii_mediachg(mii); 2252 2253 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 2254 2255 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2256 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2257 2258 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2259 } 2260 2261 /* 2262 * Set media options. 2263 */ 2264 static int 2265 re_ifmedia_upd(ifp) 2266 struct ifnet *ifp; 2267 { 2268 struct rl_softc *sc; 2269 struct mii_data *mii; 2270 2271 sc = ifp->if_softc; 2272 mii = device_get_softc(sc->rl_miibus); 2273 RL_LOCK(sc); 2274 mii_mediachg(mii); 2275 RL_UNLOCK(sc); 2276 2277 return (0); 2278 } 2279 2280 /* 2281 * Report current media status. 2282 */ 2283 static void 2284 re_ifmedia_sts(ifp, ifmr) 2285 struct ifnet *ifp; 2286 struct ifmediareq *ifmr; 2287 { 2288 struct rl_softc *sc; 2289 struct mii_data *mii; 2290 2291 sc = ifp->if_softc; 2292 mii = device_get_softc(sc->rl_miibus); 2293 2294 RL_LOCK(sc); 2295 mii_pollstat(mii); 2296 RL_UNLOCK(sc); 2297 ifmr->ifm_active = mii->mii_media_active; 2298 ifmr->ifm_status = mii->mii_media_status; 2299 } 2300 2301 static int 2302 re_ioctl(ifp, command, data) 2303 struct ifnet *ifp; 2304 u_long command; 2305 caddr_t data; 2306 { 2307 struct rl_softc *sc = ifp->if_softc; 2308 struct ifreq *ifr = (struct ifreq *) data; 2309 struct mii_data *mii; 2310 int error = 0; 2311 2312 switch (command) { 2313 case SIOCSIFMTU: 2314 RL_LOCK(sc); 2315 if (ifr->ifr_mtu > RL_JUMBO_MTU) 2316 error = EINVAL; 2317 ifp->if_mtu = ifr->ifr_mtu; 2318 RL_UNLOCK(sc); 2319 break; 2320 case SIOCSIFFLAGS: 2321 RL_LOCK(sc); 2322 if (ifp->if_flags & IFF_UP) 2323 re_init_locked(sc); 2324 else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2325 re_stop(sc); 2326 RL_UNLOCK(sc); 2327 break; 2328 case SIOCADDMULTI: 2329 case SIOCDELMULTI: 2330 RL_LOCK(sc); 2331 re_setmulti(sc); 2332 RL_UNLOCK(sc); 2333 break; 2334 case SIOCGIFMEDIA: 2335 case SIOCSIFMEDIA: 2336 mii = device_get_softc(sc->rl_miibus); 2337 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2338 break; 2339 case SIOCSIFCAP: 2340 { 2341 int mask, reinit; 2342 2343 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2344 reinit = 0; 2345 #ifdef DEVICE_POLLING 2346 if (mask & IFCAP_POLLING) { 2347 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2348 error = ether_poll_register(re_poll, ifp); 2349 if (error) 2350 return(error); 2351 RL_LOCK(sc); 2352 /* Disable interrupts */ 2353 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2354 ifp->if_capenable |= IFCAP_POLLING; 2355 RL_UNLOCK(sc); 2356 2357 } else { 2358 error = ether_poll_deregister(ifp); 2359 /* Enable interrupts. */ 2360 RL_LOCK(sc); 2361 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2362 ifp->if_capenable &= ~IFCAP_POLLING; 2363 RL_UNLOCK(sc); 2364 } 2365 } 2366 #endif /* DEVICE_POLLING */ 2367 if (mask & IFCAP_HWCSUM) { 2368 ifp->if_capenable ^= IFCAP_HWCSUM; 2369 if (ifp->if_capenable & IFCAP_TXCSUM) 2370 ifp->if_hwassist = RE_CSUM_FEATURES; 2371 else 2372 ifp->if_hwassist = 0; 2373 reinit = 1; 2374 } 2375 if (mask & IFCAP_VLAN_HWTAGGING) { 2376 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2377 reinit = 1; 2378 } 2379 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) 2380 re_init(sc); 2381 } 2382 break; 2383 default: 2384 error = ether_ioctl(ifp, command, data); 2385 break; 2386 } 2387 2388 return (error); 2389 } 2390 2391 static void 2392 re_watchdog(ifp) 2393 struct ifnet *ifp; 2394 { 2395 struct rl_softc *sc; 2396 2397 sc = ifp->if_softc; 2398 RL_LOCK(sc); 2399 if_printf(ifp, "watchdog timeout\n"); 2400 ifp->if_oerrors++; 2401 2402 re_txeof(sc); 2403 re_rxeof(sc); 2404 re_init_locked(sc); 2405 2406 RL_UNLOCK(sc); 2407 } 2408 2409 /* 2410 * Stop the adapter and free any mbufs allocated to the 2411 * RX and TX lists. 2412 */ 2413 static void 2414 re_stop(sc) 2415 struct rl_softc *sc; 2416 { 2417 register int i; 2418 struct ifnet *ifp; 2419 2420 RL_LOCK_ASSERT(sc); 2421 2422 ifp = sc->rl_ifp; 2423 ifp->if_timer = 0; 2424 2425 callout_stop(&sc->rl_stat_callout); 2426 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2427 2428 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2429 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2430 2431 if (sc->rl_head != NULL) { 2432 m_freem(sc->rl_head); 2433 sc->rl_head = sc->rl_tail = NULL; 2434 } 2435 2436 /* Free the TX list buffers. */ 2437 2438 for (i = 0; i < RL_TX_DESC_CNT; i++) { 2439 if (sc->rl_ldata.rl_tx_mbuf[i] != NULL) { 2440 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2441 sc->rl_ldata.rl_tx_dmamap[i]); 2442 m_freem(sc->rl_ldata.rl_tx_mbuf[i]); 2443 sc->rl_ldata.rl_tx_mbuf[i] = NULL; 2444 } 2445 } 2446 2447 /* Free the RX list buffers. */ 2448 2449 for (i = 0; i < RL_RX_DESC_CNT; i++) { 2450 if (sc->rl_ldata.rl_rx_mbuf[i] != NULL) { 2451 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2452 sc->rl_ldata.rl_rx_dmamap[i]); 2453 m_freem(sc->rl_ldata.rl_rx_mbuf[i]); 2454 sc->rl_ldata.rl_rx_mbuf[i] = NULL; 2455 } 2456 } 2457 } 2458 2459 /* 2460 * Device suspend routine. Stop the interface and save some PCI 2461 * settings in case the BIOS doesn't restore them properly on 2462 * resume. 2463 */ 2464 static int 2465 re_suspend(dev) 2466 device_t dev; 2467 { 2468 struct rl_softc *sc; 2469 2470 sc = device_get_softc(dev); 2471 2472 RL_LOCK(sc); 2473 re_stop(sc); 2474 sc->suspended = 1; 2475 RL_UNLOCK(sc); 2476 2477 return (0); 2478 } 2479 2480 /* 2481 * Device resume routine. Restore some PCI settings in case the BIOS 2482 * doesn't, re-enable busmastering, and restart the interface if 2483 * appropriate. 2484 */ 2485 static int 2486 re_resume(dev) 2487 device_t dev; 2488 { 2489 struct rl_softc *sc; 2490 struct ifnet *ifp; 2491 2492 sc = device_get_softc(dev); 2493 2494 RL_LOCK(sc); 2495 2496 ifp = sc->rl_ifp; 2497 2498 /* reinitialize interface if necessary */ 2499 if (ifp->if_flags & IFF_UP) 2500 re_init_locked(sc); 2501 2502 sc->suspended = 0; 2503 RL_UNLOCK(sc); 2504 2505 return (0); 2506 } 2507 2508 /* 2509 * Stop all chip I/O so that the kernel's probe routines don't 2510 * get confused by errant DMAs when rebooting. 2511 */ 2512 static void 2513 re_shutdown(dev) 2514 device_t dev; 2515 { 2516 struct rl_softc *sc; 2517 2518 sc = device_get_softc(dev); 2519 2520 RL_LOCK(sc); 2521 re_stop(sc); 2522 /* 2523 * Mark interface as down since otherwise we will panic if 2524 * interrupt comes in later on, which can happen in some 2525 * cases. 2526 */ 2527 sc->rl_ifp->if_flags &= ~IFF_UP; 2528 RL_UNLOCK(sc); 2529 } 2530