1 /*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44 /* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111 #ifdef HAVE_KERNEL_OPTION_HEADERS 112 #include "opt_device_polling.h" 113 #endif 114 115 #include <sys/param.h> 116 #include <sys/endian.h> 117 #include <sys/systm.h> 118 #include <sys/sockio.h> 119 #include <sys/mbuf.h> 120 #include <sys/malloc.h> 121 #include <sys/module.h> 122 #include <sys/kernel.h> 123 #include <sys/socket.h> 124 #include <sys/lock.h> 125 #include <sys/mutex.h> 126 #include <sys/sysctl.h> 127 #include <sys/taskqueue.h> 128 129 #include <net/if.h> 130 #include <net/if_var.h> 131 #include <net/if_arp.h> 132 #include <net/ethernet.h> 133 #include <net/if_dl.h> 134 #include <net/if_media.h> 135 #include <net/if_types.h> 136 #include <net/if_vlan_var.h> 137 138 #include <net/bpf.h> 139 140 #include <machine/bus.h> 141 #include <machine/resource.h> 142 #include <sys/bus.h> 143 #include <sys/rman.h> 144 145 #include <dev/mii/mii.h> 146 #include <dev/mii/miivar.h> 147 148 #include <dev/pci/pcireg.h> 149 #include <dev/pci/pcivar.h> 150 151 #include <dev/rl/if_rlreg.h> 152 153 MODULE_DEPEND(re, pci, 1, 1, 1); 154 MODULE_DEPEND(re, ether, 1, 1, 1); 155 MODULE_DEPEND(re, miibus, 1, 1, 1); 156 157 /* "device miibus" required. See GENERIC if you get errors here. */ 158 #include "miibus_if.h" 159 160 /* Tunables. */ 161 static int intr_filter = 0; 162 TUNABLE_INT("hw.re.intr_filter", &intr_filter); 163 static int msi_disable = 0; 164 TUNABLE_INT("hw.re.msi_disable", &msi_disable); 165 static int msix_disable = 0; 166 TUNABLE_INT("hw.re.msix_disable", &msix_disable); 167 static int prefer_iomap = 0; 168 TUNABLE_INT("hw.re.prefer_iomap", &prefer_iomap); 169 170 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 171 172 /* 173 * Various supported device vendors/types and their names. 174 */ 175 static const struct rl_type re_devs[] = { 176 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0, 177 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 178 { DLINK_VENDORID, DLINK_DEVICEID_530T_REVC, 0, 179 "D-Link DGE-530(T) Gigabit Ethernet Adapter" }, 180 { RT_VENDORID, RT_DEVICEID_8139, 0, 181 "RealTek 8139C+ 10/100BaseTX" }, 182 { RT_VENDORID, RT_DEVICEID_8101E, 0, 183 "RealTek 810xE PCIe 10/100baseTX" }, 184 { RT_VENDORID, RT_DEVICEID_8168, 0, 185 "RealTek 8168/8111 B/C/CP/D/DP/E/F/G PCIe Gigabit Ethernet" }, 186 { NCUBE_VENDORID, RT_DEVICEID_8168, 0, 187 "TP-Link TG-3468 v2 (RTL8168) Gigabit Ethernet" }, 188 { RT_VENDORID, RT_DEVICEID_8169, 0, 189 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" }, 190 { RT_VENDORID, RT_DEVICEID_8169SC, 0, 191 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 192 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0, 193 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 194 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0, 195 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 196 { USR_VENDORID, USR_DEVICEID_997902, 0, 197 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 198 }; 199 200 static const struct rl_hwrev re_hwrevs[] = { 201 { RL_HWREV_8139, RL_8139, "", RL_MTU }, 202 { RL_HWREV_8139A, RL_8139, "A", RL_MTU }, 203 { RL_HWREV_8139AG, RL_8139, "A-G", RL_MTU }, 204 { RL_HWREV_8139B, RL_8139, "B", RL_MTU }, 205 { RL_HWREV_8130, RL_8139, "8130", RL_MTU }, 206 { RL_HWREV_8139C, RL_8139, "C", RL_MTU }, 207 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C", RL_MTU }, 208 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+", RL_MTU }, 209 { RL_HWREV_8168B_SPIN1, RL_8169, "8168", RL_JUMBO_MTU }, 210 { RL_HWREV_8169, RL_8169, "8169", RL_JUMBO_MTU }, 211 { RL_HWREV_8169S, RL_8169, "8169S", RL_JUMBO_MTU }, 212 { RL_HWREV_8110S, RL_8169, "8110S", RL_JUMBO_MTU }, 213 { RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB", RL_JUMBO_MTU }, 214 { RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU }, 215 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL", RL_JUMBO_MTU }, 216 { RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU }, 217 { RL_HWREV_8100, RL_8139, "8100", RL_MTU }, 218 { RL_HWREV_8101, RL_8139, "8101", RL_MTU }, 219 { RL_HWREV_8100E, RL_8169, "8100E", RL_MTU }, 220 { RL_HWREV_8101E, RL_8169, "8101E", RL_MTU }, 221 { RL_HWREV_8102E, RL_8169, "8102E", RL_MTU }, 222 { RL_HWREV_8102EL, RL_8169, "8102EL", RL_MTU }, 223 { RL_HWREV_8102EL_SPIN1, RL_8169, "8102EL", RL_MTU }, 224 { RL_HWREV_8103E, RL_8169, "8103E", RL_MTU }, 225 { RL_HWREV_8401E, RL_8169, "8401E", RL_MTU }, 226 { RL_HWREV_8402, RL_8169, "8402", RL_MTU }, 227 { RL_HWREV_8105E, RL_8169, "8105E", RL_MTU }, 228 { RL_HWREV_8105E_SPIN1, RL_8169, "8105E", RL_MTU }, 229 { RL_HWREV_8106E, RL_8169, "8106E", RL_MTU }, 230 { RL_HWREV_8168B_SPIN2, RL_8169, "8168", RL_JUMBO_MTU }, 231 { RL_HWREV_8168B_SPIN3, RL_8169, "8168", RL_JUMBO_MTU }, 232 { RL_HWREV_8168C, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K }, 233 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K }, 234 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP", RL_JUMBO_MTU_6K }, 235 { RL_HWREV_8168D, RL_8169, "8168D/8111D", RL_JUMBO_MTU_9K }, 236 { RL_HWREV_8168DP, RL_8169, "8168DP/8111DP", RL_JUMBO_MTU_9K }, 237 { RL_HWREV_8168E, RL_8169, "8168E/8111E", RL_JUMBO_MTU_9K}, 238 { RL_HWREV_8168E_VL, RL_8169, "8168E/8111E-VL", RL_JUMBO_MTU_6K}, 239 { RL_HWREV_8168EP, RL_8169, "8168EP/8111EP", RL_JUMBO_MTU_9K}, 240 { RL_HWREV_8168F, RL_8169, "8168F/8111F", RL_JUMBO_MTU_9K}, 241 { RL_HWREV_8168G, RL_8169, "8168G/8111G", RL_JUMBO_MTU_9K}, 242 { RL_HWREV_8168GU, RL_8169, "8168GU/8111GU", RL_JUMBO_MTU_9K}, 243 { RL_HWREV_8168H, RL_8169, "8168H/8111H", RL_JUMBO_MTU_9K}, 244 { RL_HWREV_8411, RL_8169, "8411", RL_JUMBO_MTU_9K}, 245 { RL_HWREV_8411B, RL_8169, "8411B", RL_JUMBO_MTU_9K}, 246 { 0, 0, NULL, 0 } 247 }; 248 249 static int re_probe (device_t); 250 static int re_attach (device_t); 251 static int re_detach (device_t); 252 253 static int re_encap (struct rl_softc *, struct mbuf **); 254 255 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 256 static int re_allocmem (device_t, struct rl_softc *); 257 static __inline void re_discard_rxbuf 258 (struct rl_softc *, int); 259 static int re_newbuf (struct rl_softc *, int); 260 static int re_jumbo_newbuf (struct rl_softc *, int); 261 static int re_rx_list_init (struct rl_softc *); 262 static int re_jrx_list_init (struct rl_softc *); 263 static int re_tx_list_init (struct rl_softc *); 264 #ifdef RE_FIXUP_RX 265 static __inline void re_fixup_rx 266 (struct mbuf *); 267 #endif 268 static int re_rxeof (struct rl_softc *, int *); 269 static void re_txeof (struct rl_softc *); 270 #ifdef DEVICE_POLLING 271 static int re_poll (struct ifnet *, enum poll_cmd, int); 272 static int re_poll_locked (struct ifnet *, enum poll_cmd, int); 273 #endif 274 static int re_intr (void *); 275 static void re_intr_msi (void *); 276 static void re_tick (void *); 277 static void re_int_task (void *, int); 278 static void re_start (struct ifnet *); 279 static void re_start_locked (struct ifnet *); 280 static int re_ioctl (struct ifnet *, u_long, caddr_t); 281 static void re_init (void *); 282 static void re_init_locked (struct rl_softc *); 283 static void re_stop (struct rl_softc *); 284 static void re_watchdog (struct rl_softc *); 285 static int re_suspend (device_t); 286 static int re_resume (device_t); 287 static int re_shutdown (device_t); 288 static int re_ifmedia_upd (struct ifnet *); 289 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 290 291 static void re_eeprom_putbyte (struct rl_softc *, int); 292 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 293 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 294 static int re_gmii_readreg (device_t, int, int); 295 static int re_gmii_writereg (device_t, int, int, int); 296 297 static int re_miibus_readreg (device_t, int, int); 298 static int re_miibus_writereg (device_t, int, int, int); 299 static void re_miibus_statchg (device_t); 300 301 static void re_set_jumbo (struct rl_softc *, int); 302 static void re_set_rxmode (struct rl_softc *); 303 static void re_reset (struct rl_softc *); 304 static void re_setwol (struct rl_softc *); 305 static void re_clrwol (struct rl_softc *); 306 static void re_set_linkspeed (struct rl_softc *); 307 308 #ifdef DEV_NETMAP /* see ixgbe.c for details */ 309 #include <dev/netmap/if_re_netmap.h> 310 MODULE_DEPEND(re, netmap, 1, 1, 1); 311 #endif /* !DEV_NETMAP */ 312 313 #ifdef RE_DIAG 314 static int re_diag (struct rl_softc *); 315 #endif 316 317 static void re_add_sysctls (struct rl_softc *); 318 static int re_sysctl_stats (SYSCTL_HANDLER_ARGS); 319 static int sysctl_int_range (SYSCTL_HANDLER_ARGS, int, int); 320 static int sysctl_hw_re_int_mod (SYSCTL_HANDLER_ARGS); 321 322 static device_method_t re_methods[] = { 323 /* Device interface */ 324 DEVMETHOD(device_probe, re_probe), 325 DEVMETHOD(device_attach, re_attach), 326 DEVMETHOD(device_detach, re_detach), 327 DEVMETHOD(device_suspend, re_suspend), 328 DEVMETHOD(device_resume, re_resume), 329 DEVMETHOD(device_shutdown, re_shutdown), 330 331 /* MII interface */ 332 DEVMETHOD(miibus_readreg, re_miibus_readreg), 333 DEVMETHOD(miibus_writereg, re_miibus_writereg), 334 DEVMETHOD(miibus_statchg, re_miibus_statchg), 335 336 DEVMETHOD_END 337 }; 338 339 static driver_t re_driver = { 340 "re", 341 re_methods, 342 sizeof(struct rl_softc) 343 }; 344 345 static devclass_t re_devclass; 346 347 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 348 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 349 350 #define EE_SET(x) \ 351 CSR_WRITE_1(sc, RL_EECMD, \ 352 CSR_READ_1(sc, RL_EECMD) | x) 353 354 #define EE_CLR(x) \ 355 CSR_WRITE_1(sc, RL_EECMD, \ 356 CSR_READ_1(sc, RL_EECMD) & ~x) 357 358 /* 359 * Send a read command and address to the EEPROM, check for ACK. 360 */ 361 static void 362 re_eeprom_putbyte(struct rl_softc *sc, int addr) 363 { 364 int d, i; 365 366 d = addr | (RL_9346_READ << sc->rl_eewidth); 367 368 /* 369 * Feed in each bit and strobe the clock. 370 */ 371 372 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 373 if (d & i) { 374 EE_SET(RL_EE_DATAIN); 375 } else { 376 EE_CLR(RL_EE_DATAIN); 377 } 378 DELAY(100); 379 EE_SET(RL_EE_CLK); 380 DELAY(150); 381 EE_CLR(RL_EE_CLK); 382 DELAY(100); 383 } 384 } 385 386 /* 387 * Read a word of data stored in the EEPROM at address 'addr.' 388 */ 389 static void 390 re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest) 391 { 392 int i; 393 u_int16_t word = 0; 394 395 /* 396 * Send address of word we want to read. 397 */ 398 re_eeprom_putbyte(sc, addr); 399 400 /* 401 * Start reading bits from EEPROM. 402 */ 403 for (i = 0x8000; i; i >>= 1) { 404 EE_SET(RL_EE_CLK); 405 DELAY(100); 406 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 407 word |= i; 408 EE_CLR(RL_EE_CLK); 409 DELAY(100); 410 } 411 412 *dest = word; 413 } 414 415 /* 416 * Read a sequence of words from the EEPROM. 417 */ 418 static void 419 re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt) 420 { 421 int i; 422 u_int16_t word = 0, *ptr; 423 424 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 425 426 DELAY(100); 427 428 for (i = 0; i < cnt; i++) { 429 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 430 re_eeprom_getword(sc, off + i, &word); 431 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 432 ptr = (u_int16_t *)(dest + (i * 2)); 433 *ptr = word; 434 } 435 436 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 437 } 438 439 static int 440 re_gmii_readreg(device_t dev, int phy, int reg) 441 { 442 struct rl_softc *sc; 443 u_int32_t rval; 444 int i; 445 446 sc = device_get_softc(dev); 447 448 /* Let the rgephy driver read the GMEDIASTAT register */ 449 450 if (reg == RL_GMEDIASTAT) { 451 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 452 return (rval); 453 } 454 455 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 456 457 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 458 rval = CSR_READ_4(sc, RL_PHYAR); 459 if (rval & RL_PHYAR_BUSY) 460 break; 461 DELAY(25); 462 } 463 464 if (i == RL_PHY_TIMEOUT) { 465 device_printf(sc->rl_dev, "PHY read failed\n"); 466 return (0); 467 } 468 469 /* 470 * Controller requires a 20us delay to process next MDIO request. 471 */ 472 DELAY(20); 473 474 return (rval & RL_PHYAR_PHYDATA); 475 } 476 477 static int 478 re_gmii_writereg(device_t dev, int phy, int reg, int data) 479 { 480 struct rl_softc *sc; 481 u_int32_t rval; 482 int i; 483 484 sc = device_get_softc(dev); 485 486 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 487 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 488 489 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 490 rval = CSR_READ_4(sc, RL_PHYAR); 491 if (!(rval & RL_PHYAR_BUSY)) 492 break; 493 DELAY(25); 494 } 495 496 if (i == RL_PHY_TIMEOUT) { 497 device_printf(sc->rl_dev, "PHY write failed\n"); 498 return (0); 499 } 500 501 /* 502 * Controller requires a 20us delay to process next MDIO request. 503 */ 504 DELAY(20); 505 506 return (0); 507 } 508 509 static int 510 re_miibus_readreg(device_t dev, int phy, int reg) 511 { 512 struct rl_softc *sc; 513 u_int16_t rval = 0; 514 u_int16_t re8139_reg = 0; 515 516 sc = device_get_softc(dev); 517 518 if (sc->rl_type == RL_8169) { 519 rval = re_gmii_readreg(dev, phy, reg); 520 return (rval); 521 } 522 523 switch (reg) { 524 case MII_BMCR: 525 re8139_reg = RL_BMCR; 526 break; 527 case MII_BMSR: 528 re8139_reg = RL_BMSR; 529 break; 530 case MII_ANAR: 531 re8139_reg = RL_ANAR; 532 break; 533 case MII_ANER: 534 re8139_reg = RL_ANER; 535 break; 536 case MII_ANLPAR: 537 re8139_reg = RL_LPAR; 538 break; 539 case MII_PHYIDR1: 540 case MII_PHYIDR2: 541 return (0); 542 /* 543 * Allow the rlphy driver to read the media status 544 * register. If we have a link partner which does not 545 * support NWAY, this is the register which will tell 546 * us the results of parallel detection. 547 */ 548 case RL_MEDIASTAT: 549 rval = CSR_READ_1(sc, RL_MEDIASTAT); 550 return (rval); 551 default: 552 device_printf(sc->rl_dev, "bad phy register\n"); 553 return (0); 554 } 555 rval = CSR_READ_2(sc, re8139_reg); 556 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 557 /* 8139C+ has different bit layout. */ 558 rval &= ~(BMCR_LOOP | BMCR_ISO); 559 } 560 return (rval); 561 } 562 563 static int 564 re_miibus_writereg(device_t dev, int phy, int reg, int data) 565 { 566 struct rl_softc *sc; 567 u_int16_t re8139_reg = 0; 568 int rval = 0; 569 570 sc = device_get_softc(dev); 571 572 if (sc->rl_type == RL_8169) { 573 rval = re_gmii_writereg(dev, phy, reg, data); 574 return (rval); 575 } 576 577 switch (reg) { 578 case MII_BMCR: 579 re8139_reg = RL_BMCR; 580 if (sc->rl_type == RL_8139CPLUS) { 581 /* 8139C+ has different bit layout. */ 582 data &= ~(BMCR_LOOP | BMCR_ISO); 583 } 584 break; 585 case MII_BMSR: 586 re8139_reg = RL_BMSR; 587 break; 588 case MII_ANAR: 589 re8139_reg = RL_ANAR; 590 break; 591 case MII_ANER: 592 re8139_reg = RL_ANER; 593 break; 594 case MII_ANLPAR: 595 re8139_reg = RL_LPAR; 596 break; 597 case MII_PHYIDR1: 598 case MII_PHYIDR2: 599 return (0); 600 break; 601 default: 602 device_printf(sc->rl_dev, "bad phy register\n"); 603 return (0); 604 } 605 CSR_WRITE_2(sc, re8139_reg, data); 606 return (0); 607 } 608 609 static void 610 re_miibus_statchg(device_t dev) 611 { 612 struct rl_softc *sc; 613 struct ifnet *ifp; 614 struct mii_data *mii; 615 616 sc = device_get_softc(dev); 617 mii = device_get_softc(sc->rl_miibus); 618 ifp = sc->rl_ifp; 619 if (mii == NULL || ifp == NULL || 620 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 621 return; 622 623 sc->rl_flags &= ~RL_FLAG_LINK; 624 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 625 (IFM_ACTIVE | IFM_AVALID)) { 626 switch (IFM_SUBTYPE(mii->mii_media_active)) { 627 case IFM_10_T: 628 case IFM_100_TX: 629 sc->rl_flags |= RL_FLAG_LINK; 630 break; 631 case IFM_1000_T: 632 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0) 633 break; 634 sc->rl_flags |= RL_FLAG_LINK; 635 break; 636 default: 637 break; 638 } 639 } 640 /* 641 * RealTek controllers do not provide any interface to the RX/TX 642 * MACs for resolved speed, duplex and flow-control parameters. 643 */ 644 } 645 646 /* 647 * Set the RX configuration and 64-bit multicast hash filter. 648 */ 649 static void 650 re_set_rxmode(struct rl_softc *sc) 651 { 652 struct ifnet *ifp; 653 struct ifmultiaddr *ifma; 654 uint32_t hashes[2] = { 0, 0 }; 655 uint32_t h, rxfilt; 656 657 RL_LOCK_ASSERT(sc); 658 659 ifp = sc->rl_ifp; 660 661 rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD; 662 if ((sc->rl_flags & RL_FLAG_EARLYOFF) != 0) 663 rxfilt |= RL_RXCFG_EARLYOFF; 664 else if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0) 665 rxfilt |= RL_RXCFG_EARLYOFFV2; 666 667 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 668 if (ifp->if_flags & IFF_PROMISC) 669 rxfilt |= RL_RXCFG_RX_ALLPHYS; 670 /* 671 * Unlike other hardwares, we have to explicitly set 672 * RL_RXCFG_RX_MULTI to receive multicast frames in 673 * promiscuous mode. 674 */ 675 rxfilt |= RL_RXCFG_RX_MULTI; 676 hashes[0] = hashes[1] = 0xffffffff; 677 goto done; 678 } 679 680 if_maddr_rlock(ifp); 681 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 682 if (ifma->ifma_addr->sa_family != AF_LINK) 683 continue; 684 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 685 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 686 if (h < 32) 687 hashes[0] |= (1 << h); 688 else 689 hashes[1] |= (1 << (h - 32)); 690 } 691 if_maddr_runlock(ifp); 692 693 if (hashes[0] != 0 || hashes[1] != 0) { 694 /* 695 * For some unfathomable reason, RealTek decided to 696 * reverse the order of the multicast hash registers 697 * in the PCI Express parts. This means we have to 698 * write the hash pattern in reverse order for those 699 * devices. 700 */ 701 if ((sc->rl_flags & RL_FLAG_PCIE) != 0) { 702 h = bswap32(hashes[0]); 703 hashes[0] = bswap32(hashes[1]); 704 hashes[1] = h; 705 } 706 rxfilt |= RL_RXCFG_RX_MULTI; 707 } 708 709 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168F) { 710 /* Disable multicast filtering due to silicon bug. */ 711 hashes[0] = 0xffffffff; 712 hashes[1] = 0xffffffff; 713 } 714 715 done: 716 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 717 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 718 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 719 } 720 721 static void 722 re_reset(struct rl_softc *sc) 723 { 724 int i; 725 726 RL_LOCK_ASSERT(sc); 727 728 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 729 730 for (i = 0; i < RL_TIMEOUT; i++) { 731 DELAY(10); 732 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 733 break; 734 } 735 if (i == RL_TIMEOUT) 736 device_printf(sc->rl_dev, "reset never completed!\n"); 737 738 if ((sc->rl_flags & RL_FLAG_MACRESET) != 0) 739 CSR_WRITE_1(sc, 0x82, 1); 740 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169S) 741 re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0); 742 } 743 744 #ifdef RE_DIAG 745 746 /* 747 * The following routine is designed to test for a defect on some 748 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 749 * lines connected to the bus, however for a 32-bit only card, they 750 * should be pulled high. The result of this defect is that the 751 * NIC will not work right if you plug it into a 64-bit slot: DMA 752 * operations will be done with 64-bit transfers, which will fail 753 * because the 64-bit data lines aren't connected. 754 * 755 * There's no way to work around this (short of talking a soldering 756 * iron to the board), however we can detect it. The method we use 757 * here is to put the NIC into digital loopback mode, set the receiver 758 * to promiscuous mode, and then try to send a frame. We then compare 759 * the frame data we sent to what was received. If the data matches, 760 * then the NIC is working correctly, otherwise we know the user has 761 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 762 * slot. In the latter case, there's no way the NIC can work correctly, 763 * so we print out a message on the console and abort the device attach. 764 */ 765 766 static int 767 re_diag(struct rl_softc *sc) 768 { 769 struct ifnet *ifp = sc->rl_ifp; 770 struct mbuf *m0; 771 struct ether_header *eh; 772 struct rl_desc *cur_rx; 773 u_int16_t status; 774 u_int32_t rxstat; 775 int total_len, i, error = 0, phyaddr; 776 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 777 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 778 779 /* Allocate a single mbuf */ 780 MGETHDR(m0, M_NOWAIT, MT_DATA); 781 if (m0 == NULL) 782 return (ENOBUFS); 783 784 RL_LOCK(sc); 785 786 /* 787 * Initialize the NIC in test mode. This sets the chip up 788 * so that it can send and receive frames, but performs the 789 * following special functions: 790 * - Puts receiver in promiscuous mode 791 * - Enables digital loopback mode 792 * - Leaves interrupts turned off 793 */ 794 795 ifp->if_flags |= IFF_PROMISC; 796 sc->rl_testmode = 1; 797 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 798 re_init_locked(sc); 799 sc->rl_flags |= RL_FLAG_LINK; 800 if (sc->rl_type == RL_8169) 801 phyaddr = 1; 802 else 803 phyaddr = 0; 804 805 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 806 for (i = 0; i < RL_TIMEOUT; i++) { 807 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 808 if (!(status & BMCR_RESET)) 809 break; 810 } 811 812 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 813 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 814 815 DELAY(100000); 816 817 /* Put some data in the mbuf */ 818 819 eh = mtod(m0, struct ether_header *); 820 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 821 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 822 eh->ether_type = htons(ETHERTYPE_IP); 823 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 824 825 /* 826 * Queue the packet, start transmission. 827 * Note: IF_HANDOFF() ultimately calls re_start() for us. 828 */ 829 830 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 831 RL_UNLOCK(sc); 832 /* XXX: re_diag must not be called when in ALTQ mode */ 833 IF_HANDOFF(&ifp->if_snd, m0, ifp); 834 RL_LOCK(sc); 835 m0 = NULL; 836 837 /* Wait for it to propagate through the chip */ 838 839 DELAY(100000); 840 for (i = 0; i < RL_TIMEOUT; i++) { 841 status = CSR_READ_2(sc, RL_ISR); 842 CSR_WRITE_2(sc, RL_ISR, status); 843 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 844 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 845 break; 846 DELAY(10); 847 } 848 849 if (i == RL_TIMEOUT) { 850 device_printf(sc->rl_dev, 851 "diagnostic failed, failed to receive packet in" 852 " loopback mode\n"); 853 error = EIO; 854 goto done; 855 } 856 857 /* 858 * The packet should have been dumped into the first 859 * entry in the RX DMA ring. Grab it from there. 860 */ 861 862 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 863 sc->rl_ldata.rl_rx_list_map, 864 BUS_DMASYNC_POSTREAD); 865 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 866 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 867 BUS_DMASYNC_POSTREAD); 868 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 869 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 870 871 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 872 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 873 eh = mtod(m0, struct ether_header *); 874 875 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 876 total_len = RL_RXBYTES(cur_rx); 877 rxstat = le32toh(cur_rx->rl_cmdstat); 878 879 if (total_len != ETHER_MIN_LEN) { 880 device_printf(sc->rl_dev, 881 "diagnostic failed, received short packet\n"); 882 error = EIO; 883 goto done; 884 } 885 886 /* Test that the received packet data matches what we sent. */ 887 888 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 889 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 890 ntohs(eh->ether_type) != ETHERTYPE_IP) { 891 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 892 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 893 dst, ":", src, ":", ETHERTYPE_IP); 894 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 895 eh->ether_dhost, ":", eh->ether_shost, ":", 896 ntohs(eh->ether_type)); 897 device_printf(sc->rl_dev, "You may have a defective 32-bit " 898 "NIC plugged into a 64-bit PCI slot.\n"); 899 device_printf(sc->rl_dev, "Please re-install the NIC in a " 900 "32-bit slot for proper operation.\n"); 901 device_printf(sc->rl_dev, "Read the re(4) man page for more " 902 "details.\n"); 903 error = EIO; 904 } 905 906 done: 907 /* Turn interface off, release resources */ 908 909 sc->rl_testmode = 0; 910 sc->rl_flags &= ~RL_FLAG_LINK; 911 ifp->if_flags &= ~IFF_PROMISC; 912 re_stop(sc); 913 if (m0 != NULL) 914 m_freem(m0); 915 916 RL_UNLOCK(sc); 917 918 return (error); 919 } 920 921 #endif 922 923 /* 924 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 925 * IDs against our list and return a device name if we find a match. 926 */ 927 static int 928 re_probe(device_t dev) 929 { 930 const struct rl_type *t; 931 uint16_t devid, vendor; 932 uint16_t revid, sdevid; 933 int i; 934 935 vendor = pci_get_vendor(dev); 936 devid = pci_get_device(dev); 937 revid = pci_get_revid(dev); 938 sdevid = pci_get_subdevice(dev); 939 940 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 941 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 942 /* 943 * Only attach to rev. 3 of the Linksys EG1032 adapter. 944 * Rev. 2 is supported by sk(4). 945 */ 946 return (ENXIO); 947 } 948 } 949 950 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 951 if (revid != 0x20) { 952 /* 8139, let rl(4) take care of this device. */ 953 return (ENXIO); 954 } 955 } 956 957 t = re_devs; 958 for (i = 0; i < nitems(re_devs); i++, t++) { 959 if (vendor == t->rl_vid && devid == t->rl_did) { 960 device_set_desc(dev, t->rl_name); 961 return (BUS_PROBE_DEFAULT); 962 } 963 } 964 965 return (ENXIO); 966 } 967 968 /* 969 * Map a single buffer address. 970 */ 971 972 static void 973 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 974 { 975 bus_addr_t *addr; 976 977 if (error) 978 return; 979 980 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 981 addr = arg; 982 *addr = segs->ds_addr; 983 } 984 985 static int 986 re_allocmem(device_t dev, struct rl_softc *sc) 987 { 988 bus_addr_t lowaddr; 989 bus_size_t rx_list_size, tx_list_size; 990 int error; 991 int i; 992 993 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 994 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 995 996 /* 997 * Allocate the parent bus DMA tag appropriate for PCI. 998 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD 999 * register should be set. However some RealTek chips are known 1000 * to be buggy on DAC handling, therefore disable DAC by limiting 1001 * DMA address space to 32bit. PCIe variants of RealTek chips 1002 * may not have the limitation. 1003 */ 1004 lowaddr = BUS_SPACE_MAXADDR; 1005 if ((sc->rl_flags & RL_FLAG_PCIE) == 0) 1006 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1007 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 1008 lowaddr, BUS_SPACE_MAXADDR, NULL, NULL, 1009 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 1010 NULL, NULL, &sc->rl_parent_tag); 1011 if (error) { 1012 device_printf(dev, "could not allocate parent DMA tag\n"); 1013 return (error); 1014 } 1015 1016 /* 1017 * Allocate map for TX mbufs. 1018 */ 1019 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 1020 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1021 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 1022 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 1023 if (error) { 1024 device_printf(dev, "could not allocate TX DMA tag\n"); 1025 return (error); 1026 } 1027 1028 /* 1029 * Allocate map for RX mbufs. 1030 */ 1031 1032 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 1033 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 1034 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1035 MJUM9BYTES, 1, MJUM9BYTES, 0, NULL, NULL, 1036 &sc->rl_ldata.rl_jrx_mtag); 1037 if (error) { 1038 device_printf(dev, 1039 "could not allocate jumbo RX DMA tag\n"); 1040 return (error); 1041 } 1042 } 1043 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 1044 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1045 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 1046 if (error) { 1047 device_printf(dev, "could not allocate RX DMA tag\n"); 1048 return (error); 1049 } 1050 1051 /* 1052 * Allocate map for TX descriptor list. 1053 */ 1054 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1055 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1056 NULL, tx_list_size, 1, tx_list_size, 0, 1057 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1058 if (error) { 1059 device_printf(dev, "could not allocate TX DMA ring tag\n"); 1060 return (error); 1061 } 1062 1063 /* Allocate DMA'able memory for the TX ring */ 1064 1065 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1066 (void **)&sc->rl_ldata.rl_tx_list, 1067 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1068 &sc->rl_ldata.rl_tx_list_map); 1069 if (error) { 1070 device_printf(dev, "could not allocate TX DMA ring\n"); 1071 return (error); 1072 } 1073 1074 /* Load the map for the TX ring. */ 1075 1076 sc->rl_ldata.rl_tx_list_addr = 0; 1077 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1078 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1079 tx_list_size, re_dma_map_addr, 1080 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1081 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 1082 device_printf(dev, "could not load TX DMA ring\n"); 1083 return (ENOMEM); 1084 } 1085 1086 /* Create DMA maps for TX buffers */ 1087 1088 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1089 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1090 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1091 if (error) { 1092 device_printf(dev, "could not create DMA map for TX\n"); 1093 return (error); 1094 } 1095 } 1096 1097 /* 1098 * Allocate map for RX descriptor list. 1099 */ 1100 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1101 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1102 NULL, rx_list_size, 1, rx_list_size, 0, 1103 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1104 if (error) { 1105 device_printf(dev, "could not create RX DMA ring tag\n"); 1106 return (error); 1107 } 1108 1109 /* Allocate DMA'able memory for the RX ring */ 1110 1111 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1112 (void **)&sc->rl_ldata.rl_rx_list, 1113 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1114 &sc->rl_ldata.rl_rx_list_map); 1115 if (error) { 1116 device_printf(dev, "could not allocate RX DMA ring\n"); 1117 return (error); 1118 } 1119 1120 /* Load the map for the RX ring. */ 1121 1122 sc->rl_ldata.rl_rx_list_addr = 0; 1123 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1124 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1125 rx_list_size, re_dma_map_addr, 1126 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1127 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1128 device_printf(dev, "could not load RX DMA ring\n"); 1129 return (ENOMEM); 1130 } 1131 1132 /* Create DMA maps for RX buffers */ 1133 1134 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 1135 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0, 1136 &sc->rl_ldata.rl_jrx_sparemap); 1137 if (error) { 1138 device_printf(dev, 1139 "could not create spare DMA map for jumbo RX\n"); 1140 return (error); 1141 } 1142 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1143 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0, 1144 &sc->rl_ldata.rl_jrx_desc[i].rx_dmamap); 1145 if (error) { 1146 device_printf(dev, 1147 "could not create DMA map for jumbo RX\n"); 1148 return (error); 1149 } 1150 } 1151 } 1152 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1153 &sc->rl_ldata.rl_rx_sparemap); 1154 if (error) { 1155 device_printf(dev, "could not create spare DMA map for RX\n"); 1156 return (error); 1157 } 1158 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1159 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1160 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1161 if (error) { 1162 device_printf(dev, "could not create DMA map for RX\n"); 1163 return (error); 1164 } 1165 } 1166 1167 /* Create DMA map for statistics. */ 1168 error = bus_dma_tag_create(sc->rl_parent_tag, RL_DUMP_ALIGN, 0, 1169 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1170 sizeof(struct rl_stats), 1, sizeof(struct rl_stats), 0, NULL, NULL, 1171 &sc->rl_ldata.rl_stag); 1172 if (error) { 1173 device_printf(dev, "could not create statistics DMA tag\n"); 1174 return (error); 1175 } 1176 /* Allocate DMA'able memory for statistics. */ 1177 error = bus_dmamem_alloc(sc->rl_ldata.rl_stag, 1178 (void **)&sc->rl_ldata.rl_stats, 1179 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1180 &sc->rl_ldata.rl_smap); 1181 if (error) { 1182 device_printf(dev, 1183 "could not allocate statistics DMA memory\n"); 1184 return (error); 1185 } 1186 /* Load the map for statistics. */ 1187 sc->rl_ldata.rl_stats_addr = 0; 1188 error = bus_dmamap_load(sc->rl_ldata.rl_stag, sc->rl_ldata.rl_smap, 1189 sc->rl_ldata.rl_stats, sizeof(struct rl_stats), re_dma_map_addr, 1190 &sc->rl_ldata.rl_stats_addr, BUS_DMA_NOWAIT); 1191 if (error != 0 || sc->rl_ldata.rl_stats_addr == 0) { 1192 device_printf(dev, "could not load statistics DMA memory\n"); 1193 return (ENOMEM); 1194 } 1195 1196 return (0); 1197 } 1198 1199 /* 1200 * Attach the interface. Allocate softc structures, do ifmedia 1201 * setup and ethernet/BPF attach. 1202 */ 1203 static int 1204 re_attach(device_t dev) 1205 { 1206 u_char eaddr[ETHER_ADDR_LEN]; 1207 u_int16_t as[ETHER_ADDR_LEN / 2]; 1208 struct rl_softc *sc; 1209 struct ifnet *ifp; 1210 const struct rl_hwrev *hw_rev; 1211 int capmask, error = 0, hwrev, i, msic, msixc, 1212 phy, reg, rid; 1213 u_int32_t cap, ctl; 1214 u_int16_t devid, re_did = 0; 1215 uint8_t cfg; 1216 1217 sc = device_get_softc(dev); 1218 sc->rl_dev = dev; 1219 1220 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1221 MTX_DEF); 1222 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1223 1224 /* 1225 * Map control/status registers. 1226 */ 1227 pci_enable_busmaster(dev); 1228 1229 devid = pci_get_device(dev); 1230 /* 1231 * Prefer memory space register mapping over IO space. 1232 * Because RTL8169SC does not seem to work when memory mapping 1233 * is used always activate io mapping. 1234 */ 1235 if (devid == RT_DEVICEID_8169SC) 1236 prefer_iomap = 1; 1237 if (prefer_iomap == 0) { 1238 sc->rl_res_id = PCIR_BAR(1); 1239 sc->rl_res_type = SYS_RES_MEMORY; 1240 /* RTL8168/8101E seems to use different BARs. */ 1241 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E) 1242 sc->rl_res_id = PCIR_BAR(2); 1243 } else { 1244 sc->rl_res_id = PCIR_BAR(0); 1245 sc->rl_res_type = SYS_RES_IOPORT; 1246 } 1247 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1248 &sc->rl_res_id, RF_ACTIVE); 1249 if (sc->rl_res == NULL && prefer_iomap == 0) { 1250 sc->rl_res_id = PCIR_BAR(0); 1251 sc->rl_res_type = SYS_RES_IOPORT; 1252 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1253 &sc->rl_res_id, RF_ACTIVE); 1254 } 1255 if (sc->rl_res == NULL) { 1256 device_printf(dev, "couldn't map ports/memory\n"); 1257 error = ENXIO; 1258 goto fail; 1259 } 1260 1261 sc->rl_btag = rman_get_bustag(sc->rl_res); 1262 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1263 1264 msic = pci_msi_count(dev); 1265 msixc = pci_msix_count(dev); 1266 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 1267 sc->rl_flags |= RL_FLAG_PCIE; 1268 sc->rl_expcap = reg; 1269 } 1270 if (bootverbose) { 1271 device_printf(dev, "MSI count : %d\n", msic); 1272 device_printf(dev, "MSI-X count : %d\n", msixc); 1273 } 1274 if (msix_disable > 0) 1275 msixc = 0; 1276 if (msi_disable > 0) 1277 msic = 0; 1278 /* Prefer MSI-X to MSI. */ 1279 if (msixc > 0) { 1280 msixc = RL_MSI_MESSAGES; 1281 rid = PCIR_BAR(4); 1282 sc->rl_res_pba = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1283 &rid, RF_ACTIVE); 1284 if (sc->rl_res_pba == NULL) { 1285 device_printf(sc->rl_dev, 1286 "could not allocate MSI-X PBA resource\n"); 1287 } 1288 if (sc->rl_res_pba != NULL && 1289 pci_alloc_msix(dev, &msixc) == 0) { 1290 if (msixc == RL_MSI_MESSAGES) { 1291 device_printf(dev, "Using %d MSI-X message\n", 1292 msixc); 1293 sc->rl_flags |= RL_FLAG_MSIX; 1294 } else 1295 pci_release_msi(dev); 1296 } 1297 if ((sc->rl_flags & RL_FLAG_MSIX) == 0) { 1298 if (sc->rl_res_pba != NULL) 1299 bus_release_resource(dev, SYS_RES_MEMORY, rid, 1300 sc->rl_res_pba); 1301 sc->rl_res_pba = NULL; 1302 msixc = 0; 1303 } 1304 } 1305 /* Prefer MSI to INTx. */ 1306 if (msixc == 0 && msic > 0) { 1307 msic = RL_MSI_MESSAGES; 1308 if (pci_alloc_msi(dev, &msic) == 0) { 1309 if (msic == RL_MSI_MESSAGES) { 1310 device_printf(dev, "Using %d MSI message\n", 1311 msic); 1312 sc->rl_flags |= RL_FLAG_MSI; 1313 /* Explicitly set MSI enable bit. */ 1314 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1315 cfg = CSR_READ_1(sc, RL_CFG2); 1316 cfg |= RL_CFG2_MSI; 1317 CSR_WRITE_1(sc, RL_CFG2, cfg); 1318 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1319 } else 1320 pci_release_msi(dev); 1321 } 1322 if ((sc->rl_flags & RL_FLAG_MSI) == 0) 1323 msic = 0; 1324 } 1325 1326 /* Allocate interrupt */ 1327 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) { 1328 rid = 0; 1329 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1330 RF_SHAREABLE | RF_ACTIVE); 1331 if (sc->rl_irq[0] == NULL) { 1332 device_printf(dev, "couldn't allocate IRQ resources\n"); 1333 error = ENXIO; 1334 goto fail; 1335 } 1336 } else { 1337 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1338 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1339 SYS_RES_IRQ, &rid, RF_ACTIVE); 1340 if (sc->rl_irq[i] == NULL) { 1341 device_printf(dev, 1342 "couldn't allocate IRQ resources for " 1343 "message %d\n", rid); 1344 error = ENXIO; 1345 goto fail; 1346 } 1347 } 1348 } 1349 1350 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1351 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1352 cfg = CSR_READ_1(sc, RL_CFG2); 1353 if ((cfg & RL_CFG2_MSI) != 0) { 1354 device_printf(dev, "turning off MSI enable bit.\n"); 1355 cfg &= ~RL_CFG2_MSI; 1356 CSR_WRITE_1(sc, RL_CFG2, cfg); 1357 } 1358 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1359 } 1360 1361 /* Disable ASPM L0S/L1 and CLKREQ. */ 1362 if (sc->rl_expcap != 0) { 1363 cap = pci_read_config(dev, sc->rl_expcap + 1364 PCIER_LINK_CAP, 2); 1365 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { 1366 ctl = pci_read_config(dev, sc->rl_expcap + 1367 PCIER_LINK_CTL, 2); 1368 if ((ctl & (PCIEM_LINK_CTL_ECPM | 1369 PCIEM_LINK_CTL_ASPMC))!= 0) { 1370 ctl &= ~(PCIEM_LINK_CTL_ECPM | 1371 PCIEM_LINK_CTL_ASPMC); 1372 pci_write_config(dev, sc->rl_expcap + 1373 PCIER_LINK_CTL, ctl, 2); 1374 device_printf(dev, "ASPM disabled\n"); 1375 } 1376 } else 1377 device_printf(dev, "no ASPM capability\n"); 1378 } 1379 1380 hw_rev = re_hwrevs; 1381 hwrev = CSR_READ_4(sc, RL_TXCFG); 1382 switch (hwrev & 0x70000000) { 1383 case 0x00000000: 1384 case 0x10000000: 1385 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000); 1386 hwrev &= (RL_TXCFG_HWREV | 0x80000000); 1387 break; 1388 default: 1389 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000); 1390 sc->rl_macrev = hwrev & 0x00700000; 1391 hwrev &= RL_TXCFG_HWREV; 1392 break; 1393 } 1394 device_printf(dev, "MAC rev. 0x%08x\n", sc->rl_macrev); 1395 while (hw_rev->rl_desc != NULL) { 1396 if (hw_rev->rl_rev == hwrev) { 1397 sc->rl_type = hw_rev->rl_type; 1398 sc->rl_hwrev = hw_rev; 1399 break; 1400 } 1401 hw_rev++; 1402 } 1403 if (hw_rev->rl_desc == NULL) { 1404 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev); 1405 error = ENXIO; 1406 goto fail; 1407 } 1408 1409 switch (hw_rev->rl_rev) { 1410 case RL_HWREV_8139CPLUS: 1411 sc->rl_flags |= RL_FLAG_FASTETHER | RL_FLAG_AUTOPAD; 1412 break; 1413 case RL_HWREV_8100E: 1414 case RL_HWREV_8101E: 1415 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_FASTETHER; 1416 break; 1417 case RL_HWREV_8102E: 1418 case RL_HWREV_8102EL: 1419 case RL_HWREV_8102EL_SPIN1: 1420 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1421 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | 1422 RL_FLAG_AUTOPAD; 1423 break; 1424 case RL_HWREV_8103E: 1425 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1426 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | 1427 RL_FLAG_AUTOPAD | RL_FLAG_MACSLEEP; 1428 break; 1429 case RL_HWREV_8401E: 1430 case RL_HWREV_8105E: 1431 case RL_HWREV_8105E_SPIN1: 1432 case RL_HWREV_8106E: 1433 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1434 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1435 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD; 1436 break; 1437 case RL_HWREV_8402: 1438 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1439 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1440 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | 1441 RL_FLAG_CMDSTOP_WAIT_TXQ; 1442 break; 1443 case RL_HWREV_8168B_SPIN1: 1444 case RL_HWREV_8168B_SPIN2: 1445 sc->rl_flags |= RL_FLAG_WOLRXENB; 1446 /* FALLTHROUGH */ 1447 case RL_HWREV_8168B_SPIN3: 1448 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT; 1449 break; 1450 case RL_HWREV_8168C_SPIN2: 1451 sc->rl_flags |= RL_FLAG_MACSLEEP; 1452 /* FALLTHROUGH */ 1453 case RL_HWREV_8168C: 1454 if (sc->rl_macrev == 0x00200000) 1455 sc->rl_flags |= RL_FLAG_MACSLEEP; 1456 /* FALLTHROUGH */ 1457 case RL_HWREV_8168CP: 1458 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1459 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1460 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK; 1461 break; 1462 case RL_HWREV_8168D: 1463 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1464 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1465 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1466 RL_FLAG_WOL_MANLINK; 1467 break; 1468 case RL_HWREV_8168DP: 1469 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1470 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_AUTOPAD | 1471 RL_FLAG_JUMBOV2 | RL_FLAG_WAIT_TXPOLL | RL_FLAG_WOL_MANLINK; 1472 break; 1473 case RL_HWREV_8168E: 1474 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1475 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1476 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1477 RL_FLAG_WOL_MANLINK; 1478 break; 1479 case RL_HWREV_8168E_VL: 1480 case RL_HWREV_8168F: 1481 sc->rl_flags |= RL_FLAG_EARLYOFF; 1482 /* FALLTHROUGH */ 1483 case RL_HWREV_8411: 1484 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1485 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1486 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1487 RL_FLAG_CMDSTOP_WAIT_TXQ | RL_FLAG_WOL_MANLINK; 1488 break; 1489 case RL_HWREV_8168EP: 1490 case RL_HWREV_8168G: 1491 case RL_HWREV_8411B: 1492 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1493 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1494 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1495 RL_FLAG_CMDSTOP_WAIT_TXQ | RL_FLAG_WOL_MANLINK | 1496 RL_FLAG_8168G_PLUS; 1497 break; 1498 case RL_HWREV_8168GU: 1499 case RL_HWREV_8168H: 1500 if (pci_get_device(dev) == RT_DEVICEID_8101E) { 1501 /* RTL8106E(US), RTL8107E */ 1502 sc->rl_flags |= RL_FLAG_FASTETHER; 1503 } else 1504 sc->rl_flags |= RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK; 1505 1506 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1507 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1508 RL_FLAG_AUTOPAD | RL_FLAG_CMDSTOP_WAIT_TXQ | 1509 RL_FLAG_8168G_PLUS; 1510 break; 1511 case RL_HWREV_8169_8110SB: 1512 case RL_HWREV_8169_8110SBL: 1513 case RL_HWREV_8169_8110SC: 1514 case RL_HWREV_8169_8110SCE: 1515 sc->rl_flags |= RL_FLAG_PHYWAKE; 1516 /* FALLTHROUGH */ 1517 case RL_HWREV_8169: 1518 case RL_HWREV_8169S: 1519 case RL_HWREV_8110S: 1520 sc->rl_flags |= RL_FLAG_MACRESET; 1521 break; 1522 default: 1523 break; 1524 } 1525 1526 if (sc->rl_hwrev->rl_rev == RL_HWREV_8139CPLUS) { 1527 sc->rl_cfg0 = RL_8139_CFG0; 1528 sc->rl_cfg1 = RL_8139_CFG1; 1529 sc->rl_cfg2 = 0; 1530 sc->rl_cfg3 = RL_8139_CFG3; 1531 sc->rl_cfg4 = RL_8139_CFG4; 1532 sc->rl_cfg5 = RL_8139_CFG5; 1533 } else { 1534 sc->rl_cfg0 = RL_CFG0; 1535 sc->rl_cfg1 = RL_CFG1; 1536 sc->rl_cfg2 = RL_CFG2; 1537 sc->rl_cfg3 = RL_CFG3; 1538 sc->rl_cfg4 = RL_CFG4; 1539 sc->rl_cfg5 = RL_CFG5; 1540 } 1541 1542 /* Reset the adapter. */ 1543 RL_LOCK(sc); 1544 re_reset(sc); 1545 RL_UNLOCK(sc); 1546 1547 /* Enable PME. */ 1548 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1549 cfg = CSR_READ_1(sc, sc->rl_cfg1); 1550 cfg |= RL_CFG1_PME; 1551 CSR_WRITE_1(sc, sc->rl_cfg1, cfg); 1552 cfg = CSR_READ_1(sc, sc->rl_cfg5); 1553 cfg &= RL_CFG5_PME_STS; 1554 CSR_WRITE_1(sc, sc->rl_cfg5, cfg); 1555 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1556 1557 if ((sc->rl_flags & RL_FLAG_PAR) != 0) { 1558 /* 1559 * XXX Should have a better way to extract station 1560 * address from EEPROM. 1561 */ 1562 for (i = 0; i < ETHER_ADDR_LEN; i++) 1563 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1564 } else { 1565 sc->rl_eewidth = RL_9356_ADDR_LEN; 1566 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1567 if (re_did != 0x8129) 1568 sc->rl_eewidth = RL_9346_ADDR_LEN; 1569 1570 /* 1571 * Get station address from the EEPROM. 1572 */ 1573 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1574 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1575 as[i] = le16toh(as[i]); 1576 bcopy(as, eaddr, ETHER_ADDR_LEN); 1577 } 1578 1579 if (sc->rl_type == RL_8169) { 1580 /* Set RX length mask and number of descriptors. */ 1581 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1582 sc->rl_txstart = RL_GTXSTART; 1583 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1584 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1585 } else { 1586 /* Set RX length mask and number of descriptors. */ 1587 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1588 sc->rl_txstart = RL_TXSTART; 1589 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1590 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1591 } 1592 1593 error = re_allocmem(dev, sc); 1594 if (error) 1595 goto fail; 1596 re_add_sysctls(sc); 1597 1598 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1599 if (ifp == NULL) { 1600 device_printf(dev, "can not if_alloc()\n"); 1601 error = ENOSPC; 1602 goto fail; 1603 } 1604 1605 /* Take controller out of deep sleep mode. */ 1606 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 1607 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 1608 CSR_WRITE_1(sc, RL_GPIO, 1609 CSR_READ_1(sc, RL_GPIO) | 0x01); 1610 else 1611 CSR_WRITE_1(sc, RL_GPIO, 1612 CSR_READ_1(sc, RL_GPIO) & ~0x01); 1613 } 1614 1615 /* Take PHY out of power down mode. */ 1616 if ((sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) { 1617 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80); 1618 if (hw_rev->rl_rev == RL_HWREV_8401E) 1619 CSR_WRITE_1(sc, 0xD1, CSR_READ_1(sc, 0xD1) & ~0x08); 1620 } 1621 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) { 1622 re_gmii_writereg(dev, 1, 0x1f, 0); 1623 re_gmii_writereg(dev, 1, 0x0e, 0); 1624 } 1625 1626 ifp->if_softc = sc; 1627 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1628 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1629 ifp->if_ioctl = re_ioctl; 1630 ifp->if_start = re_start; 1631 /* 1632 * RTL8168/8111C generates wrong IP checksummed frame if the 1633 * packet has IP options so disable TX checksum offloading. 1634 */ 1635 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168C || 1636 sc->rl_hwrev->rl_rev == RL_HWREV_8168C_SPIN2 || 1637 sc->rl_hwrev->rl_rev == RL_HWREV_8168CP) { 1638 ifp->if_hwassist = 0; 1639 ifp->if_capabilities = IFCAP_RXCSUM | IFCAP_TSO4; 1640 } else { 1641 ifp->if_hwassist = CSUM_IP | CSUM_TCP | CSUM_UDP; 1642 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 1643 } 1644 ifp->if_hwassist |= CSUM_TSO; 1645 ifp->if_capenable = ifp->if_capabilities; 1646 ifp->if_init = re_init; 1647 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1648 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1649 IFQ_SET_READY(&ifp->if_snd); 1650 1651 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1652 1653 #define RE_PHYAD_INTERNAL 0 1654 1655 /* Do MII setup. */ 1656 phy = RE_PHYAD_INTERNAL; 1657 if (sc->rl_type == RL_8169) 1658 phy = 1; 1659 capmask = BMSR_DEFCAPMASK; 1660 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0) 1661 capmask &= ~BMSR_EXTSTAT; 1662 error = mii_attach(dev, &sc->rl_miibus, ifp, re_ifmedia_upd, 1663 re_ifmedia_sts, capmask, phy, MII_OFFSET_ANY, MIIF_DOPAUSE); 1664 if (error != 0) { 1665 device_printf(dev, "attaching PHYs failed\n"); 1666 goto fail; 1667 } 1668 1669 /* 1670 * Call MI attach routine. 1671 */ 1672 ether_ifattach(ifp, eaddr); 1673 1674 /* VLAN capability setup */ 1675 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1676 if (ifp->if_capabilities & IFCAP_HWCSUM) 1677 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1678 /* Enable WOL if PM is supported. */ 1679 if (pci_find_cap(sc->rl_dev, PCIY_PMG, ®) == 0) 1680 ifp->if_capabilities |= IFCAP_WOL; 1681 ifp->if_capenable = ifp->if_capabilities; 1682 ifp->if_capenable &= ~(IFCAP_WOL_UCAST | IFCAP_WOL_MCAST); 1683 /* 1684 * Don't enable TSO by default. It is known to generate 1685 * corrupted TCP segments(bad TCP options) under certain 1686 * circumstances. 1687 */ 1688 ifp->if_hwassist &= ~CSUM_TSO; 1689 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO); 1690 #ifdef DEVICE_POLLING 1691 ifp->if_capabilities |= IFCAP_POLLING; 1692 #endif 1693 /* 1694 * Tell the upper layer(s) we support long frames. 1695 * Must appear after the call to ether_ifattach() because 1696 * ether_ifattach() sets ifi_hdrlen to the default value. 1697 */ 1698 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 1699 1700 #ifdef DEV_NETMAP 1701 re_netmap_attach(sc); 1702 #endif /* DEV_NETMAP */ 1703 1704 #ifdef RE_DIAG 1705 /* 1706 * Perform hardware diagnostic on the original RTL8169. 1707 * Some 32-bit cards were incorrectly wired and would 1708 * malfunction if plugged into a 64-bit slot. 1709 */ 1710 if (hwrev == RL_HWREV_8169) { 1711 error = re_diag(sc); 1712 if (error) { 1713 device_printf(dev, 1714 "attach aborted due to hardware diag failure\n"); 1715 ether_ifdetach(ifp); 1716 goto fail; 1717 } 1718 } 1719 #endif 1720 1721 #ifdef RE_TX_MODERATION 1722 intr_filter = 1; 1723 #endif 1724 /* Hook interrupt last to avoid having to lock softc */ 1725 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 && 1726 intr_filter == 0) { 1727 error = bus_setup_intr(dev, sc->rl_irq[0], 1728 INTR_TYPE_NET | INTR_MPSAFE, NULL, re_intr_msi, sc, 1729 &sc->rl_intrhand[0]); 1730 } else { 1731 error = bus_setup_intr(dev, sc->rl_irq[0], 1732 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1733 &sc->rl_intrhand[0]); 1734 } 1735 if (error) { 1736 device_printf(dev, "couldn't set up irq\n"); 1737 ether_ifdetach(ifp); 1738 } 1739 1740 fail: 1741 if (error) 1742 re_detach(dev); 1743 1744 return (error); 1745 } 1746 1747 /* 1748 * Shutdown hardware and free up resources. This can be called any 1749 * time after the mutex has been initialized. It is called in both 1750 * the error case in attach and the normal detach case so it needs 1751 * to be careful about only freeing resources that have actually been 1752 * allocated. 1753 */ 1754 static int 1755 re_detach(device_t dev) 1756 { 1757 struct rl_softc *sc; 1758 struct ifnet *ifp; 1759 int i, rid; 1760 1761 sc = device_get_softc(dev); 1762 ifp = sc->rl_ifp; 1763 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1764 1765 /* These should only be active if attach succeeded */ 1766 if (device_is_attached(dev)) { 1767 #ifdef DEVICE_POLLING 1768 if (ifp->if_capenable & IFCAP_POLLING) 1769 ether_poll_deregister(ifp); 1770 #endif 1771 RL_LOCK(sc); 1772 #if 0 1773 sc->suspended = 1; 1774 #endif 1775 re_stop(sc); 1776 RL_UNLOCK(sc); 1777 callout_drain(&sc->rl_stat_callout); 1778 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1779 /* 1780 * Force off the IFF_UP flag here, in case someone 1781 * still had a BPF descriptor attached to this 1782 * interface. If they do, ether_ifdetach() will cause 1783 * the BPF code to try and clear the promisc mode 1784 * flag, which will bubble down to re_ioctl(), 1785 * which will try to call re_init() again. This will 1786 * turn the NIC back on and restart the MII ticker, 1787 * which will panic the system when the kernel tries 1788 * to invoke the re_tick() function that isn't there 1789 * anymore. 1790 */ 1791 ifp->if_flags &= ~IFF_UP; 1792 ether_ifdetach(ifp); 1793 } 1794 if (sc->rl_miibus) 1795 device_delete_child(dev, sc->rl_miibus); 1796 bus_generic_detach(dev); 1797 1798 /* 1799 * The rest is resource deallocation, so we should already be 1800 * stopped here. 1801 */ 1802 1803 if (sc->rl_intrhand[0] != NULL) { 1804 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]); 1805 sc->rl_intrhand[0] = NULL; 1806 } 1807 if (ifp != NULL) { 1808 #ifdef DEV_NETMAP 1809 netmap_detach(ifp); 1810 #endif /* DEV_NETMAP */ 1811 if_free(ifp); 1812 } 1813 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) 1814 rid = 0; 1815 else 1816 rid = 1; 1817 if (sc->rl_irq[0] != NULL) { 1818 bus_release_resource(dev, SYS_RES_IRQ, rid, sc->rl_irq[0]); 1819 sc->rl_irq[0] = NULL; 1820 } 1821 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0) 1822 pci_release_msi(dev); 1823 if (sc->rl_res_pba) { 1824 rid = PCIR_BAR(4); 1825 bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->rl_res_pba); 1826 } 1827 if (sc->rl_res) 1828 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, 1829 sc->rl_res); 1830 1831 /* Unload and free the RX DMA ring memory and map */ 1832 1833 if (sc->rl_ldata.rl_rx_list_tag) { 1834 if (sc->rl_ldata.rl_rx_list_addr) 1835 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1836 sc->rl_ldata.rl_rx_list_map); 1837 if (sc->rl_ldata.rl_rx_list) 1838 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1839 sc->rl_ldata.rl_rx_list, 1840 sc->rl_ldata.rl_rx_list_map); 1841 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1842 } 1843 1844 /* Unload and free the TX DMA ring memory and map */ 1845 1846 if (sc->rl_ldata.rl_tx_list_tag) { 1847 if (sc->rl_ldata.rl_tx_list_addr) 1848 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1849 sc->rl_ldata.rl_tx_list_map); 1850 if (sc->rl_ldata.rl_tx_list) 1851 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1852 sc->rl_ldata.rl_tx_list, 1853 sc->rl_ldata.rl_tx_list_map); 1854 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1855 } 1856 1857 /* Destroy all the RX and TX buffer maps */ 1858 1859 if (sc->rl_ldata.rl_tx_mtag) { 1860 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1861 if (sc->rl_ldata.rl_tx_desc[i].tx_dmamap) 1862 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1863 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1864 } 1865 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1866 } 1867 if (sc->rl_ldata.rl_rx_mtag) { 1868 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1869 if (sc->rl_ldata.rl_rx_desc[i].rx_dmamap) 1870 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1871 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1872 } 1873 if (sc->rl_ldata.rl_rx_sparemap) 1874 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1875 sc->rl_ldata.rl_rx_sparemap); 1876 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1877 } 1878 if (sc->rl_ldata.rl_jrx_mtag) { 1879 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1880 if (sc->rl_ldata.rl_jrx_desc[i].rx_dmamap) 1881 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag, 1882 sc->rl_ldata.rl_jrx_desc[i].rx_dmamap); 1883 } 1884 if (sc->rl_ldata.rl_jrx_sparemap) 1885 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag, 1886 sc->rl_ldata.rl_jrx_sparemap); 1887 bus_dma_tag_destroy(sc->rl_ldata.rl_jrx_mtag); 1888 } 1889 /* Unload and free the stats buffer and map */ 1890 1891 if (sc->rl_ldata.rl_stag) { 1892 if (sc->rl_ldata.rl_stats_addr) 1893 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1894 sc->rl_ldata.rl_smap); 1895 if (sc->rl_ldata.rl_stats) 1896 bus_dmamem_free(sc->rl_ldata.rl_stag, 1897 sc->rl_ldata.rl_stats, sc->rl_ldata.rl_smap); 1898 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1899 } 1900 1901 if (sc->rl_parent_tag) 1902 bus_dma_tag_destroy(sc->rl_parent_tag); 1903 1904 mtx_destroy(&sc->rl_mtx); 1905 1906 return (0); 1907 } 1908 1909 static __inline void 1910 re_discard_rxbuf(struct rl_softc *sc, int idx) 1911 { 1912 struct rl_desc *desc; 1913 struct rl_rxdesc *rxd; 1914 uint32_t cmdstat; 1915 1916 if (sc->rl_ifp->if_mtu > RL_MTU && 1917 (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) 1918 rxd = &sc->rl_ldata.rl_jrx_desc[idx]; 1919 else 1920 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1921 desc = &sc->rl_ldata.rl_rx_list[idx]; 1922 desc->rl_vlanctl = 0; 1923 cmdstat = rxd->rx_size; 1924 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1925 cmdstat |= RL_RDESC_CMD_EOR; 1926 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1927 } 1928 1929 static int 1930 re_newbuf(struct rl_softc *sc, int idx) 1931 { 1932 struct mbuf *m; 1933 struct rl_rxdesc *rxd; 1934 bus_dma_segment_t segs[1]; 1935 bus_dmamap_t map; 1936 struct rl_desc *desc; 1937 uint32_t cmdstat; 1938 int error, nsegs; 1939 1940 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1941 if (m == NULL) 1942 return (ENOBUFS); 1943 1944 m->m_len = m->m_pkthdr.len = MCLBYTES; 1945 #ifdef RE_FIXUP_RX 1946 /* 1947 * This is part of an evil trick to deal with non-x86 platforms. 1948 * The RealTek chip requires RX buffers to be aligned on 64-bit 1949 * boundaries, but that will hose non-x86 machines. To get around 1950 * this, we leave some empty space at the start of each buffer 1951 * and for non-x86 hosts, we copy the buffer back six bytes 1952 * to achieve word alignment. This is slightly more efficient 1953 * than allocating a new buffer, copying the contents, and 1954 * discarding the old buffer. 1955 */ 1956 m_adj(m, RE_ETHER_ALIGN); 1957 #endif 1958 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1959 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1960 if (error != 0) { 1961 m_freem(m); 1962 return (ENOBUFS); 1963 } 1964 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1965 1966 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1967 if (rxd->rx_m != NULL) { 1968 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1969 BUS_DMASYNC_POSTREAD); 1970 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1971 } 1972 1973 rxd->rx_m = m; 1974 map = rxd->rx_dmamap; 1975 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1976 rxd->rx_size = segs[0].ds_len; 1977 sc->rl_ldata.rl_rx_sparemap = map; 1978 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1979 BUS_DMASYNC_PREREAD); 1980 1981 desc = &sc->rl_ldata.rl_rx_list[idx]; 1982 desc->rl_vlanctl = 0; 1983 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1984 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1985 cmdstat = segs[0].ds_len; 1986 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1987 cmdstat |= RL_RDESC_CMD_EOR; 1988 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1989 1990 return (0); 1991 } 1992 1993 static int 1994 re_jumbo_newbuf(struct rl_softc *sc, int idx) 1995 { 1996 struct mbuf *m; 1997 struct rl_rxdesc *rxd; 1998 bus_dma_segment_t segs[1]; 1999 bus_dmamap_t map; 2000 struct rl_desc *desc; 2001 uint32_t cmdstat; 2002 int error, nsegs; 2003 2004 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 2005 if (m == NULL) 2006 return (ENOBUFS); 2007 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 2008 #ifdef RE_FIXUP_RX 2009 m_adj(m, RE_ETHER_ALIGN); 2010 #endif 2011 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_jrx_mtag, 2012 sc->rl_ldata.rl_jrx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 2013 if (error != 0) { 2014 m_freem(m); 2015 return (ENOBUFS); 2016 } 2017 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 2018 2019 rxd = &sc->rl_ldata.rl_jrx_desc[idx]; 2020 if (rxd->rx_m != NULL) { 2021 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap, 2022 BUS_DMASYNC_POSTREAD); 2023 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap); 2024 } 2025 2026 rxd->rx_m = m; 2027 map = rxd->rx_dmamap; 2028 rxd->rx_dmamap = sc->rl_ldata.rl_jrx_sparemap; 2029 rxd->rx_size = segs[0].ds_len; 2030 sc->rl_ldata.rl_jrx_sparemap = map; 2031 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap, 2032 BUS_DMASYNC_PREREAD); 2033 2034 desc = &sc->rl_ldata.rl_rx_list[idx]; 2035 desc->rl_vlanctl = 0; 2036 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 2037 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 2038 cmdstat = segs[0].ds_len; 2039 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 2040 cmdstat |= RL_RDESC_CMD_EOR; 2041 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 2042 2043 return (0); 2044 } 2045 2046 #ifdef RE_FIXUP_RX 2047 static __inline void 2048 re_fixup_rx(struct mbuf *m) 2049 { 2050 int i; 2051 uint16_t *src, *dst; 2052 2053 src = mtod(m, uint16_t *); 2054 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 2055 2056 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 2057 *dst++ = *src++; 2058 2059 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 2060 } 2061 #endif 2062 2063 static int 2064 re_tx_list_init(struct rl_softc *sc) 2065 { 2066 struct rl_desc *desc; 2067 int i; 2068 2069 RL_LOCK_ASSERT(sc); 2070 2071 bzero(sc->rl_ldata.rl_tx_list, 2072 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 2073 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 2074 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 2075 #ifdef DEV_NETMAP 2076 re_netmap_tx_init(sc); 2077 #endif /* DEV_NETMAP */ 2078 /* Set EOR. */ 2079 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 2080 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 2081 2082 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2083 sc->rl_ldata.rl_tx_list_map, 2084 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2085 2086 sc->rl_ldata.rl_tx_prodidx = 0; 2087 sc->rl_ldata.rl_tx_considx = 0; 2088 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 2089 2090 return (0); 2091 } 2092 2093 static int 2094 re_rx_list_init(struct rl_softc *sc) 2095 { 2096 int error, i; 2097 2098 bzero(sc->rl_ldata.rl_rx_list, 2099 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 2100 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2101 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 2102 if ((error = re_newbuf(sc, i)) != 0) 2103 return (error); 2104 } 2105 #ifdef DEV_NETMAP 2106 re_netmap_rx_init(sc); 2107 #endif /* DEV_NETMAP */ 2108 2109 /* Flush the RX descriptors */ 2110 2111 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2112 sc->rl_ldata.rl_rx_list_map, 2113 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2114 2115 sc->rl_ldata.rl_rx_prodidx = 0; 2116 sc->rl_head = sc->rl_tail = NULL; 2117 sc->rl_int_rx_act = 0; 2118 2119 return (0); 2120 } 2121 2122 static int 2123 re_jrx_list_init(struct rl_softc *sc) 2124 { 2125 int error, i; 2126 2127 bzero(sc->rl_ldata.rl_rx_list, 2128 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 2129 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2130 sc->rl_ldata.rl_jrx_desc[i].rx_m = NULL; 2131 if ((error = re_jumbo_newbuf(sc, i)) != 0) 2132 return (error); 2133 } 2134 2135 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2136 sc->rl_ldata.rl_rx_list_map, 2137 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2138 2139 sc->rl_ldata.rl_rx_prodidx = 0; 2140 sc->rl_head = sc->rl_tail = NULL; 2141 sc->rl_int_rx_act = 0; 2142 2143 return (0); 2144 } 2145 2146 /* 2147 * RX handler for C+ and 8169. For the gigE chips, we support 2148 * the reception of jumbo frames that have been fragmented 2149 * across multiple 2K mbuf cluster buffers. 2150 */ 2151 static int 2152 re_rxeof(struct rl_softc *sc, int *rx_npktsp) 2153 { 2154 struct mbuf *m; 2155 struct ifnet *ifp; 2156 int i, rxerr, total_len; 2157 struct rl_desc *cur_rx; 2158 u_int32_t rxstat, rxvlan; 2159 int jumbo, maxpkt = 16, rx_npkts = 0; 2160 2161 RL_LOCK_ASSERT(sc); 2162 2163 ifp = sc->rl_ifp; 2164 #ifdef DEV_NETMAP 2165 if (netmap_rx_irq(ifp, 0, &rx_npkts)) 2166 return 0; 2167 #endif /* DEV_NETMAP */ 2168 if (ifp->if_mtu > RL_MTU && (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) 2169 jumbo = 1; 2170 else 2171 jumbo = 0; 2172 2173 /* Invalidate the descriptor memory */ 2174 2175 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2176 sc->rl_ldata.rl_rx_list_map, 2177 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2178 2179 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 2180 i = RL_RX_DESC_NXT(sc, i)) { 2181 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2182 break; 2183 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 2184 rxstat = le32toh(cur_rx->rl_cmdstat); 2185 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 2186 break; 2187 total_len = rxstat & sc->rl_rxlenmask; 2188 rxvlan = le32toh(cur_rx->rl_vlanctl); 2189 if (jumbo != 0) 2190 m = sc->rl_ldata.rl_jrx_desc[i].rx_m; 2191 else 2192 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 2193 2194 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 2195 (rxstat & (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) != 2196 (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) { 2197 /* 2198 * RTL8168C or later controllers do not 2199 * support multi-fragment packet. 2200 */ 2201 re_discard_rxbuf(sc, i); 2202 continue; 2203 } else if ((rxstat & RL_RDESC_STAT_EOF) == 0) { 2204 if (re_newbuf(sc, i) != 0) { 2205 /* 2206 * If this is part of a multi-fragment packet, 2207 * discard all the pieces. 2208 */ 2209 if (sc->rl_head != NULL) { 2210 m_freem(sc->rl_head); 2211 sc->rl_head = sc->rl_tail = NULL; 2212 } 2213 re_discard_rxbuf(sc, i); 2214 continue; 2215 } 2216 m->m_len = RE_RX_DESC_BUFLEN; 2217 if (sc->rl_head == NULL) 2218 sc->rl_head = sc->rl_tail = m; 2219 else { 2220 m->m_flags &= ~M_PKTHDR; 2221 sc->rl_tail->m_next = m; 2222 sc->rl_tail = m; 2223 } 2224 continue; 2225 } 2226 2227 /* 2228 * NOTE: for the 8139C+, the frame length field 2229 * is always 12 bits in size, but for the gigE chips, 2230 * it is 13 bits (since the max RX frame length is 16K). 2231 * Unfortunately, all 32 bits in the status word 2232 * were already used, so to make room for the extra 2233 * length bit, RealTek took out the 'frame alignment 2234 * error' bit and shifted the other status bits 2235 * over one slot. The OWN, EOR, FS and LS bits are 2236 * still in the same places. We have already extracted 2237 * the frame length and checked the OWN bit, so rather 2238 * than using an alternate bit mapping, we shift the 2239 * status bits one space to the right so we can evaluate 2240 * them using the 8169 status as though it was in the 2241 * same format as that of the 8139C+. 2242 */ 2243 if (sc->rl_type == RL_8169) 2244 rxstat >>= 1; 2245 2246 /* 2247 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 2248 * set, but if CRC is clear, it will still be a valid frame. 2249 */ 2250 if ((rxstat & RL_RDESC_STAT_RXERRSUM) != 0) { 2251 rxerr = 1; 2252 if ((sc->rl_flags & RL_FLAG_JUMBOV2) == 0 && 2253 total_len > 8191 && 2254 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT) 2255 rxerr = 0; 2256 if (rxerr != 0) { 2257 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2258 /* 2259 * If this is part of a multi-fragment packet, 2260 * discard all the pieces. 2261 */ 2262 if (sc->rl_head != NULL) { 2263 m_freem(sc->rl_head); 2264 sc->rl_head = sc->rl_tail = NULL; 2265 } 2266 re_discard_rxbuf(sc, i); 2267 continue; 2268 } 2269 } 2270 2271 /* 2272 * If allocating a replacement mbuf fails, 2273 * reload the current one. 2274 */ 2275 if (jumbo != 0) 2276 rxerr = re_jumbo_newbuf(sc, i); 2277 else 2278 rxerr = re_newbuf(sc, i); 2279 if (rxerr != 0) { 2280 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2281 if (sc->rl_head != NULL) { 2282 m_freem(sc->rl_head); 2283 sc->rl_head = sc->rl_tail = NULL; 2284 } 2285 re_discard_rxbuf(sc, i); 2286 continue; 2287 } 2288 2289 if (sc->rl_head != NULL) { 2290 if (jumbo != 0) 2291 m->m_len = total_len; 2292 else { 2293 m->m_len = total_len % RE_RX_DESC_BUFLEN; 2294 if (m->m_len == 0) 2295 m->m_len = RE_RX_DESC_BUFLEN; 2296 } 2297 /* 2298 * Special case: if there's 4 bytes or less 2299 * in this buffer, the mbuf can be discarded: 2300 * the last 4 bytes is the CRC, which we don't 2301 * care about anyway. 2302 */ 2303 if (m->m_len <= ETHER_CRC_LEN) { 2304 sc->rl_tail->m_len -= 2305 (ETHER_CRC_LEN - m->m_len); 2306 m_freem(m); 2307 } else { 2308 m->m_len -= ETHER_CRC_LEN; 2309 m->m_flags &= ~M_PKTHDR; 2310 sc->rl_tail->m_next = m; 2311 } 2312 m = sc->rl_head; 2313 sc->rl_head = sc->rl_tail = NULL; 2314 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 2315 } else 2316 m->m_pkthdr.len = m->m_len = 2317 (total_len - ETHER_CRC_LEN); 2318 2319 #ifdef RE_FIXUP_RX 2320 re_fixup_rx(m); 2321 #endif 2322 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 2323 m->m_pkthdr.rcvif = ifp; 2324 2325 /* Do RX checksumming if enabled */ 2326 2327 if (ifp->if_capenable & IFCAP_RXCSUM) { 2328 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2329 /* Check IP header checksum */ 2330 if (rxstat & RL_RDESC_STAT_PROTOID) 2331 m->m_pkthdr.csum_flags |= 2332 CSUM_IP_CHECKED; 2333 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 2334 m->m_pkthdr.csum_flags |= 2335 CSUM_IP_VALID; 2336 2337 /* Check TCP/UDP checksum */ 2338 if ((RL_TCPPKT(rxstat) && 2339 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 2340 (RL_UDPPKT(rxstat) && 2341 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 2342 m->m_pkthdr.csum_flags |= 2343 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2344 m->m_pkthdr.csum_data = 0xffff; 2345 } 2346 } else { 2347 /* 2348 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP 2349 */ 2350 if ((rxstat & RL_RDESC_STAT_PROTOID) && 2351 (rxvlan & RL_RDESC_IPV4)) 2352 m->m_pkthdr.csum_flags |= 2353 CSUM_IP_CHECKED; 2354 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) && 2355 (rxvlan & RL_RDESC_IPV4)) 2356 m->m_pkthdr.csum_flags |= 2357 CSUM_IP_VALID; 2358 if (((rxstat & RL_RDESC_STAT_TCP) && 2359 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 2360 ((rxstat & RL_RDESC_STAT_UDP) && 2361 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 2362 m->m_pkthdr.csum_flags |= 2363 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2364 m->m_pkthdr.csum_data = 0xffff; 2365 } 2366 } 2367 } 2368 maxpkt--; 2369 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 2370 m->m_pkthdr.ether_vtag = 2371 bswap16((rxvlan & RL_RDESC_VLANCTL_DATA)); 2372 m->m_flags |= M_VLANTAG; 2373 } 2374 RL_UNLOCK(sc); 2375 (*ifp->if_input)(ifp, m); 2376 RL_LOCK(sc); 2377 rx_npkts++; 2378 } 2379 2380 /* Flush the RX DMA ring */ 2381 2382 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2383 sc->rl_ldata.rl_rx_list_map, 2384 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2385 2386 sc->rl_ldata.rl_rx_prodidx = i; 2387 2388 if (rx_npktsp != NULL) 2389 *rx_npktsp = rx_npkts; 2390 if (maxpkt) 2391 return (EAGAIN); 2392 2393 return (0); 2394 } 2395 2396 static void 2397 re_txeof(struct rl_softc *sc) 2398 { 2399 struct ifnet *ifp; 2400 struct rl_txdesc *txd; 2401 u_int32_t txstat; 2402 int cons; 2403 2404 cons = sc->rl_ldata.rl_tx_considx; 2405 if (cons == sc->rl_ldata.rl_tx_prodidx) 2406 return; 2407 2408 ifp = sc->rl_ifp; 2409 #ifdef DEV_NETMAP 2410 if (netmap_tx_irq(ifp, 0)) 2411 return; 2412 #endif /* DEV_NETMAP */ 2413 /* Invalidate the TX descriptor list */ 2414 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2415 sc->rl_ldata.rl_tx_list_map, 2416 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2417 2418 for (; cons != sc->rl_ldata.rl_tx_prodidx; 2419 cons = RL_TX_DESC_NXT(sc, cons)) { 2420 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 2421 if (txstat & RL_TDESC_STAT_OWN) 2422 break; 2423 /* 2424 * We only stash mbufs in the last descriptor 2425 * in a fragment chain, which also happens to 2426 * be the only place where the TX status bits 2427 * are valid. 2428 */ 2429 if (txstat & RL_TDESC_CMD_EOF) { 2430 txd = &sc->rl_ldata.rl_tx_desc[cons]; 2431 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2432 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2433 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2434 txd->tx_dmamap); 2435 KASSERT(txd->tx_m != NULL, 2436 ("%s: freeing NULL mbufs!", __func__)); 2437 m_freem(txd->tx_m); 2438 txd->tx_m = NULL; 2439 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 2440 RL_TDESC_STAT_COLCNT)) 2441 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 2442 if (txstat & RL_TDESC_STAT_TXERRSUM) 2443 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2444 else 2445 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 2446 } 2447 sc->rl_ldata.rl_tx_free++; 2448 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2449 } 2450 sc->rl_ldata.rl_tx_considx = cons; 2451 2452 /* No changes made to the TX ring, so no flush needed */ 2453 2454 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 2455 #ifdef RE_TX_MODERATION 2456 /* 2457 * If not all descriptors have been reaped yet, reload 2458 * the timer so that we will eventually get another 2459 * interrupt that will cause us to re-enter this routine. 2460 * This is done in case the transmitter has gone idle. 2461 */ 2462 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2463 #endif 2464 } else 2465 sc->rl_watchdog_timer = 0; 2466 } 2467 2468 static void 2469 re_tick(void *xsc) 2470 { 2471 struct rl_softc *sc; 2472 struct mii_data *mii; 2473 2474 sc = xsc; 2475 2476 RL_LOCK_ASSERT(sc); 2477 2478 mii = device_get_softc(sc->rl_miibus); 2479 mii_tick(mii); 2480 if ((sc->rl_flags & RL_FLAG_LINK) == 0) 2481 re_miibus_statchg(sc->rl_dev); 2482 /* 2483 * Reclaim transmitted frames here. Technically it is not 2484 * necessary to do here but it ensures periodic reclamation 2485 * regardless of Tx completion interrupt which seems to be 2486 * lost on PCIe based controllers under certain situations. 2487 */ 2488 re_txeof(sc); 2489 re_watchdog(sc); 2490 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2491 } 2492 2493 #ifdef DEVICE_POLLING 2494 static int 2495 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2496 { 2497 struct rl_softc *sc = ifp->if_softc; 2498 int rx_npkts = 0; 2499 2500 RL_LOCK(sc); 2501 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2502 rx_npkts = re_poll_locked(ifp, cmd, count); 2503 RL_UNLOCK(sc); 2504 return (rx_npkts); 2505 } 2506 2507 static int 2508 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2509 { 2510 struct rl_softc *sc = ifp->if_softc; 2511 int rx_npkts; 2512 2513 RL_LOCK_ASSERT(sc); 2514 2515 sc->rxcycles = count; 2516 re_rxeof(sc, &rx_npkts); 2517 re_txeof(sc); 2518 2519 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2520 re_start_locked(ifp); 2521 2522 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2523 u_int16_t status; 2524 2525 status = CSR_READ_2(sc, RL_ISR); 2526 if (status == 0xffff) 2527 return (rx_npkts); 2528 if (status) 2529 CSR_WRITE_2(sc, RL_ISR, status); 2530 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2531 (sc->rl_flags & RL_FLAG_PCIE)) 2532 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2533 2534 /* 2535 * XXX check behaviour on receiver stalls. 2536 */ 2537 2538 if (status & RL_ISR_SYSTEM_ERR) { 2539 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2540 re_init_locked(sc); 2541 } 2542 } 2543 return (rx_npkts); 2544 } 2545 #endif /* DEVICE_POLLING */ 2546 2547 static int 2548 re_intr(void *arg) 2549 { 2550 struct rl_softc *sc; 2551 uint16_t status; 2552 2553 sc = arg; 2554 2555 status = CSR_READ_2(sc, RL_ISR); 2556 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2557 return (FILTER_STRAY); 2558 CSR_WRITE_2(sc, RL_IMR, 0); 2559 2560 taskqueue_enqueue(taskqueue_fast, &sc->rl_inttask); 2561 2562 return (FILTER_HANDLED); 2563 } 2564 2565 static void 2566 re_int_task(void *arg, int npending) 2567 { 2568 struct rl_softc *sc; 2569 struct ifnet *ifp; 2570 u_int16_t status; 2571 int rval = 0; 2572 2573 sc = arg; 2574 ifp = sc->rl_ifp; 2575 2576 RL_LOCK(sc); 2577 2578 status = CSR_READ_2(sc, RL_ISR); 2579 CSR_WRITE_2(sc, RL_ISR, status); 2580 2581 if (sc->suspended || 2582 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2583 RL_UNLOCK(sc); 2584 return; 2585 } 2586 2587 #ifdef DEVICE_POLLING 2588 if (ifp->if_capenable & IFCAP_POLLING) { 2589 RL_UNLOCK(sc); 2590 return; 2591 } 2592 #endif 2593 2594 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2595 rval = re_rxeof(sc, NULL); 2596 2597 /* 2598 * Some chips will ignore a second TX request issued 2599 * while an existing transmission is in progress. If 2600 * the transmitter goes idle but there are still 2601 * packets waiting to be sent, we need to restart the 2602 * channel here to flush them out. This only seems to 2603 * be required with the PCIe devices. 2604 */ 2605 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2606 (sc->rl_flags & RL_FLAG_PCIE)) 2607 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2608 if (status & ( 2609 #ifdef RE_TX_MODERATION 2610 RL_ISR_TIMEOUT_EXPIRED| 2611 #else 2612 RL_ISR_TX_OK| 2613 #endif 2614 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2615 re_txeof(sc); 2616 2617 if (status & RL_ISR_SYSTEM_ERR) { 2618 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2619 re_init_locked(sc); 2620 } 2621 2622 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2623 re_start_locked(ifp); 2624 2625 RL_UNLOCK(sc); 2626 2627 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2628 taskqueue_enqueue(taskqueue_fast, &sc->rl_inttask); 2629 return; 2630 } 2631 2632 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2633 } 2634 2635 static void 2636 re_intr_msi(void *xsc) 2637 { 2638 struct rl_softc *sc; 2639 struct ifnet *ifp; 2640 uint16_t intrs, status; 2641 2642 sc = xsc; 2643 RL_LOCK(sc); 2644 2645 ifp = sc->rl_ifp; 2646 #ifdef DEVICE_POLLING 2647 if (ifp->if_capenable & IFCAP_POLLING) { 2648 RL_UNLOCK(sc); 2649 return; 2650 } 2651 #endif 2652 /* Disable interrupts. */ 2653 CSR_WRITE_2(sc, RL_IMR, 0); 2654 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2655 RL_UNLOCK(sc); 2656 return; 2657 } 2658 2659 intrs = RL_INTRS_CPLUS; 2660 status = CSR_READ_2(sc, RL_ISR); 2661 CSR_WRITE_2(sc, RL_ISR, status); 2662 if (sc->rl_int_rx_act > 0) { 2663 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW | 2664 RL_ISR_RX_OVERRUN); 2665 status &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW | 2666 RL_ISR_RX_OVERRUN); 2667 } 2668 2669 if (status & (RL_ISR_TIMEOUT_EXPIRED | RL_ISR_RX_OK | RL_ISR_RX_ERR | 2670 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) { 2671 re_rxeof(sc, NULL); 2672 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2673 if (sc->rl_int_rx_mod != 0 && 2674 (status & (RL_ISR_RX_OK | RL_ISR_RX_ERR | 2675 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) != 0) { 2676 /* Rearm one-shot timer. */ 2677 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2678 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | 2679 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN); 2680 sc->rl_int_rx_act = 1; 2681 } else { 2682 intrs |= RL_ISR_RX_OK | RL_ISR_RX_ERR | 2683 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN; 2684 sc->rl_int_rx_act = 0; 2685 } 2686 } 2687 } 2688 2689 /* 2690 * Some chips will ignore a second TX request issued 2691 * while an existing transmission is in progress. If 2692 * the transmitter goes idle but there are still 2693 * packets waiting to be sent, we need to restart the 2694 * channel here to flush them out. This only seems to 2695 * be required with the PCIe devices. 2696 */ 2697 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2698 (sc->rl_flags & RL_FLAG_PCIE)) 2699 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2700 if (status & (RL_ISR_TX_OK | RL_ISR_TX_ERR | RL_ISR_TX_DESC_UNAVAIL)) 2701 re_txeof(sc); 2702 2703 if (status & RL_ISR_SYSTEM_ERR) { 2704 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2705 re_init_locked(sc); 2706 } 2707 2708 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2709 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2710 re_start_locked(ifp); 2711 CSR_WRITE_2(sc, RL_IMR, intrs); 2712 } 2713 RL_UNLOCK(sc); 2714 } 2715 2716 static int 2717 re_encap(struct rl_softc *sc, struct mbuf **m_head) 2718 { 2719 struct rl_txdesc *txd, *txd_last; 2720 bus_dma_segment_t segs[RL_NTXSEGS]; 2721 bus_dmamap_t map; 2722 struct mbuf *m_new; 2723 struct rl_desc *desc; 2724 int nsegs, prod; 2725 int i, error, ei, si; 2726 int padlen; 2727 uint32_t cmdstat, csum_flags, vlanctl; 2728 2729 RL_LOCK_ASSERT(sc); 2730 M_ASSERTPKTHDR((*m_head)); 2731 2732 /* 2733 * With some of the RealTek chips, using the checksum offload 2734 * support in conjunction with the autopadding feature results 2735 * in the transmission of corrupt frames. For example, if we 2736 * need to send a really small IP fragment that's less than 60 2737 * bytes in size, and IP header checksumming is enabled, the 2738 * resulting ethernet frame that appears on the wire will 2739 * have garbled payload. To work around this, if TX IP checksum 2740 * offload is enabled, we always manually pad short frames out 2741 * to the minimum ethernet frame size. 2742 */ 2743 if ((sc->rl_flags & RL_FLAG_AUTOPAD) == 0 && 2744 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN && 2745 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) { 2746 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2747 if (M_WRITABLE(*m_head) == 0) { 2748 /* Get a writable copy. */ 2749 m_new = m_dup(*m_head, M_NOWAIT); 2750 m_freem(*m_head); 2751 if (m_new == NULL) { 2752 *m_head = NULL; 2753 return (ENOBUFS); 2754 } 2755 *m_head = m_new; 2756 } 2757 if ((*m_head)->m_next != NULL || 2758 M_TRAILINGSPACE(*m_head) < padlen) { 2759 m_new = m_defrag(*m_head, M_NOWAIT); 2760 if (m_new == NULL) { 2761 m_freem(*m_head); 2762 *m_head = NULL; 2763 return (ENOBUFS); 2764 } 2765 } else 2766 m_new = *m_head; 2767 2768 /* 2769 * Manually pad short frames, and zero the pad space 2770 * to avoid leaking data. 2771 */ 2772 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2773 m_new->m_pkthdr.len += padlen; 2774 m_new->m_len = m_new->m_pkthdr.len; 2775 *m_head = m_new; 2776 } 2777 2778 prod = sc->rl_ldata.rl_tx_prodidx; 2779 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2780 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2781 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2782 if (error == EFBIG) { 2783 m_new = m_collapse(*m_head, M_NOWAIT, RL_NTXSEGS); 2784 if (m_new == NULL) { 2785 m_freem(*m_head); 2786 *m_head = NULL; 2787 return (ENOBUFS); 2788 } 2789 *m_head = m_new; 2790 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2791 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2792 if (error != 0) { 2793 m_freem(*m_head); 2794 *m_head = NULL; 2795 return (error); 2796 } 2797 } else if (error != 0) 2798 return (error); 2799 if (nsegs == 0) { 2800 m_freem(*m_head); 2801 *m_head = NULL; 2802 return (EIO); 2803 } 2804 2805 /* Check for number of available descriptors. */ 2806 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2807 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2808 return (ENOBUFS); 2809 } 2810 2811 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2812 BUS_DMASYNC_PREWRITE); 2813 2814 /* 2815 * Set up checksum offload. Note: checksum offload bits must 2816 * appear in all descriptors of a multi-descriptor transmit 2817 * attempt. This is according to testing done with an 8169 2818 * chip. This is a requirement. 2819 */ 2820 vlanctl = 0; 2821 csum_flags = 0; 2822 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2823 if ((sc->rl_flags & RL_FLAG_DESCV2) != 0) { 2824 csum_flags |= RL_TDESC_CMD_LGSEND; 2825 vlanctl |= ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2826 RL_TDESC_CMD_MSSVALV2_SHIFT); 2827 } else { 2828 csum_flags |= RL_TDESC_CMD_LGSEND | 2829 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2830 RL_TDESC_CMD_MSSVAL_SHIFT); 2831 } 2832 } else { 2833 /* 2834 * Unconditionally enable IP checksum if TCP or UDP 2835 * checksum is required. Otherwise, TCP/UDP checksum 2836 * doesn't make effects. 2837 */ 2838 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) { 2839 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2840 csum_flags |= RL_TDESC_CMD_IPCSUM; 2841 if (((*m_head)->m_pkthdr.csum_flags & 2842 CSUM_TCP) != 0) 2843 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2844 if (((*m_head)->m_pkthdr.csum_flags & 2845 CSUM_UDP) != 0) 2846 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2847 } else { 2848 vlanctl |= RL_TDESC_CMD_IPCSUMV2; 2849 if (((*m_head)->m_pkthdr.csum_flags & 2850 CSUM_TCP) != 0) 2851 vlanctl |= RL_TDESC_CMD_TCPCSUMV2; 2852 if (((*m_head)->m_pkthdr.csum_flags & 2853 CSUM_UDP) != 0) 2854 vlanctl |= RL_TDESC_CMD_UDPCSUMV2; 2855 } 2856 } 2857 } 2858 2859 /* 2860 * Set up hardware VLAN tagging. Note: vlan tag info must 2861 * appear in all descriptors of a multi-descriptor 2862 * transmission attempt. 2863 */ 2864 if ((*m_head)->m_flags & M_VLANTAG) 2865 vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) | 2866 RL_TDESC_VLANCTL_TAG; 2867 2868 si = prod; 2869 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2870 desc = &sc->rl_ldata.rl_tx_list[prod]; 2871 desc->rl_vlanctl = htole32(vlanctl); 2872 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2873 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2874 cmdstat = segs[i].ds_len; 2875 if (i != 0) 2876 cmdstat |= RL_TDESC_CMD_OWN; 2877 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2878 cmdstat |= RL_TDESC_CMD_EOR; 2879 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2880 sc->rl_ldata.rl_tx_free--; 2881 } 2882 /* Update producer index. */ 2883 sc->rl_ldata.rl_tx_prodidx = prod; 2884 2885 /* Set EOF on the last descriptor. */ 2886 ei = RL_TX_DESC_PRV(sc, prod); 2887 desc = &sc->rl_ldata.rl_tx_list[ei]; 2888 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2889 2890 desc = &sc->rl_ldata.rl_tx_list[si]; 2891 /* Set SOF and transfer ownership of packet to the chip. */ 2892 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2893 2894 /* 2895 * Insure that the map for this transmission 2896 * is placed at the array index of the last descriptor 2897 * in this chain. (Swap last and first dmamaps.) 2898 */ 2899 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2900 map = txd->tx_dmamap; 2901 txd->tx_dmamap = txd_last->tx_dmamap; 2902 txd_last->tx_dmamap = map; 2903 txd_last->tx_m = *m_head; 2904 2905 return (0); 2906 } 2907 2908 static void 2909 re_start(struct ifnet *ifp) 2910 { 2911 struct rl_softc *sc; 2912 2913 sc = ifp->if_softc; 2914 RL_LOCK(sc); 2915 re_start_locked(ifp); 2916 RL_UNLOCK(sc); 2917 } 2918 2919 /* 2920 * Main transmit routine for C+ and gigE NICs. 2921 */ 2922 static void 2923 re_start_locked(struct ifnet *ifp) 2924 { 2925 struct rl_softc *sc; 2926 struct mbuf *m_head; 2927 int queued; 2928 2929 sc = ifp->if_softc; 2930 2931 #ifdef DEV_NETMAP 2932 /* XXX is this necessary ? */ 2933 if (ifp->if_capenable & IFCAP_NETMAP) { 2934 struct netmap_kring *kring = &NA(ifp)->tx_rings[0]; 2935 if (sc->rl_ldata.rl_tx_prodidx != kring->nr_hwcur) { 2936 /* kick the tx unit */ 2937 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2938 #ifdef RE_TX_MODERATION 2939 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2940 #endif 2941 sc->rl_watchdog_timer = 5; 2942 } 2943 return; 2944 } 2945 #endif /* DEV_NETMAP */ 2946 2947 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2948 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) 2949 return; 2950 2951 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2952 sc->rl_ldata.rl_tx_free > 1;) { 2953 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2954 if (m_head == NULL) 2955 break; 2956 2957 if (re_encap(sc, &m_head) != 0) { 2958 if (m_head == NULL) 2959 break; 2960 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2961 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2962 break; 2963 } 2964 2965 /* 2966 * If there's a BPF listener, bounce a copy of this frame 2967 * to him. 2968 */ 2969 ETHER_BPF_MTAP(ifp, m_head); 2970 2971 queued++; 2972 } 2973 2974 if (queued == 0) { 2975 #ifdef RE_TX_MODERATION 2976 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2977 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2978 #endif 2979 return; 2980 } 2981 2982 /* Flush the TX descriptors */ 2983 2984 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2985 sc->rl_ldata.rl_tx_list_map, 2986 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2987 2988 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2989 2990 #ifdef RE_TX_MODERATION 2991 /* 2992 * Use the countdown timer for interrupt moderation. 2993 * 'TX done' interrupts are disabled. Instead, we reset the 2994 * countdown timer, which will begin counting until it hits 2995 * the value in the TIMERINT register, and then trigger an 2996 * interrupt. Each time we write to the TIMERCNT register, 2997 * the timer count is reset to 0. 2998 */ 2999 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 3000 #endif 3001 3002 /* 3003 * Set a timeout in case the chip goes out to lunch. 3004 */ 3005 sc->rl_watchdog_timer = 5; 3006 } 3007 3008 static void 3009 re_set_jumbo(struct rl_softc *sc, int jumbo) 3010 { 3011 3012 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168E_VL) { 3013 pci_set_max_read_req(sc->rl_dev, 4096); 3014 return; 3015 } 3016 3017 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 3018 if (jumbo != 0) { 3019 CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) | 3020 RL_CFG3_JUMBO_EN0); 3021 switch (sc->rl_hwrev->rl_rev) { 3022 case RL_HWREV_8168DP: 3023 break; 3024 case RL_HWREV_8168E: 3025 CSR_WRITE_1(sc, sc->rl_cfg4, 3026 CSR_READ_1(sc, sc->rl_cfg4) | 0x01); 3027 break; 3028 default: 3029 CSR_WRITE_1(sc, sc->rl_cfg4, 3030 CSR_READ_1(sc, sc->rl_cfg4) | RL_CFG4_JUMBO_EN1); 3031 } 3032 } else { 3033 CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) & 3034 ~RL_CFG3_JUMBO_EN0); 3035 switch (sc->rl_hwrev->rl_rev) { 3036 case RL_HWREV_8168DP: 3037 break; 3038 case RL_HWREV_8168E: 3039 CSR_WRITE_1(sc, sc->rl_cfg4, 3040 CSR_READ_1(sc, sc->rl_cfg4) & ~0x01); 3041 break; 3042 default: 3043 CSR_WRITE_1(sc, sc->rl_cfg4, 3044 CSR_READ_1(sc, sc->rl_cfg4) & ~RL_CFG4_JUMBO_EN1); 3045 } 3046 } 3047 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3048 3049 switch (sc->rl_hwrev->rl_rev) { 3050 case RL_HWREV_8168DP: 3051 pci_set_max_read_req(sc->rl_dev, 4096); 3052 break; 3053 default: 3054 if (jumbo != 0) 3055 pci_set_max_read_req(sc->rl_dev, 512); 3056 else 3057 pci_set_max_read_req(sc->rl_dev, 4096); 3058 } 3059 } 3060 3061 static void 3062 re_init(void *xsc) 3063 { 3064 struct rl_softc *sc = xsc; 3065 3066 RL_LOCK(sc); 3067 re_init_locked(sc); 3068 RL_UNLOCK(sc); 3069 } 3070 3071 static void 3072 re_init_locked(struct rl_softc *sc) 3073 { 3074 struct ifnet *ifp = sc->rl_ifp; 3075 struct mii_data *mii; 3076 uint32_t reg; 3077 uint16_t cfg; 3078 union { 3079 uint32_t align_dummy; 3080 u_char eaddr[ETHER_ADDR_LEN]; 3081 } eaddr; 3082 3083 RL_LOCK_ASSERT(sc); 3084 3085 mii = device_get_softc(sc->rl_miibus); 3086 3087 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3088 return; 3089 3090 /* 3091 * Cancel pending I/O and free all RX/TX buffers. 3092 */ 3093 re_stop(sc); 3094 3095 /* Put controller into known state. */ 3096 re_reset(sc); 3097 3098 /* 3099 * For C+ mode, initialize the RX descriptors and mbufs. 3100 */ 3101 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3102 if (ifp->if_mtu > RL_MTU) { 3103 if (re_jrx_list_init(sc) != 0) { 3104 device_printf(sc->rl_dev, 3105 "no memory for jumbo RX buffers\n"); 3106 re_stop(sc); 3107 return; 3108 } 3109 /* Disable checksum offloading for jumbo frames. */ 3110 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_TSO4); 3111 ifp->if_hwassist &= ~(RE_CSUM_FEATURES | CSUM_TSO); 3112 } else { 3113 if (re_rx_list_init(sc) != 0) { 3114 device_printf(sc->rl_dev, 3115 "no memory for RX buffers\n"); 3116 re_stop(sc); 3117 return; 3118 } 3119 } 3120 re_set_jumbo(sc, ifp->if_mtu > RL_MTU); 3121 } else { 3122 if (re_rx_list_init(sc) != 0) { 3123 device_printf(sc->rl_dev, "no memory for RX buffers\n"); 3124 re_stop(sc); 3125 return; 3126 } 3127 if ((sc->rl_flags & RL_FLAG_PCIE) != 0 && 3128 pci_get_device(sc->rl_dev) != RT_DEVICEID_8101E) { 3129 if (ifp->if_mtu > RL_MTU) 3130 pci_set_max_read_req(sc->rl_dev, 512); 3131 else 3132 pci_set_max_read_req(sc->rl_dev, 4096); 3133 } 3134 } 3135 re_tx_list_init(sc); 3136 3137 /* 3138 * Enable C+ RX and TX mode, as well as VLAN stripping and 3139 * RX checksum offload. We must configure the C+ register 3140 * before all others. 3141 */ 3142 cfg = RL_CPLUSCMD_PCI_MRW; 3143 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 3144 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 3145 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3146 cfg |= RL_CPLUSCMD_VLANSTRIP; 3147 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) { 3148 cfg |= RL_CPLUSCMD_MACSTAT_DIS; 3149 /* XXX magic. */ 3150 cfg |= 0x0001; 3151 } else 3152 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB; 3153 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg); 3154 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SC || 3155 sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) { 3156 reg = 0x000fff00; 3157 if ((CSR_READ_1(sc, sc->rl_cfg2) & RL_CFG2_PCI66MHZ) != 0) 3158 reg |= 0x000000ff; 3159 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) 3160 reg |= 0x00f00000; 3161 CSR_WRITE_4(sc, 0x7c, reg); 3162 /* Disable interrupt mitigation. */ 3163 CSR_WRITE_2(sc, 0xe2, 0); 3164 } 3165 /* 3166 * Disable TSO if interface MTU size is greater than MSS 3167 * allowed in controller. 3168 */ 3169 if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) { 3170 ifp->if_capenable &= ~IFCAP_TSO4; 3171 ifp->if_hwassist &= ~CSUM_TSO; 3172 } 3173 3174 /* 3175 * Init our MAC address. Even though the chipset 3176 * documentation doesn't mention it, we need to enter "Config 3177 * register write enable" mode to modify the ID registers. 3178 */ 3179 /* Copy MAC address on stack to align. */ 3180 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 3181 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 3182 CSR_WRITE_4(sc, RL_IDR0, 3183 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 3184 CSR_WRITE_4(sc, RL_IDR4, 3185 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 3186 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3187 3188 /* 3189 * Load the addresses of the RX and TX lists into the chip. 3190 */ 3191 3192 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 3193 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 3194 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 3195 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 3196 3197 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 3198 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 3199 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 3200 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 3201 3202 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0) { 3203 /* Disable RXDV gate. */ 3204 CSR_WRITE_4(sc, RL_MISC, CSR_READ_4(sc, RL_MISC) & 3205 ~0x00080000); 3206 } 3207 3208 /* 3209 * Enable transmit and receive for pre-RTL8168G controllers. 3210 * RX/TX MACs should be enabled before RX/TX configuration. 3211 */ 3212 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) == 0) 3213 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB | RL_CMD_RX_ENB); 3214 3215 /* 3216 * Set the initial TX configuration. 3217 */ 3218 if (sc->rl_testmode) { 3219 if (sc->rl_type == RL_8169) 3220 CSR_WRITE_4(sc, RL_TXCFG, 3221 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 3222 else 3223 CSR_WRITE_4(sc, RL_TXCFG, 3224 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 3225 } else 3226 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 3227 3228 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 3229 3230 /* 3231 * Set the initial RX configuration. 3232 */ 3233 re_set_rxmode(sc); 3234 3235 /* Configure interrupt moderation. */ 3236 if (sc->rl_type == RL_8169) { 3237 /* Magic from vendor. */ 3238 CSR_WRITE_2(sc, RL_INTRMOD, 0x5100); 3239 } 3240 3241 /* 3242 * Enable transmit and receive for RTL8168G and later controllers. 3243 * RX/TX MACs should be enabled after RX/TX configuration. 3244 */ 3245 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0) 3246 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB | RL_CMD_RX_ENB); 3247 3248 #ifdef DEVICE_POLLING 3249 /* 3250 * Disable interrupts if we are polling. 3251 */ 3252 if (ifp->if_capenable & IFCAP_POLLING) 3253 CSR_WRITE_2(sc, RL_IMR, 0); 3254 else /* otherwise ... */ 3255 #endif 3256 3257 /* 3258 * Enable interrupts. 3259 */ 3260 if (sc->rl_testmode) 3261 CSR_WRITE_2(sc, RL_IMR, 0); 3262 else 3263 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 3264 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 3265 3266 /* Set initial TX threshold */ 3267 sc->rl_txthresh = RL_TX_THRESH_INIT; 3268 3269 /* Start RX/TX process. */ 3270 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 3271 3272 /* 3273 * Initialize the timer interrupt register so that 3274 * a timer interrupt will be generated once the timer 3275 * reaches a certain number of ticks. The timer is 3276 * reloaded on each transmit. 3277 */ 3278 #ifdef RE_TX_MODERATION 3279 /* 3280 * Use timer interrupt register to moderate TX interrupt 3281 * moderation, which dramatically improves TX frame rate. 3282 */ 3283 if (sc->rl_type == RL_8169) 3284 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 3285 else 3286 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 3287 #else 3288 /* 3289 * Use timer interrupt register to moderate RX interrupt 3290 * moderation. 3291 */ 3292 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 && 3293 intr_filter == 0) { 3294 if (sc->rl_type == RL_8169) 3295 CSR_WRITE_4(sc, RL_TIMERINT_8169, 3296 RL_USECS(sc->rl_int_rx_mod)); 3297 } else { 3298 if (sc->rl_type == RL_8169) 3299 CSR_WRITE_4(sc, RL_TIMERINT_8169, RL_USECS(0)); 3300 } 3301 #endif 3302 3303 /* 3304 * For 8169 gigE NICs, set the max allowed RX packet 3305 * size so we can receive jumbo frames. 3306 */ 3307 if (sc->rl_type == RL_8169) { 3308 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3309 /* 3310 * For controllers that use new jumbo frame scheme, 3311 * set maximum size of jumbo frame depending on 3312 * controller revisions. 3313 */ 3314 if (ifp->if_mtu > RL_MTU) 3315 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 3316 sc->rl_hwrev->rl_max_mtu + 3317 ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN + 3318 ETHER_CRC_LEN); 3319 else 3320 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 3321 RE_RX_DESC_BUFLEN); 3322 } else if ((sc->rl_flags & RL_FLAG_PCIE) != 0 && 3323 sc->rl_hwrev->rl_max_mtu == RL_MTU) { 3324 /* RTL810x has no jumbo frame support. */ 3325 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, RE_RX_DESC_BUFLEN); 3326 } else 3327 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 3328 } 3329 3330 if (sc->rl_testmode) 3331 return; 3332 3333 CSR_WRITE_1(sc, sc->rl_cfg1, CSR_READ_1(sc, sc->rl_cfg1) | 3334 RL_CFG1_DRVLOAD); 3335 3336 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3337 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3338 3339 sc->rl_flags &= ~RL_FLAG_LINK; 3340 mii_mediachg(mii); 3341 3342 sc->rl_watchdog_timer = 0; 3343 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 3344 } 3345 3346 /* 3347 * Set media options. 3348 */ 3349 static int 3350 re_ifmedia_upd(struct ifnet *ifp) 3351 { 3352 struct rl_softc *sc; 3353 struct mii_data *mii; 3354 int error; 3355 3356 sc = ifp->if_softc; 3357 mii = device_get_softc(sc->rl_miibus); 3358 RL_LOCK(sc); 3359 error = mii_mediachg(mii); 3360 RL_UNLOCK(sc); 3361 3362 return (error); 3363 } 3364 3365 /* 3366 * Report current media status. 3367 */ 3368 static void 3369 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3370 { 3371 struct rl_softc *sc; 3372 struct mii_data *mii; 3373 3374 sc = ifp->if_softc; 3375 mii = device_get_softc(sc->rl_miibus); 3376 3377 RL_LOCK(sc); 3378 mii_pollstat(mii); 3379 ifmr->ifm_active = mii->mii_media_active; 3380 ifmr->ifm_status = mii->mii_media_status; 3381 RL_UNLOCK(sc); 3382 } 3383 3384 static int 3385 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3386 { 3387 struct rl_softc *sc = ifp->if_softc; 3388 struct ifreq *ifr = (struct ifreq *) data; 3389 struct mii_data *mii; 3390 int error = 0; 3391 3392 switch (command) { 3393 case SIOCSIFMTU: 3394 if (ifr->ifr_mtu < ETHERMIN || 3395 ifr->ifr_mtu > sc->rl_hwrev->rl_max_mtu || 3396 ((sc->rl_flags & RL_FLAG_FASTETHER) != 0 && 3397 ifr->ifr_mtu > RL_MTU)) { 3398 error = EINVAL; 3399 break; 3400 } 3401 RL_LOCK(sc); 3402 if (ifp->if_mtu != ifr->ifr_mtu) { 3403 ifp->if_mtu = ifr->ifr_mtu; 3404 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 3405 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3406 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3407 re_init_locked(sc); 3408 } 3409 if (ifp->if_mtu > RL_TSO_MTU && 3410 (ifp->if_capenable & IFCAP_TSO4) != 0) { 3411 ifp->if_capenable &= ~(IFCAP_TSO4 | 3412 IFCAP_VLAN_HWTSO); 3413 ifp->if_hwassist &= ~CSUM_TSO; 3414 } 3415 VLAN_CAPABILITIES(ifp); 3416 } 3417 RL_UNLOCK(sc); 3418 break; 3419 case SIOCSIFFLAGS: 3420 RL_LOCK(sc); 3421 if ((ifp->if_flags & IFF_UP) != 0) { 3422 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3423 if (((ifp->if_flags ^ sc->rl_if_flags) 3424 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 3425 re_set_rxmode(sc); 3426 } else 3427 re_init_locked(sc); 3428 } else { 3429 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3430 re_stop(sc); 3431 } 3432 sc->rl_if_flags = ifp->if_flags; 3433 RL_UNLOCK(sc); 3434 break; 3435 case SIOCADDMULTI: 3436 case SIOCDELMULTI: 3437 RL_LOCK(sc); 3438 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3439 re_set_rxmode(sc); 3440 RL_UNLOCK(sc); 3441 break; 3442 case SIOCGIFMEDIA: 3443 case SIOCSIFMEDIA: 3444 mii = device_get_softc(sc->rl_miibus); 3445 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3446 break; 3447 case SIOCSIFCAP: 3448 { 3449 int mask, reinit; 3450 3451 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3452 reinit = 0; 3453 #ifdef DEVICE_POLLING 3454 if (mask & IFCAP_POLLING) { 3455 if (ifr->ifr_reqcap & IFCAP_POLLING) { 3456 error = ether_poll_register(re_poll, ifp); 3457 if (error) 3458 return (error); 3459 RL_LOCK(sc); 3460 /* Disable interrupts */ 3461 CSR_WRITE_2(sc, RL_IMR, 0x0000); 3462 ifp->if_capenable |= IFCAP_POLLING; 3463 RL_UNLOCK(sc); 3464 } else { 3465 error = ether_poll_deregister(ifp); 3466 /* Enable interrupts. */ 3467 RL_LOCK(sc); 3468 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 3469 ifp->if_capenable &= ~IFCAP_POLLING; 3470 RL_UNLOCK(sc); 3471 } 3472 } 3473 #endif /* DEVICE_POLLING */ 3474 RL_LOCK(sc); 3475 if ((mask & IFCAP_TXCSUM) != 0 && 3476 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 3477 ifp->if_capenable ^= IFCAP_TXCSUM; 3478 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 3479 ifp->if_hwassist |= RE_CSUM_FEATURES; 3480 else 3481 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 3482 reinit = 1; 3483 } 3484 if ((mask & IFCAP_RXCSUM) != 0 && 3485 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 3486 ifp->if_capenable ^= IFCAP_RXCSUM; 3487 reinit = 1; 3488 } 3489 if ((mask & IFCAP_TSO4) != 0 && 3490 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 3491 ifp->if_capenable ^= IFCAP_TSO4; 3492 if ((IFCAP_TSO4 & ifp->if_capenable) != 0) 3493 ifp->if_hwassist |= CSUM_TSO; 3494 else 3495 ifp->if_hwassist &= ~CSUM_TSO; 3496 if (ifp->if_mtu > RL_TSO_MTU && 3497 (ifp->if_capenable & IFCAP_TSO4) != 0) { 3498 ifp->if_capenable &= ~IFCAP_TSO4; 3499 ifp->if_hwassist &= ~CSUM_TSO; 3500 } 3501 } 3502 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 3503 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 3504 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 3505 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3506 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 3507 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 3508 /* TSO over VLAN requires VLAN hardware tagging. */ 3509 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 3510 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 3511 reinit = 1; 3512 } 3513 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 3514 (mask & (IFCAP_HWCSUM | IFCAP_TSO4 | 3515 IFCAP_VLAN_HWTSO)) != 0) 3516 reinit = 1; 3517 if ((mask & IFCAP_WOL) != 0 && 3518 (ifp->if_capabilities & IFCAP_WOL) != 0) { 3519 if ((mask & IFCAP_WOL_UCAST) != 0) 3520 ifp->if_capenable ^= IFCAP_WOL_UCAST; 3521 if ((mask & IFCAP_WOL_MCAST) != 0) 3522 ifp->if_capenable ^= IFCAP_WOL_MCAST; 3523 if ((mask & IFCAP_WOL_MAGIC) != 0) 3524 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 3525 } 3526 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) { 3527 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3528 re_init_locked(sc); 3529 } 3530 RL_UNLOCK(sc); 3531 VLAN_CAPABILITIES(ifp); 3532 } 3533 break; 3534 default: 3535 error = ether_ioctl(ifp, command, data); 3536 break; 3537 } 3538 3539 return (error); 3540 } 3541 3542 static void 3543 re_watchdog(struct rl_softc *sc) 3544 { 3545 struct ifnet *ifp; 3546 3547 RL_LOCK_ASSERT(sc); 3548 3549 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 3550 return; 3551 3552 ifp = sc->rl_ifp; 3553 re_txeof(sc); 3554 if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) { 3555 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 3556 "-- recovering\n"); 3557 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3558 re_start_locked(ifp); 3559 return; 3560 } 3561 3562 if_printf(ifp, "watchdog timeout\n"); 3563 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3564 3565 re_rxeof(sc, NULL); 3566 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3567 re_init_locked(sc); 3568 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3569 re_start_locked(ifp); 3570 } 3571 3572 /* 3573 * Stop the adapter and free any mbufs allocated to the 3574 * RX and TX lists. 3575 */ 3576 static void 3577 re_stop(struct rl_softc *sc) 3578 { 3579 int i; 3580 struct ifnet *ifp; 3581 struct rl_txdesc *txd; 3582 struct rl_rxdesc *rxd; 3583 3584 RL_LOCK_ASSERT(sc); 3585 3586 ifp = sc->rl_ifp; 3587 3588 sc->rl_watchdog_timer = 0; 3589 callout_stop(&sc->rl_stat_callout); 3590 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3591 3592 /* 3593 * Disable accepting frames to put RX MAC into idle state. 3594 * Otherwise it's possible to get frames while stop command 3595 * execution is in progress and controller can DMA the frame 3596 * to already freed RX buffer during that period. 3597 */ 3598 CSR_WRITE_4(sc, RL_RXCFG, CSR_READ_4(sc, RL_RXCFG) & 3599 ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_MULTI | 3600 RL_RXCFG_RX_BROAD)); 3601 3602 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0) { 3603 /* Enable RXDV gate. */ 3604 CSR_WRITE_4(sc, RL_MISC, CSR_READ_4(sc, RL_MISC) | 3605 0x00080000); 3606 } 3607 3608 if ((sc->rl_flags & RL_FLAG_WAIT_TXPOLL) != 0) { 3609 for (i = RL_TIMEOUT; i > 0; i--) { 3610 if ((CSR_READ_1(sc, sc->rl_txstart) & 3611 RL_TXSTART_START) == 0) 3612 break; 3613 DELAY(20); 3614 } 3615 if (i == 0) 3616 device_printf(sc->rl_dev, 3617 "stopping TX poll timed out!\n"); 3618 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 3619 } else if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0) { 3620 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB | 3621 RL_CMD_RX_ENB); 3622 if ((sc->rl_flags & RL_FLAG_CMDSTOP_WAIT_TXQ) != 0) { 3623 for (i = RL_TIMEOUT; i > 0; i--) { 3624 if ((CSR_READ_4(sc, RL_TXCFG) & 3625 RL_TXCFG_QUEUE_EMPTY) != 0) 3626 break; 3627 DELAY(100); 3628 } 3629 if (i == 0) 3630 device_printf(sc->rl_dev, 3631 "stopping TXQ timed out!\n"); 3632 } 3633 } else 3634 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 3635 DELAY(1000); 3636 CSR_WRITE_2(sc, RL_IMR, 0x0000); 3637 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 3638 3639 if (sc->rl_head != NULL) { 3640 m_freem(sc->rl_head); 3641 sc->rl_head = sc->rl_tail = NULL; 3642 } 3643 3644 /* Free the TX list buffers. */ 3645 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 3646 txd = &sc->rl_ldata.rl_tx_desc[i]; 3647 if (txd->tx_m != NULL) { 3648 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 3649 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3650 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 3651 txd->tx_dmamap); 3652 m_freem(txd->tx_m); 3653 txd->tx_m = NULL; 3654 } 3655 } 3656 3657 /* Free the RX list buffers. */ 3658 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 3659 rxd = &sc->rl_ldata.rl_rx_desc[i]; 3660 if (rxd->rx_m != NULL) { 3661 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 3662 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3663 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 3664 rxd->rx_dmamap); 3665 m_freem(rxd->rx_m); 3666 rxd->rx_m = NULL; 3667 } 3668 } 3669 3670 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3671 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 3672 rxd = &sc->rl_ldata.rl_jrx_desc[i]; 3673 if (rxd->rx_m != NULL) { 3674 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, 3675 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3676 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, 3677 rxd->rx_dmamap); 3678 m_freem(rxd->rx_m); 3679 rxd->rx_m = NULL; 3680 } 3681 } 3682 } 3683 } 3684 3685 /* 3686 * Device suspend routine. Stop the interface and save some PCI 3687 * settings in case the BIOS doesn't restore them properly on 3688 * resume. 3689 */ 3690 static int 3691 re_suspend(device_t dev) 3692 { 3693 struct rl_softc *sc; 3694 3695 sc = device_get_softc(dev); 3696 3697 RL_LOCK(sc); 3698 re_stop(sc); 3699 re_setwol(sc); 3700 sc->suspended = 1; 3701 RL_UNLOCK(sc); 3702 3703 return (0); 3704 } 3705 3706 /* 3707 * Device resume routine. Restore some PCI settings in case the BIOS 3708 * doesn't, re-enable busmastering, and restart the interface if 3709 * appropriate. 3710 */ 3711 static int 3712 re_resume(device_t dev) 3713 { 3714 struct rl_softc *sc; 3715 struct ifnet *ifp; 3716 3717 sc = device_get_softc(dev); 3718 3719 RL_LOCK(sc); 3720 3721 ifp = sc->rl_ifp; 3722 /* Take controller out of sleep mode. */ 3723 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3724 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3725 CSR_WRITE_1(sc, RL_GPIO, 3726 CSR_READ_1(sc, RL_GPIO) | 0x01); 3727 } 3728 3729 /* 3730 * Clear WOL matching such that normal Rx filtering 3731 * wouldn't interfere with WOL patterns. 3732 */ 3733 re_clrwol(sc); 3734 3735 /* reinitialize interface if necessary */ 3736 if (ifp->if_flags & IFF_UP) 3737 re_init_locked(sc); 3738 3739 sc->suspended = 0; 3740 RL_UNLOCK(sc); 3741 3742 return (0); 3743 } 3744 3745 /* 3746 * Stop all chip I/O so that the kernel's probe routines don't 3747 * get confused by errant DMAs when rebooting. 3748 */ 3749 static int 3750 re_shutdown(device_t dev) 3751 { 3752 struct rl_softc *sc; 3753 3754 sc = device_get_softc(dev); 3755 3756 RL_LOCK(sc); 3757 re_stop(sc); 3758 /* 3759 * Mark interface as down since otherwise we will panic if 3760 * interrupt comes in later on, which can happen in some 3761 * cases. 3762 */ 3763 sc->rl_ifp->if_flags &= ~IFF_UP; 3764 re_setwol(sc); 3765 RL_UNLOCK(sc); 3766 3767 return (0); 3768 } 3769 3770 static void 3771 re_set_linkspeed(struct rl_softc *sc) 3772 { 3773 struct mii_softc *miisc; 3774 struct mii_data *mii; 3775 int aneg, i, phyno; 3776 3777 RL_LOCK_ASSERT(sc); 3778 3779 mii = device_get_softc(sc->rl_miibus); 3780 mii_pollstat(mii); 3781 aneg = 0; 3782 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 3783 (IFM_ACTIVE | IFM_AVALID)) { 3784 switch IFM_SUBTYPE(mii->mii_media_active) { 3785 case IFM_10_T: 3786 case IFM_100_TX: 3787 return; 3788 case IFM_1000_T: 3789 aneg++; 3790 break; 3791 default: 3792 break; 3793 } 3794 } 3795 miisc = LIST_FIRST(&mii->mii_phys); 3796 phyno = miisc->mii_phy; 3797 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 3798 PHY_RESET(miisc); 3799 re_miibus_writereg(sc->rl_dev, phyno, MII_100T2CR, 0); 3800 re_miibus_writereg(sc->rl_dev, phyno, 3801 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 3802 re_miibus_writereg(sc->rl_dev, phyno, 3803 MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 3804 DELAY(1000); 3805 if (aneg != 0) { 3806 /* 3807 * Poll link state until re(4) get a 10/100Mbps link. 3808 */ 3809 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 3810 mii_pollstat(mii); 3811 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 3812 == (IFM_ACTIVE | IFM_AVALID)) { 3813 switch (IFM_SUBTYPE(mii->mii_media_active)) { 3814 case IFM_10_T: 3815 case IFM_100_TX: 3816 return; 3817 default: 3818 break; 3819 } 3820 } 3821 RL_UNLOCK(sc); 3822 pause("relnk", hz); 3823 RL_LOCK(sc); 3824 } 3825 if (i == MII_ANEGTICKS_GIGE) 3826 device_printf(sc->rl_dev, 3827 "establishing a link failed, WOL may not work!"); 3828 } 3829 /* 3830 * No link, force MAC to have 100Mbps, full-duplex link. 3831 * MAC does not require reprogramming on resolved speed/duplex, 3832 * so this is just for completeness. 3833 */ 3834 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 3835 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 3836 } 3837 3838 static void 3839 re_setwol(struct rl_softc *sc) 3840 { 3841 struct ifnet *ifp; 3842 int pmc; 3843 uint16_t pmstat; 3844 uint8_t v; 3845 3846 RL_LOCK_ASSERT(sc); 3847 3848 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3849 return; 3850 3851 ifp = sc->rl_ifp; 3852 /* Put controller into sleep mode. */ 3853 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3854 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3855 CSR_WRITE_1(sc, RL_GPIO, 3856 CSR_READ_1(sc, RL_GPIO) & ~0x01); 3857 } 3858 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 3859 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0) { 3860 /* Disable RXDV gate. */ 3861 CSR_WRITE_4(sc, RL_MISC, CSR_READ_4(sc, RL_MISC) & 3862 ~0x00080000); 3863 } 3864 re_set_rxmode(sc); 3865 if ((sc->rl_flags & RL_FLAG_WOL_MANLINK) != 0) 3866 re_set_linkspeed(sc); 3867 if ((sc->rl_flags & RL_FLAG_WOLRXENB) != 0) 3868 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB); 3869 } 3870 /* Enable config register write. */ 3871 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3872 3873 /* Enable PME. */ 3874 v = CSR_READ_1(sc, sc->rl_cfg1); 3875 v &= ~RL_CFG1_PME; 3876 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3877 v |= RL_CFG1_PME; 3878 CSR_WRITE_1(sc, sc->rl_cfg1, v); 3879 3880 v = CSR_READ_1(sc, sc->rl_cfg3); 3881 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3882 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3883 v |= RL_CFG3_WOL_MAGIC; 3884 CSR_WRITE_1(sc, sc->rl_cfg3, v); 3885 3886 v = CSR_READ_1(sc, sc->rl_cfg5); 3887 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST | 3888 RL_CFG5_WOL_LANWAKE); 3889 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 3890 v |= RL_CFG5_WOL_UCAST; 3891 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 3892 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 3893 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3894 v |= RL_CFG5_WOL_LANWAKE; 3895 CSR_WRITE_1(sc, sc->rl_cfg5, v); 3896 3897 /* Config register write done. */ 3898 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3899 3900 if ((ifp->if_capenable & IFCAP_WOL) == 0 && 3901 (sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) 3902 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) & ~0x80); 3903 /* 3904 * It seems that hardware resets its link speed to 100Mbps in 3905 * power down mode so switching to 100Mbps in driver is not 3906 * needed. 3907 */ 3908 3909 /* Request PME if WOL is requested. */ 3910 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 3911 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3912 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3913 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3914 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 3915 } 3916 3917 static void 3918 re_clrwol(struct rl_softc *sc) 3919 { 3920 int pmc; 3921 uint8_t v; 3922 3923 RL_LOCK_ASSERT(sc); 3924 3925 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3926 return; 3927 3928 /* Enable config register write. */ 3929 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3930 3931 v = CSR_READ_1(sc, sc->rl_cfg3); 3932 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3933 CSR_WRITE_1(sc, sc->rl_cfg3, v); 3934 3935 /* Config register write done. */ 3936 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3937 3938 v = CSR_READ_1(sc, sc->rl_cfg5); 3939 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3940 v &= ~RL_CFG5_WOL_LANWAKE; 3941 CSR_WRITE_1(sc, sc->rl_cfg5, v); 3942 } 3943 3944 static void 3945 re_add_sysctls(struct rl_softc *sc) 3946 { 3947 struct sysctl_ctx_list *ctx; 3948 struct sysctl_oid_list *children; 3949 int error; 3950 3951 ctx = device_get_sysctl_ctx(sc->rl_dev); 3952 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev)); 3953 3954 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "stats", 3955 CTLTYPE_INT | CTLFLAG_RW, sc, 0, re_sysctl_stats, "I", 3956 "Statistics Information"); 3957 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) 3958 return; 3959 3960 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "int_rx_mod", 3961 CTLTYPE_INT | CTLFLAG_RW, &sc->rl_int_rx_mod, 0, 3962 sysctl_hw_re_int_mod, "I", "re RX interrupt moderation"); 3963 /* Pull in device tunables. */ 3964 sc->rl_int_rx_mod = RL_TIMER_DEFAULT; 3965 error = resource_int_value(device_get_name(sc->rl_dev), 3966 device_get_unit(sc->rl_dev), "int_rx_mod", &sc->rl_int_rx_mod); 3967 if (error == 0) { 3968 if (sc->rl_int_rx_mod < RL_TIMER_MIN || 3969 sc->rl_int_rx_mod > RL_TIMER_MAX) { 3970 device_printf(sc->rl_dev, "int_rx_mod value out of " 3971 "range; using default: %d\n", 3972 RL_TIMER_DEFAULT); 3973 sc->rl_int_rx_mod = RL_TIMER_DEFAULT; 3974 } 3975 } 3976 } 3977 3978 static int 3979 re_sysctl_stats(SYSCTL_HANDLER_ARGS) 3980 { 3981 struct rl_softc *sc; 3982 struct rl_stats *stats; 3983 int error, i, result; 3984 3985 result = -1; 3986 error = sysctl_handle_int(oidp, &result, 0, req); 3987 if (error || req->newptr == NULL) 3988 return (error); 3989 3990 if (result == 1) { 3991 sc = (struct rl_softc *)arg1; 3992 RL_LOCK(sc); 3993 if ((sc->rl_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 3994 RL_UNLOCK(sc); 3995 goto done; 3996 } 3997 bus_dmamap_sync(sc->rl_ldata.rl_stag, 3998 sc->rl_ldata.rl_smap, BUS_DMASYNC_PREREAD); 3999 CSR_WRITE_4(sc, RL_DUMPSTATS_HI, 4000 RL_ADDR_HI(sc->rl_ldata.rl_stats_addr)); 4001 CSR_WRITE_4(sc, RL_DUMPSTATS_LO, 4002 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr)); 4003 CSR_WRITE_4(sc, RL_DUMPSTATS_LO, 4004 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr | 4005 RL_DUMPSTATS_START)); 4006 for (i = RL_TIMEOUT; i > 0; i--) { 4007 if ((CSR_READ_4(sc, RL_DUMPSTATS_LO) & 4008 RL_DUMPSTATS_START) == 0) 4009 break; 4010 DELAY(1000); 4011 } 4012 bus_dmamap_sync(sc->rl_ldata.rl_stag, 4013 sc->rl_ldata.rl_smap, BUS_DMASYNC_POSTREAD); 4014 RL_UNLOCK(sc); 4015 if (i == 0) { 4016 device_printf(sc->rl_dev, 4017 "DUMP statistics request timed out\n"); 4018 return (ETIMEDOUT); 4019 } 4020 done: 4021 stats = sc->rl_ldata.rl_stats; 4022 printf("%s statistics:\n", device_get_nameunit(sc->rl_dev)); 4023 printf("Tx frames : %ju\n", 4024 (uintmax_t)le64toh(stats->rl_tx_pkts)); 4025 printf("Rx frames : %ju\n", 4026 (uintmax_t)le64toh(stats->rl_rx_pkts)); 4027 printf("Tx errors : %ju\n", 4028 (uintmax_t)le64toh(stats->rl_tx_errs)); 4029 printf("Rx errors : %u\n", 4030 le32toh(stats->rl_rx_errs)); 4031 printf("Rx missed frames : %u\n", 4032 (uint32_t)le16toh(stats->rl_missed_pkts)); 4033 printf("Rx frame alignment errs : %u\n", 4034 (uint32_t)le16toh(stats->rl_rx_framealign_errs)); 4035 printf("Tx single collisions : %u\n", 4036 le32toh(stats->rl_tx_onecoll)); 4037 printf("Tx multiple collisions : %u\n", 4038 le32toh(stats->rl_tx_multicolls)); 4039 printf("Rx unicast frames : %ju\n", 4040 (uintmax_t)le64toh(stats->rl_rx_ucasts)); 4041 printf("Rx broadcast frames : %ju\n", 4042 (uintmax_t)le64toh(stats->rl_rx_bcasts)); 4043 printf("Rx multicast frames : %u\n", 4044 le32toh(stats->rl_rx_mcasts)); 4045 printf("Tx aborts : %u\n", 4046 (uint32_t)le16toh(stats->rl_tx_aborts)); 4047 printf("Tx underruns : %u\n", 4048 (uint32_t)le16toh(stats->rl_rx_underruns)); 4049 } 4050 4051 return (error); 4052 } 4053 4054 static int 4055 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4056 { 4057 int error, value; 4058 4059 if (arg1 == NULL) 4060 return (EINVAL); 4061 value = *(int *)arg1; 4062 error = sysctl_handle_int(oidp, &value, 0, req); 4063 if (error || req->newptr == NULL) 4064 return (error); 4065 if (value < low || value > high) 4066 return (EINVAL); 4067 *(int *)arg1 = value; 4068 4069 return (0); 4070 } 4071 4072 static int 4073 sysctl_hw_re_int_mod(SYSCTL_HANDLER_ARGS) 4074 { 4075 4076 return (sysctl_int_range(oidp, arg1, arg2, req, RL_TIMER_MIN, 4077 RL_TIMER_MAX)); 4078 } 4079