1 /*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44 /* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111 #ifdef HAVE_KERNEL_OPTION_HEADERS 112 #include "opt_device_polling.h" 113 #endif 114 115 #include <sys/param.h> 116 #include <sys/endian.h> 117 #include <sys/systm.h> 118 #include <sys/sockio.h> 119 #include <sys/mbuf.h> 120 #include <sys/malloc.h> 121 #include <sys/module.h> 122 #include <sys/kernel.h> 123 #include <sys/socket.h> 124 #include <sys/lock.h> 125 #include <sys/mutex.h> 126 #include <sys/sysctl.h> 127 #include <sys/taskqueue.h> 128 129 #include <net/if.h> 130 #include <net/if_arp.h> 131 #include <net/ethernet.h> 132 #include <net/if_dl.h> 133 #include <net/if_media.h> 134 #include <net/if_types.h> 135 #include <net/if_vlan_var.h> 136 137 #include <net/bpf.h> 138 139 #include <machine/bus.h> 140 #include <machine/resource.h> 141 #include <sys/bus.h> 142 #include <sys/rman.h> 143 144 #include <dev/mii/mii.h> 145 #include <dev/mii/miivar.h> 146 147 #include <dev/pci/pcireg.h> 148 #include <dev/pci/pcivar.h> 149 150 #include <pci/if_rlreg.h> 151 152 MODULE_DEPEND(re, pci, 1, 1, 1); 153 MODULE_DEPEND(re, ether, 1, 1, 1); 154 MODULE_DEPEND(re, miibus, 1, 1, 1); 155 156 /* "device miibus" required. See GENERIC if you get errors here. */ 157 #include "miibus_if.h" 158 159 /* Tunables. */ 160 static int intr_filter = 0; 161 TUNABLE_INT("hw.re.intr_filter", &intr_filter); 162 static int msi_disable = 0; 163 TUNABLE_INT("hw.re.msi_disable", &msi_disable); 164 static int msix_disable = 0; 165 TUNABLE_INT("hw.re.msix_disable", &msix_disable); 166 static int prefer_iomap = 0; 167 TUNABLE_INT("hw.re.prefer_iomap", &prefer_iomap); 168 169 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 170 171 /* 172 * Various supported device vendors/types and their names. 173 */ 174 static const struct rl_type const re_devs[] = { 175 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0, 176 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 177 { DLINK_VENDORID, DLINK_DEVICEID_530T_REVC, 0, 178 "D-Link DGE-530(T) Gigabit Ethernet Adapter" }, 179 { RT_VENDORID, RT_DEVICEID_8139, 0, 180 "RealTek 8139C+ 10/100BaseTX" }, 181 { RT_VENDORID, RT_DEVICEID_8101E, 0, 182 "RealTek 810xE PCIe 10/100baseTX" }, 183 { RT_VENDORID, RT_DEVICEID_8168, 0, 184 "RealTek 8168/8111 B/C/CP/D/DP/E/F PCIe Gigabit Ethernet" }, 185 { RT_VENDORID, RT_DEVICEID_8169, 0, 186 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" }, 187 { RT_VENDORID, RT_DEVICEID_8169SC, 0, 188 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 189 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0, 190 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 191 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0, 192 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 193 { USR_VENDORID, USR_DEVICEID_997902, 0, 194 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 195 }; 196 197 static const struct rl_hwrev const re_hwrevs[] = { 198 { RL_HWREV_8139, RL_8139, "", RL_MTU }, 199 { RL_HWREV_8139A, RL_8139, "A", RL_MTU }, 200 { RL_HWREV_8139AG, RL_8139, "A-G", RL_MTU }, 201 { RL_HWREV_8139B, RL_8139, "B", RL_MTU }, 202 { RL_HWREV_8130, RL_8139, "8130", RL_MTU }, 203 { RL_HWREV_8139C, RL_8139, "C", RL_MTU }, 204 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C", RL_MTU }, 205 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+", RL_MTU }, 206 { RL_HWREV_8168B_SPIN1, RL_8169, "8168", RL_JUMBO_MTU }, 207 { RL_HWREV_8169, RL_8169, "8169", RL_JUMBO_MTU }, 208 { RL_HWREV_8169S, RL_8169, "8169S", RL_JUMBO_MTU }, 209 { RL_HWREV_8110S, RL_8169, "8110S", RL_JUMBO_MTU }, 210 { RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB", RL_JUMBO_MTU }, 211 { RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU }, 212 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL", RL_JUMBO_MTU }, 213 { RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU }, 214 { RL_HWREV_8100, RL_8139, "8100", RL_MTU }, 215 { RL_HWREV_8101, RL_8139, "8101", RL_MTU }, 216 { RL_HWREV_8100E, RL_8169, "8100E", RL_MTU }, 217 { RL_HWREV_8101E, RL_8169, "8101E", RL_MTU }, 218 { RL_HWREV_8102E, RL_8169, "8102E", RL_MTU }, 219 { RL_HWREV_8102EL, RL_8169, "8102EL", RL_MTU }, 220 { RL_HWREV_8102EL_SPIN1, RL_8169, "8102EL", RL_MTU }, 221 { RL_HWREV_8103E, RL_8169, "8103E", RL_MTU }, 222 { RL_HWREV_8401E, RL_8169, "8401E", RL_MTU }, 223 { RL_HWREV_8402, RL_8169, "8402", RL_MTU }, 224 { RL_HWREV_8105E, RL_8169, "8105E", RL_MTU }, 225 { RL_HWREV_8105E_SPIN1, RL_8169, "8105E", RL_MTU }, 226 { RL_HWREV_8168B_SPIN2, RL_8169, "8168", RL_JUMBO_MTU }, 227 { RL_HWREV_8168B_SPIN3, RL_8169, "8168", RL_JUMBO_MTU }, 228 { RL_HWREV_8168C, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K }, 229 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K }, 230 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP", RL_JUMBO_MTU_6K }, 231 { RL_HWREV_8168D, RL_8169, "8168D/8111D", RL_JUMBO_MTU_9K }, 232 { RL_HWREV_8168DP, RL_8169, "8168DP/8111DP", RL_JUMBO_MTU_9K }, 233 { RL_HWREV_8168E, RL_8169, "8168E/8111E", RL_JUMBO_MTU_9K}, 234 { RL_HWREV_8168E_VL, RL_8169, "8168E/8111E-VL", RL_JUMBO_MTU_6K}, 235 { RL_HWREV_8168F, RL_8169, "8168F/8111F", RL_JUMBO_MTU_9K}, 236 { RL_HWREV_8411, RL_8169, "8411", RL_JUMBO_MTU_9K}, 237 { 0, 0, NULL, 0 } 238 }; 239 240 static int re_probe (device_t); 241 static int re_attach (device_t); 242 static int re_detach (device_t); 243 244 static int re_encap (struct rl_softc *, struct mbuf **); 245 246 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 247 static int re_allocmem (device_t, struct rl_softc *); 248 static __inline void re_discard_rxbuf 249 (struct rl_softc *, int); 250 static int re_newbuf (struct rl_softc *, int); 251 static int re_jumbo_newbuf (struct rl_softc *, int); 252 static int re_rx_list_init (struct rl_softc *); 253 static int re_jrx_list_init (struct rl_softc *); 254 static int re_tx_list_init (struct rl_softc *); 255 #ifdef RE_FIXUP_RX 256 static __inline void re_fixup_rx 257 (struct mbuf *); 258 #endif 259 static int re_rxeof (struct rl_softc *, int *); 260 static void re_txeof (struct rl_softc *); 261 #ifdef DEVICE_POLLING 262 static int re_poll (struct ifnet *, enum poll_cmd, int); 263 static int re_poll_locked (struct ifnet *, enum poll_cmd, int); 264 #endif 265 static int re_intr (void *); 266 static void re_intr_msi (void *); 267 static void re_tick (void *); 268 static void re_int_task (void *, int); 269 static void re_start (struct ifnet *); 270 static void re_start_locked (struct ifnet *); 271 static int re_ioctl (struct ifnet *, u_long, caddr_t); 272 static void re_init (void *); 273 static void re_init_locked (struct rl_softc *); 274 static void re_stop (struct rl_softc *); 275 static void re_watchdog (struct rl_softc *); 276 static int re_suspend (device_t); 277 static int re_resume (device_t); 278 static int re_shutdown (device_t); 279 static int re_ifmedia_upd (struct ifnet *); 280 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 281 282 static void re_eeprom_putbyte (struct rl_softc *, int); 283 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 284 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 285 static int re_gmii_readreg (device_t, int, int); 286 static int re_gmii_writereg (device_t, int, int, int); 287 288 static int re_miibus_readreg (device_t, int, int); 289 static int re_miibus_writereg (device_t, int, int, int); 290 static void re_miibus_statchg (device_t); 291 292 static void re_set_jumbo (struct rl_softc *, int); 293 static void re_set_rxmode (struct rl_softc *); 294 static void re_reset (struct rl_softc *); 295 static void re_setwol (struct rl_softc *); 296 static void re_clrwol (struct rl_softc *); 297 static void re_set_linkspeed (struct rl_softc *); 298 299 #ifdef DEV_NETMAP /* see ixgbe.c for details */ 300 #include <dev/netmap/if_re_netmap.h> 301 #endif /* !DEV_NETMAP */ 302 303 #ifdef RE_DIAG 304 static int re_diag (struct rl_softc *); 305 #endif 306 307 static void re_add_sysctls (struct rl_softc *); 308 static int re_sysctl_stats (SYSCTL_HANDLER_ARGS); 309 static int sysctl_int_range (SYSCTL_HANDLER_ARGS, int, int); 310 static int sysctl_hw_re_int_mod (SYSCTL_HANDLER_ARGS); 311 312 static device_method_t re_methods[] = { 313 /* Device interface */ 314 DEVMETHOD(device_probe, re_probe), 315 DEVMETHOD(device_attach, re_attach), 316 DEVMETHOD(device_detach, re_detach), 317 DEVMETHOD(device_suspend, re_suspend), 318 DEVMETHOD(device_resume, re_resume), 319 DEVMETHOD(device_shutdown, re_shutdown), 320 321 /* MII interface */ 322 DEVMETHOD(miibus_readreg, re_miibus_readreg), 323 DEVMETHOD(miibus_writereg, re_miibus_writereg), 324 DEVMETHOD(miibus_statchg, re_miibus_statchg), 325 326 DEVMETHOD_END 327 }; 328 329 static driver_t re_driver = { 330 "re", 331 re_methods, 332 sizeof(struct rl_softc) 333 }; 334 335 static devclass_t re_devclass; 336 337 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 338 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 339 340 #define EE_SET(x) \ 341 CSR_WRITE_1(sc, RL_EECMD, \ 342 CSR_READ_1(sc, RL_EECMD) | x) 343 344 #define EE_CLR(x) \ 345 CSR_WRITE_1(sc, RL_EECMD, \ 346 CSR_READ_1(sc, RL_EECMD) & ~x) 347 348 /* 349 * Send a read command and address to the EEPROM, check for ACK. 350 */ 351 static void 352 re_eeprom_putbyte(struct rl_softc *sc, int addr) 353 { 354 int d, i; 355 356 d = addr | (RL_9346_READ << sc->rl_eewidth); 357 358 /* 359 * Feed in each bit and strobe the clock. 360 */ 361 362 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 363 if (d & i) { 364 EE_SET(RL_EE_DATAIN); 365 } else { 366 EE_CLR(RL_EE_DATAIN); 367 } 368 DELAY(100); 369 EE_SET(RL_EE_CLK); 370 DELAY(150); 371 EE_CLR(RL_EE_CLK); 372 DELAY(100); 373 } 374 } 375 376 /* 377 * Read a word of data stored in the EEPROM at address 'addr.' 378 */ 379 static void 380 re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest) 381 { 382 int i; 383 u_int16_t word = 0; 384 385 /* 386 * Send address of word we want to read. 387 */ 388 re_eeprom_putbyte(sc, addr); 389 390 /* 391 * Start reading bits from EEPROM. 392 */ 393 for (i = 0x8000; i; i >>= 1) { 394 EE_SET(RL_EE_CLK); 395 DELAY(100); 396 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 397 word |= i; 398 EE_CLR(RL_EE_CLK); 399 DELAY(100); 400 } 401 402 *dest = word; 403 } 404 405 /* 406 * Read a sequence of words from the EEPROM. 407 */ 408 static void 409 re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt) 410 { 411 int i; 412 u_int16_t word = 0, *ptr; 413 414 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 415 416 DELAY(100); 417 418 for (i = 0; i < cnt; i++) { 419 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 420 re_eeprom_getword(sc, off + i, &word); 421 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 422 ptr = (u_int16_t *)(dest + (i * 2)); 423 *ptr = word; 424 } 425 426 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 427 } 428 429 static int 430 re_gmii_readreg(device_t dev, int phy, int reg) 431 { 432 struct rl_softc *sc; 433 u_int32_t rval; 434 int i; 435 436 sc = device_get_softc(dev); 437 438 /* Let the rgephy driver read the GMEDIASTAT register */ 439 440 if (reg == RL_GMEDIASTAT) { 441 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 442 return (rval); 443 } 444 445 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 446 447 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 448 rval = CSR_READ_4(sc, RL_PHYAR); 449 if (rval & RL_PHYAR_BUSY) 450 break; 451 DELAY(25); 452 } 453 454 if (i == RL_PHY_TIMEOUT) { 455 device_printf(sc->rl_dev, "PHY read failed\n"); 456 return (0); 457 } 458 459 /* 460 * Controller requires a 20us delay to process next MDIO request. 461 */ 462 DELAY(20); 463 464 return (rval & RL_PHYAR_PHYDATA); 465 } 466 467 static int 468 re_gmii_writereg(device_t dev, int phy, int reg, int data) 469 { 470 struct rl_softc *sc; 471 u_int32_t rval; 472 int i; 473 474 sc = device_get_softc(dev); 475 476 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 477 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 478 479 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 480 rval = CSR_READ_4(sc, RL_PHYAR); 481 if (!(rval & RL_PHYAR_BUSY)) 482 break; 483 DELAY(25); 484 } 485 486 if (i == RL_PHY_TIMEOUT) { 487 device_printf(sc->rl_dev, "PHY write failed\n"); 488 return (0); 489 } 490 491 /* 492 * Controller requires a 20us delay to process next MDIO request. 493 */ 494 DELAY(20); 495 496 return (0); 497 } 498 499 static int 500 re_miibus_readreg(device_t dev, int phy, int reg) 501 { 502 struct rl_softc *sc; 503 u_int16_t rval = 0; 504 u_int16_t re8139_reg = 0; 505 506 sc = device_get_softc(dev); 507 508 if (sc->rl_type == RL_8169) { 509 rval = re_gmii_readreg(dev, phy, reg); 510 return (rval); 511 } 512 513 switch (reg) { 514 case MII_BMCR: 515 re8139_reg = RL_BMCR; 516 break; 517 case MII_BMSR: 518 re8139_reg = RL_BMSR; 519 break; 520 case MII_ANAR: 521 re8139_reg = RL_ANAR; 522 break; 523 case MII_ANER: 524 re8139_reg = RL_ANER; 525 break; 526 case MII_ANLPAR: 527 re8139_reg = RL_LPAR; 528 break; 529 case MII_PHYIDR1: 530 case MII_PHYIDR2: 531 return (0); 532 /* 533 * Allow the rlphy driver to read the media status 534 * register. If we have a link partner which does not 535 * support NWAY, this is the register which will tell 536 * us the results of parallel detection. 537 */ 538 case RL_MEDIASTAT: 539 rval = CSR_READ_1(sc, RL_MEDIASTAT); 540 return (rval); 541 default: 542 device_printf(sc->rl_dev, "bad phy register\n"); 543 return (0); 544 } 545 rval = CSR_READ_2(sc, re8139_reg); 546 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 547 /* 8139C+ has different bit layout. */ 548 rval &= ~(BMCR_LOOP | BMCR_ISO); 549 } 550 return (rval); 551 } 552 553 static int 554 re_miibus_writereg(device_t dev, int phy, int reg, int data) 555 { 556 struct rl_softc *sc; 557 u_int16_t re8139_reg = 0; 558 int rval = 0; 559 560 sc = device_get_softc(dev); 561 562 if (sc->rl_type == RL_8169) { 563 rval = re_gmii_writereg(dev, phy, reg, data); 564 return (rval); 565 } 566 567 switch (reg) { 568 case MII_BMCR: 569 re8139_reg = RL_BMCR; 570 if (sc->rl_type == RL_8139CPLUS) { 571 /* 8139C+ has different bit layout. */ 572 data &= ~(BMCR_LOOP | BMCR_ISO); 573 } 574 break; 575 case MII_BMSR: 576 re8139_reg = RL_BMSR; 577 break; 578 case MII_ANAR: 579 re8139_reg = RL_ANAR; 580 break; 581 case MII_ANER: 582 re8139_reg = RL_ANER; 583 break; 584 case MII_ANLPAR: 585 re8139_reg = RL_LPAR; 586 break; 587 case MII_PHYIDR1: 588 case MII_PHYIDR2: 589 return (0); 590 break; 591 default: 592 device_printf(sc->rl_dev, "bad phy register\n"); 593 return (0); 594 } 595 CSR_WRITE_2(sc, re8139_reg, data); 596 return (0); 597 } 598 599 static void 600 re_miibus_statchg(device_t dev) 601 { 602 struct rl_softc *sc; 603 struct ifnet *ifp; 604 struct mii_data *mii; 605 606 sc = device_get_softc(dev); 607 mii = device_get_softc(sc->rl_miibus); 608 ifp = sc->rl_ifp; 609 if (mii == NULL || ifp == NULL || 610 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 611 return; 612 613 sc->rl_flags &= ~RL_FLAG_LINK; 614 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 615 (IFM_ACTIVE | IFM_AVALID)) { 616 switch (IFM_SUBTYPE(mii->mii_media_active)) { 617 case IFM_10_T: 618 case IFM_100_TX: 619 sc->rl_flags |= RL_FLAG_LINK; 620 break; 621 case IFM_1000_T: 622 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0) 623 break; 624 sc->rl_flags |= RL_FLAG_LINK; 625 break; 626 default: 627 break; 628 } 629 } 630 /* 631 * RealTek controllers does not provide any interface to 632 * Tx/Rx MACs for resolved speed, duplex and flow-control 633 * parameters. 634 */ 635 } 636 637 /* 638 * Set the RX configuration and 64-bit multicast hash filter. 639 */ 640 static void 641 re_set_rxmode(struct rl_softc *sc) 642 { 643 struct ifnet *ifp; 644 struct ifmultiaddr *ifma; 645 uint32_t hashes[2] = { 0, 0 }; 646 uint32_t h, rxfilt; 647 648 RL_LOCK_ASSERT(sc); 649 650 ifp = sc->rl_ifp; 651 652 rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD; 653 654 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 655 if (ifp->if_flags & IFF_PROMISC) 656 rxfilt |= RL_RXCFG_RX_ALLPHYS; 657 /* 658 * Unlike other hardwares, we have to explicitly set 659 * RL_RXCFG_RX_MULTI to receive multicast frames in 660 * promiscuous mode. 661 */ 662 rxfilt |= RL_RXCFG_RX_MULTI; 663 hashes[0] = hashes[1] = 0xffffffff; 664 goto done; 665 } 666 667 if_maddr_rlock(ifp); 668 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 669 if (ifma->ifma_addr->sa_family != AF_LINK) 670 continue; 671 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 672 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 673 if (h < 32) 674 hashes[0] |= (1 << h); 675 else 676 hashes[1] |= (1 << (h - 32)); 677 } 678 if_maddr_runlock(ifp); 679 680 if (hashes[0] != 0 || hashes[1] != 0) { 681 /* 682 * For some unfathomable reason, RealTek decided to 683 * reverse the order of the multicast hash registers 684 * in the PCI Express parts. This means we have to 685 * write the hash pattern in reverse order for those 686 * devices. 687 */ 688 if ((sc->rl_flags & RL_FLAG_PCIE) != 0) { 689 h = bswap32(hashes[0]); 690 hashes[0] = bswap32(hashes[1]); 691 hashes[1] = h; 692 } 693 rxfilt |= RL_RXCFG_RX_MULTI; 694 } 695 696 done: 697 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 698 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 699 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 700 } 701 702 static void 703 re_reset(struct rl_softc *sc) 704 { 705 int i; 706 707 RL_LOCK_ASSERT(sc); 708 709 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 710 711 for (i = 0; i < RL_TIMEOUT; i++) { 712 DELAY(10); 713 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 714 break; 715 } 716 if (i == RL_TIMEOUT) 717 device_printf(sc->rl_dev, "reset never completed!\n"); 718 719 if ((sc->rl_flags & RL_FLAG_MACRESET) != 0) 720 CSR_WRITE_1(sc, 0x82, 1); 721 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169S) 722 re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0); 723 } 724 725 #ifdef RE_DIAG 726 727 /* 728 * The following routine is designed to test for a defect on some 729 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 730 * lines connected to the bus, however for a 32-bit only card, they 731 * should be pulled high. The result of this defect is that the 732 * NIC will not work right if you plug it into a 64-bit slot: DMA 733 * operations will be done with 64-bit transfers, which will fail 734 * because the 64-bit data lines aren't connected. 735 * 736 * There's no way to work around this (short of talking a soldering 737 * iron to the board), however we can detect it. The method we use 738 * here is to put the NIC into digital loopback mode, set the receiver 739 * to promiscuous mode, and then try to send a frame. We then compare 740 * the frame data we sent to what was received. If the data matches, 741 * then the NIC is working correctly, otherwise we know the user has 742 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 743 * slot. In the latter case, there's no way the NIC can work correctly, 744 * so we print out a message on the console and abort the device attach. 745 */ 746 747 static int 748 re_diag(struct rl_softc *sc) 749 { 750 struct ifnet *ifp = sc->rl_ifp; 751 struct mbuf *m0; 752 struct ether_header *eh; 753 struct rl_desc *cur_rx; 754 u_int16_t status; 755 u_int32_t rxstat; 756 int total_len, i, error = 0, phyaddr; 757 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 758 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 759 760 /* Allocate a single mbuf */ 761 MGETHDR(m0, M_DONTWAIT, MT_DATA); 762 if (m0 == NULL) 763 return (ENOBUFS); 764 765 RL_LOCK(sc); 766 767 /* 768 * Initialize the NIC in test mode. This sets the chip up 769 * so that it can send and receive frames, but performs the 770 * following special functions: 771 * - Puts receiver in promiscuous mode 772 * - Enables digital loopback mode 773 * - Leaves interrupts turned off 774 */ 775 776 ifp->if_flags |= IFF_PROMISC; 777 sc->rl_testmode = 1; 778 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 779 re_init_locked(sc); 780 sc->rl_flags |= RL_FLAG_LINK; 781 if (sc->rl_type == RL_8169) 782 phyaddr = 1; 783 else 784 phyaddr = 0; 785 786 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 787 for (i = 0; i < RL_TIMEOUT; i++) { 788 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 789 if (!(status & BMCR_RESET)) 790 break; 791 } 792 793 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 794 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 795 796 DELAY(100000); 797 798 /* Put some data in the mbuf */ 799 800 eh = mtod(m0, struct ether_header *); 801 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 802 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 803 eh->ether_type = htons(ETHERTYPE_IP); 804 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 805 806 /* 807 * Queue the packet, start transmission. 808 * Note: IF_HANDOFF() ultimately calls re_start() for us. 809 */ 810 811 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 812 RL_UNLOCK(sc); 813 /* XXX: re_diag must not be called when in ALTQ mode */ 814 IF_HANDOFF(&ifp->if_snd, m0, ifp); 815 RL_LOCK(sc); 816 m0 = NULL; 817 818 /* Wait for it to propagate through the chip */ 819 820 DELAY(100000); 821 for (i = 0; i < RL_TIMEOUT; i++) { 822 status = CSR_READ_2(sc, RL_ISR); 823 CSR_WRITE_2(sc, RL_ISR, status); 824 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 825 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 826 break; 827 DELAY(10); 828 } 829 830 if (i == RL_TIMEOUT) { 831 device_printf(sc->rl_dev, 832 "diagnostic failed, failed to receive packet in" 833 " loopback mode\n"); 834 error = EIO; 835 goto done; 836 } 837 838 /* 839 * The packet should have been dumped into the first 840 * entry in the RX DMA ring. Grab it from there. 841 */ 842 843 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 844 sc->rl_ldata.rl_rx_list_map, 845 BUS_DMASYNC_POSTREAD); 846 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 847 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 848 BUS_DMASYNC_POSTREAD); 849 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 850 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 851 852 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 853 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 854 eh = mtod(m0, struct ether_header *); 855 856 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 857 total_len = RL_RXBYTES(cur_rx); 858 rxstat = le32toh(cur_rx->rl_cmdstat); 859 860 if (total_len != ETHER_MIN_LEN) { 861 device_printf(sc->rl_dev, 862 "diagnostic failed, received short packet\n"); 863 error = EIO; 864 goto done; 865 } 866 867 /* Test that the received packet data matches what we sent. */ 868 869 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 870 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 871 ntohs(eh->ether_type) != ETHERTYPE_IP) { 872 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 873 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 874 dst, ":", src, ":", ETHERTYPE_IP); 875 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 876 eh->ether_dhost, ":", eh->ether_shost, ":", 877 ntohs(eh->ether_type)); 878 device_printf(sc->rl_dev, "You may have a defective 32-bit " 879 "NIC plugged into a 64-bit PCI slot.\n"); 880 device_printf(sc->rl_dev, "Please re-install the NIC in a " 881 "32-bit slot for proper operation.\n"); 882 device_printf(sc->rl_dev, "Read the re(4) man page for more " 883 "details.\n"); 884 error = EIO; 885 } 886 887 done: 888 /* Turn interface off, release resources */ 889 890 sc->rl_testmode = 0; 891 sc->rl_flags &= ~RL_FLAG_LINK; 892 ifp->if_flags &= ~IFF_PROMISC; 893 re_stop(sc); 894 if (m0 != NULL) 895 m_freem(m0); 896 897 RL_UNLOCK(sc); 898 899 return (error); 900 } 901 902 #endif 903 904 /* 905 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 906 * IDs against our list and return a device name if we find a match. 907 */ 908 static int 909 re_probe(device_t dev) 910 { 911 const struct rl_type *t; 912 uint16_t devid, vendor; 913 uint16_t revid, sdevid; 914 int i; 915 916 vendor = pci_get_vendor(dev); 917 devid = pci_get_device(dev); 918 revid = pci_get_revid(dev); 919 sdevid = pci_get_subdevice(dev); 920 921 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 922 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 923 /* 924 * Only attach to rev. 3 of the Linksys EG1032 adapter. 925 * Rev. 2 is supported by sk(4). 926 */ 927 return (ENXIO); 928 } 929 } 930 931 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 932 if (revid != 0x20) { 933 /* 8139, let rl(4) take care of this device. */ 934 return (ENXIO); 935 } 936 } 937 938 t = re_devs; 939 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) { 940 if (vendor == t->rl_vid && devid == t->rl_did) { 941 device_set_desc(dev, t->rl_name); 942 return (BUS_PROBE_DEFAULT); 943 } 944 } 945 946 return (ENXIO); 947 } 948 949 /* 950 * Map a single buffer address. 951 */ 952 953 static void 954 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 955 { 956 bus_addr_t *addr; 957 958 if (error) 959 return; 960 961 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 962 addr = arg; 963 *addr = segs->ds_addr; 964 } 965 966 static int 967 re_allocmem(device_t dev, struct rl_softc *sc) 968 { 969 bus_addr_t lowaddr; 970 bus_size_t rx_list_size, tx_list_size; 971 int error; 972 int i; 973 974 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 975 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 976 977 /* 978 * Allocate the parent bus DMA tag appropriate for PCI. 979 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD 980 * register should be set. However some RealTek chips are known 981 * to be buggy on DAC handling, therefore disable DAC by limiting 982 * DMA address space to 32bit. PCIe variants of RealTek chips 983 * may not have the limitation. 984 */ 985 lowaddr = BUS_SPACE_MAXADDR; 986 if ((sc->rl_flags & RL_FLAG_PCIE) == 0) 987 lowaddr = BUS_SPACE_MAXADDR_32BIT; 988 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 989 lowaddr, BUS_SPACE_MAXADDR, NULL, NULL, 990 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 991 NULL, NULL, &sc->rl_parent_tag); 992 if (error) { 993 device_printf(dev, "could not allocate parent DMA tag\n"); 994 return (error); 995 } 996 997 /* 998 * Allocate map for TX mbufs. 999 */ 1000 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 1001 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1002 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 1003 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 1004 if (error) { 1005 device_printf(dev, "could not allocate TX DMA tag\n"); 1006 return (error); 1007 } 1008 1009 /* 1010 * Allocate map for RX mbufs. 1011 */ 1012 1013 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 1014 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 1015 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1016 MJUM9BYTES, 1, MJUM9BYTES, 0, NULL, NULL, 1017 &sc->rl_ldata.rl_jrx_mtag); 1018 if (error) { 1019 device_printf(dev, 1020 "could not allocate jumbo RX DMA tag\n"); 1021 return (error); 1022 } 1023 } 1024 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 1025 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1026 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 1027 if (error) { 1028 device_printf(dev, "could not allocate RX DMA tag\n"); 1029 return (error); 1030 } 1031 1032 /* 1033 * Allocate map for TX descriptor list. 1034 */ 1035 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1036 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1037 NULL, tx_list_size, 1, tx_list_size, 0, 1038 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1039 if (error) { 1040 device_printf(dev, "could not allocate TX DMA ring tag\n"); 1041 return (error); 1042 } 1043 1044 /* Allocate DMA'able memory for the TX ring */ 1045 1046 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1047 (void **)&sc->rl_ldata.rl_tx_list, 1048 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1049 &sc->rl_ldata.rl_tx_list_map); 1050 if (error) { 1051 device_printf(dev, "could not allocate TX DMA ring\n"); 1052 return (error); 1053 } 1054 1055 /* Load the map for the TX ring. */ 1056 1057 sc->rl_ldata.rl_tx_list_addr = 0; 1058 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1059 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1060 tx_list_size, re_dma_map_addr, 1061 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1062 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 1063 device_printf(dev, "could not load TX DMA ring\n"); 1064 return (ENOMEM); 1065 } 1066 1067 /* Create DMA maps for TX buffers */ 1068 1069 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1070 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1071 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1072 if (error) { 1073 device_printf(dev, "could not create DMA map for TX\n"); 1074 return (error); 1075 } 1076 } 1077 1078 /* 1079 * Allocate map for RX descriptor list. 1080 */ 1081 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1082 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1083 NULL, rx_list_size, 1, rx_list_size, 0, 1084 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1085 if (error) { 1086 device_printf(dev, "could not create RX DMA ring tag\n"); 1087 return (error); 1088 } 1089 1090 /* Allocate DMA'able memory for the RX ring */ 1091 1092 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1093 (void **)&sc->rl_ldata.rl_rx_list, 1094 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1095 &sc->rl_ldata.rl_rx_list_map); 1096 if (error) { 1097 device_printf(dev, "could not allocate RX DMA ring\n"); 1098 return (error); 1099 } 1100 1101 /* Load the map for the RX ring. */ 1102 1103 sc->rl_ldata.rl_rx_list_addr = 0; 1104 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1105 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1106 rx_list_size, re_dma_map_addr, 1107 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1108 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1109 device_printf(dev, "could not load RX DMA ring\n"); 1110 return (ENOMEM); 1111 } 1112 1113 /* Create DMA maps for RX buffers */ 1114 1115 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 1116 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0, 1117 &sc->rl_ldata.rl_jrx_sparemap); 1118 if (error) { 1119 device_printf(dev, 1120 "could not create spare DMA map for jumbo RX\n"); 1121 return (error); 1122 } 1123 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1124 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0, 1125 &sc->rl_ldata.rl_jrx_desc[i].rx_dmamap); 1126 if (error) { 1127 device_printf(dev, 1128 "could not create DMA map for jumbo RX\n"); 1129 return (error); 1130 } 1131 } 1132 } 1133 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1134 &sc->rl_ldata.rl_rx_sparemap); 1135 if (error) { 1136 device_printf(dev, "could not create spare DMA map for RX\n"); 1137 return (error); 1138 } 1139 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1140 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1141 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1142 if (error) { 1143 device_printf(dev, "could not create DMA map for RX\n"); 1144 return (error); 1145 } 1146 } 1147 1148 /* Create DMA map for statistics. */ 1149 error = bus_dma_tag_create(sc->rl_parent_tag, RL_DUMP_ALIGN, 0, 1150 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1151 sizeof(struct rl_stats), 1, sizeof(struct rl_stats), 0, NULL, NULL, 1152 &sc->rl_ldata.rl_stag); 1153 if (error) { 1154 device_printf(dev, "could not create statistics DMA tag\n"); 1155 return (error); 1156 } 1157 /* Allocate DMA'able memory for statistics. */ 1158 error = bus_dmamem_alloc(sc->rl_ldata.rl_stag, 1159 (void **)&sc->rl_ldata.rl_stats, 1160 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1161 &sc->rl_ldata.rl_smap); 1162 if (error) { 1163 device_printf(dev, 1164 "could not allocate statistics DMA memory\n"); 1165 return (error); 1166 } 1167 /* Load the map for statistics. */ 1168 sc->rl_ldata.rl_stats_addr = 0; 1169 error = bus_dmamap_load(sc->rl_ldata.rl_stag, sc->rl_ldata.rl_smap, 1170 sc->rl_ldata.rl_stats, sizeof(struct rl_stats), re_dma_map_addr, 1171 &sc->rl_ldata.rl_stats_addr, BUS_DMA_NOWAIT); 1172 if (error != 0 || sc->rl_ldata.rl_stats_addr == 0) { 1173 device_printf(dev, "could not load statistics DMA memory\n"); 1174 return (ENOMEM); 1175 } 1176 1177 return (0); 1178 } 1179 1180 /* 1181 * Attach the interface. Allocate softc structures, do ifmedia 1182 * setup and ethernet/BPF attach. 1183 */ 1184 static int 1185 re_attach(device_t dev) 1186 { 1187 u_char eaddr[ETHER_ADDR_LEN]; 1188 u_int16_t as[ETHER_ADDR_LEN / 2]; 1189 struct rl_softc *sc; 1190 struct ifnet *ifp; 1191 const struct rl_hwrev *hw_rev; 1192 u_int32_t cap, ctl; 1193 int hwrev; 1194 u_int16_t devid, re_did = 0; 1195 int error = 0, i, phy, rid; 1196 int msic, msixc, reg; 1197 uint8_t cfg; 1198 1199 sc = device_get_softc(dev); 1200 sc->rl_dev = dev; 1201 1202 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1203 MTX_DEF); 1204 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1205 1206 /* 1207 * Map control/status registers. 1208 */ 1209 pci_enable_busmaster(dev); 1210 1211 devid = pci_get_device(dev); 1212 /* 1213 * Prefer memory space register mapping over IO space. 1214 * Because RTL8169SC does not seem to work when memory mapping 1215 * is used always activate io mapping. 1216 */ 1217 if (devid == RT_DEVICEID_8169SC) 1218 prefer_iomap = 1; 1219 if (prefer_iomap == 0) { 1220 sc->rl_res_id = PCIR_BAR(1); 1221 sc->rl_res_type = SYS_RES_MEMORY; 1222 /* RTL8168/8101E seems to use different BARs. */ 1223 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E) 1224 sc->rl_res_id = PCIR_BAR(2); 1225 } else { 1226 sc->rl_res_id = PCIR_BAR(0); 1227 sc->rl_res_type = SYS_RES_IOPORT; 1228 } 1229 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1230 &sc->rl_res_id, RF_ACTIVE); 1231 if (sc->rl_res == NULL && prefer_iomap == 0) { 1232 sc->rl_res_id = PCIR_BAR(0); 1233 sc->rl_res_type = SYS_RES_IOPORT; 1234 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1235 &sc->rl_res_id, RF_ACTIVE); 1236 } 1237 if (sc->rl_res == NULL) { 1238 device_printf(dev, "couldn't map ports/memory\n"); 1239 error = ENXIO; 1240 goto fail; 1241 } 1242 1243 sc->rl_btag = rman_get_bustag(sc->rl_res); 1244 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1245 1246 msic = pci_msi_count(dev); 1247 msixc = pci_msix_count(dev); 1248 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 1249 sc->rl_flags |= RL_FLAG_PCIE; 1250 sc->rl_expcap = reg; 1251 } 1252 if (bootverbose) { 1253 device_printf(dev, "MSI count : %d\n", msic); 1254 device_printf(dev, "MSI-X count : %d\n", msixc); 1255 } 1256 if (msix_disable > 0) 1257 msixc = 0; 1258 if (msi_disable > 0) 1259 msic = 0; 1260 /* Prefer MSI-X to MSI. */ 1261 if (msixc > 0) { 1262 msixc = 1; 1263 rid = PCIR_BAR(4); 1264 sc->rl_res_pba = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1265 &rid, RF_ACTIVE); 1266 if (sc->rl_res_pba == NULL) { 1267 device_printf(sc->rl_dev, 1268 "could not allocate MSI-X PBA resource\n"); 1269 } 1270 if (sc->rl_res_pba != NULL && 1271 pci_alloc_msix(dev, &msixc) == 0) { 1272 if (msixc == 1) { 1273 device_printf(dev, "Using %d MSI-X message\n", 1274 msixc); 1275 sc->rl_flags |= RL_FLAG_MSIX; 1276 } else 1277 pci_release_msi(dev); 1278 } 1279 if ((sc->rl_flags & RL_FLAG_MSIX) == 0) { 1280 if (sc->rl_res_pba != NULL) 1281 bus_release_resource(dev, SYS_RES_MEMORY, rid, 1282 sc->rl_res_pba); 1283 sc->rl_res_pba = NULL; 1284 msixc = 0; 1285 } 1286 } 1287 /* Prefer MSI to INTx. */ 1288 if (msixc == 0 && msic > 0) { 1289 msic = 1; 1290 if (pci_alloc_msi(dev, &msic) == 0) { 1291 if (msic == RL_MSI_MESSAGES) { 1292 device_printf(dev, "Using %d MSI message\n", 1293 msic); 1294 sc->rl_flags |= RL_FLAG_MSI; 1295 /* Explicitly set MSI enable bit. */ 1296 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1297 cfg = CSR_READ_1(sc, RL_CFG2); 1298 cfg |= RL_CFG2_MSI; 1299 CSR_WRITE_1(sc, RL_CFG2, cfg); 1300 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1301 } else 1302 pci_release_msi(dev); 1303 } 1304 if ((sc->rl_flags & RL_FLAG_MSI) == 0) 1305 msic = 0; 1306 } 1307 1308 /* Allocate interrupt */ 1309 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) { 1310 rid = 0; 1311 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1312 RF_SHAREABLE | RF_ACTIVE); 1313 if (sc->rl_irq[0] == NULL) { 1314 device_printf(dev, "couldn't allocate IRQ resources\n"); 1315 error = ENXIO; 1316 goto fail; 1317 } 1318 } else { 1319 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1320 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1321 SYS_RES_IRQ, &rid, RF_ACTIVE); 1322 if (sc->rl_irq[i] == NULL) { 1323 device_printf(dev, 1324 "couldn't llocate IRQ resources for " 1325 "message %d\n", rid); 1326 error = ENXIO; 1327 goto fail; 1328 } 1329 } 1330 } 1331 1332 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1333 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1334 cfg = CSR_READ_1(sc, RL_CFG2); 1335 if ((cfg & RL_CFG2_MSI) != 0) { 1336 device_printf(dev, "turning off MSI enable bit.\n"); 1337 cfg &= ~RL_CFG2_MSI; 1338 CSR_WRITE_1(sc, RL_CFG2, cfg); 1339 } 1340 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1341 } 1342 1343 /* Disable ASPM L0S/L1. */ 1344 if (sc->rl_expcap != 0) { 1345 cap = pci_read_config(dev, sc->rl_expcap + 1346 PCIR_EXPRESS_LINK_CAP, 2); 1347 if ((cap & PCIM_LINK_CAP_ASPM) != 0) { 1348 ctl = pci_read_config(dev, sc->rl_expcap + 1349 PCIR_EXPRESS_LINK_CTL, 2); 1350 if ((ctl & 0x0003) != 0) { 1351 ctl &= ~0x0003; 1352 pci_write_config(dev, sc->rl_expcap + 1353 PCIR_EXPRESS_LINK_CTL, ctl, 2); 1354 device_printf(dev, "ASPM disabled\n"); 1355 } 1356 } else 1357 device_printf(dev, "no ASPM capability\n"); 1358 } 1359 1360 hw_rev = re_hwrevs; 1361 hwrev = CSR_READ_4(sc, RL_TXCFG); 1362 switch (hwrev & 0x70000000) { 1363 case 0x00000000: 1364 case 0x10000000: 1365 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000); 1366 hwrev &= (RL_TXCFG_HWREV | 0x80000000); 1367 break; 1368 default: 1369 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000); 1370 hwrev &= RL_TXCFG_HWREV; 1371 break; 1372 } 1373 device_printf(dev, "MAC rev. 0x%08x\n", hwrev & 0x00700000); 1374 while (hw_rev->rl_desc != NULL) { 1375 if (hw_rev->rl_rev == hwrev) { 1376 sc->rl_type = hw_rev->rl_type; 1377 sc->rl_hwrev = hw_rev; 1378 break; 1379 } 1380 hw_rev++; 1381 } 1382 if (hw_rev->rl_desc == NULL) { 1383 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev); 1384 error = ENXIO; 1385 goto fail; 1386 } 1387 1388 switch (hw_rev->rl_rev) { 1389 case RL_HWREV_8139CPLUS: 1390 sc->rl_flags |= RL_FLAG_FASTETHER | RL_FLAG_AUTOPAD; 1391 break; 1392 case RL_HWREV_8100E: 1393 case RL_HWREV_8101E: 1394 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_FASTETHER; 1395 break; 1396 case RL_HWREV_8102E: 1397 case RL_HWREV_8102EL: 1398 case RL_HWREV_8102EL_SPIN1: 1399 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1400 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | 1401 RL_FLAG_AUTOPAD; 1402 break; 1403 case RL_HWREV_8103E: 1404 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1405 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | 1406 RL_FLAG_AUTOPAD | RL_FLAG_MACSLEEP; 1407 break; 1408 case RL_HWREV_8401E: 1409 case RL_HWREV_8105E: 1410 case RL_HWREV_8105E_SPIN1: 1411 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1412 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1413 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD; 1414 break; 1415 case RL_HWREV_8402: 1416 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1417 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1418 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | 1419 RL_FLAG_CMDSTOP_WAIT_TXQ; 1420 break; 1421 case RL_HWREV_8168B_SPIN1: 1422 case RL_HWREV_8168B_SPIN2: 1423 sc->rl_flags |= RL_FLAG_WOLRXENB; 1424 /* FALLTHROUGH */ 1425 case RL_HWREV_8168B_SPIN3: 1426 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT; 1427 break; 1428 case RL_HWREV_8168C_SPIN2: 1429 sc->rl_flags |= RL_FLAG_MACSLEEP; 1430 /* FALLTHROUGH */ 1431 case RL_HWREV_8168C: 1432 if ((hwrev & 0x00700000) == 0x00200000) 1433 sc->rl_flags |= RL_FLAG_MACSLEEP; 1434 /* FALLTHROUGH */ 1435 case RL_HWREV_8168CP: 1436 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1437 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1438 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK; 1439 break; 1440 case RL_HWREV_8168D: 1441 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1442 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1443 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1444 RL_FLAG_WOL_MANLINK; 1445 break; 1446 case RL_HWREV_8168DP: 1447 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1448 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_AUTOPAD | 1449 RL_FLAG_JUMBOV2 | RL_FLAG_WAIT_TXPOLL | RL_FLAG_WOL_MANLINK; 1450 break; 1451 case RL_HWREV_8168E: 1452 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1453 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1454 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1455 RL_FLAG_WOL_MANLINK; 1456 break; 1457 case RL_HWREV_8168E_VL: 1458 case RL_HWREV_8168F: 1459 case RL_HWREV_8411: 1460 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1461 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1462 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1463 RL_FLAG_CMDSTOP_WAIT_TXQ | RL_FLAG_WOL_MANLINK; 1464 break; 1465 case RL_HWREV_8169_8110SB: 1466 case RL_HWREV_8169_8110SBL: 1467 case RL_HWREV_8169_8110SC: 1468 case RL_HWREV_8169_8110SCE: 1469 sc->rl_flags |= RL_FLAG_PHYWAKE; 1470 /* FALLTHROUGH */ 1471 case RL_HWREV_8169: 1472 case RL_HWREV_8169S: 1473 case RL_HWREV_8110S: 1474 sc->rl_flags |= RL_FLAG_MACRESET; 1475 break; 1476 default: 1477 break; 1478 } 1479 1480 /* Reset the adapter. */ 1481 RL_LOCK(sc); 1482 re_reset(sc); 1483 RL_UNLOCK(sc); 1484 1485 /* Enable PME. */ 1486 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1487 cfg = CSR_READ_1(sc, RL_CFG1); 1488 cfg |= RL_CFG1_PME; 1489 CSR_WRITE_1(sc, RL_CFG1, cfg); 1490 cfg = CSR_READ_1(sc, RL_CFG5); 1491 cfg &= RL_CFG5_PME_STS; 1492 CSR_WRITE_1(sc, RL_CFG5, cfg); 1493 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1494 1495 if ((sc->rl_flags & RL_FLAG_PAR) != 0) { 1496 /* 1497 * XXX Should have a better way to extract station 1498 * address from EEPROM. 1499 */ 1500 for (i = 0; i < ETHER_ADDR_LEN; i++) 1501 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1502 } else { 1503 sc->rl_eewidth = RL_9356_ADDR_LEN; 1504 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1505 if (re_did != 0x8129) 1506 sc->rl_eewidth = RL_9346_ADDR_LEN; 1507 1508 /* 1509 * Get station address from the EEPROM. 1510 */ 1511 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1512 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1513 as[i] = le16toh(as[i]); 1514 bcopy(as, eaddr, sizeof(eaddr)); 1515 } 1516 1517 if (sc->rl_type == RL_8169) { 1518 /* Set RX length mask and number of descriptors. */ 1519 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1520 sc->rl_txstart = RL_GTXSTART; 1521 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1522 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1523 } else { 1524 /* Set RX length mask and number of descriptors. */ 1525 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1526 sc->rl_txstart = RL_TXSTART; 1527 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1528 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1529 } 1530 1531 error = re_allocmem(dev, sc); 1532 if (error) 1533 goto fail; 1534 re_add_sysctls(sc); 1535 1536 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1537 if (ifp == NULL) { 1538 device_printf(dev, "can not if_alloc()\n"); 1539 error = ENOSPC; 1540 goto fail; 1541 } 1542 1543 /* Take controller out of deep sleep mode. */ 1544 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 1545 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 1546 CSR_WRITE_1(sc, RL_GPIO, 1547 CSR_READ_1(sc, RL_GPIO) | 0x01); 1548 else 1549 CSR_WRITE_1(sc, RL_GPIO, 1550 CSR_READ_1(sc, RL_GPIO) & ~0x01); 1551 } 1552 1553 /* Take PHY out of power down mode. */ 1554 if ((sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) { 1555 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80); 1556 if (hw_rev->rl_rev == RL_HWREV_8401E) 1557 CSR_WRITE_1(sc, 0xD1, CSR_READ_1(sc, 0xD1) & ~0x08); 1558 } 1559 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) { 1560 re_gmii_writereg(dev, 1, 0x1f, 0); 1561 re_gmii_writereg(dev, 1, 0x0e, 0); 1562 } 1563 1564 #define RE_PHYAD_INTERNAL 0 1565 1566 /* Do MII setup. */ 1567 phy = RE_PHYAD_INTERNAL; 1568 if (sc->rl_type == RL_8169) 1569 phy = 1; 1570 error = mii_attach(dev, &sc->rl_miibus, ifp, re_ifmedia_upd, 1571 re_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, MIIF_DOPAUSE); 1572 if (error != 0) { 1573 device_printf(dev, "attaching PHYs failed\n"); 1574 goto fail; 1575 } 1576 1577 ifp->if_softc = sc; 1578 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1579 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1580 ifp->if_ioctl = re_ioctl; 1581 ifp->if_start = re_start; 1582 /* 1583 * RTL8168/8111C generates wrong IP checksummed frame if the 1584 * packet has IP options so disable TX IP checksum offloading. 1585 */ 1586 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168C || 1587 sc->rl_hwrev->rl_rev == RL_HWREV_8168C_SPIN2) 1588 ifp->if_hwassist = CSUM_TCP | CSUM_UDP; 1589 else 1590 ifp->if_hwassist = CSUM_IP | CSUM_TCP | CSUM_UDP; 1591 ifp->if_hwassist |= CSUM_TSO; 1592 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 1593 ifp->if_capenable = ifp->if_capabilities; 1594 ifp->if_init = re_init; 1595 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1596 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1597 IFQ_SET_READY(&ifp->if_snd); 1598 1599 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1600 1601 /* 1602 * Call MI attach routine. 1603 */ 1604 ether_ifattach(ifp, eaddr); 1605 1606 /* VLAN capability setup */ 1607 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1608 if (ifp->if_capabilities & IFCAP_HWCSUM) 1609 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1610 /* Enable WOL if PM is supported. */ 1611 if (pci_find_cap(sc->rl_dev, PCIY_PMG, ®) == 0) 1612 ifp->if_capabilities |= IFCAP_WOL; 1613 ifp->if_capenable = ifp->if_capabilities; 1614 ifp->if_capenable &= ~(IFCAP_WOL_UCAST | IFCAP_WOL_MCAST); 1615 /* 1616 * Don't enable TSO by default. It is known to generate 1617 * corrupted TCP segments(bad TCP options) under certain 1618 * circumtances. 1619 */ 1620 ifp->if_hwassist &= ~CSUM_TSO; 1621 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO); 1622 #ifdef DEVICE_POLLING 1623 ifp->if_capabilities |= IFCAP_POLLING; 1624 #endif 1625 /* 1626 * Tell the upper layer(s) we support long frames. 1627 * Must appear after the call to ether_ifattach() because 1628 * ether_ifattach() sets ifi_hdrlen to the default value. 1629 */ 1630 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1631 1632 #ifdef DEV_NETMAP 1633 re_netmap_attach(sc); 1634 #endif /* DEV_NETMAP */ 1635 #ifdef RE_DIAG 1636 /* 1637 * Perform hardware diagnostic on the original RTL8169. 1638 * Some 32-bit cards were incorrectly wired and would 1639 * malfunction if plugged into a 64-bit slot. 1640 */ 1641 1642 if (hwrev == RL_HWREV_8169) { 1643 error = re_diag(sc); 1644 if (error) { 1645 device_printf(dev, 1646 "attach aborted due to hardware diag failure\n"); 1647 ether_ifdetach(ifp); 1648 goto fail; 1649 } 1650 } 1651 #endif 1652 1653 #ifdef RE_TX_MODERATION 1654 intr_filter = 1; 1655 #endif 1656 /* Hook interrupt last to avoid having to lock softc */ 1657 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 && 1658 intr_filter == 0) { 1659 error = bus_setup_intr(dev, sc->rl_irq[0], 1660 INTR_TYPE_NET | INTR_MPSAFE, NULL, re_intr_msi, sc, 1661 &sc->rl_intrhand[0]); 1662 } else { 1663 error = bus_setup_intr(dev, sc->rl_irq[0], 1664 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1665 &sc->rl_intrhand[0]); 1666 } 1667 if (error) { 1668 device_printf(dev, "couldn't set up irq\n"); 1669 ether_ifdetach(ifp); 1670 } 1671 1672 fail: 1673 1674 if (error) 1675 re_detach(dev); 1676 1677 return (error); 1678 } 1679 1680 /* 1681 * Shutdown hardware and free up resources. This can be called any 1682 * time after the mutex has been initialized. It is called in both 1683 * the error case in attach and the normal detach case so it needs 1684 * to be careful about only freeing resources that have actually been 1685 * allocated. 1686 */ 1687 static int 1688 re_detach(device_t dev) 1689 { 1690 struct rl_softc *sc; 1691 struct ifnet *ifp; 1692 int i, rid; 1693 1694 sc = device_get_softc(dev); 1695 ifp = sc->rl_ifp; 1696 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1697 1698 /* These should only be active if attach succeeded */ 1699 if (device_is_attached(dev)) { 1700 #ifdef DEVICE_POLLING 1701 if (ifp->if_capenable & IFCAP_POLLING) 1702 ether_poll_deregister(ifp); 1703 #endif 1704 RL_LOCK(sc); 1705 #if 0 1706 sc->suspended = 1; 1707 #endif 1708 re_stop(sc); 1709 RL_UNLOCK(sc); 1710 callout_drain(&sc->rl_stat_callout); 1711 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1712 /* 1713 * Force off the IFF_UP flag here, in case someone 1714 * still had a BPF descriptor attached to this 1715 * interface. If they do, ether_ifdetach() will cause 1716 * the BPF code to try and clear the promisc mode 1717 * flag, which will bubble down to re_ioctl(), 1718 * which will try to call re_init() again. This will 1719 * turn the NIC back on and restart the MII ticker, 1720 * which will panic the system when the kernel tries 1721 * to invoke the re_tick() function that isn't there 1722 * anymore. 1723 */ 1724 ifp->if_flags &= ~IFF_UP; 1725 ether_ifdetach(ifp); 1726 } 1727 if (sc->rl_miibus) 1728 device_delete_child(dev, sc->rl_miibus); 1729 bus_generic_detach(dev); 1730 1731 /* 1732 * The rest is resource deallocation, so we should already be 1733 * stopped here. 1734 */ 1735 1736 if (sc->rl_intrhand[0] != NULL) { 1737 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]); 1738 sc->rl_intrhand[0] = NULL; 1739 } 1740 if (ifp != NULL) 1741 if_free(ifp); 1742 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) 1743 rid = 0; 1744 else 1745 rid = 1; 1746 if (sc->rl_irq[0] != NULL) { 1747 bus_release_resource(dev, SYS_RES_IRQ, rid, sc->rl_irq[0]); 1748 sc->rl_irq[0] = NULL; 1749 } 1750 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0) 1751 pci_release_msi(dev); 1752 if (sc->rl_res_pba) { 1753 rid = PCIR_BAR(4); 1754 bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->rl_res_pba); 1755 } 1756 if (sc->rl_res) 1757 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, 1758 sc->rl_res); 1759 1760 /* Unload and free the RX DMA ring memory and map */ 1761 1762 if (sc->rl_ldata.rl_rx_list_tag) { 1763 if (sc->rl_ldata.rl_rx_list_map) 1764 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1765 sc->rl_ldata.rl_rx_list_map); 1766 if (sc->rl_ldata.rl_rx_list_map && sc->rl_ldata.rl_rx_list) 1767 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1768 sc->rl_ldata.rl_rx_list, 1769 sc->rl_ldata.rl_rx_list_map); 1770 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1771 } 1772 1773 /* Unload and free the TX DMA ring memory and map */ 1774 1775 if (sc->rl_ldata.rl_tx_list_tag) { 1776 if (sc->rl_ldata.rl_tx_list_map) 1777 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1778 sc->rl_ldata.rl_tx_list_map); 1779 if (sc->rl_ldata.rl_tx_list_map && sc->rl_ldata.rl_tx_list) 1780 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1781 sc->rl_ldata.rl_tx_list, 1782 sc->rl_ldata.rl_tx_list_map); 1783 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1784 } 1785 1786 /* Destroy all the RX and TX buffer maps */ 1787 1788 if (sc->rl_ldata.rl_tx_mtag) { 1789 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1790 if (sc->rl_ldata.rl_tx_desc[i].tx_dmamap) 1791 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1792 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1793 } 1794 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1795 } 1796 if (sc->rl_ldata.rl_rx_mtag) { 1797 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1798 if (sc->rl_ldata.rl_rx_desc[i].rx_dmamap) 1799 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1800 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1801 } 1802 if (sc->rl_ldata.rl_rx_sparemap) 1803 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1804 sc->rl_ldata.rl_rx_sparemap); 1805 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1806 } 1807 if (sc->rl_ldata.rl_jrx_mtag) { 1808 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1809 if (sc->rl_ldata.rl_jrx_desc[i].rx_dmamap) 1810 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag, 1811 sc->rl_ldata.rl_jrx_desc[i].rx_dmamap); 1812 } 1813 if (sc->rl_ldata.rl_jrx_sparemap) 1814 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag, 1815 sc->rl_ldata.rl_jrx_sparemap); 1816 bus_dma_tag_destroy(sc->rl_ldata.rl_jrx_mtag); 1817 } 1818 /* Unload and free the stats buffer and map */ 1819 1820 if (sc->rl_ldata.rl_stag) { 1821 if (sc->rl_ldata.rl_smap) 1822 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1823 sc->rl_ldata.rl_smap); 1824 if (sc->rl_ldata.rl_smap && sc->rl_ldata.rl_stats) 1825 bus_dmamem_free(sc->rl_ldata.rl_stag, 1826 sc->rl_ldata.rl_stats, sc->rl_ldata.rl_smap); 1827 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1828 } 1829 1830 #ifdef DEV_NETMAP 1831 netmap_detach(ifp); 1832 #endif /* DEV_NETMAP */ 1833 if (sc->rl_parent_tag) 1834 bus_dma_tag_destroy(sc->rl_parent_tag); 1835 1836 mtx_destroy(&sc->rl_mtx); 1837 1838 return (0); 1839 } 1840 1841 static __inline void 1842 re_discard_rxbuf(struct rl_softc *sc, int idx) 1843 { 1844 struct rl_desc *desc; 1845 struct rl_rxdesc *rxd; 1846 uint32_t cmdstat; 1847 1848 if (sc->rl_ifp->if_mtu > RL_MTU && 1849 (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) 1850 rxd = &sc->rl_ldata.rl_jrx_desc[idx]; 1851 else 1852 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1853 desc = &sc->rl_ldata.rl_rx_list[idx]; 1854 desc->rl_vlanctl = 0; 1855 cmdstat = rxd->rx_size; 1856 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1857 cmdstat |= RL_RDESC_CMD_EOR; 1858 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1859 } 1860 1861 static int 1862 re_newbuf(struct rl_softc *sc, int idx) 1863 { 1864 struct mbuf *m; 1865 struct rl_rxdesc *rxd; 1866 bus_dma_segment_t segs[1]; 1867 bus_dmamap_t map; 1868 struct rl_desc *desc; 1869 uint32_t cmdstat; 1870 int error, nsegs; 1871 1872 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1873 if (m == NULL) 1874 return (ENOBUFS); 1875 1876 m->m_len = m->m_pkthdr.len = MCLBYTES; 1877 #ifdef RE_FIXUP_RX 1878 /* 1879 * This is part of an evil trick to deal with non-x86 platforms. 1880 * The RealTek chip requires RX buffers to be aligned on 64-bit 1881 * boundaries, but that will hose non-x86 machines. To get around 1882 * this, we leave some empty space at the start of each buffer 1883 * and for non-x86 hosts, we copy the buffer back six bytes 1884 * to achieve word alignment. This is slightly more efficient 1885 * than allocating a new buffer, copying the contents, and 1886 * discarding the old buffer. 1887 */ 1888 m_adj(m, RE_ETHER_ALIGN); 1889 #endif 1890 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1891 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1892 if (error != 0) { 1893 m_freem(m); 1894 return (ENOBUFS); 1895 } 1896 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1897 1898 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1899 if (rxd->rx_m != NULL) { 1900 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1901 BUS_DMASYNC_POSTREAD); 1902 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1903 } 1904 1905 rxd->rx_m = m; 1906 map = rxd->rx_dmamap; 1907 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1908 rxd->rx_size = segs[0].ds_len; 1909 sc->rl_ldata.rl_rx_sparemap = map; 1910 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1911 BUS_DMASYNC_PREREAD); 1912 1913 desc = &sc->rl_ldata.rl_rx_list[idx]; 1914 desc->rl_vlanctl = 0; 1915 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1916 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1917 cmdstat = segs[0].ds_len; 1918 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1919 cmdstat |= RL_RDESC_CMD_EOR; 1920 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1921 1922 return (0); 1923 } 1924 1925 static int 1926 re_jumbo_newbuf(struct rl_softc *sc, int idx) 1927 { 1928 struct mbuf *m; 1929 struct rl_rxdesc *rxd; 1930 bus_dma_segment_t segs[1]; 1931 bus_dmamap_t map; 1932 struct rl_desc *desc; 1933 uint32_t cmdstat; 1934 int error, nsegs; 1935 1936 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 1937 if (m == NULL) 1938 return (ENOBUFS); 1939 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1940 #ifdef RE_FIXUP_RX 1941 m_adj(m, RE_ETHER_ALIGN); 1942 #endif 1943 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_jrx_mtag, 1944 sc->rl_ldata.rl_jrx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1945 if (error != 0) { 1946 m_freem(m); 1947 return (ENOBUFS); 1948 } 1949 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1950 1951 rxd = &sc->rl_ldata.rl_jrx_desc[idx]; 1952 if (rxd->rx_m != NULL) { 1953 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap, 1954 BUS_DMASYNC_POSTREAD); 1955 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap); 1956 } 1957 1958 rxd->rx_m = m; 1959 map = rxd->rx_dmamap; 1960 rxd->rx_dmamap = sc->rl_ldata.rl_jrx_sparemap; 1961 rxd->rx_size = segs[0].ds_len; 1962 sc->rl_ldata.rl_jrx_sparemap = map; 1963 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap, 1964 BUS_DMASYNC_PREREAD); 1965 1966 desc = &sc->rl_ldata.rl_rx_list[idx]; 1967 desc->rl_vlanctl = 0; 1968 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1969 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1970 cmdstat = segs[0].ds_len; 1971 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1972 cmdstat |= RL_RDESC_CMD_EOR; 1973 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1974 1975 return (0); 1976 } 1977 1978 #ifdef RE_FIXUP_RX 1979 static __inline void 1980 re_fixup_rx(struct mbuf *m) 1981 { 1982 int i; 1983 uint16_t *src, *dst; 1984 1985 src = mtod(m, uint16_t *); 1986 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1987 1988 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1989 *dst++ = *src++; 1990 1991 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1992 } 1993 #endif 1994 1995 static int 1996 re_tx_list_init(struct rl_softc *sc) 1997 { 1998 struct rl_desc *desc; 1999 int i; 2000 2001 RL_LOCK_ASSERT(sc); 2002 2003 bzero(sc->rl_ldata.rl_tx_list, 2004 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 2005 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 2006 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 2007 #ifdef DEV_NETMAP 2008 re_netmap_tx_init(sc); 2009 #endif /* DEV_NETMAP */ 2010 /* Set EOR. */ 2011 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 2012 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 2013 2014 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2015 sc->rl_ldata.rl_tx_list_map, 2016 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2017 2018 sc->rl_ldata.rl_tx_prodidx = 0; 2019 sc->rl_ldata.rl_tx_considx = 0; 2020 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 2021 2022 return (0); 2023 } 2024 2025 static int 2026 re_rx_list_init(struct rl_softc *sc) 2027 { 2028 int error, i; 2029 2030 bzero(sc->rl_ldata.rl_rx_list, 2031 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 2032 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2033 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 2034 if ((error = re_newbuf(sc, i)) != 0) 2035 return (error); 2036 } 2037 #ifdef DEV_NETMAP 2038 re_netmap_rx_init(sc); 2039 #endif /* DEV_NETMAP */ 2040 2041 /* Flush the RX descriptors */ 2042 2043 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2044 sc->rl_ldata.rl_rx_list_map, 2045 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2046 2047 sc->rl_ldata.rl_rx_prodidx = 0; 2048 sc->rl_head = sc->rl_tail = NULL; 2049 sc->rl_int_rx_act = 0; 2050 2051 return (0); 2052 } 2053 2054 static int 2055 re_jrx_list_init(struct rl_softc *sc) 2056 { 2057 int error, i; 2058 2059 bzero(sc->rl_ldata.rl_rx_list, 2060 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 2061 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2062 sc->rl_ldata.rl_jrx_desc[i].rx_m = NULL; 2063 if ((error = re_jumbo_newbuf(sc, i)) != 0) 2064 return (error); 2065 } 2066 2067 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2068 sc->rl_ldata.rl_rx_list_map, 2069 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2070 2071 sc->rl_ldata.rl_rx_prodidx = 0; 2072 sc->rl_head = sc->rl_tail = NULL; 2073 sc->rl_int_rx_act = 0; 2074 2075 return (0); 2076 } 2077 2078 /* 2079 * RX handler for C+ and 8169. For the gigE chips, we support 2080 * the reception of jumbo frames that have been fragmented 2081 * across multiple 2K mbuf cluster buffers. 2082 */ 2083 static int 2084 re_rxeof(struct rl_softc *sc, int *rx_npktsp) 2085 { 2086 struct mbuf *m; 2087 struct ifnet *ifp; 2088 int i, rxerr, total_len; 2089 struct rl_desc *cur_rx; 2090 u_int32_t rxstat, rxvlan; 2091 int jumbo, maxpkt = 16, rx_npkts = 0; 2092 2093 RL_LOCK_ASSERT(sc); 2094 2095 ifp = sc->rl_ifp; 2096 #ifdef DEV_NETMAP 2097 if (ifp->if_capenable & IFCAP_NETMAP) { 2098 selwakeuppri(&NA(ifp)->rx_rings->si, PI_NET); 2099 return 0; 2100 } 2101 #endif /* DEV_NETMAP */ 2102 if (ifp->if_mtu > RL_MTU && (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) 2103 jumbo = 1; 2104 else 2105 jumbo = 0; 2106 2107 /* Invalidate the descriptor memory */ 2108 2109 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2110 sc->rl_ldata.rl_rx_list_map, 2111 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2112 2113 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 2114 i = RL_RX_DESC_NXT(sc, i)) { 2115 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2116 break; 2117 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 2118 rxstat = le32toh(cur_rx->rl_cmdstat); 2119 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 2120 break; 2121 total_len = rxstat & sc->rl_rxlenmask; 2122 rxvlan = le32toh(cur_rx->rl_vlanctl); 2123 if (jumbo != 0) 2124 m = sc->rl_ldata.rl_jrx_desc[i].rx_m; 2125 else 2126 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 2127 2128 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 2129 (rxstat & (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) != 2130 (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) { 2131 /* 2132 * RTL8168C or later controllers do not 2133 * support multi-fragment packet. 2134 */ 2135 re_discard_rxbuf(sc, i); 2136 continue; 2137 } else if ((rxstat & RL_RDESC_STAT_EOF) == 0) { 2138 if (re_newbuf(sc, i) != 0) { 2139 /* 2140 * If this is part of a multi-fragment packet, 2141 * discard all the pieces. 2142 */ 2143 if (sc->rl_head != NULL) { 2144 m_freem(sc->rl_head); 2145 sc->rl_head = sc->rl_tail = NULL; 2146 } 2147 re_discard_rxbuf(sc, i); 2148 continue; 2149 } 2150 m->m_len = RE_RX_DESC_BUFLEN; 2151 if (sc->rl_head == NULL) 2152 sc->rl_head = sc->rl_tail = m; 2153 else { 2154 m->m_flags &= ~M_PKTHDR; 2155 sc->rl_tail->m_next = m; 2156 sc->rl_tail = m; 2157 } 2158 continue; 2159 } 2160 2161 /* 2162 * NOTE: for the 8139C+, the frame length field 2163 * is always 12 bits in size, but for the gigE chips, 2164 * it is 13 bits (since the max RX frame length is 16K). 2165 * Unfortunately, all 32 bits in the status word 2166 * were already used, so to make room for the extra 2167 * length bit, RealTek took out the 'frame alignment 2168 * error' bit and shifted the other status bits 2169 * over one slot. The OWN, EOR, FS and LS bits are 2170 * still in the same places. We have already extracted 2171 * the frame length and checked the OWN bit, so rather 2172 * than using an alternate bit mapping, we shift the 2173 * status bits one space to the right so we can evaluate 2174 * them using the 8169 status as though it was in the 2175 * same format as that of the 8139C+. 2176 */ 2177 if (sc->rl_type == RL_8169) 2178 rxstat >>= 1; 2179 2180 /* 2181 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 2182 * set, but if CRC is clear, it will still be a valid frame. 2183 */ 2184 if ((rxstat & RL_RDESC_STAT_RXERRSUM) != 0) { 2185 rxerr = 1; 2186 if ((sc->rl_flags & RL_FLAG_JUMBOV2) == 0 && 2187 total_len > 8191 && 2188 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT) 2189 rxerr = 0; 2190 if (rxerr != 0) { 2191 ifp->if_ierrors++; 2192 /* 2193 * If this is part of a multi-fragment packet, 2194 * discard all the pieces. 2195 */ 2196 if (sc->rl_head != NULL) { 2197 m_freem(sc->rl_head); 2198 sc->rl_head = sc->rl_tail = NULL; 2199 } 2200 re_discard_rxbuf(sc, i); 2201 continue; 2202 } 2203 } 2204 2205 /* 2206 * If allocating a replacement mbuf fails, 2207 * reload the current one. 2208 */ 2209 if (jumbo != 0) 2210 rxerr = re_jumbo_newbuf(sc, i); 2211 else 2212 rxerr = re_newbuf(sc, i); 2213 if (rxerr != 0) { 2214 ifp->if_iqdrops++; 2215 if (sc->rl_head != NULL) { 2216 m_freem(sc->rl_head); 2217 sc->rl_head = sc->rl_tail = NULL; 2218 } 2219 re_discard_rxbuf(sc, i); 2220 continue; 2221 } 2222 2223 if (sc->rl_head != NULL) { 2224 if (jumbo != 0) 2225 m->m_len = total_len; 2226 else { 2227 m->m_len = total_len % RE_RX_DESC_BUFLEN; 2228 if (m->m_len == 0) 2229 m->m_len = RE_RX_DESC_BUFLEN; 2230 } 2231 /* 2232 * Special case: if there's 4 bytes or less 2233 * in this buffer, the mbuf can be discarded: 2234 * the last 4 bytes is the CRC, which we don't 2235 * care about anyway. 2236 */ 2237 if (m->m_len <= ETHER_CRC_LEN) { 2238 sc->rl_tail->m_len -= 2239 (ETHER_CRC_LEN - m->m_len); 2240 m_freem(m); 2241 } else { 2242 m->m_len -= ETHER_CRC_LEN; 2243 m->m_flags &= ~M_PKTHDR; 2244 sc->rl_tail->m_next = m; 2245 } 2246 m = sc->rl_head; 2247 sc->rl_head = sc->rl_tail = NULL; 2248 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 2249 } else 2250 m->m_pkthdr.len = m->m_len = 2251 (total_len - ETHER_CRC_LEN); 2252 2253 #ifdef RE_FIXUP_RX 2254 re_fixup_rx(m); 2255 #endif 2256 ifp->if_ipackets++; 2257 m->m_pkthdr.rcvif = ifp; 2258 2259 /* Do RX checksumming if enabled */ 2260 2261 if (ifp->if_capenable & IFCAP_RXCSUM) { 2262 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2263 /* Check IP header checksum */ 2264 if (rxstat & RL_RDESC_STAT_PROTOID) 2265 m->m_pkthdr.csum_flags |= 2266 CSUM_IP_CHECKED; 2267 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 2268 m->m_pkthdr.csum_flags |= 2269 CSUM_IP_VALID; 2270 2271 /* Check TCP/UDP checksum */ 2272 if ((RL_TCPPKT(rxstat) && 2273 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 2274 (RL_UDPPKT(rxstat) && 2275 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 2276 m->m_pkthdr.csum_flags |= 2277 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2278 m->m_pkthdr.csum_data = 0xffff; 2279 } 2280 } else { 2281 /* 2282 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP 2283 */ 2284 if ((rxstat & RL_RDESC_STAT_PROTOID) && 2285 (rxvlan & RL_RDESC_IPV4)) 2286 m->m_pkthdr.csum_flags |= 2287 CSUM_IP_CHECKED; 2288 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) && 2289 (rxvlan & RL_RDESC_IPV4)) 2290 m->m_pkthdr.csum_flags |= 2291 CSUM_IP_VALID; 2292 if (((rxstat & RL_RDESC_STAT_TCP) && 2293 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 2294 ((rxstat & RL_RDESC_STAT_UDP) && 2295 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 2296 m->m_pkthdr.csum_flags |= 2297 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2298 m->m_pkthdr.csum_data = 0xffff; 2299 } 2300 } 2301 } 2302 maxpkt--; 2303 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 2304 m->m_pkthdr.ether_vtag = 2305 bswap16((rxvlan & RL_RDESC_VLANCTL_DATA)); 2306 m->m_flags |= M_VLANTAG; 2307 } 2308 RL_UNLOCK(sc); 2309 (*ifp->if_input)(ifp, m); 2310 RL_LOCK(sc); 2311 rx_npkts++; 2312 } 2313 2314 /* Flush the RX DMA ring */ 2315 2316 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2317 sc->rl_ldata.rl_rx_list_map, 2318 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2319 2320 sc->rl_ldata.rl_rx_prodidx = i; 2321 2322 if (rx_npktsp != NULL) 2323 *rx_npktsp = rx_npkts; 2324 if (maxpkt) 2325 return (EAGAIN); 2326 2327 return (0); 2328 } 2329 2330 static void 2331 re_txeof(struct rl_softc *sc) 2332 { 2333 struct ifnet *ifp; 2334 struct rl_txdesc *txd; 2335 u_int32_t txstat; 2336 int cons; 2337 2338 cons = sc->rl_ldata.rl_tx_considx; 2339 if (cons == sc->rl_ldata.rl_tx_prodidx) 2340 return; 2341 2342 ifp = sc->rl_ifp; 2343 #ifdef DEV_NETMAP 2344 if (ifp->if_capenable & IFCAP_NETMAP) { 2345 selwakeuppri(&NA(ifp)->tx_rings[0].si, PI_NET); 2346 return; 2347 } 2348 #endif /* DEV_NETMAP */ 2349 /* Invalidate the TX descriptor list */ 2350 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2351 sc->rl_ldata.rl_tx_list_map, 2352 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2353 2354 for (; cons != sc->rl_ldata.rl_tx_prodidx; 2355 cons = RL_TX_DESC_NXT(sc, cons)) { 2356 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 2357 if (txstat & RL_TDESC_STAT_OWN) 2358 break; 2359 /* 2360 * We only stash mbufs in the last descriptor 2361 * in a fragment chain, which also happens to 2362 * be the only place where the TX status bits 2363 * are valid. 2364 */ 2365 if (txstat & RL_TDESC_CMD_EOF) { 2366 txd = &sc->rl_ldata.rl_tx_desc[cons]; 2367 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2368 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2369 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2370 txd->tx_dmamap); 2371 KASSERT(txd->tx_m != NULL, 2372 ("%s: freeing NULL mbufs!", __func__)); 2373 m_freem(txd->tx_m); 2374 txd->tx_m = NULL; 2375 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 2376 RL_TDESC_STAT_COLCNT)) 2377 ifp->if_collisions++; 2378 if (txstat & RL_TDESC_STAT_TXERRSUM) 2379 ifp->if_oerrors++; 2380 else 2381 ifp->if_opackets++; 2382 } 2383 sc->rl_ldata.rl_tx_free++; 2384 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2385 } 2386 sc->rl_ldata.rl_tx_considx = cons; 2387 2388 /* No changes made to the TX ring, so no flush needed */ 2389 2390 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 2391 #ifdef RE_TX_MODERATION 2392 /* 2393 * If not all descriptors have been reaped yet, reload 2394 * the timer so that we will eventually get another 2395 * interrupt that will cause us to re-enter this routine. 2396 * This is done in case the transmitter has gone idle. 2397 */ 2398 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2399 #endif 2400 } else 2401 sc->rl_watchdog_timer = 0; 2402 } 2403 2404 static void 2405 re_tick(void *xsc) 2406 { 2407 struct rl_softc *sc; 2408 struct mii_data *mii; 2409 2410 sc = xsc; 2411 2412 RL_LOCK_ASSERT(sc); 2413 2414 mii = device_get_softc(sc->rl_miibus); 2415 mii_tick(mii); 2416 if ((sc->rl_flags & RL_FLAG_LINK) == 0) 2417 re_miibus_statchg(sc->rl_dev); 2418 /* 2419 * Reclaim transmitted frames here. Technically it is not 2420 * necessary to do here but it ensures periodic reclamation 2421 * regardless of Tx completion interrupt which seems to be 2422 * lost on PCIe based controllers under certain situations. 2423 */ 2424 re_txeof(sc); 2425 re_watchdog(sc); 2426 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2427 } 2428 2429 #ifdef DEVICE_POLLING 2430 static int 2431 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2432 { 2433 struct rl_softc *sc = ifp->if_softc; 2434 int rx_npkts = 0; 2435 2436 RL_LOCK(sc); 2437 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2438 rx_npkts = re_poll_locked(ifp, cmd, count); 2439 RL_UNLOCK(sc); 2440 return (rx_npkts); 2441 } 2442 2443 static int 2444 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2445 { 2446 struct rl_softc *sc = ifp->if_softc; 2447 int rx_npkts; 2448 2449 RL_LOCK_ASSERT(sc); 2450 2451 sc->rxcycles = count; 2452 re_rxeof(sc, &rx_npkts); 2453 re_txeof(sc); 2454 2455 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2456 re_start_locked(ifp); 2457 2458 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2459 u_int16_t status; 2460 2461 status = CSR_READ_2(sc, RL_ISR); 2462 if (status == 0xffff) 2463 return (rx_npkts); 2464 if (status) 2465 CSR_WRITE_2(sc, RL_ISR, status); 2466 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2467 (sc->rl_flags & RL_FLAG_PCIE)) 2468 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2469 2470 /* 2471 * XXX check behaviour on receiver stalls. 2472 */ 2473 2474 if (status & RL_ISR_SYSTEM_ERR) { 2475 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2476 re_init_locked(sc); 2477 } 2478 } 2479 return (rx_npkts); 2480 } 2481 #endif /* DEVICE_POLLING */ 2482 2483 static int 2484 re_intr(void *arg) 2485 { 2486 struct rl_softc *sc; 2487 uint16_t status; 2488 2489 sc = arg; 2490 2491 status = CSR_READ_2(sc, RL_ISR); 2492 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2493 return (FILTER_STRAY); 2494 CSR_WRITE_2(sc, RL_IMR, 0); 2495 2496 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2497 2498 return (FILTER_HANDLED); 2499 } 2500 2501 static void 2502 re_int_task(void *arg, int npending) 2503 { 2504 struct rl_softc *sc; 2505 struct ifnet *ifp; 2506 u_int16_t status; 2507 int rval = 0; 2508 2509 sc = arg; 2510 ifp = sc->rl_ifp; 2511 2512 RL_LOCK(sc); 2513 2514 status = CSR_READ_2(sc, RL_ISR); 2515 CSR_WRITE_2(sc, RL_ISR, status); 2516 2517 if (sc->suspended || 2518 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2519 RL_UNLOCK(sc); 2520 return; 2521 } 2522 2523 #ifdef DEVICE_POLLING 2524 if (ifp->if_capenable & IFCAP_POLLING) { 2525 RL_UNLOCK(sc); 2526 return; 2527 } 2528 #endif 2529 2530 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2531 rval = re_rxeof(sc, NULL); 2532 2533 /* 2534 * Some chips will ignore a second TX request issued 2535 * while an existing transmission is in progress. If 2536 * the transmitter goes idle but there are still 2537 * packets waiting to be sent, we need to restart the 2538 * channel here to flush them out. This only seems to 2539 * be required with the PCIe devices. 2540 */ 2541 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2542 (sc->rl_flags & RL_FLAG_PCIE)) 2543 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2544 if (status & ( 2545 #ifdef RE_TX_MODERATION 2546 RL_ISR_TIMEOUT_EXPIRED| 2547 #else 2548 RL_ISR_TX_OK| 2549 #endif 2550 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2551 re_txeof(sc); 2552 2553 if (status & RL_ISR_SYSTEM_ERR) { 2554 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2555 re_init_locked(sc); 2556 } 2557 2558 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2559 re_start_locked(ifp); 2560 2561 RL_UNLOCK(sc); 2562 2563 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2564 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2565 return; 2566 } 2567 2568 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2569 } 2570 2571 static void 2572 re_intr_msi(void *xsc) 2573 { 2574 struct rl_softc *sc; 2575 struct ifnet *ifp; 2576 uint16_t intrs, status; 2577 2578 sc = xsc; 2579 RL_LOCK(sc); 2580 2581 ifp = sc->rl_ifp; 2582 #ifdef DEVICE_POLLING 2583 if (ifp->if_capenable & IFCAP_POLLING) { 2584 RL_UNLOCK(sc); 2585 return; 2586 } 2587 #endif 2588 /* Disable interrupts. */ 2589 CSR_WRITE_2(sc, RL_IMR, 0); 2590 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2591 RL_UNLOCK(sc); 2592 return; 2593 } 2594 2595 intrs = RL_INTRS_CPLUS; 2596 status = CSR_READ_2(sc, RL_ISR); 2597 CSR_WRITE_2(sc, RL_ISR, status); 2598 if (sc->rl_int_rx_act > 0) { 2599 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW | 2600 RL_ISR_RX_OVERRUN); 2601 status &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW | 2602 RL_ISR_RX_OVERRUN); 2603 } 2604 2605 if (status & (RL_ISR_TIMEOUT_EXPIRED | RL_ISR_RX_OK | RL_ISR_RX_ERR | 2606 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) { 2607 re_rxeof(sc, NULL); 2608 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2609 if (sc->rl_int_rx_mod != 0 && 2610 (status & (RL_ISR_RX_OK | RL_ISR_RX_ERR | 2611 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) != 0) { 2612 /* Rearm one-shot timer. */ 2613 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2614 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | 2615 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN); 2616 sc->rl_int_rx_act = 1; 2617 } else { 2618 intrs |= RL_ISR_RX_OK | RL_ISR_RX_ERR | 2619 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN; 2620 sc->rl_int_rx_act = 0; 2621 } 2622 } 2623 } 2624 2625 /* 2626 * Some chips will ignore a second TX request issued 2627 * while an existing transmission is in progress. If 2628 * the transmitter goes idle but there are still 2629 * packets waiting to be sent, we need to restart the 2630 * channel here to flush them out. This only seems to 2631 * be required with the PCIe devices. 2632 */ 2633 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2634 (sc->rl_flags & RL_FLAG_PCIE)) 2635 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2636 if (status & (RL_ISR_TX_OK | RL_ISR_TX_ERR | RL_ISR_TX_DESC_UNAVAIL)) 2637 re_txeof(sc); 2638 2639 if (status & RL_ISR_SYSTEM_ERR) { 2640 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2641 re_init_locked(sc); 2642 } 2643 2644 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2645 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2646 re_start_locked(ifp); 2647 CSR_WRITE_2(sc, RL_IMR, intrs); 2648 } 2649 RL_UNLOCK(sc); 2650 } 2651 2652 static int 2653 re_encap(struct rl_softc *sc, struct mbuf **m_head) 2654 { 2655 struct rl_txdesc *txd, *txd_last; 2656 bus_dma_segment_t segs[RL_NTXSEGS]; 2657 bus_dmamap_t map; 2658 struct mbuf *m_new; 2659 struct rl_desc *desc; 2660 int nsegs, prod; 2661 int i, error, ei, si; 2662 int padlen; 2663 uint32_t cmdstat, csum_flags, vlanctl; 2664 2665 RL_LOCK_ASSERT(sc); 2666 M_ASSERTPKTHDR((*m_head)); 2667 2668 /* 2669 * With some of the RealTek chips, using the checksum offload 2670 * support in conjunction with the autopadding feature results 2671 * in the transmission of corrupt frames. For example, if we 2672 * need to send a really small IP fragment that's less than 60 2673 * bytes in size, and IP header checksumming is enabled, the 2674 * resulting ethernet frame that appears on the wire will 2675 * have garbled payload. To work around this, if TX IP checksum 2676 * offload is enabled, we always manually pad short frames out 2677 * to the minimum ethernet frame size. 2678 */ 2679 if ((sc->rl_flags & RL_FLAG_AUTOPAD) == 0 && 2680 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN && 2681 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) { 2682 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2683 if (M_WRITABLE(*m_head) == 0) { 2684 /* Get a writable copy. */ 2685 m_new = m_dup(*m_head, M_DONTWAIT); 2686 m_freem(*m_head); 2687 if (m_new == NULL) { 2688 *m_head = NULL; 2689 return (ENOBUFS); 2690 } 2691 *m_head = m_new; 2692 } 2693 if ((*m_head)->m_next != NULL || 2694 M_TRAILINGSPACE(*m_head) < padlen) { 2695 m_new = m_defrag(*m_head, M_DONTWAIT); 2696 if (m_new == NULL) { 2697 m_freem(*m_head); 2698 *m_head = NULL; 2699 return (ENOBUFS); 2700 } 2701 } else 2702 m_new = *m_head; 2703 2704 /* 2705 * Manually pad short frames, and zero the pad space 2706 * to avoid leaking data. 2707 */ 2708 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2709 m_new->m_pkthdr.len += padlen; 2710 m_new->m_len = m_new->m_pkthdr.len; 2711 *m_head = m_new; 2712 } 2713 2714 prod = sc->rl_ldata.rl_tx_prodidx; 2715 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2716 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2717 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2718 if (error == EFBIG) { 2719 m_new = m_collapse(*m_head, M_DONTWAIT, RL_NTXSEGS); 2720 if (m_new == NULL) { 2721 m_freem(*m_head); 2722 *m_head = NULL; 2723 return (ENOBUFS); 2724 } 2725 *m_head = m_new; 2726 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2727 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2728 if (error != 0) { 2729 m_freem(*m_head); 2730 *m_head = NULL; 2731 return (error); 2732 } 2733 } else if (error != 0) 2734 return (error); 2735 if (nsegs == 0) { 2736 m_freem(*m_head); 2737 *m_head = NULL; 2738 return (EIO); 2739 } 2740 2741 /* Check for number of available descriptors. */ 2742 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2743 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2744 return (ENOBUFS); 2745 } 2746 2747 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2748 BUS_DMASYNC_PREWRITE); 2749 2750 /* 2751 * Set up checksum offload. Note: checksum offload bits must 2752 * appear in all descriptors of a multi-descriptor transmit 2753 * attempt. This is according to testing done with an 8169 2754 * chip. This is a requirement. 2755 */ 2756 vlanctl = 0; 2757 csum_flags = 0; 2758 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2759 if ((sc->rl_flags & RL_FLAG_DESCV2) != 0) { 2760 csum_flags |= RL_TDESC_CMD_LGSEND; 2761 vlanctl |= ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2762 RL_TDESC_CMD_MSSVALV2_SHIFT); 2763 } else { 2764 csum_flags |= RL_TDESC_CMD_LGSEND | 2765 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2766 RL_TDESC_CMD_MSSVAL_SHIFT); 2767 } 2768 } else { 2769 /* 2770 * Unconditionally enable IP checksum if TCP or UDP 2771 * checksum is required. Otherwise, TCP/UDP checksum 2772 * does't make effects. 2773 */ 2774 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) { 2775 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2776 csum_flags |= RL_TDESC_CMD_IPCSUM; 2777 if (((*m_head)->m_pkthdr.csum_flags & 2778 CSUM_TCP) != 0) 2779 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2780 if (((*m_head)->m_pkthdr.csum_flags & 2781 CSUM_UDP) != 0) 2782 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2783 } else { 2784 vlanctl |= RL_TDESC_CMD_IPCSUMV2; 2785 if (((*m_head)->m_pkthdr.csum_flags & 2786 CSUM_TCP) != 0) 2787 vlanctl |= RL_TDESC_CMD_TCPCSUMV2; 2788 if (((*m_head)->m_pkthdr.csum_flags & 2789 CSUM_UDP) != 0) 2790 vlanctl |= RL_TDESC_CMD_UDPCSUMV2; 2791 } 2792 } 2793 } 2794 2795 /* 2796 * Set up hardware VLAN tagging. Note: vlan tag info must 2797 * appear in all descriptors of a multi-descriptor 2798 * transmission attempt. 2799 */ 2800 if ((*m_head)->m_flags & M_VLANTAG) 2801 vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) | 2802 RL_TDESC_VLANCTL_TAG; 2803 2804 si = prod; 2805 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2806 desc = &sc->rl_ldata.rl_tx_list[prod]; 2807 desc->rl_vlanctl = htole32(vlanctl); 2808 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2809 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2810 cmdstat = segs[i].ds_len; 2811 if (i != 0) 2812 cmdstat |= RL_TDESC_CMD_OWN; 2813 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2814 cmdstat |= RL_TDESC_CMD_EOR; 2815 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2816 sc->rl_ldata.rl_tx_free--; 2817 } 2818 /* Update producer index. */ 2819 sc->rl_ldata.rl_tx_prodidx = prod; 2820 2821 /* Set EOF on the last descriptor. */ 2822 ei = RL_TX_DESC_PRV(sc, prod); 2823 desc = &sc->rl_ldata.rl_tx_list[ei]; 2824 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2825 2826 desc = &sc->rl_ldata.rl_tx_list[si]; 2827 /* Set SOF and transfer ownership of packet to the chip. */ 2828 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2829 2830 /* 2831 * Insure that the map for this transmission 2832 * is placed at the array index of the last descriptor 2833 * in this chain. (Swap last and first dmamaps.) 2834 */ 2835 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2836 map = txd->tx_dmamap; 2837 txd->tx_dmamap = txd_last->tx_dmamap; 2838 txd_last->tx_dmamap = map; 2839 txd_last->tx_m = *m_head; 2840 2841 return (0); 2842 } 2843 2844 static void 2845 re_start(struct ifnet *ifp) 2846 { 2847 struct rl_softc *sc; 2848 2849 sc = ifp->if_softc; 2850 RL_LOCK(sc); 2851 re_start_locked(ifp); 2852 RL_UNLOCK(sc); 2853 } 2854 2855 /* 2856 * Main transmit routine for C+ and gigE NICs. 2857 */ 2858 static void 2859 re_start_locked(struct ifnet *ifp) 2860 { 2861 struct rl_softc *sc; 2862 struct mbuf *m_head; 2863 int queued; 2864 2865 sc = ifp->if_softc; 2866 2867 #ifdef DEV_NETMAP 2868 /* XXX is this necessary ? */ 2869 if (ifp->if_capenable & IFCAP_NETMAP) { 2870 struct netmap_kring *kring = &NA(ifp)->tx_rings[0]; 2871 if (sc->rl_ldata.rl_tx_prodidx != kring->nr_hwcur) { 2872 /* kick the tx unit */ 2873 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2874 #ifdef RE_TX_MODERATION 2875 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2876 #endif 2877 sc->rl_watchdog_timer = 5; 2878 } 2879 return; 2880 } 2881 #endif /* DEV_NETMAP */ 2882 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2883 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) 2884 return; 2885 2886 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2887 sc->rl_ldata.rl_tx_free > 1;) { 2888 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2889 if (m_head == NULL) 2890 break; 2891 2892 if (re_encap(sc, &m_head) != 0) { 2893 if (m_head == NULL) 2894 break; 2895 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2896 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2897 break; 2898 } 2899 2900 /* 2901 * If there's a BPF listener, bounce a copy of this frame 2902 * to him. 2903 */ 2904 ETHER_BPF_MTAP(ifp, m_head); 2905 2906 queued++; 2907 } 2908 2909 if (queued == 0) { 2910 #ifdef RE_TX_MODERATION 2911 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2912 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2913 #endif 2914 return; 2915 } 2916 2917 /* Flush the TX descriptors */ 2918 2919 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2920 sc->rl_ldata.rl_tx_list_map, 2921 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2922 2923 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2924 2925 #ifdef RE_TX_MODERATION 2926 /* 2927 * Use the countdown timer for interrupt moderation. 2928 * 'TX done' interrupts are disabled. Instead, we reset the 2929 * countdown timer, which will begin counting until it hits 2930 * the value in the TIMERINT register, and then trigger an 2931 * interrupt. Each time we write to the TIMERCNT register, 2932 * the timer count is reset to 0. 2933 */ 2934 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2935 #endif 2936 2937 /* 2938 * Set a timeout in case the chip goes out to lunch. 2939 */ 2940 sc->rl_watchdog_timer = 5; 2941 } 2942 2943 static void 2944 re_set_jumbo(struct rl_softc *sc, int jumbo) 2945 { 2946 2947 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168E_VL) { 2948 pci_set_max_read_req(sc->rl_dev, 4096); 2949 return; 2950 } 2951 2952 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2953 if (jumbo != 0) { 2954 CSR_WRITE_1(sc, RL_CFG3, CSR_READ_1(sc, RL_CFG3) | 2955 RL_CFG3_JUMBO_EN0); 2956 switch (sc->rl_hwrev->rl_rev) { 2957 case RL_HWREV_8168DP: 2958 break; 2959 case RL_HWREV_8168E: 2960 CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) | 2961 0x01); 2962 break; 2963 default: 2964 CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) | 2965 RL_CFG4_JUMBO_EN1); 2966 } 2967 } else { 2968 CSR_WRITE_1(sc, RL_CFG3, CSR_READ_1(sc, RL_CFG3) & 2969 ~RL_CFG3_JUMBO_EN0); 2970 switch (sc->rl_hwrev->rl_rev) { 2971 case RL_HWREV_8168DP: 2972 break; 2973 case RL_HWREV_8168E: 2974 CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) & 2975 ~0x01); 2976 break; 2977 default: 2978 CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) & 2979 ~RL_CFG4_JUMBO_EN1); 2980 } 2981 } 2982 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2983 2984 switch (sc->rl_hwrev->rl_rev) { 2985 case RL_HWREV_8168DP: 2986 pci_set_max_read_req(sc->rl_dev, 4096); 2987 break; 2988 default: 2989 if (jumbo != 0) 2990 pci_set_max_read_req(sc->rl_dev, 512); 2991 else 2992 pci_set_max_read_req(sc->rl_dev, 4096); 2993 } 2994 } 2995 2996 static void 2997 re_init(void *xsc) 2998 { 2999 struct rl_softc *sc = xsc; 3000 3001 RL_LOCK(sc); 3002 re_init_locked(sc); 3003 RL_UNLOCK(sc); 3004 } 3005 3006 static void 3007 re_init_locked(struct rl_softc *sc) 3008 { 3009 struct ifnet *ifp = sc->rl_ifp; 3010 struct mii_data *mii; 3011 uint32_t reg; 3012 uint16_t cfg; 3013 union { 3014 uint32_t align_dummy; 3015 u_char eaddr[ETHER_ADDR_LEN]; 3016 } eaddr; 3017 3018 RL_LOCK_ASSERT(sc); 3019 3020 mii = device_get_softc(sc->rl_miibus); 3021 3022 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3023 return; 3024 3025 /* 3026 * Cancel pending I/O and free all RX/TX buffers. 3027 */ 3028 re_stop(sc); 3029 3030 /* Put controller into known state. */ 3031 re_reset(sc); 3032 3033 /* 3034 * For C+ mode, initialize the RX descriptors and mbufs. 3035 */ 3036 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3037 if (ifp->if_mtu > RL_MTU) { 3038 if (re_jrx_list_init(sc) != 0) { 3039 device_printf(sc->rl_dev, 3040 "no memory for jumbo RX buffers\n"); 3041 re_stop(sc); 3042 return; 3043 } 3044 /* Disable checksum offloading for jumbo frames. */ 3045 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_TSO4); 3046 ifp->if_hwassist &= ~(RE_CSUM_FEATURES | CSUM_TSO); 3047 } else { 3048 if (re_rx_list_init(sc) != 0) { 3049 device_printf(sc->rl_dev, 3050 "no memory for RX buffers\n"); 3051 re_stop(sc); 3052 return; 3053 } 3054 } 3055 re_set_jumbo(sc, ifp->if_mtu > RL_MTU); 3056 } else { 3057 if (re_rx_list_init(sc) != 0) { 3058 device_printf(sc->rl_dev, "no memory for RX buffers\n"); 3059 re_stop(sc); 3060 return; 3061 } 3062 if ((sc->rl_flags & RL_FLAG_PCIE) != 0 && 3063 pci_get_device(sc->rl_dev) != RT_DEVICEID_8101E) { 3064 if (ifp->if_mtu > RL_MTU) 3065 pci_set_max_read_req(sc->rl_dev, 512); 3066 else 3067 pci_set_max_read_req(sc->rl_dev, 4096); 3068 } 3069 } 3070 re_tx_list_init(sc); 3071 3072 /* 3073 * Enable C+ RX and TX mode, as well as VLAN stripping and 3074 * RX checksum offload. We must configure the C+ register 3075 * before all others. 3076 */ 3077 cfg = RL_CPLUSCMD_PCI_MRW; 3078 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 3079 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 3080 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3081 cfg |= RL_CPLUSCMD_VLANSTRIP; 3082 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) { 3083 cfg |= RL_CPLUSCMD_MACSTAT_DIS; 3084 /* XXX magic. */ 3085 cfg |= 0x0001; 3086 } else 3087 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB; 3088 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg); 3089 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SC || 3090 sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) { 3091 reg = 0x000fff00; 3092 if ((CSR_READ_1(sc, RL_CFG2) & RL_CFG2_PCI66MHZ) != 0) 3093 reg |= 0x000000ff; 3094 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) 3095 reg |= 0x00f00000; 3096 CSR_WRITE_4(sc, 0x7c, reg); 3097 /* Disable interrupt mitigation. */ 3098 CSR_WRITE_2(sc, 0xe2, 0); 3099 } 3100 /* 3101 * Disable TSO if interface MTU size is greater than MSS 3102 * allowed in controller. 3103 */ 3104 if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) { 3105 ifp->if_capenable &= ~IFCAP_TSO4; 3106 ifp->if_hwassist &= ~CSUM_TSO; 3107 } 3108 3109 /* 3110 * Init our MAC address. Even though the chipset 3111 * documentation doesn't mention it, we need to enter "Config 3112 * register write enable" mode to modify the ID registers. 3113 */ 3114 /* Copy MAC address on stack to align. */ 3115 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 3116 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 3117 CSR_WRITE_4(sc, RL_IDR0, 3118 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 3119 CSR_WRITE_4(sc, RL_IDR4, 3120 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 3121 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3122 3123 /* 3124 * Load the addresses of the RX and TX lists into the chip. 3125 */ 3126 3127 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 3128 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 3129 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 3130 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 3131 3132 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 3133 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 3134 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 3135 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 3136 3137 /* 3138 * Enable transmit and receive. 3139 */ 3140 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 3141 3142 /* 3143 * Set the initial TX configuration. 3144 */ 3145 if (sc->rl_testmode) { 3146 if (sc->rl_type == RL_8169) 3147 CSR_WRITE_4(sc, RL_TXCFG, 3148 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 3149 else 3150 CSR_WRITE_4(sc, RL_TXCFG, 3151 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 3152 } else 3153 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 3154 3155 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 3156 3157 /* 3158 * Set the initial RX configuration. 3159 */ 3160 re_set_rxmode(sc); 3161 3162 /* Configure interrupt moderation. */ 3163 if (sc->rl_type == RL_8169) { 3164 /* Magic from vendor. */ 3165 CSR_WRITE_2(sc, RL_INTRMOD, 0x5100); 3166 } 3167 3168 #ifdef DEVICE_POLLING 3169 /* 3170 * Disable interrupts if we are polling. 3171 */ 3172 if (ifp->if_capenable & IFCAP_POLLING) 3173 CSR_WRITE_2(sc, RL_IMR, 0); 3174 else /* otherwise ... */ 3175 #endif 3176 3177 /* 3178 * Enable interrupts. 3179 */ 3180 if (sc->rl_testmode) 3181 CSR_WRITE_2(sc, RL_IMR, 0); 3182 else 3183 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 3184 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 3185 3186 /* Set initial TX threshold */ 3187 sc->rl_txthresh = RL_TX_THRESH_INIT; 3188 3189 /* Start RX/TX process. */ 3190 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 3191 #ifdef notdef 3192 /* Enable receiver and transmitter. */ 3193 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 3194 #endif 3195 3196 /* 3197 * Initialize the timer interrupt register so that 3198 * a timer interrupt will be generated once the timer 3199 * reaches a certain number of ticks. The timer is 3200 * reloaded on each transmit. 3201 */ 3202 #ifdef RE_TX_MODERATION 3203 /* 3204 * Use timer interrupt register to moderate TX interrupt 3205 * moderation, which dramatically improves TX frame rate. 3206 */ 3207 if (sc->rl_type == RL_8169) 3208 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 3209 else 3210 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 3211 #else 3212 /* 3213 * Use timer interrupt register to moderate RX interrupt 3214 * moderation. 3215 */ 3216 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 && 3217 intr_filter == 0) { 3218 if (sc->rl_type == RL_8169) 3219 CSR_WRITE_4(sc, RL_TIMERINT_8169, 3220 RL_USECS(sc->rl_int_rx_mod)); 3221 } else { 3222 if (sc->rl_type == RL_8169) 3223 CSR_WRITE_4(sc, RL_TIMERINT_8169, RL_USECS(0)); 3224 } 3225 #endif 3226 3227 /* 3228 * For 8169 gigE NICs, set the max allowed RX packet 3229 * size so we can receive jumbo frames. 3230 */ 3231 if (sc->rl_type == RL_8169) { 3232 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3233 /* 3234 * For controllers that use new jumbo frame scheme, 3235 * set maximum size of jumbo frame depedning on 3236 * controller revisions. 3237 */ 3238 if (ifp->if_mtu > RL_MTU) 3239 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 3240 sc->rl_hwrev->rl_max_mtu + 3241 ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN + 3242 ETHER_CRC_LEN); 3243 else 3244 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 3245 RE_RX_DESC_BUFLEN); 3246 } else if ((sc->rl_flags & RL_FLAG_PCIE) != 0 && 3247 sc->rl_hwrev->rl_max_mtu == RL_MTU) { 3248 /* RTL810x has no jumbo frame support. */ 3249 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, RE_RX_DESC_BUFLEN); 3250 } else 3251 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 3252 } 3253 3254 if (sc->rl_testmode) 3255 return; 3256 3257 CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD); 3258 3259 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3260 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3261 3262 sc->rl_flags &= ~RL_FLAG_LINK; 3263 mii_mediachg(mii); 3264 3265 sc->rl_watchdog_timer = 0; 3266 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 3267 } 3268 3269 /* 3270 * Set media options. 3271 */ 3272 static int 3273 re_ifmedia_upd(struct ifnet *ifp) 3274 { 3275 struct rl_softc *sc; 3276 struct mii_data *mii; 3277 int error; 3278 3279 sc = ifp->if_softc; 3280 mii = device_get_softc(sc->rl_miibus); 3281 RL_LOCK(sc); 3282 error = mii_mediachg(mii); 3283 RL_UNLOCK(sc); 3284 3285 return (error); 3286 } 3287 3288 /* 3289 * Report current media status. 3290 */ 3291 static void 3292 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3293 { 3294 struct rl_softc *sc; 3295 struct mii_data *mii; 3296 3297 sc = ifp->if_softc; 3298 mii = device_get_softc(sc->rl_miibus); 3299 3300 RL_LOCK(sc); 3301 mii_pollstat(mii); 3302 ifmr->ifm_active = mii->mii_media_active; 3303 ifmr->ifm_status = mii->mii_media_status; 3304 RL_UNLOCK(sc); 3305 } 3306 3307 static int 3308 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3309 { 3310 struct rl_softc *sc = ifp->if_softc; 3311 struct ifreq *ifr = (struct ifreq *) data; 3312 struct mii_data *mii; 3313 uint32_t rev; 3314 int error = 0; 3315 3316 switch (command) { 3317 case SIOCSIFMTU: 3318 if (ifr->ifr_mtu < ETHERMIN || 3319 ifr->ifr_mtu > sc->rl_hwrev->rl_max_mtu) { 3320 error = EINVAL; 3321 break; 3322 } 3323 RL_LOCK(sc); 3324 if (ifp->if_mtu != ifr->ifr_mtu) { 3325 ifp->if_mtu = ifr->ifr_mtu; 3326 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 3327 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3328 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3329 re_init_locked(sc); 3330 } 3331 if (ifp->if_mtu > RL_TSO_MTU && 3332 (ifp->if_capenable & IFCAP_TSO4) != 0) { 3333 ifp->if_capenable &= ~(IFCAP_TSO4 | 3334 IFCAP_VLAN_HWTSO); 3335 ifp->if_hwassist &= ~CSUM_TSO; 3336 } 3337 VLAN_CAPABILITIES(ifp); 3338 } 3339 RL_UNLOCK(sc); 3340 break; 3341 case SIOCSIFFLAGS: 3342 RL_LOCK(sc); 3343 if ((ifp->if_flags & IFF_UP) != 0) { 3344 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3345 if (((ifp->if_flags ^ sc->rl_if_flags) 3346 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 3347 re_set_rxmode(sc); 3348 } else 3349 re_init_locked(sc); 3350 } else { 3351 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3352 re_stop(sc); 3353 } 3354 sc->rl_if_flags = ifp->if_flags; 3355 RL_UNLOCK(sc); 3356 break; 3357 case SIOCADDMULTI: 3358 case SIOCDELMULTI: 3359 RL_LOCK(sc); 3360 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3361 re_set_rxmode(sc); 3362 RL_UNLOCK(sc); 3363 break; 3364 case SIOCGIFMEDIA: 3365 case SIOCSIFMEDIA: 3366 mii = device_get_softc(sc->rl_miibus); 3367 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3368 break; 3369 case SIOCSIFCAP: 3370 { 3371 int mask, reinit; 3372 3373 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3374 reinit = 0; 3375 #ifdef DEVICE_POLLING 3376 if (mask & IFCAP_POLLING) { 3377 if (ifr->ifr_reqcap & IFCAP_POLLING) { 3378 error = ether_poll_register(re_poll, ifp); 3379 if (error) 3380 return (error); 3381 RL_LOCK(sc); 3382 /* Disable interrupts */ 3383 CSR_WRITE_2(sc, RL_IMR, 0x0000); 3384 ifp->if_capenable |= IFCAP_POLLING; 3385 RL_UNLOCK(sc); 3386 } else { 3387 error = ether_poll_deregister(ifp); 3388 /* Enable interrupts. */ 3389 RL_LOCK(sc); 3390 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 3391 ifp->if_capenable &= ~IFCAP_POLLING; 3392 RL_UNLOCK(sc); 3393 } 3394 } 3395 #endif /* DEVICE_POLLING */ 3396 RL_LOCK(sc); 3397 if ((mask & IFCAP_TXCSUM) != 0 && 3398 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 3399 ifp->if_capenable ^= IFCAP_TXCSUM; 3400 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) { 3401 rev = sc->rl_hwrev->rl_rev; 3402 if (rev == RL_HWREV_8168C || 3403 rev == RL_HWREV_8168C_SPIN2) 3404 ifp->if_hwassist |= CSUM_TCP | CSUM_UDP; 3405 else 3406 ifp->if_hwassist |= RE_CSUM_FEATURES; 3407 } else 3408 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 3409 reinit = 1; 3410 } 3411 if ((mask & IFCAP_RXCSUM) != 0 && 3412 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 3413 ifp->if_capenable ^= IFCAP_RXCSUM; 3414 reinit = 1; 3415 } 3416 if ((mask & IFCAP_TSO4) != 0 && 3417 (ifp->if_capabilities & IFCAP_TSO) != 0) { 3418 ifp->if_capenable ^= IFCAP_TSO4; 3419 if ((IFCAP_TSO4 & ifp->if_capenable) != 0) 3420 ifp->if_hwassist |= CSUM_TSO; 3421 else 3422 ifp->if_hwassist &= ~CSUM_TSO; 3423 if (ifp->if_mtu > RL_TSO_MTU && 3424 (ifp->if_capenable & IFCAP_TSO4) != 0) { 3425 ifp->if_capenable &= ~IFCAP_TSO4; 3426 ifp->if_hwassist &= ~CSUM_TSO; 3427 } 3428 } 3429 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 3430 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 3431 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 3432 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3433 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 3434 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 3435 /* TSO over VLAN requires VLAN hardware tagging. */ 3436 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 3437 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 3438 reinit = 1; 3439 } 3440 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 3441 (mask & (IFCAP_HWCSUM | IFCAP_TSO4 | 3442 IFCAP_VLAN_HWTSO)) != 0) 3443 reinit = 1; 3444 if ((mask & IFCAP_WOL) != 0 && 3445 (ifp->if_capabilities & IFCAP_WOL) != 0) { 3446 if ((mask & IFCAP_WOL_UCAST) != 0) 3447 ifp->if_capenable ^= IFCAP_WOL_UCAST; 3448 if ((mask & IFCAP_WOL_MCAST) != 0) 3449 ifp->if_capenable ^= IFCAP_WOL_MCAST; 3450 if ((mask & IFCAP_WOL_MAGIC) != 0) 3451 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 3452 } 3453 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) { 3454 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3455 re_init_locked(sc); 3456 } 3457 RL_UNLOCK(sc); 3458 VLAN_CAPABILITIES(ifp); 3459 } 3460 break; 3461 default: 3462 error = ether_ioctl(ifp, command, data); 3463 break; 3464 } 3465 3466 return (error); 3467 } 3468 3469 static void 3470 re_watchdog(struct rl_softc *sc) 3471 { 3472 struct ifnet *ifp; 3473 3474 RL_LOCK_ASSERT(sc); 3475 3476 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 3477 return; 3478 3479 ifp = sc->rl_ifp; 3480 re_txeof(sc); 3481 if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) { 3482 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 3483 "-- recovering\n"); 3484 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3485 re_start_locked(ifp); 3486 return; 3487 } 3488 3489 if_printf(ifp, "watchdog timeout\n"); 3490 ifp->if_oerrors++; 3491 3492 re_rxeof(sc, NULL); 3493 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3494 re_init_locked(sc); 3495 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3496 re_start_locked(ifp); 3497 } 3498 3499 /* 3500 * Stop the adapter and free any mbufs allocated to the 3501 * RX and TX lists. 3502 */ 3503 static void 3504 re_stop(struct rl_softc *sc) 3505 { 3506 int i; 3507 struct ifnet *ifp; 3508 struct rl_txdesc *txd; 3509 struct rl_rxdesc *rxd; 3510 3511 RL_LOCK_ASSERT(sc); 3512 3513 ifp = sc->rl_ifp; 3514 3515 sc->rl_watchdog_timer = 0; 3516 callout_stop(&sc->rl_stat_callout); 3517 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3518 3519 /* 3520 * Disable accepting frames to put RX MAC into idle state. 3521 * Otherwise it's possible to get frames while stop command 3522 * execution is in progress and controller can DMA the frame 3523 * to already freed RX buffer during that period. 3524 */ 3525 CSR_WRITE_4(sc, RL_RXCFG, CSR_READ_4(sc, RL_RXCFG) & 3526 ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_MULTI | 3527 RL_RXCFG_RX_BROAD)); 3528 3529 if ((sc->rl_flags & RL_FLAG_WAIT_TXPOLL) != 0) { 3530 for (i = RL_TIMEOUT; i > 0; i--) { 3531 if ((CSR_READ_1(sc, sc->rl_txstart) & 3532 RL_TXSTART_START) == 0) 3533 break; 3534 DELAY(20); 3535 } 3536 if (i == 0) 3537 device_printf(sc->rl_dev, 3538 "stopping TX poll timed out!\n"); 3539 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 3540 } else if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0) { 3541 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB | 3542 RL_CMD_RX_ENB); 3543 if ((sc->rl_flags & RL_FLAG_CMDSTOP_WAIT_TXQ) != 0) { 3544 for (i = RL_TIMEOUT; i > 0; i--) { 3545 if ((CSR_READ_4(sc, RL_TXCFG) & 3546 RL_TXCFG_QUEUE_EMPTY) != 0) 3547 break; 3548 DELAY(100); 3549 } 3550 if (i == 0) 3551 device_printf(sc->rl_dev, 3552 "stopping TXQ timed out!\n"); 3553 } 3554 } else 3555 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 3556 DELAY(1000); 3557 CSR_WRITE_2(sc, RL_IMR, 0x0000); 3558 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 3559 3560 if (sc->rl_head != NULL) { 3561 m_freem(sc->rl_head); 3562 sc->rl_head = sc->rl_tail = NULL; 3563 } 3564 3565 /* Free the TX list buffers. */ 3566 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 3567 txd = &sc->rl_ldata.rl_tx_desc[i]; 3568 if (txd->tx_m != NULL) { 3569 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 3570 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3571 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 3572 txd->tx_dmamap); 3573 m_freem(txd->tx_m); 3574 txd->tx_m = NULL; 3575 } 3576 } 3577 3578 /* Free the RX list buffers. */ 3579 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 3580 rxd = &sc->rl_ldata.rl_rx_desc[i]; 3581 if (rxd->rx_m != NULL) { 3582 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 3583 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3584 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 3585 rxd->rx_dmamap); 3586 m_freem(rxd->rx_m); 3587 rxd->rx_m = NULL; 3588 } 3589 } 3590 3591 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3592 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 3593 rxd = &sc->rl_ldata.rl_jrx_desc[i]; 3594 if (rxd->rx_m != NULL) { 3595 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, 3596 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3597 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, 3598 rxd->rx_dmamap); 3599 m_freem(rxd->rx_m); 3600 rxd->rx_m = NULL; 3601 } 3602 } 3603 } 3604 } 3605 3606 /* 3607 * Device suspend routine. Stop the interface and save some PCI 3608 * settings in case the BIOS doesn't restore them properly on 3609 * resume. 3610 */ 3611 static int 3612 re_suspend(device_t dev) 3613 { 3614 struct rl_softc *sc; 3615 3616 sc = device_get_softc(dev); 3617 3618 RL_LOCK(sc); 3619 re_stop(sc); 3620 re_setwol(sc); 3621 sc->suspended = 1; 3622 RL_UNLOCK(sc); 3623 3624 return (0); 3625 } 3626 3627 /* 3628 * Device resume routine. Restore some PCI settings in case the BIOS 3629 * doesn't, re-enable busmastering, and restart the interface if 3630 * appropriate. 3631 */ 3632 static int 3633 re_resume(device_t dev) 3634 { 3635 struct rl_softc *sc; 3636 struct ifnet *ifp; 3637 3638 sc = device_get_softc(dev); 3639 3640 RL_LOCK(sc); 3641 3642 ifp = sc->rl_ifp; 3643 /* Take controller out of sleep mode. */ 3644 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3645 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3646 CSR_WRITE_1(sc, RL_GPIO, 3647 CSR_READ_1(sc, RL_GPIO) | 0x01); 3648 } 3649 3650 /* 3651 * Clear WOL matching such that normal Rx filtering 3652 * wouldn't interfere with WOL patterns. 3653 */ 3654 re_clrwol(sc); 3655 3656 /* reinitialize interface if necessary */ 3657 if (ifp->if_flags & IFF_UP) 3658 re_init_locked(sc); 3659 3660 sc->suspended = 0; 3661 RL_UNLOCK(sc); 3662 3663 return (0); 3664 } 3665 3666 /* 3667 * Stop all chip I/O so that the kernel's probe routines don't 3668 * get confused by errant DMAs when rebooting. 3669 */ 3670 static int 3671 re_shutdown(device_t dev) 3672 { 3673 struct rl_softc *sc; 3674 3675 sc = device_get_softc(dev); 3676 3677 RL_LOCK(sc); 3678 re_stop(sc); 3679 /* 3680 * Mark interface as down since otherwise we will panic if 3681 * interrupt comes in later on, which can happen in some 3682 * cases. 3683 */ 3684 sc->rl_ifp->if_flags &= ~IFF_UP; 3685 re_setwol(sc); 3686 RL_UNLOCK(sc); 3687 3688 return (0); 3689 } 3690 3691 static void 3692 re_set_linkspeed(struct rl_softc *sc) 3693 { 3694 struct mii_softc *miisc; 3695 struct mii_data *mii; 3696 int aneg, i, phyno; 3697 3698 RL_LOCK_ASSERT(sc); 3699 3700 mii = device_get_softc(sc->rl_miibus); 3701 mii_pollstat(mii); 3702 aneg = 0; 3703 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 3704 (IFM_ACTIVE | IFM_AVALID)) { 3705 switch IFM_SUBTYPE(mii->mii_media_active) { 3706 case IFM_10_T: 3707 case IFM_100_TX: 3708 return; 3709 case IFM_1000_T: 3710 aneg++; 3711 break; 3712 default: 3713 break; 3714 } 3715 } 3716 miisc = LIST_FIRST(&mii->mii_phys); 3717 phyno = miisc->mii_phy; 3718 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 3719 PHY_RESET(miisc); 3720 re_miibus_writereg(sc->rl_dev, phyno, MII_100T2CR, 0); 3721 re_miibus_writereg(sc->rl_dev, phyno, 3722 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 3723 re_miibus_writereg(sc->rl_dev, phyno, 3724 MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 3725 DELAY(1000); 3726 if (aneg != 0) { 3727 /* 3728 * Poll link state until re(4) get a 10/100Mbps link. 3729 */ 3730 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 3731 mii_pollstat(mii); 3732 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 3733 == (IFM_ACTIVE | IFM_AVALID)) { 3734 switch (IFM_SUBTYPE(mii->mii_media_active)) { 3735 case IFM_10_T: 3736 case IFM_100_TX: 3737 return; 3738 default: 3739 break; 3740 } 3741 } 3742 RL_UNLOCK(sc); 3743 pause("relnk", hz); 3744 RL_LOCK(sc); 3745 } 3746 if (i == MII_ANEGTICKS_GIGE) 3747 device_printf(sc->rl_dev, 3748 "establishing a link failed, WOL may not work!"); 3749 } 3750 /* 3751 * No link, force MAC to have 100Mbps, full-duplex link. 3752 * MAC does not require reprogramming on resolved speed/duplex, 3753 * so this is just for completeness. 3754 */ 3755 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 3756 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 3757 } 3758 3759 static void 3760 re_setwol(struct rl_softc *sc) 3761 { 3762 struct ifnet *ifp; 3763 int pmc; 3764 uint16_t pmstat; 3765 uint8_t v; 3766 3767 RL_LOCK_ASSERT(sc); 3768 3769 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3770 return; 3771 3772 ifp = sc->rl_ifp; 3773 /* Put controller into sleep mode. */ 3774 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3775 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3776 CSR_WRITE_1(sc, RL_GPIO, 3777 CSR_READ_1(sc, RL_GPIO) & ~0x01); 3778 } 3779 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 3780 re_set_rxmode(sc); 3781 if ((sc->rl_flags & RL_FLAG_WOL_MANLINK) != 0) 3782 re_set_linkspeed(sc); 3783 if ((sc->rl_flags & RL_FLAG_WOLRXENB) != 0) 3784 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB); 3785 } 3786 /* Enable config register write. */ 3787 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3788 3789 /* Enable PME. */ 3790 v = CSR_READ_1(sc, RL_CFG1); 3791 v &= ~RL_CFG1_PME; 3792 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3793 v |= RL_CFG1_PME; 3794 CSR_WRITE_1(sc, RL_CFG1, v); 3795 3796 v = CSR_READ_1(sc, RL_CFG3); 3797 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3798 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3799 v |= RL_CFG3_WOL_MAGIC; 3800 CSR_WRITE_1(sc, RL_CFG3, v); 3801 3802 v = CSR_READ_1(sc, RL_CFG5); 3803 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST | 3804 RL_CFG5_WOL_LANWAKE); 3805 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 3806 v |= RL_CFG5_WOL_UCAST; 3807 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 3808 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 3809 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3810 v |= RL_CFG5_WOL_LANWAKE; 3811 CSR_WRITE_1(sc, RL_CFG5, v); 3812 3813 /* Config register write done. */ 3814 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3815 3816 if ((ifp->if_capenable & IFCAP_WOL) == 0 && 3817 (sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) 3818 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) & ~0x80); 3819 /* 3820 * It seems that hardware resets its link speed to 100Mbps in 3821 * power down mode so switching to 100Mbps in driver is not 3822 * needed. 3823 */ 3824 3825 /* Request PME if WOL is requested. */ 3826 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 3827 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3828 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3829 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3830 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 3831 } 3832 3833 static void 3834 re_clrwol(struct rl_softc *sc) 3835 { 3836 int pmc; 3837 uint8_t v; 3838 3839 RL_LOCK_ASSERT(sc); 3840 3841 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3842 return; 3843 3844 /* Enable config register write. */ 3845 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3846 3847 v = CSR_READ_1(sc, RL_CFG3); 3848 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3849 CSR_WRITE_1(sc, RL_CFG3, v); 3850 3851 /* Config register write done. */ 3852 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3853 3854 v = CSR_READ_1(sc, RL_CFG5); 3855 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3856 v &= ~RL_CFG5_WOL_LANWAKE; 3857 CSR_WRITE_1(sc, RL_CFG5, v); 3858 } 3859 3860 static void 3861 re_add_sysctls(struct rl_softc *sc) 3862 { 3863 struct sysctl_ctx_list *ctx; 3864 struct sysctl_oid_list *children; 3865 int error; 3866 3867 ctx = device_get_sysctl_ctx(sc->rl_dev); 3868 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev)); 3869 3870 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "stats", 3871 CTLTYPE_INT | CTLFLAG_RW, sc, 0, re_sysctl_stats, "I", 3872 "Statistics Information"); 3873 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) 3874 return; 3875 3876 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "int_rx_mod", 3877 CTLTYPE_INT | CTLFLAG_RW, &sc->rl_int_rx_mod, 0, 3878 sysctl_hw_re_int_mod, "I", "re RX interrupt moderation"); 3879 /* Pull in device tunables. */ 3880 sc->rl_int_rx_mod = RL_TIMER_DEFAULT; 3881 error = resource_int_value(device_get_name(sc->rl_dev), 3882 device_get_unit(sc->rl_dev), "int_rx_mod", &sc->rl_int_rx_mod); 3883 if (error == 0) { 3884 if (sc->rl_int_rx_mod < RL_TIMER_MIN || 3885 sc->rl_int_rx_mod > RL_TIMER_MAX) { 3886 device_printf(sc->rl_dev, "int_rx_mod value out of " 3887 "range; using default: %d\n", 3888 RL_TIMER_DEFAULT); 3889 sc->rl_int_rx_mod = RL_TIMER_DEFAULT; 3890 } 3891 } 3892 3893 } 3894 3895 static int 3896 re_sysctl_stats(SYSCTL_HANDLER_ARGS) 3897 { 3898 struct rl_softc *sc; 3899 struct rl_stats *stats; 3900 int error, i, result; 3901 3902 result = -1; 3903 error = sysctl_handle_int(oidp, &result, 0, req); 3904 if (error || req->newptr == NULL) 3905 return (error); 3906 3907 if (result == 1) { 3908 sc = (struct rl_softc *)arg1; 3909 RL_LOCK(sc); 3910 if ((sc->rl_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 3911 RL_UNLOCK(sc); 3912 goto done; 3913 } 3914 bus_dmamap_sync(sc->rl_ldata.rl_stag, 3915 sc->rl_ldata.rl_smap, BUS_DMASYNC_PREREAD); 3916 CSR_WRITE_4(sc, RL_DUMPSTATS_HI, 3917 RL_ADDR_HI(sc->rl_ldata.rl_stats_addr)); 3918 CSR_WRITE_4(sc, RL_DUMPSTATS_LO, 3919 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr)); 3920 CSR_WRITE_4(sc, RL_DUMPSTATS_LO, 3921 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr | 3922 RL_DUMPSTATS_START)); 3923 for (i = RL_TIMEOUT; i > 0; i--) { 3924 if ((CSR_READ_4(sc, RL_DUMPSTATS_LO) & 3925 RL_DUMPSTATS_START) == 0) 3926 break; 3927 DELAY(1000); 3928 } 3929 bus_dmamap_sync(sc->rl_ldata.rl_stag, 3930 sc->rl_ldata.rl_smap, BUS_DMASYNC_POSTREAD); 3931 RL_UNLOCK(sc); 3932 if (i == 0) { 3933 device_printf(sc->rl_dev, 3934 "DUMP statistics request timedout\n"); 3935 return (ETIMEDOUT); 3936 } 3937 done: 3938 stats = sc->rl_ldata.rl_stats; 3939 printf("%s statistics:\n", device_get_nameunit(sc->rl_dev)); 3940 printf("Tx frames : %ju\n", 3941 (uintmax_t)le64toh(stats->rl_tx_pkts)); 3942 printf("Rx frames : %ju\n", 3943 (uintmax_t)le64toh(stats->rl_rx_pkts)); 3944 printf("Tx errors : %ju\n", 3945 (uintmax_t)le64toh(stats->rl_tx_errs)); 3946 printf("Rx errors : %u\n", 3947 le32toh(stats->rl_rx_errs)); 3948 printf("Rx missed frames : %u\n", 3949 (uint32_t)le16toh(stats->rl_missed_pkts)); 3950 printf("Rx frame alignment errs : %u\n", 3951 (uint32_t)le16toh(stats->rl_rx_framealign_errs)); 3952 printf("Tx single collisions : %u\n", 3953 le32toh(stats->rl_tx_onecoll)); 3954 printf("Tx multiple collisions : %u\n", 3955 le32toh(stats->rl_tx_multicolls)); 3956 printf("Rx unicast frames : %ju\n", 3957 (uintmax_t)le64toh(stats->rl_rx_ucasts)); 3958 printf("Rx broadcast frames : %ju\n", 3959 (uintmax_t)le64toh(stats->rl_rx_bcasts)); 3960 printf("Rx multicast frames : %u\n", 3961 le32toh(stats->rl_rx_mcasts)); 3962 printf("Tx aborts : %u\n", 3963 (uint32_t)le16toh(stats->rl_tx_aborts)); 3964 printf("Tx underruns : %u\n", 3965 (uint32_t)le16toh(stats->rl_rx_underruns)); 3966 } 3967 3968 return (error); 3969 } 3970 3971 static int 3972 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3973 { 3974 int error, value; 3975 3976 if (arg1 == NULL) 3977 return (EINVAL); 3978 value = *(int *)arg1; 3979 error = sysctl_handle_int(oidp, &value, 0, req); 3980 if (error || req->newptr == NULL) 3981 return (error); 3982 if (value < low || value > high) 3983 return (EINVAL); 3984 *(int *)arg1 = value; 3985 3986 return (0); 3987 } 3988 3989 static int 3990 sysctl_hw_re_int_mod(SYSCTL_HANDLER_ARGS) 3991 { 3992 3993 return (sysctl_int_range(oidp, arg1, arg2, req, RL_TIMER_MIN, 3994 RL_TIMER_MAX)); 3995 } 3996