1 /*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44 /* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111 #ifdef HAVE_KERNEL_OPTION_HEADERS 112 #include "opt_device_polling.h" 113 #endif 114 115 #include <sys/param.h> 116 #include <sys/endian.h> 117 #include <sys/systm.h> 118 #include <sys/sockio.h> 119 #include <sys/mbuf.h> 120 #include <sys/malloc.h> 121 #include <sys/module.h> 122 #include <sys/kernel.h> 123 #include <sys/socket.h> 124 #include <sys/lock.h> 125 #include <sys/mutex.h> 126 #include <sys/sysctl.h> 127 #include <sys/taskqueue.h> 128 129 #include <net/if.h> 130 #include <net/if_var.h> 131 #include <net/if_arp.h> 132 #include <net/ethernet.h> 133 #include <net/if_dl.h> 134 #include <net/if_media.h> 135 #include <net/if_types.h> 136 #include <net/if_vlan_var.h> 137 138 #include <net/bpf.h> 139 140 #include <machine/bus.h> 141 #include <machine/resource.h> 142 #include <sys/bus.h> 143 #include <sys/rman.h> 144 145 #include <dev/mii/mii.h> 146 #include <dev/mii/miivar.h> 147 148 #include <dev/pci/pcireg.h> 149 #include <dev/pci/pcivar.h> 150 151 #include <pci/if_rlreg.h> 152 153 MODULE_DEPEND(re, pci, 1, 1, 1); 154 MODULE_DEPEND(re, ether, 1, 1, 1); 155 MODULE_DEPEND(re, miibus, 1, 1, 1); 156 157 /* "device miibus" required. See GENERIC if you get errors here. */ 158 #include "miibus_if.h" 159 160 /* Tunables. */ 161 static int intr_filter = 0; 162 TUNABLE_INT("hw.re.intr_filter", &intr_filter); 163 static int msi_disable = 0; 164 TUNABLE_INT("hw.re.msi_disable", &msi_disable); 165 static int msix_disable = 0; 166 TUNABLE_INT("hw.re.msix_disable", &msix_disable); 167 static int prefer_iomap = 0; 168 TUNABLE_INT("hw.re.prefer_iomap", &prefer_iomap); 169 170 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 171 172 /* 173 * Various supported device vendors/types and their names. 174 */ 175 static const struct rl_type re_devs[] = { 176 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0, 177 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 178 { DLINK_VENDORID, DLINK_DEVICEID_530T_REVC, 0, 179 "D-Link DGE-530(T) Gigabit Ethernet Adapter" }, 180 { RT_VENDORID, RT_DEVICEID_8139, 0, 181 "RealTek 8139C+ 10/100BaseTX" }, 182 { RT_VENDORID, RT_DEVICEID_8101E, 0, 183 "RealTek 810xE PCIe 10/100baseTX" }, 184 { RT_VENDORID, RT_DEVICEID_8168, 0, 185 "RealTek 8168/8111 B/C/CP/D/DP/E/F/G PCIe Gigabit Ethernet" }, 186 { RT_VENDORID, RT_DEVICEID_8169, 0, 187 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" }, 188 { RT_VENDORID, RT_DEVICEID_8169SC, 0, 189 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 190 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0, 191 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 192 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0, 193 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 194 { USR_VENDORID, USR_DEVICEID_997902, 0, 195 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 196 }; 197 198 static const struct rl_hwrev re_hwrevs[] = { 199 { RL_HWREV_8139, RL_8139, "", RL_MTU }, 200 { RL_HWREV_8139A, RL_8139, "A", RL_MTU }, 201 { RL_HWREV_8139AG, RL_8139, "A-G", RL_MTU }, 202 { RL_HWREV_8139B, RL_8139, "B", RL_MTU }, 203 { RL_HWREV_8130, RL_8139, "8130", RL_MTU }, 204 { RL_HWREV_8139C, RL_8139, "C", RL_MTU }, 205 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C", RL_MTU }, 206 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+", RL_MTU }, 207 { RL_HWREV_8168B_SPIN1, RL_8169, "8168", RL_JUMBO_MTU }, 208 { RL_HWREV_8169, RL_8169, "8169", RL_JUMBO_MTU }, 209 { RL_HWREV_8169S, RL_8169, "8169S", RL_JUMBO_MTU }, 210 { RL_HWREV_8110S, RL_8169, "8110S", RL_JUMBO_MTU }, 211 { RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB", RL_JUMBO_MTU }, 212 { RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU }, 213 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL", RL_JUMBO_MTU }, 214 { RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU }, 215 { RL_HWREV_8100, RL_8139, "8100", RL_MTU }, 216 { RL_HWREV_8101, RL_8139, "8101", RL_MTU }, 217 { RL_HWREV_8100E, RL_8169, "8100E", RL_MTU }, 218 { RL_HWREV_8101E, RL_8169, "8101E", RL_MTU }, 219 { RL_HWREV_8102E, RL_8169, "8102E", RL_MTU }, 220 { RL_HWREV_8102EL, RL_8169, "8102EL", RL_MTU }, 221 { RL_HWREV_8102EL_SPIN1, RL_8169, "8102EL", RL_MTU }, 222 { RL_HWREV_8103E, RL_8169, "8103E", RL_MTU }, 223 { RL_HWREV_8401E, RL_8169, "8401E", RL_MTU }, 224 { RL_HWREV_8402, RL_8169, "8402", RL_MTU }, 225 { RL_HWREV_8105E, RL_8169, "8105E", RL_MTU }, 226 { RL_HWREV_8105E_SPIN1, RL_8169, "8105E", RL_MTU }, 227 { RL_HWREV_8106E, RL_8169, "8106E", RL_MTU }, 228 { RL_HWREV_8168B_SPIN2, RL_8169, "8168", RL_JUMBO_MTU }, 229 { RL_HWREV_8168B_SPIN3, RL_8169, "8168", RL_JUMBO_MTU }, 230 { RL_HWREV_8168C, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K }, 231 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K }, 232 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP", RL_JUMBO_MTU_6K }, 233 { RL_HWREV_8168D, RL_8169, "8168D/8111D", RL_JUMBO_MTU_9K }, 234 { RL_HWREV_8168DP, RL_8169, "8168DP/8111DP", RL_JUMBO_MTU_9K }, 235 { RL_HWREV_8168E, RL_8169, "8168E/8111E", RL_JUMBO_MTU_9K}, 236 { RL_HWREV_8168E_VL, RL_8169, "8168E/8111E-VL", RL_JUMBO_MTU_6K}, 237 { RL_HWREV_8168EP, RL_8169, "8168EP/8111EP", RL_JUMBO_MTU_9K}, 238 { RL_HWREV_8168F, RL_8169, "8168F/8111F", RL_JUMBO_MTU_9K}, 239 { RL_HWREV_8168G, RL_8169, "8168G/8111G", RL_JUMBO_MTU_9K}, 240 { RL_HWREV_8168GU, RL_8169, "8168GU/8111GU", RL_JUMBO_MTU_9K}, 241 { RL_HWREV_8411, RL_8169, "8411", RL_JUMBO_MTU_9K}, 242 { RL_HWREV_8411B, RL_8169, "8411B", RL_JUMBO_MTU_9K}, 243 { 0, 0, NULL, 0 } 244 }; 245 246 static int re_probe (device_t); 247 static int re_attach (device_t); 248 static int re_detach (device_t); 249 250 static int re_encap (struct rl_softc *, struct mbuf **); 251 252 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 253 static int re_allocmem (device_t, struct rl_softc *); 254 static __inline void re_discard_rxbuf 255 (struct rl_softc *, int); 256 static int re_newbuf (struct rl_softc *, int); 257 static int re_jumbo_newbuf (struct rl_softc *, int); 258 static int re_rx_list_init (struct rl_softc *); 259 static int re_jrx_list_init (struct rl_softc *); 260 static int re_tx_list_init (struct rl_softc *); 261 #ifdef RE_FIXUP_RX 262 static __inline void re_fixup_rx 263 (struct mbuf *); 264 #endif 265 static int re_rxeof (struct rl_softc *, int *); 266 static void re_txeof (struct rl_softc *); 267 #ifdef DEVICE_POLLING 268 static int re_poll (struct ifnet *, enum poll_cmd, int); 269 static int re_poll_locked (struct ifnet *, enum poll_cmd, int); 270 #endif 271 static int re_intr (void *); 272 static void re_intr_msi (void *); 273 static void re_tick (void *); 274 static void re_int_task (void *, int); 275 static void re_start (struct ifnet *); 276 static void re_start_locked (struct ifnet *); 277 static int re_ioctl (struct ifnet *, u_long, caddr_t); 278 static void re_init (void *); 279 static void re_init_locked (struct rl_softc *); 280 static void re_stop (struct rl_softc *); 281 static void re_watchdog (struct rl_softc *); 282 static int re_suspend (device_t); 283 static int re_resume (device_t); 284 static int re_shutdown (device_t); 285 static int re_ifmedia_upd (struct ifnet *); 286 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 287 288 static void re_eeprom_putbyte (struct rl_softc *, int); 289 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 290 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 291 static int re_gmii_readreg (device_t, int, int); 292 static int re_gmii_writereg (device_t, int, int, int); 293 294 static int re_miibus_readreg (device_t, int, int); 295 static int re_miibus_writereg (device_t, int, int, int); 296 static void re_miibus_statchg (device_t); 297 298 static void re_set_jumbo (struct rl_softc *, int); 299 static void re_set_rxmode (struct rl_softc *); 300 static void re_reset (struct rl_softc *); 301 static void re_setwol (struct rl_softc *); 302 static void re_clrwol (struct rl_softc *); 303 static void re_set_linkspeed (struct rl_softc *); 304 305 #ifdef DEV_NETMAP /* see ixgbe.c for details */ 306 #include <dev/netmap/if_re_netmap.h> 307 #endif /* !DEV_NETMAP */ 308 309 #ifdef RE_DIAG 310 static int re_diag (struct rl_softc *); 311 #endif 312 313 static void re_add_sysctls (struct rl_softc *); 314 static int re_sysctl_stats (SYSCTL_HANDLER_ARGS); 315 static int sysctl_int_range (SYSCTL_HANDLER_ARGS, int, int); 316 static int sysctl_hw_re_int_mod (SYSCTL_HANDLER_ARGS); 317 318 static device_method_t re_methods[] = { 319 /* Device interface */ 320 DEVMETHOD(device_probe, re_probe), 321 DEVMETHOD(device_attach, re_attach), 322 DEVMETHOD(device_detach, re_detach), 323 DEVMETHOD(device_suspend, re_suspend), 324 DEVMETHOD(device_resume, re_resume), 325 DEVMETHOD(device_shutdown, re_shutdown), 326 327 /* MII interface */ 328 DEVMETHOD(miibus_readreg, re_miibus_readreg), 329 DEVMETHOD(miibus_writereg, re_miibus_writereg), 330 DEVMETHOD(miibus_statchg, re_miibus_statchg), 331 332 DEVMETHOD_END 333 }; 334 335 static driver_t re_driver = { 336 "re", 337 re_methods, 338 sizeof(struct rl_softc) 339 }; 340 341 static devclass_t re_devclass; 342 343 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 344 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 345 346 #define EE_SET(x) \ 347 CSR_WRITE_1(sc, RL_EECMD, \ 348 CSR_READ_1(sc, RL_EECMD) | x) 349 350 #define EE_CLR(x) \ 351 CSR_WRITE_1(sc, RL_EECMD, \ 352 CSR_READ_1(sc, RL_EECMD) & ~x) 353 354 /* 355 * Send a read command and address to the EEPROM, check for ACK. 356 */ 357 static void 358 re_eeprom_putbyte(struct rl_softc *sc, int addr) 359 { 360 int d, i; 361 362 d = addr | (RL_9346_READ << sc->rl_eewidth); 363 364 /* 365 * Feed in each bit and strobe the clock. 366 */ 367 368 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 369 if (d & i) { 370 EE_SET(RL_EE_DATAIN); 371 } else { 372 EE_CLR(RL_EE_DATAIN); 373 } 374 DELAY(100); 375 EE_SET(RL_EE_CLK); 376 DELAY(150); 377 EE_CLR(RL_EE_CLK); 378 DELAY(100); 379 } 380 } 381 382 /* 383 * Read a word of data stored in the EEPROM at address 'addr.' 384 */ 385 static void 386 re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest) 387 { 388 int i; 389 u_int16_t word = 0; 390 391 /* 392 * Send address of word we want to read. 393 */ 394 re_eeprom_putbyte(sc, addr); 395 396 /* 397 * Start reading bits from EEPROM. 398 */ 399 for (i = 0x8000; i; i >>= 1) { 400 EE_SET(RL_EE_CLK); 401 DELAY(100); 402 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 403 word |= i; 404 EE_CLR(RL_EE_CLK); 405 DELAY(100); 406 } 407 408 *dest = word; 409 } 410 411 /* 412 * Read a sequence of words from the EEPROM. 413 */ 414 static void 415 re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt) 416 { 417 int i; 418 u_int16_t word = 0, *ptr; 419 420 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 421 422 DELAY(100); 423 424 for (i = 0; i < cnt; i++) { 425 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 426 re_eeprom_getword(sc, off + i, &word); 427 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 428 ptr = (u_int16_t *)(dest + (i * 2)); 429 *ptr = word; 430 } 431 432 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 433 } 434 435 static int 436 re_gmii_readreg(device_t dev, int phy, int reg) 437 { 438 struct rl_softc *sc; 439 u_int32_t rval; 440 int i; 441 442 sc = device_get_softc(dev); 443 444 /* Let the rgephy driver read the GMEDIASTAT register */ 445 446 if (reg == RL_GMEDIASTAT) { 447 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 448 return (rval); 449 } 450 451 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 452 453 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 454 rval = CSR_READ_4(sc, RL_PHYAR); 455 if (rval & RL_PHYAR_BUSY) 456 break; 457 DELAY(25); 458 } 459 460 if (i == RL_PHY_TIMEOUT) { 461 device_printf(sc->rl_dev, "PHY read failed\n"); 462 return (0); 463 } 464 465 /* 466 * Controller requires a 20us delay to process next MDIO request. 467 */ 468 DELAY(20); 469 470 return (rval & RL_PHYAR_PHYDATA); 471 } 472 473 static int 474 re_gmii_writereg(device_t dev, int phy, int reg, int data) 475 { 476 struct rl_softc *sc; 477 u_int32_t rval; 478 int i; 479 480 sc = device_get_softc(dev); 481 482 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 483 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 484 485 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 486 rval = CSR_READ_4(sc, RL_PHYAR); 487 if (!(rval & RL_PHYAR_BUSY)) 488 break; 489 DELAY(25); 490 } 491 492 if (i == RL_PHY_TIMEOUT) { 493 device_printf(sc->rl_dev, "PHY write failed\n"); 494 return (0); 495 } 496 497 /* 498 * Controller requires a 20us delay to process next MDIO request. 499 */ 500 DELAY(20); 501 502 return (0); 503 } 504 505 static int 506 re_miibus_readreg(device_t dev, int phy, int reg) 507 { 508 struct rl_softc *sc; 509 u_int16_t rval = 0; 510 u_int16_t re8139_reg = 0; 511 512 sc = device_get_softc(dev); 513 514 if (sc->rl_type == RL_8169) { 515 rval = re_gmii_readreg(dev, phy, reg); 516 return (rval); 517 } 518 519 switch (reg) { 520 case MII_BMCR: 521 re8139_reg = RL_BMCR; 522 break; 523 case MII_BMSR: 524 re8139_reg = RL_BMSR; 525 break; 526 case MII_ANAR: 527 re8139_reg = RL_ANAR; 528 break; 529 case MII_ANER: 530 re8139_reg = RL_ANER; 531 break; 532 case MII_ANLPAR: 533 re8139_reg = RL_LPAR; 534 break; 535 case MII_PHYIDR1: 536 case MII_PHYIDR2: 537 return (0); 538 /* 539 * Allow the rlphy driver to read the media status 540 * register. If we have a link partner which does not 541 * support NWAY, this is the register which will tell 542 * us the results of parallel detection. 543 */ 544 case RL_MEDIASTAT: 545 rval = CSR_READ_1(sc, RL_MEDIASTAT); 546 return (rval); 547 default: 548 device_printf(sc->rl_dev, "bad phy register\n"); 549 return (0); 550 } 551 rval = CSR_READ_2(sc, re8139_reg); 552 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 553 /* 8139C+ has different bit layout. */ 554 rval &= ~(BMCR_LOOP | BMCR_ISO); 555 } 556 return (rval); 557 } 558 559 static int 560 re_miibus_writereg(device_t dev, int phy, int reg, int data) 561 { 562 struct rl_softc *sc; 563 u_int16_t re8139_reg = 0; 564 int rval = 0; 565 566 sc = device_get_softc(dev); 567 568 if (sc->rl_type == RL_8169) { 569 rval = re_gmii_writereg(dev, phy, reg, data); 570 return (rval); 571 } 572 573 switch (reg) { 574 case MII_BMCR: 575 re8139_reg = RL_BMCR; 576 if (sc->rl_type == RL_8139CPLUS) { 577 /* 8139C+ has different bit layout. */ 578 data &= ~(BMCR_LOOP | BMCR_ISO); 579 } 580 break; 581 case MII_BMSR: 582 re8139_reg = RL_BMSR; 583 break; 584 case MII_ANAR: 585 re8139_reg = RL_ANAR; 586 break; 587 case MII_ANER: 588 re8139_reg = RL_ANER; 589 break; 590 case MII_ANLPAR: 591 re8139_reg = RL_LPAR; 592 break; 593 case MII_PHYIDR1: 594 case MII_PHYIDR2: 595 return (0); 596 break; 597 default: 598 device_printf(sc->rl_dev, "bad phy register\n"); 599 return (0); 600 } 601 CSR_WRITE_2(sc, re8139_reg, data); 602 return (0); 603 } 604 605 static void 606 re_miibus_statchg(device_t dev) 607 { 608 struct rl_softc *sc; 609 struct ifnet *ifp; 610 struct mii_data *mii; 611 612 sc = device_get_softc(dev); 613 mii = device_get_softc(sc->rl_miibus); 614 ifp = sc->rl_ifp; 615 if (mii == NULL || ifp == NULL || 616 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 617 return; 618 619 sc->rl_flags &= ~RL_FLAG_LINK; 620 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 621 (IFM_ACTIVE | IFM_AVALID)) { 622 switch (IFM_SUBTYPE(mii->mii_media_active)) { 623 case IFM_10_T: 624 case IFM_100_TX: 625 sc->rl_flags |= RL_FLAG_LINK; 626 break; 627 case IFM_1000_T: 628 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0) 629 break; 630 sc->rl_flags |= RL_FLAG_LINK; 631 break; 632 default: 633 break; 634 } 635 } 636 /* 637 * RealTek controllers does not provide any interface to 638 * Tx/Rx MACs for resolved speed, duplex and flow-control 639 * parameters. 640 */ 641 } 642 643 /* 644 * Set the RX configuration and 64-bit multicast hash filter. 645 */ 646 static void 647 re_set_rxmode(struct rl_softc *sc) 648 { 649 struct ifnet *ifp; 650 struct ifmultiaddr *ifma; 651 uint32_t hashes[2] = { 0, 0 }; 652 uint32_t h, rxfilt; 653 654 RL_LOCK_ASSERT(sc); 655 656 ifp = sc->rl_ifp; 657 658 rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD; 659 660 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 661 if (ifp->if_flags & IFF_PROMISC) 662 rxfilt |= RL_RXCFG_RX_ALLPHYS; 663 /* 664 * Unlike other hardwares, we have to explicitly set 665 * RL_RXCFG_RX_MULTI to receive multicast frames in 666 * promiscuous mode. 667 */ 668 rxfilt |= RL_RXCFG_RX_MULTI; 669 hashes[0] = hashes[1] = 0xffffffff; 670 goto done; 671 } 672 673 if_maddr_rlock(ifp); 674 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 675 if (ifma->ifma_addr->sa_family != AF_LINK) 676 continue; 677 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 678 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 679 if (h < 32) 680 hashes[0] |= (1 << h); 681 else 682 hashes[1] |= (1 << (h - 32)); 683 } 684 if_maddr_runlock(ifp); 685 686 if (hashes[0] != 0 || hashes[1] != 0) { 687 /* 688 * For some unfathomable reason, RealTek decided to 689 * reverse the order of the multicast hash registers 690 * in the PCI Express parts. This means we have to 691 * write the hash pattern in reverse order for those 692 * devices. 693 */ 694 if ((sc->rl_flags & RL_FLAG_PCIE) != 0) { 695 h = bswap32(hashes[0]); 696 hashes[0] = bswap32(hashes[1]); 697 hashes[1] = h; 698 } 699 rxfilt |= RL_RXCFG_RX_MULTI; 700 } 701 702 done: 703 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 704 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 705 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 706 } 707 708 static void 709 re_reset(struct rl_softc *sc) 710 { 711 int i; 712 713 RL_LOCK_ASSERT(sc); 714 715 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 716 717 for (i = 0; i < RL_TIMEOUT; i++) { 718 DELAY(10); 719 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 720 break; 721 } 722 if (i == RL_TIMEOUT) 723 device_printf(sc->rl_dev, "reset never completed!\n"); 724 725 if ((sc->rl_flags & RL_FLAG_MACRESET) != 0) 726 CSR_WRITE_1(sc, 0x82, 1); 727 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169S) 728 re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0); 729 } 730 731 #ifdef RE_DIAG 732 733 /* 734 * The following routine is designed to test for a defect on some 735 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 736 * lines connected to the bus, however for a 32-bit only card, they 737 * should be pulled high. The result of this defect is that the 738 * NIC will not work right if you plug it into a 64-bit slot: DMA 739 * operations will be done with 64-bit transfers, which will fail 740 * because the 64-bit data lines aren't connected. 741 * 742 * There's no way to work around this (short of talking a soldering 743 * iron to the board), however we can detect it. The method we use 744 * here is to put the NIC into digital loopback mode, set the receiver 745 * to promiscuous mode, and then try to send a frame. We then compare 746 * the frame data we sent to what was received. If the data matches, 747 * then the NIC is working correctly, otherwise we know the user has 748 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 749 * slot. In the latter case, there's no way the NIC can work correctly, 750 * so we print out a message on the console and abort the device attach. 751 */ 752 753 static int 754 re_diag(struct rl_softc *sc) 755 { 756 struct ifnet *ifp = sc->rl_ifp; 757 struct mbuf *m0; 758 struct ether_header *eh; 759 struct rl_desc *cur_rx; 760 u_int16_t status; 761 u_int32_t rxstat; 762 int total_len, i, error = 0, phyaddr; 763 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 764 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 765 766 /* Allocate a single mbuf */ 767 MGETHDR(m0, M_NOWAIT, MT_DATA); 768 if (m0 == NULL) 769 return (ENOBUFS); 770 771 RL_LOCK(sc); 772 773 /* 774 * Initialize the NIC in test mode. This sets the chip up 775 * so that it can send and receive frames, but performs the 776 * following special functions: 777 * - Puts receiver in promiscuous mode 778 * - Enables digital loopback mode 779 * - Leaves interrupts turned off 780 */ 781 782 ifp->if_flags |= IFF_PROMISC; 783 sc->rl_testmode = 1; 784 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 785 re_init_locked(sc); 786 sc->rl_flags |= RL_FLAG_LINK; 787 if (sc->rl_type == RL_8169) 788 phyaddr = 1; 789 else 790 phyaddr = 0; 791 792 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 793 for (i = 0; i < RL_TIMEOUT; i++) { 794 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 795 if (!(status & BMCR_RESET)) 796 break; 797 } 798 799 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 800 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 801 802 DELAY(100000); 803 804 /* Put some data in the mbuf */ 805 806 eh = mtod(m0, struct ether_header *); 807 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 808 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 809 eh->ether_type = htons(ETHERTYPE_IP); 810 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 811 812 /* 813 * Queue the packet, start transmission. 814 * Note: IF_HANDOFF() ultimately calls re_start() for us. 815 */ 816 817 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 818 RL_UNLOCK(sc); 819 /* XXX: re_diag must not be called when in ALTQ mode */ 820 IF_HANDOFF(&ifp->if_snd, m0, ifp); 821 RL_LOCK(sc); 822 m0 = NULL; 823 824 /* Wait for it to propagate through the chip */ 825 826 DELAY(100000); 827 for (i = 0; i < RL_TIMEOUT; i++) { 828 status = CSR_READ_2(sc, RL_ISR); 829 CSR_WRITE_2(sc, RL_ISR, status); 830 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 831 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 832 break; 833 DELAY(10); 834 } 835 836 if (i == RL_TIMEOUT) { 837 device_printf(sc->rl_dev, 838 "diagnostic failed, failed to receive packet in" 839 " loopback mode\n"); 840 error = EIO; 841 goto done; 842 } 843 844 /* 845 * The packet should have been dumped into the first 846 * entry in the RX DMA ring. Grab it from there. 847 */ 848 849 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 850 sc->rl_ldata.rl_rx_list_map, 851 BUS_DMASYNC_POSTREAD); 852 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 853 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 854 BUS_DMASYNC_POSTREAD); 855 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 856 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 857 858 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 859 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 860 eh = mtod(m0, struct ether_header *); 861 862 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 863 total_len = RL_RXBYTES(cur_rx); 864 rxstat = le32toh(cur_rx->rl_cmdstat); 865 866 if (total_len != ETHER_MIN_LEN) { 867 device_printf(sc->rl_dev, 868 "diagnostic failed, received short packet\n"); 869 error = EIO; 870 goto done; 871 } 872 873 /* Test that the received packet data matches what we sent. */ 874 875 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 876 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 877 ntohs(eh->ether_type) != ETHERTYPE_IP) { 878 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 879 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 880 dst, ":", src, ":", ETHERTYPE_IP); 881 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 882 eh->ether_dhost, ":", eh->ether_shost, ":", 883 ntohs(eh->ether_type)); 884 device_printf(sc->rl_dev, "You may have a defective 32-bit " 885 "NIC plugged into a 64-bit PCI slot.\n"); 886 device_printf(sc->rl_dev, "Please re-install the NIC in a " 887 "32-bit slot for proper operation.\n"); 888 device_printf(sc->rl_dev, "Read the re(4) man page for more " 889 "details.\n"); 890 error = EIO; 891 } 892 893 done: 894 /* Turn interface off, release resources */ 895 896 sc->rl_testmode = 0; 897 sc->rl_flags &= ~RL_FLAG_LINK; 898 ifp->if_flags &= ~IFF_PROMISC; 899 re_stop(sc); 900 if (m0 != NULL) 901 m_freem(m0); 902 903 RL_UNLOCK(sc); 904 905 return (error); 906 } 907 908 #endif 909 910 /* 911 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 912 * IDs against our list and return a device name if we find a match. 913 */ 914 static int 915 re_probe(device_t dev) 916 { 917 const struct rl_type *t; 918 uint16_t devid, vendor; 919 uint16_t revid, sdevid; 920 int i; 921 922 vendor = pci_get_vendor(dev); 923 devid = pci_get_device(dev); 924 revid = pci_get_revid(dev); 925 sdevid = pci_get_subdevice(dev); 926 927 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 928 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 929 /* 930 * Only attach to rev. 3 of the Linksys EG1032 adapter. 931 * Rev. 2 is supported by sk(4). 932 */ 933 return (ENXIO); 934 } 935 } 936 937 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 938 if (revid != 0x20) { 939 /* 8139, let rl(4) take care of this device. */ 940 return (ENXIO); 941 } 942 } 943 944 t = re_devs; 945 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) { 946 if (vendor == t->rl_vid && devid == t->rl_did) { 947 device_set_desc(dev, t->rl_name); 948 return (BUS_PROBE_DEFAULT); 949 } 950 } 951 952 return (ENXIO); 953 } 954 955 /* 956 * Map a single buffer address. 957 */ 958 959 static void 960 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 961 { 962 bus_addr_t *addr; 963 964 if (error) 965 return; 966 967 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 968 addr = arg; 969 *addr = segs->ds_addr; 970 } 971 972 static int 973 re_allocmem(device_t dev, struct rl_softc *sc) 974 { 975 bus_addr_t lowaddr; 976 bus_size_t rx_list_size, tx_list_size; 977 int error; 978 int i; 979 980 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 981 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 982 983 /* 984 * Allocate the parent bus DMA tag appropriate for PCI. 985 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD 986 * register should be set. However some RealTek chips are known 987 * to be buggy on DAC handling, therefore disable DAC by limiting 988 * DMA address space to 32bit. PCIe variants of RealTek chips 989 * may not have the limitation. 990 */ 991 lowaddr = BUS_SPACE_MAXADDR; 992 if ((sc->rl_flags & RL_FLAG_PCIE) == 0) 993 lowaddr = BUS_SPACE_MAXADDR_32BIT; 994 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 995 lowaddr, BUS_SPACE_MAXADDR, NULL, NULL, 996 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 997 NULL, NULL, &sc->rl_parent_tag); 998 if (error) { 999 device_printf(dev, "could not allocate parent DMA tag\n"); 1000 return (error); 1001 } 1002 1003 /* 1004 * Allocate map for TX mbufs. 1005 */ 1006 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 1007 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1008 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 1009 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 1010 if (error) { 1011 device_printf(dev, "could not allocate TX DMA tag\n"); 1012 return (error); 1013 } 1014 1015 /* 1016 * Allocate map for RX mbufs. 1017 */ 1018 1019 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 1020 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 1021 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1022 MJUM9BYTES, 1, MJUM9BYTES, 0, NULL, NULL, 1023 &sc->rl_ldata.rl_jrx_mtag); 1024 if (error) { 1025 device_printf(dev, 1026 "could not allocate jumbo RX DMA tag\n"); 1027 return (error); 1028 } 1029 } 1030 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 1031 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1032 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 1033 if (error) { 1034 device_printf(dev, "could not allocate RX DMA tag\n"); 1035 return (error); 1036 } 1037 1038 /* 1039 * Allocate map for TX descriptor list. 1040 */ 1041 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1042 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1043 NULL, tx_list_size, 1, tx_list_size, 0, 1044 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1045 if (error) { 1046 device_printf(dev, "could not allocate TX DMA ring tag\n"); 1047 return (error); 1048 } 1049 1050 /* Allocate DMA'able memory for the TX ring */ 1051 1052 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1053 (void **)&sc->rl_ldata.rl_tx_list, 1054 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1055 &sc->rl_ldata.rl_tx_list_map); 1056 if (error) { 1057 device_printf(dev, "could not allocate TX DMA ring\n"); 1058 return (error); 1059 } 1060 1061 /* Load the map for the TX ring. */ 1062 1063 sc->rl_ldata.rl_tx_list_addr = 0; 1064 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1065 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1066 tx_list_size, re_dma_map_addr, 1067 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1068 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 1069 device_printf(dev, "could not load TX DMA ring\n"); 1070 return (ENOMEM); 1071 } 1072 1073 /* Create DMA maps for TX buffers */ 1074 1075 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1076 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1077 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1078 if (error) { 1079 device_printf(dev, "could not create DMA map for TX\n"); 1080 return (error); 1081 } 1082 } 1083 1084 /* 1085 * Allocate map for RX descriptor list. 1086 */ 1087 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1088 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1089 NULL, rx_list_size, 1, rx_list_size, 0, 1090 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1091 if (error) { 1092 device_printf(dev, "could not create RX DMA ring tag\n"); 1093 return (error); 1094 } 1095 1096 /* Allocate DMA'able memory for the RX ring */ 1097 1098 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1099 (void **)&sc->rl_ldata.rl_rx_list, 1100 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1101 &sc->rl_ldata.rl_rx_list_map); 1102 if (error) { 1103 device_printf(dev, "could not allocate RX DMA ring\n"); 1104 return (error); 1105 } 1106 1107 /* Load the map for the RX ring. */ 1108 1109 sc->rl_ldata.rl_rx_list_addr = 0; 1110 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1111 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1112 rx_list_size, re_dma_map_addr, 1113 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1114 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1115 device_printf(dev, "could not load RX DMA ring\n"); 1116 return (ENOMEM); 1117 } 1118 1119 /* Create DMA maps for RX buffers */ 1120 1121 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 1122 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0, 1123 &sc->rl_ldata.rl_jrx_sparemap); 1124 if (error) { 1125 device_printf(dev, 1126 "could not create spare DMA map for jumbo RX\n"); 1127 return (error); 1128 } 1129 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1130 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0, 1131 &sc->rl_ldata.rl_jrx_desc[i].rx_dmamap); 1132 if (error) { 1133 device_printf(dev, 1134 "could not create DMA map for jumbo RX\n"); 1135 return (error); 1136 } 1137 } 1138 } 1139 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1140 &sc->rl_ldata.rl_rx_sparemap); 1141 if (error) { 1142 device_printf(dev, "could not create spare DMA map for RX\n"); 1143 return (error); 1144 } 1145 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1146 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1147 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1148 if (error) { 1149 device_printf(dev, "could not create DMA map for RX\n"); 1150 return (error); 1151 } 1152 } 1153 1154 /* Create DMA map for statistics. */ 1155 error = bus_dma_tag_create(sc->rl_parent_tag, RL_DUMP_ALIGN, 0, 1156 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1157 sizeof(struct rl_stats), 1, sizeof(struct rl_stats), 0, NULL, NULL, 1158 &sc->rl_ldata.rl_stag); 1159 if (error) { 1160 device_printf(dev, "could not create statistics DMA tag\n"); 1161 return (error); 1162 } 1163 /* Allocate DMA'able memory for statistics. */ 1164 error = bus_dmamem_alloc(sc->rl_ldata.rl_stag, 1165 (void **)&sc->rl_ldata.rl_stats, 1166 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1167 &sc->rl_ldata.rl_smap); 1168 if (error) { 1169 device_printf(dev, 1170 "could not allocate statistics DMA memory\n"); 1171 return (error); 1172 } 1173 /* Load the map for statistics. */ 1174 sc->rl_ldata.rl_stats_addr = 0; 1175 error = bus_dmamap_load(sc->rl_ldata.rl_stag, sc->rl_ldata.rl_smap, 1176 sc->rl_ldata.rl_stats, sizeof(struct rl_stats), re_dma_map_addr, 1177 &sc->rl_ldata.rl_stats_addr, BUS_DMA_NOWAIT); 1178 if (error != 0 || sc->rl_ldata.rl_stats_addr == 0) { 1179 device_printf(dev, "could not load statistics DMA memory\n"); 1180 return (ENOMEM); 1181 } 1182 1183 return (0); 1184 } 1185 1186 /* 1187 * Attach the interface. Allocate softc structures, do ifmedia 1188 * setup and ethernet/BPF attach. 1189 */ 1190 static int 1191 re_attach(device_t dev) 1192 { 1193 u_char eaddr[ETHER_ADDR_LEN]; 1194 u_int16_t as[ETHER_ADDR_LEN / 2]; 1195 struct rl_softc *sc; 1196 struct ifnet *ifp; 1197 const struct rl_hwrev *hw_rev; 1198 u_int32_t cap, ctl; 1199 int hwrev; 1200 u_int16_t devid, re_did = 0; 1201 int error = 0, i, phy, rid; 1202 int msic, msixc, reg; 1203 uint8_t cfg; 1204 1205 sc = device_get_softc(dev); 1206 sc->rl_dev = dev; 1207 1208 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1209 MTX_DEF); 1210 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1211 1212 /* 1213 * Map control/status registers. 1214 */ 1215 pci_enable_busmaster(dev); 1216 1217 devid = pci_get_device(dev); 1218 /* 1219 * Prefer memory space register mapping over IO space. 1220 * Because RTL8169SC does not seem to work when memory mapping 1221 * is used always activate io mapping. 1222 */ 1223 if (devid == RT_DEVICEID_8169SC) 1224 prefer_iomap = 1; 1225 if (prefer_iomap == 0) { 1226 sc->rl_res_id = PCIR_BAR(1); 1227 sc->rl_res_type = SYS_RES_MEMORY; 1228 /* RTL8168/8101E seems to use different BARs. */ 1229 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E) 1230 sc->rl_res_id = PCIR_BAR(2); 1231 } else { 1232 sc->rl_res_id = PCIR_BAR(0); 1233 sc->rl_res_type = SYS_RES_IOPORT; 1234 } 1235 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1236 &sc->rl_res_id, RF_ACTIVE); 1237 if (sc->rl_res == NULL && prefer_iomap == 0) { 1238 sc->rl_res_id = PCIR_BAR(0); 1239 sc->rl_res_type = SYS_RES_IOPORT; 1240 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1241 &sc->rl_res_id, RF_ACTIVE); 1242 } 1243 if (sc->rl_res == NULL) { 1244 device_printf(dev, "couldn't map ports/memory\n"); 1245 error = ENXIO; 1246 goto fail; 1247 } 1248 1249 sc->rl_btag = rman_get_bustag(sc->rl_res); 1250 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1251 1252 msic = pci_msi_count(dev); 1253 msixc = pci_msix_count(dev); 1254 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 1255 sc->rl_flags |= RL_FLAG_PCIE; 1256 sc->rl_expcap = reg; 1257 } 1258 if (bootverbose) { 1259 device_printf(dev, "MSI count : %d\n", msic); 1260 device_printf(dev, "MSI-X count : %d\n", msixc); 1261 } 1262 if (msix_disable > 0) 1263 msixc = 0; 1264 if (msi_disable > 0) 1265 msic = 0; 1266 /* Prefer MSI-X to MSI. */ 1267 if (msixc > 0) { 1268 msixc = 1; 1269 rid = PCIR_BAR(4); 1270 sc->rl_res_pba = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1271 &rid, RF_ACTIVE); 1272 if (sc->rl_res_pba == NULL) { 1273 device_printf(sc->rl_dev, 1274 "could not allocate MSI-X PBA resource\n"); 1275 } 1276 if (sc->rl_res_pba != NULL && 1277 pci_alloc_msix(dev, &msixc) == 0) { 1278 if (msixc == 1) { 1279 device_printf(dev, "Using %d MSI-X message\n", 1280 msixc); 1281 sc->rl_flags |= RL_FLAG_MSIX; 1282 } else 1283 pci_release_msi(dev); 1284 } 1285 if ((sc->rl_flags & RL_FLAG_MSIX) == 0) { 1286 if (sc->rl_res_pba != NULL) 1287 bus_release_resource(dev, SYS_RES_MEMORY, rid, 1288 sc->rl_res_pba); 1289 sc->rl_res_pba = NULL; 1290 msixc = 0; 1291 } 1292 } 1293 /* Prefer MSI to INTx. */ 1294 if (msixc == 0 && msic > 0) { 1295 msic = 1; 1296 if (pci_alloc_msi(dev, &msic) == 0) { 1297 if (msic == RL_MSI_MESSAGES) { 1298 device_printf(dev, "Using %d MSI message\n", 1299 msic); 1300 sc->rl_flags |= RL_FLAG_MSI; 1301 /* Explicitly set MSI enable bit. */ 1302 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1303 cfg = CSR_READ_1(sc, RL_CFG2); 1304 cfg |= RL_CFG2_MSI; 1305 CSR_WRITE_1(sc, RL_CFG2, cfg); 1306 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1307 } else 1308 pci_release_msi(dev); 1309 } 1310 if ((sc->rl_flags & RL_FLAG_MSI) == 0) 1311 msic = 0; 1312 } 1313 1314 /* Allocate interrupt */ 1315 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) { 1316 rid = 0; 1317 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1318 RF_SHAREABLE | RF_ACTIVE); 1319 if (sc->rl_irq[0] == NULL) { 1320 device_printf(dev, "couldn't allocate IRQ resources\n"); 1321 error = ENXIO; 1322 goto fail; 1323 } 1324 } else { 1325 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1326 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1327 SYS_RES_IRQ, &rid, RF_ACTIVE); 1328 if (sc->rl_irq[i] == NULL) { 1329 device_printf(dev, 1330 "couldn't allocate IRQ resources for " 1331 "message %d\n", rid); 1332 error = ENXIO; 1333 goto fail; 1334 } 1335 } 1336 } 1337 1338 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1339 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1340 cfg = CSR_READ_1(sc, RL_CFG2); 1341 if ((cfg & RL_CFG2_MSI) != 0) { 1342 device_printf(dev, "turning off MSI enable bit.\n"); 1343 cfg &= ~RL_CFG2_MSI; 1344 CSR_WRITE_1(sc, RL_CFG2, cfg); 1345 } 1346 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1347 } 1348 1349 /* Disable ASPM L0S/L1. */ 1350 if (sc->rl_expcap != 0) { 1351 cap = pci_read_config(dev, sc->rl_expcap + 1352 PCIER_LINK_CAP, 2); 1353 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { 1354 ctl = pci_read_config(dev, sc->rl_expcap + 1355 PCIER_LINK_CTL, 2); 1356 if ((ctl & PCIEM_LINK_CTL_ASPMC) != 0) { 1357 ctl &= ~PCIEM_LINK_CTL_ASPMC; 1358 pci_write_config(dev, sc->rl_expcap + 1359 PCIER_LINK_CTL, ctl, 2); 1360 device_printf(dev, "ASPM disabled\n"); 1361 } 1362 } else 1363 device_printf(dev, "no ASPM capability\n"); 1364 } 1365 1366 hw_rev = re_hwrevs; 1367 hwrev = CSR_READ_4(sc, RL_TXCFG); 1368 switch (hwrev & 0x70000000) { 1369 case 0x00000000: 1370 case 0x10000000: 1371 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000); 1372 hwrev &= (RL_TXCFG_HWREV | 0x80000000); 1373 break; 1374 default: 1375 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000); 1376 sc->rl_macrev = hwrev & 0x00700000; 1377 hwrev &= RL_TXCFG_HWREV; 1378 break; 1379 } 1380 device_printf(dev, "MAC rev. 0x%08x\n", sc->rl_macrev); 1381 while (hw_rev->rl_desc != NULL) { 1382 if (hw_rev->rl_rev == hwrev) { 1383 sc->rl_type = hw_rev->rl_type; 1384 sc->rl_hwrev = hw_rev; 1385 break; 1386 } 1387 hw_rev++; 1388 } 1389 if (hw_rev->rl_desc == NULL) { 1390 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev); 1391 error = ENXIO; 1392 goto fail; 1393 } 1394 1395 switch (hw_rev->rl_rev) { 1396 case RL_HWREV_8139CPLUS: 1397 sc->rl_flags |= RL_FLAG_FASTETHER | RL_FLAG_AUTOPAD; 1398 break; 1399 case RL_HWREV_8100E: 1400 case RL_HWREV_8101E: 1401 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_FASTETHER; 1402 break; 1403 case RL_HWREV_8102E: 1404 case RL_HWREV_8102EL: 1405 case RL_HWREV_8102EL_SPIN1: 1406 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1407 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | 1408 RL_FLAG_AUTOPAD; 1409 break; 1410 case RL_HWREV_8103E: 1411 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1412 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | 1413 RL_FLAG_AUTOPAD | RL_FLAG_MACSLEEP; 1414 break; 1415 case RL_HWREV_8401E: 1416 case RL_HWREV_8105E: 1417 case RL_HWREV_8105E_SPIN1: 1418 case RL_HWREV_8106E: 1419 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1420 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1421 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD; 1422 break; 1423 case RL_HWREV_8402: 1424 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1425 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1426 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | 1427 RL_FLAG_CMDSTOP_WAIT_TXQ; 1428 break; 1429 case RL_HWREV_8168B_SPIN1: 1430 case RL_HWREV_8168B_SPIN2: 1431 sc->rl_flags |= RL_FLAG_WOLRXENB; 1432 /* FALLTHROUGH */ 1433 case RL_HWREV_8168B_SPIN3: 1434 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT; 1435 break; 1436 case RL_HWREV_8168C_SPIN2: 1437 sc->rl_flags |= RL_FLAG_MACSLEEP; 1438 /* FALLTHROUGH */ 1439 case RL_HWREV_8168C: 1440 if (sc->rl_macrev == 0x00200000) 1441 sc->rl_flags |= RL_FLAG_MACSLEEP; 1442 /* FALLTHROUGH */ 1443 case RL_HWREV_8168CP: 1444 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1445 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1446 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK; 1447 break; 1448 case RL_HWREV_8168D: 1449 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1450 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1451 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1452 RL_FLAG_WOL_MANLINK; 1453 break; 1454 case RL_HWREV_8168DP: 1455 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1456 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_AUTOPAD | 1457 RL_FLAG_JUMBOV2 | RL_FLAG_WAIT_TXPOLL | RL_FLAG_WOL_MANLINK; 1458 break; 1459 case RL_HWREV_8168E: 1460 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1461 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1462 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1463 RL_FLAG_WOL_MANLINK; 1464 break; 1465 case RL_HWREV_8168E_VL: 1466 case RL_HWREV_8168EP: 1467 case RL_HWREV_8168F: 1468 case RL_HWREV_8168G: 1469 case RL_HWREV_8411: 1470 case RL_HWREV_8411B: 1471 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1472 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1473 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1474 RL_FLAG_CMDSTOP_WAIT_TXQ | RL_FLAG_WOL_MANLINK; 1475 break; 1476 case RL_HWREV_8168GU: 1477 if (pci_get_device(dev) == RT_DEVICEID_8101E) { 1478 /* RTL8106EUS */ 1479 sc->rl_flags |= RL_FLAG_FASTETHER; 1480 } else 1481 sc->rl_flags |= RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK; 1482 1483 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1484 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1485 RL_FLAG_AUTOPAD | RL_FLAG_CMDSTOP_WAIT_TXQ; 1486 break; 1487 case RL_HWREV_8169_8110SB: 1488 case RL_HWREV_8169_8110SBL: 1489 case RL_HWREV_8169_8110SC: 1490 case RL_HWREV_8169_8110SCE: 1491 sc->rl_flags |= RL_FLAG_PHYWAKE; 1492 /* FALLTHROUGH */ 1493 case RL_HWREV_8169: 1494 case RL_HWREV_8169S: 1495 case RL_HWREV_8110S: 1496 sc->rl_flags |= RL_FLAG_MACRESET; 1497 break; 1498 default: 1499 break; 1500 } 1501 1502 if (sc->rl_hwrev->rl_rev == RL_HWREV_8139CPLUS) { 1503 sc->rl_cfg0 = RL_8139_CFG0; 1504 sc->rl_cfg1 = RL_8139_CFG1; 1505 sc->rl_cfg2 = 0; 1506 sc->rl_cfg3 = RL_8139_CFG3; 1507 sc->rl_cfg4 = RL_8139_CFG4; 1508 sc->rl_cfg5 = RL_8139_CFG5; 1509 } else { 1510 sc->rl_cfg0 = RL_CFG0; 1511 sc->rl_cfg1 = RL_CFG1; 1512 sc->rl_cfg2 = RL_CFG2; 1513 sc->rl_cfg3 = RL_CFG3; 1514 sc->rl_cfg4 = RL_CFG4; 1515 sc->rl_cfg5 = RL_CFG5; 1516 } 1517 1518 /* Reset the adapter. */ 1519 RL_LOCK(sc); 1520 re_reset(sc); 1521 RL_UNLOCK(sc); 1522 1523 /* Enable PME. */ 1524 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1525 cfg = CSR_READ_1(sc, sc->rl_cfg1); 1526 cfg |= RL_CFG1_PME; 1527 CSR_WRITE_1(sc, sc->rl_cfg1, cfg); 1528 cfg = CSR_READ_1(sc, sc->rl_cfg5); 1529 cfg &= RL_CFG5_PME_STS; 1530 CSR_WRITE_1(sc, sc->rl_cfg5, cfg); 1531 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1532 1533 if ((sc->rl_flags & RL_FLAG_PAR) != 0) { 1534 /* 1535 * XXX Should have a better way to extract station 1536 * address from EEPROM. 1537 */ 1538 for (i = 0; i < ETHER_ADDR_LEN; i++) 1539 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1540 } else { 1541 sc->rl_eewidth = RL_9356_ADDR_LEN; 1542 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1543 if (re_did != 0x8129) 1544 sc->rl_eewidth = RL_9346_ADDR_LEN; 1545 1546 /* 1547 * Get station address from the EEPROM. 1548 */ 1549 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1550 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1551 as[i] = le16toh(as[i]); 1552 bcopy(as, eaddr, ETHER_ADDR_LEN); 1553 } 1554 1555 if (sc->rl_type == RL_8169) { 1556 /* Set RX length mask and number of descriptors. */ 1557 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1558 sc->rl_txstart = RL_GTXSTART; 1559 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1560 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1561 } else { 1562 /* Set RX length mask and number of descriptors. */ 1563 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1564 sc->rl_txstart = RL_TXSTART; 1565 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1566 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1567 } 1568 1569 error = re_allocmem(dev, sc); 1570 if (error) 1571 goto fail; 1572 re_add_sysctls(sc); 1573 1574 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1575 if (ifp == NULL) { 1576 device_printf(dev, "can not if_alloc()\n"); 1577 error = ENOSPC; 1578 goto fail; 1579 } 1580 1581 /* Take controller out of deep sleep mode. */ 1582 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 1583 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 1584 CSR_WRITE_1(sc, RL_GPIO, 1585 CSR_READ_1(sc, RL_GPIO) | 0x01); 1586 else 1587 CSR_WRITE_1(sc, RL_GPIO, 1588 CSR_READ_1(sc, RL_GPIO) & ~0x01); 1589 } 1590 1591 /* Take PHY out of power down mode. */ 1592 if ((sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) { 1593 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80); 1594 if (hw_rev->rl_rev == RL_HWREV_8401E) 1595 CSR_WRITE_1(sc, 0xD1, CSR_READ_1(sc, 0xD1) & ~0x08); 1596 } 1597 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) { 1598 re_gmii_writereg(dev, 1, 0x1f, 0); 1599 re_gmii_writereg(dev, 1, 0x0e, 0); 1600 } 1601 1602 ifp->if_softc = sc; 1603 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1604 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1605 ifp->if_ioctl = re_ioctl; 1606 ifp->if_start = re_start; 1607 /* 1608 * RTL8168/8111C generates wrong IP checksummed frame if the 1609 * packet has IP options so disable TX IP checksum offloading. 1610 */ 1611 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168C || 1612 sc->rl_hwrev->rl_rev == RL_HWREV_8168C_SPIN2 || 1613 sc->rl_hwrev->rl_rev == RL_HWREV_8168CP) 1614 ifp->if_hwassist = CSUM_TCP | CSUM_UDP; 1615 else 1616 ifp->if_hwassist = CSUM_IP | CSUM_TCP | CSUM_UDP; 1617 ifp->if_hwassist |= CSUM_TSO; 1618 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 1619 ifp->if_capenable = ifp->if_capabilities; 1620 ifp->if_init = re_init; 1621 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1622 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1623 IFQ_SET_READY(&ifp->if_snd); 1624 1625 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1626 1627 #define RE_PHYAD_INTERNAL 0 1628 1629 /* Do MII setup. */ 1630 phy = RE_PHYAD_INTERNAL; 1631 if (sc->rl_type == RL_8169) 1632 phy = 1; 1633 error = mii_attach(dev, &sc->rl_miibus, ifp, re_ifmedia_upd, 1634 re_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, MIIF_DOPAUSE); 1635 if (error != 0) { 1636 device_printf(dev, "attaching PHYs failed\n"); 1637 goto fail; 1638 } 1639 1640 /* 1641 * Call MI attach routine. 1642 */ 1643 ether_ifattach(ifp, eaddr); 1644 1645 /* VLAN capability setup */ 1646 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1647 if (ifp->if_capabilities & IFCAP_HWCSUM) 1648 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1649 /* Enable WOL if PM is supported. */ 1650 if (pci_find_cap(sc->rl_dev, PCIY_PMG, ®) == 0) 1651 ifp->if_capabilities |= IFCAP_WOL; 1652 ifp->if_capenable = ifp->if_capabilities; 1653 ifp->if_capenable &= ~(IFCAP_WOL_UCAST | IFCAP_WOL_MCAST); 1654 /* 1655 * Don't enable TSO by default. It is known to generate 1656 * corrupted TCP segments(bad TCP options) under certain 1657 * circumstances. 1658 */ 1659 ifp->if_hwassist &= ~CSUM_TSO; 1660 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO); 1661 #ifdef DEVICE_POLLING 1662 ifp->if_capabilities |= IFCAP_POLLING; 1663 #endif 1664 /* 1665 * Tell the upper layer(s) we support long frames. 1666 * Must appear after the call to ether_ifattach() because 1667 * ether_ifattach() sets ifi_hdrlen to the default value. 1668 */ 1669 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1670 1671 #ifdef DEV_NETMAP 1672 re_netmap_attach(sc); 1673 #endif /* DEV_NETMAP */ 1674 #ifdef RE_DIAG 1675 /* 1676 * Perform hardware diagnostic on the original RTL8169. 1677 * Some 32-bit cards were incorrectly wired and would 1678 * malfunction if plugged into a 64-bit slot. 1679 */ 1680 1681 if (hwrev == RL_HWREV_8169) { 1682 error = re_diag(sc); 1683 if (error) { 1684 device_printf(dev, 1685 "attach aborted due to hardware diag failure\n"); 1686 ether_ifdetach(ifp); 1687 goto fail; 1688 } 1689 } 1690 #endif 1691 1692 #ifdef RE_TX_MODERATION 1693 intr_filter = 1; 1694 #endif 1695 /* Hook interrupt last to avoid having to lock softc */ 1696 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 && 1697 intr_filter == 0) { 1698 error = bus_setup_intr(dev, sc->rl_irq[0], 1699 INTR_TYPE_NET | INTR_MPSAFE, NULL, re_intr_msi, sc, 1700 &sc->rl_intrhand[0]); 1701 } else { 1702 error = bus_setup_intr(dev, sc->rl_irq[0], 1703 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1704 &sc->rl_intrhand[0]); 1705 } 1706 if (error) { 1707 device_printf(dev, "couldn't set up irq\n"); 1708 ether_ifdetach(ifp); 1709 } 1710 1711 fail: 1712 1713 if (error) 1714 re_detach(dev); 1715 1716 return (error); 1717 } 1718 1719 /* 1720 * Shutdown hardware and free up resources. This can be called any 1721 * time after the mutex has been initialized. It is called in both 1722 * the error case in attach and the normal detach case so it needs 1723 * to be careful about only freeing resources that have actually been 1724 * allocated. 1725 */ 1726 static int 1727 re_detach(device_t dev) 1728 { 1729 struct rl_softc *sc; 1730 struct ifnet *ifp; 1731 int i, rid; 1732 1733 sc = device_get_softc(dev); 1734 ifp = sc->rl_ifp; 1735 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1736 1737 /* These should only be active if attach succeeded */ 1738 if (device_is_attached(dev)) { 1739 #ifdef DEVICE_POLLING 1740 if (ifp->if_capenable & IFCAP_POLLING) 1741 ether_poll_deregister(ifp); 1742 #endif 1743 RL_LOCK(sc); 1744 #if 0 1745 sc->suspended = 1; 1746 #endif 1747 re_stop(sc); 1748 RL_UNLOCK(sc); 1749 callout_drain(&sc->rl_stat_callout); 1750 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1751 /* 1752 * Force off the IFF_UP flag here, in case someone 1753 * still had a BPF descriptor attached to this 1754 * interface. If they do, ether_ifdetach() will cause 1755 * the BPF code to try and clear the promisc mode 1756 * flag, which will bubble down to re_ioctl(), 1757 * which will try to call re_init() again. This will 1758 * turn the NIC back on and restart the MII ticker, 1759 * which will panic the system when the kernel tries 1760 * to invoke the re_tick() function that isn't there 1761 * anymore. 1762 */ 1763 ifp->if_flags &= ~IFF_UP; 1764 ether_ifdetach(ifp); 1765 } 1766 if (sc->rl_miibus) 1767 device_delete_child(dev, sc->rl_miibus); 1768 bus_generic_detach(dev); 1769 1770 /* 1771 * The rest is resource deallocation, so we should already be 1772 * stopped here. 1773 */ 1774 1775 if (sc->rl_intrhand[0] != NULL) { 1776 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]); 1777 sc->rl_intrhand[0] = NULL; 1778 } 1779 if (ifp != NULL) { 1780 #ifdef DEV_NETMAP 1781 netmap_detach(ifp); 1782 #endif /* DEV_NETMAP */ 1783 if_free(ifp); 1784 } 1785 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) 1786 rid = 0; 1787 else 1788 rid = 1; 1789 if (sc->rl_irq[0] != NULL) { 1790 bus_release_resource(dev, SYS_RES_IRQ, rid, sc->rl_irq[0]); 1791 sc->rl_irq[0] = NULL; 1792 } 1793 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0) 1794 pci_release_msi(dev); 1795 if (sc->rl_res_pba) { 1796 rid = PCIR_BAR(4); 1797 bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->rl_res_pba); 1798 } 1799 if (sc->rl_res) 1800 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, 1801 sc->rl_res); 1802 1803 /* Unload and free the RX DMA ring memory and map */ 1804 1805 if (sc->rl_ldata.rl_rx_list_tag) { 1806 if (sc->rl_ldata.rl_rx_list_map) 1807 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1808 sc->rl_ldata.rl_rx_list_map); 1809 if (sc->rl_ldata.rl_rx_list_map && sc->rl_ldata.rl_rx_list) 1810 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1811 sc->rl_ldata.rl_rx_list, 1812 sc->rl_ldata.rl_rx_list_map); 1813 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1814 } 1815 1816 /* Unload and free the TX DMA ring memory and map */ 1817 1818 if (sc->rl_ldata.rl_tx_list_tag) { 1819 if (sc->rl_ldata.rl_tx_list_map) 1820 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1821 sc->rl_ldata.rl_tx_list_map); 1822 if (sc->rl_ldata.rl_tx_list_map && sc->rl_ldata.rl_tx_list) 1823 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1824 sc->rl_ldata.rl_tx_list, 1825 sc->rl_ldata.rl_tx_list_map); 1826 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1827 } 1828 1829 /* Destroy all the RX and TX buffer maps */ 1830 1831 if (sc->rl_ldata.rl_tx_mtag) { 1832 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1833 if (sc->rl_ldata.rl_tx_desc[i].tx_dmamap) 1834 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1835 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1836 } 1837 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1838 } 1839 if (sc->rl_ldata.rl_rx_mtag) { 1840 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1841 if (sc->rl_ldata.rl_rx_desc[i].rx_dmamap) 1842 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1843 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1844 } 1845 if (sc->rl_ldata.rl_rx_sparemap) 1846 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1847 sc->rl_ldata.rl_rx_sparemap); 1848 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1849 } 1850 if (sc->rl_ldata.rl_jrx_mtag) { 1851 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1852 if (sc->rl_ldata.rl_jrx_desc[i].rx_dmamap) 1853 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag, 1854 sc->rl_ldata.rl_jrx_desc[i].rx_dmamap); 1855 } 1856 if (sc->rl_ldata.rl_jrx_sparemap) 1857 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag, 1858 sc->rl_ldata.rl_jrx_sparemap); 1859 bus_dma_tag_destroy(sc->rl_ldata.rl_jrx_mtag); 1860 } 1861 /* Unload and free the stats buffer and map */ 1862 1863 if (sc->rl_ldata.rl_stag) { 1864 if (sc->rl_ldata.rl_smap) 1865 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1866 sc->rl_ldata.rl_smap); 1867 if (sc->rl_ldata.rl_smap && sc->rl_ldata.rl_stats) 1868 bus_dmamem_free(sc->rl_ldata.rl_stag, 1869 sc->rl_ldata.rl_stats, sc->rl_ldata.rl_smap); 1870 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1871 } 1872 1873 if (sc->rl_parent_tag) 1874 bus_dma_tag_destroy(sc->rl_parent_tag); 1875 1876 mtx_destroy(&sc->rl_mtx); 1877 1878 return (0); 1879 } 1880 1881 static __inline void 1882 re_discard_rxbuf(struct rl_softc *sc, int idx) 1883 { 1884 struct rl_desc *desc; 1885 struct rl_rxdesc *rxd; 1886 uint32_t cmdstat; 1887 1888 if (sc->rl_ifp->if_mtu > RL_MTU && 1889 (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) 1890 rxd = &sc->rl_ldata.rl_jrx_desc[idx]; 1891 else 1892 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1893 desc = &sc->rl_ldata.rl_rx_list[idx]; 1894 desc->rl_vlanctl = 0; 1895 cmdstat = rxd->rx_size; 1896 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1897 cmdstat |= RL_RDESC_CMD_EOR; 1898 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1899 } 1900 1901 static int 1902 re_newbuf(struct rl_softc *sc, int idx) 1903 { 1904 struct mbuf *m; 1905 struct rl_rxdesc *rxd; 1906 bus_dma_segment_t segs[1]; 1907 bus_dmamap_t map; 1908 struct rl_desc *desc; 1909 uint32_t cmdstat; 1910 int error, nsegs; 1911 1912 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1913 if (m == NULL) 1914 return (ENOBUFS); 1915 1916 m->m_len = m->m_pkthdr.len = MCLBYTES; 1917 #ifdef RE_FIXUP_RX 1918 /* 1919 * This is part of an evil trick to deal with non-x86 platforms. 1920 * The RealTek chip requires RX buffers to be aligned on 64-bit 1921 * boundaries, but that will hose non-x86 machines. To get around 1922 * this, we leave some empty space at the start of each buffer 1923 * and for non-x86 hosts, we copy the buffer back six bytes 1924 * to achieve word alignment. This is slightly more efficient 1925 * than allocating a new buffer, copying the contents, and 1926 * discarding the old buffer. 1927 */ 1928 m_adj(m, RE_ETHER_ALIGN); 1929 #endif 1930 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1931 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1932 if (error != 0) { 1933 m_freem(m); 1934 return (ENOBUFS); 1935 } 1936 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1937 1938 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1939 if (rxd->rx_m != NULL) { 1940 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1941 BUS_DMASYNC_POSTREAD); 1942 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1943 } 1944 1945 rxd->rx_m = m; 1946 map = rxd->rx_dmamap; 1947 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1948 rxd->rx_size = segs[0].ds_len; 1949 sc->rl_ldata.rl_rx_sparemap = map; 1950 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1951 BUS_DMASYNC_PREREAD); 1952 1953 desc = &sc->rl_ldata.rl_rx_list[idx]; 1954 desc->rl_vlanctl = 0; 1955 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1956 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1957 cmdstat = segs[0].ds_len; 1958 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1959 cmdstat |= RL_RDESC_CMD_EOR; 1960 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1961 1962 return (0); 1963 } 1964 1965 static int 1966 re_jumbo_newbuf(struct rl_softc *sc, int idx) 1967 { 1968 struct mbuf *m; 1969 struct rl_rxdesc *rxd; 1970 bus_dma_segment_t segs[1]; 1971 bus_dmamap_t map; 1972 struct rl_desc *desc; 1973 uint32_t cmdstat; 1974 int error, nsegs; 1975 1976 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 1977 if (m == NULL) 1978 return (ENOBUFS); 1979 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1980 #ifdef RE_FIXUP_RX 1981 m_adj(m, RE_ETHER_ALIGN); 1982 #endif 1983 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_jrx_mtag, 1984 sc->rl_ldata.rl_jrx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1985 if (error != 0) { 1986 m_freem(m); 1987 return (ENOBUFS); 1988 } 1989 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1990 1991 rxd = &sc->rl_ldata.rl_jrx_desc[idx]; 1992 if (rxd->rx_m != NULL) { 1993 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap, 1994 BUS_DMASYNC_POSTREAD); 1995 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap); 1996 } 1997 1998 rxd->rx_m = m; 1999 map = rxd->rx_dmamap; 2000 rxd->rx_dmamap = sc->rl_ldata.rl_jrx_sparemap; 2001 rxd->rx_size = segs[0].ds_len; 2002 sc->rl_ldata.rl_jrx_sparemap = map; 2003 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap, 2004 BUS_DMASYNC_PREREAD); 2005 2006 desc = &sc->rl_ldata.rl_rx_list[idx]; 2007 desc->rl_vlanctl = 0; 2008 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 2009 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 2010 cmdstat = segs[0].ds_len; 2011 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 2012 cmdstat |= RL_RDESC_CMD_EOR; 2013 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 2014 2015 return (0); 2016 } 2017 2018 #ifdef RE_FIXUP_RX 2019 static __inline void 2020 re_fixup_rx(struct mbuf *m) 2021 { 2022 int i; 2023 uint16_t *src, *dst; 2024 2025 src = mtod(m, uint16_t *); 2026 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 2027 2028 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 2029 *dst++ = *src++; 2030 2031 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 2032 } 2033 #endif 2034 2035 static int 2036 re_tx_list_init(struct rl_softc *sc) 2037 { 2038 struct rl_desc *desc; 2039 int i; 2040 2041 RL_LOCK_ASSERT(sc); 2042 2043 bzero(sc->rl_ldata.rl_tx_list, 2044 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 2045 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 2046 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 2047 #ifdef DEV_NETMAP 2048 re_netmap_tx_init(sc); 2049 #endif /* DEV_NETMAP */ 2050 /* Set EOR. */ 2051 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 2052 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 2053 2054 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2055 sc->rl_ldata.rl_tx_list_map, 2056 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2057 2058 sc->rl_ldata.rl_tx_prodidx = 0; 2059 sc->rl_ldata.rl_tx_considx = 0; 2060 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 2061 2062 return (0); 2063 } 2064 2065 static int 2066 re_rx_list_init(struct rl_softc *sc) 2067 { 2068 int error, i; 2069 2070 bzero(sc->rl_ldata.rl_rx_list, 2071 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 2072 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2073 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 2074 if ((error = re_newbuf(sc, i)) != 0) 2075 return (error); 2076 } 2077 #ifdef DEV_NETMAP 2078 re_netmap_rx_init(sc); 2079 #endif /* DEV_NETMAP */ 2080 2081 /* Flush the RX descriptors */ 2082 2083 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2084 sc->rl_ldata.rl_rx_list_map, 2085 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2086 2087 sc->rl_ldata.rl_rx_prodidx = 0; 2088 sc->rl_head = sc->rl_tail = NULL; 2089 sc->rl_int_rx_act = 0; 2090 2091 return (0); 2092 } 2093 2094 static int 2095 re_jrx_list_init(struct rl_softc *sc) 2096 { 2097 int error, i; 2098 2099 bzero(sc->rl_ldata.rl_rx_list, 2100 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 2101 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2102 sc->rl_ldata.rl_jrx_desc[i].rx_m = NULL; 2103 if ((error = re_jumbo_newbuf(sc, i)) != 0) 2104 return (error); 2105 } 2106 2107 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2108 sc->rl_ldata.rl_rx_list_map, 2109 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2110 2111 sc->rl_ldata.rl_rx_prodidx = 0; 2112 sc->rl_head = sc->rl_tail = NULL; 2113 sc->rl_int_rx_act = 0; 2114 2115 return (0); 2116 } 2117 2118 /* 2119 * RX handler for C+ and 8169. For the gigE chips, we support 2120 * the reception of jumbo frames that have been fragmented 2121 * across multiple 2K mbuf cluster buffers. 2122 */ 2123 static int 2124 re_rxeof(struct rl_softc *sc, int *rx_npktsp) 2125 { 2126 struct mbuf *m; 2127 struct ifnet *ifp; 2128 int i, rxerr, total_len; 2129 struct rl_desc *cur_rx; 2130 u_int32_t rxstat, rxvlan; 2131 int jumbo, maxpkt = 16, rx_npkts = 0; 2132 2133 RL_LOCK_ASSERT(sc); 2134 2135 ifp = sc->rl_ifp; 2136 #ifdef DEV_NETMAP 2137 if (netmap_rx_irq(ifp, 0 | (NETMAP_LOCKED_ENTER|NETMAP_LOCKED_EXIT), 2138 &rx_npkts)) 2139 return 0; 2140 #endif /* DEV_NETMAP */ 2141 if (ifp->if_mtu > RL_MTU && (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) 2142 jumbo = 1; 2143 else 2144 jumbo = 0; 2145 2146 /* Invalidate the descriptor memory */ 2147 2148 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2149 sc->rl_ldata.rl_rx_list_map, 2150 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2151 2152 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 2153 i = RL_RX_DESC_NXT(sc, i)) { 2154 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2155 break; 2156 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 2157 rxstat = le32toh(cur_rx->rl_cmdstat); 2158 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 2159 break; 2160 total_len = rxstat & sc->rl_rxlenmask; 2161 rxvlan = le32toh(cur_rx->rl_vlanctl); 2162 if (jumbo != 0) 2163 m = sc->rl_ldata.rl_jrx_desc[i].rx_m; 2164 else 2165 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 2166 2167 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 2168 (rxstat & (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) != 2169 (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) { 2170 /* 2171 * RTL8168C or later controllers do not 2172 * support multi-fragment packet. 2173 */ 2174 re_discard_rxbuf(sc, i); 2175 continue; 2176 } else if ((rxstat & RL_RDESC_STAT_EOF) == 0) { 2177 if (re_newbuf(sc, i) != 0) { 2178 /* 2179 * If this is part of a multi-fragment packet, 2180 * discard all the pieces. 2181 */ 2182 if (sc->rl_head != NULL) { 2183 m_freem(sc->rl_head); 2184 sc->rl_head = sc->rl_tail = NULL; 2185 } 2186 re_discard_rxbuf(sc, i); 2187 continue; 2188 } 2189 m->m_len = RE_RX_DESC_BUFLEN; 2190 if (sc->rl_head == NULL) 2191 sc->rl_head = sc->rl_tail = m; 2192 else { 2193 m->m_flags &= ~M_PKTHDR; 2194 sc->rl_tail->m_next = m; 2195 sc->rl_tail = m; 2196 } 2197 continue; 2198 } 2199 2200 /* 2201 * NOTE: for the 8139C+, the frame length field 2202 * is always 12 bits in size, but for the gigE chips, 2203 * it is 13 bits (since the max RX frame length is 16K). 2204 * Unfortunately, all 32 bits in the status word 2205 * were already used, so to make room for the extra 2206 * length bit, RealTek took out the 'frame alignment 2207 * error' bit and shifted the other status bits 2208 * over one slot. The OWN, EOR, FS and LS bits are 2209 * still in the same places. We have already extracted 2210 * the frame length and checked the OWN bit, so rather 2211 * than using an alternate bit mapping, we shift the 2212 * status bits one space to the right so we can evaluate 2213 * them using the 8169 status as though it was in the 2214 * same format as that of the 8139C+. 2215 */ 2216 if (sc->rl_type == RL_8169) 2217 rxstat >>= 1; 2218 2219 /* 2220 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 2221 * set, but if CRC is clear, it will still be a valid frame. 2222 */ 2223 if ((rxstat & RL_RDESC_STAT_RXERRSUM) != 0) { 2224 rxerr = 1; 2225 if ((sc->rl_flags & RL_FLAG_JUMBOV2) == 0 && 2226 total_len > 8191 && 2227 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT) 2228 rxerr = 0; 2229 if (rxerr != 0) { 2230 ifp->if_ierrors++; 2231 /* 2232 * If this is part of a multi-fragment packet, 2233 * discard all the pieces. 2234 */ 2235 if (sc->rl_head != NULL) { 2236 m_freem(sc->rl_head); 2237 sc->rl_head = sc->rl_tail = NULL; 2238 } 2239 re_discard_rxbuf(sc, i); 2240 continue; 2241 } 2242 } 2243 2244 /* 2245 * If allocating a replacement mbuf fails, 2246 * reload the current one. 2247 */ 2248 if (jumbo != 0) 2249 rxerr = re_jumbo_newbuf(sc, i); 2250 else 2251 rxerr = re_newbuf(sc, i); 2252 if (rxerr != 0) { 2253 ifp->if_iqdrops++; 2254 if (sc->rl_head != NULL) { 2255 m_freem(sc->rl_head); 2256 sc->rl_head = sc->rl_tail = NULL; 2257 } 2258 re_discard_rxbuf(sc, i); 2259 continue; 2260 } 2261 2262 if (sc->rl_head != NULL) { 2263 if (jumbo != 0) 2264 m->m_len = total_len; 2265 else { 2266 m->m_len = total_len % RE_RX_DESC_BUFLEN; 2267 if (m->m_len == 0) 2268 m->m_len = RE_RX_DESC_BUFLEN; 2269 } 2270 /* 2271 * Special case: if there's 4 bytes or less 2272 * in this buffer, the mbuf can be discarded: 2273 * the last 4 bytes is the CRC, which we don't 2274 * care about anyway. 2275 */ 2276 if (m->m_len <= ETHER_CRC_LEN) { 2277 sc->rl_tail->m_len -= 2278 (ETHER_CRC_LEN - m->m_len); 2279 m_freem(m); 2280 } else { 2281 m->m_len -= ETHER_CRC_LEN; 2282 m->m_flags &= ~M_PKTHDR; 2283 sc->rl_tail->m_next = m; 2284 } 2285 m = sc->rl_head; 2286 sc->rl_head = sc->rl_tail = NULL; 2287 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 2288 } else 2289 m->m_pkthdr.len = m->m_len = 2290 (total_len - ETHER_CRC_LEN); 2291 2292 #ifdef RE_FIXUP_RX 2293 re_fixup_rx(m); 2294 #endif 2295 ifp->if_ipackets++; 2296 m->m_pkthdr.rcvif = ifp; 2297 2298 /* Do RX checksumming if enabled */ 2299 2300 if (ifp->if_capenable & IFCAP_RXCSUM) { 2301 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2302 /* Check IP header checksum */ 2303 if (rxstat & RL_RDESC_STAT_PROTOID) 2304 m->m_pkthdr.csum_flags |= 2305 CSUM_IP_CHECKED; 2306 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 2307 m->m_pkthdr.csum_flags |= 2308 CSUM_IP_VALID; 2309 2310 /* Check TCP/UDP checksum */ 2311 if ((RL_TCPPKT(rxstat) && 2312 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 2313 (RL_UDPPKT(rxstat) && 2314 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 2315 m->m_pkthdr.csum_flags |= 2316 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2317 m->m_pkthdr.csum_data = 0xffff; 2318 } 2319 } else { 2320 /* 2321 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP 2322 */ 2323 if ((rxstat & RL_RDESC_STAT_PROTOID) && 2324 (rxvlan & RL_RDESC_IPV4)) 2325 m->m_pkthdr.csum_flags |= 2326 CSUM_IP_CHECKED; 2327 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) && 2328 (rxvlan & RL_RDESC_IPV4)) 2329 m->m_pkthdr.csum_flags |= 2330 CSUM_IP_VALID; 2331 if (((rxstat & RL_RDESC_STAT_TCP) && 2332 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 2333 ((rxstat & RL_RDESC_STAT_UDP) && 2334 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 2335 m->m_pkthdr.csum_flags |= 2336 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2337 m->m_pkthdr.csum_data = 0xffff; 2338 } 2339 } 2340 } 2341 maxpkt--; 2342 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 2343 m->m_pkthdr.ether_vtag = 2344 bswap16((rxvlan & RL_RDESC_VLANCTL_DATA)); 2345 m->m_flags |= M_VLANTAG; 2346 } 2347 RL_UNLOCK(sc); 2348 (*ifp->if_input)(ifp, m); 2349 RL_LOCK(sc); 2350 rx_npkts++; 2351 } 2352 2353 /* Flush the RX DMA ring */ 2354 2355 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2356 sc->rl_ldata.rl_rx_list_map, 2357 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2358 2359 sc->rl_ldata.rl_rx_prodidx = i; 2360 2361 if (rx_npktsp != NULL) 2362 *rx_npktsp = rx_npkts; 2363 if (maxpkt) 2364 return (EAGAIN); 2365 2366 return (0); 2367 } 2368 2369 static void 2370 re_txeof(struct rl_softc *sc) 2371 { 2372 struct ifnet *ifp; 2373 struct rl_txdesc *txd; 2374 u_int32_t txstat; 2375 int cons; 2376 2377 cons = sc->rl_ldata.rl_tx_considx; 2378 if (cons == sc->rl_ldata.rl_tx_prodidx) 2379 return; 2380 2381 ifp = sc->rl_ifp; 2382 #ifdef DEV_NETMAP 2383 if (netmap_tx_irq(ifp, 0 | (NETMAP_LOCKED_ENTER|NETMAP_LOCKED_EXIT))) 2384 return; 2385 #endif /* DEV_NETMAP */ 2386 /* Invalidate the TX descriptor list */ 2387 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2388 sc->rl_ldata.rl_tx_list_map, 2389 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2390 2391 for (; cons != sc->rl_ldata.rl_tx_prodidx; 2392 cons = RL_TX_DESC_NXT(sc, cons)) { 2393 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 2394 if (txstat & RL_TDESC_STAT_OWN) 2395 break; 2396 /* 2397 * We only stash mbufs in the last descriptor 2398 * in a fragment chain, which also happens to 2399 * be the only place where the TX status bits 2400 * are valid. 2401 */ 2402 if (txstat & RL_TDESC_CMD_EOF) { 2403 txd = &sc->rl_ldata.rl_tx_desc[cons]; 2404 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2405 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2406 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2407 txd->tx_dmamap); 2408 KASSERT(txd->tx_m != NULL, 2409 ("%s: freeing NULL mbufs!", __func__)); 2410 m_freem(txd->tx_m); 2411 txd->tx_m = NULL; 2412 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 2413 RL_TDESC_STAT_COLCNT)) 2414 ifp->if_collisions++; 2415 if (txstat & RL_TDESC_STAT_TXERRSUM) 2416 ifp->if_oerrors++; 2417 else 2418 ifp->if_opackets++; 2419 } 2420 sc->rl_ldata.rl_tx_free++; 2421 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2422 } 2423 sc->rl_ldata.rl_tx_considx = cons; 2424 2425 /* No changes made to the TX ring, so no flush needed */ 2426 2427 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 2428 #ifdef RE_TX_MODERATION 2429 /* 2430 * If not all descriptors have been reaped yet, reload 2431 * the timer so that we will eventually get another 2432 * interrupt that will cause us to re-enter this routine. 2433 * This is done in case the transmitter has gone idle. 2434 */ 2435 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2436 #endif 2437 } else 2438 sc->rl_watchdog_timer = 0; 2439 } 2440 2441 static void 2442 re_tick(void *xsc) 2443 { 2444 struct rl_softc *sc; 2445 struct mii_data *mii; 2446 2447 sc = xsc; 2448 2449 RL_LOCK_ASSERT(sc); 2450 2451 mii = device_get_softc(sc->rl_miibus); 2452 mii_tick(mii); 2453 if ((sc->rl_flags & RL_FLAG_LINK) == 0) 2454 re_miibus_statchg(sc->rl_dev); 2455 /* 2456 * Reclaim transmitted frames here. Technically it is not 2457 * necessary to do here but it ensures periodic reclamation 2458 * regardless of Tx completion interrupt which seems to be 2459 * lost on PCIe based controllers under certain situations. 2460 */ 2461 re_txeof(sc); 2462 re_watchdog(sc); 2463 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2464 } 2465 2466 #ifdef DEVICE_POLLING 2467 static int 2468 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2469 { 2470 struct rl_softc *sc = ifp->if_softc; 2471 int rx_npkts = 0; 2472 2473 RL_LOCK(sc); 2474 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2475 rx_npkts = re_poll_locked(ifp, cmd, count); 2476 RL_UNLOCK(sc); 2477 return (rx_npkts); 2478 } 2479 2480 static int 2481 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2482 { 2483 struct rl_softc *sc = ifp->if_softc; 2484 int rx_npkts; 2485 2486 RL_LOCK_ASSERT(sc); 2487 2488 sc->rxcycles = count; 2489 re_rxeof(sc, &rx_npkts); 2490 re_txeof(sc); 2491 2492 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2493 re_start_locked(ifp); 2494 2495 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2496 u_int16_t status; 2497 2498 status = CSR_READ_2(sc, RL_ISR); 2499 if (status == 0xffff) 2500 return (rx_npkts); 2501 if (status) 2502 CSR_WRITE_2(sc, RL_ISR, status); 2503 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2504 (sc->rl_flags & RL_FLAG_PCIE)) 2505 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2506 2507 /* 2508 * XXX check behaviour on receiver stalls. 2509 */ 2510 2511 if (status & RL_ISR_SYSTEM_ERR) { 2512 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2513 re_init_locked(sc); 2514 } 2515 } 2516 return (rx_npkts); 2517 } 2518 #endif /* DEVICE_POLLING */ 2519 2520 static int 2521 re_intr(void *arg) 2522 { 2523 struct rl_softc *sc; 2524 uint16_t status; 2525 2526 sc = arg; 2527 2528 status = CSR_READ_2(sc, RL_ISR); 2529 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2530 return (FILTER_STRAY); 2531 CSR_WRITE_2(sc, RL_IMR, 0); 2532 2533 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2534 2535 return (FILTER_HANDLED); 2536 } 2537 2538 static void 2539 re_int_task(void *arg, int npending) 2540 { 2541 struct rl_softc *sc; 2542 struct ifnet *ifp; 2543 u_int16_t status; 2544 int rval = 0; 2545 2546 sc = arg; 2547 ifp = sc->rl_ifp; 2548 2549 RL_LOCK(sc); 2550 2551 status = CSR_READ_2(sc, RL_ISR); 2552 CSR_WRITE_2(sc, RL_ISR, status); 2553 2554 if (sc->suspended || 2555 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2556 RL_UNLOCK(sc); 2557 return; 2558 } 2559 2560 #ifdef DEVICE_POLLING 2561 if (ifp->if_capenable & IFCAP_POLLING) { 2562 RL_UNLOCK(sc); 2563 return; 2564 } 2565 #endif 2566 2567 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2568 rval = re_rxeof(sc, NULL); 2569 2570 /* 2571 * Some chips will ignore a second TX request issued 2572 * while an existing transmission is in progress. If 2573 * the transmitter goes idle but there are still 2574 * packets waiting to be sent, we need to restart the 2575 * channel here to flush them out. This only seems to 2576 * be required with the PCIe devices. 2577 */ 2578 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2579 (sc->rl_flags & RL_FLAG_PCIE)) 2580 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2581 if (status & ( 2582 #ifdef RE_TX_MODERATION 2583 RL_ISR_TIMEOUT_EXPIRED| 2584 #else 2585 RL_ISR_TX_OK| 2586 #endif 2587 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2588 re_txeof(sc); 2589 2590 if (status & RL_ISR_SYSTEM_ERR) { 2591 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2592 re_init_locked(sc); 2593 } 2594 2595 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2596 re_start_locked(ifp); 2597 2598 RL_UNLOCK(sc); 2599 2600 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2601 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2602 return; 2603 } 2604 2605 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2606 } 2607 2608 static void 2609 re_intr_msi(void *xsc) 2610 { 2611 struct rl_softc *sc; 2612 struct ifnet *ifp; 2613 uint16_t intrs, status; 2614 2615 sc = xsc; 2616 RL_LOCK(sc); 2617 2618 ifp = sc->rl_ifp; 2619 #ifdef DEVICE_POLLING 2620 if (ifp->if_capenable & IFCAP_POLLING) { 2621 RL_UNLOCK(sc); 2622 return; 2623 } 2624 #endif 2625 /* Disable interrupts. */ 2626 CSR_WRITE_2(sc, RL_IMR, 0); 2627 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2628 RL_UNLOCK(sc); 2629 return; 2630 } 2631 2632 intrs = RL_INTRS_CPLUS; 2633 status = CSR_READ_2(sc, RL_ISR); 2634 CSR_WRITE_2(sc, RL_ISR, status); 2635 if (sc->rl_int_rx_act > 0) { 2636 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW | 2637 RL_ISR_RX_OVERRUN); 2638 status &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW | 2639 RL_ISR_RX_OVERRUN); 2640 } 2641 2642 if (status & (RL_ISR_TIMEOUT_EXPIRED | RL_ISR_RX_OK | RL_ISR_RX_ERR | 2643 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) { 2644 re_rxeof(sc, NULL); 2645 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2646 if (sc->rl_int_rx_mod != 0 && 2647 (status & (RL_ISR_RX_OK | RL_ISR_RX_ERR | 2648 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) != 0) { 2649 /* Rearm one-shot timer. */ 2650 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2651 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | 2652 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN); 2653 sc->rl_int_rx_act = 1; 2654 } else { 2655 intrs |= RL_ISR_RX_OK | RL_ISR_RX_ERR | 2656 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN; 2657 sc->rl_int_rx_act = 0; 2658 } 2659 } 2660 } 2661 2662 /* 2663 * Some chips will ignore a second TX request issued 2664 * while an existing transmission is in progress. If 2665 * the transmitter goes idle but there are still 2666 * packets waiting to be sent, we need to restart the 2667 * channel here to flush them out. This only seems to 2668 * be required with the PCIe devices. 2669 */ 2670 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2671 (sc->rl_flags & RL_FLAG_PCIE)) 2672 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2673 if (status & (RL_ISR_TX_OK | RL_ISR_TX_ERR | RL_ISR_TX_DESC_UNAVAIL)) 2674 re_txeof(sc); 2675 2676 if (status & RL_ISR_SYSTEM_ERR) { 2677 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2678 re_init_locked(sc); 2679 } 2680 2681 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2682 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2683 re_start_locked(ifp); 2684 CSR_WRITE_2(sc, RL_IMR, intrs); 2685 } 2686 RL_UNLOCK(sc); 2687 } 2688 2689 static int 2690 re_encap(struct rl_softc *sc, struct mbuf **m_head) 2691 { 2692 struct rl_txdesc *txd, *txd_last; 2693 bus_dma_segment_t segs[RL_NTXSEGS]; 2694 bus_dmamap_t map; 2695 struct mbuf *m_new; 2696 struct rl_desc *desc; 2697 int nsegs, prod; 2698 int i, error, ei, si; 2699 int padlen; 2700 uint32_t cmdstat, csum_flags, vlanctl; 2701 2702 RL_LOCK_ASSERT(sc); 2703 M_ASSERTPKTHDR((*m_head)); 2704 2705 /* 2706 * With some of the RealTek chips, using the checksum offload 2707 * support in conjunction with the autopadding feature results 2708 * in the transmission of corrupt frames. For example, if we 2709 * need to send a really small IP fragment that's less than 60 2710 * bytes in size, and IP header checksumming is enabled, the 2711 * resulting ethernet frame that appears on the wire will 2712 * have garbled payload. To work around this, if TX IP checksum 2713 * offload is enabled, we always manually pad short frames out 2714 * to the minimum ethernet frame size. 2715 */ 2716 if ((sc->rl_flags & RL_FLAG_AUTOPAD) == 0 && 2717 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN && 2718 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) { 2719 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2720 if (M_WRITABLE(*m_head) == 0) { 2721 /* Get a writable copy. */ 2722 m_new = m_dup(*m_head, M_NOWAIT); 2723 m_freem(*m_head); 2724 if (m_new == NULL) { 2725 *m_head = NULL; 2726 return (ENOBUFS); 2727 } 2728 *m_head = m_new; 2729 } 2730 if ((*m_head)->m_next != NULL || 2731 M_TRAILINGSPACE(*m_head) < padlen) { 2732 m_new = m_defrag(*m_head, M_NOWAIT); 2733 if (m_new == NULL) { 2734 m_freem(*m_head); 2735 *m_head = NULL; 2736 return (ENOBUFS); 2737 } 2738 } else 2739 m_new = *m_head; 2740 2741 /* 2742 * Manually pad short frames, and zero the pad space 2743 * to avoid leaking data. 2744 */ 2745 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2746 m_new->m_pkthdr.len += padlen; 2747 m_new->m_len = m_new->m_pkthdr.len; 2748 *m_head = m_new; 2749 } 2750 2751 prod = sc->rl_ldata.rl_tx_prodidx; 2752 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2753 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2754 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2755 if (error == EFBIG) { 2756 m_new = m_collapse(*m_head, M_NOWAIT, RL_NTXSEGS); 2757 if (m_new == NULL) { 2758 m_freem(*m_head); 2759 *m_head = NULL; 2760 return (ENOBUFS); 2761 } 2762 *m_head = m_new; 2763 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2764 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2765 if (error != 0) { 2766 m_freem(*m_head); 2767 *m_head = NULL; 2768 return (error); 2769 } 2770 } else if (error != 0) 2771 return (error); 2772 if (nsegs == 0) { 2773 m_freem(*m_head); 2774 *m_head = NULL; 2775 return (EIO); 2776 } 2777 2778 /* Check for number of available descriptors. */ 2779 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2780 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2781 return (ENOBUFS); 2782 } 2783 2784 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2785 BUS_DMASYNC_PREWRITE); 2786 2787 /* 2788 * Set up checksum offload. Note: checksum offload bits must 2789 * appear in all descriptors of a multi-descriptor transmit 2790 * attempt. This is according to testing done with an 8169 2791 * chip. This is a requirement. 2792 */ 2793 vlanctl = 0; 2794 csum_flags = 0; 2795 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2796 if ((sc->rl_flags & RL_FLAG_DESCV2) != 0) { 2797 csum_flags |= RL_TDESC_CMD_LGSEND; 2798 vlanctl |= ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2799 RL_TDESC_CMD_MSSVALV2_SHIFT); 2800 } else { 2801 csum_flags |= RL_TDESC_CMD_LGSEND | 2802 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2803 RL_TDESC_CMD_MSSVAL_SHIFT); 2804 } 2805 } else { 2806 /* 2807 * Unconditionally enable IP checksum if TCP or UDP 2808 * checksum is required. Otherwise, TCP/UDP checksum 2809 * doesn't make effects. 2810 */ 2811 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) { 2812 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2813 csum_flags |= RL_TDESC_CMD_IPCSUM; 2814 if (((*m_head)->m_pkthdr.csum_flags & 2815 CSUM_TCP) != 0) 2816 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2817 if (((*m_head)->m_pkthdr.csum_flags & 2818 CSUM_UDP) != 0) 2819 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2820 } else { 2821 vlanctl |= RL_TDESC_CMD_IPCSUMV2; 2822 if (((*m_head)->m_pkthdr.csum_flags & 2823 CSUM_TCP) != 0) 2824 vlanctl |= RL_TDESC_CMD_TCPCSUMV2; 2825 if (((*m_head)->m_pkthdr.csum_flags & 2826 CSUM_UDP) != 0) 2827 vlanctl |= RL_TDESC_CMD_UDPCSUMV2; 2828 } 2829 } 2830 } 2831 2832 /* 2833 * Set up hardware VLAN tagging. Note: vlan tag info must 2834 * appear in all descriptors of a multi-descriptor 2835 * transmission attempt. 2836 */ 2837 if ((*m_head)->m_flags & M_VLANTAG) 2838 vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) | 2839 RL_TDESC_VLANCTL_TAG; 2840 2841 si = prod; 2842 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2843 desc = &sc->rl_ldata.rl_tx_list[prod]; 2844 desc->rl_vlanctl = htole32(vlanctl); 2845 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2846 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2847 cmdstat = segs[i].ds_len; 2848 if (i != 0) 2849 cmdstat |= RL_TDESC_CMD_OWN; 2850 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2851 cmdstat |= RL_TDESC_CMD_EOR; 2852 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2853 sc->rl_ldata.rl_tx_free--; 2854 } 2855 /* Update producer index. */ 2856 sc->rl_ldata.rl_tx_prodidx = prod; 2857 2858 /* Set EOF on the last descriptor. */ 2859 ei = RL_TX_DESC_PRV(sc, prod); 2860 desc = &sc->rl_ldata.rl_tx_list[ei]; 2861 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2862 2863 desc = &sc->rl_ldata.rl_tx_list[si]; 2864 /* Set SOF and transfer ownership of packet to the chip. */ 2865 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2866 2867 /* 2868 * Insure that the map for this transmission 2869 * is placed at the array index of the last descriptor 2870 * in this chain. (Swap last and first dmamaps.) 2871 */ 2872 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2873 map = txd->tx_dmamap; 2874 txd->tx_dmamap = txd_last->tx_dmamap; 2875 txd_last->tx_dmamap = map; 2876 txd_last->tx_m = *m_head; 2877 2878 return (0); 2879 } 2880 2881 static void 2882 re_start(struct ifnet *ifp) 2883 { 2884 struct rl_softc *sc; 2885 2886 sc = ifp->if_softc; 2887 RL_LOCK(sc); 2888 re_start_locked(ifp); 2889 RL_UNLOCK(sc); 2890 } 2891 2892 /* 2893 * Main transmit routine for C+ and gigE NICs. 2894 */ 2895 static void 2896 re_start_locked(struct ifnet *ifp) 2897 { 2898 struct rl_softc *sc; 2899 struct mbuf *m_head; 2900 int queued; 2901 2902 sc = ifp->if_softc; 2903 2904 #ifdef DEV_NETMAP 2905 /* XXX is this necessary ? */ 2906 if (ifp->if_capenable & IFCAP_NETMAP) { 2907 struct netmap_kring *kring = &NA(ifp)->tx_rings[0]; 2908 if (sc->rl_ldata.rl_tx_prodidx != kring->nr_hwcur) { 2909 /* kick the tx unit */ 2910 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2911 #ifdef RE_TX_MODERATION 2912 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2913 #endif 2914 sc->rl_watchdog_timer = 5; 2915 } 2916 return; 2917 } 2918 #endif /* DEV_NETMAP */ 2919 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2920 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) 2921 return; 2922 2923 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2924 sc->rl_ldata.rl_tx_free > 1;) { 2925 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2926 if (m_head == NULL) 2927 break; 2928 2929 if (re_encap(sc, &m_head) != 0) { 2930 if (m_head == NULL) 2931 break; 2932 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2933 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2934 break; 2935 } 2936 2937 /* 2938 * If there's a BPF listener, bounce a copy of this frame 2939 * to him. 2940 */ 2941 ETHER_BPF_MTAP(ifp, m_head); 2942 2943 queued++; 2944 } 2945 2946 if (queued == 0) { 2947 #ifdef RE_TX_MODERATION 2948 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2949 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2950 #endif 2951 return; 2952 } 2953 2954 /* Flush the TX descriptors */ 2955 2956 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2957 sc->rl_ldata.rl_tx_list_map, 2958 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2959 2960 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2961 2962 #ifdef RE_TX_MODERATION 2963 /* 2964 * Use the countdown timer for interrupt moderation. 2965 * 'TX done' interrupts are disabled. Instead, we reset the 2966 * countdown timer, which will begin counting until it hits 2967 * the value in the TIMERINT register, and then trigger an 2968 * interrupt. Each time we write to the TIMERCNT register, 2969 * the timer count is reset to 0. 2970 */ 2971 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2972 #endif 2973 2974 /* 2975 * Set a timeout in case the chip goes out to lunch. 2976 */ 2977 sc->rl_watchdog_timer = 5; 2978 } 2979 2980 static void 2981 re_set_jumbo(struct rl_softc *sc, int jumbo) 2982 { 2983 2984 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168E_VL) { 2985 pci_set_max_read_req(sc->rl_dev, 4096); 2986 return; 2987 } 2988 2989 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2990 if (jumbo != 0) { 2991 CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) | 2992 RL_CFG3_JUMBO_EN0); 2993 switch (sc->rl_hwrev->rl_rev) { 2994 case RL_HWREV_8168DP: 2995 break; 2996 case RL_HWREV_8168E: 2997 CSR_WRITE_1(sc, sc->rl_cfg4, 2998 CSR_READ_1(sc, sc->rl_cfg4) | 0x01); 2999 break; 3000 default: 3001 CSR_WRITE_1(sc, sc->rl_cfg4, 3002 CSR_READ_1(sc, sc->rl_cfg4) | RL_CFG4_JUMBO_EN1); 3003 } 3004 } else { 3005 CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) & 3006 ~RL_CFG3_JUMBO_EN0); 3007 switch (sc->rl_hwrev->rl_rev) { 3008 case RL_HWREV_8168DP: 3009 break; 3010 case RL_HWREV_8168E: 3011 CSR_WRITE_1(sc, sc->rl_cfg4, 3012 CSR_READ_1(sc, sc->rl_cfg4) & ~0x01); 3013 break; 3014 default: 3015 CSR_WRITE_1(sc, sc->rl_cfg4, 3016 CSR_READ_1(sc, sc->rl_cfg4) & ~RL_CFG4_JUMBO_EN1); 3017 } 3018 } 3019 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3020 3021 switch (sc->rl_hwrev->rl_rev) { 3022 case RL_HWREV_8168DP: 3023 pci_set_max_read_req(sc->rl_dev, 4096); 3024 break; 3025 default: 3026 if (jumbo != 0) 3027 pci_set_max_read_req(sc->rl_dev, 512); 3028 else 3029 pci_set_max_read_req(sc->rl_dev, 4096); 3030 } 3031 } 3032 3033 static void 3034 re_init(void *xsc) 3035 { 3036 struct rl_softc *sc = xsc; 3037 3038 RL_LOCK(sc); 3039 re_init_locked(sc); 3040 RL_UNLOCK(sc); 3041 } 3042 3043 static void 3044 re_init_locked(struct rl_softc *sc) 3045 { 3046 struct ifnet *ifp = sc->rl_ifp; 3047 struct mii_data *mii; 3048 uint32_t reg; 3049 uint16_t cfg; 3050 union { 3051 uint32_t align_dummy; 3052 u_char eaddr[ETHER_ADDR_LEN]; 3053 } eaddr; 3054 3055 RL_LOCK_ASSERT(sc); 3056 3057 mii = device_get_softc(sc->rl_miibus); 3058 3059 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3060 return; 3061 3062 /* 3063 * Cancel pending I/O and free all RX/TX buffers. 3064 */ 3065 re_stop(sc); 3066 3067 /* Put controller into known state. */ 3068 re_reset(sc); 3069 3070 /* 3071 * For C+ mode, initialize the RX descriptors and mbufs. 3072 */ 3073 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3074 if (ifp->if_mtu > RL_MTU) { 3075 if (re_jrx_list_init(sc) != 0) { 3076 device_printf(sc->rl_dev, 3077 "no memory for jumbo RX buffers\n"); 3078 re_stop(sc); 3079 return; 3080 } 3081 /* Disable checksum offloading for jumbo frames. */ 3082 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_TSO4); 3083 ifp->if_hwassist &= ~(RE_CSUM_FEATURES | CSUM_TSO); 3084 } else { 3085 if (re_rx_list_init(sc) != 0) { 3086 device_printf(sc->rl_dev, 3087 "no memory for RX buffers\n"); 3088 re_stop(sc); 3089 return; 3090 } 3091 } 3092 re_set_jumbo(sc, ifp->if_mtu > RL_MTU); 3093 } else { 3094 if (re_rx_list_init(sc) != 0) { 3095 device_printf(sc->rl_dev, "no memory for RX buffers\n"); 3096 re_stop(sc); 3097 return; 3098 } 3099 if ((sc->rl_flags & RL_FLAG_PCIE) != 0 && 3100 pci_get_device(sc->rl_dev) != RT_DEVICEID_8101E) { 3101 if (ifp->if_mtu > RL_MTU) 3102 pci_set_max_read_req(sc->rl_dev, 512); 3103 else 3104 pci_set_max_read_req(sc->rl_dev, 4096); 3105 } 3106 } 3107 re_tx_list_init(sc); 3108 3109 /* 3110 * Enable C+ RX and TX mode, as well as VLAN stripping and 3111 * RX checksum offload. We must configure the C+ register 3112 * before all others. 3113 */ 3114 cfg = RL_CPLUSCMD_PCI_MRW; 3115 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 3116 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 3117 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3118 cfg |= RL_CPLUSCMD_VLANSTRIP; 3119 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) { 3120 cfg |= RL_CPLUSCMD_MACSTAT_DIS; 3121 /* XXX magic. */ 3122 cfg |= 0x0001; 3123 } else 3124 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB; 3125 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg); 3126 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SC || 3127 sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) { 3128 reg = 0x000fff00; 3129 if ((CSR_READ_1(sc, sc->rl_cfg2) & RL_CFG2_PCI66MHZ) != 0) 3130 reg |= 0x000000ff; 3131 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) 3132 reg |= 0x00f00000; 3133 CSR_WRITE_4(sc, 0x7c, reg); 3134 /* Disable interrupt mitigation. */ 3135 CSR_WRITE_2(sc, 0xe2, 0); 3136 } 3137 /* 3138 * Disable TSO if interface MTU size is greater than MSS 3139 * allowed in controller. 3140 */ 3141 if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) { 3142 ifp->if_capenable &= ~IFCAP_TSO4; 3143 ifp->if_hwassist &= ~CSUM_TSO; 3144 } 3145 3146 /* 3147 * Init our MAC address. Even though the chipset 3148 * documentation doesn't mention it, we need to enter "Config 3149 * register write enable" mode to modify the ID registers. 3150 */ 3151 /* Copy MAC address on stack to align. */ 3152 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 3153 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 3154 CSR_WRITE_4(sc, RL_IDR0, 3155 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 3156 CSR_WRITE_4(sc, RL_IDR4, 3157 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 3158 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3159 3160 /* 3161 * Load the addresses of the RX and TX lists into the chip. 3162 */ 3163 3164 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 3165 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 3166 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 3167 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 3168 3169 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 3170 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 3171 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 3172 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 3173 3174 /* 3175 * Enable transmit and receive. 3176 */ 3177 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 3178 3179 /* 3180 * Set the initial TX configuration. 3181 */ 3182 if (sc->rl_testmode) { 3183 if (sc->rl_type == RL_8169) 3184 CSR_WRITE_4(sc, RL_TXCFG, 3185 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 3186 else 3187 CSR_WRITE_4(sc, RL_TXCFG, 3188 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 3189 } else 3190 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 3191 3192 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 3193 3194 /* 3195 * Set the initial RX configuration. 3196 */ 3197 re_set_rxmode(sc); 3198 3199 /* Configure interrupt moderation. */ 3200 if (sc->rl_type == RL_8169) { 3201 /* Magic from vendor. */ 3202 CSR_WRITE_2(sc, RL_INTRMOD, 0x5100); 3203 } 3204 3205 #ifdef DEVICE_POLLING 3206 /* 3207 * Disable interrupts if we are polling. 3208 */ 3209 if (ifp->if_capenable & IFCAP_POLLING) 3210 CSR_WRITE_2(sc, RL_IMR, 0); 3211 else /* otherwise ... */ 3212 #endif 3213 3214 /* 3215 * Enable interrupts. 3216 */ 3217 if (sc->rl_testmode) 3218 CSR_WRITE_2(sc, RL_IMR, 0); 3219 else 3220 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 3221 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 3222 3223 /* Set initial TX threshold */ 3224 sc->rl_txthresh = RL_TX_THRESH_INIT; 3225 3226 /* Start RX/TX process. */ 3227 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 3228 #ifdef notdef 3229 /* Enable receiver and transmitter. */ 3230 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 3231 #endif 3232 3233 /* 3234 * Initialize the timer interrupt register so that 3235 * a timer interrupt will be generated once the timer 3236 * reaches a certain number of ticks. The timer is 3237 * reloaded on each transmit. 3238 */ 3239 #ifdef RE_TX_MODERATION 3240 /* 3241 * Use timer interrupt register to moderate TX interrupt 3242 * moderation, which dramatically improves TX frame rate. 3243 */ 3244 if (sc->rl_type == RL_8169) 3245 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 3246 else 3247 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 3248 #else 3249 /* 3250 * Use timer interrupt register to moderate RX interrupt 3251 * moderation. 3252 */ 3253 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 && 3254 intr_filter == 0) { 3255 if (sc->rl_type == RL_8169) 3256 CSR_WRITE_4(sc, RL_TIMERINT_8169, 3257 RL_USECS(sc->rl_int_rx_mod)); 3258 } else { 3259 if (sc->rl_type == RL_8169) 3260 CSR_WRITE_4(sc, RL_TIMERINT_8169, RL_USECS(0)); 3261 } 3262 #endif 3263 3264 /* 3265 * For 8169 gigE NICs, set the max allowed RX packet 3266 * size so we can receive jumbo frames. 3267 */ 3268 if (sc->rl_type == RL_8169) { 3269 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3270 /* 3271 * For controllers that use new jumbo frame scheme, 3272 * set maximum size of jumbo frame depending on 3273 * controller revisions. 3274 */ 3275 if (ifp->if_mtu > RL_MTU) 3276 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 3277 sc->rl_hwrev->rl_max_mtu + 3278 ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN + 3279 ETHER_CRC_LEN); 3280 else 3281 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 3282 RE_RX_DESC_BUFLEN); 3283 } else if ((sc->rl_flags & RL_FLAG_PCIE) != 0 && 3284 sc->rl_hwrev->rl_max_mtu == RL_MTU) { 3285 /* RTL810x has no jumbo frame support. */ 3286 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, RE_RX_DESC_BUFLEN); 3287 } else 3288 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 3289 } 3290 3291 if (sc->rl_testmode) 3292 return; 3293 3294 CSR_WRITE_1(sc, sc->rl_cfg1, CSR_READ_1(sc, sc->rl_cfg1) | 3295 RL_CFG1_DRVLOAD); 3296 3297 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3298 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3299 3300 sc->rl_flags &= ~RL_FLAG_LINK; 3301 mii_mediachg(mii); 3302 3303 sc->rl_watchdog_timer = 0; 3304 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 3305 } 3306 3307 /* 3308 * Set media options. 3309 */ 3310 static int 3311 re_ifmedia_upd(struct ifnet *ifp) 3312 { 3313 struct rl_softc *sc; 3314 struct mii_data *mii; 3315 int error; 3316 3317 sc = ifp->if_softc; 3318 mii = device_get_softc(sc->rl_miibus); 3319 RL_LOCK(sc); 3320 error = mii_mediachg(mii); 3321 RL_UNLOCK(sc); 3322 3323 return (error); 3324 } 3325 3326 /* 3327 * Report current media status. 3328 */ 3329 static void 3330 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3331 { 3332 struct rl_softc *sc; 3333 struct mii_data *mii; 3334 3335 sc = ifp->if_softc; 3336 mii = device_get_softc(sc->rl_miibus); 3337 3338 RL_LOCK(sc); 3339 mii_pollstat(mii); 3340 ifmr->ifm_active = mii->mii_media_active; 3341 ifmr->ifm_status = mii->mii_media_status; 3342 RL_UNLOCK(sc); 3343 } 3344 3345 static int 3346 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3347 { 3348 struct rl_softc *sc = ifp->if_softc; 3349 struct ifreq *ifr = (struct ifreq *) data; 3350 struct mii_data *mii; 3351 uint32_t rev; 3352 int error = 0; 3353 3354 switch (command) { 3355 case SIOCSIFMTU: 3356 if (ifr->ifr_mtu < ETHERMIN || 3357 ifr->ifr_mtu > sc->rl_hwrev->rl_max_mtu || 3358 ((sc->rl_flags & RL_FLAG_FASTETHER) != 0 && 3359 ifr->ifr_mtu > RL_MTU)) { 3360 error = EINVAL; 3361 break; 3362 } 3363 RL_LOCK(sc); 3364 if (ifp->if_mtu != ifr->ifr_mtu) { 3365 ifp->if_mtu = ifr->ifr_mtu; 3366 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 3367 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3368 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3369 re_init_locked(sc); 3370 } 3371 if (ifp->if_mtu > RL_TSO_MTU && 3372 (ifp->if_capenable & IFCAP_TSO4) != 0) { 3373 ifp->if_capenable &= ~(IFCAP_TSO4 | 3374 IFCAP_VLAN_HWTSO); 3375 ifp->if_hwassist &= ~CSUM_TSO; 3376 } 3377 VLAN_CAPABILITIES(ifp); 3378 } 3379 RL_UNLOCK(sc); 3380 break; 3381 case SIOCSIFFLAGS: 3382 RL_LOCK(sc); 3383 if ((ifp->if_flags & IFF_UP) != 0) { 3384 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3385 if (((ifp->if_flags ^ sc->rl_if_flags) 3386 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 3387 re_set_rxmode(sc); 3388 } else 3389 re_init_locked(sc); 3390 } else { 3391 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3392 re_stop(sc); 3393 } 3394 sc->rl_if_flags = ifp->if_flags; 3395 RL_UNLOCK(sc); 3396 break; 3397 case SIOCADDMULTI: 3398 case SIOCDELMULTI: 3399 RL_LOCK(sc); 3400 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3401 re_set_rxmode(sc); 3402 RL_UNLOCK(sc); 3403 break; 3404 case SIOCGIFMEDIA: 3405 case SIOCSIFMEDIA: 3406 mii = device_get_softc(sc->rl_miibus); 3407 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3408 break; 3409 case SIOCSIFCAP: 3410 { 3411 int mask, reinit; 3412 3413 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3414 reinit = 0; 3415 #ifdef DEVICE_POLLING 3416 if (mask & IFCAP_POLLING) { 3417 if (ifr->ifr_reqcap & IFCAP_POLLING) { 3418 error = ether_poll_register(re_poll, ifp); 3419 if (error) 3420 return (error); 3421 RL_LOCK(sc); 3422 /* Disable interrupts */ 3423 CSR_WRITE_2(sc, RL_IMR, 0x0000); 3424 ifp->if_capenable |= IFCAP_POLLING; 3425 RL_UNLOCK(sc); 3426 } else { 3427 error = ether_poll_deregister(ifp); 3428 /* Enable interrupts. */ 3429 RL_LOCK(sc); 3430 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 3431 ifp->if_capenable &= ~IFCAP_POLLING; 3432 RL_UNLOCK(sc); 3433 } 3434 } 3435 #endif /* DEVICE_POLLING */ 3436 RL_LOCK(sc); 3437 if ((mask & IFCAP_TXCSUM) != 0 && 3438 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 3439 ifp->if_capenable ^= IFCAP_TXCSUM; 3440 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) { 3441 rev = sc->rl_hwrev->rl_rev; 3442 if (rev == RL_HWREV_8168C || 3443 rev == RL_HWREV_8168C_SPIN2 || 3444 rev == RL_HWREV_8168CP) 3445 ifp->if_hwassist |= CSUM_TCP | CSUM_UDP; 3446 else 3447 ifp->if_hwassist |= RE_CSUM_FEATURES; 3448 } else 3449 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 3450 reinit = 1; 3451 } 3452 if ((mask & IFCAP_RXCSUM) != 0 && 3453 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 3454 ifp->if_capenable ^= IFCAP_RXCSUM; 3455 reinit = 1; 3456 } 3457 if ((mask & IFCAP_TSO4) != 0 && 3458 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 3459 ifp->if_capenable ^= IFCAP_TSO4; 3460 if ((IFCAP_TSO4 & ifp->if_capenable) != 0) 3461 ifp->if_hwassist |= CSUM_TSO; 3462 else 3463 ifp->if_hwassist &= ~CSUM_TSO; 3464 if (ifp->if_mtu > RL_TSO_MTU && 3465 (ifp->if_capenable & IFCAP_TSO4) != 0) { 3466 ifp->if_capenable &= ~IFCAP_TSO4; 3467 ifp->if_hwassist &= ~CSUM_TSO; 3468 } 3469 } 3470 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 3471 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 3472 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 3473 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3474 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 3475 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 3476 /* TSO over VLAN requires VLAN hardware tagging. */ 3477 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 3478 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 3479 reinit = 1; 3480 } 3481 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 3482 (mask & (IFCAP_HWCSUM | IFCAP_TSO4 | 3483 IFCAP_VLAN_HWTSO)) != 0) 3484 reinit = 1; 3485 if ((mask & IFCAP_WOL) != 0 && 3486 (ifp->if_capabilities & IFCAP_WOL) != 0) { 3487 if ((mask & IFCAP_WOL_UCAST) != 0) 3488 ifp->if_capenable ^= IFCAP_WOL_UCAST; 3489 if ((mask & IFCAP_WOL_MCAST) != 0) 3490 ifp->if_capenable ^= IFCAP_WOL_MCAST; 3491 if ((mask & IFCAP_WOL_MAGIC) != 0) 3492 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 3493 } 3494 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) { 3495 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3496 re_init_locked(sc); 3497 } 3498 RL_UNLOCK(sc); 3499 VLAN_CAPABILITIES(ifp); 3500 } 3501 break; 3502 default: 3503 error = ether_ioctl(ifp, command, data); 3504 break; 3505 } 3506 3507 return (error); 3508 } 3509 3510 static void 3511 re_watchdog(struct rl_softc *sc) 3512 { 3513 struct ifnet *ifp; 3514 3515 RL_LOCK_ASSERT(sc); 3516 3517 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 3518 return; 3519 3520 ifp = sc->rl_ifp; 3521 re_txeof(sc); 3522 if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) { 3523 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 3524 "-- recovering\n"); 3525 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3526 re_start_locked(ifp); 3527 return; 3528 } 3529 3530 if_printf(ifp, "watchdog timeout\n"); 3531 ifp->if_oerrors++; 3532 3533 re_rxeof(sc, NULL); 3534 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3535 re_init_locked(sc); 3536 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3537 re_start_locked(ifp); 3538 } 3539 3540 /* 3541 * Stop the adapter and free any mbufs allocated to the 3542 * RX and TX lists. 3543 */ 3544 static void 3545 re_stop(struct rl_softc *sc) 3546 { 3547 int i; 3548 struct ifnet *ifp; 3549 struct rl_txdesc *txd; 3550 struct rl_rxdesc *rxd; 3551 3552 RL_LOCK_ASSERT(sc); 3553 3554 ifp = sc->rl_ifp; 3555 3556 sc->rl_watchdog_timer = 0; 3557 callout_stop(&sc->rl_stat_callout); 3558 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3559 3560 /* 3561 * Disable accepting frames to put RX MAC into idle state. 3562 * Otherwise it's possible to get frames while stop command 3563 * execution is in progress and controller can DMA the frame 3564 * to already freed RX buffer during that period. 3565 */ 3566 CSR_WRITE_4(sc, RL_RXCFG, CSR_READ_4(sc, RL_RXCFG) & 3567 ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_MULTI | 3568 RL_RXCFG_RX_BROAD)); 3569 3570 if ((sc->rl_flags & RL_FLAG_WAIT_TXPOLL) != 0) { 3571 for (i = RL_TIMEOUT; i > 0; i--) { 3572 if ((CSR_READ_1(sc, sc->rl_txstart) & 3573 RL_TXSTART_START) == 0) 3574 break; 3575 DELAY(20); 3576 } 3577 if (i == 0) 3578 device_printf(sc->rl_dev, 3579 "stopping TX poll timed out!\n"); 3580 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 3581 } else if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0) { 3582 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB | 3583 RL_CMD_RX_ENB); 3584 if ((sc->rl_flags & RL_FLAG_CMDSTOP_WAIT_TXQ) != 0) { 3585 for (i = RL_TIMEOUT; i > 0; i--) { 3586 if ((CSR_READ_4(sc, RL_TXCFG) & 3587 RL_TXCFG_QUEUE_EMPTY) != 0) 3588 break; 3589 DELAY(100); 3590 } 3591 if (i == 0) 3592 device_printf(sc->rl_dev, 3593 "stopping TXQ timed out!\n"); 3594 } 3595 } else 3596 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 3597 DELAY(1000); 3598 CSR_WRITE_2(sc, RL_IMR, 0x0000); 3599 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 3600 3601 if (sc->rl_head != NULL) { 3602 m_freem(sc->rl_head); 3603 sc->rl_head = sc->rl_tail = NULL; 3604 } 3605 3606 /* Free the TX list buffers. */ 3607 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 3608 txd = &sc->rl_ldata.rl_tx_desc[i]; 3609 if (txd->tx_m != NULL) { 3610 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 3611 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3612 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 3613 txd->tx_dmamap); 3614 m_freem(txd->tx_m); 3615 txd->tx_m = NULL; 3616 } 3617 } 3618 3619 /* Free the RX list buffers. */ 3620 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 3621 rxd = &sc->rl_ldata.rl_rx_desc[i]; 3622 if (rxd->rx_m != NULL) { 3623 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 3624 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3625 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 3626 rxd->rx_dmamap); 3627 m_freem(rxd->rx_m); 3628 rxd->rx_m = NULL; 3629 } 3630 } 3631 3632 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3633 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 3634 rxd = &sc->rl_ldata.rl_jrx_desc[i]; 3635 if (rxd->rx_m != NULL) { 3636 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, 3637 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3638 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, 3639 rxd->rx_dmamap); 3640 m_freem(rxd->rx_m); 3641 rxd->rx_m = NULL; 3642 } 3643 } 3644 } 3645 } 3646 3647 /* 3648 * Device suspend routine. Stop the interface and save some PCI 3649 * settings in case the BIOS doesn't restore them properly on 3650 * resume. 3651 */ 3652 static int 3653 re_suspend(device_t dev) 3654 { 3655 struct rl_softc *sc; 3656 3657 sc = device_get_softc(dev); 3658 3659 RL_LOCK(sc); 3660 re_stop(sc); 3661 re_setwol(sc); 3662 sc->suspended = 1; 3663 RL_UNLOCK(sc); 3664 3665 return (0); 3666 } 3667 3668 /* 3669 * Device resume routine. Restore some PCI settings in case the BIOS 3670 * doesn't, re-enable busmastering, and restart the interface if 3671 * appropriate. 3672 */ 3673 static int 3674 re_resume(device_t dev) 3675 { 3676 struct rl_softc *sc; 3677 struct ifnet *ifp; 3678 3679 sc = device_get_softc(dev); 3680 3681 RL_LOCK(sc); 3682 3683 ifp = sc->rl_ifp; 3684 /* Take controller out of sleep mode. */ 3685 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3686 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3687 CSR_WRITE_1(sc, RL_GPIO, 3688 CSR_READ_1(sc, RL_GPIO) | 0x01); 3689 } 3690 3691 /* 3692 * Clear WOL matching such that normal Rx filtering 3693 * wouldn't interfere with WOL patterns. 3694 */ 3695 re_clrwol(sc); 3696 3697 /* reinitialize interface if necessary */ 3698 if (ifp->if_flags & IFF_UP) 3699 re_init_locked(sc); 3700 3701 sc->suspended = 0; 3702 RL_UNLOCK(sc); 3703 3704 return (0); 3705 } 3706 3707 /* 3708 * Stop all chip I/O so that the kernel's probe routines don't 3709 * get confused by errant DMAs when rebooting. 3710 */ 3711 static int 3712 re_shutdown(device_t dev) 3713 { 3714 struct rl_softc *sc; 3715 3716 sc = device_get_softc(dev); 3717 3718 RL_LOCK(sc); 3719 re_stop(sc); 3720 /* 3721 * Mark interface as down since otherwise we will panic if 3722 * interrupt comes in later on, which can happen in some 3723 * cases. 3724 */ 3725 sc->rl_ifp->if_flags &= ~IFF_UP; 3726 re_setwol(sc); 3727 RL_UNLOCK(sc); 3728 3729 return (0); 3730 } 3731 3732 static void 3733 re_set_linkspeed(struct rl_softc *sc) 3734 { 3735 struct mii_softc *miisc; 3736 struct mii_data *mii; 3737 int aneg, i, phyno; 3738 3739 RL_LOCK_ASSERT(sc); 3740 3741 mii = device_get_softc(sc->rl_miibus); 3742 mii_pollstat(mii); 3743 aneg = 0; 3744 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 3745 (IFM_ACTIVE | IFM_AVALID)) { 3746 switch IFM_SUBTYPE(mii->mii_media_active) { 3747 case IFM_10_T: 3748 case IFM_100_TX: 3749 return; 3750 case IFM_1000_T: 3751 aneg++; 3752 break; 3753 default: 3754 break; 3755 } 3756 } 3757 miisc = LIST_FIRST(&mii->mii_phys); 3758 phyno = miisc->mii_phy; 3759 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 3760 PHY_RESET(miisc); 3761 re_miibus_writereg(sc->rl_dev, phyno, MII_100T2CR, 0); 3762 re_miibus_writereg(sc->rl_dev, phyno, 3763 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 3764 re_miibus_writereg(sc->rl_dev, phyno, 3765 MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 3766 DELAY(1000); 3767 if (aneg != 0) { 3768 /* 3769 * Poll link state until re(4) get a 10/100Mbps link. 3770 */ 3771 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 3772 mii_pollstat(mii); 3773 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 3774 == (IFM_ACTIVE | IFM_AVALID)) { 3775 switch (IFM_SUBTYPE(mii->mii_media_active)) { 3776 case IFM_10_T: 3777 case IFM_100_TX: 3778 return; 3779 default: 3780 break; 3781 } 3782 } 3783 RL_UNLOCK(sc); 3784 pause("relnk", hz); 3785 RL_LOCK(sc); 3786 } 3787 if (i == MII_ANEGTICKS_GIGE) 3788 device_printf(sc->rl_dev, 3789 "establishing a link failed, WOL may not work!"); 3790 } 3791 /* 3792 * No link, force MAC to have 100Mbps, full-duplex link. 3793 * MAC does not require reprogramming on resolved speed/duplex, 3794 * so this is just for completeness. 3795 */ 3796 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 3797 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 3798 } 3799 3800 static void 3801 re_setwol(struct rl_softc *sc) 3802 { 3803 struct ifnet *ifp; 3804 int pmc; 3805 uint16_t pmstat; 3806 uint8_t v; 3807 3808 RL_LOCK_ASSERT(sc); 3809 3810 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3811 return; 3812 3813 ifp = sc->rl_ifp; 3814 /* Put controller into sleep mode. */ 3815 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3816 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3817 CSR_WRITE_1(sc, RL_GPIO, 3818 CSR_READ_1(sc, RL_GPIO) & ~0x01); 3819 } 3820 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 3821 re_set_rxmode(sc); 3822 if ((sc->rl_flags & RL_FLAG_WOL_MANLINK) != 0) 3823 re_set_linkspeed(sc); 3824 if ((sc->rl_flags & RL_FLAG_WOLRXENB) != 0) 3825 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB); 3826 } 3827 /* Enable config register write. */ 3828 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3829 3830 /* Enable PME. */ 3831 v = CSR_READ_1(sc, sc->rl_cfg1); 3832 v &= ~RL_CFG1_PME; 3833 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3834 v |= RL_CFG1_PME; 3835 CSR_WRITE_1(sc, sc->rl_cfg1, v); 3836 3837 v = CSR_READ_1(sc, sc->rl_cfg3); 3838 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3839 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3840 v |= RL_CFG3_WOL_MAGIC; 3841 CSR_WRITE_1(sc, sc->rl_cfg3, v); 3842 3843 v = CSR_READ_1(sc, sc->rl_cfg5); 3844 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST | 3845 RL_CFG5_WOL_LANWAKE); 3846 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 3847 v |= RL_CFG5_WOL_UCAST; 3848 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 3849 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 3850 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3851 v |= RL_CFG5_WOL_LANWAKE; 3852 CSR_WRITE_1(sc, sc->rl_cfg5, v); 3853 3854 /* Config register write done. */ 3855 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3856 3857 if ((ifp->if_capenable & IFCAP_WOL) == 0 && 3858 (sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) 3859 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) & ~0x80); 3860 /* 3861 * It seems that hardware resets its link speed to 100Mbps in 3862 * power down mode so switching to 100Mbps in driver is not 3863 * needed. 3864 */ 3865 3866 /* Request PME if WOL is requested. */ 3867 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 3868 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3869 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3870 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3871 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 3872 } 3873 3874 static void 3875 re_clrwol(struct rl_softc *sc) 3876 { 3877 int pmc; 3878 uint8_t v; 3879 3880 RL_LOCK_ASSERT(sc); 3881 3882 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3883 return; 3884 3885 /* Enable config register write. */ 3886 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3887 3888 v = CSR_READ_1(sc, sc->rl_cfg3); 3889 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3890 CSR_WRITE_1(sc, sc->rl_cfg3, v); 3891 3892 /* Config register write done. */ 3893 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3894 3895 v = CSR_READ_1(sc, sc->rl_cfg5); 3896 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3897 v &= ~RL_CFG5_WOL_LANWAKE; 3898 CSR_WRITE_1(sc, sc->rl_cfg5, v); 3899 } 3900 3901 static void 3902 re_add_sysctls(struct rl_softc *sc) 3903 { 3904 struct sysctl_ctx_list *ctx; 3905 struct sysctl_oid_list *children; 3906 int error; 3907 3908 ctx = device_get_sysctl_ctx(sc->rl_dev); 3909 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev)); 3910 3911 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "stats", 3912 CTLTYPE_INT | CTLFLAG_RW, sc, 0, re_sysctl_stats, "I", 3913 "Statistics Information"); 3914 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) 3915 return; 3916 3917 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "int_rx_mod", 3918 CTLTYPE_INT | CTLFLAG_RW, &sc->rl_int_rx_mod, 0, 3919 sysctl_hw_re_int_mod, "I", "re RX interrupt moderation"); 3920 /* Pull in device tunables. */ 3921 sc->rl_int_rx_mod = RL_TIMER_DEFAULT; 3922 error = resource_int_value(device_get_name(sc->rl_dev), 3923 device_get_unit(sc->rl_dev), "int_rx_mod", &sc->rl_int_rx_mod); 3924 if (error == 0) { 3925 if (sc->rl_int_rx_mod < RL_TIMER_MIN || 3926 sc->rl_int_rx_mod > RL_TIMER_MAX) { 3927 device_printf(sc->rl_dev, "int_rx_mod value out of " 3928 "range; using default: %d\n", 3929 RL_TIMER_DEFAULT); 3930 sc->rl_int_rx_mod = RL_TIMER_DEFAULT; 3931 } 3932 } 3933 3934 } 3935 3936 static int 3937 re_sysctl_stats(SYSCTL_HANDLER_ARGS) 3938 { 3939 struct rl_softc *sc; 3940 struct rl_stats *stats; 3941 int error, i, result; 3942 3943 result = -1; 3944 error = sysctl_handle_int(oidp, &result, 0, req); 3945 if (error || req->newptr == NULL) 3946 return (error); 3947 3948 if (result == 1) { 3949 sc = (struct rl_softc *)arg1; 3950 RL_LOCK(sc); 3951 if ((sc->rl_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 3952 RL_UNLOCK(sc); 3953 goto done; 3954 } 3955 bus_dmamap_sync(sc->rl_ldata.rl_stag, 3956 sc->rl_ldata.rl_smap, BUS_DMASYNC_PREREAD); 3957 CSR_WRITE_4(sc, RL_DUMPSTATS_HI, 3958 RL_ADDR_HI(sc->rl_ldata.rl_stats_addr)); 3959 CSR_WRITE_4(sc, RL_DUMPSTATS_LO, 3960 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr)); 3961 CSR_WRITE_4(sc, RL_DUMPSTATS_LO, 3962 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr | 3963 RL_DUMPSTATS_START)); 3964 for (i = RL_TIMEOUT; i > 0; i--) { 3965 if ((CSR_READ_4(sc, RL_DUMPSTATS_LO) & 3966 RL_DUMPSTATS_START) == 0) 3967 break; 3968 DELAY(1000); 3969 } 3970 bus_dmamap_sync(sc->rl_ldata.rl_stag, 3971 sc->rl_ldata.rl_smap, BUS_DMASYNC_POSTREAD); 3972 RL_UNLOCK(sc); 3973 if (i == 0) { 3974 device_printf(sc->rl_dev, 3975 "DUMP statistics request timed out\n"); 3976 return (ETIMEDOUT); 3977 } 3978 done: 3979 stats = sc->rl_ldata.rl_stats; 3980 printf("%s statistics:\n", device_get_nameunit(sc->rl_dev)); 3981 printf("Tx frames : %ju\n", 3982 (uintmax_t)le64toh(stats->rl_tx_pkts)); 3983 printf("Rx frames : %ju\n", 3984 (uintmax_t)le64toh(stats->rl_rx_pkts)); 3985 printf("Tx errors : %ju\n", 3986 (uintmax_t)le64toh(stats->rl_tx_errs)); 3987 printf("Rx errors : %u\n", 3988 le32toh(stats->rl_rx_errs)); 3989 printf("Rx missed frames : %u\n", 3990 (uint32_t)le16toh(stats->rl_missed_pkts)); 3991 printf("Rx frame alignment errs : %u\n", 3992 (uint32_t)le16toh(stats->rl_rx_framealign_errs)); 3993 printf("Tx single collisions : %u\n", 3994 le32toh(stats->rl_tx_onecoll)); 3995 printf("Tx multiple collisions : %u\n", 3996 le32toh(stats->rl_tx_multicolls)); 3997 printf("Rx unicast frames : %ju\n", 3998 (uintmax_t)le64toh(stats->rl_rx_ucasts)); 3999 printf("Rx broadcast frames : %ju\n", 4000 (uintmax_t)le64toh(stats->rl_rx_bcasts)); 4001 printf("Rx multicast frames : %u\n", 4002 le32toh(stats->rl_rx_mcasts)); 4003 printf("Tx aborts : %u\n", 4004 (uint32_t)le16toh(stats->rl_tx_aborts)); 4005 printf("Tx underruns : %u\n", 4006 (uint32_t)le16toh(stats->rl_rx_underruns)); 4007 } 4008 4009 return (error); 4010 } 4011 4012 static int 4013 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4014 { 4015 int error, value; 4016 4017 if (arg1 == NULL) 4018 return (EINVAL); 4019 value = *(int *)arg1; 4020 error = sysctl_handle_int(oidp, &value, 0, req); 4021 if (error || req->newptr == NULL) 4022 return (error); 4023 if (value < low || value > high) 4024 return (EINVAL); 4025 *(int *)arg1 = value; 4026 4027 return (0); 4028 } 4029 4030 static int 4031 sysctl_hw_re_int_mod(SYSCTL_HANDLER_ARGS) 4032 { 4033 4034 return (sysctl_int_range(oidp, arg1, arg2, req, RL_TIMER_MIN, 4035 RL_TIMER_MAX)); 4036 } 4037