1 /*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44 /* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111 #ifdef HAVE_KERNEL_OPTION_HEADERS 112 #include "opt_device_polling.h" 113 #endif 114 115 #include <sys/param.h> 116 #include <sys/endian.h> 117 #include <sys/systm.h> 118 #include <sys/sockio.h> 119 #include <sys/mbuf.h> 120 #include <sys/malloc.h> 121 #include <sys/module.h> 122 #include <sys/kernel.h> 123 #include <sys/socket.h> 124 #include <sys/lock.h> 125 #include <sys/mutex.h> 126 #include <sys/sysctl.h> 127 #include <sys/taskqueue.h> 128 129 #include <net/if.h> 130 #include <net/if_arp.h> 131 #include <net/ethernet.h> 132 #include <net/if_dl.h> 133 #include <net/if_media.h> 134 #include <net/if_types.h> 135 #include <net/if_vlan_var.h> 136 137 #include <net/bpf.h> 138 139 #include <machine/bus.h> 140 #include <machine/resource.h> 141 #include <sys/bus.h> 142 #include <sys/rman.h> 143 144 #include <dev/mii/mii.h> 145 #include <dev/mii/miivar.h> 146 147 #include <dev/pci/pcireg.h> 148 #include <dev/pci/pcivar.h> 149 150 #include <pci/if_rlreg.h> 151 152 MODULE_DEPEND(re, pci, 1, 1, 1); 153 MODULE_DEPEND(re, ether, 1, 1, 1); 154 MODULE_DEPEND(re, miibus, 1, 1, 1); 155 156 /* "device miibus" required. See GENERIC if you get errors here. */ 157 #include "miibus_if.h" 158 159 /* Tunables. */ 160 static int intr_filter = 0; 161 TUNABLE_INT("hw.re.intr_filter", &intr_filter); 162 static int msi_disable = 0; 163 TUNABLE_INT("hw.re.msi_disable", &msi_disable); 164 static int msix_disable = 0; 165 TUNABLE_INT("hw.re.msix_disable", &msix_disable); 166 static int prefer_iomap = 0; 167 TUNABLE_INT("hw.re.prefer_iomap", &prefer_iomap); 168 169 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 170 171 /* 172 * Various supported device vendors/types and their names. 173 */ 174 static struct rl_type re_devs[] = { 175 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0, 176 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 177 { RT_VENDORID, RT_DEVICEID_8139, 0, 178 "RealTek 8139C+ 10/100BaseTX" }, 179 { RT_VENDORID, RT_DEVICEID_8101E, 0, 180 "RealTek 810xE PCIe 10/100baseTX" }, 181 { RT_VENDORID, RT_DEVICEID_8168, 0, 182 "RealTek 8168/8111 B/C/CP/D/DP/E PCIe Gigabit Ethernet" }, 183 { RT_VENDORID, RT_DEVICEID_8169, 0, 184 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" }, 185 { RT_VENDORID, RT_DEVICEID_8169SC, 0, 186 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 187 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0, 188 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 189 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0, 190 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 191 { USR_VENDORID, USR_DEVICEID_997902, 0, 192 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 193 }; 194 195 static struct rl_hwrev re_hwrevs[] = { 196 { RL_HWREV_8139, RL_8139, "", RL_MTU }, 197 { RL_HWREV_8139A, RL_8139, "A", RL_MTU }, 198 { RL_HWREV_8139AG, RL_8139, "A-G", RL_MTU }, 199 { RL_HWREV_8139B, RL_8139, "B", RL_MTU }, 200 { RL_HWREV_8130, RL_8139, "8130", RL_MTU }, 201 { RL_HWREV_8139C, RL_8139, "C", RL_MTU }, 202 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C", RL_MTU }, 203 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+", RL_MTU }, 204 { RL_HWREV_8168B_SPIN1, RL_8169, "8168", RL_JUMBO_MTU }, 205 { RL_HWREV_8169, RL_8169, "8169", RL_JUMBO_MTU }, 206 { RL_HWREV_8169S, RL_8169, "8169S", RL_JUMBO_MTU }, 207 { RL_HWREV_8110S, RL_8169, "8110S", RL_JUMBO_MTU }, 208 { RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB", RL_JUMBO_MTU }, 209 { RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU }, 210 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL", RL_JUMBO_MTU }, 211 { RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU }, 212 { RL_HWREV_8100, RL_8139, "8100", RL_MTU }, 213 { RL_HWREV_8101, RL_8139, "8101", RL_MTU }, 214 { RL_HWREV_8100E, RL_8169, "8100E", RL_MTU }, 215 { RL_HWREV_8101E, RL_8169, "8101E", RL_MTU }, 216 { RL_HWREV_8102E, RL_8169, "8102E", RL_MTU }, 217 { RL_HWREV_8102EL, RL_8169, "8102EL", RL_MTU }, 218 { RL_HWREV_8102EL_SPIN1, RL_8169, "8102EL", RL_MTU }, 219 { RL_HWREV_8103E, RL_8169, "8103E", RL_MTU }, 220 { RL_HWREV_8401E, RL_8169, "8401E", RL_MTU }, 221 { RL_HWREV_8105E, RL_8169, "8105E", RL_MTU }, 222 { RL_HWREV_8168B_SPIN2, RL_8169, "8168", RL_JUMBO_MTU }, 223 { RL_HWREV_8168B_SPIN3, RL_8169, "8168", RL_JUMBO_MTU }, 224 { RL_HWREV_8168C, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K }, 225 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K }, 226 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP", RL_JUMBO_MTU_6K }, 227 { RL_HWREV_8168D, RL_8169, "8168D/8111D", RL_JUMBO_MTU_9K }, 228 { RL_HWREV_8168DP, RL_8169, "8168DP/8111DP", RL_JUMBO_MTU_9K }, 229 { RL_HWREV_8168E, RL_8169, "8168E/8111E", RL_JUMBO_MTU_9K}, 230 { RL_HWREV_8168E_VL, RL_8169, "8168E/8111E-VL", RL_JUMBO_MTU_6K}, 231 { 0, 0, NULL, 0 } 232 }; 233 234 static int re_probe (device_t); 235 static int re_attach (device_t); 236 static int re_detach (device_t); 237 238 static int re_encap (struct rl_softc *, struct mbuf **); 239 240 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 241 static int re_allocmem (device_t, struct rl_softc *); 242 static __inline void re_discard_rxbuf 243 (struct rl_softc *, int); 244 static int re_newbuf (struct rl_softc *, int); 245 static int re_jumbo_newbuf (struct rl_softc *, int); 246 static int re_rx_list_init (struct rl_softc *); 247 static int re_jrx_list_init (struct rl_softc *); 248 static int re_tx_list_init (struct rl_softc *); 249 #ifdef RE_FIXUP_RX 250 static __inline void re_fixup_rx 251 (struct mbuf *); 252 #endif 253 static int re_rxeof (struct rl_softc *, int *); 254 static void re_txeof (struct rl_softc *); 255 #ifdef DEVICE_POLLING 256 static int re_poll (struct ifnet *, enum poll_cmd, int); 257 static int re_poll_locked (struct ifnet *, enum poll_cmd, int); 258 #endif 259 static int re_intr (void *); 260 static void re_intr_msi (void *); 261 static void re_tick (void *); 262 static void re_int_task (void *, int); 263 static void re_start (struct ifnet *); 264 static void re_start_locked (struct ifnet *); 265 static int re_ioctl (struct ifnet *, u_long, caddr_t); 266 static void re_init (void *); 267 static void re_init_locked (struct rl_softc *); 268 static void re_stop (struct rl_softc *); 269 static void re_watchdog (struct rl_softc *); 270 static int re_suspend (device_t); 271 static int re_resume (device_t); 272 static int re_shutdown (device_t); 273 static int re_ifmedia_upd (struct ifnet *); 274 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 275 276 static void re_eeprom_putbyte (struct rl_softc *, int); 277 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 278 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 279 static int re_gmii_readreg (device_t, int, int); 280 static int re_gmii_writereg (device_t, int, int, int); 281 282 static int re_miibus_readreg (device_t, int, int); 283 static int re_miibus_writereg (device_t, int, int, int); 284 static void re_miibus_statchg (device_t); 285 286 static void re_set_jumbo (struct rl_softc *, int); 287 static void re_set_rxmode (struct rl_softc *); 288 static void re_reset (struct rl_softc *); 289 static void re_setwol (struct rl_softc *); 290 static void re_clrwol (struct rl_softc *); 291 292 #ifdef RE_DIAG 293 static int re_diag (struct rl_softc *); 294 #endif 295 296 static void re_add_sysctls (struct rl_softc *); 297 static int re_sysctl_stats (SYSCTL_HANDLER_ARGS); 298 static int sysctl_int_range (SYSCTL_HANDLER_ARGS, int, int); 299 static int sysctl_hw_re_int_mod (SYSCTL_HANDLER_ARGS); 300 301 static device_method_t re_methods[] = { 302 /* Device interface */ 303 DEVMETHOD(device_probe, re_probe), 304 DEVMETHOD(device_attach, re_attach), 305 DEVMETHOD(device_detach, re_detach), 306 DEVMETHOD(device_suspend, re_suspend), 307 DEVMETHOD(device_resume, re_resume), 308 DEVMETHOD(device_shutdown, re_shutdown), 309 310 /* bus interface */ 311 DEVMETHOD(bus_print_child, bus_generic_print_child), 312 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 313 314 /* MII interface */ 315 DEVMETHOD(miibus_readreg, re_miibus_readreg), 316 DEVMETHOD(miibus_writereg, re_miibus_writereg), 317 DEVMETHOD(miibus_statchg, re_miibus_statchg), 318 319 { 0, 0 } 320 }; 321 322 static driver_t re_driver = { 323 "re", 324 re_methods, 325 sizeof(struct rl_softc) 326 }; 327 328 static devclass_t re_devclass; 329 330 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 331 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 332 333 #define EE_SET(x) \ 334 CSR_WRITE_1(sc, RL_EECMD, \ 335 CSR_READ_1(sc, RL_EECMD) | x) 336 337 #define EE_CLR(x) \ 338 CSR_WRITE_1(sc, RL_EECMD, \ 339 CSR_READ_1(sc, RL_EECMD) & ~x) 340 341 /* 342 * Send a read command and address to the EEPROM, check for ACK. 343 */ 344 static void 345 re_eeprom_putbyte(struct rl_softc *sc, int addr) 346 { 347 int d, i; 348 349 d = addr | (RL_9346_READ << sc->rl_eewidth); 350 351 /* 352 * Feed in each bit and strobe the clock. 353 */ 354 355 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 356 if (d & i) { 357 EE_SET(RL_EE_DATAIN); 358 } else { 359 EE_CLR(RL_EE_DATAIN); 360 } 361 DELAY(100); 362 EE_SET(RL_EE_CLK); 363 DELAY(150); 364 EE_CLR(RL_EE_CLK); 365 DELAY(100); 366 } 367 } 368 369 /* 370 * Read a word of data stored in the EEPROM at address 'addr.' 371 */ 372 static void 373 re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest) 374 { 375 int i; 376 u_int16_t word = 0; 377 378 /* 379 * Send address of word we want to read. 380 */ 381 re_eeprom_putbyte(sc, addr); 382 383 /* 384 * Start reading bits from EEPROM. 385 */ 386 for (i = 0x8000; i; i >>= 1) { 387 EE_SET(RL_EE_CLK); 388 DELAY(100); 389 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 390 word |= i; 391 EE_CLR(RL_EE_CLK); 392 DELAY(100); 393 } 394 395 *dest = word; 396 } 397 398 /* 399 * Read a sequence of words from the EEPROM. 400 */ 401 static void 402 re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt) 403 { 404 int i; 405 u_int16_t word = 0, *ptr; 406 407 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 408 409 DELAY(100); 410 411 for (i = 0; i < cnt; i++) { 412 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 413 re_eeprom_getword(sc, off + i, &word); 414 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 415 ptr = (u_int16_t *)(dest + (i * 2)); 416 *ptr = word; 417 } 418 419 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 420 } 421 422 static int 423 re_gmii_readreg(device_t dev, int phy, int reg) 424 { 425 struct rl_softc *sc; 426 u_int32_t rval; 427 int i; 428 429 sc = device_get_softc(dev); 430 431 /* Let the rgephy driver read the GMEDIASTAT register */ 432 433 if (reg == RL_GMEDIASTAT) { 434 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 435 return (rval); 436 } 437 438 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 439 440 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 441 rval = CSR_READ_4(sc, RL_PHYAR); 442 if (rval & RL_PHYAR_BUSY) 443 break; 444 DELAY(25); 445 } 446 447 if (i == RL_PHY_TIMEOUT) { 448 device_printf(sc->rl_dev, "PHY read failed\n"); 449 return (0); 450 } 451 452 /* 453 * Controller requires a 20us delay to process next MDIO request. 454 */ 455 DELAY(20); 456 457 return (rval & RL_PHYAR_PHYDATA); 458 } 459 460 static int 461 re_gmii_writereg(device_t dev, int phy, int reg, int data) 462 { 463 struct rl_softc *sc; 464 u_int32_t rval; 465 int i; 466 467 sc = device_get_softc(dev); 468 469 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 470 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 471 472 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 473 rval = CSR_READ_4(sc, RL_PHYAR); 474 if (!(rval & RL_PHYAR_BUSY)) 475 break; 476 DELAY(25); 477 } 478 479 if (i == RL_PHY_TIMEOUT) { 480 device_printf(sc->rl_dev, "PHY write failed\n"); 481 return (0); 482 } 483 484 /* 485 * Controller requires a 20us delay to process next MDIO request. 486 */ 487 DELAY(20); 488 489 return (0); 490 } 491 492 static int 493 re_miibus_readreg(device_t dev, int phy, int reg) 494 { 495 struct rl_softc *sc; 496 u_int16_t rval = 0; 497 u_int16_t re8139_reg = 0; 498 499 sc = device_get_softc(dev); 500 501 if (sc->rl_type == RL_8169) { 502 rval = re_gmii_readreg(dev, phy, reg); 503 return (rval); 504 } 505 506 switch (reg) { 507 case MII_BMCR: 508 re8139_reg = RL_BMCR; 509 break; 510 case MII_BMSR: 511 re8139_reg = RL_BMSR; 512 break; 513 case MII_ANAR: 514 re8139_reg = RL_ANAR; 515 break; 516 case MII_ANER: 517 re8139_reg = RL_ANER; 518 break; 519 case MII_ANLPAR: 520 re8139_reg = RL_LPAR; 521 break; 522 case MII_PHYIDR1: 523 case MII_PHYIDR2: 524 return (0); 525 /* 526 * Allow the rlphy driver to read the media status 527 * register. If we have a link partner which does not 528 * support NWAY, this is the register which will tell 529 * us the results of parallel detection. 530 */ 531 case RL_MEDIASTAT: 532 rval = CSR_READ_1(sc, RL_MEDIASTAT); 533 return (rval); 534 default: 535 device_printf(sc->rl_dev, "bad phy register\n"); 536 return (0); 537 } 538 rval = CSR_READ_2(sc, re8139_reg); 539 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 540 /* 8139C+ has different bit layout. */ 541 rval &= ~(BMCR_LOOP | BMCR_ISO); 542 } 543 return (rval); 544 } 545 546 static int 547 re_miibus_writereg(device_t dev, int phy, int reg, int data) 548 { 549 struct rl_softc *sc; 550 u_int16_t re8139_reg = 0; 551 int rval = 0; 552 553 sc = device_get_softc(dev); 554 555 if (sc->rl_type == RL_8169) { 556 rval = re_gmii_writereg(dev, phy, reg, data); 557 return (rval); 558 } 559 560 switch (reg) { 561 case MII_BMCR: 562 re8139_reg = RL_BMCR; 563 if (sc->rl_type == RL_8139CPLUS) { 564 /* 8139C+ has different bit layout. */ 565 data &= ~(BMCR_LOOP | BMCR_ISO); 566 } 567 break; 568 case MII_BMSR: 569 re8139_reg = RL_BMSR; 570 break; 571 case MII_ANAR: 572 re8139_reg = RL_ANAR; 573 break; 574 case MII_ANER: 575 re8139_reg = RL_ANER; 576 break; 577 case MII_ANLPAR: 578 re8139_reg = RL_LPAR; 579 break; 580 case MII_PHYIDR1: 581 case MII_PHYIDR2: 582 return (0); 583 break; 584 default: 585 device_printf(sc->rl_dev, "bad phy register\n"); 586 return (0); 587 } 588 CSR_WRITE_2(sc, re8139_reg, data); 589 return (0); 590 } 591 592 static void 593 re_miibus_statchg(device_t dev) 594 { 595 struct rl_softc *sc; 596 struct ifnet *ifp; 597 struct mii_data *mii; 598 599 sc = device_get_softc(dev); 600 mii = device_get_softc(sc->rl_miibus); 601 ifp = sc->rl_ifp; 602 if (mii == NULL || ifp == NULL || 603 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 604 return; 605 606 sc->rl_flags &= ~RL_FLAG_LINK; 607 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 608 (IFM_ACTIVE | IFM_AVALID)) { 609 switch (IFM_SUBTYPE(mii->mii_media_active)) { 610 case IFM_10_T: 611 case IFM_100_TX: 612 sc->rl_flags |= RL_FLAG_LINK; 613 break; 614 case IFM_1000_T: 615 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0) 616 break; 617 sc->rl_flags |= RL_FLAG_LINK; 618 break; 619 default: 620 break; 621 } 622 } 623 /* 624 * RealTek controllers does not provide any interface to 625 * Tx/Rx MACs for resolved speed, duplex and flow-control 626 * parameters. 627 */ 628 } 629 630 /* 631 * Set the RX configuration and 64-bit multicast hash filter. 632 */ 633 static void 634 re_set_rxmode(struct rl_softc *sc) 635 { 636 struct ifnet *ifp; 637 struct ifmultiaddr *ifma; 638 uint32_t hashes[2] = { 0, 0 }; 639 uint32_t h, rxfilt; 640 641 RL_LOCK_ASSERT(sc); 642 643 ifp = sc->rl_ifp; 644 645 rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD; 646 647 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 648 if (ifp->if_flags & IFF_PROMISC) 649 rxfilt |= RL_RXCFG_RX_ALLPHYS; 650 /* 651 * Unlike other hardwares, we have to explicitly set 652 * RL_RXCFG_RX_MULTI to receive multicast frames in 653 * promiscuous mode. 654 */ 655 rxfilt |= RL_RXCFG_RX_MULTI; 656 hashes[0] = hashes[1] = 0xffffffff; 657 goto done; 658 } 659 660 if_maddr_rlock(ifp); 661 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 662 if (ifma->ifma_addr->sa_family != AF_LINK) 663 continue; 664 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 665 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 666 if (h < 32) 667 hashes[0] |= (1 << h); 668 else 669 hashes[1] |= (1 << (h - 32)); 670 } 671 if_maddr_runlock(ifp); 672 673 if (hashes[0] != 0 || hashes[1] != 0) { 674 /* 675 * For some unfathomable reason, RealTek decided to 676 * reverse the order of the multicast hash registers 677 * in the PCI Express parts. This means we have to 678 * write the hash pattern in reverse order for those 679 * devices. 680 */ 681 if ((sc->rl_flags & RL_FLAG_PCIE) != 0) { 682 h = bswap32(hashes[0]); 683 hashes[0] = bswap32(hashes[1]); 684 hashes[1] = h; 685 } 686 rxfilt |= RL_RXCFG_RX_MULTI; 687 } 688 689 done: 690 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 691 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 692 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 693 } 694 695 static void 696 re_reset(struct rl_softc *sc) 697 { 698 int i; 699 700 RL_LOCK_ASSERT(sc); 701 702 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 703 704 for (i = 0; i < RL_TIMEOUT; i++) { 705 DELAY(10); 706 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 707 break; 708 } 709 if (i == RL_TIMEOUT) 710 device_printf(sc->rl_dev, "reset never completed!\n"); 711 712 if ((sc->rl_flags & RL_FLAG_MACRESET) != 0) 713 CSR_WRITE_1(sc, 0x82, 1); 714 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169S) 715 re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0); 716 } 717 718 #ifdef RE_DIAG 719 720 /* 721 * The following routine is designed to test for a defect on some 722 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 723 * lines connected to the bus, however for a 32-bit only card, they 724 * should be pulled high. The result of this defect is that the 725 * NIC will not work right if you plug it into a 64-bit slot: DMA 726 * operations will be done with 64-bit transfers, which will fail 727 * because the 64-bit data lines aren't connected. 728 * 729 * There's no way to work around this (short of talking a soldering 730 * iron to the board), however we can detect it. The method we use 731 * here is to put the NIC into digital loopback mode, set the receiver 732 * to promiscuous mode, and then try to send a frame. We then compare 733 * the frame data we sent to what was received. If the data matches, 734 * then the NIC is working correctly, otherwise we know the user has 735 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 736 * slot. In the latter case, there's no way the NIC can work correctly, 737 * so we print out a message on the console and abort the device attach. 738 */ 739 740 static int 741 re_diag(struct rl_softc *sc) 742 { 743 struct ifnet *ifp = sc->rl_ifp; 744 struct mbuf *m0; 745 struct ether_header *eh; 746 struct rl_desc *cur_rx; 747 u_int16_t status; 748 u_int32_t rxstat; 749 int total_len, i, error = 0, phyaddr; 750 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 751 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 752 753 /* Allocate a single mbuf */ 754 MGETHDR(m0, M_DONTWAIT, MT_DATA); 755 if (m0 == NULL) 756 return (ENOBUFS); 757 758 RL_LOCK(sc); 759 760 /* 761 * Initialize the NIC in test mode. This sets the chip up 762 * so that it can send and receive frames, but performs the 763 * following special functions: 764 * - Puts receiver in promiscuous mode 765 * - Enables digital loopback mode 766 * - Leaves interrupts turned off 767 */ 768 769 ifp->if_flags |= IFF_PROMISC; 770 sc->rl_testmode = 1; 771 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 772 re_init_locked(sc); 773 sc->rl_flags |= RL_FLAG_LINK; 774 if (sc->rl_type == RL_8169) 775 phyaddr = 1; 776 else 777 phyaddr = 0; 778 779 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 780 for (i = 0; i < RL_TIMEOUT; i++) { 781 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 782 if (!(status & BMCR_RESET)) 783 break; 784 } 785 786 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 787 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 788 789 DELAY(100000); 790 791 /* Put some data in the mbuf */ 792 793 eh = mtod(m0, struct ether_header *); 794 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 795 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 796 eh->ether_type = htons(ETHERTYPE_IP); 797 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 798 799 /* 800 * Queue the packet, start transmission. 801 * Note: IF_HANDOFF() ultimately calls re_start() for us. 802 */ 803 804 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 805 RL_UNLOCK(sc); 806 /* XXX: re_diag must not be called when in ALTQ mode */ 807 IF_HANDOFF(&ifp->if_snd, m0, ifp); 808 RL_LOCK(sc); 809 m0 = NULL; 810 811 /* Wait for it to propagate through the chip */ 812 813 DELAY(100000); 814 for (i = 0; i < RL_TIMEOUT; i++) { 815 status = CSR_READ_2(sc, RL_ISR); 816 CSR_WRITE_2(sc, RL_ISR, status); 817 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 818 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 819 break; 820 DELAY(10); 821 } 822 823 if (i == RL_TIMEOUT) { 824 device_printf(sc->rl_dev, 825 "diagnostic failed, failed to receive packet in" 826 " loopback mode\n"); 827 error = EIO; 828 goto done; 829 } 830 831 /* 832 * The packet should have been dumped into the first 833 * entry in the RX DMA ring. Grab it from there. 834 */ 835 836 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 837 sc->rl_ldata.rl_rx_list_map, 838 BUS_DMASYNC_POSTREAD); 839 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 840 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 841 BUS_DMASYNC_POSTREAD); 842 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 843 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 844 845 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 846 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 847 eh = mtod(m0, struct ether_header *); 848 849 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 850 total_len = RL_RXBYTES(cur_rx); 851 rxstat = le32toh(cur_rx->rl_cmdstat); 852 853 if (total_len != ETHER_MIN_LEN) { 854 device_printf(sc->rl_dev, 855 "diagnostic failed, received short packet\n"); 856 error = EIO; 857 goto done; 858 } 859 860 /* Test that the received packet data matches what we sent. */ 861 862 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 863 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 864 ntohs(eh->ether_type) != ETHERTYPE_IP) { 865 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 866 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 867 dst, ":", src, ":", ETHERTYPE_IP); 868 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 869 eh->ether_dhost, ":", eh->ether_shost, ":", 870 ntohs(eh->ether_type)); 871 device_printf(sc->rl_dev, "You may have a defective 32-bit " 872 "NIC plugged into a 64-bit PCI slot.\n"); 873 device_printf(sc->rl_dev, "Please re-install the NIC in a " 874 "32-bit slot for proper operation.\n"); 875 device_printf(sc->rl_dev, "Read the re(4) man page for more " 876 "details.\n"); 877 error = EIO; 878 } 879 880 done: 881 /* Turn interface off, release resources */ 882 883 sc->rl_testmode = 0; 884 sc->rl_flags &= ~RL_FLAG_LINK; 885 ifp->if_flags &= ~IFF_PROMISC; 886 re_stop(sc); 887 if (m0 != NULL) 888 m_freem(m0); 889 890 RL_UNLOCK(sc); 891 892 return (error); 893 } 894 895 #endif 896 897 /* 898 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 899 * IDs against our list and return a device name if we find a match. 900 */ 901 static int 902 re_probe(device_t dev) 903 { 904 struct rl_type *t; 905 uint16_t devid, vendor; 906 uint16_t revid, sdevid; 907 int i; 908 909 vendor = pci_get_vendor(dev); 910 devid = pci_get_device(dev); 911 revid = pci_get_revid(dev); 912 sdevid = pci_get_subdevice(dev); 913 914 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 915 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 916 /* 917 * Only attach to rev. 3 of the Linksys EG1032 adapter. 918 * Rev. 2 is supported by sk(4). 919 */ 920 return (ENXIO); 921 } 922 } 923 924 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 925 if (revid != 0x20) { 926 /* 8139, let rl(4) take care of this device. */ 927 return (ENXIO); 928 } 929 } 930 931 t = re_devs; 932 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) { 933 if (vendor == t->rl_vid && devid == t->rl_did) { 934 device_set_desc(dev, t->rl_name); 935 return (BUS_PROBE_DEFAULT); 936 } 937 } 938 939 return (ENXIO); 940 } 941 942 /* 943 * Map a single buffer address. 944 */ 945 946 static void 947 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 948 { 949 bus_addr_t *addr; 950 951 if (error) 952 return; 953 954 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 955 addr = arg; 956 *addr = segs->ds_addr; 957 } 958 959 static int 960 re_allocmem(device_t dev, struct rl_softc *sc) 961 { 962 bus_addr_t lowaddr; 963 bus_size_t rx_list_size, tx_list_size; 964 int error; 965 int i; 966 967 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 968 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 969 970 /* 971 * Allocate the parent bus DMA tag appropriate for PCI. 972 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD 973 * register should be set. However some RealTek chips are known 974 * to be buggy on DAC handling, therefore disable DAC by limiting 975 * DMA address space to 32bit. PCIe variants of RealTek chips 976 * may not have the limitation. 977 */ 978 lowaddr = BUS_SPACE_MAXADDR; 979 if ((sc->rl_flags & RL_FLAG_PCIE) == 0) 980 lowaddr = BUS_SPACE_MAXADDR_32BIT; 981 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 982 lowaddr, BUS_SPACE_MAXADDR, NULL, NULL, 983 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 984 NULL, NULL, &sc->rl_parent_tag); 985 if (error) { 986 device_printf(dev, "could not allocate parent DMA tag\n"); 987 return (error); 988 } 989 990 /* 991 * Allocate map for TX mbufs. 992 */ 993 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 994 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 995 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 996 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 997 if (error) { 998 device_printf(dev, "could not allocate TX DMA tag\n"); 999 return (error); 1000 } 1001 1002 /* 1003 * Allocate map for RX mbufs. 1004 */ 1005 1006 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 1007 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 1008 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1009 MJUM9BYTES, 1, MJUM9BYTES, 0, NULL, NULL, 1010 &sc->rl_ldata.rl_jrx_mtag); 1011 if (error) { 1012 device_printf(dev, 1013 "could not allocate jumbo RX DMA tag\n"); 1014 return (error); 1015 } 1016 } 1017 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 1018 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1019 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 1020 if (error) { 1021 device_printf(dev, "could not allocate RX DMA tag\n"); 1022 return (error); 1023 } 1024 1025 /* 1026 * Allocate map for TX descriptor list. 1027 */ 1028 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1029 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1030 NULL, tx_list_size, 1, tx_list_size, 0, 1031 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1032 if (error) { 1033 device_printf(dev, "could not allocate TX DMA ring tag\n"); 1034 return (error); 1035 } 1036 1037 /* Allocate DMA'able memory for the TX ring */ 1038 1039 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1040 (void **)&sc->rl_ldata.rl_tx_list, 1041 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1042 &sc->rl_ldata.rl_tx_list_map); 1043 if (error) { 1044 device_printf(dev, "could not allocate TX DMA ring\n"); 1045 return (error); 1046 } 1047 1048 /* Load the map for the TX ring. */ 1049 1050 sc->rl_ldata.rl_tx_list_addr = 0; 1051 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1052 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1053 tx_list_size, re_dma_map_addr, 1054 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1055 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 1056 device_printf(dev, "could not load TX DMA ring\n"); 1057 return (ENOMEM); 1058 } 1059 1060 /* Create DMA maps for TX buffers */ 1061 1062 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1063 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1064 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1065 if (error) { 1066 device_printf(dev, "could not create DMA map for TX\n"); 1067 return (error); 1068 } 1069 } 1070 1071 /* 1072 * Allocate map for RX descriptor list. 1073 */ 1074 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1075 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1076 NULL, rx_list_size, 1, rx_list_size, 0, 1077 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1078 if (error) { 1079 device_printf(dev, "could not create RX DMA ring tag\n"); 1080 return (error); 1081 } 1082 1083 /* Allocate DMA'able memory for the RX ring */ 1084 1085 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1086 (void **)&sc->rl_ldata.rl_rx_list, 1087 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1088 &sc->rl_ldata.rl_rx_list_map); 1089 if (error) { 1090 device_printf(dev, "could not allocate RX DMA ring\n"); 1091 return (error); 1092 } 1093 1094 /* Load the map for the RX ring. */ 1095 1096 sc->rl_ldata.rl_rx_list_addr = 0; 1097 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1098 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1099 rx_list_size, re_dma_map_addr, 1100 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1101 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1102 device_printf(dev, "could not load RX DMA ring\n"); 1103 return (ENOMEM); 1104 } 1105 1106 /* Create DMA maps for RX buffers */ 1107 1108 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 1109 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0, 1110 &sc->rl_ldata.rl_jrx_sparemap); 1111 if (error) { 1112 device_printf(dev, 1113 "could not create spare DMA map for jumbo RX\n"); 1114 return (error); 1115 } 1116 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1117 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0, 1118 &sc->rl_ldata.rl_jrx_desc[i].rx_dmamap); 1119 if (error) { 1120 device_printf(dev, 1121 "could not create DMA map for jumbo RX\n"); 1122 return (error); 1123 } 1124 } 1125 } 1126 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1127 &sc->rl_ldata.rl_rx_sparemap); 1128 if (error) { 1129 device_printf(dev, "could not create spare DMA map for RX\n"); 1130 return (error); 1131 } 1132 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1133 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1134 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1135 if (error) { 1136 device_printf(dev, "could not create DMA map for RX\n"); 1137 return (error); 1138 } 1139 } 1140 1141 /* Create DMA map for statistics. */ 1142 error = bus_dma_tag_create(sc->rl_parent_tag, RL_DUMP_ALIGN, 0, 1143 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1144 sizeof(struct rl_stats), 1, sizeof(struct rl_stats), 0, NULL, NULL, 1145 &sc->rl_ldata.rl_stag); 1146 if (error) { 1147 device_printf(dev, "could not create statistics DMA tag\n"); 1148 return (error); 1149 } 1150 /* Allocate DMA'able memory for statistics. */ 1151 error = bus_dmamem_alloc(sc->rl_ldata.rl_stag, 1152 (void **)&sc->rl_ldata.rl_stats, 1153 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1154 &sc->rl_ldata.rl_smap); 1155 if (error) { 1156 device_printf(dev, 1157 "could not allocate statistics DMA memory\n"); 1158 return (error); 1159 } 1160 /* Load the map for statistics. */ 1161 sc->rl_ldata.rl_stats_addr = 0; 1162 error = bus_dmamap_load(sc->rl_ldata.rl_stag, sc->rl_ldata.rl_smap, 1163 sc->rl_ldata.rl_stats, sizeof(struct rl_stats), re_dma_map_addr, 1164 &sc->rl_ldata.rl_stats_addr, BUS_DMA_NOWAIT); 1165 if (error != 0 || sc->rl_ldata.rl_stats_addr == 0) { 1166 device_printf(dev, "could not load statistics DMA memory\n"); 1167 return (ENOMEM); 1168 } 1169 1170 return (0); 1171 } 1172 1173 /* 1174 * Attach the interface. Allocate softc structures, do ifmedia 1175 * setup and ethernet/BPF attach. 1176 */ 1177 static int 1178 re_attach(device_t dev) 1179 { 1180 u_char eaddr[ETHER_ADDR_LEN]; 1181 u_int16_t as[ETHER_ADDR_LEN / 2]; 1182 struct rl_softc *sc; 1183 struct ifnet *ifp; 1184 struct rl_hwrev *hw_rev; 1185 int hwrev; 1186 u_int16_t devid, re_did = 0; 1187 int error = 0, i, phy, rid; 1188 int msic, msixc, reg; 1189 uint8_t cfg; 1190 1191 sc = device_get_softc(dev); 1192 sc->rl_dev = dev; 1193 1194 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1195 MTX_DEF); 1196 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1197 1198 /* 1199 * Map control/status registers. 1200 */ 1201 pci_enable_busmaster(dev); 1202 1203 devid = pci_get_device(dev); 1204 /* 1205 * Prefer memory space register mapping over IO space. 1206 * Because RTL8169SC does not seem to work when memory mapping 1207 * is used always activate io mapping. 1208 */ 1209 if (devid == RT_DEVICEID_8169SC) 1210 prefer_iomap = 1; 1211 if (prefer_iomap == 0) { 1212 sc->rl_res_id = PCIR_BAR(1); 1213 sc->rl_res_type = SYS_RES_MEMORY; 1214 /* RTL8168/8101E seems to use different BARs. */ 1215 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E) 1216 sc->rl_res_id = PCIR_BAR(2); 1217 } else { 1218 sc->rl_res_id = PCIR_BAR(0); 1219 sc->rl_res_type = SYS_RES_IOPORT; 1220 } 1221 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1222 &sc->rl_res_id, RF_ACTIVE); 1223 if (sc->rl_res == NULL && prefer_iomap == 0) { 1224 sc->rl_res_id = PCIR_BAR(0); 1225 sc->rl_res_type = SYS_RES_IOPORT; 1226 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1227 &sc->rl_res_id, RF_ACTIVE); 1228 } 1229 if (sc->rl_res == NULL) { 1230 device_printf(dev, "couldn't map ports/memory\n"); 1231 error = ENXIO; 1232 goto fail; 1233 } 1234 1235 sc->rl_btag = rman_get_bustag(sc->rl_res); 1236 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1237 1238 msic = pci_msi_count(dev); 1239 msixc = pci_msix_count(dev); 1240 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) 1241 sc->rl_flags |= RL_FLAG_PCIE; 1242 if (bootverbose) { 1243 device_printf(dev, "MSI count : %d\n", msic); 1244 device_printf(dev, "MSI-X count : %d\n", msixc); 1245 } 1246 if (msix_disable > 0) 1247 msixc = 0; 1248 if (msi_disable > 0) 1249 msic = 0; 1250 /* Prefer MSI-X to MSI. */ 1251 if (msixc > 0) { 1252 msixc = 1; 1253 rid = PCIR_BAR(4); 1254 sc->rl_res_pba = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1255 &rid, RF_ACTIVE); 1256 if (sc->rl_res_pba == NULL) { 1257 device_printf(sc->rl_dev, 1258 "could not allocate MSI-X PBA resource\n"); 1259 } 1260 if (sc->rl_res_pba != NULL && 1261 pci_alloc_msix(dev, &msixc) == 0) { 1262 if (msixc == 1) { 1263 device_printf(dev, "Using %d MSI-X message\n", 1264 msixc); 1265 sc->rl_flags |= RL_FLAG_MSIX; 1266 } else 1267 pci_release_msi(dev); 1268 } 1269 if ((sc->rl_flags & RL_FLAG_MSIX) == 0) { 1270 if (sc->rl_res_pba != NULL) 1271 bus_release_resource(dev, SYS_RES_MEMORY, rid, 1272 sc->rl_res_pba); 1273 sc->rl_res_pba = NULL; 1274 msixc = 0; 1275 } 1276 } 1277 /* Prefer MSI to INTx. */ 1278 if (msixc == 0 && msic > 0) { 1279 msic = 1; 1280 if (pci_alloc_msi(dev, &msic) == 0) { 1281 if (msic == RL_MSI_MESSAGES) { 1282 device_printf(dev, "Using %d MSI message\n", 1283 msic); 1284 sc->rl_flags |= RL_FLAG_MSI; 1285 /* Explicitly set MSI enable bit. */ 1286 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1287 cfg = CSR_READ_1(sc, RL_CFG2); 1288 cfg |= RL_CFG2_MSI; 1289 CSR_WRITE_1(sc, RL_CFG2, cfg); 1290 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1291 } else 1292 pci_release_msi(dev); 1293 } 1294 if ((sc->rl_flags & RL_FLAG_MSI) == 0) 1295 msic = 0; 1296 } 1297 1298 /* Allocate interrupt */ 1299 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) { 1300 rid = 0; 1301 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1302 RF_SHAREABLE | RF_ACTIVE); 1303 if (sc->rl_irq[0] == NULL) { 1304 device_printf(dev, "couldn't allocate IRQ resources\n"); 1305 error = ENXIO; 1306 goto fail; 1307 } 1308 } else { 1309 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1310 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1311 SYS_RES_IRQ, &rid, RF_ACTIVE); 1312 if (sc->rl_irq[i] == NULL) { 1313 device_printf(dev, 1314 "couldn't llocate IRQ resources for " 1315 "message %d\n", rid); 1316 error = ENXIO; 1317 goto fail; 1318 } 1319 } 1320 } 1321 1322 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1323 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1324 cfg = CSR_READ_1(sc, RL_CFG2); 1325 if ((cfg & RL_CFG2_MSI) != 0) { 1326 device_printf(dev, "turning off MSI enable bit.\n"); 1327 cfg &= ~RL_CFG2_MSI; 1328 CSR_WRITE_1(sc, RL_CFG2, cfg); 1329 } 1330 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1331 } 1332 1333 hw_rev = re_hwrevs; 1334 hwrev = CSR_READ_4(sc, RL_TXCFG); 1335 switch (hwrev & 0x70000000) { 1336 case 0x00000000: 1337 case 0x10000000: 1338 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000); 1339 hwrev &= (RL_TXCFG_HWREV | 0x80000000); 1340 break; 1341 default: 1342 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000); 1343 hwrev &= RL_TXCFG_HWREV; 1344 break; 1345 } 1346 device_printf(dev, "MAC rev. 0x%08x\n", hwrev & 0x00700000); 1347 while (hw_rev->rl_desc != NULL) { 1348 if (hw_rev->rl_rev == hwrev) { 1349 sc->rl_type = hw_rev->rl_type; 1350 sc->rl_hwrev = hw_rev; 1351 break; 1352 } 1353 hw_rev++; 1354 } 1355 if (hw_rev->rl_desc == NULL) { 1356 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev); 1357 error = ENXIO; 1358 goto fail; 1359 } 1360 1361 switch (hw_rev->rl_rev) { 1362 case RL_HWREV_8139CPLUS: 1363 sc->rl_flags |= RL_FLAG_FASTETHER | RL_FLAG_AUTOPAD; 1364 break; 1365 case RL_HWREV_8100E: 1366 case RL_HWREV_8101E: 1367 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_FASTETHER; 1368 break; 1369 case RL_HWREV_8102E: 1370 case RL_HWREV_8102EL: 1371 case RL_HWREV_8102EL_SPIN1: 1372 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1373 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | 1374 RL_FLAG_AUTOPAD; 1375 break; 1376 case RL_HWREV_8103E: 1377 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1378 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | 1379 RL_FLAG_AUTOPAD | RL_FLAG_MACSLEEP; 1380 break; 1381 case RL_HWREV_8401E: 1382 case RL_HWREV_8105E: 1383 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1384 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1385 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD; 1386 break; 1387 case RL_HWREV_8168B_SPIN1: 1388 case RL_HWREV_8168B_SPIN2: 1389 sc->rl_flags |= RL_FLAG_WOLRXENB; 1390 /* FALLTHROUGH */ 1391 case RL_HWREV_8168B_SPIN3: 1392 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT; 1393 break; 1394 case RL_HWREV_8168C_SPIN2: 1395 sc->rl_flags |= RL_FLAG_MACSLEEP; 1396 /* FALLTHROUGH */ 1397 case RL_HWREV_8168C: 1398 if ((hwrev & 0x00700000) == 0x00200000) 1399 sc->rl_flags |= RL_FLAG_MACSLEEP; 1400 /* FALLTHROUGH */ 1401 case RL_HWREV_8168CP: 1402 case RL_HWREV_8168D: 1403 case RL_HWREV_8168DP: 1404 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1405 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1406 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2; 1407 break; 1408 case RL_HWREV_8168E: 1409 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1410 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1411 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2; 1412 break; 1413 case RL_HWREV_8168E_VL: 1414 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1415 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1416 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2; 1417 break; 1418 case RL_HWREV_8169_8110SB: 1419 case RL_HWREV_8169_8110SBL: 1420 case RL_HWREV_8169_8110SC: 1421 case RL_HWREV_8169_8110SCE: 1422 sc->rl_flags |= RL_FLAG_PHYWAKE; 1423 /* FALLTHROUGH */ 1424 case RL_HWREV_8169: 1425 case RL_HWREV_8169S: 1426 case RL_HWREV_8110S: 1427 sc->rl_flags |= RL_FLAG_MACRESET; 1428 break; 1429 default: 1430 break; 1431 } 1432 1433 /* Reset the adapter. */ 1434 RL_LOCK(sc); 1435 re_reset(sc); 1436 RL_UNLOCK(sc); 1437 1438 /* Enable PME. */ 1439 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1440 cfg = CSR_READ_1(sc, RL_CFG1); 1441 cfg |= RL_CFG1_PME; 1442 CSR_WRITE_1(sc, RL_CFG1, cfg); 1443 cfg = CSR_READ_1(sc, RL_CFG5); 1444 cfg &= RL_CFG5_PME_STS; 1445 CSR_WRITE_1(sc, RL_CFG5, cfg); 1446 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1447 1448 if ((sc->rl_flags & RL_FLAG_PAR) != 0) { 1449 /* 1450 * XXX Should have a better way to extract station 1451 * address from EEPROM. 1452 */ 1453 for (i = 0; i < ETHER_ADDR_LEN; i++) 1454 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1455 } else { 1456 sc->rl_eewidth = RL_9356_ADDR_LEN; 1457 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1458 if (re_did != 0x8129) 1459 sc->rl_eewidth = RL_9346_ADDR_LEN; 1460 1461 /* 1462 * Get station address from the EEPROM. 1463 */ 1464 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1465 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1466 as[i] = le16toh(as[i]); 1467 bcopy(as, eaddr, sizeof(eaddr)); 1468 } 1469 1470 if (sc->rl_type == RL_8169) { 1471 /* Set RX length mask and number of descriptors. */ 1472 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1473 sc->rl_txstart = RL_GTXSTART; 1474 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1475 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1476 } else { 1477 /* Set RX length mask and number of descriptors. */ 1478 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1479 sc->rl_txstart = RL_TXSTART; 1480 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1481 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1482 } 1483 1484 error = re_allocmem(dev, sc); 1485 if (error) 1486 goto fail; 1487 re_add_sysctls(sc); 1488 1489 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1490 if (ifp == NULL) { 1491 device_printf(dev, "can not if_alloc()\n"); 1492 error = ENOSPC; 1493 goto fail; 1494 } 1495 1496 /* Take controller out of deep sleep mode. */ 1497 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 1498 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 1499 CSR_WRITE_1(sc, RL_GPIO, 1500 CSR_READ_1(sc, RL_GPIO) | 0x01); 1501 else 1502 CSR_WRITE_1(sc, RL_GPIO, 1503 CSR_READ_1(sc, RL_GPIO) & ~0x01); 1504 } 1505 1506 /* Take PHY out of power down mode. */ 1507 if ((sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) { 1508 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80); 1509 if (hw_rev->rl_rev == RL_HWREV_8401E) 1510 CSR_WRITE_1(sc, 0xD1, CSR_READ_1(sc, 0xD1) & ~0x08); 1511 } 1512 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) { 1513 re_gmii_writereg(dev, 1, 0x1f, 0); 1514 re_gmii_writereg(dev, 1, 0x0e, 0); 1515 } 1516 1517 #define RE_PHYAD_INTERNAL 0 1518 1519 /* Do MII setup. */ 1520 phy = RE_PHYAD_INTERNAL; 1521 if (sc->rl_type == RL_8169) 1522 phy = 1; 1523 error = mii_attach(dev, &sc->rl_miibus, ifp, re_ifmedia_upd, 1524 re_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, MIIF_DOPAUSE); 1525 if (error != 0) { 1526 device_printf(dev, "attaching PHYs failed\n"); 1527 goto fail; 1528 } 1529 1530 ifp->if_softc = sc; 1531 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1532 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1533 ifp->if_ioctl = re_ioctl; 1534 ifp->if_start = re_start; 1535 /* 1536 * RTL8168/8111C generates wrong IP checksummed frame if the 1537 * packet has IP options so disable TX IP checksum offloading. 1538 */ 1539 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168C || 1540 sc->rl_hwrev->rl_rev == RL_HWREV_8168C_SPIN2) 1541 ifp->if_hwassist = CSUM_TCP | CSUM_UDP; 1542 else 1543 ifp->if_hwassist = CSUM_IP | CSUM_TCP | CSUM_UDP; 1544 ifp->if_hwassist |= CSUM_TSO; 1545 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 1546 ifp->if_capenable = ifp->if_capabilities; 1547 ifp->if_init = re_init; 1548 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1549 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1550 IFQ_SET_READY(&ifp->if_snd); 1551 1552 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1553 1554 /* 1555 * Call MI attach routine. 1556 */ 1557 ether_ifattach(ifp, eaddr); 1558 1559 /* VLAN capability setup */ 1560 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1561 if (ifp->if_capabilities & IFCAP_HWCSUM) 1562 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1563 /* Enable WOL if PM is supported. */ 1564 if (pci_find_cap(sc->rl_dev, PCIY_PMG, ®) == 0) 1565 ifp->if_capabilities |= IFCAP_WOL; 1566 ifp->if_capenable = ifp->if_capabilities; 1567 /* 1568 * Don't enable TSO by default. It is known to generate 1569 * corrupted TCP segments(bad TCP options) under certain 1570 * circumtances. 1571 */ 1572 ifp->if_hwassist &= ~CSUM_TSO; 1573 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO); 1574 #ifdef DEVICE_POLLING 1575 ifp->if_capabilities |= IFCAP_POLLING; 1576 #endif 1577 /* 1578 * Tell the upper layer(s) we support long frames. 1579 * Must appear after the call to ether_ifattach() because 1580 * ether_ifattach() sets ifi_hdrlen to the default value. 1581 */ 1582 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1583 1584 #ifdef RE_DIAG 1585 /* 1586 * Perform hardware diagnostic on the original RTL8169. 1587 * Some 32-bit cards were incorrectly wired and would 1588 * malfunction if plugged into a 64-bit slot. 1589 */ 1590 1591 if (hwrev == RL_HWREV_8169) { 1592 error = re_diag(sc); 1593 if (error) { 1594 device_printf(dev, 1595 "attach aborted due to hardware diag failure\n"); 1596 ether_ifdetach(ifp); 1597 goto fail; 1598 } 1599 } 1600 #endif 1601 1602 #ifdef RE_TX_MODERATION 1603 intr_filter = 1; 1604 #endif 1605 /* Hook interrupt last to avoid having to lock softc */ 1606 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 && 1607 intr_filter == 0) { 1608 error = bus_setup_intr(dev, sc->rl_irq[0], 1609 INTR_TYPE_NET | INTR_MPSAFE, NULL, re_intr_msi, sc, 1610 &sc->rl_intrhand[0]); 1611 } else { 1612 error = bus_setup_intr(dev, sc->rl_irq[0], 1613 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1614 &sc->rl_intrhand[0]); 1615 } 1616 if (error) { 1617 device_printf(dev, "couldn't set up irq\n"); 1618 ether_ifdetach(ifp); 1619 } 1620 1621 fail: 1622 1623 if (error) 1624 re_detach(dev); 1625 1626 return (error); 1627 } 1628 1629 /* 1630 * Shutdown hardware and free up resources. This can be called any 1631 * time after the mutex has been initialized. It is called in both 1632 * the error case in attach and the normal detach case so it needs 1633 * to be careful about only freeing resources that have actually been 1634 * allocated. 1635 */ 1636 static int 1637 re_detach(device_t dev) 1638 { 1639 struct rl_softc *sc; 1640 struct ifnet *ifp; 1641 int i, rid; 1642 1643 sc = device_get_softc(dev); 1644 ifp = sc->rl_ifp; 1645 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1646 1647 /* These should only be active if attach succeeded */ 1648 if (device_is_attached(dev)) { 1649 #ifdef DEVICE_POLLING 1650 if (ifp->if_capenable & IFCAP_POLLING) 1651 ether_poll_deregister(ifp); 1652 #endif 1653 RL_LOCK(sc); 1654 #if 0 1655 sc->suspended = 1; 1656 #endif 1657 re_stop(sc); 1658 RL_UNLOCK(sc); 1659 callout_drain(&sc->rl_stat_callout); 1660 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1661 /* 1662 * Force off the IFF_UP flag here, in case someone 1663 * still had a BPF descriptor attached to this 1664 * interface. If they do, ether_ifdetach() will cause 1665 * the BPF code to try and clear the promisc mode 1666 * flag, which will bubble down to re_ioctl(), 1667 * which will try to call re_init() again. This will 1668 * turn the NIC back on and restart the MII ticker, 1669 * which will panic the system when the kernel tries 1670 * to invoke the re_tick() function that isn't there 1671 * anymore. 1672 */ 1673 ifp->if_flags &= ~IFF_UP; 1674 ether_ifdetach(ifp); 1675 } 1676 if (sc->rl_miibus) 1677 device_delete_child(dev, sc->rl_miibus); 1678 bus_generic_detach(dev); 1679 1680 /* 1681 * The rest is resource deallocation, so we should already be 1682 * stopped here. 1683 */ 1684 1685 if (sc->rl_intrhand[0] != NULL) { 1686 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]); 1687 sc->rl_intrhand[0] = NULL; 1688 } 1689 if (ifp != NULL) 1690 if_free(ifp); 1691 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) 1692 rid = 0; 1693 else 1694 rid = 1; 1695 if (sc->rl_irq[0] != NULL) { 1696 bus_release_resource(dev, SYS_RES_IRQ, rid, sc->rl_irq[0]); 1697 sc->rl_irq[0] = NULL; 1698 } 1699 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0) 1700 pci_release_msi(dev); 1701 if (sc->rl_res_pba) { 1702 rid = PCIR_BAR(4); 1703 bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->rl_res_pba); 1704 } 1705 if (sc->rl_res) 1706 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, 1707 sc->rl_res); 1708 1709 /* Unload and free the RX DMA ring memory and map */ 1710 1711 if (sc->rl_ldata.rl_rx_list_tag) { 1712 if (sc->rl_ldata.rl_rx_list_map) 1713 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1714 sc->rl_ldata.rl_rx_list_map); 1715 if (sc->rl_ldata.rl_rx_list_map && sc->rl_ldata.rl_rx_list) 1716 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1717 sc->rl_ldata.rl_rx_list, 1718 sc->rl_ldata.rl_rx_list_map); 1719 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1720 } 1721 1722 /* Unload and free the TX DMA ring memory and map */ 1723 1724 if (sc->rl_ldata.rl_tx_list_tag) { 1725 if (sc->rl_ldata.rl_tx_list_map) 1726 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1727 sc->rl_ldata.rl_tx_list_map); 1728 if (sc->rl_ldata.rl_tx_list_map && sc->rl_ldata.rl_tx_list) 1729 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1730 sc->rl_ldata.rl_tx_list, 1731 sc->rl_ldata.rl_tx_list_map); 1732 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1733 } 1734 1735 /* Destroy all the RX and TX buffer maps */ 1736 1737 if (sc->rl_ldata.rl_tx_mtag) { 1738 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1739 if (sc->rl_ldata.rl_tx_desc[i].tx_dmamap) 1740 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1741 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1742 } 1743 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1744 } 1745 if (sc->rl_ldata.rl_rx_mtag) { 1746 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1747 if (sc->rl_ldata.rl_rx_desc[i].rx_dmamap) 1748 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1749 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1750 } 1751 if (sc->rl_ldata.rl_rx_sparemap) 1752 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1753 sc->rl_ldata.rl_rx_sparemap); 1754 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1755 } 1756 if (sc->rl_ldata.rl_jrx_mtag) { 1757 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1758 if (sc->rl_ldata.rl_jrx_desc[i].rx_dmamap) 1759 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag, 1760 sc->rl_ldata.rl_jrx_desc[i].rx_dmamap); 1761 } 1762 if (sc->rl_ldata.rl_jrx_sparemap) 1763 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag, 1764 sc->rl_ldata.rl_jrx_sparemap); 1765 bus_dma_tag_destroy(sc->rl_ldata.rl_jrx_mtag); 1766 } 1767 /* Unload and free the stats buffer and map */ 1768 1769 if (sc->rl_ldata.rl_stag) { 1770 if (sc->rl_ldata.rl_smap) 1771 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1772 sc->rl_ldata.rl_smap); 1773 if (sc->rl_ldata.rl_smap && sc->rl_ldata.rl_stats) 1774 bus_dmamem_free(sc->rl_ldata.rl_stag, 1775 sc->rl_ldata.rl_stats, sc->rl_ldata.rl_smap); 1776 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1777 } 1778 1779 if (sc->rl_parent_tag) 1780 bus_dma_tag_destroy(sc->rl_parent_tag); 1781 1782 mtx_destroy(&sc->rl_mtx); 1783 1784 return (0); 1785 } 1786 1787 static __inline void 1788 re_discard_rxbuf(struct rl_softc *sc, int idx) 1789 { 1790 struct rl_desc *desc; 1791 struct rl_rxdesc *rxd; 1792 uint32_t cmdstat; 1793 1794 if (sc->rl_ifp->if_mtu > RL_MTU && 1795 (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) 1796 rxd = &sc->rl_ldata.rl_jrx_desc[idx]; 1797 else 1798 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1799 desc = &sc->rl_ldata.rl_rx_list[idx]; 1800 desc->rl_vlanctl = 0; 1801 cmdstat = rxd->rx_size; 1802 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1803 cmdstat |= RL_RDESC_CMD_EOR; 1804 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1805 } 1806 1807 static int 1808 re_newbuf(struct rl_softc *sc, int idx) 1809 { 1810 struct mbuf *m; 1811 struct rl_rxdesc *rxd; 1812 bus_dma_segment_t segs[1]; 1813 bus_dmamap_t map; 1814 struct rl_desc *desc; 1815 uint32_t cmdstat; 1816 int error, nsegs; 1817 1818 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1819 if (m == NULL) 1820 return (ENOBUFS); 1821 1822 m->m_len = m->m_pkthdr.len = MCLBYTES; 1823 #ifdef RE_FIXUP_RX 1824 /* 1825 * This is part of an evil trick to deal with non-x86 platforms. 1826 * The RealTek chip requires RX buffers to be aligned on 64-bit 1827 * boundaries, but that will hose non-x86 machines. To get around 1828 * this, we leave some empty space at the start of each buffer 1829 * and for non-x86 hosts, we copy the buffer back six bytes 1830 * to achieve word alignment. This is slightly more efficient 1831 * than allocating a new buffer, copying the contents, and 1832 * discarding the old buffer. 1833 */ 1834 m_adj(m, RE_ETHER_ALIGN); 1835 #endif 1836 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1837 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1838 if (error != 0) { 1839 m_freem(m); 1840 return (ENOBUFS); 1841 } 1842 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1843 1844 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1845 if (rxd->rx_m != NULL) { 1846 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1847 BUS_DMASYNC_POSTREAD); 1848 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1849 } 1850 1851 rxd->rx_m = m; 1852 map = rxd->rx_dmamap; 1853 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1854 rxd->rx_size = segs[0].ds_len; 1855 sc->rl_ldata.rl_rx_sparemap = map; 1856 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1857 BUS_DMASYNC_PREREAD); 1858 1859 desc = &sc->rl_ldata.rl_rx_list[idx]; 1860 desc->rl_vlanctl = 0; 1861 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1862 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1863 cmdstat = segs[0].ds_len; 1864 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1865 cmdstat |= RL_RDESC_CMD_EOR; 1866 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1867 1868 return (0); 1869 } 1870 1871 static int 1872 re_jumbo_newbuf(struct rl_softc *sc, int idx) 1873 { 1874 struct mbuf *m; 1875 struct rl_rxdesc *rxd; 1876 bus_dma_segment_t segs[1]; 1877 bus_dmamap_t map; 1878 struct rl_desc *desc; 1879 uint32_t cmdstat; 1880 int error, nsegs; 1881 1882 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 1883 if (m == NULL) 1884 return (ENOBUFS); 1885 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1886 #ifdef RE_FIXUP_RX 1887 m_adj(m, RE_ETHER_ALIGN); 1888 #endif 1889 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_jrx_mtag, 1890 sc->rl_ldata.rl_jrx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1891 if (error != 0) { 1892 m_freem(m); 1893 return (ENOBUFS); 1894 } 1895 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1896 1897 rxd = &sc->rl_ldata.rl_jrx_desc[idx]; 1898 if (rxd->rx_m != NULL) { 1899 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap, 1900 BUS_DMASYNC_POSTREAD); 1901 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap); 1902 } 1903 1904 rxd->rx_m = m; 1905 map = rxd->rx_dmamap; 1906 rxd->rx_dmamap = sc->rl_ldata.rl_jrx_sparemap; 1907 rxd->rx_size = segs[0].ds_len; 1908 sc->rl_ldata.rl_jrx_sparemap = map; 1909 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap, 1910 BUS_DMASYNC_PREREAD); 1911 1912 desc = &sc->rl_ldata.rl_rx_list[idx]; 1913 desc->rl_vlanctl = 0; 1914 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1915 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1916 cmdstat = segs[0].ds_len; 1917 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1918 cmdstat |= RL_RDESC_CMD_EOR; 1919 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1920 1921 return (0); 1922 } 1923 1924 #ifdef RE_FIXUP_RX 1925 static __inline void 1926 re_fixup_rx(struct mbuf *m) 1927 { 1928 int i; 1929 uint16_t *src, *dst; 1930 1931 src = mtod(m, uint16_t *); 1932 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1933 1934 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1935 *dst++ = *src++; 1936 1937 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1938 } 1939 #endif 1940 1941 static int 1942 re_tx_list_init(struct rl_softc *sc) 1943 { 1944 struct rl_desc *desc; 1945 int i; 1946 1947 RL_LOCK_ASSERT(sc); 1948 1949 bzero(sc->rl_ldata.rl_tx_list, 1950 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 1951 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1952 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 1953 /* Set EOR. */ 1954 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 1955 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 1956 1957 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1958 sc->rl_ldata.rl_tx_list_map, 1959 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1960 1961 sc->rl_ldata.rl_tx_prodidx = 0; 1962 sc->rl_ldata.rl_tx_considx = 0; 1963 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 1964 1965 return (0); 1966 } 1967 1968 static int 1969 re_rx_list_init(struct rl_softc *sc) 1970 { 1971 int error, i; 1972 1973 bzero(sc->rl_ldata.rl_rx_list, 1974 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 1975 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1976 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 1977 if ((error = re_newbuf(sc, i)) != 0) 1978 return (error); 1979 } 1980 1981 /* Flush the RX descriptors */ 1982 1983 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1984 sc->rl_ldata.rl_rx_list_map, 1985 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1986 1987 sc->rl_ldata.rl_rx_prodidx = 0; 1988 sc->rl_head = sc->rl_tail = NULL; 1989 sc->rl_int_rx_act = 0; 1990 1991 return (0); 1992 } 1993 1994 static int 1995 re_jrx_list_init(struct rl_softc *sc) 1996 { 1997 int error, i; 1998 1999 bzero(sc->rl_ldata.rl_rx_list, 2000 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 2001 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2002 sc->rl_ldata.rl_jrx_desc[i].rx_m = NULL; 2003 if ((error = re_jumbo_newbuf(sc, i)) != 0) 2004 return (error); 2005 } 2006 2007 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2008 sc->rl_ldata.rl_rx_list_map, 2009 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2010 2011 sc->rl_ldata.rl_rx_prodidx = 0; 2012 sc->rl_head = sc->rl_tail = NULL; 2013 sc->rl_int_rx_act = 0; 2014 2015 return (0); 2016 } 2017 2018 /* 2019 * RX handler for C+ and 8169. For the gigE chips, we support 2020 * the reception of jumbo frames that have been fragmented 2021 * across multiple 2K mbuf cluster buffers. 2022 */ 2023 static int 2024 re_rxeof(struct rl_softc *sc, int *rx_npktsp) 2025 { 2026 struct mbuf *m; 2027 struct ifnet *ifp; 2028 int i, rxerr, total_len; 2029 struct rl_desc *cur_rx; 2030 u_int32_t rxstat, rxvlan; 2031 int jumbo, maxpkt = 16, rx_npkts = 0; 2032 2033 RL_LOCK_ASSERT(sc); 2034 2035 ifp = sc->rl_ifp; 2036 if (ifp->if_mtu > RL_MTU && (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) 2037 jumbo = 1; 2038 else 2039 jumbo = 0; 2040 2041 /* Invalidate the descriptor memory */ 2042 2043 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2044 sc->rl_ldata.rl_rx_list_map, 2045 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2046 2047 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 2048 i = RL_RX_DESC_NXT(sc, i)) { 2049 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2050 break; 2051 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 2052 rxstat = le32toh(cur_rx->rl_cmdstat); 2053 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 2054 break; 2055 total_len = rxstat & sc->rl_rxlenmask; 2056 rxvlan = le32toh(cur_rx->rl_vlanctl); 2057 if (jumbo != 0) 2058 m = sc->rl_ldata.rl_jrx_desc[i].rx_m; 2059 else 2060 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 2061 2062 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 2063 (rxstat & (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) != 2064 (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) { 2065 /* 2066 * RTL8168C or later controllers do not 2067 * support multi-fragment packet. 2068 */ 2069 re_discard_rxbuf(sc, i); 2070 continue; 2071 } else if ((rxstat & RL_RDESC_STAT_EOF) == 0) { 2072 if (re_newbuf(sc, i) != 0) { 2073 /* 2074 * If this is part of a multi-fragment packet, 2075 * discard all the pieces. 2076 */ 2077 if (sc->rl_head != NULL) { 2078 m_freem(sc->rl_head); 2079 sc->rl_head = sc->rl_tail = NULL; 2080 } 2081 re_discard_rxbuf(sc, i); 2082 continue; 2083 } 2084 m->m_len = RE_RX_DESC_BUFLEN; 2085 if (sc->rl_head == NULL) 2086 sc->rl_head = sc->rl_tail = m; 2087 else { 2088 m->m_flags &= ~M_PKTHDR; 2089 sc->rl_tail->m_next = m; 2090 sc->rl_tail = m; 2091 } 2092 continue; 2093 } 2094 2095 /* 2096 * NOTE: for the 8139C+, the frame length field 2097 * is always 12 bits in size, but for the gigE chips, 2098 * it is 13 bits (since the max RX frame length is 16K). 2099 * Unfortunately, all 32 bits in the status word 2100 * were already used, so to make room for the extra 2101 * length bit, RealTek took out the 'frame alignment 2102 * error' bit and shifted the other status bits 2103 * over one slot. The OWN, EOR, FS and LS bits are 2104 * still in the same places. We have already extracted 2105 * the frame length and checked the OWN bit, so rather 2106 * than using an alternate bit mapping, we shift the 2107 * status bits one space to the right so we can evaluate 2108 * them using the 8169 status as though it was in the 2109 * same format as that of the 8139C+. 2110 */ 2111 if (sc->rl_type == RL_8169) 2112 rxstat >>= 1; 2113 2114 /* 2115 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 2116 * set, but if CRC is clear, it will still be a valid frame. 2117 */ 2118 if ((rxstat & RL_RDESC_STAT_RXERRSUM) != 0) { 2119 rxerr = 1; 2120 if ((sc->rl_flags & RL_FLAG_JUMBOV2) == 0 && 2121 total_len > 8191 && 2122 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT) 2123 rxerr = 0; 2124 if (rxerr != 0) { 2125 ifp->if_ierrors++; 2126 /* 2127 * If this is part of a multi-fragment packet, 2128 * discard all the pieces. 2129 */ 2130 if (sc->rl_head != NULL) { 2131 m_freem(sc->rl_head); 2132 sc->rl_head = sc->rl_tail = NULL; 2133 } 2134 re_discard_rxbuf(sc, i); 2135 continue; 2136 } 2137 } 2138 2139 /* 2140 * If allocating a replacement mbuf fails, 2141 * reload the current one. 2142 */ 2143 if (jumbo != 0) 2144 rxerr = re_jumbo_newbuf(sc, i); 2145 else 2146 rxerr = re_newbuf(sc, i); 2147 if (rxerr != 0) { 2148 ifp->if_iqdrops++; 2149 if (sc->rl_head != NULL) { 2150 m_freem(sc->rl_head); 2151 sc->rl_head = sc->rl_tail = NULL; 2152 } 2153 re_discard_rxbuf(sc, i); 2154 continue; 2155 } 2156 2157 if (sc->rl_head != NULL) { 2158 if (jumbo != 0) 2159 m->m_len = total_len; 2160 else { 2161 m->m_len = total_len % RE_RX_DESC_BUFLEN; 2162 if (m->m_len == 0) 2163 m->m_len = RE_RX_DESC_BUFLEN; 2164 } 2165 /* 2166 * Special case: if there's 4 bytes or less 2167 * in this buffer, the mbuf can be discarded: 2168 * the last 4 bytes is the CRC, which we don't 2169 * care about anyway. 2170 */ 2171 if (m->m_len <= ETHER_CRC_LEN) { 2172 sc->rl_tail->m_len -= 2173 (ETHER_CRC_LEN - m->m_len); 2174 m_freem(m); 2175 } else { 2176 m->m_len -= ETHER_CRC_LEN; 2177 m->m_flags &= ~M_PKTHDR; 2178 sc->rl_tail->m_next = m; 2179 } 2180 m = sc->rl_head; 2181 sc->rl_head = sc->rl_tail = NULL; 2182 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 2183 } else 2184 m->m_pkthdr.len = m->m_len = 2185 (total_len - ETHER_CRC_LEN); 2186 2187 #ifdef RE_FIXUP_RX 2188 re_fixup_rx(m); 2189 #endif 2190 ifp->if_ipackets++; 2191 m->m_pkthdr.rcvif = ifp; 2192 2193 /* Do RX checksumming if enabled */ 2194 2195 if (ifp->if_capenable & IFCAP_RXCSUM) { 2196 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2197 /* Check IP header checksum */ 2198 if (rxstat & RL_RDESC_STAT_PROTOID) 2199 m->m_pkthdr.csum_flags |= 2200 CSUM_IP_CHECKED; 2201 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 2202 m->m_pkthdr.csum_flags |= 2203 CSUM_IP_VALID; 2204 2205 /* Check TCP/UDP checksum */ 2206 if ((RL_TCPPKT(rxstat) && 2207 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 2208 (RL_UDPPKT(rxstat) && 2209 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 2210 m->m_pkthdr.csum_flags |= 2211 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2212 m->m_pkthdr.csum_data = 0xffff; 2213 } 2214 } else { 2215 /* 2216 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP 2217 */ 2218 if ((rxstat & RL_RDESC_STAT_PROTOID) && 2219 (rxvlan & RL_RDESC_IPV4)) 2220 m->m_pkthdr.csum_flags |= 2221 CSUM_IP_CHECKED; 2222 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) && 2223 (rxvlan & RL_RDESC_IPV4)) 2224 m->m_pkthdr.csum_flags |= 2225 CSUM_IP_VALID; 2226 if (((rxstat & RL_RDESC_STAT_TCP) && 2227 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 2228 ((rxstat & RL_RDESC_STAT_UDP) && 2229 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 2230 m->m_pkthdr.csum_flags |= 2231 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2232 m->m_pkthdr.csum_data = 0xffff; 2233 } 2234 } 2235 } 2236 maxpkt--; 2237 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 2238 m->m_pkthdr.ether_vtag = 2239 bswap16((rxvlan & RL_RDESC_VLANCTL_DATA)); 2240 m->m_flags |= M_VLANTAG; 2241 } 2242 RL_UNLOCK(sc); 2243 (*ifp->if_input)(ifp, m); 2244 RL_LOCK(sc); 2245 rx_npkts++; 2246 } 2247 2248 /* Flush the RX DMA ring */ 2249 2250 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2251 sc->rl_ldata.rl_rx_list_map, 2252 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2253 2254 sc->rl_ldata.rl_rx_prodidx = i; 2255 2256 if (rx_npktsp != NULL) 2257 *rx_npktsp = rx_npkts; 2258 if (maxpkt) 2259 return (EAGAIN); 2260 2261 return (0); 2262 } 2263 2264 static void 2265 re_txeof(struct rl_softc *sc) 2266 { 2267 struct ifnet *ifp; 2268 struct rl_txdesc *txd; 2269 u_int32_t txstat; 2270 int cons; 2271 2272 cons = sc->rl_ldata.rl_tx_considx; 2273 if (cons == sc->rl_ldata.rl_tx_prodidx) 2274 return; 2275 2276 ifp = sc->rl_ifp; 2277 /* Invalidate the TX descriptor list */ 2278 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2279 sc->rl_ldata.rl_tx_list_map, 2280 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2281 2282 for (; cons != sc->rl_ldata.rl_tx_prodidx; 2283 cons = RL_TX_DESC_NXT(sc, cons)) { 2284 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 2285 if (txstat & RL_TDESC_STAT_OWN) 2286 break; 2287 /* 2288 * We only stash mbufs in the last descriptor 2289 * in a fragment chain, which also happens to 2290 * be the only place where the TX status bits 2291 * are valid. 2292 */ 2293 if (txstat & RL_TDESC_CMD_EOF) { 2294 txd = &sc->rl_ldata.rl_tx_desc[cons]; 2295 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2296 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2297 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2298 txd->tx_dmamap); 2299 KASSERT(txd->tx_m != NULL, 2300 ("%s: freeing NULL mbufs!", __func__)); 2301 m_freem(txd->tx_m); 2302 txd->tx_m = NULL; 2303 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 2304 RL_TDESC_STAT_COLCNT)) 2305 ifp->if_collisions++; 2306 if (txstat & RL_TDESC_STAT_TXERRSUM) 2307 ifp->if_oerrors++; 2308 else 2309 ifp->if_opackets++; 2310 } 2311 sc->rl_ldata.rl_tx_free++; 2312 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2313 } 2314 sc->rl_ldata.rl_tx_considx = cons; 2315 2316 /* No changes made to the TX ring, so no flush needed */ 2317 2318 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 2319 #ifdef RE_TX_MODERATION 2320 /* 2321 * If not all descriptors have been reaped yet, reload 2322 * the timer so that we will eventually get another 2323 * interrupt that will cause us to re-enter this routine. 2324 * This is done in case the transmitter has gone idle. 2325 */ 2326 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2327 #endif 2328 } else 2329 sc->rl_watchdog_timer = 0; 2330 } 2331 2332 static void 2333 re_tick(void *xsc) 2334 { 2335 struct rl_softc *sc; 2336 struct mii_data *mii; 2337 2338 sc = xsc; 2339 2340 RL_LOCK_ASSERT(sc); 2341 2342 mii = device_get_softc(sc->rl_miibus); 2343 mii_tick(mii); 2344 if ((sc->rl_flags & RL_FLAG_LINK) == 0) 2345 re_miibus_statchg(sc->rl_dev); 2346 /* 2347 * Reclaim transmitted frames here. Technically it is not 2348 * necessary to do here but it ensures periodic reclamation 2349 * regardless of Tx completion interrupt which seems to be 2350 * lost on PCIe based controllers under certain situations. 2351 */ 2352 re_txeof(sc); 2353 re_watchdog(sc); 2354 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2355 } 2356 2357 #ifdef DEVICE_POLLING 2358 static int 2359 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2360 { 2361 struct rl_softc *sc = ifp->if_softc; 2362 int rx_npkts = 0; 2363 2364 RL_LOCK(sc); 2365 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2366 rx_npkts = re_poll_locked(ifp, cmd, count); 2367 RL_UNLOCK(sc); 2368 return (rx_npkts); 2369 } 2370 2371 static int 2372 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2373 { 2374 struct rl_softc *sc = ifp->if_softc; 2375 int rx_npkts; 2376 2377 RL_LOCK_ASSERT(sc); 2378 2379 sc->rxcycles = count; 2380 re_rxeof(sc, &rx_npkts); 2381 re_txeof(sc); 2382 2383 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2384 re_start_locked(ifp); 2385 2386 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2387 u_int16_t status; 2388 2389 status = CSR_READ_2(sc, RL_ISR); 2390 if (status == 0xffff) 2391 return (rx_npkts); 2392 if (status) 2393 CSR_WRITE_2(sc, RL_ISR, status); 2394 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2395 (sc->rl_flags & RL_FLAG_PCIE)) 2396 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2397 2398 /* 2399 * XXX check behaviour on receiver stalls. 2400 */ 2401 2402 if (status & RL_ISR_SYSTEM_ERR) { 2403 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2404 re_init_locked(sc); 2405 } 2406 } 2407 return (rx_npkts); 2408 } 2409 #endif /* DEVICE_POLLING */ 2410 2411 static int 2412 re_intr(void *arg) 2413 { 2414 struct rl_softc *sc; 2415 uint16_t status; 2416 2417 sc = arg; 2418 2419 status = CSR_READ_2(sc, RL_ISR); 2420 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2421 return (FILTER_STRAY); 2422 CSR_WRITE_2(sc, RL_IMR, 0); 2423 2424 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2425 2426 return (FILTER_HANDLED); 2427 } 2428 2429 static void 2430 re_int_task(void *arg, int npending) 2431 { 2432 struct rl_softc *sc; 2433 struct ifnet *ifp; 2434 u_int16_t status; 2435 int rval = 0; 2436 2437 sc = arg; 2438 ifp = sc->rl_ifp; 2439 2440 RL_LOCK(sc); 2441 2442 status = CSR_READ_2(sc, RL_ISR); 2443 CSR_WRITE_2(sc, RL_ISR, status); 2444 2445 if (sc->suspended || 2446 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2447 RL_UNLOCK(sc); 2448 return; 2449 } 2450 2451 #ifdef DEVICE_POLLING 2452 if (ifp->if_capenable & IFCAP_POLLING) { 2453 RL_UNLOCK(sc); 2454 return; 2455 } 2456 #endif 2457 2458 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2459 rval = re_rxeof(sc, NULL); 2460 2461 /* 2462 * Some chips will ignore a second TX request issued 2463 * while an existing transmission is in progress. If 2464 * the transmitter goes idle but there are still 2465 * packets waiting to be sent, we need to restart the 2466 * channel here to flush them out. This only seems to 2467 * be required with the PCIe devices. 2468 */ 2469 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2470 (sc->rl_flags & RL_FLAG_PCIE)) 2471 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2472 if (status & ( 2473 #ifdef RE_TX_MODERATION 2474 RL_ISR_TIMEOUT_EXPIRED| 2475 #else 2476 RL_ISR_TX_OK| 2477 #endif 2478 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2479 re_txeof(sc); 2480 2481 if (status & RL_ISR_SYSTEM_ERR) { 2482 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2483 re_init_locked(sc); 2484 } 2485 2486 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2487 re_start_locked(ifp); 2488 2489 RL_UNLOCK(sc); 2490 2491 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2492 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2493 return; 2494 } 2495 2496 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2497 } 2498 2499 static void 2500 re_intr_msi(void *xsc) 2501 { 2502 struct rl_softc *sc; 2503 struct ifnet *ifp; 2504 uint16_t intrs, status; 2505 2506 sc = xsc; 2507 RL_LOCK(sc); 2508 2509 ifp = sc->rl_ifp; 2510 #ifdef DEVICE_POLLING 2511 if (ifp->if_capenable & IFCAP_POLLING) { 2512 RL_UNLOCK(sc); 2513 return; 2514 } 2515 #endif 2516 /* Disable interrupts. */ 2517 CSR_WRITE_2(sc, RL_IMR, 0); 2518 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2519 RL_UNLOCK(sc); 2520 return; 2521 } 2522 2523 intrs = RL_INTRS_CPLUS; 2524 status = CSR_READ_2(sc, RL_ISR); 2525 CSR_WRITE_2(sc, RL_ISR, status); 2526 if (sc->rl_int_rx_act > 0) { 2527 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW | 2528 RL_ISR_RX_OVERRUN); 2529 status &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW | 2530 RL_ISR_RX_OVERRUN); 2531 } 2532 2533 if (status & (RL_ISR_TIMEOUT_EXPIRED | RL_ISR_RX_OK | RL_ISR_RX_ERR | 2534 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) { 2535 re_rxeof(sc, NULL); 2536 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2537 if (sc->rl_int_rx_mod != 0 && 2538 (status & (RL_ISR_RX_OK | RL_ISR_RX_ERR | 2539 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) != 0) { 2540 /* Rearm one-shot timer. */ 2541 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2542 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | 2543 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN); 2544 sc->rl_int_rx_act = 1; 2545 } else { 2546 intrs |= RL_ISR_RX_OK | RL_ISR_RX_ERR | 2547 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN; 2548 sc->rl_int_rx_act = 0; 2549 } 2550 } 2551 } 2552 2553 /* 2554 * Some chips will ignore a second TX request issued 2555 * while an existing transmission is in progress. If 2556 * the transmitter goes idle but there are still 2557 * packets waiting to be sent, we need to restart the 2558 * channel here to flush them out. This only seems to 2559 * be required with the PCIe devices. 2560 */ 2561 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2562 (sc->rl_flags & RL_FLAG_PCIE)) 2563 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2564 if (status & (RL_ISR_TX_OK | RL_ISR_TX_ERR | RL_ISR_TX_DESC_UNAVAIL)) 2565 re_txeof(sc); 2566 2567 if (status & RL_ISR_SYSTEM_ERR) { 2568 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2569 re_init_locked(sc); 2570 } 2571 2572 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2573 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2574 re_start_locked(ifp); 2575 CSR_WRITE_2(sc, RL_IMR, intrs); 2576 } 2577 RL_UNLOCK(sc); 2578 } 2579 2580 static int 2581 re_encap(struct rl_softc *sc, struct mbuf **m_head) 2582 { 2583 struct rl_txdesc *txd, *txd_last; 2584 bus_dma_segment_t segs[RL_NTXSEGS]; 2585 bus_dmamap_t map; 2586 struct mbuf *m_new; 2587 struct rl_desc *desc; 2588 int nsegs, prod; 2589 int i, error, ei, si; 2590 int padlen; 2591 uint32_t cmdstat, csum_flags, vlanctl; 2592 2593 RL_LOCK_ASSERT(sc); 2594 M_ASSERTPKTHDR((*m_head)); 2595 2596 /* 2597 * With some of the RealTek chips, using the checksum offload 2598 * support in conjunction with the autopadding feature results 2599 * in the transmission of corrupt frames. For example, if we 2600 * need to send a really small IP fragment that's less than 60 2601 * bytes in size, and IP header checksumming is enabled, the 2602 * resulting ethernet frame that appears on the wire will 2603 * have garbled payload. To work around this, if TX IP checksum 2604 * offload is enabled, we always manually pad short frames out 2605 * to the minimum ethernet frame size. 2606 */ 2607 if ((sc->rl_flags & RL_FLAG_AUTOPAD) == 0 && 2608 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN && 2609 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) { 2610 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2611 if (M_WRITABLE(*m_head) == 0) { 2612 /* Get a writable copy. */ 2613 m_new = m_dup(*m_head, M_DONTWAIT); 2614 m_freem(*m_head); 2615 if (m_new == NULL) { 2616 *m_head = NULL; 2617 return (ENOBUFS); 2618 } 2619 *m_head = m_new; 2620 } 2621 if ((*m_head)->m_next != NULL || 2622 M_TRAILINGSPACE(*m_head) < padlen) { 2623 m_new = m_defrag(*m_head, M_DONTWAIT); 2624 if (m_new == NULL) { 2625 m_freem(*m_head); 2626 *m_head = NULL; 2627 return (ENOBUFS); 2628 } 2629 } else 2630 m_new = *m_head; 2631 2632 /* 2633 * Manually pad short frames, and zero the pad space 2634 * to avoid leaking data. 2635 */ 2636 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2637 m_new->m_pkthdr.len += padlen; 2638 m_new->m_len = m_new->m_pkthdr.len; 2639 *m_head = m_new; 2640 } 2641 2642 prod = sc->rl_ldata.rl_tx_prodidx; 2643 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2644 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2645 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2646 if (error == EFBIG) { 2647 m_new = m_collapse(*m_head, M_DONTWAIT, RL_NTXSEGS); 2648 if (m_new == NULL) { 2649 m_freem(*m_head); 2650 *m_head = NULL; 2651 return (ENOBUFS); 2652 } 2653 *m_head = m_new; 2654 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2655 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2656 if (error != 0) { 2657 m_freem(*m_head); 2658 *m_head = NULL; 2659 return (error); 2660 } 2661 } else if (error != 0) 2662 return (error); 2663 if (nsegs == 0) { 2664 m_freem(*m_head); 2665 *m_head = NULL; 2666 return (EIO); 2667 } 2668 2669 /* Check for number of available descriptors. */ 2670 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2671 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2672 return (ENOBUFS); 2673 } 2674 2675 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2676 BUS_DMASYNC_PREWRITE); 2677 2678 /* 2679 * Set up checksum offload. Note: checksum offload bits must 2680 * appear in all descriptors of a multi-descriptor transmit 2681 * attempt. This is according to testing done with an 8169 2682 * chip. This is a requirement. 2683 */ 2684 vlanctl = 0; 2685 csum_flags = 0; 2686 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2687 if ((sc->rl_flags & RL_FLAG_DESCV2) != 0) { 2688 csum_flags |= RL_TDESC_CMD_LGSEND; 2689 vlanctl |= ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2690 RL_TDESC_CMD_MSSVALV2_SHIFT); 2691 } else { 2692 csum_flags |= RL_TDESC_CMD_LGSEND | 2693 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2694 RL_TDESC_CMD_MSSVAL_SHIFT); 2695 } 2696 } else { 2697 /* 2698 * Unconditionally enable IP checksum if TCP or UDP 2699 * checksum is required. Otherwise, TCP/UDP checksum 2700 * does't make effects. 2701 */ 2702 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) { 2703 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2704 csum_flags |= RL_TDESC_CMD_IPCSUM; 2705 if (((*m_head)->m_pkthdr.csum_flags & 2706 CSUM_TCP) != 0) 2707 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2708 if (((*m_head)->m_pkthdr.csum_flags & 2709 CSUM_UDP) != 0) 2710 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2711 } else { 2712 vlanctl |= RL_TDESC_CMD_IPCSUMV2; 2713 if (((*m_head)->m_pkthdr.csum_flags & 2714 CSUM_TCP) != 0) 2715 vlanctl |= RL_TDESC_CMD_TCPCSUMV2; 2716 if (((*m_head)->m_pkthdr.csum_flags & 2717 CSUM_UDP) != 0) 2718 vlanctl |= RL_TDESC_CMD_UDPCSUMV2; 2719 } 2720 } 2721 } 2722 2723 /* 2724 * Set up hardware VLAN tagging. Note: vlan tag info must 2725 * appear in all descriptors of a multi-descriptor 2726 * transmission attempt. 2727 */ 2728 if ((*m_head)->m_flags & M_VLANTAG) 2729 vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) | 2730 RL_TDESC_VLANCTL_TAG; 2731 2732 si = prod; 2733 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2734 desc = &sc->rl_ldata.rl_tx_list[prod]; 2735 desc->rl_vlanctl = htole32(vlanctl); 2736 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2737 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2738 cmdstat = segs[i].ds_len; 2739 if (i != 0) 2740 cmdstat |= RL_TDESC_CMD_OWN; 2741 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2742 cmdstat |= RL_TDESC_CMD_EOR; 2743 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2744 sc->rl_ldata.rl_tx_free--; 2745 } 2746 /* Update producer index. */ 2747 sc->rl_ldata.rl_tx_prodidx = prod; 2748 2749 /* Set EOF on the last descriptor. */ 2750 ei = RL_TX_DESC_PRV(sc, prod); 2751 desc = &sc->rl_ldata.rl_tx_list[ei]; 2752 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2753 2754 desc = &sc->rl_ldata.rl_tx_list[si]; 2755 /* Set SOF and transfer ownership of packet to the chip. */ 2756 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2757 2758 /* 2759 * Insure that the map for this transmission 2760 * is placed at the array index of the last descriptor 2761 * in this chain. (Swap last and first dmamaps.) 2762 */ 2763 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2764 map = txd->tx_dmamap; 2765 txd->tx_dmamap = txd_last->tx_dmamap; 2766 txd_last->tx_dmamap = map; 2767 txd_last->tx_m = *m_head; 2768 2769 return (0); 2770 } 2771 2772 static void 2773 re_start(struct ifnet *ifp) 2774 { 2775 struct rl_softc *sc; 2776 2777 sc = ifp->if_softc; 2778 RL_LOCK(sc); 2779 re_start_locked(ifp); 2780 RL_UNLOCK(sc); 2781 } 2782 2783 /* 2784 * Main transmit routine for C+ and gigE NICs. 2785 */ 2786 static void 2787 re_start_locked(struct ifnet *ifp) 2788 { 2789 struct rl_softc *sc; 2790 struct mbuf *m_head; 2791 int queued; 2792 2793 sc = ifp->if_softc; 2794 2795 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2796 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) 2797 return; 2798 2799 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2800 sc->rl_ldata.rl_tx_free > 1;) { 2801 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2802 if (m_head == NULL) 2803 break; 2804 2805 if (re_encap(sc, &m_head) != 0) { 2806 if (m_head == NULL) 2807 break; 2808 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2809 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2810 break; 2811 } 2812 2813 /* 2814 * If there's a BPF listener, bounce a copy of this frame 2815 * to him. 2816 */ 2817 ETHER_BPF_MTAP(ifp, m_head); 2818 2819 queued++; 2820 } 2821 2822 if (queued == 0) { 2823 #ifdef RE_TX_MODERATION 2824 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2825 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2826 #endif 2827 return; 2828 } 2829 2830 /* Flush the TX descriptors */ 2831 2832 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2833 sc->rl_ldata.rl_tx_list_map, 2834 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2835 2836 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2837 2838 #ifdef RE_TX_MODERATION 2839 /* 2840 * Use the countdown timer for interrupt moderation. 2841 * 'TX done' interrupts are disabled. Instead, we reset the 2842 * countdown timer, which will begin counting until it hits 2843 * the value in the TIMERINT register, and then trigger an 2844 * interrupt. Each time we write to the TIMERCNT register, 2845 * the timer count is reset to 0. 2846 */ 2847 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2848 #endif 2849 2850 /* 2851 * Set a timeout in case the chip goes out to lunch. 2852 */ 2853 sc->rl_watchdog_timer = 5; 2854 } 2855 2856 static void 2857 re_set_jumbo(struct rl_softc *sc, int jumbo) 2858 { 2859 2860 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168E_VL) { 2861 pci_set_max_read_req(sc->rl_dev, 4096); 2862 return; 2863 } 2864 2865 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2866 if (jumbo != 0) { 2867 CSR_WRITE_1(sc, RL_CFG3, CSR_READ_1(sc, RL_CFG3) | 2868 RL_CFG3_JUMBO_EN0); 2869 switch (sc->rl_hwrev->rl_rev) { 2870 case RL_HWREV_8168DP: 2871 break; 2872 case RL_HWREV_8168E: 2873 CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) | 2874 0x01); 2875 break; 2876 default: 2877 CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) | 2878 RL_CFG4_JUMBO_EN1); 2879 } 2880 } else { 2881 CSR_WRITE_1(sc, RL_CFG3, CSR_READ_1(sc, RL_CFG3) & 2882 ~RL_CFG3_JUMBO_EN0); 2883 switch (sc->rl_hwrev->rl_rev) { 2884 case RL_HWREV_8168DP: 2885 break; 2886 case RL_HWREV_8168E: 2887 CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) & 2888 ~0x01); 2889 break; 2890 default: 2891 CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) & 2892 ~RL_CFG4_JUMBO_EN1); 2893 } 2894 } 2895 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2896 2897 switch (sc->rl_hwrev->rl_rev) { 2898 case RL_HWREV_8168DP: 2899 pci_set_max_read_req(sc->rl_dev, 4096); 2900 break; 2901 default: 2902 if (jumbo != 0) 2903 pci_set_max_read_req(sc->rl_dev, 512); 2904 else 2905 pci_set_max_read_req(sc->rl_dev, 4096); 2906 } 2907 } 2908 2909 static void 2910 re_init(void *xsc) 2911 { 2912 struct rl_softc *sc = xsc; 2913 2914 RL_LOCK(sc); 2915 re_init_locked(sc); 2916 RL_UNLOCK(sc); 2917 } 2918 2919 static void 2920 re_init_locked(struct rl_softc *sc) 2921 { 2922 struct ifnet *ifp = sc->rl_ifp; 2923 struct mii_data *mii; 2924 uint32_t reg; 2925 uint16_t cfg; 2926 union { 2927 uint32_t align_dummy; 2928 u_char eaddr[ETHER_ADDR_LEN]; 2929 } eaddr; 2930 2931 RL_LOCK_ASSERT(sc); 2932 2933 mii = device_get_softc(sc->rl_miibus); 2934 2935 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2936 return; 2937 2938 /* 2939 * Cancel pending I/O and free all RX/TX buffers. 2940 */ 2941 re_stop(sc); 2942 2943 /* Put controller into known state. */ 2944 re_reset(sc); 2945 2946 /* 2947 * For C+ mode, initialize the RX descriptors and mbufs. 2948 */ 2949 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 2950 if (ifp->if_mtu > RL_MTU) { 2951 if (re_jrx_list_init(sc) != 0) { 2952 device_printf(sc->rl_dev, 2953 "no memory for jumbo RX buffers\n"); 2954 re_stop(sc); 2955 return; 2956 } 2957 /* Disable checksum offloading for jumbo frames. */ 2958 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_TSO4); 2959 ifp->if_hwassist &= ~(RE_CSUM_FEATURES | CSUM_TSO); 2960 } else { 2961 if (re_rx_list_init(sc) != 0) { 2962 device_printf(sc->rl_dev, 2963 "no memory for RX buffers\n"); 2964 re_stop(sc); 2965 return; 2966 } 2967 } 2968 re_set_jumbo(sc, ifp->if_mtu > RL_MTU); 2969 } else { 2970 if (re_rx_list_init(sc) != 0) { 2971 device_printf(sc->rl_dev, "no memory for RX buffers\n"); 2972 re_stop(sc); 2973 return; 2974 } 2975 if ((sc->rl_flags & RL_FLAG_PCIE) != 0 && 2976 pci_get_device(sc->rl_dev) != RT_DEVICEID_8101E) { 2977 if (ifp->if_mtu > RL_MTU) 2978 pci_set_max_read_req(sc->rl_dev, 512); 2979 else 2980 pci_set_max_read_req(sc->rl_dev, 4096); 2981 } 2982 } 2983 re_tx_list_init(sc); 2984 2985 /* 2986 * Enable C+ RX and TX mode, as well as VLAN stripping and 2987 * RX checksum offload. We must configure the C+ register 2988 * before all others. 2989 */ 2990 cfg = RL_CPLUSCMD_PCI_MRW; 2991 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2992 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 2993 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2994 cfg |= RL_CPLUSCMD_VLANSTRIP; 2995 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) { 2996 cfg |= RL_CPLUSCMD_MACSTAT_DIS; 2997 /* XXX magic. */ 2998 cfg |= 0x0001; 2999 } else 3000 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB; 3001 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg); 3002 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SC || 3003 sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) { 3004 reg = 0x000fff00; 3005 if ((CSR_READ_1(sc, RL_CFG2) & RL_CFG2_PCI66MHZ) != 0) 3006 reg |= 0x000000ff; 3007 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) 3008 reg |= 0x00f00000; 3009 CSR_WRITE_4(sc, 0x7c, reg); 3010 /* Disable interrupt mitigation. */ 3011 CSR_WRITE_2(sc, 0xe2, 0); 3012 } 3013 /* 3014 * Disable TSO if interface MTU size is greater than MSS 3015 * allowed in controller. 3016 */ 3017 if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) { 3018 ifp->if_capenable &= ~IFCAP_TSO4; 3019 ifp->if_hwassist &= ~CSUM_TSO; 3020 } 3021 3022 /* 3023 * Init our MAC address. Even though the chipset 3024 * documentation doesn't mention it, we need to enter "Config 3025 * register write enable" mode to modify the ID registers. 3026 */ 3027 /* Copy MAC address on stack to align. */ 3028 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 3029 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 3030 CSR_WRITE_4(sc, RL_IDR0, 3031 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 3032 CSR_WRITE_4(sc, RL_IDR4, 3033 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 3034 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3035 3036 /* 3037 * Load the addresses of the RX and TX lists into the chip. 3038 */ 3039 3040 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 3041 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 3042 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 3043 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 3044 3045 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 3046 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 3047 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 3048 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 3049 3050 /* 3051 * Enable transmit and receive. 3052 */ 3053 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 3054 3055 /* 3056 * Set the initial TX configuration. 3057 */ 3058 if (sc->rl_testmode) { 3059 if (sc->rl_type == RL_8169) 3060 CSR_WRITE_4(sc, RL_TXCFG, 3061 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 3062 else 3063 CSR_WRITE_4(sc, RL_TXCFG, 3064 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 3065 } else 3066 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 3067 3068 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 3069 3070 /* 3071 * Set the initial RX configuration. 3072 */ 3073 re_set_rxmode(sc); 3074 3075 /* Configure interrupt moderation. */ 3076 if (sc->rl_type == RL_8169) { 3077 /* Magic from vendor. */ 3078 CSR_WRITE_2(sc, RL_INTRMOD, 0x5100); 3079 } 3080 3081 #ifdef DEVICE_POLLING 3082 /* 3083 * Disable interrupts if we are polling. 3084 */ 3085 if (ifp->if_capenable & IFCAP_POLLING) 3086 CSR_WRITE_2(sc, RL_IMR, 0); 3087 else /* otherwise ... */ 3088 #endif 3089 3090 /* 3091 * Enable interrupts. 3092 */ 3093 if (sc->rl_testmode) 3094 CSR_WRITE_2(sc, RL_IMR, 0); 3095 else 3096 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 3097 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 3098 3099 /* Set initial TX threshold */ 3100 sc->rl_txthresh = RL_TX_THRESH_INIT; 3101 3102 /* Start RX/TX process. */ 3103 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 3104 #ifdef notdef 3105 /* Enable receiver and transmitter. */ 3106 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 3107 #endif 3108 3109 /* 3110 * Initialize the timer interrupt register so that 3111 * a timer interrupt will be generated once the timer 3112 * reaches a certain number of ticks. The timer is 3113 * reloaded on each transmit. 3114 */ 3115 #ifdef RE_TX_MODERATION 3116 /* 3117 * Use timer interrupt register to moderate TX interrupt 3118 * moderation, which dramatically improves TX frame rate. 3119 */ 3120 if (sc->rl_type == RL_8169) 3121 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 3122 else 3123 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 3124 #else 3125 /* 3126 * Use timer interrupt register to moderate RX interrupt 3127 * moderation. 3128 */ 3129 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 && 3130 intr_filter == 0) { 3131 if (sc->rl_type == RL_8169) 3132 CSR_WRITE_4(sc, RL_TIMERINT_8169, 3133 RL_USECS(sc->rl_int_rx_mod)); 3134 } else { 3135 if (sc->rl_type == RL_8169) 3136 CSR_WRITE_4(sc, RL_TIMERINT_8169, RL_USECS(0)); 3137 } 3138 #endif 3139 3140 /* 3141 * For 8169 gigE NICs, set the max allowed RX packet 3142 * size so we can receive jumbo frames. 3143 */ 3144 if (sc->rl_type == RL_8169) { 3145 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3146 /* 3147 * For controllers that use new jumbo frame scheme, 3148 * set maximum size of jumbo frame depedning on 3149 * controller revisions. 3150 */ 3151 if (ifp->if_mtu > RL_MTU) 3152 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 3153 sc->rl_hwrev->rl_max_mtu + 3154 ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN + 3155 ETHER_CRC_LEN); 3156 else 3157 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 3158 RE_RX_DESC_BUFLEN); 3159 } else if ((sc->rl_flags & RL_FLAG_PCIE) != 0 && 3160 sc->rl_hwrev->rl_max_mtu == RL_MTU) { 3161 /* RTL810x has no jumbo frame support. */ 3162 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, RE_RX_DESC_BUFLEN); 3163 } else 3164 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 3165 } 3166 3167 if (sc->rl_testmode) 3168 return; 3169 3170 mii_mediachg(mii); 3171 3172 CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD); 3173 3174 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3175 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3176 3177 sc->rl_flags &= ~RL_FLAG_LINK; 3178 sc->rl_watchdog_timer = 0; 3179 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 3180 } 3181 3182 /* 3183 * Set media options. 3184 */ 3185 static int 3186 re_ifmedia_upd(struct ifnet *ifp) 3187 { 3188 struct rl_softc *sc; 3189 struct mii_data *mii; 3190 int error; 3191 3192 sc = ifp->if_softc; 3193 mii = device_get_softc(sc->rl_miibus); 3194 RL_LOCK(sc); 3195 error = mii_mediachg(mii); 3196 RL_UNLOCK(sc); 3197 3198 return (error); 3199 } 3200 3201 /* 3202 * Report current media status. 3203 */ 3204 static void 3205 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3206 { 3207 struct rl_softc *sc; 3208 struct mii_data *mii; 3209 3210 sc = ifp->if_softc; 3211 mii = device_get_softc(sc->rl_miibus); 3212 3213 RL_LOCK(sc); 3214 mii_pollstat(mii); 3215 RL_UNLOCK(sc); 3216 ifmr->ifm_active = mii->mii_media_active; 3217 ifmr->ifm_status = mii->mii_media_status; 3218 } 3219 3220 static int 3221 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3222 { 3223 struct rl_softc *sc = ifp->if_softc; 3224 struct ifreq *ifr = (struct ifreq *) data; 3225 struct mii_data *mii; 3226 uint32_t rev; 3227 int error = 0; 3228 3229 switch (command) { 3230 case SIOCSIFMTU: 3231 if (ifr->ifr_mtu < ETHERMIN || 3232 ifr->ifr_mtu > sc->rl_hwrev->rl_max_mtu) { 3233 error = EINVAL; 3234 break; 3235 } 3236 RL_LOCK(sc); 3237 if (ifp->if_mtu != ifr->ifr_mtu) { 3238 ifp->if_mtu = ifr->ifr_mtu; 3239 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 3240 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3241 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3242 re_init_locked(sc); 3243 } 3244 if (ifp->if_mtu > RL_TSO_MTU && 3245 (ifp->if_capenable & IFCAP_TSO4) != 0) { 3246 ifp->if_capenable &= ~(IFCAP_TSO4 | 3247 IFCAP_VLAN_HWTSO); 3248 ifp->if_hwassist &= ~CSUM_TSO; 3249 } 3250 VLAN_CAPABILITIES(ifp); 3251 } 3252 RL_UNLOCK(sc); 3253 break; 3254 case SIOCSIFFLAGS: 3255 RL_LOCK(sc); 3256 if ((ifp->if_flags & IFF_UP) != 0) { 3257 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3258 if (((ifp->if_flags ^ sc->rl_if_flags) 3259 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 3260 re_set_rxmode(sc); 3261 } else 3262 re_init_locked(sc); 3263 } else { 3264 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3265 re_stop(sc); 3266 } 3267 sc->rl_if_flags = ifp->if_flags; 3268 RL_UNLOCK(sc); 3269 break; 3270 case SIOCADDMULTI: 3271 case SIOCDELMULTI: 3272 RL_LOCK(sc); 3273 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3274 re_set_rxmode(sc); 3275 RL_UNLOCK(sc); 3276 break; 3277 case SIOCGIFMEDIA: 3278 case SIOCSIFMEDIA: 3279 mii = device_get_softc(sc->rl_miibus); 3280 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3281 break; 3282 case SIOCSIFCAP: 3283 { 3284 int mask, reinit; 3285 3286 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3287 reinit = 0; 3288 #ifdef DEVICE_POLLING 3289 if (mask & IFCAP_POLLING) { 3290 if (ifr->ifr_reqcap & IFCAP_POLLING) { 3291 error = ether_poll_register(re_poll, ifp); 3292 if (error) 3293 return (error); 3294 RL_LOCK(sc); 3295 /* Disable interrupts */ 3296 CSR_WRITE_2(sc, RL_IMR, 0x0000); 3297 ifp->if_capenable |= IFCAP_POLLING; 3298 RL_UNLOCK(sc); 3299 } else { 3300 error = ether_poll_deregister(ifp); 3301 /* Enable interrupts. */ 3302 RL_LOCK(sc); 3303 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 3304 ifp->if_capenable &= ~IFCAP_POLLING; 3305 RL_UNLOCK(sc); 3306 } 3307 } 3308 #endif /* DEVICE_POLLING */ 3309 if ((mask & IFCAP_TXCSUM) != 0 && 3310 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 3311 ifp->if_capenable ^= IFCAP_TXCSUM; 3312 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) { 3313 rev = sc->rl_hwrev->rl_rev; 3314 if (rev == RL_HWREV_8168C || 3315 rev == RL_HWREV_8168C_SPIN2) 3316 ifp->if_hwassist |= CSUM_TCP | CSUM_UDP; 3317 else 3318 ifp->if_hwassist |= RE_CSUM_FEATURES; 3319 } else 3320 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 3321 reinit = 1; 3322 } 3323 if ((mask & IFCAP_RXCSUM) != 0 && 3324 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 3325 ifp->if_capenable ^= IFCAP_RXCSUM; 3326 reinit = 1; 3327 } 3328 if ((mask & IFCAP_TSO4) != 0 && 3329 (ifp->if_capabilities & IFCAP_TSO) != 0) { 3330 ifp->if_capenable ^= IFCAP_TSO4; 3331 if ((IFCAP_TSO4 & ifp->if_capenable) != 0) 3332 ifp->if_hwassist |= CSUM_TSO; 3333 else 3334 ifp->if_hwassist &= ~CSUM_TSO; 3335 if (ifp->if_mtu > RL_TSO_MTU && 3336 (ifp->if_capenable & IFCAP_TSO4) != 0) { 3337 ifp->if_capenable &= ~IFCAP_TSO4; 3338 ifp->if_hwassist &= ~CSUM_TSO; 3339 } 3340 } 3341 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 3342 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 3343 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 3344 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3345 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 3346 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 3347 /* TSO over VLAN requires VLAN hardware tagging. */ 3348 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 3349 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 3350 reinit = 1; 3351 } 3352 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 3353 (mask & (IFCAP_HWCSUM | IFCAP_TSO4 | 3354 IFCAP_VLAN_HWTSO)) != 0) 3355 reinit = 1; 3356 if ((mask & IFCAP_WOL) != 0 && 3357 (ifp->if_capabilities & IFCAP_WOL) != 0) { 3358 if ((mask & IFCAP_WOL_UCAST) != 0) 3359 ifp->if_capenable ^= IFCAP_WOL_UCAST; 3360 if ((mask & IFCAP_WOL_MCAST) != 0) 3361 ifp->if_capenable ^= IFCAP_WOL_MCAST; 3362 if ((mask & IFCAP_WOL_MAGIC) != 0) 3363 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 3364 } 3365 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) { 3366 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3367 re_init(sc); 3368 } 3369 VLAN_CAPABILITIES(ifp); 3370 } 3371 break; 3372 default: 3373 error = ether_ioctl(ifp, command, data); 3374 break; 3375 } 3376 3377 return (error); 3378 } 3379 3380 static void 3381 re_watchdog(struct rl_softc *sc) 3382 { 3383 struct ifnet *ifp; 3384 3385 RL_LOCK_ASSERT(sc); 3386 3387 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 3388 return; 3389 3390 ifp = sc->rl_ifp; 3391 re_txeof(sc); 3392 if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) { 3393 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 3394 "-- recovering\n"); 3395 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3396 re_start_locked(ifp); 3397 return; 3398 } 3399 3400 if_printf(ifp, "watchdog timeout\n"); 3401 ifp->if_oerrors++; 3402 3403 re_rxeof(sc, NULL); 3404 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3405 re_init_locked(sc); 3406 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3407 re_start_locked(ifp); 3408 } 3409 3410 /* 3411 * Stop the adapter and free any mbufs allocated to the 3412 * RX and TX lists. 3413 */ 3414 static void 3415 re_stop(struct rl_softc *sc) 3416 { 3417 int i; 3418 struct ifnet *ifp; 3419 struct rl_txdesc *txd; 3420 struct rl_rxdesc *rxd; 3421 3422 RL_LOCK_ASSERT(sc); 3423 3424 ifp = sc->rl_ifp; 3425 3426 sc->rl_watchdog_timer = 0; 3427 callout_stop(&sc->rl_stat_callout); 3428 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3429 3430 if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0) 3431 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB | 3432 RL_CMD_RX_ENB); 3433 else 3434 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 3435 DELAY(1000); 3436 CSR_WRITE_2(sc, RL_IMR, 0x0000); 3437 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 3438 3439 if (sc->rl_head != NULL) { 3440 m_freem(sc->rl_head); 3441 sc->rl_head = sc->rl_tail = NULL; 3442 } 3443 3444 /* Free the TX list buffers. */ 3445 3446 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 3447 txd = &sc->rl_ldata.rl_tx_desc[i]; 3448 if (txd->tx_m != NULL) { 3449 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 3450 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3451 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 3452 txd->tx_dmamap); 3453 m_freem(txd->tx_m); 3454 txd->tx_m = NULL; 3455 } 3456 } 3457 3458 /* Free the RX list buffers. */ 3459 3460 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 3461 rxd = &sc->rl_ldata.rl_rx_desc[i]; 3462 if (rxd->rx_m != NULL) { 3463 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 3464 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3465 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 3466 rxd->rx_dmamap); 3467 m_freem(rxd->rx_m); 3468 rxd->rx_m = NULL; 3469 } 3470 } 3471 } 3472 3473 /* 3474 * Device suspend routine. Stop the interface and save some PCI 3475 * settings in case the BIOS doesn't restore them properly on 3476 * resume. 3477 */ 3478 static int 3479 re_suspend(device_t dev) 3480 { 3481 struct rl_softc *sc; 3482 3483 sc = device_get_softc(dev); 3484 3485 RL_LOCK(sc); 3486 re_stop(sc); 3487 re_setwol(sc); 3488 sc->suspended = 1; 3489 RL_UNLOCK(sc); 3490 3491 return (0); 3492 } 3493 3494 /* 3495 * Device resume routine. Restore some PCI settings in case the BIOS 3496 * doesn't, re-enable busmastering, and restart the interface if 3497 * appropriate. 3498 */ 3499 static int 3500 re_resume(device_t dev) 3501 { 3502 struct rl_softc *sc; 3503 struct ifnet *ifp; 3504 3505 sc = device_get_softc(dev); 3506 3507 RL_LOCK(sc); 3508 3509 ifp = sc->rl_ifp; 3510 /* Take controller out of sleep mode. */ 3511 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3512 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3513 CSR_WRITE_1(sc, RL_GPIO, 3514 CSR_READ_1(sc, RL_GPIO) | 0x01); 3515 } 3516 3517 /* 3518 * Clear WOL matching such that normal Rx filtering 3519 * wouldn't interfere with WOL patterns. 3520 */ 3521 re_clrwol(sc); 3522 3523 /* reinitialize interface if necessary */ 3524 if (ifp->if_flags & IFF_UP) 3525 re_init_locked(sc); 3526 3527 sc->suspended = 0; 3528 RL_UNLOCK(sc); 3529 3530 return (0); 3531 } 3532 3533 /* 3534 * Stop all chip I/O so that the kernel's probe routines don't 3535 * get confused by errant DMAs when rebooting. 3536 */ 3537 static int 3538 re_shutdown(device_t dev) 3539 { 3540 struct rl_softc *sc; 3541 3542 sc = device_get_softc(dev); 3543 3544 RL_LOCK(sc); 3545 re_stop(sc); 3546 /* 3547 * Mark interface as down since otherwise we will panic if 3548 * interrupt comes in later on, which can happen in some 3549 * cases. 3550 */ 3551 sc->rl_ifp->if_flags &= ~IFF_UP; 3552 re_setwol(sc); 3553 RL_UNLOCK(sc); 3554 3555 return (0); 3556 } 3557 3558 static void 3559 re_setwol(struct rl_softc *sc) 3560 { 3561 struct ifnet *ifp; 3562 int pmc; 3563 uint16_t pmstat; 3564 uint8_t v; 3565 3566 RL_LOCK_ASSERT(sc); 3567 3568 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3569 return; 3570 3571 ifp = sc->rl_ifp; 3572 /* Put controller into sleep mode. */ 3573 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3574 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3575 CSR_WRITE_1(sc, RL_GPIO, 3576 CSR_READ_1(sc, RL_GPIO) & ~0x01); 3577 } 3578 if ((ifp->if_capenable & IFCAP_WOL) != 0 && 3579 (sc->rl_flags & RL_FLAG_WOLRXENB) != 0) 3580 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB); 3581 /* Enable config register write. */ 3582 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3583 3584 /* Enable PME. */ 3585 v = CSR_READ_1(sc, RL_CFG1); 3586 v &= ~RL_CFG1_PME; 3587 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3588 v |= RL_CFG1_PME; 3589 CSR_WRITE_1(sc, RL_CFG1, v); 3590 3591 v = CSR_READ_1(sc, RL_CFG3); 3592 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3593 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3594 v |= RL_CFG3_WOL_MAGIC; 3595 CSR_WRITE_1(sc, RL_CFG3, v); 3596 3597 /* Config register write done. */ 3598 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3599 3600 v = CSR_READ_1(sc, RL_CFG5); 3601 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3602 v &= ~RL_CFG5_WOL_LANWAKE; 3603 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 3604 v |= RL_CFG5_WOL_UCAST; 3605 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 3606 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 3607 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3608 v |= RL_CFG5_WOL_LANWAKE; 3609 CSR_WRITE_1(sc, RL_CFG5, v); 3610 3611 if ((ifp->if_capenable & IFCAP_WOL) != 0 && 3612 (sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) 3613 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) & ~0x80); 3614 /* 3615 * It seems that hardware resets its link speed to 100Mbps in 3616 * power down mode so switching to 100Mbps in driver is not 3617 * needed. 3618 */ 3619 3620 /* Request PME if WOL is requested. */ 3621 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 3622 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3623 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3624 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3625 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 3626 } 3627 3628 static void 3629 re_clrwol(struct rl_softc *sc) 3630 { 3631 int pmc; 3632 uint8_t v; 3633 3634 RL_LOCK_ASSERT(sc); 3635 3636 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3637 return; 3638 3639 /* Enable config register write. */ 3640 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3641 3642 v = CSR_READ_1(sc, RL_CFG3); 3643 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3644 CSR_WRITE_1(sc, RL_CFG3, v); 3645 3646 /* Config register write done. */ 3647 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3648 3649 v = CSR_READ_1(sc, RL_CFG5); 3650 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3651 v &= ~RL_CFG5_WOL_LANWAKE; 3652 CSR_WRITE_1(sc, RL_CFG5, v); 3653 } 3654 3655 static void 3656 re_add_sysctls(struct rl_softc *sc) 3657 { 3658 struct sysctl_ctx_list *ctx; 3659 struct sysctl_oid_list *children; 3660 int error; 3661 3662 ctx = device_get_sysctl_ctx(sc->rl_dev); 3663 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev)); 3664 3665 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "stats", 3666 CTLTYPE_INT | CTLFLAG_RW, sc, 0, re_sysctl_stats, "I", 3667 "Statistics Information"); 3668 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) 3669 return; 3670 3671 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "int_rx_mod", 3672 CTLTYPE_INT | CTLFLAG_RW, &sc->rl_int_rx_mod, 0, 3673 sysctl_hw_re_int_mod, "I", "re RX interrupt moderation"); 3674 /* Pull in device tunables. */ 3675 sc->rl_int_rx_mod = RL_TIMER_DEFAULT; 3676 error = resource_int_value(device_get_name(sc->rl_dev), 3677 device_get_unit(sc->rl_dev), "int_rx_mod", &sc->rl_int_rx_mod); 3678 if (error == 0) { 3679 if (sc->rl_int_rx_mod < RL_TIMER_MIN || 3680 sc->rl_int_rx_mod > RL_TIMER_MAX) { 3681 device_printf(sc->rl_dev, "int_rx_mod value out of " 3682 "range; using default: %d\n", 3683 RL_TIMER_DEFAULT); 3684 sc->rl_int_rx_mod = RL_TIMER_DEFAULT; 3685 } 3686 } 3687 3688 } 3689 3690 static int 3691 re_sysctl_stats(SYSCTL_HANDLER_ARGS) 3692 { 3693 struct rl_softc *sc; 3694 struct rl_stats *stats; 3695 int error, i, result; 3696 3697 result = -1; 3698 error = sysctl_handle_int(oidp, &result, 0, req); 3699 if (error || req->newptr == NULL) 3700 return (error); 3701 3702 if (result == 1) { 3703 sc = (struct rl_softc *)arg1; 3704 RL_LOCK(sc); 3705 if ((sc->rl_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 3706 RL_UNLOCK(sc); 3707 goto done; 3708 } 3709 bus_dmamap_sync(sc->rl_ldata.rl_stag, 3710 sc->rl_ldata.rl_smap, BUS_DMASYNC_PREREAD); 3711 CSR_WRITE_4(sc, RL_DUMPSTATS_HI, 3712 RL_ADDR_HI(sc->rl_ldata.rl_stats_addr)); 3713 CSR_WRITE_4(sc, RL_DUMPSTATS_LO, 3714 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr)); 3715 CSR_WRITE_4(sc, RL_DUMPSTATS_LO, 3716 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr | 3717 RL_DUMPSTATS_START)); 3718 for (i = RL_TIMEOUT; i > 0; i--) { 3719 if ((CSR_READ_4(sc, RL_DUMPSTATS_LO) & 3720 RL_DUMPSTATS_START) == 0) 3721 break; 3722 DELAY(1000); 3723 } 3724 bus_dmamap_sync(sc->rl_ldata.rl_stag, 3725 sc->rl_ldata.rl_smap, BUS_DMASYNC_POSTREAD); 3726 RL_UNLOCK(sc); 3727 if (i == 0) { 3728 device_printf(sc->rl_dev, 3729 "DUMP statistics request timedout\n"); 3730 return (ETIMEDOUT); 3731 } 3732 done: 3733 stats = sc->rl_ldata.rl_stats; 3734 printf("%s statistics:\n", device_get_nameunit(sc->rl_dev)); 3735 printf("Tx frames : %ju\n", 3736 (uintmax_t)le64toh(stats->rl_tx_pkts)); 3737 printf("Rx frames : %ju\n", 3738 (uintmax_t)le64toh(stats->rl_rx_pkts)); 3739 printf("Tx errors : %ju\n", 3740 (uintmax_t)le64toh(stats->rl_tx_errs)); 3741 printf("Rx errors : %u\n", 3742 le32toh(stats->rl_rx_errs)); 3743 printf("Rx missed frames : %u\n", 3744 (uint32_t)le16toh(stats->rl_missed_pkts)); 3745 printf("Rx frame alignment errs : %u\n", 3746 (uint32_t)le16toh(stats->rl_rx_framealign_errs)); 3747 printf("Tx single collisions : %u\n", 3748 le32toh(stats->rl_tx_onecoll)); 3749 printf("Tx multiple collisions : %u\n", 3750 le32toh(stats->rl_tx_multicolls)); 3751 printf("Rx unicast frames : %ju\n", 3752 (uintmax_t)le64toh(stats->rl_rx_ucasts)); 3753 printf("Rx broadcast frames : %ju\n", 3754 (uintmax_t)le64toh(stats->rl_rx_bcasts)); 3755 printf("Rx multicast frames : %u\n", 3756 le32toh(stats->rl_rx_mcasts)); 3757 printf("Tx aborts : %u\n", 3758 (uint32_t)le16toh(stats->rl_tx_aborts)); 3759 printf("Tx underruns : %u\n", 3760 (uint32_t)le16toh(stats->rl_rx_underruns)); 3761 } 3762 3763 return (error); 3764 } 3765 3766 static int 3767 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3768 { 3769 int error, value; 3770 3771 if (arg1 == NULL) 3772 return (EINVAL); 3773 value = *(int *)arg1; 3774 error = sysctl_handle_int(oidp, &value, 0, req); 3775 if (error || req->newptr == NULL) 3776 return (error); 3777 if (value < low || value > high) 3778 return (EINVAL); 3779 *(int *)arg1 = value; 3780 3781 return (0); 3782 } 3783 3784 static int 3785 sysctl_hw_re_int_mod(SYSCTL_HANDLER_ARGS) 3786 { 3787 3788 return (sysctl_int_range(oidp, arg1, arg2, req, RL_TIMER_MIN, 3789 RL_TIMER_MAX)); 3790 } 3791