1 /*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44 /* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111 #ifdef HAVE_KERNEL_OPTION_HEADERS 112 #include "opt_device_polling.h" 113 #endif 114 115 #include <sys/param.h> 116 #include <sys/endian.h> 117 #include <sys/systm.h> 118 #include <sys/sockio.h> 119 #include <sys/mbuf.h> 120 #include <sys/malloc.h> 121 #include <sys/module.h> 122 #include <sys/kernel.h> 123 #include <sys/socket.h> 124 #include <sys/lock.h> 125 #include <sys/mutex.h> 126 #include <sys/taskqueue.h> 127 128 #include <net/if.h> 129 #include <net/if_arp.h> 130 #include <net/ethernet.h> 131 #include <net/if_dl.h> 132 #include <net/if_media.h> 133 #include <net/if_types.h> 134 #include <net/if_vlan_var.h> 135 136 #include <net/bpf.h> 137 138 #include <machine/bus.h> 139 #include <machine/resource.h> 140 #include <sys/bus.h> 141 #include <sys/rman.h> 142 143 #include <dev/mii/mii.h> 144 #include <dev/mii/miivar.h> 145 146 #include <dev/pci/pcireg.h> 147 #include <dev/pci/pcivar.h> 148 149 MODULE_DEPEND(re, pci, 1, 1, 1); 150 MODULE_DEPEND(re, ether, 1, 1, 1); 151 MODULE_DEPEND(re, miibus, 1, 1, 1); 152 153 /* "device miibus" required. See GENERIC if you get errors here. */ 154 #include "miibus_if.h" 155 156 /* 157 * Default to using PIO access for this driver. 158 */ 159 #define RE_USEIOSPACE 160 161 #include <pci/if_rlreg.h> 162 163 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 164 165 /* 166 * Various supported device vendors/types and their names. 167 */ 168 static struct rl_type re_devs[] = { 169 { DLINK_VENDORID, DLINK_DEVICEID_528T, RL_HWREV_8169S, 170 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 171 { RT_VENDORID, RT_DEVICEID_8139, RL_HWREV_8139CPLUS, 172 "RealTek 8139C+ 10/100BaseTX" }, 173 { RT_VENDORID, RT_DEVICEID_8101E, RL_HWREV_8101E, 174 "RealTek 8101E PCIe 10/100baseTX" }, 175 { RT_VENDORID, RT_DEVICEID_8168, RL_HWREV_8168_SPIN1, 176 "RealTek 8168/8111B PCIe Gigabit Ethernet" }, 177 { RT_VENDORID, RT_DEVICEID_8168, RL_HWREV_8168_SPIN2, 178 "RealTek 8168/8111B PCIe Gigabit Ethernet" }, 179 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169, 180 "RealTek 8169 Gigabit Ethernet" }, 181 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169S, 182 "RealTek 8169S Single-chip Gigabit Ethernet" }, 183 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169_8110SB, 184 "RealTek 8169SB/8110SB Single-chip Gigabit Ethernet" }, 185 { RT_VENDORID, RT_DEVICEID_8169SC, RL_HWREV_8169_8110SC, 186 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 187 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8110S, 188 "RealTek 8110S Single-chip Gigabit Ethernet" }, 189 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, RL_HWREV_8169S, 190 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 191 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, RL_HWREV_8169S, 192 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 193 { USR_VENDORID, USR_DEVICEID_997902, RL_HWREV_8169S, 194 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" }, 195 { 0, 0, 0, NULL } 196 }; 197 198 static struct rl_hwrev re_hwrevs[] = { 199 { RL_HWREV_8139, RL_8139, "" }, 200 { RL_HWREV_8139A, RL_8139, "A" }, 201 { RL_HWREV_8139AG, RL_8139, "A-G" }, 202 { RL_HWREV_8139B, RL_8139, "B" }, 203 { RL_HWREV_8130, RL_8139, "8130" }, 204 { RL_HWREV_8139C, RL_8139, "C" }, 205 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 206 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 207 { RL_HWREV_8168_SPIN1, RL_8169, "8168"}, 208 { RL_HWREV_8169, RL_8169, "8169"}, 209 { RL_HWREV_8169S, RL_8169, "8169S"}, 210 { RL_HWREV_8110S, RL_8169, "8110S"}, 211 { RL_HWREV_8169_8110SB, RL_8169, "8169SB"}, 212 { RL_HWREV_8169_8110SC, RL_8169, "8169SC"}, 213 { RL_HWREV_8100, RL_8139, "8100"}, 214 { RL_HWREV_8101, RL_8139, "8101"}, 215 { RL_HWREV_8100E, RL_8169, "8100E"}, 216 { RL_HWREV_8101E, RL_8169, "8101E"}, 217 { RL_HWREV_8168_SPIN2, RL_8169, "8168"}, 218 { 0, 0, NULL } 219 }; 220 221 static int re_probe (device_t); 222 static int re_attach (device_t); 223 static int re_detach (device_t); 224 225 static int re_encap (struct rl_softc *, struct mbuf **, int *); 226 227 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 228 static void re_dma_map_desc (void *, bus_dma_segment_t *, int, 229 bus_size_t, int); 230 static int re_allocmem (device_t, struct rl_softc *); 231 static int re_newbuf (struct rl_softc *, int, struct mbuf *); 232 static int re_rx_list_init (struct rl_softc *); 233 static int re_tx_list_init (struct rl_softc *); 234 #ifdef RE_FIXUP_RX 235 static __inline void re_fixup_rx 236 (struct mbuf *); 237 #endif 238 static int re_rxeof (struct rl_softc *); 239 static void re_txeof (struct rl_softc *); 240 #ifdef DEVICE_POLLING 241 static void re_poll (struct ifnet *, enum poll_cmd, int); 242 static void re_poll_locked (struct ifnet *, enum poll_cmd, int); 243 #endif 244 static void re_intr (void *); 245 static void re_tick (void *); 246 static void re_tx_task (void *, int); 247 static void re_int_task (void *, int); 248 static void re_start (struct ifnet *); 249 static int re_ioctl (struct ifnet *, u_long, caddr_t); 250 static void re_init (void *); 251 static void re_init_locked (struct rl_softc *); 252 static void re_stop (struct rl_softc *); 253 static void re_watchdog (struct ifnet *); 254 static int re_suspend (device_t); 255 static int re_resume (device_t); 256 static void re_shutdown (device_t); 257 static int re_ifmedia_upd (struct ifnet *); 258 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 259 260 static void re_eeprom_putbyte (struct rl_softc *, int); 261 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 262 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 263 static int re_gmii_readreg (device_t, int, int); 264 static int re_gmii_writereg (device_t, int, int, int); 265 266 static int re_miibus_readreg (device_t, int, int); 267 static int re_miibus_writereg (device_t, int, int, int); 268 static void re_miibus_statchg (device_t); 269 270 static void re_setmulti (struct rl_softc *); 271 static void re_reset (struct rl_softc *); 272 273 #ifdef RE_DIAG 274 static int re_diag (struct rl_softc *); 275 #endif 276 277 #ifdef RE_USEIOSPACE 278 #define RL_RES SYS_RES_IOPORT 279 #define RL_RID RL_PCI_LOIO 280 #else 281 #define RL_RES SYS_RES_MEMORY 282 #define RL_RID RL_PCI_LOMEM 283 #endif 284 285 static device_method_t re_methods[] = { 286 /* Device interface */ 287 DEVMETHOD(device_probe, re_probe), 288 DEVMETHOD(device_attach, re_attach), 289 DEVMETHOD(device_detach, re_detach), 290 DEVMETHOD(device_suspend, re_suspend), 291 DEVMETHOD(device_resume, re_resume), 292 DEVMETHOD(device_shutdown, re_shutdown), 293 294 /* bus interface */ 295 DEVMETHOD(bus_print_child, bus_generic_print_child), 296 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 297 298 /* MII interface */ 299 DEVMETHOD(miibus_readreg, re_miibus_readreg), 300 DEVMETHOD(miibus_writereg, re_miibus_writereg), 301 DEVMETHOD(miibus_statchg, re_miibus_statchg), 302 303 { 0, 0 } 304 }; 305 306 static driver_t re_driver = { 307 "re", 308 re_methods, 309 sizeof(struct rl_softc) 310 }; 311 312 static devclass_t re_devclass; 313 314 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 315 DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0); 316 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 317 318 #define EE_SET(x) \ 319 CSR_WRITE_1(sc, RL_EECMD, \ 320 CSR_READ_1(sc, RL_EECMD) | x) 321 322 #define EE_CLR(x) \ 323 CSR_WRITE_1(sc, RL_EECMD, \ 324 CSR_READ_1(sc, RL_EECMD) & ~x) 325 326 /* 327 * Send a read command and address to the EEPROM, check for ACK. 328 */ 329 static void 330 re_eeprom_putbyte(sc, addr) 331 struct rl_softc *sc; 332 int addr; 333 { 334 register int d, i; 335 336 d = addr | (RL_9346_READ << sc->rl_eewidth); 337 338 /* 339 * Feed in each bit and strobe the clock. 340 */ 341 342 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 343 if (d & i) { 344 EE_SET(RL_EE_DATAIN); 345 } else { 346 EE_CLR(RL_EE_DATAIN); 347 } 348 DELAY(100); 349 EE_SET(RL_EE_CLK); 350 DELAY(150); 351 EE_CLR(RL_EE_CLK); 352 DELAY(100); 353 } 354 355 return; 356 } 357 358 /* 359 * Read a word of data stored in the EEPROM at address 'addr.' 360 */ 361 static void 362 re_eeprom_getword(sc, addr, dest) 363 struct rl_softc *sc; 364 int addr; 365 u_int16_t *dest; 366 { 367 register int i; 368 u_int16_t word = 0; 369 370 /* 371 * Send address of word we want to read. 372 */ 373 re_eeprom_putbyte(sc, addr); 374 375 /* 376 * Start reading bits from EEPROM. 377 */ 378 for (i = 0x8000; i; i >>= 1) { 379 EE_SET(RL_EE_CLK); 380 DELAY(100); 381 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 382 word |= i; 383 EE_CLR(RL_EE_CLK); 384 DELAY(100); 385 } 386 387 *dest = word; 388 389 return; 390 } 391 392 /* 393 * Read a sequence of words from the EEPROM. 394 */ 395 static void 396 re_read_eeprom(sc, dest, off, cnt) 397 struct rl_softc *sc; 398 caddr_t dest; 399 int off; 400 int cnt; 401 { 402 int i; 403 u_int16_t word = 0, *ptr; 404 405 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 406 407 DELAY(100); 408 409 for (i = 0; i < cnt; i++) { 410 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 411 re_eeprom_getword(sc, off + i, &word); 412 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 413 ptr = (u_int16_t *)(dest + (i * 2)); 414 *ptr = word; 415 } 416 417 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 418 419 return; 420 } 421 422 static int 423 re_gmii_readreg(dev, phy, reg) 424 device_t dev; 425 int phy, reg; 426 { 427 struct rl_softc *sc; 428 u_int32_t rval; 429 int i; 430 431 if (phy != 1) 432 return (0); 433 434 sc = device_get_softc(dev); 435 436 /* Let the rgephy driver read the GMEDIASTAT register */ 437 438 if (reg == RL_GMEDIASTAT) { 439 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 440 return (rval); 441 } 442 443 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 444 DELAY(1000); 445 446 for (i = 0; i < RL_TIMEOUT; i++) { 447 rval = CSR_READ_4(sc, RL_PHYAR); 448 if (rval & RL_PHYAR_BUSY) 449 break; 450 DELAY(100); 451 } 452 453 if (i == RL_TIMEOUT) { 454 device_printf(sc->rl_dev, "PHY read failed\n"); 455 return (0); 456 } 457 458 return (rval & RL_PHYAR_PHYDATA); 459 } 460 461 static int 462 re_gmii_writereg(dev, phy, reg, data) 463 device_t dev; 464 int phy, reg, data; 465 { 466 struct rl_softc *sc; 467 u_int32_t rval; 468 int i; 469 470 sc = device_get_softc(dev); 471 472 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 473 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 474 DELAY(1000); 475 476 for (i = 0; i < RL_TIMEOUT; i++) { 477 rval = CSR_READ_4(sc, RL_PHYAR); 478 if (!(rval & RL_PHYAR_BUSY)) 479 break; 480 DELAY(100); 481 } 482 483 if (i == RL_TIMEOUT) { 484 device_printf(sc->rl_dev, "PHY write failed\n"); 485 return (0); 486 } 487 488 return (0); 489 } 490 491 static int 492 re_miibus_readreg(dev, phy, reg) 493 device_t dev; 494 int phy, reg; 495 { 496 struct rl_softc *sc; 497 u_int16_t rval = 0; 498 u_int16_t re8139_reg = 0; 499 500 sc = device_get_softc(dev); 501 502 if (sc->rl_type == RL_8169) { 503 rval = re_gmii_readreg(dev, phy, reg); 504 return (rval); 505 } 506 507 /* Pretend the internal PHY is only at address 0 */ 508 if (phy) { 509 return (0); 510 } 511 switch (reg) { 512 case MII_BMCR: 513 re8139_reg = RL_BMCR; 514 break; 515 case MII_BMSR: 516 re8139_reg = RL_BMSR; 517 break; 518 case MII_ANAR: 519 re8139_reg = RL_ANAR; 520 break; 521 case MII_ANER: 522 re8139_reg = RL_ANER; 523 break; 524 case MII_ANLPAR: 525 re8139_reg = RL_LPAR; 526 break; 527 case MII_PHYIDR1: 528 case MII_PHYIDR2: 529 return (0); 530 /* 531 * Allow the rlphy driver to read the media status 532 * register. If we have a link partner which does not 533 * support NWAY, this is the register which will tell 534 * us the results of parallel detection. 535 */ 536 case RL_MEDIASTAT: 537 rval = CSR_READ_1(sc, RL_MEDIASTAT); 538 return (rval); 539 default: 540 device_printf(sc->rl_dev, "bad phy register\n"); 541 return (0); 542 } 543 rval = CSR_READ_2(sc, re8139_reg); 544 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 545 /* 8139C+ has different bit layout. */ 546 rval &= ~(BMCR_LOOP | BMCR_ISO); 547 } 548 return (rval); 549 } 550 551 static int 552 re_miibus_writereg(dev, phy, reg, data) 553 device_t dev; 554 int phy, reg, data; 555 { 556 struct rl_softc *sc; 557 u_int16_t re8139_reg = 0; 558 int rval = 0; 559 560 sc = device_get_softc(dev); 561 562 if (sc->rl_type == RL_8169) { 563 rval = re_gmii_writereg(dev, phy, reg, data); 564 return (rval); 565 } 566 567 /* Pretend the internal PHY is only at address 0 */ 568 if (phy) 569 return (0); 570 571 switch (reg) { 572 case MII_BMCR: 573 re8139_reg = RL_BMCR; 574 if (sc->rl_type == RL_8139CPLUS) { 575 /* 8139C+ has different bit layout. */ 576 data &= ~(BMCR_LOOP | BMCR_ISO); 577 } 578 break; 579 case MII_BMSR: 580 re8139_reg = RL_BMSR; 581 break; 582 case MII_ANAR: 583 re8139_reg = RL_ANAR; 584 break; 585 case MII_ANER: 586 re8139_reg = RL_ANER; 587 break; 588 case MII_ANLPAR: 589 re8139_reg = RL_LPAR; 590 break; 591 case MII_PHYIDR1: 592 case MII_PHYIDR2: 593 return (0); 594 break; 595 default: 596 device_printf(sc->rl_dev, "bad phy register\n"); 597 return (0); 598 } 599 CSR_WRITE_2(sc, re8139_reg, data); 600 return (0); 601 } 602 603 static void 604 re_miibus_statchg(dev) 605 device_t dev; 606 { 607 608 } 609 610 /* 611 * Program the 64-bit multicast hash filter. 612 */ 613 static void 614 re_setmulti(sc) 615 struct rl_softc *sc; 616 { 617 struct ifnet *ifp; 618 int h = 0; 619 u_int32_t hashes[2] = { 0, 0 }; 620 struct ifmultiaddr *ifma; 621 u_int32_t rxfilt; 622 int mcnt = 0; 623 624 RL_LOCK_ASSERT(sc); 625 626 ifp = sc->rl_ifp; 627 628 rxfilt = CSR_READ_4(sc, RL_RXCFG); 629 630 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 631 rxfilt |= RL_RXCFG_RX_MULTI; 632 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 633 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 634 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 635 return; 636 } 637 638 /* first, zot all the existing hash bits */ 639 CSR_WRITE_4(sc, RL_MAR0, 0); 640 CSR_WRITE_4(sc, RL_MAR4, 0); 641 642 /* now program new ones */ 643 IF_ADDR_LOCK(ifp); 644 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 645 if (ifma->ifma_addr->sa_family != AF_LINK) 646 continue; 647 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 648 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 649 if (h < 32) 650 hashes[0] |= (1 << h); 651 else 652 hashes[1] |= (1 << (h - 32)); 653 mcnt++; 654 } 655 IF_ADDR_UNLOCK(ifp); 656 657 if (mcnt) 658 rxfilt |= RL_RXCFG_RX_MULTI; 659 else 660 rxfilt &= ~RL_RXCFG_RX_MULTI; 661 662 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 663 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 664 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 665 } 666 667 static void 668 re_reset(sc) 669 struct rl_softc *sc; 670 { 671 register int i; 672 673 RL_LOCK_ASSERT(sc); 674 675 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 676 677 for (i = 0; i < RL_TIMEOUT; i++) { 678 DELAY(10); 679 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 680 break; 681 } 682 if (i == RL_TIMEOUT) 683 device_printf(sc->rl_dev, "reset never completed!\n"); 684 685 CSR_WRITE_1(sc, 0x82, 1); 686 } 687 688 #ifdef RE_DIAG 689 690 /* 691 * The following routine is designed to test for a defect on some 692 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 693 * lines connected to the bus, however for a 32-bit only card, they 694 * should be pulled high. The result of this defect is that the 695 * NIC will not work right if you plug it into a 64-bit slot: DMA 696 * operations will be done with 64-bit transfers, which will fail 697 * because the 64-bit data lines aren't connected. 698 * 699 * There's no way to work around this (short of talking a soldering 700 * iron to the board), however we can detect it. The method we use 701 * here is to put the NIC into digital loopback mode, set the receiver 702 * to promiscuous mode, and then try to send a frame. We then compare 703 * the frame data we sent to what was received. If the data matches, 704 * then the NIC is working correctly, otherwise we know the user has 705 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 706 * slot. In the latter case, there's no way the NIC can work correctly, 707 * so we print out a message on the console and abort the device attach. 708 */ 709 710 static int 711 re_diag(sc) 712 struct rl_softc *sc; 713 { 714 struct ifnet *ifp = sc->rl_ifp; 715 struct mbuf *m0; 716 struct ether_header *eh; 717 struct rl_desc *cur_rx; 718 u_int16_t status; 719 u_int32_t rxstat; 720 int total_len, i, error = 0, phyaddr; 721 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 722 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 723 724 /* Allocate a single mbuf */ 725 MGETHDR(m0, M_DONTWAIT, MT_DATA); 726 if (m0 == NULL) 727 return (ENOBUFS); 728 729 RL_LOCK(sc); 730 731 /* 732 * Initialize the NIC in test mode. This sets the chip up 733 * so that it can send and receive frames, but performs the 734 * following special functions: 735 * - Puts receiver in promiscuous mode 736 * - Enables digital loopback mode 737 * - Leaves interrupts turned off 738 */ 739 740 ifp->if_flags |= IFF_PROMISC; 741 sc->rl_testmode = 1; 742 re_reset(sc); 743 re_init_locked(sc); 744 sc->rl_link = 1; 745 if (sc->rl_type == RL_8169) 746 phyaddr = 1; 747 else 748 phyaddr = 0; 749 750 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 751 for (i = 0; i < RL_TIMEOUT; i++) { 752 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 753 if (!(status & BMCR_RESET)) 754 break; 755 } 756 757 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 758 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 759 760 DELAY(100000); 761 762 /* Put some data in the mbuf */ 763 764 eh = mtod(m0, struct ether_header *); 765 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 766 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 767 eh->ether_type = htons(ETHERTYPE_IP); 768 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 769 770 /* 771 * Queue the packet, start transmission. 772 * Note: IF_HANDOFF() ultimately calls re_start() for us. 773 */ 774 775 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 776 RL_UNLOCK(sc); 777 /* XXX: re_diag must not be called when in ALTQ mode */ 778 IF_HANDOFF(&ifp->if_snd, m0, ifp); 779 RL_LOCK(sc); 780 m0 = NULL; 781 782 /* Wait for it to propagate through the chip */ 783 784 DELAY(100000); 785 for (i = 0; i < RL_TIMEOUT; i++) { 786 status = CSR_READ_2(sc, RL_ISR); 787 CSR_WRITE_2(sc, RL_ISR, status); 788 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 789 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 790 break; 791 DELAY(10); 792 } 793 794 if (i == RL_TIMEOUT) { 795 device_printf(sc->rl_dev, 796 "diagnostic failed, failed to receive packet in" 797 " loopback mode\n"); 798 error = EIO; 799 goto done; 800 } 801 802 /* 803 * The packet should have been dumped into the first 804 * entry in the RX DMA ring. Grab it from there. 805 */ 806 807 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 808 sc->rl_ldata.rl_rx_list_map, 809 BUS_DMASYNC_POSTREAD); 810 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 811 sc->rl_ldata.rl_rx_dmamap[0], 812 BUS_DMASYNC_POSTWRITE); 813 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 814 sc->rl_ldata.rl_rx_dmamap[0]); 815 816 m0 = sc->rl_ldata.rl_rx_mbuf[0]; 817 sc->rl_ldata.rl_rx_mbuf[0] = NULL; 818 eh = mtod(m0, struct ether_header *); 819 820 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 821 total_len = RL_RXBYTES(cur_rx); 822 rxstat = le32toh(cur_rx->rl_cmdstat); 823 824 if (total_len != ETHER_MIN_LEN) { 825 device_printf(sc->rl_dev, 826 "diagnostic failed, received short packet\n"); 827 error = EIO; 828 goto done; 829 } 830 831 /* Test that the received packet data matches what we sent. */ 832 833 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 834 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 835 ntohs(eh->ether_type) != ETHERTYPE_IP) { 836 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 837 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 838 dst, ":", src, ":", ETHERTYPE_IP); 839 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 840 eh->ether_dhost, ":", eh->ether_shost, ":", 841 ntohs(eh->ether_type)); 842 device_printf(sc->rl_dev, "You may have a defective 32-bit " 843 "NIC plugged into a 64-bit PCI slot.\n"); 844 device_printf(sc->rl_dev, "Please re-install the NIC in a " 845 "32-bit slot for proper operation.\n"); 846 device_printf(sc->rl_dev, "Read the re(4) man page for more " 847 "details.\n"); 848 error = EIO; 849 } 850 851 done: 852 /* Turn interface off, release resources */ 853 854 sc->rl_testmode = 0; 855 sc->rl_link = 0; 856 ifp->if_flags &= ~IFF_PROMISC; 857 re_stop(sc); 858 if (m0 != NULL) 859 m_freem(m0); 860 861 RL_UNLOCK(sc); 862 863 return (error); 864 } 865 866 #endif 867 868 /* 869 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 870 * IDs against our list and return a device name if we find a match. 871 */ 872 static int 873 re_probe(dev) 874 device_t dev; 875 { 876 struct rl_type *t; 877 struct rl_softc *sc; 878 int rid; 879 u_int32_t hwrev; 880 881 t = re_devs; 882 sc = device_get_softc(dev); 883 884 while (t->rl_name != NULL) { 885 if ((pci_get_vendor(dev) == t->rl_vid) && 886 (pci_get_device(dev) == t->rl_did)) { 887 /* 888 * Only attach to rev. 3 of the Linksys EG1032 adapter. 889 * Rev. 2 i supported by sk(4). 890 */ 891 if ((t->rl_vid == LINKSYS_VENDORID) && 892 (t->rl_did == LINKSYS_DEVICEID_EG1032) && 893 (pci_get_subdevice(dev) != 894 LINKSYS_SUBDEVICE_EG1032_REV3)) { 895 t++; 896 continue; 897 } 898 899 /* 900 * Temporarily map the I/O space 901 * so we can read the chip ID register. 902 */ 903 rid = RL_RID; 904 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 905 RF_ACTIVE); 906 if (sc->rl_res == NULL) { 907 device_printf(dev, 908 "couldn't map ports/memory\n"); 909 return (ENXIO); 910 } 911 sc->rl_btag = rman_get_bustag(sc->rl_res); 912 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 913 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 914 bus_release_resource(dev, RL_RES, 915 RL_RID, sc->rl_res); 916 if (t->rl_basetype == hwrev) { 917 device_set_desc(dev, t->rl_name); 918 return (BUS_PROBE_DEFAULT); 919 } 920 } 921 t++; 922 } 923 924 return (ENXIO); 925 } 926 927 /* 928 * This routine takes the segment list provided as the result of 929 * a bus_dma_map_load() operation and assigns the addresses/lengths 930 * to RealTek DMA descriptors. This can be called either by the RX 931 * code or the TX code. In the RX case, we'll probably wind up mapping 932 * at most one segment. For the TX case, there could be any number of 933 * segments since TX packets may span multiple mbufs. In either case, 934 * if the number of segments is larger than the rl_maxsegs limit 935 * specified by the caller, we abort the mapping operation. Sadly, 936 * whoever designed the buffer mapping API did not provide a way to 937 * return an error from here, so we have to fake it a bit. 938 */ 939 940 static void 941 re_dma_map_desc(arg, segs, nseg, mapsize, error) 942 void *arg; 943 bus_dma_segment_t *segs; 944 int nseg; 945 bus_size_t mapsize; 946 int error; 947 { 948 struct rl_dmaload_arg *ctx; 949 struct rl_desc *d = NULL; 950 int i = 0, idx; 951 u_int32_t cmdstat; 952 int totlen = 0; 953 954 if (error) 955 return; 956 957 ctx = arg; 958 959 /* Signal error to caller if there's too many segments */ 960 if (nseg > ctx->rl_maxsegs) { 961 ctx->rl_maxsegs = 0; 962 return; 963 } 964 965 /* 966 * Map the segment array into descriptors. Note that we set the 967 * start-of-frame and end-of-frame markers for either TX or RX, but 968 * they really only have meaning in the TX case. (In the RX case, 969 * it's the chip that tells us where packets begin and end.) 970 * We also keep track of the end of the ring and set the 971 * end-of-ring bits as needed, and we set the ownership bits 972 * in all except the very first descriptor. (The caller will 973 * set this descriptor later when it start transmission or 974 * reception.) 975 */ 976 idx = ctx->rl_idx; 977 for (;;) { 978 d = &ctx->rl_ring[idx]; 979 if (le32toh(d->rl_cmdstat) & RL_RDESC_STAT_OWN) { 980 ctx->rl_maxsegs = 0; 981 return; 982 } 983 cmdstat = segs[i].ds_len; 984 totlen += segs[i].ds_len; 985 d->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 986 d->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 987 if (i == 0) 988 cmdstat |= RL_TDESC_CMD_SOF; 989 else 990 cmdstat |= RL_TDESC_CMD_OWN; 991 if (idx == (RL_RX_DESC_CNT - 1)) 992 cmdstat |= RL_TDESC_CMD_EOR; 993 d->rl_cmdstat = htole32(cmdstat | ctx->rl_flags); 994 i++; 995 if (i == nseg) 996 break; 997 RL_DESC_INC(idx); 998 } 999 1000 d->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 1001 ctx->rl_maxsegs = nseg; 1002 ctx->rl_idx = idx; 1003 } 1004 1005 /* 1006 * Map a single buffer address. 1007 */ 1008 1009 static void 1010 re_dma_map_addr(arg, segs, nseg, error) 1011 void *arg; 1012 bus_dma_segment_t *segs; 1013 int nseg; 1014 int error; 1015 { 1016 bus_addr_t *addr; 1017 1018 if (error) 1019 return; 1020 1021 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 1022 addr = arg; 1023 *addr = segs->ds_addr; 1024 } 1025 1026 static int 1027 re_allocmem(dev, sc) 1028 device_t dev; 1029 struct rl_softc *sc; 1030 { 1031 int error; 1032 int nseg; 1033 int i; 1034 1035 /* 1036 * Allocate map for RX mbufs. 1037 */ 1038 nseg = 32; 1039 error = bus_dma_tag_create(sc->rl_parent_tag, ETHER_ALIGN, 0, 1040 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1041 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 1042 NULL, NULL, &sc->rl_ldata.rl_mtag); 1043 if (error) { 1044 device_printf(dev, "could not allocate dma tag\n"); 1045 return (ENOMEM); 1046 } 1047 1048 /* 1049 * Allocate map for TX descriptor list. 1050 */ 1051 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1052 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1053 NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 1054 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1055 if (error) { 1056 device_printf(dev, "could not allocate dma tag\n"); 1057 return (ENOMEM); 1058 } 1059 1060 /* Allocate DMA'able memory for the TX ring */ 1061 1062 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1063 (void **)&sc->rl_ldata.rl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1064 &sc->rl_ldata.rl_tx_list_map); 1065 if (error) 1066 return (ENOMEM); 1067 1068 /* Load the map for the TX ring. */ 1069 1070 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1071 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1072 RL_TX_LIST_SZ, re_dma_map_addr, 1073 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1074 1075 /* Create DMA maps for TX buffers */ 1076 1077 for (i = 0; i < RL_TX_DESC_CNT; i++) { 1078 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1079 &sc->rl_ldata.rl_tx_dmamap[i]); 1080 if (error) { 1081 device_printf(dev, "can't create DMA map for TX\n"); 1082 return (ENOMEM); 1083 } 1084 } 1085 1086 /* 1087 * Allocate map for RX descriptor list. 1088 */ 1089 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1090 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1091 NULL, RL_RX_LIST_SZ, 1, RL_RX_LIST_SZ, BUS_DMA_ALLOCNOW, 1092 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1093 if (error) { 1094 device_printf(dev, "could not allocate dma tag\n"); 1095 return (ENOMEM); 1096 } 1097 1098 /* Allocate DMA'able memory for the RX ring */ 1099 1100 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1101 (void **)&sc->rl_ldata.rl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1102 &sc->rl_ldata.rl_rx_list_map); 1103 if (error) 1104 return (ENOMEM); 1105 1106 /* Load the map for the RX ring. */ 1107 1108 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1109 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1110 RL_RX_LIST_SZ, re_dma_map_addr, 1111 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1112 1113 /* Create DMA maps for RX buffers */ 1114 1115 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1116 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1117 &sc->rl_ldata.rl_rx_dmamap[i]); 1118 if (error) { 1119 device_printf(dev, "can't create DMA map for RX\n"); 1120 return (ENOMEM); 1121 } 1122 } 1123 1124 return (0); 1125 } 1126 1127 /* 1128 * Attach the interface. Allocate softc structures, do ifmedia 1129 * setup and ethernet/BPF attach. 1130 */ 1131 static int 1132 re_attach(dev) 1133 device_t dev; 1134 { 1135 u_char eaddr[ETHER_ADDR_LEN]; 1136 u_int16_t as[ETHER_ADDR_LEN / 2]; 1137 struct rl_softc *sc; 1138 struct ifnet *ifp; 1139 struct rl_hwrev *hw_rev; 1140 int hwrev; 1141 u_int16_t re_did = 0; 1142 int error = 0, rid, i; 1143 1144 sc = device_get_softc(dev); 1145 sc->rl_dev = dev; 1146 1147 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1148 MTX_DEF); 1149 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1150 1151 /* 1152 * Map control/status registers. 1153 */ 1154 pci_enable_busmaster(dev); 1155 1156 rid = RL_RID; 1157 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 1158 RF_ACTIVE); 1159 1160 if (sc->rl_res == NULL) { 1161 device_printf(dev, "couldn't map ports/memory\n"); 1162 error = ENXIO; 1163 goto fail; 1164 } 1165 1166 sc->rl_btag = rman_get_bustag(sc->rl_res); 1167 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1168 1169 /* Allocate interrupt */ 1170 rid = 0; 1171 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1172 RF_SHAREABLE | RF_ACTIVE); 1173 1174 if (sc->rl_irq == NULL) { 1175 device_printf(dev, "couldn't map interrupt\n"); 1176 error = ENXIO; 1177 goto fail; 1178 } 1179 1180 /* Reset the adapter. */ 1181 RL_LOCK(sc); 1182 re_reset(sc); 1183 RL_UNLOCK(sc); 1184 1185 hw_rev = re_hwrevs; 1186 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 1187 while (hw_rev->rl_desc != NULL) { 1188 if (hw_rev->rl_rev == hwrev) { 1189 sc->rl_type = hw_rev->rl_type; 1190 break; 1191 } 1192 hw_rev++; 1193 } 1194 1195 sc->rl_eewidth = 6; 1196 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1197 if (re_did != 0x8129) 1198 sc->rl_eewidth = 8; 1199 1200 /* 1201 * Get station address from the EEPROM. 1202 */ 1203 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1204 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1205 as[i] = le16toh(as[i]); 1206 bcopy(as, eaddr, sizeof(eaddr)); 1207 1208 if (sc->rl_type == RL_8169) { 1209 /* Set RX length mask */ 1210 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1211 sc->rl_txstart = RL_GTXSTART; 1212 } else { 1213 /* Set RX length mask */ 1214 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1215 sc->rl_txstart = RL_TXSTART; 1216 } 1217 1218 /* 1219 * Allocate the parent bus DMA tag appropriate for PCI. 1220 */ 1221 #define RL_NSEG_NEW 32 1222 error = bus_dma_tag_create(NULL, /* parent */ 1223 1, 0, /* alignment, boundary */ 1224 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1225 BUS_SPACE_MAXADDR, /* highaddr */ 1226 NULL, NULL, /* filter, filterarg */ 1227 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 1228 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1229 BUS_DMA_ALLOCNOW, /* flags */ 1230 NULL, NULL, /* lockfunc, lockarg */ 1231 &sc->rl_parent_tag); 1232 if (error) 1233 goto fail; 1234 1235 error = re_allocmem(dev, sc); 1236 1237 if (error) 1238 goto fail; 1239 1240 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1241 if (ifp == NULL) { 1242 device_printf(dev, "can not if_alloc()\n"); 1243 error = ENOSPC; 1244 goto fail; 1245 } 1246 1247 /* Do MII setup */ 1248 if (mii_phy_probe(dev, &sc->rl_miibus, 1249 re_ifmedia_upd, re_ifmedia_sts)) { 1250 device_printf(dev, "MII without any phy!\n"); 1251 error = ENXIO; 1252 goto fail; 1253 } 1254 1255 ifp->if_softc = sc; 1256 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1257 ifp->if_mtu = ETHERMTU; 1258 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1259 ifp->if_ioctl = re_ioctl; 1260 ifp->if_capabilities = IFCAP_VLAN_MTU; 1261 ifp->if_start = re_start; 1262 ifp->if_hwassist = RE_CSUM_FEATURES; 1263 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1264 ifp->if_capenable = ifp->if_capabilities; 1265 #ifdef DEVICE_POLLING 1266 ifp->if_capabilities |= IFCAP_POLLING; 1267 #endif 1268 ifp->if_watchdog = re_watchdog; 1269 ifp->if_init = re_init; 1270 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1271 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1272 IFQ_SET_READY(&ifp->if_snd); 1273 1274 TASK_INIT(&sc->rl_txtask, 1, re_tx_task, ifp); 1275 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1276 1277 /* 1278 * Call MI attach routine. 1279 */ 1280 ether_ifattach(ifp, eaddr); 1281 1282 #ifdef RE_DIAG 1283 /* 1284 * Perform hardware diagnostic on the original RTL8169. 1285 * Some 32-bit cards were incorrectly wired and would 1286 * malfunction if plugged into a 64-bit slot. 1287 */ 1288 1289 if (hwrev == RL_HWREV_8169) { 1290 error = re_diag(sc); 1291 if (error) { 1292 device_printf(dev, 1293 "attach aborted due to hardware diag failure\n"); 1294 ether_ifdetach(ifp); 1295 goto fail; 1296 } 1297 } 1298 #endif 1299 1300 /* Hook interrupt last to avoid having to lock softc */ 1301 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET | INTR_MPSAFE | 1302 INTR_FAST, re_intr, sc, &sc->rl_intrhand); 1303 if (error) { 1304 device_printf(dev, "couldn't set up irq\n"); 1305 ether_ifdetach(ifp); 1306 } 1307 1308 fail: 1309 1310 if (error) 1311 re_detach(dev); 1312 1313 return (error); 1314 } 1315 1316 /* 1317 * Shutdown hardware and free up resources. This can be called any 1318 * time after the mutex has been initialized. It is called in both 1319 * the error case in attach and the normal detach case so it needs 1320 * to be careful about only freeing resources that have actually been 1321 * allocated. 1322 */ 1323 static int 1324 re_detach(dev) 1325 device_t dev; 1326 { 1327 struct rl_softc *sc; 1328 struct ifnet *ifp; 1329 int i; 1330 1331 sc = device_get_softc(dev); 1332 ifp = sc->rl_ifp; 1333 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1334 1335 #ifdef DEVICE_POLLING 1336 if (ifp->if_capenable & IFCAP_POLLING) 1337 ether_poll_deregister(ifp); 1338 #endif 1339 /* These should only be active if attach succeeded */ 1340 if (device_is_attached(dev)) { 1341 RL_LOCK(sc); 1342 #if 0 1343 sc->suspended = 1; 1344 #endif 1345 re_stop(sc); 1346 RL_UNLOCK(sc); 1347 callout_drain(&sc->rl_stat_callout); 1348 /* 1349 * Force off the IFF_UP flag here, in case someone 1350 * still had a BPF descriptor attached to this 1351 * interface. If they do, ether_ifdetach() will cause 1352 * the BPF code to try and clear the promisc mode 1353 * flag, which will bubble down to re_ioctl(), 1354 * which will try to call re_init() again. This will 1355 * turn the NIC back on and restart the MII ticker, 1356 * which will panic the system when the kernel tries 1357 * to invoke the re_tick() function that isn't there 1358 * anymore. 1359 */ 1360 ifp->if_flags &= ~IFF_UP; 1361 ether_ifdetach(ifp); 1362 } 1363 if (sc->rl_miibus) 1364 device_delete_child(dev, sc->rl_miibus); 1365 bus_generic_detach(dev); 1366 1367 /* 1368 * The rest is resource deallocation, so we should already be 1369 * stopped here. 1370 */ 1371 1372 if (sc->rl_intrhand) 1373 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1374 if (ifp != NULL) 1375 if_free(ifp); 1376 if (sc->rl_irq) 1377 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1378 if (sc->rl_res) 1379 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1380 1381 /* Yield the CPU long enough for any tasks to drain */ 1382 1383 tsleep(sc, PPAUSE, "rewait", hz); 1384 1385 /* Unload and free the RX DMA ring memory and map */ 1386 1387 if (sc->rl_ldata.rl_rx_list_tag) { 1388 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1389 sc->rl_ldata.rl_rx_list_map); 1390 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1391 sc->rl_ldata.rl_rx_list, 1392 sc->rl_ldata.rl_rx_list_map); 1393 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1394 } 1395 1396 /* Unload and free the TX DMA ring memory and map */ 1397 1398 if (sc->rl_ldata.rl_tx_list_tag) { 1399 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1400 sc->rl_ldata.rl_tx_list_map); 1401 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1402 sc->rl_ldata.rl_tx_list, 1403 sc->rl_ldata.rl_tx_list_map); 1404 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1405 } 1406 1407 /* Destroy all the RX and TX buffer maps */ 1408 1409 if (sc->rl_ldata.rl_mtag) { 1410 for (i = 0; i < RL_TX_DESC_CNT; i++) 1411 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1412 sc->rl_ldata.rl_tx_dmamap[i]); 1413 for (i = 0; i < RL_RX_DESC_CNT; i++) 1414 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1415 sc->rl_ldata.rl_rx_dmamap[i]); 1416 bus_dma_tag_destroy(sc->rl_ldata.rl_mtag); 1417 } 1418 1419 /* Unload and free the stats buffer and map */ 1420 1421 if (sc->rl_ldata.rl_stag) { 1422 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1423 sc->rl_ldata.rl_rx_list_map); 1424 bus_dmamem_free(sc->rl_ldata.rl_stag, 1425 sc->rl_ldata.rl_stats, 1426 sc->rl_ldata.rl_smap); 1427 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1428 } 1429 1430 if (sc->rl_parent_tag) 1431 bus_dma_tag_destroy(sc->rl_parent_tag); 1432 1433 mtx_destroy(&sc->rl_mtx); 1434 1435 return (0); 1436 } 1437 1438 static int 1439 re_newbuf(sc, idx, m) 1440 struct rl_softc *sc; 1441 int idx; 1442 struct mbuf *m; 1443 { 1444 struct rl_dmaload_arg arg; 1445 struct mbuf *n = NULL; 1446 int error; 1447 1448 if (m == NULL) { 1449 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1450 if (n == NULL) 1451 return (ENOBUFS); 1452 m = n; 1453 } else 1454 m->m_data = m->m_ext.ext_buf; 1455 1456 m->m_len = m->m_pkthdr.len = MCLBYTES; 1457 #ifdef RE_FIXUP_RX 1458 /* 1459 * This is part of an evil trick to deal with non-x86 platforms. 1460 * The RealTek chip requires RX buffers to be aligned on 64-bit 1461 * boundaries, but that will hose non-x86 machines. To get around 1462 * this, we leave some empty space at the start of each buffer 1463 * and for non-x86 hosts, we copy the buffer back six bytes 1464 * to achieve word alignment. This is slightly more efficient 1465 * than allocating a new buffer, copying the contents, and 1466 * discarding the old buffer. 1467 */ 1468 m_adj(m, RE_ETHER_ALIGN); 1469 #endif 1470 arg.sc = sc; 1471 arg.rl_idx = idx; 1472 arg.rl_maxsegs = 1; 1473 arg.rl_flags = 0; 1474 arg.rl_ring = sc->rl_ldata.rl_rx_list; 1475 1476 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, 1477 sc->rl_ldata.rl_rx_dmamap[idx], m, re_dma_map_desc, 1478 &arg, BUS_DMA_NOWAIT); 1479 if (error || arg.rl_maxsegs != 1) { 1480 if (n != NULL) 1481 m_freem(n); 1482 return (ENOMEM); 1483 } 1484 1485 sc->rl_ldata.rl_rx_list[idx].rl_cmdstat |= htole32(RL_RDESC_CMD_OWN); 1486 sc->rl_ldata.rl_rx_mbuf[idx] = m; 1487 1488 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1489 sc->rl_ldata.rl_rx_dmamap[idx], 1490 BUS_DMASYNC_PREREAD); 1491 1492 return (0); 1493 } 1494 1495 #ifdef RE_FIXUP_RX 1496 static __inline void 1497 re_fixup_rx(m) 1498 struct mbuf *m; 1499 { 1500 int i; 1501 uint16_t *src, *dst; 1502 1503 src = mtod(m, uint16_t *); 1504 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1505 1506 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1507 *dst++ = *src++; 1508 1509 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1510 1511 return; 1512 } 1513 #endif 1514 1515 static int 1516 re_tx_list_init(sc) 1517 struct rl_softc *sc; 1518 { 1519 1520 RL_LOCK_ASSERT(sc); 1521 1522 bzero ((char *)sc->rl_ldata.rl_tx_list, RL_TX_LIST_SZ); 1523 bzero ((char *)&sc->rl_ldata.rl_tx_mbuf, 1524 (RL_TX_DESC_CNT * sizeof(struct mbuf *))); 1525 1526 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1527 sc->rl_ldata.rl_tx_list_map, BUS_DMASYNC_PREWRITE); 1528 sc->rl_ldata.rl_tx_prodidx = 0; 1529 sc->rl_ldata.rl_tx_considx = 0; 1530 sc->rl_ldata.rl_tx_free = RL_TX_DESC_CNT; 1531 1532 return (0); 1533 } 1534 1535 static int 1536 re_rx_list_init(sc) 1537 struct rl_softc *sc; 1538 { 1539 int i; 1540 1541 bzero ((char *)sc->rl_ldata.rl_rx_list, RL_RX_LIST_SZ); 1542 bzero ((char *)&sc->rl_ldata.rl_rx_mbuf, 1543 (RL_RX_DESC_CNT * sizeof(struct mbuf *))); 1544 1545 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1546 if (re_newbuf(sc, i, NULL) == ENOBUFS) 1547 return (ENOBUFS); 1548 } 1549 1550 /* Flush the RX descriptors */ 1551 1552 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1553 sc->rl_ldata.rl_rx_list_map, 1554 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1555 1556 sc->rl_ldata.rl_rx_prodidx = 0; 1557 sc->rl_head = sc->rl_tail = NULL; 1558 1559 return (0); 1560 } 1561 1562 /* 1563 * RX handler for C+ and 8169. For the gigE chips, we support 1564 * the reception of jumbo frames that have been fragmented 1565 * across multiple 2K mbuf cluster buffers. 1566 */ 1567 static int 1568 re_rxeof(sc) 1569 struct rl_softc *sc; 1570 { 1571 struct mbuf *m; 1572 struct ifnet *ifp; 1573 int i, total_len; 1574 struct rl_desc *cur_rx; 1575 u_int32_t rxstat, rxvlan; 1576 int maxpkt = 16; 1577 1578 RL_LOCK_ASSERT(sc); 1579 1580 ifp = sc->rl_ifp; 1581 i = sc->rl_ldata.rl_rx_prodidx; 1582 1583 /* Invalidate the descriptor memory */ 1584 1585 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1586 sc->rl_ldata.rl_rx_list_map, 1587 BUS_DMASYNC_POSTREAD); 1588 1589 while (!RL_OWN(&sc->rl_ldata.rl_rx_list[i]) && maxpkt) { 1590 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1591 m = sc->rl_ldata.rl_rx_mbuf[i]; 1592 total_len = RL_RXBYTES(cur_rx); 1593 rxstat = le32toh(cur_rx->rl_cmdstat); 1594 rxvlan = le32toh(cur_rx->rl_vlanctl); 1595 1596 /* Invalidate the RX mbuf and unload its map */ 1597 1598 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1599 sc->rl_ldata.rl_rx_dmamap[i], 1600 BUS_DMASYNC_POSTWRITE); 1601 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1602 sc->rl_ldata.rl_rx_dmamap[i]); 1603 1604 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1605 m->m_len = RE_RX_DESC_BUFLEN; 1606 if (sc->rl_head == NULL) 1607 sc->rl_head = sc->rl_tail = m; 1608 else { 1609 m->m_flags &= ~M_PKTHDR; 1610 sc->rl_tail->m_next = m; 1611 sc->rl_tail = m; 1612 } 1613 re_newbuf(sc, i, NULL); 1614 RL_DESC_INC(i); 1615 continue; 1616 } 1617 1618 /* 1619 * NOTE: for the 8139C+, the frame length field 1620 * is always 12 bits in size, but for the gigE chips, 1621 * it is 13 bits (since the max RX frame length is 16K). 1622 * Unfortunately, all 32 bits in the status word 1623 * were already used, so to make room for the extra 1624 * length bit, RealTek took out the 'frame alignment 1625 * error' bit and shifted the other status bits 1626 * over one slot. The OWN, EOR, FS and LS bits are 1627 * still in the same places. We have already extracted 1628 * the frame length and checked the OWN bit, so rather 1629 * than using an alternate bit mapping, we shift the 1630 * status bits one space to the right so we can evaluate 1631 * them using the 8169 status as though it was in the 1632 * same format as that of the 8139C+. 1633 */ 1634 if (sc->rl_type == RL_8169) 1635 rxstat >>= 1; 1636 1637 /* 1638 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 1639 * set, but if CRC is clear, it will still be a valid frame. 1640 */ 1641 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 && 1642 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) { 1643 ifp->if_ierrors++; 1644 /* 1645 * If this is part of a multi-fragment packet, 1646 * discard all the pieces. 1647 */ 1648 if (sc->rl_head != NULL) { 1649 m_freem(sc->rl_head); 1650 sc->rl_head = sc->rl_tail = NULL; 1651 } 1652 re_newbuf(sc, i, m); 1653 RL_DESC_INC(i); 1654 continue; 1655 } 1656 1657 /* 1658 * If allocating a replacement mbuf fails, 1659 * reload the current one. 1660 */ 1661 1662 if (re_newbuf(sc, i, NULL)) { 1663 ifp->if_ierrors++; 1664 if (sc->rl_head != NULL) { 1665 m_freem(sc->rl_head); 1666 sc->rl_head = sc->rl_tail = NULL; 1667 } 1668 re_newbuf(sc, i, m); 1669 RL_DESC_INC(i); 1670 continue; 1671 } 1672 1673 RL_DESC_INC(i); 1674 1675 if (sc->rl_head != NULL) { 1676 m->m_len = total_len % RE_RX_DESC_BUFLEN; 1677 if (m->m_len == 0) 1678 m->m_len = RE_RX_DESC_BUFLEN; 1679 /* 1680 * Special case: if there's 4 bytes or less 1681 * in this buffer, the mbuf can be discarded: 1682 * the last 4 bytes is the CRC, which we don't 1683 * care about anyway. 1684 */ 1685 if (m->m_len <= ETHER_CRC_LEN) { 1686 sc->rl_tail->m_len -= 1687 (ETHER_CRC_LEN - m->m_len); 1688 m_freem(m); 1689 } else { 1690 m->m_len -= ETHER_CRC_LEN; 1691 m->m_flags &= ~M_PKTHDR; 1692 sc->rl_tail->m_next = m; 1693 } 1694 m = sc->rl_head; 1695 sc->rl_head = sc->rl_tail = NULL; 1696 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1697 } else 1698 m->m_pkthdr.len = m->m_len = 1699 (total_len - ETHER_CRC_LEN); 1700 1701 #ifdef RE_FIXUP_RX 1702 re_fixup_rx(m); 1703 #endif 1704 ifp->if_ipackets++; 1705 m->m_pkthdr.rcvif = ifp; 1706 1707 /* Do RX checksumming if enabled */ 1708 1709 if (ifp->if_capenable & IFCAP_RXCSUM) { 1710 1711 /* Check IP header checksum */ 1712 if (rxstat & RL_RDESC_STAT_PROTOID) 1713 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1714 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1715 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1716 1717 /* Check TCP/UDP checksum */ 1718 if ((RL_TCPPKT(rxstat) && 1719 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1720 (RL_UDPPKT(rxstat) && 1721 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1722 m->m_pkthdr.csum_flags |= 1723 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1724 m->m_pkthdr.csum_data = 0xffff; 1725 } 1726 } 1727 maxpkt--; 1728 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 1729 m->m_pkthdr.ether_vtag = 1730 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)); 1731 m->m_flags |= M_VLANTAG; 1732 } 1733 RL_UNLOCK(sc); 1734 (*ifp->if_input)(ifp, m); 1735 RL_LOCK(sc); 1736 } 1737 1738 /* Flush the RX DMA ring */ 1739 1740 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1741 sc->rl_ldata.rl_rx_list_map, 1742 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1743 1744 sc->rl_ldata.rl_rx_prodidx = i; 1745 1746 if (maxpkt) 1747 return(EAGAIN); 1748 1749 return(0); 1750 } 1751 1752 static void 1753 re_txeof(sc) 1754 struct rl_softc *sc; 1755 { 1756 struct ifnet *ifp; 1757 u_int32_t txstat; 1758 int idx; 1759 1760 ifp = sc->rl_ifp; 1761 idx = sc->rl_ldata.rl_tx_considx; 1762 1763 /* Invalidate the TX descriptor list */ 1764 1765 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1766 sc->rl_ldata.rl_tx_list_map, 1767 BUS_DMASYNC_POSTREAD); 1768 1769 while (sc->rl_ldata.rl_tx_free < RL_TX_DESC_CNT) { 1770 1771 txstat = le32toh(sc->rl_ldata.rl_tx_list[idx].rl_cmdstat); 1772 if (txstat & RL_TDESC_CMD_OWN) 1773 break; 1774 1775 sc->rl_ldata.rl_tx_list[idx].rl_bufaddr_lo = 0; 1776 1777 /* 1778 * We only stash mbufs in the last descriptor 1779 * in a fragment chain, which also happens to 1780 * be the only place where the TX status bits 1781 * are valid. 1782 */ 1783 1784 if (txstat & RL_TDESC_CMD_EOF) { 1785 m_freem(sc->rl_ldata.rl_tx_mbuf[idx]); 1786 sc->rl_ldata.rl_tx_mbuf[idx] = NULL; 1787 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1788 sc->rl_ldata.rl_tx_dmamap[idx]); 1789 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 1790 RL_TDESC_STAT_COLCNT)) 1791 ifp->if_collisions++; 1792 if (txstat & RL_TDESC_STAT_TXERRSUM) 1793 ifp->if_oerrors++; 1794 else 1795 ifp->if_opackets++; 1796 } 1797 sc->rl_ldata.rl_tx_free++; 1798 RL_DESC_INC(idx); 1799 } 1800 1801 /* No changes made to the TX ring, so no flush needed */ 1802 1803 if (sc->rl_ldata.rl_tx_free) { 1804 sc->rl_ldata.rl_tx_considx = idx; 1805 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1806 ifp->if_timer = 0; 1807 } 1808 1809 /* 1810 * Some chips will ignore a second TX request issued while an 1811 * existing transmission is in progress. If the transmitter goes 1812 * idle but there are still packets waiting to be sent, we need 1813 * to restart the channel here to flush them out. This only seems 1814 * to be required with the PCIe devices. 1815 */ 1816 1817 if (sc->rl_ldata.rl_tx_free < RL_TX_DESC_CNT) 1818 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 1819 1820 #ifdef RE_TX_MODERATION 1821 /* 1822 * If not all descriptors have been released reaped yet, 1823 * reload the timer so that we will eventually get another 1824 * interrupt that will cause us to re-enter this routine. 1825 * This is done in case the transmitter has gone idle. 1826 */ 1827 if (sc->rl_ldata.rl_tx_free != RL_TX_DESC_CNT) 1828 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 1829 #endif 1830 1831 } 1832 1833 static void 1834 re_tick(xsc) 1835 void *xsc; 1836 { 1837 struct rl_softc *sc; 1838 struct mii_data *mii; 1839 struct ifnet *ifp; 1840 1841 sc = xsc; 1842 ifp = sc->rl_ifp; 1843 1844 RL_LOCK_ASSERT(sc); 1845 1846 mii = device_get_softc(sc->rl_miibus); 1847 1848 mii_tick(mii); 1849 if (sc->rl_link) { 1850 if (!(mii->mii_media_status & IFM_ACTIVE)) 1851 sc->rl_link = 0; 1852 } else { 1853 if (mii->mii_media_status & IFM_ACTIVE && 1854 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1855 sc->rl_link = 1; 1856 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1857 taskqueue_enqueue_fast(taskqueue_fast, 1858 &sc->rl_txtask); 1859 } 1860 } 1861 1862 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 1863 } 1864 1865 #ifdef DEVICE_POLLING 1866 static void 1867 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1868 { 1869 struct rl_softc *sc = ifp->if_softc; 1870 1871 RL_LOCK(sc); 1872 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1873 re_poll_locked(ifp, cmd, count); 1874 RL_UNLOCK(sc); 1875 } 1876 1877 static void 1878 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1879 { 1880 struct rl_softc *sc = ifp->if_softc; 1881 1882 RL_LOCK_ASSERT(sc); 1883 1884 sc->rxcycles = count; 1885 re_rxeof(sc); 1886 re_txeof(sc); 1887 1888 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1889 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 1890 1891 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1892 u_int16_t status; 1893 1894 status = CSR_READ_2(sc, RL_ISR); 1895 if (status == 0xffff) 1896 return; 1897 if (status) 1898 CSR_WRITE_2(sc, RL_ISR, status); 1899 1900 /* 1901 * XXX check behaviour on receiver stalls. 1902 */ 1903 1904 if (status & RL_ISR_SYSTEM_ERR) { 1905 re_reset(sc); 1906 re_init_locked(sc); 1907 } 1908 } 1909 } 1910 #endif /* DEVICE_POLLING */ 1911 1912 static void 1913 re_intr(arg) 1914 void *arg; 1915 { 1916 struct rl_softc *sc; 1917 struct ifnet *ifp; 1918 uint16_t status; 1919 1920 sc = arg; 1921 ifp = sc->rl_ifp; 1922 1923 status = CSR_READ_2(sc, RL_ISR); 1924 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 1925 return; 1926 CSR_WRITE_2(sc, RL_IMR, 0); 1927 1928 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 1929 1930 return; 1931 } 1932 1933 static void 1934 re_int_task(arg, npending) 1935 void *arg; 1936 int npending; 1937 { 1938 struct rl_softc *sc; 1939 struct ifnet *ifp; 1940 u_int16_t status; 1941 int rval = 0; 1942 1943 sc = arg; 1944 ifp = sc->rl_ifp; 1945 1946 RL_LOCK(sc); 1947 1948 status = CSR_READ_2(sc, RL_ISR); 1949 CSR_WRITE_2(sc, RL_ISR, status); 1950 1951 if (sc->suspended || !(ifp->if_flags & IFF_UP)) { 1952 RL_UNLOCK(sc); 1953 return; 1954 } 1955 1956 #ifdef DEVICE_POLLING 1957 if (ifp->if_capenable & IFCAP_POLLING) { 1958 RL_UNLOCK(sc); 1959 return; 1960 } 1961 #endif 1962 1963 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 1964 rval = re_rxeof(sc); 1965 1966 #ifdef RE_TX_MODERATION 1967 if (status & (RL_ISR_TIMEOUT_EXPIRED| 1968 #else 1969 if (status & (RL_ISR_TX_OK| 1970 #endif 1971 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 1972 re_txeof(sc); 1973 1974 if (status & RL_ISR_SYSTEM_ERR) { 1975 re_reset(sc); 1976 re_init_locked(sc); 1977 } 1978 1979 if (status & RL_ISR_LINKCHG) { 1980 callout_stop(&sc->rl_stat_callout); 1981 re_tick(sc); 1982 } 1983 1984 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1985 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 1986 1987 RL_UNLOCK(sc); 1988 1989 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 1990 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 1991 return; 1992 } 1993 1994 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 1995 1996 return; 1997 } 1998 1999 static int 2000 re_encap(sc, m_head, idx) 2001 struct rl_softc *sc; 2002 struct mbuf **m_head; 2003 int *idx; 2004 { 2005 struct mbuf *m_new = NULL; 2006 struct rl_dmaload_arg arg; 2007 bus_dmamap_t map; 2008 int error; 2009 2010 RL_LOCK_ASSERT(sc); 2011 2012 if (sc->rl_ldata.rl_tx_free <= 4) 2013 return (EFBIG); 2014 2015 /* 2016 * Set up checksum offload. Note: checksum offload bits must 2017 * appear in all descriptors of a multi-descriptor transmit 2018 * attempt. This is according to testing done with an 8169 2019 * chip. This is a requirement. 2020 */ 2021 2022 arg.rl_flags = 0; 2023 2024 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) 2025 arg.rl_flags |= RL_TDESC_CMD_IPCSUM; 2026 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) 2027 arg.rl_flags |= RL_TDESC_CMD_TCPCSUM; 2028 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) 2029 arg.rl_flags |= RL_TDESC_CMD_UDPCSUM; 2030 2031 arg.sc = sc; 2032 arg.rl_idx = *idx; 2033 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 2034 if (arg.rl_maxsegs > 4) 2035 arg.rl_maxsegs -= 4; 2036 arg.rl_ring = sc->rl_ldata.rl_tx_list; 2037 2038 map = sc->rl_ldata.rl_tx_dmamap[*idx]; 2039 2040 /* 2041 * With some of the RealTek chips, using the checksum offload 2042 * support in conjunction with the autopadding feature results 2043 * in the transmission of corrupt frames. For example, if we 2044 * need to send a really small IP fragment that's less than 60 2045 * bytes in size, and IP header checksumming is enabled, the 2046 * resulting ethernet frame that appears on the wire will 2047 * have garbled payload. To work around this, if TX checksum 2048 * offload is enabled, we always manually pad short frames out 2049 * to the minimum ethernet frame size. We do this by pretending 2050 * the mbuf chain has too many fragments so the coalescing code 2051 * below can assemble the packet into a single buffer that's 2052 * padded out to the mininum frame size. 2053 */ 2054 2055 if (arg.rl_flags && (*m_head)->m_pkthdr.len < RL_MIN_FRAMELEN) 2056 error = EFBIG; 2057 else 2058 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 2059 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 2060 2061 if (error && error != EFBIG) { 2062 device_printf(sc->rl_dev, "can't map mbuf (error %d)\n", error); 2063 return (ENOBUFS); 2064 } 2065 2066 /* Too many segments to map, coalesce into a single mbuf */ 2067 2068 if (error || arg.rl_maxsegs == 0) { 2069 m_new = m_defrag(*m_head, M_DONTWAIT); 2070 if (m_new == NULL) 2071 return (ENOBUFS); 2072 else 2073 *m_head = m_new; 2074 2075 /* 2076 * Manually pad short frames, and zero the pad space 2077 * to avoid leaking data. 2078 */ 2079 2080 if (m_new->m_pkthdr.len < RL_MIN_FRAMELEN) { 2081 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, 2082 RL_MIN_FRAMELEN - m_new->m_pkthdr.len); 2083 m_new->m_pkthdr.len += RL_MIN_FRAMELEN - 2084 m_new->m_pkthdr.len; 2085 m_new->m_len = m_new->m_pkthdr.len; 2086 } 2087 2088 arg.sc = sc; 2089 arg.rl_idx = *idx; 2090 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 2091 arg.rl_ring = sc->rl_ldata.rl_tx_list; 2092 2093 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 2094 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 2095 if (error) { 2096 device_printf(sc->rl_dev, "can't map mbuf (error %d)\n", 2097 error); 2098 return (EFBIG); 2099 } 2100 } 2101 2102 /* 2103 * Insure that the map for this transmission 2104 * is placed at the array index of the last descriptor 2105 * in this chain. (Swap last and first dmamaps.) 2106 */ 2107 sc->rl_ldata.rl_tx_dmamap[*idx] = 2108 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx]; 2109 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx] = map; 2110 2111 sc->rl_ldata.rl_tx_mbuf[arg.rl_idx] = *m_head; 2112 sc->rl_ldata.rl_tx_free -= arg.rl_maxsegs; 2113 2114 /* 2115 * Set up hardware VLAN tagging. Note: vlan tag info must 2116 * appear in the first descriptor of a multi-descriptor 2117 * transmission attempt. 2118 */ 2119 if ((*m_head)->m_flags & M_VLANTAG) 2120 sc->rl_ldata.rl_tx_list[*idx].rl_vlanctl = 2121 htole32(htons((*m_head)->m_pkthdr.ether_vtag) | 2122 RL_TDESC_VLANCTL_TAG); 2123 2124 /* Transfer ownership of packet to the chip. */ 2125 2126 sc->rl_ldata.rl_tx_list[arg.rl_idx].rl_cmdstat |= 2127 htole32(RL_TDESC_CMD_OWN); 2128 if (*idx != arg.rl_idx) 2129 sc->rl_ldata.rl_tx_list[*idx].rl_cmdstat |= 2130 htole32(RL_TDESC_CMD_OWN); 2131 2132 RL_DESC_INC(arg.rl_idx); 2133 *idx = arg.rl_idx; 2134 2135 return (0); 2136 } 2137 2138 static void 2139 re_tx_task(arg, npending) 2140 void *arg; 2141 int npending; 2142 { 2143 struct ifnet *ifp; 2144 2145 ifp = arg; 2146 re_start(ifp); 2147 2148 return; 2149 } 2150 2151 /* 2152 * Main transmit routine for C+ and gigE NICs. 2153 */ 2154 static void 2155 re_start(ifp) 2156 struct ifnet *ifp; 2157 { 2158 struct rl_softc *sc; 2159 struct mbuf *m_head = NULL; 2160 int idx, queued = 0; 2161 2162 sc = ifp->if_softc; 2163 2164 RL_LOCK(sc); 2165 2166 if (!sc->rl_link || ifp->if_drv_flags & IFF_DRV_OACTIVE) { 2167 RL_UNLOCK(sc); 2168 return; 2169 } 2170 2171 idx = sc->rl_ldata.rl_tx_prodidx; 2172 2173 while (sc->rl_ldata.rl_tx_mbuf[idx] == NULL) { 2174 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2175 if (m_head == NULL) 2176 break; 2177 2178 if (re_encap(sc, &m_head, &idx)) { 2179 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2180 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2181 break; 2182 } 2183 2184 /* 2185 * If there's a BPF listener, bounce a copy of this frame 2186 * to him. 2187 */ 2188 BPF_MTAP(ifp, m_head); 2189 2190 queued++; 2191 } 2192 2193 if (queued == 0) { 2194 #ifdef RE_TX_MODERATION 2195 if (sc->rl_ldata.rl_tx_free != RL_TX_DESC_CNT) 2196 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2197 #endif 2198 RL_UNLOCK(sc); 2199 return; 2200 } 2201 2202 /* Flush the TX descriptors */ 2203 2204 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2205 sc->rl_ldata.rl_tx_list_map, 2206 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2207 2208 sc->rl_ldata.rl_tx_prodidx = idx; 2209 2210 /* 2211 * RealTek put the TX poll request register in a different 2212 * location on the 8169 gigE chip. I don't know why. 2213 */ 2214 2215 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2216 2217 #ifdef RE_TX_MODERATION 2218 /* 2219 * Use the countdown timer for interrupt moderation. 2220 * 'TX done' interrupts are disabled. Instead, we reset the 2221 * countdown timer, which will begin counting until it hits 2222 * the value in the TIMERINT register, and then trigger an 2223 * interrupt. Each time we write to the TIMERCNT register, 2224 * the timer count is reset to 0. 2225 */ 2226 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2227 #endif 2228 2229 /* 2230 * Set a timeout in case the chip goes out to lunch. 2231 */ 2232 2233 ifp->if_timer = 5; 2234 2235 RL_UNLOCK(sc); 2236 2237 return; 2238 } 2239 2240 static void 2241 re_init(xsc) 2242 void *xsc; 2243 { 2244 struct rl_softc *sc = xsc; 2245 2246 RL_LOCK(sc); 2247 re_init_locked(sc); 2248 RL_UNLOCK(sc); 2249 } 2250 2251 static void 2252 re_init_locked(sc) 2253 struct rl_softc *sc; 2254 { 2255 struct ifnet *ifp = sc->rl_ifp; 2256 struct mii_data *mii; 2257 u_int32_t rxcfg = 0; 2258 union { 2259 uint32_t align_dummy; 2260 u_char eaddr[ETHER_ADDR_LEN]; 2261 } eaddr; 2262 2263 RL_LOCK_ASSERT(sc); 2264 2265 mii = device_get_softc(sc->rl_miibus); 2266 2267 /* 2268 * Cancel pending I/O and free all RX/TX buffers. 2269 */ 2270 re_stop(sc); 2271 2272 /* 2273 * Enable C+ RX and TX mode, as well as VLAN stripping and 2274 * RX checksum offload. We must configure the C+ register 2275 * before all others. 2276 */ 2277 CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB| 2278 RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW| 2279 RL_CPLUSCMD_VLANSTRIP|RL_CPLUSCMD_RXCSUM_ENB); 2280 2281 /* 2282 * Init our MAC address. Even though the chipset 2283 * documentation doesn't mention it, we need to enter "Config 2284 * register write enable" mode to modify the ID registers. 2285 */ 2286 /* Copy MAC address on stack to align. */ 2287 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 2288 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2289 CSR_WRITE_4(sc, RL_IDR0, 2290 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 2291 CSR_WRITE_4(sc, RL_IDR4, 2292 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 2293 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2294 2295 /* 2296 * For C+ mode, initialize the RX descriptors and mbufs. 2297 */ 2298 re_rx_list_init(sc); 2299 re_tx_list_init(sc); 2300 2301 /* 2302 * Enable transmit and receive. 2303 */ 2304 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2305 2306 /* 2307 * Set the initial TX and RX configuration. 2308 */ 2309 if (sc->rl_testmode) { 2310 if (sc->rl_type == RL_8169) 2311 CSR_WRITE_4(sc, RL_TXCFG, 2312 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2313 else 2314 CSR_WRITE_4(sc, RL_TXCFG, 2315 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2316 } else 2317 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2318 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 2319 2320 /* Set the individual bit to receive frames for this host only. */ 2321 rxcfg = CSR_READ_4(sc, RL_RXCFG); 2322 rxcfg |= RL_RXCFG_RX_INDIV; 2323 2324 /* If we want promiscuous mode, set the allframes bit. */ 2325 if (ifp->if_flags & IFF_PROMISC) 2326 rxcfg |= RL_RXCFG_RX_ALLPHYS; 2327 else 2328 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 2329 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2330 2331 /* 2332 * Set capture broadcast bit to capture broadcast frames. 2333 */ 2334 if (ifp->if_flags & IFF_BROADCAST) 2335 rxcfg |= RL_RXCFG_RX_BROAD; 2336 else 2337 rxcfg &= ~RL_RXCFG_RX_BROAD; 2338 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2339 2340 /* 2341 * Program the multicast filter, if necessary. 2342 */ 2343 re_setmulti(sc); 2344 2345 #ifdef DEVICE_POLLING 2346 /* 2347 * Disable interrupts if we are polling. 2348 */ 2349 if (ifp->if_capenable & IFCAP_POLLING) 2350 CSR_WRITE_2(sc, RL_IMR, 0); 2351 else /* otherwise ... */ 2352 #endif 2353 2354 /* 2355 * Enable interrupts. 2356 */ 2357 if (sc->rl_testmode) 2358 CSR_WRITE_2(sc, RL_IMR, 0); 2359 else 2360 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2361 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 2362 2363 /* Set initial TX threshold */ 2364 sc->rl_txthresh = RL_TX_THRESH_INIT; 2365 2366 /* Start RX/TX process. */ 2367 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2368 #ifdef notdef 2369 /* Enable receiver and transmitter. */ 2370 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2371 #endif 2372 /* 2373 * Load the addresses of the RX and TX lists into the chip. 2374 */ 2375 2376 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2377 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2378 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2379 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2380 2381 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2382 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2383 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2384 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2385 2386 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2387 2388 #ifdef RE_TX_MODERATION 2389 /* 2390 * Initialize the timer interrupt register so that 2391 * a timer interrupt will be generated once the timer 2392 * reaches a certain number of ticks. The timer is 2393 * reloaded on each transmit. This gives us TX interrupt 2394 * moderation, which dramatically improves TX frame rate. 2395 */ 2396 if (sc->rl_type == RL_8169) 2397 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2398 else 2399 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2400 #endif 2401 2402 /* 2403 * For 8169 gigE NICs, set the max allowed RX packet 2404 * size so we can receive jumbo frames. 2405 */ 2406 if (sc->rl_type == RL_8169) 2407 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2408 2409 if (sc->rl_testmode) 2410 return; 2411 2412 mii_mediachg(mii); 2413 2414 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 2415 2416 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2417 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2418 2419 2420 sc->rl_link = 0; 2421 2422 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2423 } 2424 2425 /* 2426 * Set media options. 2427 */ 2428 static int 2429 re_ifmedia_upd(ifp) 2430 struct ifnet *ifp; 2431 { 2432 struct rl_softc *sc; 2433 struct mii_data *mii; 2434 2435 sc = ifp->if_softc; 2436 mii = device_get_softc(sc->rl_miibus); 2437 RL_LOCK(sc); 2438 mii_mediachg(mii); 2439 RL_UNLOCK(sc); 2440 2441 return (0); 2442 } 2443 2444 /* 2445 * Report current media status. 2446 */ 2447 static void 2448 re_ifmedia_sts(ifp, ifmr) 2449 struct ifnet *ifp; 2450 struct ifmediareq *ifmr; 2451 { 2452 struct rl_softc *sc; 2453 struct mii_data *mii; 2454 2455 sc = ifp->if_softc; 2456 mii = device_get_softc(sc->rl_miibus); 2457 2458 RL_LOCK(sc); 2459 mii_pollstat(mii); 2460 RL_UNLOCK(sc); 2461 ifmr->ifm_active = mii->mii_media_active; 2462 ifmr->ifm_status = mii->mii_media_status; 2463 } 2464 2465 static int 2466 re_ioctl(ifp, command, data) 2467 struct ifnet *ifp; 2468 u_long command; 2469 caddr_t data; 2470 { 2471 struct rl_softc *sc = ifp->if_softc; 2472 struct ifreq *ifr = (struct ifreq *) data; 2473 struct mii_data *mii; 2474 int error = 0; 2475 2476 switch (command) { 2477 case SIOCSIFMTU: 2478 RL_LOCK(sc); 2479 if (ifr->ifr_mtu > RL_JUMBO_MTU) 2480 error = EINVAL; 2481 ifp->if_mtu = ifr->ifr_mtu; 2482 RL_UNLOCK(sc); 2483 break; 2484 case SIOCSIFFLAGS: 2485 RL_LOCK(sc); 2486 if (ifp->if_flags & IFF_UP) 2487 re_init_locked(sc); 2488 else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2489 re_stop(sc); 2490 RL_UNLOCK(sc); 2491 break; 2492 case SIOCADDMULTI: 2493 case SIOCDELMULTI: 2494 RL_LOCK(sc); 2495 re_setmulti(sc); 2496 RL_UNLOCK(sc); 2497 break; 2498 case SIOCGIFMEDIA: 2499 case SIOCSIFMEDIA: 2500 mii = device_get_softc(sc->rl_miibus); 2501 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2502 break; 2503 case SIOCSIFCAP: 2504 { 2505 int mask, reinit; 2506 2507 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2508 reinit = 0; 2509 #ifdef DEVICE_POLLING 2510 if (mask & IFCAP_POLLING) { 2511 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2512 error = ether_poll_register(re_poll, ifp); 2513 if (error) 2514 return(error); 2515 RL_LOCK(sc); 2516 /* Disable interrupts */ 2517 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2518 ifp->if_capenable |= IFCAP_POLLING; 2519 RL_UNLOCK(sc); 2520 2521 } else { 2522 error = ether_poll_deregister(ifp); 2523 /* Enable interrupts. */ 2524 RL_LOCK(sc); 2525 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2526 ifp->if_capenable &= ~IFCAP_POLLING; 2527 RL_UNLOCK(sc); 2528 } 2529 } 2530 #endif /* DEVICE_POLLING */ 2531 if (mask & IFCAP_HWCSUM) { 2532 ifp->if_capenable ^= IFCAP_HWCSUM; 2533 if (ifp->if_capenable & IFCAP_TXCSUM) 2534 ifp->if_hwassist = RE_CSUM_FEATURES; 2535 else 2536 ifp->if_hwassist = 0; 2537 reinit = 1; 2538 } 2539 if (mask & IFCAP_VLAN_HWTAGGING) { 2540 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2541 reinit = 1; 2542 } 2543 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) 2544 re_init(sc); 2545 } 2546 break; 2547 default: 2548 error = ether_ioctl(ifp, command, data); 2549 break; 2550 } 2551 2552 return (error); 2553 } 2554 2555 static void 2556 re_watchdog(ifp) 2557 struct ifnet *ifp; 2558 { 2559 struct rl_softc *sc; 2560 2561 sc = ifp->if_softc; 2562 RL_LOCK(sc); 2563 if_printf(ifp, "watchdog timeout\n"); 2564 ifp->if_oerrors++; 2565 2566 re_txeof(sc); 2567 re_rxeof(sc); 2568 re_init_locked(sc); 2569 2570 RL_UNLOCK(sc); 2571 } 2572 2573 /* 2574 * Stop the adapter and free any mbufs allocated to the 2575 * RX and TX lists. 2576 */ 2577 static void 2578 re_stop(sc) 2579 struct rl_softc *sc; 2580 { 2581 register int i; 2582 struct ifnet *ifp; 2583 2584 RL_LOCK_ASSERT(sc); 2585 2586 ifp = sc->rl_ifp; 2587 ifp->if_timer = 0; 2588 2589 callout_stop(&sc->rl_stat_callout); 2590 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2591 2592 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2593 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2594 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 2595 2596 if (sc->rl_head != NULL) { 2597 m_freem(sc->rl_head); 2598 sc->rl_head = sc->rl_tail = NULL; 2599 } 2600 2601 /* Free the TX list buffers. */ 2602 2603 for (i = 0; i < RL_TX_DESC_CNT; i++) { 2604 if (sc->rl_ldata.rl_tx_mbuf[i] != NULL) { 2605 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2606 sc->rl_ldata.rl_tx_dmamap[i]); 2607 m_freem(sc->rl_ldata.rl_tx_mbuf[i]); 2608 sc->rl_ldata.rl_tx_mbuf[i] = NULL; 2609 } 2610 } 2611 2612 /* Free the RX list buffers. */ 2613 2614 for (i = 0; i < RL_RX_DESC_CNT; i++) { 2615 if (sc->rl_ldata.rl_rx_mbuf[i] != NULL) { 2616 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2617 sc->rl_ldata.rl_rx_dmamap[i]); 2618 m_freem(sc->rl_ldata.rl_rx_mbuf[i]); 2619 sc->rl_ldata.rl_rx_mbuf[i] = NULL; 2620 } 2621 } 2622 } 2623 2624 /* 2625 * Device suspend routine. Stop the interface and save some PCI 2626 * settings in case the BIOS doesn't restore them properly on 2627 * resume. 2628 */ 2629 static int 2630 re_suspend(dev) 2631 device_t dev; 2632 { 2633 struct rl_softc *sc; 2634 2635 sc = device_get_softc(dev); 2636 2637 RL_LOCK(sc); 2638 re_stop(sc); 2639 sc->suspended = 1; 2640 RL_UNLOCK(sc); 2641 2642 return (0); 2643 } 2644 2645 /* 2646 * Device resume routine. Restore some PCI settings in case the BIOS 2647 * doesn't, re-enable busmastering, and restart the interface if 2648 * appropriate. 2649 */ 2650 static int 2651 re_resume(dev) 2652 device_t dev; 2653 { 2654 struct rl_softc *sc; 2655 struct ifnet *ifp; 2656 2657 sc = device_get_softc(dev); 2658 2659 RL_LOCK(sc); 2660 2661 ifp = sc->rl_ifp; 2662 2663 /* reinitialize interface if necessary */ 2664 if (ifp->if_flags & IFF_UP) 2665 re_init_locked(sc); 2666 2667 sc->suspended = 0; 2668 RL_UNLOCK(sc); 2669 2670 return (0); 2671 } 2672 2673 /* 2674 * Stop all chip I/O so that the kernel's probe routines don't 2675 * get confused by errant DMAs when rebooting. 2676 */ 2677 static void 2678 re_shutdown(dev) 2679 device_t dev; 2680 { 2681 struct rl_softc *sc; 2682 2683 sc = device_get_softc(dev); 2684 2685 RL_LOCK(sc); 2686 re_stop(sc); 2687 /* 2688 * Mark interface as down since otherwise we will panic if 2689 * interrupt comes in later on, which can happen in some 2690 * cases. 2691 */ 2692 sc->rl_ifp->if_flags &= ~IFF_UP; 2693 RL_UNLOCK(sc); 2694 } 2695