1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 1997, 1998-2003 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __FBSDID("$FreeBSD$"); 37 38 /* 39 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 40 * 41 * Written by Bill Paul <wpaul@windriver.com> 42 * Senior Networking Software Engineer 43 * Wind River Systems 44 */ 45 46 /* 47 * This driver is designed to support RealTek's next generation of 48 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 49 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 50 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 51 * 52 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 53 * with the older 8139 family, however it also supports a special 54 * C+ mode of operation that provides several new performance enhancing 55 * features. These include: 56 * 57 * o Descriptor based DMA mechanism. Each descriptor represents 58 * a single packet fragment. Data buffers may be aligned on 59 * any byte boundary. 60 * 61 * o 64-bit DMA 62 * 63 * o TCP/IP checksum offload for both RX and TX 64 * 65 * o High and normal priority transmit DMA rings 66 * 67 * o VLAN tag insertion and extraction 68 * 69 * o TCP large send (segmentation offload) 70 * 71 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 72 * programming API is fairly straightforward. The RX filtering, EEPROM 73 * access and PHY access is the same as it is on the older 8139 series 74 * chips. 75 * 76 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 77 * same programming API and feature set as the 8139C+ with the following 78 * differences and additions: 79 * 80 * o 1000Mbps mode 81 * 82 * o Jumbo frames 83 * 84 * o GMII and TBI ports/registers for interfacing with copper 85 * or fiber PHYs 86 * 87 * o RX and TX DMA rings can have up to 1024 descriptors 88 * (the 8139C+ allows a maximum of 64) 89 * 90 * o Slight differences in register layout from the 8139C+ 91 * 92 * The TX start and timer interrupt registers are at different locations 93 * on the 8169 than they are on the 8139C+. Also, the status word in the 94 * RX descriptor has a slightly different bit layout. The 8169 does not 95 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 96 * copper gigE PHY. 97 * 98 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 99 * (the 'S' stands for 'single-chip'). These devices have the same 100 * programming API as the older 8169, but also have some vendor-specific 101 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 102 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 103 * 104 * This driver takes advantage of the RX and TX checksum offload and 105 * VLAN tag insertion/extraction features. It also implements TX 106 * interrupt moderation using the timer interrupt registers, which 107 * significantly reduces TX interrupt load. There is also support 108 * for jumbo frames, however the 8169/8169S/8110S can not transmit 109 * jumbo frames larger than 7440, so the max MTU possible with this 110 * driver is 7422 bytes. 111 */ 112 113 #ifdef HAVE_KERNEL_OPTION_HEADERS 114 #include "opt_device_polling.h" 115 #endif 116 117 #include <sys/param.h> 118 #include <sys/endian.h> 119 #include <sys/systm.h> 120 #include <sys/sockio.h> 121 #include <sys/mbuf.h> 122 #include <sys/malloc.h> 123 #include <sys/module.h> 124 #include <sys/kernel.h> 125 #include <sys/socket.h> 126 #include <sys/lock.h> 127 #include <sys/mutex.h> 128 #include <sys/sysctl.h> 129 #include <sys/taskqueue.h> 130 131 #include <net/debugnet.h> 132 #include <net/if.h> 133 #include <net/if_var.h> 134 #include <net/if_arp.h> 135 #include <net/ethernet.h> 136 #include <net/if_dl.h> 137 #include <net/if_media.h> 138 #include <net/if_types.h> 139 #include <net/if_vlan_var.h> 140 141 #include <net/bpf.h> 142 143 #include <machine/bus.h> 144 #include <machine/resource.h> 145 #include <sys/bus.h> 146 #include <sys/rman.h> 147 148 #include <dev/mii/mii.h> 149 #include <dev/mii/miivar.h> 150 151 #include <dev/pci/pcireg.h> 152 #include <dev/pci/pcivar.h> 153 154 #include <dev/rl/if_rlreg.h> 155 156 MODULE_DEPEND(re, pci, 1, 1, 1); 157 MODULE_DEPEND(re, ether, 1, 1, 1); 158 MODULE_DEPEND(re, miibus, 1, 1, 1); 159 160 /* "device miibus" required. See GENERIC if you get errors here. */ 161 #include "miibus_if.h" 162 163 /* Tunables. */ 164 static int intr_filter = 0; 165 TUNABLE_INT("hw.re.intr_filter", &intr_filter); 166 static int msi_disable = 0; 167 TUNABLE_INT("hw.re.msi_disable", &msi_disable); 168 static int msix_disable = 0; 169 TUNABLE_INT("hw.re.msix_disable", &msix_disable); 170 static int prefer_iomap = 0; 171 TUNABLE_INT("hw.re.prefer_iomap", &prefer_iomap); 172 173 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 174 175 /* 176 * Various supported device vendors/types and their names. 177 */ 178 static const struct rl_type re_devs[] = { 179 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0, 180 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 181 { DLINK_VENDORID, DLINK_DEVICEID_530T_REVC, 0, 182 "D-Link DGE-530(T) Gigabit Ethernet Adapter" }, 183 { RT_VENDORID, RT_DEVICEID_8139, 0, 184 "RealTek 8139C+ 10/100BaseTX" }, 185 { RT_VENDORID, RT_DEVICEID_8101E, 0, 186 "RealTek 810xE PCIe 10/100baseTX" }, 187 { RT_VENDORID, RT_DEVICEID_8168, 0, 188 "RealTek 8168/8111 B/C/CP/D/DP/E/F/G PCIe Gigabit Ethernet" }, 189 { NCUBE_VENDORID, RT_DEVICEID_8168, 0, 190 "TP-Link TG-3468 v2 (RTL8168) Gigabit Ethernet" }, 191 { RT_VENDORID, RT_DEVICEID_8169, 0, 192 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" }, 193 { RT_VENDORID, RT_DEVICEID_8169SC, 0, 194 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 195 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0, 196 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 197 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0, 198 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 199 { USR_VENDORID, USR_DEVICEID_997902, 0, 200 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 201 }; 202 203 static const struct rl_hwrev re_hwrevs[] = { 204 { RL_HWREV_8139, RL_8139, "", RL_MTU }, 205 { RL_HWREV_8139A, RL_8139, "A", RL_MTU }, 206 { RL_HWREV_8139AG, RL_8139, "A-G", RL_MTU }, 207 { RL_HWREV_8139B, RL_8139, "B", RL_MTU }, 208 { RL_HWREV_8130, RL_8139, "8130", RL_MTU }, 209 { RL_HWREV_8139C, RL_8139, "C", RL_MTU }, 210 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C", RL_MTU }, 211 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+", RL_MTU }, 212 { RL_HWREV_8168B_SPIN1, RL_8169, "8168", RL_JUMBO_MTU }, 213 { RL_HWREV_8169, RL_8169, "8169", RL_JUMBO_MTU }, 214 { RL_HWREV_8169S, RL_8169, "8169S", RL_JUMBO_MTU }, 215 { RL_HWREV_8110S, RL_8169, "8110S", RL_JUMBO_MTU }, 216 { RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB", RL_JUMBO_MTU }, 217 { RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU }, 218 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL", RL_JUMBO_MTU }, 219 { RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU }, 220 { RL_HWREV_8100, RL_8139, "8100", RL_MTU }, 221 { RL_HWREV_8101, RL_8139, "8101", RL_MTU }, 222 { RL_HWREV_8100E, RL_8169, "8100E", RL_MTU }, 223 { RL_HWREV_8101E, RL_8169, "8101E", RL_MTU }, 224 { RL_HWREV_8102E, RL_8169, "8102E", RL_MTU }, 225 { RL_HWREV_8102EL, RL_8169, "8102EL", RL_MTU }, 226 { RL_HWREV_8102EL_SPIN1, RL_8169, "8102EL", RL_MTU }, 227 { RL_HWREV_8103E, RL_8169, "8103E", RL_MTU }, 228 { RL_HWREV_8401E, RL_8169, "8401E", RL_MTU }, 229 { RL_HWREV_8402, RL_8169, "8402", RL_MTU }, 230 { RL_HWREV_8105E, RL_8169, "8105E", RL_MTU }, 231 { RL_HWREV_8105E_SPIN1, RL_8169, "8105E", RL_MTU }, 232 { RL_HWREV_8106E, RL_8169, "8106E", RL_MTU }, 233 { RL_HWREV_8168B_SPIN2, RL_8169, "8168", RL_JUMBO_MTU }, 234 { RL_HWREV_8168B_SPIN3, RL_8169, "8168", RL_JUMBO_MTU }, 235 { RL_HWREV_8168C, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K }, 236 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K }, 237 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP", RL_JUMBO_MTU_6K }, 238 { RL_HWREV_8168D, RL_8169, "8168D/8111D", RL_JUMBO_MTU_9K }, 239 { RL_HWREV_8168DP, RL_8169, "8168DP/8111DP", RL_JUMBO_MTU_9K }, 240 { RL_HWREV_8168E, RL_8169, "8168E/8111E", RL_JUMBO_MTU_9K}, 241 { RL_HWREV_8168E_VL, RL_8169, "8168E/8111E-VL", RL_JUMBO_MTU_6K}, 242 { RL_HWREV_8168EP, RL_8169, "8168EP/8111EP", RL_JUMBO_MTU_9K}, 243 { RL_HWREV_8168F, RL_8169, "8168F/8111F", RL_JUMBO_MTU_9K}, 244 { RL_HWREV_8168G, RL_8169, "8168G/8111G", RL_JUMBO_MTU_9K}, 245 { RL_HWREV_8168GU, RL_8169, "8168GU/8111GU", RL_JUMBO_MTU_9K}, 246 { RL_HWREV_8168H, RL_8169, "8168H/8111H", RL_JUMBO_MTU_9K}, 247 { RL_HWREV_8411, RL_8169, "8411", RL_JUMBO_MTU_9K}, 248 { RL_HWREV_8411B, RL_8169, "8411B", RL_JUMBO_MTU_9K}, 249 { 0, 0, NULL, 0 } 250 }; 251 252 static int re_probe (device_t); 253 static int re_attach (device_t); 254 static int re_detach (device_t); 255 256 static int re_encap (struct rl_softc *, struct mbuf **); 257 258 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 259 static int re_allocmem (device_t, struct rl_softc *); 260 static __inline void re_discard_rxbuf 261 (struct rl_softc *, int); 262 static int re_newbuf (struct rl_softc *, int); 263 static int re_jumbo_newbuf (struct rl_softc *, int); 264 static int re_rx_list_init (struct rl_softc *); 265 static int re_jrx_list_init (struct rl_softc *); 266 static int re_tx_list_init (struct rl_softc *); 267 #ifdef RE_FIXUP_RX 268 static __inline void re_fixup_rx 269 (struct mbuf *); 270 #endif 271 static int re_rxeof (struct rl_softc *, int *); 272 static void re_txeof (struct rl_softc *); 273 #ifdef DEVICE_POLLING 274 static int re_poll (struct ifnet *, enum poll_cmd, int); 275 static int re_poll_locked (struct ifnet *, enum poll_cmd, int); 276 #endif 277 static int re_intr (void *); 278 static void re_intr_msi (void *); 279 static void re_tick (void *); 280 static void re_int_task (void *, int); 281 static void re_start (struct ifnet *); 282 static void re_start_locked (struct ifnet *); 283 static void re_start_tx (struct rl_softc *); 284 static int re_ioctl (struct ifnet *, u_long, caddr_t); 285 static void re_init (void *); 286 static void re_init_locked (struct rl_softc *); 287 static void re_stop (struct rl_softc *); 288 static void re_watchdog (struct rl_softc *); 289 static int re_suspend (device_t); 290 static int re_resume (device_t); 291 static int re_shutdown (device_t); 292 static int re_ifmedia_upd (struct ifnet *); 293 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 294 295 static void re_eeprom_putbyte (struct rl_softc *, int); 296 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 297 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 298 static int re_gmii_readreg (device_t, int, int); 299 static int re_gmii_writereg (device_t, int, int, int); 300 301 static int re_miibus_readreg (device_t, int, int); 302 static int re_miibus_writereg (device_t, int, int, int); 303 static void re_miibus_statchg (device_t); 304 305 static void re_set_jumbo (struct rl_softc *, int); 306 static void re_set_rxmode (struct rl_softc *); 307 static void re_reset (struct rl_softc *); 308 static void re_setwol (struct rl_softc *); 309 static void re_clrwol (struct rl_softc *); 310 static void re_set_linkspeed (struct rl_softc *); 311 312 DEBUGNET_DEFINE(re); 313 314 #ifdef DEV_NETMAP /* see ixgbe.c for details */ 315 #include <dev/netmap/if_re_netmap.h> 316 MODULE_DEPEND(re, netmap, 1, 1, 1); 317 #endif /* !DEV_NETMAP */ 318 319 #ifdef RE_DIAG 320 static int re_diag (struct rl_softc *); 321 #endif 322 323 static void re_add_sysctls (struct rl_softc *); 324 static int re_sysctl_stats (SYSCTL_HANDLER_ARGS); 325 static int sysctl_int_range (SYSCTL_HANDLER_ARGS, int, int); 326 static int sysctl_hw_re_int_mod (SYSCTL_HANDLER_ARGS); 327 328 static device_method_t re_methods[] = { 329 /* Device interface */ 330 DEVMETHOD(device_probe, re_probe), 331 DEVMETHOD(device_attach, re_attach), 332 DEVMETHOD(device_detach, re_detach), 333 DEVMETHOD(device_suspend, re_suspend), 334 DEVMETHOD(device_resume, re_resume), 335 DEVMETHOD(device_shutdown, re_shutdown), 336 337 /* MII interface */ 338 DEVMETHOD(miibus_readreg, re_miibus_readreg), 339 DEVMETHOD(miibus_writereg, re_miibus_writereg), 340 DEVMETHOD(miibus_statchg, re_miibus_statchg), 341 342 DEVMETHOD_END 343 }; 344 345 static driver_t re_driver = { 346 "re", 347 re_methods, 348 sizeof(struct rl_softc) 349 }; 350 351 static devclass_t re_devclass; 352 353 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 354 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 355 356 #define EE_SET(x) \ 357 CSR_WRITE_1(sc, RL_EECMD, \ 358 CSR_READ_1(sc, RL_EECMD) | x) 359 360 #define EE_CLR(x) \ 361 CSR_WRITE_1(sc, RL_EECMD, \ 362 CSR_READ_1(sc, RL_EECMD) & ~x) 363 364 /* 365 * Send a read command and address to the EEPROM, check for ACK. 366 */ 367 static void 368 re_eeprom_putbyte(struct rl_softc *sc, int addr) 369 { 370 int d, i; 371 372 d = addr | (RL_9346_READ << sc->rl_eewidth); 373 374 /* 375 * Feed in each bit and strobe the clock. 376 */ 377 378 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 379 if (d & i) { 380 EE_SET(RL_EE_DATAIN); 381 } else { 382 EE_CLR(RL_EE_DATAIN); 383 } 384 DELAY(100); 385 EE_SET(RL_EE_CLK); 386 DELAY(150); 387 EE_CLR(RL_EE_CLK); 388 DELAY(100); 389 } 390 } 391 392 /* 393 * Read a word of data stored in the EEPROM at address 'addr.' 394 */ 395 static void 396 re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest) 397 { 398 int i; 399 u_int16_t word = 0; 400 401 /* 402 * Send address of word we want to read. 403 */ 404 re_eeprom_putbyte(sc, addr); 405 406 /* 407 * Start reading bits from EEPROM. 408 */ 409 for (i = 0x8000; i; i >>= 1) { 410 EE_SET(RL_EE_CLK); 411 DELAY(100); 412 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 413 word |= i; 414 EE_CLR(RL_EE_CLK); 415 DELAY(100); 416 } 417 418 *dest = word; 419 } 420 421 /* 422 * Read a sequence of words from the EEPROM. 423 */ 424 static void 425 re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt) 426 { 427 int i; 428 u_int16_t word = 0, *ptr; 429 430 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 431 432 DELAY(100); 433 434 for (i = 0; i < cnt; i++) { 435 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 436 re_eeprom_getword(sc, off + i, &word); 437 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 438 ptr = (u_int16_t *)(dest + (i * 2)); 439 *ptr = word; 440 } 441 442 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 443 } 444 445 static int 446 re_gmii_readreg(device_t dev, int phy, int reg) 447 { 448 struct rl_softc *sc; 449 u_int32_t rval; 450 int i; 451 452 sc = device_get_softc(dev); 453 454 /* Let the rgephy driver read the GMEDIASTAT register */ 455 456 if (reg == RL_GMEDIASTAT) { 457 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 458 return (rval); 459 } 460 461 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 462 463 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 464 rval = CSR_READ_4(sc, RL_PHYAR); 465 if (rval & RL_PHYAR_BUSY) 466 break; 467 DELAY(25); 468 } 469 470 if (i == RL_PHY_TIMEOUT) { 471 device_printf(sc->rl_dev, "PHY read failed\n"); 472 return (0); 473 } 474 475 /* 476 * Controller requires a 20us delay to process next MDIO request. 477 */ 478 DELAY(20); 479 480 return (rval & RL_PHYAR_PHYDATA); 481 } 482 483 static int 484 re_gmii_writereg(device_t dev, int phy, int reg, int data) 485 { 486 struct rl_softc *sc; 487 u_int32_t rval; 488 int i; 489 490 sc = device_get_softc(dev); 491 492 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 493 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 494 495 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 496 rval = CSR_READ_4(sc, RL_PHYAR); 497 if (!(rval & RL_PHYAR_BUSY)) 498 break; 499 DELAY(25); 500 } 501 502 if (i == RL_PHY_TIMEOUT) { 503 device_printf(sc->rl_dev, "PHY write failed\n"); 504 return (0); 505 } 506 507 /* 508 * Controller requires a 20us delay to process next MDIO request. 509 */ 510 DELAY(20); 511 512 return (0); 513 } 514 515 static int 516 re_miibus_readreg(device_t dev, int phy, int reg) 517 { 518 struct rl_softc *sc; 519 u_int16_t rval = 0; 520 u_int16_t re8139_reg = 0; 521 522 sc = device_get_softc(dev); 523 524 if (sc->rl_type == RL_8169) { 525 rval = re_gmii_readreg(dev, phy, reg); 526 return (rval); 527 } 528 529 switch (reg) { 530 case MII_BMCR: 531 re8139_reg = RL_BMCR; 532 break; 533 case MII_BMSR: 534 re8139_reg = RL_BMSR; 535 break; 536 case MII_ANAR: 537 re8139_reg = RL_ANAR; 538 break; 539 case MII_ANER: 540 re8139_reg = RL_ANER; 541 break; 542 case MII_ANLPAR: 543 re8139_reg = RL_LPAR; 544 break; 545 case MII_PHYIDR1: 546 case MII_PHYIDR2: 547 return (0); 548 /* 549 * Allow the rlphy driver to read the media status 550 * register. If we have a link partner which does not 551 * support NWAY, this is the register which will tell 552 * us the results of parallel detection. 553 */ 554 case RL_MEDIASTAT: 555 rval = CSR_READ_1(sc, RL_MEDIASTAT); 556 return (rval); 557 default: 558 device_printf(sc->rl_dev, "bad phy register\n"); 559 return (0); 560 } 561 rval = CSR_READ_2(sc, re8139_reg); 562 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 563 /* 8139C+ has different bit layout. */ 564 rval &= ~(BMCR_LOOP | BMCR_ISO); 565 } 566 return (rval); 567 } 568 569 static int 570 re_miibus_writereg(device_t dev, int phy, int reg, int data) 571 { 572 struct rl_softc *sc; 573 u_int16_t re8139_reg = 0; 574 int rval = 0; 575 576 sc = device_get_softc(dev); 577 578 if (sc->rl_type == RL_8169) { 579 rval = re_gmii_writereg(dev, phy, reg, data); 580 return (rval); 581 } 582 583 switch (reg) { 584 case MII_BMCR: 585 re8139_reg = RL_BMCR; 586 if (sc->rl_type == RL_8139CPLUS) { 587 /* 8139C+ has different bit layout. */ 588 data &= ~(BMCR_LOOP | BMCR_ISO); 589 } 590 break; 591 case MII_BMSR: 592 re8139_reg = RL_BMSR; 593 break; 594 case MII_ANAR: 595 re8139_reg = RL_ANAR; 596 break; 597 case MII_ANER: 598 re8139_reg = RL_ANER; 599 break; 600 case MII_ANLPAR: 601 re8139_reg = RL_LPAR; 602 break; 603 case MII_PHYIDR1: 604 case MII_PHYIDR2: 605 return (0); 606 break; 607 default: 608 device_printf(sc->rl_dev, "bad phy register\n"); 609 return (0); 610 } 611 CSR_WRITE_2(sc, re8139_reg, data); 612 return (0); 613 } 614 615 static void 616 re_miibus_statchg(device_t dev) 617 { 618 struct rl_softc *sc; 619 struct ifnet *ifp; 620 struct mii_data *mii; 621 622 sc = device_get_softc(dev); 623 mii = device_get_softc(sc->rl_miibus); 624 ifp = sc->rl_ifp; 625 if (mii == NULL || ifp == NULL || 626 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 627 return; 628 629 sc->rl_flags &= ~RL_FLAG_LINK; 630 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 631 (IFM_ACTIVE | IFM_AVALID)) { 632 switch (IFM_SUBTYPE(mii->mii_media_active)) { 633 case IFM_10_T: 634 case IFM_100_TX: 635 sc->rl_flags |= RL_FLAG_LINK; 636 break; 637 case IFM_1000_T: 638 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0) 639 break; 640 sc->rl_flags |= RL_FLAG_LINK; 641 break; 642 default: 643 break; 644 } 645 } 646 /* 647 * RealTek controllers do not provide any interface to the RX/TX 648 * MACs for resolved speed, duplex and flow-control parameters. 649 */ 650 } 651 652 /* 653 * Set the RX configuration and 64-bit multicast hash filter. 654 */ 655 static void 656 re_set_rxmode(struct rl_softc *sc) 657 { 658 struct ifnet *ifp; 659 struct ifmultiaddr *ifma; 660 uint32_t hashes[2] = { 0, 0 }; 661 uint32_t h, rxfilt; 662 663 RL_LOCK_ASSERT(sc); 664 665 ifp = sc->rl_ifp; 666 667 rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD; 668 if ((sc->rl_flags & RL_FLAG_EARLYOFF) != 0) 669 rxfilt |= RL_RXCFG_EARLYOFF; 670 else if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0) 671 rxfilt |= RL_RXCFG_EARLYOFFV2; 672 673 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 674 if (ifp->if_flags & IFF_PROMISC) 675 rxfilt |= RL_RXCFG_RX_ALLPHYS; 676 /* 677 * Unlike other hardwares, we have to explicitly set 678 * RL_RXCFG_RX_MULTI to receive multicast frames in 679 * promiscuous mode. 680 */ 681 rxfilt |= RL_RXCFG_RX_MULTI; 682 hashes[0] = hashes[1] = 0xffffffff; 683 goto done; 684 } 685 686 if_maddr_rlock(ifp); 687 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 688 if (ifma->ifma_addr->sa_family != AF_LINK) 689 continue; 690 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 691 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 692 if (h < 32) 693 hashes[0] |= (1 << h); 694 else 695 hashes[1] |= (1 << (h - 32)); 696 } 697 if_maddr_runlock(ifp); 698 699 if (hashes[0] != 0 || hashes[1] != 0) { 700 /* 701 * For some unfathomable reason, RealTek decided to 702 * reverse the order of the multicast hash registers 703 * in the PCI Express parts. This means we have to 704 * write the hash pattern in reverse order for those 705 * devices. 706 */ 707 if ((sc->rl_flags & RL_FLAG_PCIE) != 0) { 708 h = bswap32(hashes[0]); 709 hashes[0] = bswap32(hashes[1]); 710 hashes[1] = h; 711 } 712 rxfilt |= RL_RXCFG_RX_MULTI; 713 } 714 715 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168F) { 716 /* Disable multicast filtering due to silicon bug. */ 717 hashes[0] = 0xffffffff; 718 hashes[1] = 0xffffffff; 719 } 720 721 done: 722 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 723 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 724 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 725 } 726 727 static void 728 re_reset(struct rl_softc *sc) 729 { 730 int i; 731 732 RL_LOCK_ASSERT(sc); 733 734 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 735 736 for (i = 0; i < RL_TIMEOUT; i++) { 737 DELAY(10); 738 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 739 break; 740 } 741 if (i == RL_TIMEOUT) 742 device_printf(sc->rl_dev, "reset never completed!\n"); 743 744 if ((sc->rl_flags & RL_FLAG_MACRESET) != 0) 745 CSR_WRITE_1(sc, 0x82, 1); 746 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169S) 747 re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0); 748 } 749 750 #ifdef RE_DIAG 751 752 /* 753 * The following routine is designed to test for a defect on some 754 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 755 * lines connected to the bus, however for a 32-bit only card, they 756 * should be pulled high. The result of this defect is that the 757 * NIC will not work right if you plug it into a 64-bit slot: DMA 758 * operations will be done with 64-bit transfers, which will fail 759 * because the 64-bit data lines aren't connected. 760 * 761 * There's no way to work around this (short of talking a soldering 762 * iron to the board), however we can detect it. The method we use 763 * here is to put the NIC into digital loopback mode, set the receiver 764 * to promiscuous mode, and then try to send a frame. We then compare 765 * the frame data we sent to what was received. If the data matches, 766 * then the NIC is working correctly, otherwise we know the user has 767 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 768 * slot. In the latter case, there's no way the NIC can work correctly, 769 * so we print out a message on the console and abort the device attach. 770 */ 771 772 static int 773 re_diag(struct rl_softc *sc) 774 { 775 struct ifnet *ifp = sc->rl_ifp; 776 struct mbuf *m0; 777 struct ether_header *eh; 778 struct rl_desc *cur_rx; 779 u_int16_t status; 780 u_int32_t rxstat; 781 int total_len, i, error = 0, phyaddr; 782 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 783 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 784 785 /* Allocate a single mbuf */ 786 MGETHDR(m0, M_NOWAIT, MT_DATA); 787 if (m0 == NULL) 788 return (ENOBUFS); 789 790 RL_LOCK(sc); 791 792 /* 793 * Initialize the NIC in test mode. This sets the chip up 794 * so that it can send and receive frames, but performs the 795 * following special functions: 796 * - Puts receiver in promiscuous mode 797 * - Enables digital loopback mode 798 * - Leaves interrupts turned off 799 */ 800 801 ifp->if_flags |= IFF_PROMISC; 802 sc->rl_testmode = 1; 803 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 804 re_init_locked(sc); 805 sc->rl_flags |= RL_FLAG_LINK; 806 if (sc->rl_type == RL_8169) 807 phyaddr = 1; 808 else 809 phyaddr = 0; 810 811 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 812 for (i = 0; i < RL_TIMEOUT; i++) { 813 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 814 if (!(status & BMCR_RESET)) 815 break; 816 } 817 818 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 819 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 820 821 DELAY(100000); 822 823 /* Put some data in the mbuf */ 824 825 eh = mtod(m0, struct ether_header *); 826 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 827 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 828 eh->ether_type = htons(ETHERTYPE_IP); 829 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 830 831 /* 832 * Queue the packet, start transmission. 833 * Note: IF_HANDOFF() ultimately calls re_start() for us. 834 */ 835 836 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 837 RL_UNLOCK(sc); 838 /* XXX: re_diag must not be called when in ALTQ mode */ 839 IF_HANDOFF(&ifp->if_snd, m0, ifp); 840 RL_LOCK(sc); 841 m0 = NULL; 842 843 /* Wait for it to propagate through the chip */ 844 845 DELAY(100000); 846 for (i = 0; i < RL_TIMEOUT; i++) { 847 status = CSR_READ_2(sc, RL_ISR); 848 CSR_WRITE_2(sc, RL_ISR, status); 849 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 850 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 851 break; 852 DELAY(10); 853 } 854 855 if (i == RL_TIMEOUT) { 856 device_printf(sc->rl_dev, 857 "diagnostic failed, failed to receive packet in" 858 " loopback mode\n"); 859 error = EIO; 860 goto done; 861 } 862 863 /* 864 * The packet should have been dumped into the first 865 * entry in the RX DMA ring. Grab it from there. 866 */ 867 868 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 869 sc->rl_ldata.rl_rx_list_map, 870 BUS_DMASYNC_POSTREAD); 871 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 872 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 873 BUS_DMASYNC_POSTREAD); 874 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 875 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 876 877 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 878 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 879 eh = mtod(m0, struct ether_header *); 880 881 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 882 total_len = RL_RXBYTES(cur_rx); 883 rxstat = le32toh(cur_rx->rl_cmdstat); 884 885 if (total_len != ETHER_MIN_LEN) { 886 device_printf(sc->rl_dev, 887 "diagnostic failed, received short packet\n"); 888 error = EIO; 889 goto done; 890 } 891 892 /* Test that the received packet data matches what we sent. */ 893 894 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 895 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 896 ntohs(eh->ether_type) != ETHERTYPE_IP) { 897 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 898 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 899 dst, ":", src, ":", ETHERTYPE_IP); 900 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 901 eh->ether_dhost, ":", eh->ether_shost, ":", 902 ntohs(eh->ether_type)); 903 device_printf(sc->rl_dev, "You may have a defective 32-bit " 904 "NIC plugged into a 64-bit PCI slot.\n"); 905 device_printf(sc->rl_dev, "Please re-install the NIC in a " 906 "32-bit slot for proper operation.\n"); 907 device_printf(sc->rl_dev, "Read the re(4) man page for more " 908 "details.\n"); 909 error = EIO; 910 } 911 912 done: 913 /* Turn interface off, release resources */ 914 915 sc->rl_testmode = 0; 916 sc->rl_flags &= ~RL_FLAG_LINK; 917 ifp->if_flags &= ~IFF_PROMISC; 918 re_stop(sc); 919 if (m0 != NULL) 920 m_freem(m0); 921 922 RL_UNLOCK(sc); 923 924 return (error); 925 } 926 927 #endif 928 929 /* 930 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 931 * IDs against our list and return a device name if we find a match. 932 */ 933 static int 934 re_probe(device_t dev) 935 { 936 const struct rl_type *t; 937 uint16_t devid, vendor; 938 uint16_t revid, sdevid; 939 int i; 940 941 vendor = pci_get_vendor(dev); 942 devid = pci_get_device(dev); 943 revid = pci_get_revid(dev); 944 sdevid = pci_get_subdevice(dev); 945 946 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 947 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 948 /* 949 * Only attach to rev. 3 of the Linksys EG1032 adapter. 950 * Rev. 2 is supported by sk(4). 951 */ 952 return (ENXIO); 953 } 954 } 955 956 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 957 if (revid != 0x20) { 958 /* 8139, let rl(4) take care of this device. */ 959 return (ENXIO); 960 } 961 } 962 963 t = re_devs; 964 for (i = 0; i < nitems(re_devs); i++, t++) { 965 if (vendor == t->rl_vid && devid == t->rl_did) { 966 device_set_desc(dev, t->rl_name); 967 return (BUS_PROBE_DEFAULT); 968 } 969 } 970 971 return (ENXIO); 972 } 973 974 /* 975 * Map a single buffer address. 976 */ 977 978 static void 979 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 980 { 981 bus_addr_t *addr; 982 983 if (error) 984 return; 985 986 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 987 addr = arg; 988 *addr = segs->ds_addr; 989 } 990 991 static int 992 re_allocmem(device_t dev, struct rl_softc *sc) 993 { 994 bus_addr_t lowaddr; 995 bus_size_t rx_list_size, tx_list_size; 996 int error; 997 int i; 998 999 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 1000 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 1001 1002 /* 1003 * Allocate the parent bus DMA tag appropriate for PCI. 1004 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD 1005 * register should be set. However some RealTek chips are known 1006 * to be buggy on DAC handling, therefore disable DAC by limiting 1007 * DMA address space to 32bit. PCIe variants of RealTek chips 1008 * may not have the limitation. 1009 */ 1010 lowaddr = BUS_SPACE_MAXADDR; 1011 if ((sc->rl_flags & RL_FLAG_PCIE) == 0) 1012 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1013 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 1014 lowaddr, BUS_SPACE_MAXADDR, NULL, NULL, 1015 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 1016 NULL, NULL, &sc->rl_parent_tag); 1017 if (error) { 1018 device_printf(dev, "could not allocate parent DMA tag\n"); 1019 return (error); 1020 } 1021 1022 /* 1023 * Allocate map for TX mbufs. 1024 */ 1025 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 1026 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1027 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 1028 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 1029 if (error) { 1030 device_printf(dev, "could not allocate TX DMA tag\n"); 1031 return (error); 1032 } 1033 1034 /* 1035 * Allocate map for RX mbufs. 1036 */ 1037 1038 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 1039 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 1040 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1041 MJUM9BYTES, 1, MJUM9BYTES, 0, NULL, NULL, 1042 &sc->rl_ldata.rl_jrx_mtag); 1043 if (error) { 1044 device_printf(dev, 1045 "could not allocate jumbo RX DMA tag\n"); 1046 return (error); 1047 } 1048 } 1049 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 1050 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1051 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 1052 if (error) { 1053 device_printf(dev, "could not allocate RX DMA tag\n"); 1054 return (error); 1055 } 1056 1057 /* 1058 * Allocate map for TX descriptor list. 1059 */ 1060 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1061 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1062 NULL, tx_list_size, 1, tx_list_size, 0, 1063 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1064 if (error) { 1065 device_printf(dev, "could not allocate TX DMA ring tag\n"); 1066 return (error); 1067 } 1068 1069 /* Allocate DMA'able memory for the TX ring */ 1070 1071 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1072 (void **)&sc->rl_ldata.rl_tx_list, 1073 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1074 &sc->rl_ldata.rl_tx_list_map); 1075 if (error) { 1076 device_printf(dev, "could not allocate TX DMA ring\n"); 1077 return (error); 1078 } 1079 1080 /* Load the map for the TX ring. */ 1081 1082 sc->rl_ldata.rl_tx_list_addr = 0; 1083 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1084 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1085 tx_list_size, re_dma_map_addr, 1086 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1087 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 1088 device_printf(dev, "could not load TX DMA ring\n"); 1089 return (ENOMEM); 1090 } 1091 1092 /* Create DMA maps for TX buffers */ 1093 1094 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1095 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1096 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1097 if (error) { 1098 device_printf(dev, "could not create DMA map for TX\n"); 1099 return (error); 1100 } 1101 } 1102 1103 /* 1104 * Allocate map for RX descriptor list. 1105 */ 1106 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1107 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1108 NULL, rx_list_size, 1, rx_list_size, 0, 1109 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1110 if (error) { 1111 device_printf(dev, "could not create RX DMA ring tag\n"); 1112 return (error); 1113 } 1114 1115 /* Allocate DMA'able memory for the RX ring */ 1116 1117 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1118 (void **)&sc->rl_ldata.rl_rx_list, 1119 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1120 &sc->rl_ldata.rl_rx_list_map); 1121 if (error) { 1122 device_printf(dev, "could not allocate RX DMA ring\n"); 1123 return (error); 1124 } 1125 1126 /* Load the map for the RX ring. */ 1127 1128 sc->rl_ldata.rl_rx_list_addr = 0; 1129 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1130 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1131 rx_list_size, re_dma_map_addr, 1132 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1133 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1134 device_printf(dev, "could not load RX DMA ring\n"); 1135 return (ENOMEM); 1136 } 1137 1138 /* Create DMA maps for RX buffers */ 1139 1140 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 1141 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0, 1142 &sc->rl_ldata.rl_jrx_sparemap); 1143 if (error) { 1144 device_printf(dev, 1145 "could not create spare DMA map for jumbo RX\n"); 1146 return (error); 1147 } 1148 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1149 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0, 1150 &sc->rl_ldata.rl_jrx_desc[i].rx_dmamap); 1151 if (error) { 1152 device_printf(dev, 1153 "could not create DMA map for jumbo RX\n"); 1154 return (error); 1155 } 1156 } 1157 } 1158 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1159 &sc->rl_ldata.rl_rx_sparemap); 1160 if (error) { 1161 device_printf(dev, "could not create spare DMA map for RX\n"); 1162 return (error); 1163 } 1164 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1165 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1166 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1167 if (error) { 1168 device_printf(dev, "could not create DMA map for RX\n"); 1169 return (error); 1170 } 1171 } 1172 1173 /* Create DMA map for statistics. */ 1174 error = bus_dma_tag_create(sc->rl_parent_tag, RL_DUMP_ALIGN, 0, 1175 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1176 sizeof(struct rl_stats), 1, sizeof(struct rl_stats), 0, NULL, NULL, 1177 &sc->rl_ldata.rl_stag); 1178 if (error) { 1179 device_printf(dev, "could not create statistics DMA tag\n"); 1180 return (error); 1181 } 1182 /* Allocate DMA'able memory for statistics. */ 1183 error = bus_dmamem_alloc(sc->rl_ldata.rl_stag, 1184 (void **)&sc->rl_ldata.rl_stats, 1185 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1186 &sc->rl_ldata.rl_smap); 1187 if (error) { 1188 device_printf(dev, 1189 "could not allocate statistics DMA memory\n"); 1190 return (error); 1191 } 1192 /* Load the map for statistics. */ 1193 sc->rl_ldata.rl_stats_addr = 0; 1194 error = bus_dmamap_load(sc->rl_ldata.rl_stag, sc->rl_ldata.rl_smap, 1195 sc->rl_ldata.rl_stats, sizeof(struct rl_stats), re_dma_map_addr, 1196 &sc->rl_ldata.rl_stats_addr, BUS_DMA_NOWAIT); 1197 if (error != 0 || sc->rl_ldata.rl_stats_addr == 0) { 1198 device_printf(dev, "could not load statistics DMA memory\n"); 1199 return (ENOMEM); 1200 } 1201 1202 return (0); 1203 } 1204 1205 /* 1206 * Attach the interface. Allocate softc structures, do ifmedia 1207 * setup and ethernet/BPF attach. 1208 */ 1209 static int 1210 re_attach(device_t dev) 1211 { 1212 u_char eaddr[ETHER_ADDR_LEN]; 1213 u_int16_t as[ETHER_ADDR_LEN / 2]; 1214 struct rl_softc *sc; 1215 struct ifnet *ifp; 1216 const struct rl_hwrev *hw_rev; 1217 int capmask, error = 0, hwrev, i, msic, msixc, 1218 phy, reg, rid; 1219 u_int32_t cap, ctl; 1220 u_int16_t devid, re_did = 0; 1221 uint8_t cfg; 1222 1223 sc = device_get_softc(dev); 1224 sc->rl_dev = dev; 1225 1226 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1227 MTX_DEF); 1228 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1229 1230 /* 1231 * Map control/status registers. 1232 */ 1233 pci_enable_busmaster(dev); 1234 1235 devid = pci_get_device(dev); 1236 /* 1237 * Prefer memory space register mapping over IO space. 1238 * Because RTL8169SC does not seem to work when memory mapping 1239 * is used always activate io mapping. 1240 */ 1241 if (devid == RT_DEVICEID_8169SC) 1242 prefer_iomap = 1; 1243 if (prefer_iomap == 0) { 1244 sc->rl_res_id = PCIR_BAR(1); 1245 sc->rl_res_type = SYS_RES_MEMORY; 1246 /* RTL8168/8101E seems to use different BARs. */ 1247 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E) 1248 sc->rl_res_id = PCIR_BAR(2); 1249 } else { 1250 sc->rl_res_id = PCIR_BAR(0); 1251 sc->rl_res_type = SYS_RES_IOPORT; 1252 } 1253 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1254 &sc->rl_res_id, RF_ACTIVE); 1255 if (sc->rl_res == NULL && prefer_iomap == 0) { 1256 sc->rl_res_id = PCIR_BAR(0); 1257 sc->rl_res_type = SYS_RES_IOPORT; 1258 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1259 &sc->rl_res_id, RF_ACTIVE); 1260 } 1261 if (sc->rl_res == NULL) { 1262 device_printf(dev, "couldn't map ports/memory\n"); 1263 error = ENXIO; 1264 goto fail; 1265 } 1266 1267 sc->rl_btag = rman_get_bustag(sc->rl_res); 1268 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1269 1270 msic = pci_msi_count(dev); 1271 msixc = pci_msix_count(dev); 1272 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 1273 sc->rl_flags |= RL_FLAG_PCIE; 1274 sc->rl_expcap = reg; 1275 } 1276 if (bootverbose) { 1277 device_printf(dev, "MSI count : %d\n", msic); 1278 device_printf(dev, "MSI-X count : %d\n", msixc); 1279 } 1280 if (msix_disable > 0) 1281 msixc = 0; 1282 if (msi_disable > 0) 1283 msic = 0; 1284 /* Prefer MSI-X to MSI. */ 1285 if (msixc > 0) { 1286 msixc = RL_MSI_MESSAGES; 1287 rid = PCIR_BAR(4); 1288 sc->rl_res_pba = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1289 &rid, RF_ACTIVE); 1290 if (sc->rl_res_pba == NULL) { 1291 device_printf(sc->rl_dev, 1292 "could not allocate MSI-X PBA resource\n"); 1293 } 1294 if (sc->rl_res_pba != NULL && 1295 pci_alloc_msix(dev, &msixc) == 0) { 1296 if (msixc == RL_MSI_MESSAGES) { 1297 device_printf(dev, "Using %d MSI-X message\n", 1298 msixc); 1299 sc->rl_flags |= RL_FLAG_MSIX; 1300 } else 1301 pci_release_msi(dev); 1302 } 1303 if ((sc->rl_flags & RL_FLAG_MSIX) == 0) { 1304 if (sc->rl_res_pba != NULL) 1305 bus_release_resource(dev, SYS_RES_MEMORY, rid, 1306 sc->rl_res_pba); 1307 sc->rl_res_pba = NULL; 1308 msixc = 0; 1309 } 1310 } 1311 /* Prefer MSI to INTx. */ 1312 if (msixc == 0 && msic > 0) { 1313 msic = RL_MSI_MESSAGES; 1314 if (pci_alloc_msi(dev, &msic) == 0) { 1315 if (msic == RL_MSI_MESSAGES) { 1316 device_printf(dev, "Using %d MSI message\n", 1317 msic); 1318 sc->rl_flags |= RL_FLAG_MSI; 1319 /* Explicitly set MSI enable bit. */ 1320 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1321 cfg = CSR_READ_1(sc, RL_CFG2); 1322 cfg |= RL_CFG2_MSI; 1323 CSR_WRITE_1(sc, RL_CFG2, cfg); 1324 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1325 } else 1326 pci_release_msi(dev); 1327 } 1328 if ((sc->rl_flags & RL_FLAG_MSI) == 0) 1329 msic = 0; 1330 } 1331 1332 /* Allocate interrupt */ 1333 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) { 1334 rid = 0; 1335 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1336 RF_SHAREABLE | RF_ACTIVE); 1337 if (sc->rl_irq[0] == NULL) { 1338 device_printf(dev, "couldn't allocate IRQ resources\n"); 1339 error = ENXIO; 1340 goto fail; 1341 } 1342 } else { 1343 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1344 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1345 SYS_RES_IRQ, &rid, RF_ACTIVE); 1346 if (sc->rl_irq[i] == NULL) { 1347 device_printf(dev, 1348 "couldn't allocate IRQ resources for " 1349 "message %d\n", rid); 1350 error = ENXIO; 1351 goto fail; 1352 } 1353 } 1354 } 1355 1356 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1357 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1358 cfg = CSR_READ_1(sc, RL_CFG2); 1359 if ((cfg & RL_CFG2_MSI) != 0) { 1360 device_printf(dev, "turning off MSI enable bit.\n"); 1361 cfg &= ~RL_CFG2_MSI; 1362 CSR_WRITE_1(sc, RL_CFG2, cfg); 1363 } 1364 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1365 } 1366 1367 /* Disable ASPM L0S/L1 and CLKREQ. */ 1368 if (sc->rl_expcap != 0) { 1369 cap = pci_read_config(dev, sc->rl_expcap + 1370 PCIER_LINK_CAP, 2); 1371 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { 1372 ctl = pci_read_config(dev, sc->rl_expcap + 1373 PCIER_LINK_CTL, 2); 1374 if ((ctl & (PCIEM_LINK_CTL_ECPM | 1375 PCIEM_LINK_CTL_ASPMC))!= 0) { 1376 ctl &= ~(PCIEM_LINK_CTL_ECPM | 1377 PCIEM_LINK_CTL_ASPMC); 1378 pci_write_config(dev, sc->rl_expcap + 1379 PCIER_LINK_CTL, ctl, 2); 1380 device_printf(dev, "ASPM disabled\n"); 1381 } 1382 } else 1383 device_printf(dev, "no ASPM capability\n"); 1384 } 1385 1386 hw_rev = re_hwrevs; 1387 hwrev = CSR_READ_4(sc, RL_TXCFG); 1388 switch (hwrev & 0x70000000) { 1389 case 0x00000000: 1390 case 0x10000000: 1391 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000); 1392 hwrev &= (RL_TXCFG_HWREV | 0x80000000); 1393 break; 1394 default: 1395 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000); 1396 sc->rl_macrev = hwrev & 0x00700000; 1397 hwrev &= RL_TXCFG_HWREV; 1398 break; 1399 } 1400 device_printf(dev, "MAC rev. 0x%08x\n", sc->rl_macrev); 1401 while (hw_rev->rl_desc != NULL) { 1402 if (hw_rev->rl_rev == hwrev) { 1403 sc->rl_type = hw_rev->rl_type; 1404 sc->rl_hwrev = hw_rev; 1405 break; 1406 } 1407 hw_rev++; 1408 } 1409 if (hw_rev->rl_desc == NULL) { 1410 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev); 1411 error = ENXIO; 1412 goto fail; 1413 } 1414 1415 switch (hw_rev->rl_rev) { 1416 case RL_HWREV_8139CPLUS: 1417 sc->rl_flags |= RL_FLAG_FASTETHER | RL_FLAG_AUTOPAD; 1418 break; 1419 case RL_HWREV_8100E: 1420 case RL_HWREV_8101E: 1421 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_FASTETHER; 1422 break; 1423 case RL_HWREV_8102E: 1424 case RL_HWREV_8102EL: 1425 case RL_HWREV_8102EL_SPIN1: 1426 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1427 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | 1428 RL_FLAG_AUTOPAD; 1429 break; 1430 case RL_HWREV_8103E: 1431 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1432 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | 1433 RL_FLAG_AUTOPAD | RL_FLAG_MACSLEEP; 1434 break; 1435 case RL_HWREV_8401E: 1436 case RL_HWREV_8105E: 1437 case RL_HWREV_8105E_SPIN1: 1438 case RL_HWREV_8106E: 1439 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1440 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1441 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD; 1442 break; 1443 case RL_HWREV_8402: 1444 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1445 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1446 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | 1447 RL_FLAG_CMDSTOP_WAIT_TXQ; 1448 break; 1449 case RL_HWREV_8168B_SPIN1: 1450 case RL_HWREV_8168B_SPIN2: 1451 sc->rl_flags |= RL_FLAG_WOLRXENB; 1452 /* FALLTHROUGH */ 1453 case RL_HWREV_8168B_SPIN3: 1454 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT; 1455 break; 1456 case RL_HWREV_8168C_SPIN2: 1457 sc->rl_flags |= RL_FLAG_MACSLEEP; 1458 /* FALLTHROUGH */ 1459 case RL_HWREV_8168C: 1460 if (sc->rl_macrev == 0x00200000) 1461 sc->rl_flags |= RL_FLAG_MACSLEEP; 1462 /* FALLTHROUGH */ 1463 case RL_HWREV_8168CP: 1464 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1465 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1466 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK; 1467 break; 1468 case RL_HWREV_8168D: 1469 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1470 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1471 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1472 RL_FLAG_WOL_MANLINK; 1473 break; 1474 case RL_HWREV_8168DP: 1475 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1476 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_AUTOPAD | 1477 RL_FLAG_JUMBOV2 | RL_FLAG_WAIT_TXPOLL | RL_FLAG_WOL_MANLINK; 1478 break; 1479 case RL_HWREV_8168E: 1480 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1481 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1482 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1483 RL_FLAG_WOL_MANLINK; 1484 break; 1485 case RL_HWREV_8168E_VL: 1486 case RL_HWREV_8168F: 1487 sc->rl_flags |= RL_FLAG_EARLYOFF; 1488 /* FALLTHROUGH */ 1489 case RL_HWREV_8411: 1490 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1491 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1492 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1493 RL_FLAG_CMDSTOP_WAIT_TXQ | RL_FLAG_WOL_MANLINK; 1494 break; 1495 case RL_HWREV_8168EP: 1496 case RL_HWREV_8168G: 1497 case RL_HWREV_8411B: 1498 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1499 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1500 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1501 RL_FLAG_CMDSTOP_WAIT_TXQ | RL_FLAG_WOL_MANLINK | 1502 RL_FLAG_8168G_PLUS; 1503 break; 1504 case RL_HWREV_8168GU: 1505 case RL_HWREV_8168H: 1506 if (pci_get_device(dev) == RT_DEVICEID_8101E) { 1507 /* RTL8106E(US), RTL8107E */ 1508 sc->rl_flags |= RL_FLAG_FASTETHER; 1509 } else 1510 sc->rl_flags |= RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK; 1511 1512 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1513 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1514 RL_FLAG_AUTOPAD | RL_FLAG_CMDSTOP_WAIT_TXQ | 1515 RL_FLAG_8168G_PLUS; 1516 break; 1517 case RL_HWREV_8169_8110SB: 1518 case RL_HWREV_8169_8110SBL: 1519 case RL_HWREV_8169_8110SC: 1520 case RL_HWREV_8169_8110SCE: 1521 sc->rl_flags |= RL_FLAG_PHYWAKE; 1522 /* FALLTHROUGH */ 1523 case RL_HWREV_8169: 1524 case RL_HWREV_8169S: 1525 case RL_HWREV_8110S: 1526 sc->rl_flags |= RL_FLAG_MACRESET; 1527 break; 1528 default: 1529 break; 1530 } 1531 1532 if (sc->rl_hwrev->rl_rev == RL_HWREV_8139CPLUS) { 1533 sc->rl_cfg0 = RL_8139_CFG0; 1534 sc->rl_cfg1 = RL_8139_CFG1; 1535 sc->rl_cfg2 = 0; 1536 sc->rl_cfg3 = RL_8139_CFG3; 1537 sc->rl_cfg4 = RL_8139_CFG4; 1538 sc->rl_cfg5 = RL_8139_CFG5; 1539 } else { 1540 sc->rl_cfg0 = RL_CFG0; 1541 sc->rl_cfg1 = RL_CFG1; 1542 sc->rl_cfg2 = RL_CFG2; 1543 sc->rl_cfg3 = RL_CFG3; 1544 sc->rl_cfg4 = RL_CFG4; 1545 sc->rl_cfg5 = RL_CFG5; 1546 } 1547 1548 /* Reset the adapter. */ 1549 RL_LOCK(sc); 1550 re_reset(sc); 1551 RL_UNLOCK(sc); 1552 1553 /* Enable PME. */ 1554 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1555 cfg = CSR_READ_1(sc, sc->rl_cfg1); 1556 cfg |= RL_CFG1_PME; 1557 CSR_WRITE_1(sc, sc->rl_cfg1, cfg); 1558 cfg = CSR_READ_1(sc, sc->rl_cfg5); 1559 cfg &= RL_CFG5_PME_STS; 1560 CSR_WRITE_1(sc, sc->rl_cfg5, cfg); 1561 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1562 1563 if ((sc->rl_flags & RL_FLAG_PAR) != 0) { 1564 /* 1565 * XXX Should have a better way to extract station 1566 * address from EEPROM. 1567 */ 1568 for (i = 0; i < ETHER_ADDR_LEN; i++) 1569 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1570 } else { 1571 sc->rl_eewidth = RL_9356_ADDR_LEN; 1572 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1573 if (re_did != 0x8129) 1574 sc->rl_eewidth = RL_9346_ADDR_LEN; 1575 1576 /* 1577 * Get station address from the EEPROM. 1578 */ 1579 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1580 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1581 as[i] = le16toh(as[i]); 1582 bcopy(as, eaddr, ETHER_ADDR_LEN); 1583 } 1584 1585 if (sc->rl_type == RL_8169) { 1586 /* Set RX length mask and number of descriptors. */ 1587 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1588 sc->rl_txstart = RL_GTXSTART; 1589 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1590 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1591 } else { 1592 /* Set RX length mask and number of descriptors. */ 1593 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1594 sc->rl_txstart = RL_TXSTART; 1595 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1596 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1597 } 1598 1599 error = re_allocmem(dev, sc); 1600 if (error) 1601 goto fail; 1602 re_add_sysctls(sc); 1603 1604 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1605 if (ifp == NULL) { 1606 device_printf(dev, "can not if_alloc()\n"); 1607 error = ENOSPC; 1608 goto fail; 1609 } 1610 1611 /* Take controller out of deep sleep mode. */ 1612 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 1613 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 1614 CSR_WRITE_1(sc, RL_GPIO, 1615 CSR_READ_1(sc, RL_GPIO) | 0x01); 1616 else 1617 CSR_WRITE_1(sc, RL_GPIO, 1618 CSR_READ_1(sc, RL_GPIO) & ~0x01); 1619 } 1620 1621 /* Take PHY out of power down mode. */ 1622 if ((sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) { 1623 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80); 1624 if (hw_rev->rl_rev == RL_HWREV_8401E) 1625 CSR_WRITE_1(sc, 0xD1, CSR_READ_1(sc, 0xD1) & ~0x08); 1626 } 1627 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) { 1628 re_gmii_writereg(dev, 1, 0x1f, 0); 1629 re_gmii_writereg(dev, 1, 0x0e, 0); 1630 } 1631 1632 ifp->if_softc = sc; 1633 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1634 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1635 ifp->if_ioctl = re_ioctl; 1636 ifp->if_start = re_start; 1637 /* 1638 * RTL8168/8111C generates wrong IP checksummed frame if the 1639 * packet has IP options so disable TX checksum offloading. 1640 */ 1641 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168C || 1642 sc->rl_hwrev->rl_rev == RL_HWREV_8168C_SPIN2 || 1643 sc->rl_hwrev->rl_rev == RL_HWREV_8168CP) { 1644 ifp->if_hwassist = 0; 1645 ifp->if_capabilities = IFCAP_RXCSUM | IFCAP_TSO4; 1646 } else { 1647 ifp->if_hwassist = CSUM_IP | CSUM_TCP | CSUM_UDP; 1648 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 1649 } 1650 ifp->if_hwassist |= CSUM_TSO; 1651 ifp->if_capenable = ifp->if_capabilities; 1652 ifp->if_init = re_init; 1653 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1654 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1655 IFQ_SET_READY(&ifp->if_snd); 1656 1657 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1658 1659 #define RE_PHYAD_INTERNAL 0 1660 1661 /* Do MII setup. */ 1662 phy = RE_PHYAD_INTERNAL; 1663 if (sc->rl_type == RL_8169) 1664 phy = 1; 1665 capmask = BMSR_DEFCAPMASK; 1666 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0) 1667 capmask &= ~BMSR_EXTSTAT; 1668 error = mii_attach(dev, &sc->rl_miibus, ifp, re_ifmedia_upd, 1669 re_ifmedia_sts, capmask, phy, MII_OFFSET_ANY, MIIF_DOPAUSE); 1670 if (error != 0) { 1671 device_printf(dev, "attaching PHYs failed\n"); 1672 goto fail; 1673 } 1674 1675 /* 1676 * Call MI attach routine. 1677 */ 1678 ether_ifattach(ifp, eaddr); 1679 1680 /* VLAN capability setup */ 1681 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1682 if (ifp->if_capabilities & IFCAP_HWCSUM) 1683 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1684 /* Enable WOL if PM is supported. */ 1685 if (pci_find_cap(sc->rl_dev, PCIY_PMG, ®) == 0) 1686 ifp->if_capabilities |= IFCAP_WOL; 1687 ifp->if_capenable = ifp->if_capabilities; 1688 ifp->if_capenable &= ~(IFCAP_WOL_UCAST | IFCAP_WOL_MCAST); 1689 /* 1690 * Don't enable TSO by default. It is known to generate 1691 * corrupted TCP segments(bad TCP options) under certain 1692 * circumstances. 1693 */ 1694 ifp->if_hwassist &= ~CSUM_TSO; 1695 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO); 1696 #ifdef DEVICE_POLLING 1697 ifp->if_capabilities |= IFCAP_POLLING; 1698 #endif 1699 /* 1700 * Tell the upper layer(s) we support long frames. 1701 * Must appear after the call to ether_ifattach() because 1702 * ether_ifattach() sets ifi_hdrlen to the default value. 1703 */ 1704 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 1705 1706 #ifdef DEV_NETMAP 1707 re_netmap_attach(sc); 1708 #endif /* DEV_NETMAP */ 1709 1710 #ifdef RE_DIAG 1711 /* 1712 * Perform hardware diagnostic on the original RTL8169. 1713 * Some 32-bit cards were incorrectly wired and would 1714 * malfunction if plugged into a 64-bit slot. 1715 */ 1716 if (hwrev == RL_HWREV_8169) { 1717 error = re_diag(sc); 1718 if (error) { 1719 device_printf(dev, 1720 "attach aborted due to hardware diag failure\n"); 1721 ether_ifdetach(ifp); 1722 goto fail; 1723 } 1724 } 1725 #endif 1726 1727 #ifdef RE_TX_MODERATION 1728 intr_filter = 1; 1729 #endif 1730 /* Hook interrupt last to avoid having to lock softc */ 1731 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 && 1732 intr_filter == 0) { 1733 error = bus_setup_intr(dev, sc->rl_irq[0], 1734 INTR_TYPE_NET | INTR_MPSAFE, NULL, re_intr_msi, sc, 1735 &sc->rl_intrhand[0]); 1736 } else { 1737 error = bus_setup_intr(dev, sc->rl_irq[0], 1738 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1739 &sc->rl_intrhand[0]); 1740 } 1741 if (error) { 1742 device_printf(dev, "couldn't set up irq\n"); 1743 ether_ifdetach(ifp); 1744 goto fail; 1745 } 1746 1747 DEBUGNET_SET(ifp, re); 1748 1749 fail: 1750 if (error) 1751 re_detach(dev); 1752 1753 return (error); 1754 } 1755 1756 /* 1757 * Shutdown hardware and free up resources. This can be called any 1758 * time after the mutex has been initialized. It is called in both 1759 * the error case in attach and the normal detach case so it needs 1760 * to be careful about only freeing resources that have actually been 1761 * allocated. 1762 */ 1763 static int 1764 re_detach(device_t dev) 1765 { 1766 struct rl_softc *sc; 1767 struct ifnet *ifp; 1768 int i, rid; 1769 1770 sc = device_get_softc(dev); 1771 ifp = sc->rl_ifp; 1772 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1773 1774 /* These should only be active if attach succeeded */ 1775 if (device_is_attached(dev)) { 1776 #ifdef DEVICE_POLLING 1777 if (ifp->if_capenable & IFCAP_POLLING) 1778 ether_poll_deregister(ifp); 1779 #endif 1780 RL_LOCK(sc); 1781 #if 0 1782 sc->suspended = 1; 1783 #endif 1784 re_stop(sc); 1785 RL_UNLOCK(sc); 1786 callout_drain(&sc->rl_stat_callout); 1787 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1788 /* 1789 * Force off the IFF_UP flag here, in case someone 1790 * still had a BPF descriptor attached to this 1791 * interface. If they do, ether_ifdetach() will cause 1792 * the BPF code to try and clear the promisc mode 1793 * flag, which will bubble down to re_ioctl(), 1794 * which will try to call re_init() again. This will 1795 * turn the NIC back on and restart the MII ticker, 1796 * which will panic the system when the kernel tries 1797 * to invoke the re_tick() function that isn't there 1798 * anymore. 1799 */ 1800 ifp->if_flags &= ~IFF_UP; 1801 ether_ifdetach(ifp); 1802 } 1803 if (sc->rl_miibus) 1804 device_delete_child(dev, sc->rl_miibus); 1805 bus_generic_detach(dev); 1806 1807 /* 1808 * The rest is resource deallocation, so we should already be 1809 * stopped here. 1810 */ 1811 1812 if (sc->rl_intrhand[0] != NULL) { 1813 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]); 1814 sc->rl_intrhand[0] = NULL; 1815 } 1816 if (ifp != NULL) { 1817 #ifdef DEV_NETMAP 1818 netmap_detach(ifp); 1819 #endif /* DEV_NETMAP */ 1820 if_free(ifp); 1821 } 1822 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) 1823 rid = 0; 1824 else 1825 rid = 1; 1826 if (sc->rl_irq[0] != NULL) { 1827 bus_release_resource(dev, SYS_RES_IRQ, rid, sc->rl_irq[0]); 1828 sc->rl_irq[0] = NULL; 1829 } 1830 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0) 1831 pci_release_msi(dev); 1832 if (sc->rl_res_pba) { 1833 rid = PCIR_BAR(4); 1834 bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->rl_res_pba); 1835 } 1836 if (sc->rl_res) 1837 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, 1838 sc->rl_res); 1839 1840 /* Unload and free the RX DMA ring memory and map */ 1841 1842 if (sc->rl_ldata.rl_rx_list_tag) { 1843 if (sc->rl_ldata.rl_rx_list_addr) 1844 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1845 sc->rl_ldata.rl_rx_list_map); 1846 if (sc->rl_ldata.rl_rx_list) 1847 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1848 sc->rl_ldata.rl_rx_list, 1849 sc->rl_ldata.rl_rx_list_map); 1850 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1851 } 1852 1853 /* Unload and free the TX DMA ring memory and map */ 1854 1855 if (sc->rl_ldata.rl_tx_list_tag) { 1856 if (sc->rl_ldata.rl_tx_list_addr) 1857 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1858 sc->rl_ldata.rl_tx_list_map); 1859 if (sc->rl_ldata.rl_tx_list) 1860 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1861 sc->rl_ldata.rl_tx_list, 1862 sc->rl_ldata.rl_tx_list_map); 1863 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1864 } 1865 1866 /* Destroy all the RX and TX buffer maps */ 1867 1868 if (sc->rl_ldata.rl_tx_mtag) { 1869 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1870 if (sc->rl_ldata.rl_tx_desc[i].tx_dmamap) 1871 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1872 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1873 } 1874 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1875 } 1876 if (sc->rl_ldata.rl_rx_mtag) { 1877 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1878 if (sc->rl_ldata.rl_rx_desc[i].rx_dmamap) 1879 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1880 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1881 } 1882 if (sc->rl_ldata.rl_rx_sparemap) 1883 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1884 sc->rl_ldata.rl_rx_sparemap); 1885 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1886 } 1887 if (sc->rl_ldata.rl_jrx_mtag) { 1888 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1889 if (sc->rl_ldata.rl_jrx_desc[i].rx_dmamap) 1890 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag, 1891 sc->rl_ldata.rl_jrx_desc[i].rx_dmamap); 1892 } 1893 if (sc->rl_ldata.rl_jrx_sparemap) 1894 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag, 1895 sc->rl_ldata.rl_jrx_sparemap); 1896 bus_dma_tag_destroy(sc->rl_ldata.rl_jrx_mtag); 1897 } 1898 /* Unload and free the stats buffer and map */ 1899 1900 if (sc->rl_ldata.rl_stag) { 1901 if (sc->rl_ldata.rl_stats_addr) 1902 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1903 sc->rl_ldata.rl_smap); 1904 if (sc->rl_ldata.rl_stats) 1905 bus_dmamem_free(sc->rl_ldata.rl_stag, 1906 sc->rl_ldata.rl_stats, sc->rl_ldata.rl_smap); 1907 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1908 } 1909 1910 if (sc->rl_parent_tag) 1911 bus_dma_tag_destroy(sc->rl_parent_tag); 1912 1913 mtx_destroy(&sc->rl_mtx); 1914 1915 return (0); 1916 } 1917 1918 static __inline void 1919 re_discard_rxbuf(struct rl_softc *sc, int idx) 1920 { 1921 struct rl_desc *desc; 1922 struct rl_rxdesc *rxd; 1923 uint32_t cmdstat; 1924 1925 if (sc->rl_ifp->if_mtu > RL_MTU && 1926 (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) 1927 rxd = &sc->rl_ldata.rl_jrx_desc[idx]; 1928 else 1929 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1930 desc = &sc->rl_ldata.rl_rx_list[idx]; 1931 desc->rl_vlanctl = 0; 1932 cmdstat = rxd->rx_size; 1933 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1934 cmdstat |= RL_RDESC_CMD_EOR; 1935 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1936 } 1937 1938 static int 1939 re_newbuf(struct rl_softc *sc, int idx) 1940 { 1941 struct mbuf *m; 1942 struct rl_rxdesc *rxd; 1943 bus_dma_segment_t segs[1]; 1944 bus_dmamap_t map; 1945 struct rl_desc *desc; 1946 uint32_t cmdstat; 1947 int error, nsegs; 1948 1949 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1950 if (m == NULL) 1951 return (ENOBUFS); 1952 1953 m->m_len = m->m_pkthdr.len = MCLBYTES; 1954 #ifdef RE_FIXUP_RX 1955 /* 1956 * This is part of an evil trick to deal with non-x86 platforms. 1957 * The RealTek chip requires RX buffers to be aligned on 64-bit 1958 * boundaries, but that will hose non-x86 machines. To get around 1959 * this, we leave some empty space at the start of each buffer 1960 * and for non-x86 hosts, we copy the buffer back six bytes 1961 * to achieve word alignment. This is slightly more efficient 1962 * than allocating a new buffer, copying the contents, and 1963 * discarding the old buffer. 1964 */ 1965 m_adj(m, RE_ETHER_ALIGN); 1966 #endif 1967 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1968 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1969 if (error != 0) { 1970 m_freem(m); 1971 return (ENOBUFS); 1972 } 1973 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1974 1975 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1976 if (rxd->rx_m != NULL) { 1977 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1978 BUS_DMASYNC_POSTREAD); 1979 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1980 } 1981 1982 rxd->rx_m = m; 1983 map = rxd->rx_dmamap; 1984 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1985 rxd->rx_size = segs[0].ds_len; 1986 sc->rl_ldata.rl_rx_sparemap = map; 1987 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1988 BUS_DMASYNC_PREREAD); 1989 1990 desc = &sc->rl_ldata.rl_rx_list[idx]; 1991 desc->rl_vlanctl = 0; 1992 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1993 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1994 cmdstat = segs[0].ds_len; 1995 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1996 cmdstat |= RL_RDESC_CMD_EOR; 1997 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1998 1999 return (0); 2000 } 2001 2002 static int 2003 re_jumbo_newbuf(struct rl_softc *sc, int idx) 2004 { 2005 struct mbuf *m; 2006 struct rl_rxdesc *rxd; 2007 bus_dma_segment_t segs[1]; 2008 bus_dmamap_t map; 2009 struct rl_desc *desc; 2010 uint32_t cmdstat; 2011 int error, nsegs; 2012 2013 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 2014 if (m == NULL) 2015 return (ENOBUFS); 2016 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 2017 #ifdef RE_FIXUP_RX 2018 m_adj(m, RE_ETHER_ALIGN); 2019 #endif 2020 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_jrx_mtag, 2021 sc->rl_ldata.rl_jrx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 2022 if (error != 0) { 2023 m_freem(m); 2024 return (ENOBUFS); 2025 } 2026 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 2027 2028 rxd = &sc->rl_ldata.rl_jrx_desc[idx]; 2029 if (rxd->rx_m != NULL) { 2030 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap, 2031 BUS_DMASYNC_POSTREAD); 2032 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap); 2033 } 2034 2035 rxd->rx_m = m; 2036 map = rxd->rx_dmamap; 2037 rxd->rx_dmamap = sc->rl_ldata.rl_jrx_sparemap; 2038 rxd->rx_size = segs[0].ds_len; 2039 sc->rl_ldata.rl_jrx_sparemap = map; 2040 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap, 2041 BUS_DMASYNC_PREREAD); 2042 2043 desc = &sc->rl_ldata.rl_rx_list[idx]; 2044 desc->rl_vlanctl = 0; 2045 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 2046 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 2047 cmdstat = segs[0].ds_len; 2048 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 2049 cmdstat |= RL_RDESC_CMD_EOR; 2050 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 2051 2052 return (0); 2053 } 2054 2055 #ifdef RE_FIXUP_RX 2056 static __inline void 2057 re_fixup_rx(struct mbuf *m) 2058 { 2059 int i; 2060 uint16_t *src, *dst; 2061 2062 src = mtod(m, uint16_t *); 2063 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 2064 2065 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 2066 *dst++ = *src++; 2067 2068 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 2069 } 2070 #endif 2071 2072 static int 2073 re_tx_list_init(struct rl_softc *sc) 2074 { 2075 struct rl_desc *desc; 2076 int i; 2077 2078 RL_LOCK_ASSERT(sc); 2079 2080 bzero(sc->rl_ldata.rl_tx_list, 2081 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 2082 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 2083 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 2084 #ifdef DEV_NETMAP 2085 re_netmap_tx_init(sc); 2086 #endif /* DEV_NETMAP */ 2087 /* Set EOR. */ 2088 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 2089 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 2090 2091 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2092 sc->rl_ldata.rl_tx_list_map, 2093 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2094 2095 sc->rl_ldata.rl_tx_prodidx = 0; 2096 sc->rl_ldata.rl_tx_considx = 0; 2097 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 2098 2099 return (0); 2100 } 2101 2102 static int 2103 re_rx_list_init(struct rl_softc *sc) 2104 { 2105 int error, i; 2106 2107 bzero(sc->rl_ldata.rl_rx_list, 2108 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 2109 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2110 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 2111 if ((error = re_newbuf(sc, i)) != 0) 2112 return (error); 2113 } 2114 #ifdef DEV_NETMAP 2115 re_netmap_rx_init(sc); 2116 #endif /* DEV_NETMAP */ 2117 2118 /* Flush the RX descriptors */ 2119 2120 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2121 sc->rl_ldata.rl_rx_list_map, 2122 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2123 2124 sc->rl_ldata.rl_rx_prodidx = 0; 2125 sc->rl_head = sc->rl_tail = NULL; 2126 sc->rl_int_rx_act = 0; 2127 2128 return (0); 2129 } 2130 2131 static int 2132 re_jrx_list_init(struct rl_softc *sc) 2133 { 2134 int error, i; 2135 2136 bzero(sc->rl_ldata.rl_rx_list, 2137 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 2138 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2139 sc->rl_ldata.rl_jrx_desc[i].rx_m = NULL; 2140 if ((error = re_jumbo_newbuf(sc, i)) != 0) 2141 return (error); 2142 } 2143 2144 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2145 sc->rl_ldata.rl_rx_list_map, 2146 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2147 2148 sc->rl_ldata.rl_rx_prodidx = 0; 2149 sc->rl_head = sc->rl_tail = NULL; 2150 sc->rl_int_rx_act = 0; 2151 2152 return (0); 2153 } 2154 2155 /* 2156 * RX handler for C+ and 8169. For the gigE chips, we support 2157 * the reception of jumbo frames that have been fragmented 2158 * across multiple 2K mbuf cluster buffers. 2159 */ 2160 static int 2161 re_rxeof(struct rl_softc *sc, int *rx_npktsp) 2162 { 2163 struct mbuf *m; 2164 struct ifnet *ifp; 2165 int i, rxerr, total_len; 2166 struct rl_desc *cur_rx; 2167 u_int32_t rxstat, rxvlan; 2168 int jumbo, maxpkt = 16, rx_npkts = 0; 2169 2170 RL_LOCK_ASSERT(sc); 2171 2172 ifp = sc->rl_ifp; 2173 #ifdef DEV_NETMAP 2174 if (netmap_rx_irq(ifp, 0, &rx_npkts)) 2175 return 0; 2176 #endif /* DEV_NETMAP */ 2177 if (ifp->if_mtu > RL_MTU && (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) 2178 jumbo = 1; 2179 else 2180 jumbo = 0; 2181 2182 /* Invalidate the descriptor memory */ 2183 2184 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2185 sc->rl_ldata.rl_rx_list_map, 2186 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2187 2188 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 2189 i = RL_RX_DESC_NXT(sc, i)) { 2190 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2191 break; 2192 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 2193 rxstat = le32toh(cur_rx->rl_cmdstat); 2194 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 2195 break; 2196 total_len = rxstat & sc->rl_rxlenmask; 2197 rxvlan = le32toh(cur_rx->rl_vlanctl); 2198 if (jumbo != 0) 2199 m = sc->rl_ldata.rl_jrx_desc[i].rx_m; 2200 else 2201 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 2202 2203 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 2204 (rxstat & (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) != 2205 (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) { 2206 /* 2207 * RTL8168C or later controllers do not 2208 * support multi-fragment packet. 2209 */ 2210 re_discard_rxbuf(sc, i); 2211 continue; 2212 } else if ((rxstat & RL_RDESC_STAT_EOF) == 0) { 2213 if (re_newbuf(sc, i) != 0) { 2214 /* 2215 * If this is part of a multi-fragment packet, 2216 * discard all the pieces. 2217 */ 2218 if (sc->rl_head != NULL) { 2219 m_freem(sc->rl_head); 2220 sc->rl_head = sc->rl_tail = NULL; 2221 } 2222 re_discard_rxbuf(sc, i); 2223 continue; 2224 } 2225 m->m_len = RE_RX_DESC_BUFLEN; 2226 if (sc->rl_head == NULL) 2227 sc->rl_head = sc->rl_tail = m; 2228 else { 2229 m->m_flags &= ~M_PKTHDR; 2230 sc->rl_tail->m_next = m; 2231 sc->rl_tail = m; 2232 } 2233 continue; 2234 } 2235 2236 /* 2237 * NOTE: for the 8139C+, the frame length field 2238 * is always 12 bits in size, but for the gigE chips, 2239 * it is 13 bits (since the max RX frame length is 16K). 2240 * Unfortunately, all 32 bits in the status word 2241 * were already used, so to make room for the extra 2242 * length bit, RealTek took out the 'frame alignment 2243 * error' bit and shifted the other status bits 2244 * over one slot. The OWN, EOR, FS and LS bits are 2245 * still in the same places. We have already extracted 2246 * the frame length and checked the OWN bit, so rather 2247 * than using an alternate bit mapping, we shift the 2248 * status bits one space to the right so we can evaluate 2249 * them using the 8169 status as though it was in the 2250 * same format as that of the 8139C+. 2251 */ 2252 if (sc->rl_type == RL_8169) 2253 rxstat >>= 1; 2254 2255 /* 2256 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 2257 * set, but if CRC is clear, it will still be a valid frame. 2258 */ 2259 if ((rxstat & RL_RDESC_STAT_RXERRSUM) != 0) { 2260 rxerr = 1; 2261 if ((sc->rl_flags & RL_FLAG_JUMBOV2) == 0 && 2262 total_len > 8191 && 2263 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT) 2264 rxerr = 0; 2265 if (rxerr != 0) { 2266 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2267 /* 2268 * If this is part of a multi-fragment packet, 2269 * discard all the pieces. 2270 */ 2271 if (sc->rl_head != NULL) { 2272 m_freem(sc->rl_head); 2273 sc->rl_head = sc->rl_tail = NULL; 2274 } 2275 re_discard_rxbuf(sc, i); 2276 continue; 2277 } 2278 } 2279 2280 /* 2281 * If allocating a replacement mbuf fails, 2282 * reload the current one. 2283 */ 2284 if (jumbo != 0) 2285 rxerr = re_jumbo_newbuf(sc, i); 2286 else 2287 rxerr = re_newbuf(sc, i); 2288 if (rxerr != 0) { 2289 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2290 if (sc->rl_head != NULL) { 2291 m_freem(sc->rl_head); 2292 sc->rl_head = sc->rl_tail = NULL; 2293 } 2294 re_discard_rxbuf(sc, i); 2295 continue; 2296 } 2297 2298 if (sc->rl_head != NULL) { 2299 if (jumbo != 0) 2300 m->m_len = total_len; 2301 else { 2302 m->m_len = total_len % RE_RX_DESC_BUFLEN; 2303 if (m->m_len == 0) 2304 m->m_len = RE_RX_DESC_BUFLEN; 2305 } 2306 /* 2307 * Special case: if there's 4 bytes or less 2308 * in this buffer, the mbuf can be discarded: 2309 * the last 4 bytes is the CRC, which we don't 2310 * care about anyway. 2311 */ 2312 if (m->m_len <= ETHER_CRC_LEN) { 2313 sc->rl_tail->m_len -= 2314 (ETHER_CRC_LEN - m->m_len); 2315 m_freem(m); 2316 } else { 2317 m->m_len -= ETHER_CRC_LEN; 2318 m->m_flags &= ~M_PKTHDR; 2319 sc->rl_tail->m_next = m; 2320 } 2321 m = sc->rl_head; 2322 sc->rl_head = sc->rl_tail = NULL; 2323 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 2324 } else 2325 m->m_pkthdr.len = m->m_len = 2326 (total_len - ETHER_CRC_LEN); 2327 2328 #ifdef RE_FIXUP_RX 2329 re_fixup_rx(m); 2330 #endif 2331 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 2332 m->m_pkthdr.rcvif = ifp; 2333 2334 /* Do RX checksumming if enabled */ 2335 2336 if (ifp->if_capenable & IFCAP_RXCSUM) { 2337 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2338 /* Check IP header checksum */ 2339 if (rxstat & RL_RDESC_STAT_PROTOID) 2340 m->m_pkthdr.csum_flags |= 2341 CSUM_IP_CHECKED; 2342 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 2343 m->m_pkthdr.csum_flags |= 2344 CSUM_IP_VALID; 2345 2346 /* Check TCP/UDP checksum */ 2347 if ((RL_TCPPKT(rxstat) && 2348 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 2349 (RL_UDPPKT(rxstat) && 2350 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 2351 m->m_pkthdr.csum_flags |= 2352 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2353 m->m_pkthdr.csum_data = 0xffff; 2354 } 2355 } else { 2356 /* 2357 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP 2358 */ 2359 if ((rxstat & RL_RDESC_STAT_PROTOID) && 2360 (rxvlan & RL_RDESC_IPV4)) 2361 m->m_pkthdr.csum_flags |= 2362 CSUM_IP_CHECKED; 2363 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) && 2364 (rxvlan & RL_RDESC_IPV4)) 2365 m->m_pkthdr.csum_flags |= 2366 CSUM_IP_VALID; 2367 if (((rxstat & RL_RDESC_STAT_TCP) && 2368 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 2369 ((rxstat & RL_RDESC_STAT_UDP) && 2370 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 2371 m->m_pkthdr.csum_flags |= 2372 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2373 m->m_pkthdr.csum_data = 0xffff; 2374 } 2375 } 2376 } 2377 maxpkt--; 2378 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 2379 m->m_pkthdr.ether_vtag = 2380 bswap16((rxvlan & RL_RDESC_VLANCTL_DATA)); 2381 m->m_flags |= M_VLANTAG; 2382 } 2383 RL_UNLOCK(sc); 2384 (*ifp->if_input)(ifp, m); 2385 RL_LOCK(sc); 2386 rx_npkts++; 2387 } 2388 2389 /* Flush the RX DMA ring */ 2390 2391 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2392 sc->rl_ldata.rl_rx_list_map, 2393 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2394 2395 sc->rl_ldata.rl_rx_prodidx = i; 2396 2397 if (rx_npktsp != NULL) 2398 *rx_npktsp = rx_npkts; 2399 if (maxpkt) 2400 return (EAGAIN); 2401 2402 return (0); 2403 } 2404 2405 static void 2406 re_txeof(struct rl_softc *sc) 2407 { 2408 struct ifnet *ifp; 2409 struct rl_txdesc *txd; 2410 u_int32_t txstat; 2411 int cons; 2412 2413 cons = sc->rl_ldata.rl_tx_considx; 2414 if (cons == sc->rl_ldata.rl_tx_prodidx) 2415 return; 2416 2417 ifp = sc->rl_ifp; 2418 #ifdef DEV_NETMAP 2419 if (netmap_tx_irq(ifp, 0)) 2420 return; 2421 #endif /* DEV_NETMAP */ 2422 /* Invalidate the TX descriptor list */ 2423 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2424 sc->rl_ldata.rl_tx_list_map, 2425 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2426 2427 for (; cons != sc->rl_ldata.rl_tx_prodidx; 2428 cons = RL_TX_DESC_NXT(sc, cons)) { 2429 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 2430 if (txstat & RL_TDESC_STAT_OWN) 2431 break; 2432 /* 2433 * We only stash mbufs in the last descriptor 2434 * in a fragment chain, which also happens to 2435 * be the only place where the TX status bits 2436 * are valid. 2437 */ 2438 if (txstat & RL_TDESC_CMD_EOF) { 2439 txd = &sc->rl_ldata.rl_tx_desc[cons]; 2440 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2441 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2442 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2443 txd->tx_dmamap); 2444 KASSERT(txd->tx_m != NULL, 2445 ("%s: freeing NULL mbufs!", __func__)); 2446 m_freem(txd->tx_m); 2447 txd->tx_m = NULL; 2448 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 2449 RL_TDESC_STAT_COLCNT)) 2450 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 2451 if (txstat & RL_TDESC_STAT_TXERRSUM) 2452 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2453 else 2454 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 2455 } 2456 sc->rl_ldata.rl_tx_free++; 2457 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2458 } 2459 sc->rl_ldata.rl_tx_considx = cons; 2460 2461 /* No changes made to the TX ring, so no flush needed */ 2462 2463 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 2464 #ifdef RE_TX_MODERATION 2465 /* 2466 * If not all descriptors have been reaped yet, reload 2467 * the timer so that we will eventually get another 2468 * interrupt that will cause us to re-enter this routine. 2469 * This is done in case the transmitter has gone idle. 2470 */ 2471 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2472 #endif 2473 } else 2474 sc->rl_watchdog_timer = 0; 2475 } 2476 2477 static void 2478 re_tick(void *xsc) 2479 { 2480 struct rl_softc *sc; 2481 struct mii_data *mii; 2482 2483 sc = xsc; 2484 2485 RL_LOCK_ASSERT(sc); 2486 2487 mii = device_get_softc(sc->rl_miibus); 2488 mii_tick(mii); 2489 if ((sc->rl_flags & RL_FLAG_LINK) == 0) 2490 re_miibus_statchg(sc->rl_dev); 2491 /* 2492 * Reclaim transmitted frames here. Technically it is not 2493 * necessary to do here but it ensures periodic reclamation 2494 * regardless of Tx completion interrupt which seems to be 2495 * lost on PCIe based controllers under certain situations. 2496 */ 2497 re_txeof(sc); 2498 re_watchdog(sc); 2499 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2500 } 2501 2502 #ifdef DEVICE_POLLING 2503 static int 2504 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2505 { 2506 struct rl_softc *sc = ifp->if_softc; 2507 int rx_npkts = 0; 2508 2509 RL_LOCK(sc); 2510 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2511 rx_npkts = re_poll_locked(ifp, cmd, count); 2512 RL_UNLOCK(sc); 2513 return (rx_npkts); 2514 } 2515 2516 static int 2517 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2518 { 2519 struct rl_softc *sc = ifp->if_softc; 2520 int rx_npkts; 2521 2522 RL_LOCK_ASSERT(sc); 2523 2524 sc->rxcycles = count; 2525 re_rxeof(sc, &rx_npkts); 2526 re_txeof(sc); 2527 2528 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2529 re_start_locked(ifp); 2530 2531 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2532 u_int16_t status; 2533 2534 status = CSR_READ_2(sc, RL_ISR); 2535 if (status == 0xffff) 2536 return (rx_npkts); 2537 if (status) 2538 CSR_WRITE_2(sc, RL_ISR, status); 2539 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2540 (sc->rl_flags & RL_FLAG_PCIE)) 2541 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2542 2543 /* 2544 * XXX check behaviour on receiver stalls. 2545 */ 2546 2547 if (status & RL_ISR_SYSTEM_ERR) { 2548 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2549 re_init_locked(sc); 2550 } 2551 } 2552 return (rx_npkts); 2553 } 2554 #endif /* DEVICE_POLLING */ 2555 2556 static int 2557 re_intr(void *arg) 2558 { 2559 struct rl_softc *sc; 2560 uint16_t status; 2561 2562 sc = arg; 2563 2564 status = CSR_READ_2(sc, RL_ISR); 2565 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2566 return (FILTER_STRAY); 2567 CSR_WRITE_2(sc, RL_IMR, 0); 2568 2569 taskqueue_enqueue(taskqueue_fast, &sc->rl_inttask); 2570 2571 return (FILTER_HANDLED); 2572 } 2573 2574 static void 2575 re_int_task(void *arg, int npending) 2576 { 2577 struct rl_softc *sc; 2578 struct ifnet *ifp; 2579 u_int16_t status; 2580 int rval = 0; 2581 2582 sc = arg; 2583 ifp = sc->rl_ifp; 2584 2585 RL_LOCK(sc); 2586 2587 status = CSR_READ_2(sc, RL_ISR); 2588 CSR_WRITE_2(sc, RL_ISR, status); 2589 2590 if (sc->suspended || 2591 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2592 RL_UNLOCK(sc); 2593 return; 2594 } 2595 2596 #ifdef DEVICE_POLLING 2597 if (ifp->if_capenable & IFCAP_POLLING) { 2598 RL_UNLOCK(sc); 2599 return; 2600 } 2601 #endif 2602 2603 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2604 rval = re_rxeof(sc, NULL); 2605 2606 /* 2607 * Some chips will ignore a second TX request issued 2608 * while an existing transmission is in progress. If 2609 * the transmitter goes idle but there are still 2610 * packets waiting to be sent, we need to restart the 2611 * channel here to flush them out. This only seems to 2612 * be required with the PCIe devices. 2613 */ 2614 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2615 (sc->rl_flags & RL_FLAG_PCIE)) 2616 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2617 if (status & ( 2618 #ifdef RE_TX_MODERATION 2619 RL_ISR_TIMEOUT_EXPIRED| 2620 #else 2621 RL_ISR_TX_OK| 2622 #endif 2623 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2624 re_txeof(sc); 2625 2626 if (status & RL_ISR_SYSTEM_ERR) { 2627 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2628 re_init_locked(sc); 2629 } 2630 2631 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2632 re_start_locked(ifp); 2633 2634 RL_UNLOCK(sc); 2635 2636 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2637 taskqueue_enqueue(taskqueue_fast, &sc->rl_inttask); 2638 return; 2639 } 2640 2641 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2642 } 2643 2644 static void 2645 re_intr_msi(void *xsc) 2646 { 2647 struct rl_softc *sc; 2648 struct ifnet *ifp; 2649 uint16_t intrs, status; 2650 2651 sc = xsc; 2652 RL_LOCK(sc); 2653 2654 ifp = sc->rl_ifp; 2655 #ifdef DEVICE_POLLING 2656 if (ifp->if_capenable & IFCAP_POLLING) { 2657 RL_UNLOCK(sc); 2658 return; 2659 } 2660 #endif 2661 /* Disable interrupts. */ 2662 CSR_WRITE_2(sc, RL_IMR, 0); 2663 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2664 RL_UNLOCK(sc); 2665 return; 2666 } 2667 2668 intrs = RL_INTRS_CPLUS; 2669 status = CSR_READ_2(sc, RL_ISR); 2670 CSR_WRITE_2(sc, RL_ISR, status); 2671 if (sc->rl_int_rx_act > 0) { 2672 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW | 2673 RL_ISR_RX_OVERRUN); 2674 status &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW | 2675 RL_ISR_RX_OVERRUN); 2676 } 2677 2678 if (status & (RL_ISR_TIMEOUT_EXPIRED | RL_ISR_RX_OK | RL_ISR_RX_ERR | 2679 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) { 2680 re_rxeof(sc, NULL); 2681 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2682 if (sc->rl_int_rx_mod != 0 && 2683 (status & (RL_ISR_RX_OK | RL_ISR_RX_ERR | 2684 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) != 0) { 2685 /* Rearm one-shot timer. */ 2686 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2687 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | 2688 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN); 2689 sc->rl_int_rx_act = 1; 2690 } else { 2691 intrs |= RL_ISR_RX_OK | RL_ISR_RX_ERR | 2692 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN; 2693 sc->rl_int_rx_act = 0; 2694 } 2695 } 2696 } 2697 2698 /* 2699 * Some chips will ignore a second TX request issued 2700 * while an existing transmission is in progress. If 2701 * the transmitter goes idle but there are still 2702 * packets waiting to be sent, we need to restart the 2703 * channel here to flush them out. This only seems to 2704 * be required with the PCIe devices. 2705 */ 2706 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2707 (sc->rl_flags & RL_FLAG_PCIE)) 2708 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2709 if (status & (RL_ISR_TX_OK | RL_ISR_TX_ERR | RL_ISR_TX_DESC_UNAVAIL)) 2710 re_txeof(sc); 2711 2712 if (status & RL_ISR_SYSTEM_ERR) { 2713 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2714 re_init_locked(sc); 2715 } 2716 2717 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2718 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2719 re_start_locked(ifp); 2720 CSR_WRITE_2(sc, RL_IMR, intrs); 2721 } 2722 RL_UNLOCK(sc); 2723 } 2724 2725 static int 2726 re_encap(struct rl_softc *sc, struct mbuf **m_head) 2727 { 2728 struct rl_txdesc *txd, *txd_last; 2729 bus_dma_segment_t segs[RL_NTXSEGS]; 2730 bus_dmamap_t map; 2731 struct mbuf *m_new; 2732 struct rl_desc *desc; 2733 int nsegs, prod; 2734 int i, error, ei, si; 2735 int padlen; 2736 uint32_t cmdstat, csum_flags, vlanctl; 2737 2738 RL_LOCK_ASSERT(sc); 2739 M_ASSERTPKTHDR((*m_head)); 2740 2741 /* 2742 * With some of the RealTek chips, using the checksum offload 2743 * support in conjunction with the autopadding feature results 2744 * in the transmission of corrupt frames. For example, if we 2745 * need to send a really small IP fragment that's less than 60 2746 * bytes in size, and IP header checksumming is enabled, the 2747 * resulting ethernet frame that appears on the wire will 2748 * have garbled payload. To work around this, if TX IP checksum 2749 * offload is enabled, we always manually pad short frames out 2750 * to the minimum ethernet frame size. 2751 */ 2752 if ((sc->rl_flags & RL_FLAG_AUTOPAD) == 0 && 2753 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN && 2754 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) { 2755 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2756 if (M_WRITABLE(*m_head) == 0) { 2757 /* Get a writable copy. */ 2758 m_new = m_dup(*m_head, M_NOWAIT); 2759 m_freem(*m_head); 2760 if (m_new == NULL) { 2761 *m_head = NULL; 2762 return (ENOBUFS); 2763 } 2764 *m_head = m_new; 2765 } 2766 if ((*m_head)->m_next != NULL || 2767 M_TRAILINGSPACE(*m_head) < padlen) { 2768 m_new = m_defrag(*m_head, M_NOWAIT); 2769 if (m_new == NULL) { 2770 m_freem(*m_head); 2771 *m_head = NULL; 2772 return (ENOBUFS); 2773 } 2774 } else 2775 m_new = *m_head; 2776 2777 /* 2778 * Manually pad short frames, and zero the pad space 2779 * to avoid leaking data. 2780 */ 2781 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2782 m_new->m_pkthdr.len += padlen; 2783 m_new->m_len = m_new->m_pkthdr.len; 2784 *m_head = m_new; 2785 } 2786 2787 prod = sc->rl_ldata.rl_tx_prodidx; 2788 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2789 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2790 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2791 if (error == EFBIG) { 2792 m_new = m_collapse(*m_head, M_NOWAIT, RL_NTXSEGS); 2793 if (m_new == NULL) { 2794 m_freem(*m_head); 2795 *m_head = NULL; 2796 return (ENOBUFS); 2797 } 2798 *m_head = m_new; 2799 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2800 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2801 if (error != 0) { 2802 m_freem(*m_head); 2803 *m_head = NULL; 2804 return (error); 2805 } 2806 } else if (error != 0) 2807 return (error); 2808 if (nsegs == 0) { 2809 m_freem(*m_head); 2810 *m_head = NULL; 2811 return (EIO); 2812 } 2813 2814 /* Check for number of available descriptors. */ 2815 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2816 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2817 return (ENOBUFS); 2818 } 2819 2820 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2821 BUS_DMASYNC_PREWRITE); 2822 2823 /* 2824 * Set up checksum offload. Note: checksum offload bits must 2825 * appear in all descriptors of a multi-descriptor transmit 2826 * attempt. This is according to testing done with an 8169 2827 * chip. This is a requirement. 2828 */ 2829 vlanctl = 0; 2830 csum_flags = 0; 2831 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2832 if ((sc->rl_flags & RL_FLAG_DESCV2) != 0) { 2833 csum_flags |= RL_TDESC_CMD_LGSEND; 2834 vlanctl |= ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2835 RL_TDESC_CMD_MSSVALV2_SHIFT); 2836 } else { 2837 csum_flags |= RL_TDESC_CMD_LGSEND | 2838 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2839 RL_TDESC_CMD_MSSVAL_SHIFT); 2840 } 2841 } else { 2842 /* 2843 * Unconditionally enable IP checksum if TCP or UDP 2844 * checksum is required. Otherwise, TCP/UDP checksum 2845 * doesn't make effects. 2846 */ 2847 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) { 2848 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2849 csum_flags |= RL_TDESC_CMD_IPCSUM; 2850 if (((*m_head)->m_pkthdr.csum_flags & 2851 CSUM_TCP) != 0) 2852 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2853 if (((*m_head)->m_pkthdr.csum_flags & 2854 CSUM_UDP) != 0) 2855 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2856 } else { 2857 vlanctl |= RL_TDESC_CMD_IPCSUMV2; 2858 if (((*m_head)->m_pkthdr.csum_flags & 2859 CSUM_TCP) != 0) 2860 vlanctl |= RL_TDESC_CMD_TCPCSUMV2; 2861 if (((*m_head)->m_pkthdr.csum_flags & 2862 CSUM_UDP) != 0) 2863 vlanctl |= RL_TDESC_CMD_UDPCSUMV2; 2864 } 2865 } 2866 } 2867 2868 /* 2869 * Set up hardware VLAN tagging. Note: vlan tag info must 2870 * appear in all descriptors of a multi-descriptor 2871 * transmission attempt. 2872 */ 2873 if ((*m_head)->m_flags & M_VLANTAG) 2874 vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) | 2875 RL_TDESC_VLANCTL_TAG; 2876 2877 si = prod; 2878 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2879 desc = &sc->rl_ldata.rl_tx_list[prod]; 2880 desc->rl_vlanctl = htole32(vlanctl); 2881 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2882 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2883 cmdstat = segs[i].ds_len; 2884 if (i != 0) 2885 cmdstat |= RL_TDESC_CMD_OWN; 2886 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2887 cmdstat |= RL_TDESC_CMD_EOR; 2888 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2889 sc->rl_ldata.rl_tx_free--; 2890 } 2891 /* Update producer index. */ 2892 sc->rl_ldata.rl_tx_prodidx = prod; 2893 2894 /* Set EOF on the last descriptor. */ 2895 ei = RL_TX_DESC_PRV(sc, prod); 2896 desc = &sc->rl_ldata.rl_tx_list[ei]; 2897 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2898 2899 desc = &sc->rl_ldata.rl_tx_list[si]; 2900 /* Set SOF and transfer ownership of packet to the chip. */ 2901 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2902 2903 /* 2904 * Insure that the map for this transmission 2905 * is placed at the array index of the last descriptor 2906 * in this chain. (Swap last and first dmamaps.) 2907 */ 2908 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2909 map = txd->tx_dmamap; 2910 txd->tx_dmamap = txd_last->tx_dmamap; 2911 txd_last->tx_dmamap = map; 2912 txd_last->tx_m = *m_head; 2913 2914 return (0); 2915 } 2916 2917 static void 2918 re_start(struct ifnet *ifp) 2919 { 2920 struct rl_softc *sc; 2921 2922 sc = ifp->if_softc; 2923 RL_LOCK(sc); 2924 re_start_locked(ifp); 2925 RL_UNLOCK(sc); 2926 } 2927 2928 /* 2929 * Main transmit routine for C+ and gigE NICs. 2930 */ 2931 static void 2932 re_start_locked(struct ifnet *ifp) 2933 { 2934 struct rl_softc *sc; 2935 struct mbuf *m_head; 2936 int queued; 2937 2938 sc = ifp->if_softc; 2939 2940 #ifdef DEV_NETMAP 2941 /* XXX is this necessary ? */ 2942 if (ifp->if_capenable & IFCAP_NETMAP) { 2943 struct netmap_kring *kring = NA(ifp)->tx_rings[0]; 2944 if (sc->rl_ldata.rl_tx_prodidx != kring->nr_hwcur) { 2945 /* kick the tx unit */ 2946 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2947 #ifdef RE_TX_MODERATION 2948 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2949 #endif 2950 sc->rl_watchdog_timer = 5; 2951 } 2952 return; 2953 } 2954 #endif /* DEV_NETMAP */ 2955 2956 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2957 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) 2958 return; 2959 2960 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2961 sc->rl_ldata.rl_tx_free > 1;) { 2962 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2963 if (m_head == NULL) 2964 break; 2965 2966 if (re_encap(sc, &m_head) != 0) { 2967 if (m_head == NULL) 2968 break; 2969 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2970 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2971 break; 2972 } 2973 2974 /* 2975 * If there's a BPF listener, bounce a copy of this frame 2976 * to him. 2977 */ 2978 ETHER_BPF_MTAP(ifp, m_head); 2979 2980 queued++; 2981 } 2982 2983 if (queued == 0) { 2984 #ifdef RE_TX_MODERATION 2985 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2986 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2987 #endif 2988 return; 2989 } 2990 2991 re_start_tx(sc); 2992 } 2993 2994 static void 2995 re_start_tx(struct rl_softc *sc) 2996 { 2997 2998 /* Flush the TX descriptors */ 2999 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 3000 sc->rl_ldata.rl_tx_list_map, 3001 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 3002 3003 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 3004 3005 #ifdef RE_TX_MODERATION 3006 /* 3007 * Use the countdown timer for interrupt moderation. 3008 * 'TX done' interrupts are disabled. Instead, we reset the 3009 * countdown timer, which will begin counting until it hits 3010 * the value in the TIMERINT register, and then trigger an 3011 * interrupt. Each time we write to the TIMERCNT register, 3012 * the timer count is reset to 0. 3013 */ 3014 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 3015 #endif 3016 3017 /* 3018 * Set a timeout in case the chip goes out to lunch. 3019 */ 3020 sc->rl_watchdog_timer = 5; 3021 } 3022 3023 static void 3024 re_set_jumbo(struct rl_softc *sc, int jumbo) 3025 { 3026 3027 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168E_VL) { 3028 pci_set_max_read_req(sc->rl_dev, 4096); 3029 return; 3030 } 3031 3032 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 3033 if (jumbo != 0) { 3034 CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) | 3035 RL_CFG3_JUMBO_EN0); 3036 switch (sc->rl_hwrev->rl_rev) { 3037 case RL_HWREV_8168DP: 3038 break; 3039 case RL_HWREV_8168E: 3040 CSR_WRITE_1(sc, sc->rl_cfg4, 3041 CSR_READ_1(sc, sc->rl_cfg4) | 0x01); 3042 break; 3043 default: 3044 CSR_WRITE_1(sc, sc->rl_cfg4, 3045 CSR_READ_1(sc, sc->rl_cfg4) | RL_CFG4_JUMBO_EN1); 3046 } 3047 } else { 3048 CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) & 3049 ~RL_CFG3_JUMBO_EN0); 3050 switch (sc->rl_hwrev->rl_rev) { 3051 case RL_HWREV_8168DP: 3052 break; 3053 case RL_HWREV_8168E: 3054 CSR_WRITE_1(sc, sc->rl_cfg4, 3055 CSR_READ_1(sc, sc->rl_cfg4) & ~0x01); 3056 break; 3057 default: 3058 CSR_WRITE_1(sc, sc->rl_cfg4, 3059 CSR_READ_1(sc, sc->rl_cfg4) & ~RL_CFG4_JUMBO_EN1); 3060 } 3061 } 3062 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3063 3064 switch (sc->rl_hwrev->rl_rev) { 3065 case RL_HWREV_8168DP: 3066 pci_set_max_read_req(sc->rl_dev, 4096); 3067 break; 3068 default: 3069 if (jumbo != 0) 3070 pci_set_max_read_req(sc->rl_dev, 512); 3071 else 3072 pci_set_max_read_req(sc->rl_dev, 4096); 3073 } 3074 } 3075 3076 static void 3077 re_init(void *xsc) 3078 { 3079 struct rl_softc *sc = xsc; 3080 3081 RL_LOCK(sc); 3082 re_init_locked(sc); 3083 RL_UNLOCK(sc); 3084 } 3085 3086 static void 3087 re_init_locked(struct rl_softc *sc) 3088 { 3089 struct ifnet *ifp = sc->rl_ifp; 3090 struct mii_data *mii; 3091 uint32_t reg; 3092 uint16_t cfg; 3093 union { 3094 uint32_t align_dummy; 3095 u_char eaddr[ETHER_ADDR_LEN]; 3096 } eaddr; 3097 3098 RL_LOCK_ASSERT(sc); 3099 3100 mii = device_get_softc(sc->rl_miibus); 3101 3102 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3103 return; 3104 3105 /* 3106 * Cancel pending I/O and free all RX/TX buffers. 3107 */ 3108 re_stop(sc); 3109 3110 /* Put controller into known state. */ 3111 re_reset(sc); 3112 3113 /* 3114 * For C+ mode, initialize the RX descriptors and mbufs. 3115 */ 3116 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3117 if (ifp->if_mtu > RL_MTU) { 3118 if (re_jrx_list_init(sc) != 0) { 3119 device_printf(sc->rl_dev, 3120 "no memory for jumbo RX buffers\n"); 3121 re_stop(sc); 3122 return; 3123 } 3124 /* Disable checksum offloading for jumbo frames. */ 3125 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_TSO4); 3126 ifp->if_hwassist &= ~(RE_CSUM_FEATURES | CSUM_TSO); 3127 } else { 3128 if (re_rx_list_init(sc) != 0) { 3129 device_printf(sc->rl_dev, 3130 "no memory for RX buffers\n"); 3131 re_stop(sc); 3132 return; 3133 } 3134 } 3135 re_set_jumbo(sc, ifp->if_mtu > RL_MTU); 3136 } else { 3137 if (re_rx_list_init(sc) != 0) { 3138 device_printf(sc->rl_dev, "no memory for RX buffers\n"); 3139 re_stop(sc); 3140 return; 3141 } 3142 if ((sc->rl_flags & RL_FLAG_PCIE) != 0 && 3143 pci_get_device(sc->rl_dev) != RT_DEVICEID_8101E) { 3144 if (ifp->if_mtu > RL_MTU) 3145 pci_set_max_read_req(sc->rl_dev, 512); 3146 else 3147 pci_set_max_read_req(sc->rl_dev, 4096); 3148 } 3149 } 3150 re_tx_list_init(sc); 3151 3152 /* 3153 * Enable C+ RX and TX mode, as well as VLAN stripping and 3154 * RX checksum offload. We must configure the C+ register 3155 * before all others. 3156 */ 3157 cfg = RL_CPLUSCMD_PCI_MRW; 3158 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 3159 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 3160 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3161 cfg |= RL_CPLUSCMD_VLANSTRIP; 3162 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) { 3163 cfg |= RL_CPLUSCMD_MACSTAT_DIS; 3164 /* XXX magic. */ 3165 cfg |= 0x0001; 3166 } else 3167 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB; 3168 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg); 3169 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SC || 3170 sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) { 3171 reg = 0x000fff00; 3172 if ((CSR_READ_1(sc, sc->rl_cfg2) & RL_CFG2_PCI66MHZ) != 0) 3173 reg |= 0x000000ff; 3174 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) 3175 reg |= 0x00f00000; 3176 CSR_WRITE_4(sc, 0x7c, reg); 3177 /* Disable interrupt mitigation. */ 3178 CSR_WRITE_2(sc, 0xe2, 0); 3179 } 3180 /* 3181 * Disable TSO if interface MTU size is greater than MSS 3182 * allowed in controller. 3183 */ 3184 if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) { 3185 ifp->if_capenable &= ~IFCAP_TSO4; 3186 ifp->if_hwassist &= ~CSUM_TSO; 3187 } 3188 3189 /* 3190 * Init our MAC address. Even though the chipset 3191 * documentation doesn't mention it, we need to enter "Config 3192 * register write enable" mode to modify the ID registers. 3193 */ 3194 /* Copy MAC address on stack to align. */ 3195 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 3196 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 3197 CSR_WRITE_4(sc, RL_IDR0, 3198 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 3199 CSR_WRITE_4(sc, RL_IDR4, 3200 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 3201 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3202 3203 /* 3204 * Load the addresses of the RX and TX lists into the chip. 3205 */ 3206 3207 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 3208 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 3209 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 3210 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 3211 3212 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 3213 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 3214 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 3215 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 3216 3217 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0) { 3218 /* Disable RXDV gate. */ 3219 CSR_WRITE_4(sc, RL_MISC, CSR_READ_4(sc, RL_MISC) & 3220 ~0x00080000); 3221 } 3222 3223 /* 3224 * Enable transmit and receive for pre-RTL8168G controllers. 3225 * RX/TX MACs should be enabled before RX/TX configuration. 3226 */ 3227 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) == 0) 3228 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB | RL_CMD_RX_ENB); 3229 3230 /* 3231 * Set the initial TX configuration. 3232 */ 3233 if (sc->rl_testmode) { 3234 if (sc->rl_type == RL_8169) 3235 CSR_WRITE_4(sc, RL_TXCFG, 3236 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 3237 else 3238 CSR_WRITE_4(sc, RL_TXCFG, 3239 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 3240 } else 3241 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 3242 3243 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 3244 3245 /* 3246 * Set the initial RX configuration. 3247 */ 3248 re_set_rxmode(sc); 3249 3250 /* Configure interrupt moderation. */ 3251 if (sc->rl_type == RL_8169) { 3252 /* Magic from vendor. */ 3253 CSR_WRITE_2(sc, RL_INTRMOD, 0x5100); 3254 } 3255 3256 /* 3257 * Enable transmit and receive for RTL8168G and later controllers. 3258 * RX/TX MACs should be enabled after RX/TX configuration. 3259 */ 3260 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0) 3261 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB | RL_CMD_RX_ENB); 3262 3263 #ifdef DEVICE_POLLING 3264 /* 3265 * Disable interrupts if we are polling. 3266 */ 3267 if (ifp->if_capenable & IFCAP_POLLING) 3268 CSR_WRITE_2(sc, RL_IMR, 0); 3269 else /* otherwise ... */ 3270 #endif 3271 3272 /* 3273 * Enable interrupts. 3274 */ 3275 if (sc->rl_testmode) 3276 CSR_WRITE_2(sc, RL_IMR, 0); 3277 else 3278 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 3279 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 3280 3281 /* Set initial TX threshold */ 3282 sc->rl_txthresh = RL_TX_THRESH_INIT; 3283 3284 /* Start RX/TX process. */ 3285 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 3286 3287 /* 3288 * Initialize the timer interrupt register so that 3289 * a timer interrupt will be generated once the timer 3290 * reaches a certain number of ticks. The timer is 3291 * reloaded on each transmit. 3292 */ 3293 #ifdef RE_TX_MODERATION 3294 /* 3295 * Use timer interrupt register to moderate TX interrupt 3296 * moderation, which dramatically improves TX frame rate. 3297 */ 3298 if (sc->rl_type == RL_8169) 3299 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 3300 else 3301 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 3302 #else 3303 /* 3304 * Use timer interrupt register to moderate RX interrupt 3305 * moderation. 3306 */ 3307 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 && 3308 intr_filter == 0) { 3309 if (sc->rl_type == RL_8169) 3310 CSR_WRITE_4(sc, RL_TIMERINT_8169, 3311 RL_USECS(sc->rl_int_rx_mod)); 3312 } else { 3313 if (sc->rl_type == RL_8169) 3314 CSR_WRITE_4(sc, RL_TIMERINT_8169, RL_USECS(0)); 3315 } 3316 #endif 3317 3318 /* 3319 * For 8169 gigE NICs, set the max allowed RX packet 3320 * size so we can receive jumbo frames. 3321 */ 3322 if (sc->rl_type == RL_8169) { 3323 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3324 /* 3325 * For controllers that use new jumbo frame scheme, 3326 * set maximum size of jumbo frame depending on 3327 * controller revisions. 3328 */ 3329 if (ifp->if_mtu > RL_MTU) 3330 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 3331 sc->rl_hwrev->rl_max_mtu + 3332 ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN + 3333 ETHER_CRC_LEN); 3334 else 3335 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 3336 RE_RX_DESC_BUFLEN); 3337 } else if ((sc->rl_flags & RL_FLAG_PCIE) != 0 && 3338 sc->rl_hwrev->rl_max_mtu == RL_MTU) { 3339 /* RTL810x has no jumbo frame support. */ 3340 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, RE_RX_DESC_BUFLEN); 3341 } else 3342 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 3343 } 3344 3345 if (sc->rl_testmode) 3346 return; 3347 3348 CSR_WRITE_1(sc, sc->rl_cfg1, CSR_READ_1(sc, sc->rl_cfg1) | 3349 RL_CFG1_DRVLOAD); 3350 3351 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3352 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3353 3354 sc->rl_flags &= ~RL_FLAG_LINK; 3355 mii_mediachg(mii); 3356 3357 sc->rl_watchdog_timer = 0; 3358 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 3359 } 3360 3361 /* 3362 * Set media options. 3363 */ 3364 static int 3365 re_ifmedia_upd(struct ifnet *ifp) 3366 { 3367 struct rl_softc *sc; 3368 struct mii_data *mii; 3369 int error; 3370 3371 sc = ifp->if_softc; 3372 mii = device_get_softc(sc->rl_miibus); 3373 RL_LOCK(sc); 3374 error = mii_mediachg(mii); 3375 RL_UNLOCK(sc); 3376 3377 return (error); 3378 } 3379 3380 /* 3381 * Report current media status. 3382 */ 3383 static void 3384 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3385 { 3386 struct rl_softc *sc; 3387 struct mii_data *mii; 3388 3389 sc = ifp->if_softc; 3390 mii = device_get_softc(sc->rl_miibus); 3391 3392 RL_LOCK(sc); 3393 mii_pollstat(mii); 3394 ifmr->ifm_active = mii->mii_media_active; 3395 ifmr->ifm_status = mii->mii_media_status; 3396 RL_UNLOCK(sc); 3397 } 3398 3399 static int 3400 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3401 { 3402 struct rl_softc *sc = ifp->if_softc; 3403 struct ifreq *ifr = (struct ifreq *) data; 3404 struct mii_data *mii; 3405 int error = 0; 3406 3407 switch (command) { 3408 case SIOCSIFMTU: 3409 if (ifr->ifr_mtu < ETHERMIN || 3410 ifr->ifr_mtu > sc->rl_hwrev->rl_max_mtu || 3411 ((sc->rl_flags & RL_FLAG_FASTETHER) != 0 && 3412 ifr->ifr_mtu > RL_MTU)) { 3413 error = EINVAL; 3414 break; 3415 } 3416 RL_LOCK(sc); 3417 if (ifp->if_mtu != ifr->ifr_mtu) { 3418 ifp->if_mtu = ifr->ifr_mtu; 3419 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 3420 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3421 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3422 re_init_locked(sc); 3423 } 3424 if (ifp->if_mtu > RL_TSO_MTU && 3425 (ifp->if_capenable & IFCAP_TSO4) != 0) { 3426 ifp->if_capenable &= ~(IFCAP_TSO4 | 3427 IFCAP_VLAN_HWTSO); 3428 ifp->if_hwassist &= ~CSUM_TSO; 3429 } 3430 VLAN_CAPABILITIES(ifp); 3431 } 3432 RL_UNLOCK(sc); 3433 break; 3434 case SIOCSIFFLAGS: 3435 RL_LOCK(sc); 3436 if ((ifp->if_flags & IFF_UP) != 0) { 3437 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3438 if (((ifp->if_flags ^ sc->rl_if_flags) 3439 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 3440 re_set_rxmode(sc); 3441 } else 3442 re_init_locked(sc); 3443 } else { 3444 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3445 re_stop(sc); 3446 } 3447 sc->rl_if_flags = ifp->if_flags; 3448 RL_UNLOCK(sc); 3449 break; 3450 case SIOCADDMULTI: 3451 case SIOCDELMULTI: 3452 RL_LOCK(sc); 3453 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3454 re_set_rxmode(sc); 3455 RL_UNLOCK(sc); 3456 break; 3457 case SIOCGIFMEDIA: 3458 case SIOCSIFMEDIA: 3459 mii = device_get_softc(sc->rl_miibus); 3460 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3461 break; 3462 case SIOCSIFCAP: 3463 { 3464 int mask, reinit; 3465 3466 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3467 reinit = 0; 3468 #ifdef DEVICE_POLLING 3469 if (mask & IFCAP_POLLING) { 3470 if (ifr->ifr_reqcap & IFCAP_POLLING) { 3471 error = ether_poll_register(re_poll, ifp); 3472 if (error) 3473 return (error); 3474 RL_LOCK(sc); 3475 /* Disable interrupts */ 3476 CSR_WRITE_2(sc, RL_IMR, 0x0000); 3477 ifp->if_capenable |= IFCAP_POLLING; 3478 RL_UNLOCK(sc); 3479 } else { 3480 error = ether_poll_deregister(ifp); 3481 /* Enable interrupts. */ 3482 RL_LOCK(sc); 3483 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 3484 ifp->if_capenable &= ~IFCAP_POLLING; 3485 RL_UNLOCK(sc); 3486 } 3487 } 3488 #endif /* DEVICE_POLLING */ 3489 RL_LOCK(sc); 3490 if ((mask & IFCAP_TXCSUM) != 0 && 3491 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 3492 ifp->if_capenable ^= IFCAP_TXCSUM; 3493 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 3494 ifp->if_hwassist |= RE_CSUM_FEATURES; 3495 else 3496 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 3497 reinit = 1; 3498 } 3499 if ((mask & IFCAP_RXCSUM) != 0 && 3500 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 3501 ifp->if_capenable ^= IFCAP_RXCSUM; 3502 reinit = 1; 3503 } 3504 if ((mask & IFCAP_TSO4) != 0 && 3505 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 3506 ifp->if_capenable ^= IFCAP_TSO4; 3507 if ((IFCAP_TSO4 & ifp->if_capenable) != 0) 3508 ifp->if_hwassist |= CSUM_TSO; 3509 else 3510 ifp->if_hwassist &= ~CSUM_TSO; 3511 if (ifp->if_mtu > RL_TSO_MTU && 3512 (ifp->if_capenable & IFCAP_TSO4) != 0) { 3513 ifp->if_capenable &= ~IFCAP_TSO4; 3514 ifp->if_hwassist &= ~CSUM_TSO; 3515 } 3516 } 3517 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 3518 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 3519 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 3520 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3521 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 3522 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 3523 /* TSO over VLAN requires VLAN hardware tagging. */ 3524 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 3525 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 3526 reinit = 1; 3527 } 3528 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 3529 (mask & (IFCAP_HWCSUM | IFCAP_TSO4 | 3530 IFCAP_VLAN_HWTSO)) != 0) 3531 reinit = 1; 3532 if ((mask & IFCAP_WOL) != 0 && 3533 (ifp->if_capabilities & IFCAP_WOL) != 0) { 3534 if ((mask & IFCAP_WOL_UCAST) != 0) 3535 ifp->if_capenable ^= IFCAP_WOL_UCAST; 3536 if ((mask & IFCAP_WOL_MCAST) != 0) 3537 ifp->if_capenable ^= IFCAP_WOL_MCAST; 3538 if ((mask & IFCAP_WOL_MAGIC) != 0) 3539 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 3540 } 3541 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) { 3542 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3543 re_init_locked(sc); 3544 } 3545 RL_UNLOCK(sc); 3546 VLAN_CAPABILITIES(ifp); 3547 } 3548 break; 3549 default: 3550 error = ether_ioctl(ifp, command, data); 3551 break; 3552 } 3553 3554 return (error); 3555 } 3556 3557 static void 3558 re_watchdog(struct rl_softc *sc) 3559 { 3560 struct ifnet *ifp; 3561 3562 RL_LOCK_ASSERT(sc); 3563 3564 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 3565 return; 3566 3567 ifp = sc->rl_ifp; 3568 re_txeof(sc); 3569 if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) { 3570 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 3571 "-- recovering\n"); 3572 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3573 re_start_locked(ifp); 3574 return; 3575 } 3576 3577 if_printf(ifp, "watchdog timeout\n"); 3578 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3579 3580 re_rxeof(sc, NULL); 3581 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3582 re_init_locked(sc); 3583 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3584 re_start_locked(ifp); 3585 } 3586 3587 /* 3588 * Stop the adapter and free any mbufs allocated to the 3589 * RX and TX lists. 3590 */ 3591 static void 3592 re_stop(struct rl_softc *sc) 3593 { 3594 int i; 3595 struct ifnet *ifp; 3596 struct rl_txdesc *txd; 3597 struct rl_rxdesc *rxd; 3598 3599 RL_LOCK_ASSERT(sc); 3600 3601 ifp = sc->rl_ifp; 3602 3603 sc->rl_watchdog_timer = 0; 3604 callout_stop(&sc->rl_stat_callout); 3605 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3606 3607 /* 3608 * Disable accepting frames to put RX MAC into idle state. 3609 * Otherwise it's possible to get frames while stop command 3610 * execution is in progress and controller can DMA the frame 3611 * to already freed RX buffer during that period. 3612 */ 3613 CSR_WRITE_4(sc, RL_RXCFG, CSR_READ_4(sc, RL_RXCFG) & 3614 ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_MULTI | 3615 RL_RXCFG_RX_BROAD)); 3616 3617 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0) { 3618 /* Enable RXDV gate. */ 3619 CSR_WRITE_4(sc, RL_MISC, CSR_READ_4(sc, RL_MISC) | 3620 0x00080000); 3621 } 3622 3623 if ((sc->rl_flags & RL_FLAG_WAIT_TXPOLL) != 0) { 3624 for (i = RL_TIMEOUT; i > 0; i--) { 3625 if ((CSR_READ_1(sc, sc->rl_txstart) & 3626 RL_TXSTART_START) == 0) 3627 break; 3628 DELAY(20); 3629 } 3630 if (i == 0) 3631 device_printf(sc->rl_dev, 3632 "stopping TX poll timed out!\n"); 3633 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 3634 } else if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0) { 3635 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB | 3636 RL_CMD_RX_ENB); 3637 if ((sc->rl_flags & RL_FLAG_CMDSTOP_WAIT_TXQ) != 0) { 3638 for (i = RL_TIMEOUT; i > 0; i--) { 3639 if ((CSR_READ_4(sc, RL_TXCFG) & 3640 RL_TXCFG_QUEUE_EMPTY) != 0) 3641 break; 3642 DELAY(100); 3643 } 3644 if (i == 0) 3645 device_printf(sc->rl_dev, 3646 "stopping TXQ timed out!\n"); 3647 } 3648 } else 3649 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 3650 DELAY(1000); 3651 CSR_WRITE_2(sc, RL_IMR, 0x0000); 3652 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 3653 3654 if (sc->rl_head != NULL) { 3655 m_freem(sc->rl_head); 3656 sc->rl_head = sc->rl_tail = NULL; 3657 } 3658 3659 /* Free the TX list buffers. */ 3660 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 3661 txd = &sc->rl_ldata.rl_tx_desc[i]; 3662 if (txd->tx_m != NULL) { 3663 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 3664 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3665 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 3666 txd->tx_dmamap); 3667 m_freem(txd->tx_m); 3668 txd->tx_m = NULL; 3669 } 3670 } 3671 3672 /* Free the RX list buffers. */ 3673 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 3674 rxd = &sc->rl_ldata.rl_rx_desc[i]; 3675 if (rxd->rx_m != NULL) { 3676 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 3677 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3678 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 3679 rxd->rx_dmamap); 3680 m_freem(rxd->rx_m); 3681 rxd->rx_m = NULL; 3682 } 3683 } 3684 3685 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3686 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 3687 rxd = &sc->rl_ldata.rl_jrx_desc[i]; 3688 if (rxd->rx_m != NULL) { 3689 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, 3690 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3691 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, 3692 rxd->rx_dmamap); 3693 m_freem(rxd->rx_m); 3694 rxd->rx_m = NULL; 3695 } 3696 } 3697 } 3698 } 3699 3700 /* 3701 * Device suspend routine. Stop the interface and save some PCI 3702 * settings in case the BIOS doesn't restore them properly on 3703 * resume. 3704 */ 3705 static int 3706 re_suspend(device_t dev) 3707 { 3708 struct rl_softc *sc; 3709 3710 sc = device_get_softc(dev); 3711 3712 RL_LOCK(sc); 3713 re_stop(sc); 3714 re_setwol(sc); 3715 sc->suspended = 1; 3716 RL_UNLOCK(sc); 3717 3718 return (0); 3719 } 3720 3721 /* 3722 * Device resume routine. Restore some PCI settings in case the BIOS 3723 * doesn't, re-enable busmastering, and restart the interface if 3724 * appropriate. 3725 */ 3726 static int 3727 re_resume(device_t dev) 3728 { 3729 struct rl_softc *sc; 3730 struct ifnet *ifp; 3731 3732 sc = device_get_softc(dev); 3733 3734 RL_LOCK(sc); 3735 3736 ifp = sc->rl_ifp; 3737 /* Take controller out of sleep mode. */ 3738 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3739 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3740 CSR_WRITE_1(sc, RL_GPIO, 3741 CSR_READ_1(sc, RL_GPIO) | 0x01); 3742 } 3743 3744 /* 3745 * Clear WOL matching such that normal Rx filtering 3746 * wouldn't interfere with WOL patterns. 3747 */ 3748 re_clrwol(sc); 3749 3750 /* reinitialize interface if necessary */ 3751 if (ifp->if_flags & IFF_UP) 3752 re_init_locked(sc); 3753 3754 sc->suspended = 0; 3755 RL_UNLOCK(sc); 3756 3757 return (0); 3758 } 3759 3760 /* 3761 * Stop all chip I/O so that the kernel's probe routines don't 3762 * get confused by errant DMAs when rebooting. 3763 */ 3764 static int 3765 re_shutdown(device_t dev) 3766 { 3767 struct rl_softc *sc; 3768 3769 sc = device_get_softc(dev); 3770 3771 RL_LOCK(sc); 3772 re_stop(sc); 3773 /* 3774 * Mark interface as down since otherwise we will panic if 3775 * interrupt comes in later on, which can happen in some 3776 * cases. 3777 */ 3778 sc->rl_ifp->if_flags &= ~IFF_UP; 3779 re_setwol(sc); 3780 RL_UNLOCK(sc); 3781 3782 return (0); 3783 } 3784 3785 static void 3786 re_set_linkspeed(struct rl_softc *sc) 3787 { 3788 struct mii_softc *miisc; 3789 struct mii_data *mii; 3790 int aneg, i, phyno; 3791 3792 RL_LOCK_ASSERT(sc); 3793 3794 mii = device_get_softc(sc->rl_miibus); 3795 mii_pollstat(mii); 3796 aneg = 0; 3797 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 3798 (IFM_ACTIVE | IFM_AVALID)) { 3799 switch IFM_SUBTYPE(mii->mii_media_active) { 3800 case IFM_10_T: 3801 case IFM_100_TX: 3802 return; 3803 case IFM_1000_T: 3804 aneg++; 3805 break; 3806 default: 3807 break; 3808 } 3809 } 3810 miisc = LIST_FIRST(&mii->mii_phys); 3811 phyno = miisc->mii_phy; 3812 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 3813 PHY_RESET(miisc); 3814 re_miibus_writereg(sc->rl_dev, phyno, MII_100T2CR, 0); 3815 re_miibus_writereg(sc->rl_dev, phyno, 3816 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 3817 re_miibus_writereg(sc->rl_dev, phyno, 3818 MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 3819 DELAY(1000); 3820 if (aneg != 0) { 3821 /* 3822 * Poll link state until re(4) get a 10/100Mbps link. 3823 */ 3824 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 3825 mii_pollstat(mii); 3826 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 3827 == (IFM_ACTIVE | IFM_AVALID)) { 3828 switch (IFM_SUBTYPE(mii->mii_media_active)) { 3829 case IFM_10_T: 3830 case IFM_100_TX: 3831 return; 3832 default: 3833 break; 3834 } 3835 } 3836 RL_UNLOCK(sc); 3837 pause("relnk", hz); 3838 RL_LOCK(sc); 3839 } 3840 if (i == MII_ANEGTICKS_GIGE) 3841 device_printf(sc->rl_dev, 3842 "establishing a link failed, WOL may not work!"); 3843 } 3844 /* 3845 * No link, force MAC to have 100Mbps, full-duplex link. 3846 * MAC does not require reprogramming on resolved speed/duplex, 3847 * so this is just for completeness. 3848 */ 3849 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 3850 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 3851 } 3852 3853 static void 3854 re_setwol(struct rl_softc *sc) 3855 { 3856 struct ifnet *ifp; 3857 int pmc; 3858 uint16_t pmstat; 3859 uint8_t v; 3860 3861 RL_LOCK_ASSERT(sc); 3862 3863 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3864 return; 3865 3866 ifp = sc->rl_ifp; 3867 /* Put controller into sleep mode. */ 3868 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3869 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3870 CSR_WRITE_1(sc, RL_GPIO, 3871 CSR_READ_1(sc, RL_GPIO) & ~0x01); 3872 } 3873 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 3874 if ((sc->rl_flags & RL_FLAG_8168G_PLUS) != 0) { 3875 /* Disable RXDV gate. */ 3876 CSR_WRITE_4(sc, RL_MISC, CSR_READ_4(sc, RL_MISC) & 3877 ~0x00080000); 3878 } 3879 re_set_rxmode(sc); 3880 if ((sc->rl_flags & RL_FLAG_WOL_MANLINK) != 0) 3881 re_set_linkspeed(sc); 3882 if ((sc->rl_flags & RL_FLAG_WOLRXENB) != 0) 3883 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB); 3884 } 3885 /* Enable config register write. */ 3886 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3887 3888 /* Enable PME. */ 3889 v = CSR_READ_1(sc, sc->rl_cfg1); 3890 v &= ~RL_CFG1_PME; 3891 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3892 v |= RL_CFG1_PME; 3893 CSR_WRITE_1(sc, sc->rl_cfg1, v); 3894 3895 v = CSR_READ_1(sc, sc->rl_cfg3); 3896 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3897 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3898 v |= RL_CFG3_WOL_MAGIC; 3899 CSR_WRITE_1(sc, sc->rl_cfg3, v); 3900 3901 v = CSR_READ_1(sc, sc->rl_cfg5); 3902 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST | 3903 RL_CFG5_WOL_LANWAKE); 3904 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 3905 v |= RL_CFG5_WOL_UCAST; 3906 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 3907 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 3908 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3909 v |= RL_CFG5_WOL_LANWAKE; 3910 CSR_WRITE_1(sc, sc->rl_cfg5, v); 3911 3912 /* Config register write done. */ 3913 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3914 3915 if ((ifp->if_capenable & IFCAP_WOL) == 0 && 3916 (sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) 3917 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) & ~0x80); 3918 /* 3919 * It seems that hardware resets its link speed to 100Mbps in 3920 * power down mode so switching to 100Mbps in driver is not 3921 * needed. 3922 */ 3923 3924 /* Request PME if WOL is requested. */ 3925 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 3926 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3927 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3928 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3929 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 3930 } 3931 3932 static void 3933 re_clrwol(struct rl_softc *sc) 3934 { 3935 int pmc; 3936 uint8_t v; 3937 3938 RL_LOCK_ASSERT(sc); 3939 3940 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3941 return; 3942 3943 /* Enable config register write. */ 3944 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3945 3946 v = CSR_READ_1(sc, sc->rl_cfg3); 3947 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3948 CSR_WRITE_1(sc, sc->rl_cfg3, v); 3949 3950 /* Config register write done. */ 3951 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3952 3953 v = CSR_READ_1(sc, sc->rl_cfg5); 3954 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3955 v &= ~RL_CFG5_WOL_LANWAKE; 3956 CSR_WRITE_1(sc, sc->rl_cfg5, v); 3957 } 3958 3959 static void 3960 re_add_sysctls(struct rl_softc *sc) 3961 { 3962 struct sysctl_ctx_list *ctx; 3963 struct sysctl_oid_list *children; 3964 int error; 3965 3966 ctx = device_get_sysctl_ctx(sc->rl_dev); 3967 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev)); 3968 3969 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "stats", 3970 CTLTYPE_INT | CTLFLAG_RW, sc, 0, re_sysctl_stats, "I", 3971 "Statistics Information"); 3972 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) 3973 return; 3974 3975 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "int_rx_mod", 3976 CTLTYPE_INT | CTLFLAG_RW, &sc->rl_int_rx_mod, 0, 3977 sysctl_hw_re_int_mod, "I", "re RX interrupt moderation"); 3978 /* Pull in device tunables. */ 3979 sc->rl_int_rx_mod = RL_TIMER_DEFAULT; 3980 error = resource_int_value(device_get_name(sc->rl_dev), 3981 device_get_unit(sc->rl_dev), "int_rx_mod", &sc->rl_int_rx_mod); 3982 if (error == 0) { 3983 if (sc->rl_int_rx_mod < RL_TIMER_MIN || 3984 sc->rl_int_rx_mod > RL_TIMER_MAX) { 3985 device_printf(sc->rl_dev, "int_rx_mod value out of " 3986 "range; using default: %d\n", 3987 RL_TIMER_DEFAULT); 3988 sc->rl_int_rx_mod = RL_TIMER_DEFAULT; 3989 } 3990 } 3991 } 3992 3993 static int 3994 re_sysctl_stats(SYSCTL_HANDLER_ARGS) 3995 { 3996 struct rl_softc *sc; 3997 struct rl_stats *stats; 3998 int error, i, result; 3999 4000 result = -1; 4001 error = sysctl_handle_int(oidp, &result, 0, req); 4002 if (error || req->newptr == NULL) 4003 return (error); 4004 4005 if (result == 1) { 4006 sc = (struct rl_softc *)arg1; 4007 RL_LOCK(sc); 4008 if ((sc->rl_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 4009 RL_UNLOCK(sc); 4010 goto done; 4011 } 4012 bus_dmamap_sync(sc->rl_ldata.rl_stag, 4013 sc->rl_ldata.rl_smap, BUS_DMASYNC_PREREAD); 4014 CSR_WRITE_4(sc, RL_DUMPSTATS_HI, 4015 RL_ADDR_HI(sc->rl_ldata.rl_stats_addr)); 4016 CSR_WRITE_4(sc, RL_DUMPSTATS_LO, 4017 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr)); 4018 CSR_WRITE_4(sc, RL_DUMPSTATS_LO, 4019 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr | 4020 RL_DUMPSTATS_START)); 4021 for (i = RL_TIMEOUT; i > 0; i--) { 4022 if ((CSR_READ_4(sc, RL_DUMPSTATS_LO) & 4023 RL_DUMPSTATS_START) == 0) 4024 break; 4025 DELAY(1000); 4026 } 4027 bus_dmamap_sync(sc->rl_ldata.rl_stag, 4028 sc->rl_ldata.rl_smap, BUS_DMASYNC_POSTREAD); 4029 RL_UNLOCK(sc); 4030 if (i == 0) { 4031 device_printf(sc->rl_dev, 4032 "DUMP statistics request timed out\n"); 4033 return (ETIMEDOUT); 4034 } 4035 done: 4036 stats = sc->rl_ldata.rl_stats; 4037 printf("%s statistics:\n", device_get_nameunit(sc->rl_dev)); 4038 printf("Tx frames : %ju\n", 4039 (uintmax_t)le64toh(stats->rl_tx_pkts)); 4040 printf("Rx frames : %ju\n", 4041 (uintmax_t)le64toh(stats->rl_rx_pkts)); 4042 printf("Tx errors : %ju\n", 4043 (uintmax_t)le64toh(stats->rl_tx_errs)); 4044 printf("Rx errors : %u\n", 4045 le32toh(stats->rl_rx_errs)); 4046 printf("Rx missed frames : %u\n", 4047 (uint32_t)le16toh(stats->rl_missed_pkts)); 4048 printf("Rx frame alignment errs : %u\n", 4049 (uint32_t)le16toh(stats->rl_rx_framealign_errs)); 4050 printf("Tx single collisions : %u\n", 4051 le32toh(stats->rl_tx_onecoll)); 4052 printf("Tx multiple collisions : %u\n", 4053 le32toh(stats->rl_tx_multicolls)); 4054 printf("Rx unicast frames : %ju\n", 4055 (uintmax_t)le64toh(stats->rl_rx_ucasts)); 4056 printf("Rx broadcast frames : %ju\n", 4057 (uintmax_t)le64toh(stats->rl_rx_bcasts)); 4058 printf("Rx multicast frames : %u\n", 4059 le32toh(stats->rl_rx_mcasts)); 4060 printf("Tx aborts : %u\n", 4061 (uint32_t)le16toh(stats->rl_tx_aborts)); 4062 printf("Tx underruns : %u\n", 4063 (uint32_t)le16toh(stats->rl_rx_underruns)); 4064 } 4065 4066 return (error); 4067 } 4068 4069 static int 4070 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4071 { 4072 int error, value; 4073 4074 if (arg1 == NULL) 4075 return (EINVAL); 4076 value = *(int *)arg1; 4077 error = sysctl_handle_int(oidp, &value, 0, req); 4078 if (error || req->newptr == NULL) 4079 return (error); 4080 if (value < low || value > high) 4081 return (EINVAL); 4082 *(int *)arg1 = value; 4083 4084 return (0); 4085 } 4086 4087 static int 4088 sysctl_hw_re_int_mod(SYSCTL_HANDLER_ARGS) 4089 { 4090 4091 return (sysctl_int_range(oidp, arg1, arg2, req, RL_TIMER_MIN, 4092 RL_TIMER_MAX)); 4093 } 4094 4095 #ifdef DEBUGNET 4096 static void 4097 re_debugnet_init(struct ifnet *ifp, int *nrxr, int *ncl, int *clsize) 4098 { 4099 struct rl_softc *sc; 4100 4101 sc = if_getsoftc(ifp); 4102 RL_LOCK(sc); 4103 *nrxr = sc->rl_ldata.rl_rx_desc_cnt; 4104 *ncl = DEBUGNET_MAX_IN_FLIGHT; 4105 *clsize = (ifp->if_mtu > RL_MTU && 4106 (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) ? MJUM9BYTES : MCLBYTES; 4107 RL_UNLOCK(sc); 4108 } 4109 4110 static void 4111 re_debugnet_event(struct ifnet *ifp __unused, enum debugnet_ev event __unused) 4112 { 4113 } 4114 4115 static int 4116 re_debugnet_transmit(struct ifnet *ifp, struct mbuf *m) 4117 { 4118 struct rl_softc *sc; 4119 int error; 4120 4121 sc = if_getsoftc(ifp); 4122 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 4123 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) 4124 return (EBUSY); 4125 4126 error = re_encap(sc, &m); 4127 if (error == 0) 4128 re_start_tx(sc); 4129 return (error); 4130 } 4131 4132 static int 4133 re_debugnet_poll(struct ifnet *ifp, int count) 4134 { 4135 struct rl_softc *sc; 4136 int error; 4137 4138 sc = if_getsoftc(ifp); 4139 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0 || 4140 (sc->rl_flags & RL_FLAG_LINK) == 0) 4141 return (EBUSY); 4142 4143 re_txeof(sc); 4144 error = re_rxeof(sc, NULL); 4145 if (error != 0 && error != EAGAIN) 4146 return (error); 4147 return (0); 4148 } 4149 #endif /* DEBUGNET */ 4150