1 /* 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver 35 * 36 * Written by Bill Paul <wpaul@windriver.com> 37 * Senior Networking Software Engineer 38 * Wind River Systems 39 */ 40 41 /* 42 * This driver is designed to support RealTek's next generation of 43 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 44 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S 45 * and the RTL8110S. 46 * 47 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 48 * with the older 8139 family, however it also supports a special 49 * C+ mode of operation that provides several new performance enhancing 50 * features. These include: 51 * 52 * o Descriptor based DMA mechanism. Each descriptor represents 53 * a single packet fragment. Data buffers may be aligned on 54 * any byte boundary. 55 * 56 * o 64-bit DMA 57 * 58 * o TCP/IP checksum offload for both RX and TX 59 * 60 * o High and normal priority transmit DMA rings 61 * 62 * o VLAN tag insertion and extraction 63 * 64 * o TCP large send (segmentation offload) 65 * 66 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 67 * programming API is fairly straightforward. The RX filtering, EEPROM 68 * access and PHY access is the same as it is on the older 8139 series 69 * chips. 70 * 71 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 72 * same programming API and feature set as the 8139C+ with the following 73 * differences and additions: 74 * 75 * o 1000Mbps mode 76 * 77 * o Jumbo frames 78 * 79 * o GMII and TBI ports/registers for interfacing with copper 80 * or fiber PHYs 81 * 82 * o RX and TX DMA rings can have up to 1024 descriptors 83 * (the 8139C+ allows a maximum of 64) 84 * 85 * o Slight differences in register layout from the 8139C+ 86 * 87 * The TX start and timer interrupt registers are at different locations 88 * on the 8169 than they are on the 8139C+. Also, the status word in the 89 * RX descriptor has a slightly different bit layout. The 8169 does not 90 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 91 * copper gigE PHY. 92 * 93 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 94 * (the 'S' stands for 'single-chip'). These devices have the same 95 * programming API as the older 8169, but also have some vendor-specific 96 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 97 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 98 * 99 * This driver takes advantage of the RX and TX checksum offload and 100 * VLAN tag insertion/extraction features. It also implements TX 101 * interrupt moderation using the timer interrupt registers, which 102 * significantly reduces TX interrupt load. There is also support 103 * for jumbo frames, however the 8169/8169S/8110S can not transmit 104 * jumbo frames larger than 7.5K, so the max MTU possible with this 105 * driver is 7500 bytes. 106 */ 107 108 #include <sys/cdefs.h> 109 __FBSDID("$FreeBSD$"); 110 111 #include <sys/param.h> 112 #include <sys/endian.h> 113 #include <sys/systm.h> 114 #include <sys/sockio.h> 115 #include <sys/mbuf.h> 116 #include <sys/malloc.h> 117 #include <sys/kernel.h> 118 #include <sys/socket.h> 119 120 #include <net/if.h> 121 #include <net/if_arp.h> 122 #include <net/ethernet.h> 123 #include <net/if_dl.h> 124 #include <net/if_media.h> 125 #include <net/if_vlan_var.h> 126 127 #include <net/bpf.h> 128 129 #include <machine/bus_pio.h> 130 #include <machine/bus_memio.h> 131 #include <machine/bus.h> 132 #include <machine/resource.h> 133 #include <sys/bus.h> 134 #include <sys/rman.h> 135 136 #include <dev/mii/mii.h> 137 #include <dev/mii/miivar.h> 138 139 #include <dev/pci/pcireg.h> 140 #include <dev/pci/pcivar.h> 141 142 MODULE_DEPEND(re, pci, 1, 1, 1); 143 MODULE_DEPEND(re, ether, 1, 1, 1); 144 MODULE_DEPEND(re, miibus, 1, 1, 1); 145 146 /* "controller miibus0" required. See GENERIC if you get errors here. */ 147 #include "miibus_if.h" 148 149 /* 150 * Default to using PIO access for this driver. 151 */ 152 #define RE_USEIOSPACE 153 154 #include <pci/if_rlreg.h> 155 156 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 157 158 /* 159 * Various supported device vendors/types and their names. 160 */ 161 static struct rl_type re_devs[] = { 162 { RT_VENDORID, RT_DEVICEID_8139, RL_HWREV_8139CPLUS, 163 "RealTek 8139C+ 10/100BaseTX" }, 164 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169, 165 "RealTek 8169 Gigabit Ethernet" }, 166 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169S, 167 "RealTek 8169S Single-chip Gigabit Ethernet" }, 168 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8110S, 169 "RealTek 8110S Single-chip Gigabit Ethernet" }, 170 { 0, 0, 0, NULL } 171 }; 172 173 static struct rl_hwrev re_hwrevs[] = { 174 { RL_HWREV_8139, RL_8139, "" }, 175 { RL_HWREV_8139A, RL_8139, "A" }, 176 { RL_HWREV_8139AG, RL_8139, "A-G" }, 177 { RL_HWREV_8139B, RL_8139, "B" }, 178 { RL_HWREV_8130, RL_8139, "8130" }, 179 { RL_HWREV_8139C, RL_8139, "C" }, 180 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 181 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 182 { RL_HWREV_8169, RL_8169, "8169"}, 183 { RL_HWREV_8169S, RL_8169, "8169S"}, 184 { RL_HWREV_8110S, RL_8169, "8110S"}, 185 { RL_HWREV_8100, RL_8139, "8100"}, 186 { RL_HWREV_8101, RL_8139, "8101"}, 187 { 0, 0, NULL } 188 }; 189 190 static int re_probe (device_t); 191 static int re_attach (device_t); 192 static int re_detach (device_t); 193 194 static int re_encap (struct rl_softc *, struct mbuf *, int *); 195 196 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 197 static void re_dma_map_desc (void *, bus_dma_segment_t *, int, 198 bus_size_t, int); 199 static int re_allocmem (device_t, struct rl_softc *); 200 static int re_newbuf (struct rl_softc *, int, struct mbuf *); 201 static int re_rx_list_init (struct rl_softc *); 202 static int re_tx_list_init (struct rl_softc *); 203 static void re_rxeof (struct rl_softc *); 204 static void re_txeof (struct rl_softc *); 205 static void re_intr (void *); 206 static void re_tick (void *); 207 static void re_start (struct ifnet *); 208 static int re_ioctl (struct ifnet *, u_long, caddr_t); 209 static void re_init (void *); 210 static void re_stop (struct rl_softc *); 211 static void re_watchdog (struct ifnet *); 212 static int re_suspend (device_t); 213 static int re_resume (device_t); 214 static void re_shutdown (device_t); 215 static int re_ifmedia_upd (struct ifnet *); 216 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 217 218 static void re_eeprom_putbyte (struct rl_softc *, int); 219 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 220 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int, int); 221 static int re_gmii_readreg (device_t, int, int); 222 static int re_gmii_writereg (device_t, int, int, int); 223 224 static int re_miibus_readreg (device_t, int, int); 225 static int re_miibus_writereg (device_t, int, int, int); 226 static void re_miibus_statchg (device_t); 227 228 static u_int8_t re_calchash (caddr_t); 229 static void re_setmulti (struct rl_softc *); 230 static void re_reset (struct rl_softc *); 231 232 static int re_diag (struct rl_softc *); 233 234 #ifdef RE_USEIOSPACE 235 #define RL_RES SYS_RES_IOPORT 236 #define RL_RID RL_PCI_LOIO 237 #else 238 #define RL_RES SYS_RES_MEMORY 239 #define RL_RID RL_PCI_LOMEM 240 #endif 241 242 static device_method_t re_methods[] = { 243 /* Device interface */ 244 DEVMETHOD(device_probe, re_probe), 245 DEVMETHOD(device_attach, re_attach), 246 DEVMETHOD(device_detach, re_detach), 247 DEVMETHOD(device_suspend, re_suspend), 248 DEVMETHOD(device_resume, re_resume), 249 DEVMETHOD(device_shutdown, re_shutdown), 250 251 /* bus interface */ 252 DEVMETHOD(bus_print_child, bus_generic_print_child), 253 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 254 255 /* MII interface */ 256 DEVMETHOD(miibus_readreg, re_miibus_readreg), 257 DEVMETHOD(miibus_writereg, re_miibus_writereg), 258 DEVMETHOD(miibus_statchg, re_miibus_statchg), 259 260 { 0, 0 } 261 }; 262 263 static driver_t re_driver = { 264 "re", 265 re_methods, 266 sizeof(struct rl_softc) 267 }; 268 269 static devclass_t re_devclass; 270 271 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 272 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 273 274 #define EE_SET(x) \ 275 CSR_WRITE_1(sc, RL_EECMD, \ 276 CSR_READ_1(sc, RL_EECMD) | x) 277 278 #define EE_CLR(x) \ 279 CSR_WRITE_1(sc, RL_EECMD, \ 280 CSR_READ_1(sc, RL_EECMD) & ~x) 281 282 /* 283 * Send a read command and address to the EEPROM, check for ACK. 284 */ 285 static void 286 re_eeprom_putbyte(sc, addr) 287 struct rl_softc *sc; 288 int addr; 289 { 290 register int d, i; 291 292 d = addr | sc->rl_eecmd_read; 293 294 /* 295 * Feed in each bit and strobe the clock. 296 */ 297 for (i = 0x400; i; i >>= 1) { 298 if (d & i) { 299 EE_SET(RL_EE_DATAIN); 300 } else { 301 EE_CLR(RL_EE_DATAIN); 302 } 303 DELAY(100); 304 EE_SET(RL_EE_CLK); 305 DELAY(150); 306 EE_CLR(RL_EE_CLK); 307 DELAY(100); 308 } 309 310 return; 311 } 312 313 /* 314 * Read a word of data stored in the EEPROM at address 'addr.' 315 */ 316 static void 317 re_eeprom_getword(sc, addr, dest) 318 struct rl_softc *sc; 319 int addr; 320 u_int16_t *dest; 321 { 322 register int i; 323 u_int16_t word = 0; 324 325 /* Enter EEPROM access mode. */ 326 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 327 328 /* 329 * Send address of word we want to read. 330 */ 331 re_eeprom_putbyte(sc, addr); 332 333 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 334 335 /* 336 * Start reading bits from EEPROM. 337 */ 338 for (i = 0x8000; i; i >>= 1) { 339 EE_SET(RL_EE_CLK); 340 DELAY(100); 341 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 342 word |= i; 343 EE_CLR(RL_EE_CLK); 344 DELAY(100); 345 } 346 347 /* Turn off EEPROM access mode. */ 348 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 349 350 *dest = word; 351 352 return; 353 } 354 355 /* 356 * Read a sequence of words from the EEPROM. 357 */ 358 static void 359 re_read_eeprom(sc, dest, off, cnt, swap) 360 struct rl_softc *sc; 361 caddr_t dest; 362 int off; 363 int cnt; 364 int swap; 365 { 366 int i; 367 u_int16_t word = 0, *ptr; 368 369 for (i = 0; i < cnt; i++) { 370 re_eeprom_getword(sc, off + i, &word); 371 ptr = (u_int16_t *)(dest + (i * 2)); 372 if (swap) 373 *ptr = ntohs(word); 374 else 375 *ptr = word; 376 } 377 378 return; 379 } 380 381 static int 382 re_gmii_readreg(dev, phy, reg) 383 device_t dev; 384 int phy, reg; 385 { 386 struct rl_softc *sc; 387 u_int32_t rval; 388 int i; 389 390 if (phy != 1) 391 return(0); 392 393 sc = device_get_softc(dev); 394 395 /* Let the rgephy driver read the GMEDIASTAT register */ 396 397 if (reg == RL_GMEDIASTAT) { 398 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 399 return(rval); 400 } 401 402 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 403 DELAY(1000); 404 405 for (i = 0; i < RL_TIMEOUT; i++) { 406 rval = CSR_READ_4(sc, RL_PHYAR); 407 if (rval & RL_PHYAR_BUSY) 408 break; 409 DELAY(100); 410 } 411 412 if (i == RL_TIMEOUT) { 413 printf ("re%d: PHY read failed\n", sc->rl_unit); 414 return (0); 415 } 416 417 return (rval & RL_PHYAR_PHYDATA); 418 } 419 420 static int 421 re_gmii_writereg(dev, phy, reg, data) 422 device_t dev; 423 int phy, reg, data; 424 { 425 struct rl_softc *sc; 426 u_int32_t rval; 427 int i; 428 429 sc = device_get_softc(dev); 430 431 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 432 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 433 DELAY(1000); 434 435 for (i = 0; i < RL_TIMEOUT; i++) { 436 rval = CSR_READ_4(sc, RL_PHYAR); 437 if (!(rval & RL_PHYAR_BUSY)) 438 break; 439 DELAY(100); 440 } 441 442 if (i == RL_TIMEOUT) { 443 printf ("re%d: PHY write failed\n", sc->rl_unit); 444 return (0); 445 } 446 447 return (0); 448 } 449 450 static int 451 re_miibus_readreg(dev, phy, reg) 452 device_t dev; 453 int phy, reg; 454 { 455 struct rl_softc *sc; 456 u_int16_t rval = 0; 457 u_int16_t re8139_reg = 0; 458 459 sc = device_get_softc(dev); 460 RL_LOCK(sc); 461 462 if (sc->rl_type == RL_8169) { 463 rval = re_gmii_readreg(dev, phy, reg); 464 RL_UNLOCK(sc); 465 return (rval); 466 } 467 468 /* Pretend the internal PHY is only at address 0 */ 469 if (phy) { 470 RL_UNLOCK(sc); 471 return(0); 472 } 473 switch(reg) { 474 case MII_BMCR: 475 re8139_reg = RL_BMCR; 476 break; 477 case MII_BMSR: 478 re8139_reg = RL_BMSR; 479 break; 480 case MII_ANAR: 481 re8139_reg = RL_ANAR; 482 break; 483 case MII_ANER: 484 re8139_reg = RL_ANER; 485 break; 486 case MII_ANLPAR: 487 re8139_reg = RL_LPAR; 488 break; 489 case MII_PHYIDR1: 490 case MII_PHYIDR2: 491 RL_UNLOCK(sc); 492 return(0); 493 /* 494 * Allow the rlphy driver to read the media status 495 * register. If we have a link partner which does not 496 * support NWAY, this is the register which will tell 497 * us the results of parallel detection. 498 */ 499 case RL_MEDIASTAT: 500 rval = CSR_READ_1(sc, RL_MEDIASTAT); 501 RL_UNLOCK(sc); 502 return(rval); 503 default: 504 printf("re%d: bad phy register\n", sc->rl_unit); 505 RL_UNLOCK(sc); 506 return(0); 507 } 508 rval = CSR_READ_2(sc, re8139_reg); 509 RL_UNLOCK(sc); 510 return(rval); 511 } 512 513 static int 514 re_miibus_writereg(dev, phy, reg, data) 515 device_t dev; 516 int phy, reg, data; 517 { 518 struct rl_softc *sc; 519 u_int16_t re8139_reg = 0; 520 int rval = 0; 521 522 sc = device_get_softc(dev); 523 RL_LOCK(sc); 524 525 if (sc->rl_type == RL_8169) { 526 rval = re_gmii_writereg(dev, phy, reg, data); 527 RL_UNLOCK(sc); 528 return (rval); 529 } 530 531 /* Pretend the internal PHY is only at address 0 */ 532 if (phy) { 533 RL_UNLOCK(sc); 534 return(0); 535 } 536 switch(reg) { 537 case MII_BMCR: 538 re8139_reg = RL_BMCR; 539 break; 540 case MII_BMSR: 541 re8139_reg = RL_BMSR; 542 break; 543 case MII_ANAR: 544 re8139_reg = RL_ANAR; 545 break; 546 case MII_ANER: 547 re8139_reg = RL_ANER; 548 break; 549 case MII_ANLPAR: 550 re8139_reg = RL_LPAR; 551 break; 552 case MII_PHYIDR1: 553 case MII_PHYIDR2: 554 RL_UNLOCK(sc); 555 return(0); 556 break; 557 default: 558 printf("re%d: bad phy register\n", sc->rl_unit); 559 RL_UNLOCK(sc); 560 return(0); 561 } 562 CSR_WRITE_2(sc, re8139_reg, data); 563 RL_UNLOCK(sc); 564 return(0); 565 } 566 567 static void 568 re_miibus_statchg(dev) 569 device_t dev; 570 { 571 return; 572 } 573 574 /* 575 * Calculate CRC of a multicast group address, return the upper 6 bits. 576 */ 577 static u_int8_t 578 re_calchash(addr) 579 caddr_t addr; 580 { 581 u_int32_t crc, carry; 582 int i, j; 583 u_int8_t c; 584 585 /* Compute CRC for the address value. */ 586 crc = 0xFFFFFFFF; /* initial value */ 587 588 for (i = 0; i < 6; i++) { 589 c = *(addr + i); 590 for (j = 0; j < 8; j++) { 591 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 592 crc <<= 1; 593 c >>= 1; 594 if (carry) 595 crc = (crc ^ 0x04c11db6) | carry; 596 } 597 } 598 599 /* return the filter bit position */ 600 return(crc >> 26); 601 } 602 603 /* 604 * Program the 64-bit multicast hash filter. 605 */ 606 static void 607 re_setmulti(sc) 608 struct rl_softc *sc; 609 { 610 struct ifnet *ifp; 611 int h = 0; 612 u_int32_t hashes[2] = { 0, 0 }; 613 struct ifmultiaddr *ifma; 614 u_int32_t rxfilt; 615 int mcnt = 0; 616 617 ifp = &sc->arpcom.ac_if; 618 619 rxfilt = CSR_READ_4(sc, RL_RXCFG); 620 621 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 622 rxfilt |= RL_RXCFG_RX_MULTI; 623 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 624 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 625 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 626 return; 627 } 628 629 /* first, zot all the existing hash bits */ 630 CSR_WRITE_4(sc, RL_MAR0, 0); 631 CSR_WRITE_4(sc, RL_MAR4, 0); 632 633 /* now program new ones */ 634 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 635 if (ifma->ifma_addr->sa_family != AF_LINK) 636 continue; 637 h = re_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 638 if (h < 32) 639 hashes[0] |= (1 << h); 640 else 641 hashes[1] |= (1 << (h - 32)); 642 mcnt++; 643 } 644 645 if (mcnt) 646 rxfilt |= RL_RXCFG_RX_MULTI; 647 else 648 rxfilt &= ~RL_RXCFG_RX_MULTI; 649 650 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 651 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 652 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 653 654 return; 655 } 656 657 static void 658 re_reset(sc) 659 struct rl_softc *sc; 660 { 661 register int i; 662 663 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 664 665 for (i = 0; i < RL_TIMEOUT; i++) { 666 DELAY(10); 667 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 668 break; 669 } 670 if (i == RL_TIMEOUT) 671 printf("re%d: reset never completed!\n", sc->rl_unit); 672 673 CSR_WRITE_1(sc, 0x82, 1); 674 675 return; 676 } 677 678 /* 679 * The following routine is designed to test for a defect on some 680 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 681 * lines connected to the bus, however for a 32-bit only card, they 682 * should be pulled high. The result of this defect is that the 683 * NIC will not work right if you plug it into a 64-bit slot: DMA 684 * operations will be done with 64-bit transfers, which will fail 685 * because the 64-bit data lines aren't connected. 686 * 687 * There's no way to work around this (short of talking a soldering 688 * iron to the board), however we can detect it. The method we use 689 * here is to put the NIC into digital loopback mode, set the receiver 690 * to promiscuous mode, and then try to send a frame. We then compare 691 * the frame data we sent to what was received. If the data matches, 692 * then the NIC is working correctly, otherwise we know the user has 693 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 694 * slot. In the latter case, there's no way the NIC can work correctly, 695 * so we print out a message on the console and abort the device attach. 696 */ 697 698 static int 699 re_diag(sc) 700 struct rl_softc *sc; 701 { 702 struct ifnet *ifp = &sc->arpcom.ac_if; 703 struct mbuf *m0; 704 struct ether_header *eh; 705 struct rl_desc *cur_rx; 706 u_int16_t status; 707 u_int32_t rxstat; 708 int total_len, i, error = 0; 709 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 710 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 711 712 /* Allocate a single mbuf */ 713 714 MGETHDR(m0, M_DONTWAIT, MT_DATA); 715 if (m0 == NULL) 716 return(ENOBUFS); 717 718 /* 719 * Initialize the NIC in test mode. This sets the chip up 720 * so that it can send and receive frames, but performs the 721 * following special functions: 722 * - Puts receiver in promiscuous mode 723 * - Enables digital loopback mode 724 * - Leaves interrupts turned off 725 */ 726 727 ifp->if_flags |= IFF_PROMISC; 728 sc->rl_testmode = 1; 729 re_init(sc); 730 re_stop(sc); 731 DELAY(100000); 732 re_init(sc); 733 734 /* Put some data in the mbuf */ 735 736 eh = mtod(m0, struct ether_header *); 737 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 738 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 739 eh->ether_type = htons(ETHERTYPE_IP); 740 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 741 742 /* 743 * Queue the packet, start transmission. 744 * Note: IF_HANDOFF() ultimately calls re_start() for us. 745 */ 746 747 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 748 IF_HANDOFF(&ifp->if_snd, m0, ifp); 749 m0 = NULL; 750 751 /* Wait for it to propagate through the chip */ 752 753 DELAY(100000); 754 for (i = 0; i < RL_TIMEOUT; i++) { 755 status = CSR_READ_2(sc, RL_ISR); 756 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 757 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 758 break; 759 DELAY(10); 760 } 761 762 if (i == RL_TIMEOUT) { 763 printf("re%d: diagnostic failed, failed to receive packet " 764 "in loopback mode\n", sc->rl_unit); 765 error = EIO; 766 goto done; 767 } 768 769 /* 770 * The packet should have been dumped into the first 771 * entry in the RX DMA ring. Grab it from there. 772 */ 773 774 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 775 sc->rl_ldata.rl_rx_list_map, 776 BUS_DMASYNC_POSTREAD); 777 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 778 sc->rl_ldata.rl_rx_dmamap[0], 779 BUS_DMASYNC_POSTWRITE); 780 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 781 sc->rl_ldata.rl_rx_dmamap[0]); 782 783 m0 = sc->rl_ldata.rl_rx_mbuf[0]; 784 sc->rl_ldata.rl_rx_mbuf[0] = NULL; 785 eh = mtod(m0, struct ether_header *); 786 787 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 788 total_len = RL_RXBYTES(cur_rx); 789 rxstat = le32toh(cur_rx->rl_cmdstat); 790 791 if (total_len != ETHER_MIN_LEN) { 792 printf("re%d: diagnostic failed, received short packet\n", 793 sc->rl_unit); 794 error = EIO; 795 goto done; 796 } 797 798 /* Test that the received packet data matches what we sent. */ 799 800 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 801 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 802 ntohs(eh->ether_type) != ETHERTYPE_IP) { 803 printf("re%d: WARNING, DMA FAILURE!\n", sc->rl_unit); 804 printf("re%d: expected TX data: %6D/%6D/0x%x\n", sc->rl_unit, 805 dst, ":", src, ":", ETHERTYPE_IP); 806 printf("re%d: received RX data: %6D/%6D/0x%x\n", sc->rl_unit, 807 eh->ether_dhost, ":", eh->ether_shost, ":", 808 ntohs(eh->ether_type)); 809 printf("re%d: You may have a defective 32-bit NIC plugged " 810 "into a 64-bit PCI slot.\n", sc->rl_unit); 811 printf("re%d: Please re-install the NIC in a 32-bit slot " 812 "for proper operation.\n", sc->rl_unit); 813 printf("re%d: Read the re(4) man page for more details.\n", 814 sc->rl_unit); 815 error = EIO; 816 } 817 818 done: 819 /* Turn interface off, release resources */ 820 821 sc->rl_testmode = 0; 822 ifp->if_flags &= ~IFF_PROMISC; 823 re_stop(sc); 824 if (m0 != NULL) 825 m_freem(m0); 826 827 return (error); 828 } 829 830 /* 831 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 832 * IDs against our list and return a device name if we find a match. 833 */ 834 static int 835 re_probe(dev) 836 device_t dev; 837 { 838 struct rl_type *t; 839 struct rl_softc *sc; 840 int rid; 841 u_int32_t hwrev; 842 843 t = re_devs; 844 sc = device_get_softc(dev); 845 846 while(t->rl_name != NULL) { 847 if ((pci_get_vendor(dev) == t->rl_vid) && 848 (pci_get_device(dev) == t->rl_did)) { 849 850 /* 851 * Temporarily map the I/O space 852 * so we can read the chip ID register. 853 */ 854 rid = RL_RID; 855 sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid, 856 0, ~0, 1, RF_ACTIVE); 857 if (sc->rl_res == NULL) { 858 device_printf(dev, 859 "couldn't map ports/memory\n"); 860 return(ENXIO); 861 } 862 sc->rl_btag = rman_get_bustag(sc->rl_res); 863 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 864 mtx_init(&sc->rl_mtx, 865 device_get_nameunit(dev), 866 MTX_NETWORK_LOCK, MTX_DEF); 867 RL_LOCK(sc); 868 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 869 bus_release_resource(dev, RL_RES, 870 RL_RID, sc->rl_res); 871 RL_UNLOCK(sc); 872 mtx_destroy(&sc->rl_mtx); 873 if (t->rl_basetype == hwrev) { 874 device_set_desc(dev, t->rl_name); 875 return(0); 876 } 877 } 878 t++; 879 } 880 881 return(ENXIO); 882 } 883 884 /* 885 * This routine takes the segment list provided as the result of 886 * a bus_dma_map_load() operation and assigns the addresses/lengths 887 * to RealTek DMA descriptors. This can be called either by the RX 888 * code or the TX code. In the RX case, we'll probably wind up mapping 889 * at most one segment. For the TX case, there could be any number of 890 * segments since TX packets may span multiple mbufs. In either case, 891 * if the number of segments is larger than the rl_maxsegs limit 892 * specified by the caller, we abort the mapping operation. Sadly, 893 * whoever designed the buffer mapping API did not provide a way to 894 * return an error from here, so we have to fake it a bit. 895 */ 896 897 static void 898 re_dma_map_desc(arg, segs, nseg, mapsize, error) 899 void *arg; 900 bus_dma_segment_t *segs; 901 int nseg; 902 bus_size_t mapsize; 903 int error; 904 { 905 struct rl_dmaload_arg *ctx; 906 struct rl_desc *d = NULL; 907 int i = 0, idx; 908 909 if (error) 910 return; 911 912 ctx = arg; 913 914 /* Signal error to caller if there's too many segments */ 915 if (nseg > ctx->rl_maxsegs) { 916 ctx->rl_maxsegs = 0; 917 return; 918 } 919 920 /* 921 * Map the segment array into descriptors. Note that we set the 922 * start-of-frame and end-of-frame markers for either TX or RX, but 923 * they really only have meaning in the TX case. (In the RX case, 924 * it's the chip that tells us where packets begin and end.) 925 * We also keep track of the end of the ring and set the 926 * end-of-ring bits as needed, and we set the ownership bits 927 * in all except the very first descriptor. (The caller will 928 * set this descriptor later when it start transmission or 929 * reception.) 930 */ 931 idx = ctx->rl_idx; 932 while(1) { 933 u_int32_t cmdstat; 934 d = &ctx->rl_ring[idx]; 935 if (le32toh(d->rl_cmdstat) & RL_RDESC_STAT_OWN) { 936 ctx->rl_maxsegs = 0; 937 return; 938 } 939 cmdstat = segs[i].ds_len; 940 d->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 941 d->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 942 if (i == 0) 943 cmdstat |= RL_TDESC_CMD_SOF; 944 else 945 cmdstat |= RL_TDESC_CMD_OWN; 946 if (idx == (RL_RX_DESC_CNT - 1)) 947 cmdstat |= RL_TDESC_CMD_EOR; 948 d->rl_cmdstat = htole32(cmdstat | ctx->rl_flags); 949 i++; 950 if (i == nseg) 951 break; 952 RL_DESC_INC(idx); 953 } 954 955 d->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 956 ctx->rl_maxsegs = nseg; 957 ctx->rl_idx = idx; 958 959 return; 960 } 961 962 /* 963 * Map a single buffer address. 964 */ 965 966 static void 967 re_dma_map_addr(arg, segs, nseg, error) 968 void *arg; 969 bus_dma_segment_t *segs; 970 int nseg; 971 int error; 972 { 973 u_int32_t *addr; 974 975 if (error) 976 return; 977 978 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 979 addr = arg; 980 *addr = segs->ds_addr; 981 982 return; 983 } 984 985 static int 986 re_allocmem(dev, sc) 987 device_t dev; 988 struct rl_softc *sc; 989 { 990 int error; 991 int nseg; 992 int i; 993 994 /* 995 * Allocate map for RX mbufs. 996 */ 997 nseg = 32; 998 error = bus_dma_tag_create(sc->rl_parent_tag, ETHER_ALIGN, 0, 999 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1000 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 1001 NULL, NULL, &sc->rl_ldata.rl_mtag); 1002 if (error) { 1003 device_printf(dev, "could not allocate dma tag\n"); 1004 return (ENOMEM); 1005 } 1006 1007 /* 1008 * Allocate map for TX descriptor list. 1009 */ 1010 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1011 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1012 NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 1013 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1014 if (error) { 1015 device_printf(dev, "could not allocate dma tag\n"); 1016 return (ENOMEM); 1017 } 1018 1019 /* Allocate DMA'able memory for the TX ring */ 1020 1021 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1022 (void **)&sc->rl_ldata.rl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1023 &sc->rl_ldata.rl_tx_list_map); 1024 if (error) 1025 return (ENOMEM); 1026 1027 /* Load the map for the TX ring. */ 1028 1029 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1030 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1031 RL_TX_LIST_SZ, re_dma_map_addr, 1032 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1033 1034 /* Create DMA maps for TX buffers */ 1035 1036 for (i = 0; i < RL_TX_DESC_CNT; i++) { 1037 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1038 &sc->rl_ldata.rl_tx_dmamap[i]); 1039 if (error) { 1040 device_printf(dev, "can't create DMA map for TX\n"); 1041 return(ENOMEM); 1042 } 1043 } 1044 1045 /* 1046 * Allocate map for RX descriptor list. 1047 */ 1048 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1049 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1050 NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 1051 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1052 if (error) { 1053 device_printf(dev, "could not allocate dma tag\n"); 1054 return (ENOMEM); 1055 } 1056 1057 /* Allocate DMA'able memory for the RX ring */ 1058 1059 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1060 (void **)&sc->rl_ldata.rl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1061 &sc->rl_ldata.rl_rx_list_map); 1062 if (error) 1063 return (ENOMEM); 1064 1065 /* Load the map for the RX ring. */ 1066 1067 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1068 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1069 RL_TX_LIST_SZ, re_dma_map_addr, 1070 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1071 1072 /* Create DMA maps for RX buffers */ 1073 1074 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1075 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1076 &sc->rl_ldata.rl_rx_dmamap[i]); 1077 if (error) { 1078 device_printf(dev, "can't create DMA map for RX\n"); 1079 return(ENOMEM); 1080 } 1081 } 1082 1083 return(0); 1084 } 1085 1086 /* 1087 * Attach the interface. Allocate softc structures, do ifmedia 1088 * setup and ethernet/BPF attach. 1089 */ 1090 static int 1091 re_attach(dev) 1092 device_t dev; 1093 { 1094 u_char eaddr[ETHER_ADDR_LEN]; 1095 u_int16_t as[3]; 1096 struct rl_softc *sc; 1097 struct ifnet *ifp; 1098 struct rl_hwrev *hw_rev; 1099 int hwrev; 1100 u_int16_t re_did = 0; 1101 int unit, error = 0, rid, i; 1102 1103 sc = device_get_softc(dev); 1104 unit = device_get_unit(dev); 1105 1106 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1107 MTX_DEF | MTX_RECURSE); 1108 #ifndef BURN_BRIDGES 1109 /* 1110 * Handle power management nonsense. 1111 */ 1112 1113 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1114 u_int32_t iobase, membase, irq; 1115 1116 /* Save important PCI config data. */ 1117 iobase = pci_read_config(dev, RL_PCI_LOIO, 4); 1118 membase = pci_read_config(dev, RL_PCI_LOMEM, 4); 1119 irq = pci_read_config(dev, RL_PCI_INTLINE, 4); 1120 1121 /* Reset the power state. */ 1122 printf("re%d: chip is is in D%d power mode " 1123 "-- setting to D0\n", unit, 1124 pci_get_powerstate(dev)); 1125 1126 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1127 1128 /* Restore PCI config data. */ 1129 pci_write_config(dev, RL_PCI_LOIO, iobase, 4); 1130 pci_write_config(dev, RL_PCI_LOMEM, membase, 4); 1131 pci_write_config(dev, RL_PCI_INTLINE, irq, 4); 1132 } 1133 #endif 1134 /* 1135 * Map control/status registers. 1136 */ 1137 pci_enable_busmaster(dev); 1138 1139 rid = RL_RID; 1140 sc->rl_res = bus_alloc_resource(dev, RL_RES, &rid, 1141 0, ~0, 1, RF_ACTIVE); 1142 1143 if (sc->rl_res == NULL) { 1144 printf ("re%d: couldn't map ports/memory\n", unit); 1145 error = ENXIO; 1146 goto fail; 1147 } 1148 1149 sc->rl_btag = rman_get_bustag(sc->rl_res); 1150 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1151 1152 /* Allocate interrupt */ 1153 rid = 0; 1154 sc->rl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1155 RF_SHAREABLE | RF_ACTIVE); 1156 1157 if (sc->rl_irq == NULL) { 1158 printf("re%d: couldn't map interrupt\n", unit); 1159 error = ENXIO; 1160 goto fail; 1161 } 1162 1163 /* Reset the adapter. */ 1164 re_reset(sc); 1165 1166 hw_rev = re_hwrevs; 1167 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 1168 while (hw_rev->rl_desc != NULL) { 1169 if (hw_rev->rl_rev == hwrev) { 1170 sc->rl_type = hw_rev->rl_type; 1171 break; 1172 } 1173 hw_rev++; 1174 } 1175 1176 if (sc->rl_type == RL_8169) { 1177 1178 /* Set RX length mask */ 1179 1180 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1181 1182 /* Force station address autoload from the EEPROM */ 1183 1184 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_AUTOLOAD); 1185 for (i = 0; i < RL_TIMEOUT; i++) { 1186 if (!(CSR_READ_1(sc, RL_EECMD) & RL_EEMODE_AUTOLOAD)) 1187 break; 1188 DELAY(100); 1189 } 1190 if (i == RL_TIMEOUT) 1191 printf ("re%d: eeprom autoload timed out\n", unit); 1192 1193 for (i = 0; i < ETHER_ADDR_LEN; i++) 1194 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1195 } else { 1196 1197 /* Set RX length mask */ 1198 1199 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1200 1201 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 1202 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1, 0); 1203 if (re_did != 0x8129) 1204 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 1205 1206 /* 1207 * Get station address from the EEPROM. 1208 */ 1209 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0); 1210 for (i = 0; i < 3; i++) { 1211 eaddr[(i * 2) + 0] = as[i] & 0xff; 1212 eaddr[(i * 2) + 1] = as[i] >> 8; 1213 } 1214 } 1215 1216 /* 1217 * A RealTek chip was detected. Inform the world. 1218 */ 1219 printf("re%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1220 1221 sc->rl_unit = unit; 1222 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1223 1224 /* 1225 * Allocate the parent bus DMA tag appropriate for PCI. 1226 */ 1227 #define RL_NSEG_NEW 32 1228 error = bus_dma_tag_create(NULL, /* parent */ 1229 1, 0, /* alignment, boundary */ 1230 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1231 BUS_SPACE_MAXADDR, /* highaddr */ 1232 NULL, NULL, /* filter, filterarg */ 1233 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 1234 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1235 BUS_DMA_ALLOCNOW, /* flags */ 1236 NULL, NULL, /* lockfunc, lockarg */ 1237 &sc->rl_parent_tag); 1238 if (error) 1239 goto fail; 1240 1241 error = re_allocmem(dev, sc); 1242 1243 if (error) 1244 goto fail; 1245 1246 /* Do MII setup */ 1247 if (mii_phy_probe(dev, &sc->rl_miibus, 1248 re_ifmedia_upd, re_ifmedia_sts)) { 1249 printf("re%d: MII without any phy!\n", sc->rl_unit); 1250 error = ENXIO; 1251 goto fail; 1252 } 1253 1254 ifp = &sc->arpcom.ac_if; 1255 ifp->if_softc = sc; 1256 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1257 ifp->if_mtu = ETHERMTU; 1258 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1259 ifp->if_ioctl = re_ioctl; 1260 ifp->if_output = ether_output; 1261 ifp->if_capabilities = IFCAP_VLAN_MTU; 1262 ifp->if_start = re_start; 1263 ifp->if_hwassist = RE_CSUM_FEATURES; 1264 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1265 ifp->if_watchdog = re_watchdog; 1266 ifp->if_init = re_init; 1267 if (sc->rl_type == RL_8169) 1268 ifp->if_baudrate = 1000000000; 1269 else 1270 ifp->if_baudrate = 100000000; 1271 ifp->if_snd.ifq_maxlen = RL_IFQ_MAXLEN; 1272 ifp->if_capenable = ifp->if_capabilities; 1273 1274 callout_handle_init(&sc->rl_stat_ch); 1275 1276 /* 1277 * Call MI attach routine. 1278 */ 1279 ether_ifattach(ifp, eaddr); 1280 1281 /* Perform hardware diagnostic. */ 1282 error = re_diag(sc); 1283 1284 if (error) { 1285 printf("re%d: attach aborted due to hardware diag failure\n", 1286 unit); 1287 ether_ifdetach(ifp); 1288 goto fail; 1289 } 1290 1291 /* Hook interrupt last to avoid having to lock softc */ 1292 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, 1293 re_intr, sc, &sc->rl_intrhand); 1294 1295 if (error) { 1296 printf("re%d: couldn't set up irq\n", unit); 1297 ether_ifdetach(ifp); 1298 goto fail; 1299 } 1300 1301 fail: 1302 if (error) 1303 re_detach(dev); 1304 1305 return (error); 1306 } 1307 1308 /* 1309 * Shutdown hardware and free up resources. This can be called any 1310 * time after the mutex has been initialized. It is called in both 1311 * the error case in attach and the normal detach case so it needs 1312 * to be careful about only freeing resources that have actually been 1313 * allocated. 1314 */ 1315 static int 1316 re_detach(dev) 1317 device_t dev; 1318 { 1319 struct rl_softc *sc; 1320 struct ifnet *ifp; 1321 int i; 1322 1323 sc = device_get_softc(dev); 1324 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized")); 1325 RL_LOCK(sc); 1326 ifp = &sc->arpcom.ac_if; 1327 1328 /* These should only be active if attach succeeded */ 1329 if (device_is_attached(dev)) { 1330 re_stop(sc); 1331 /* 1332 * Force off the IFF_UP flag here, in case someone 1333 * still had a BPF descriptor attached to this 1334 * interface. If they do, ether_ifattach() will cause 1335 * the BPF code to try and clear the promisc mode 1336 * flag, which will bubble down to re_ioctl(), 1337 * which will try to call re_init() again. This will 1338 * turn the NIC back on and restart the MII ticker, 1339 * which will panic the system when the kernel tries 1340 * to invoke the re_tick() function that isn't there 1341 * anymore. 1342 */ 1343 ifp->if_flags &= ~IFF_UP; 1344 ether_ifdetach(ifp); 1345 } 1346 if (sc->rl_miibus) 1347 device_delete_child(dev, sc->rl_miibus); 1348 bus_generic_detach(dev); 1349 1350 if (sc->rl_intrhand) 1351 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1352 if (sc->rl_irq) 1353 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1354 if (sc->rl_res) 1355 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1356 1357 1358 /* Unload and free the RX DMA ring memory and map */ 1359 1360 if (sc->rl_ldata.rl_rx_list_tag) { 1361 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1362 sc->rl_ldata.rl_rx_list_map); 1363 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1364 sc->rl_ldata.rl_rx_list, 1365 sc->rl_ldata.rl_rx_list_map); 1366 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1367 } 1368 1369 /* Unload and free the TX DMA ring memory and map */ 1370 1371 if (sc->rl_ldata.rl_tx_list_tag) { 1372 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1373 sc->rl_ldata.rl_tx_list_map); 1374 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1375 sc->rl_ldata.rl_tx_list, 1376 sc->rl_ldata.rl_tx_list_map); 1377 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1378 } 1379 1380 /* Destroy all the RX and TX buffer maps */ 1381 1382 if (sc->rl_ldata.rl_mtag) { 1383 for (i = 0; i < RL_TX_DESC_CNT; i++) 1384 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1385 sc->rl_ldata.rl_tx_dmamap[i]); 1386 for (i = 0; i < RL_RX_DESC_CNT; i++) 1387 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1388 sc->rl_ldata.rl_rx_dmamap[i]); 1389 bus_dma_tag_destroy(sc->rl_ldata.rl_mtag); 1390 } 1391 1392 /* Unload and free the stats buffer and map */ 1393 1394 if (sc->rl_ldata.rl_stag) { 1395 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1396 sc->rl_ldata.rl_rx_list_map); 1397 bus_dmamem_free(sc->rl_ldata.rl_stag, 1398 sc->rl_ldata.rl_stats, 1399 sc->rl_ldata.rl_smap); 1400 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1401 } 1402 1403 if (sc->rl_parent_tag) 1404 bus_dma_tag_destroy(sc->rl_parent_tag); 1405 1406 RL_UNLOCK(sc); 1407 mtx_destroy(&sc->rl_mtx); 1408 1409 return(0); 1410 } 1411 1412 static int 1413 re_newbuf(sc, idx, m) 1414 struct rl_softc *sc; 1415 int idx; 1416 struct mbuf *m; 1417 { 1418 struct rl_dmaload_arg arg; 1419 struct mbuf *n = NULL; 1420 int error; 1421 1422 if (m == NULL) { 1423 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1424 if (n == NULL) 1425 return(ENOBUFS); 1426 m = n; 1427 } else 1428 m->m_data = m->m_ext.ext_buf; 1429 1430 /* 1431 * Initialize mbuf length fields and fixup 1432 * alignment so that the frame payload is 1433 * longword aligned. 1434 */ 1435 m->m_len = m->m_pkthdr.len = MCLBYTES; 1436 m_adj(m, ETHER_ALIGN); 1437 1438 arg.sc = sc; 1439 arg.rl_idx = idx; 1440 arg.rl_maxsegs = 1; 1441 arg.rl_flags = 0; 1442 arg.rl_ring = sc->rl_ldata.rl_rx_list; 1443 1444 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, 1445 sc->rl_ldata.rl_rx_dmamap[idx], m, re_dma_map_desc, 1446 &arg, BUS_DMA_NOWAIT); 1447 if (error || arg.rl_maxsegs != 1) { 1448 if (n != NULL) 1449 m_freem(n); 1450 return (ENOMEM); 1451 } 1452 1453 sc->rl_ldata.rl_rx_list[idx].rl_cmdstat |= htole32(RL_RDESC_CMD_OWN); 1454 sc->rl_ldata.rl_rx_mbuf[idx] = m; 1455 1456 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1457 sc->rl_ldata.rl_rx_dmamap[idx], 1458 BUS_DMASYNC_PREREAD); 1459 1460 return(0); 1461 } 1462 1463 static int 1464 re_tx_list_init(sc) 1465 struct rl_softc *sc; 1466 { 1467 bzero ((char *)sc->rl_ldata.rl_tx_list, RL_TX_LIST_SZ); 1468 bzero ((char *)&sc->rl_ldata.rl_tx_mbuf, 1469 (RL_TX_DESC_CNT * sizeof(struct mbuf *))); 1470 1471 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1472 sc->rl_ldata.rl_tx_list_map, BUS_DMASYNC_PREWRITE); 1473 sc->rl_ldata.rl_tx_prodidx = 0; 1474 sc->rl_ldata.rl_tx_considx = 0; 1475 sc->rl_ldata.rl_tx_free = RL_TX_DESC_CNT; 1476 1477 return(0); 1478 } 1479 1480 static int 1481 re_rx_list_init(sc) 1482 struct rl_softc *sc; 1483 { 1484 int i; 1485 1486 bzero ((char *)sc->rl_ldata.rl_rx_list, RL_RX_LIST_SZ); 1487 bzero ((char *)&sc->rl_ldata.rl_rx_mbuf, 1488 (RL_RX_DESC_CNT * sizeof(struct mbuf *))); 1489 1490 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1491 if (re_newbuf(sc, i, NULL) == ENOBUFS) 1492 return(ENOBUFS); 1493 } 1494 1495 /* Flush the RX descriptors */ 1496 1497 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1498 sc->rl_ldata.rl_rx_list_map, 1499 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1500 1501 sc->rl_ldata.rl_rx_prodidx = 0; 1502 sc->rl_head = sc->rl_tail = NULL; 1503 1504 return(0); 1505 } 1506 1507 /* 1508 * RX handler for C+ and 8169. For the gigE chips, we support 1509 * the reception of jumbo frames that have been fragmented 1510 * across multiple 2K mbuf cluster buffers. 1511 */ 1512 static void 1513 re_rxeof(sc) 1514 struct rl_softc *sc; 1515 { 1516 struct mbuf *m; 1517 struct ifnet *ifp; 1518 int i, total_len; 1519 struct rl_desc *cur_rx; 1520 u_int32_t rxstat, rxvlan; 1521 1522 ifp = &sc->arpcom.ac_if; 1523 i = sc->rl_ldata.rl_rx_prodidx; 1524 1525 /* Invalidate the descriptor memory */ 1526 1527 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1528 sc->rl_ldata.rl_rx_list_map, 1529 BUS_DMASYNC_POSTREAD); 1530 1531 while (!RL_OWN(&sc->rl_ldata.rl_rx_list[i])) { 1532 1533 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1534 m = sc->rl_ldata.rl_rx_mbuf[i]; 1535 total_len = RL_RXBYTES(cur_rx); 1536 rxstat = le32toh(cur_rx->rl_cmdstat); 1537 rxvlan = le32toh(cur_rx->rl_vlanctl); 1538 1539 /* Invalidate the RX mbuf and unload its map */ 1540 1541 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1542 sc->rl_ldata.rl_rx_dmamap[i], 1543 BUS_DMASYNC_POSTWRITE); 1544 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1545 sc->rl_ldata.rl_rx_dmamap[i]); 1546 1547 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1548 m->m_len = MCLBYTES - ETHER_ALIGN; 1549 if (sc->rl_head == NULL) 1550 sc->rl_head = sc->rl_tail = m; 1551 else { 1552 m->m_flags &= ~M_PKTHDR; 1553 sc->rl_tail->m_next = m; 1554 sc->rl_tail = m; 1555 } 1556 re_newbuf(sc, i, NULL); 1557 RL_DESC_INC(i); 1558 continue; 1559 } 1560 1561 /* 1562 * NOTE: for the 8139C+, the frame length field 1563 * is always 12 bits in size, but for the gigE chips, 1564 * it is 13 bits (since the max RX frame length is 16K). 1565 * Unfortunately, all 32 bits in the status word 1566 * were already used, so to make room for the extra 1567 * length bit, RealTek took out the 'frame alignment 1568 * error' bit and shifted the other status bits 1569 * over one slot. The OWN, EOR, FS and LS bits are 1570 * still in the same places. We have already extracted 1571 * the frame length and checked the OWN bit, so rather 1572 * than using an alternate bit mapping, we shift the 1573 * status bits one space to the right so we can evaluate 1574 * them using the 8169 status as though it was in the 1575 * same format as that of the 8139C+. 1576 */ 1577 if (sc->rl_type == RL_8169) 1578 rxstat >>= 1; 1579 1580 if (rxstat & RL_RDESC_STAT_RXERRSUM) { 1581 ifp->if_ierrors++; 1582 /* 1583 * If this is part of a multi-fragment packet, 1584 * discard all the pieces. 1585 */ 1586 if (sc->rl_head != NULL) { 1587 m_freem(sc->rl_head); 1588 sc->rl_head = sc->rl_tail = NULL; 1589 } 1590 re_newbuf(sc, i, m); 1591 RL_DESC_INC(i); 1592 continue; 1593 } 1594 1595 /* 1596 * If allocating a replacement mbuf fails, 1597 * reload the current one. 1598 */ 1599 1600 if (re_newbuf(sc, i, NULL)) { 1601 ifp->if_ierrors++; 1602 if (sc->rl_head != NULL) { 1603 m_freem(sc->rl_head); 1604 sc->rl_head = sc->rl_tail = NULL; 1605 } 1606 re_newbuf(sc, i, m); 1607 RL_DESC_INC(i); 1608 continue; 1609 } 1610 1611 RL_DESC_INC(i); 1612 1613 if (sc->rl_head != NULL) { 1614 m->m_len = total_len % (MCLBYTES - ETHER_ALIGN); 1615 /* 1616 * Special case: if there's 4 bytes or less 1617 * in this buffer, the mbuf can be discarded: 1618 * the last 4 bytes is the CRC, which we don't 1619 * care about anyway. 1620 */ 1621 if (m->m_len <= ETHER_CRC_LEN) { 1622 sc->rl_tail->m_len -= 1623 (ETHER_CRC_LEN - m->m_len); 1624 m_freem(m); 1625 } else { 1626 m->m_len -= ETHER_CRC_LEN; 1627 m->m_flags &= ~M_PKTHDR; 1628 sc->rl_tail->m_next = m; 1629 } 1630 m = sc->rl_head; 1631 sc->rl_head = sc->rl_tail = NULL; 1632 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1633 } else 1634 m->m_pkthdr.len = m->m_len = 1635 (total_len - ETHER_CRC_LEN); 1636 1637 ifp->if_ipackets++; 1638 m->m_pkthdr.rcvif = ifp; 1639 1640 /* Do RX checksumming if enabled */ 1641 1642 if (ifp->if_capenable & IFCAP_RXCSUM) { 1643 1644 /* Check IP header checksum */ 1645 if (rxstat & RL_RDESC_STAT_PROTOID) 1646 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1647 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1648 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1649 1650 /* Check TCP/UDP checksum */ 1651 if ((RL_TCPPKT(rxstat) && 1652 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1653 (RL_UDPPKT(rxstat) && 1654 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1655 m->m_pkthdr.csum_flags |= 1656 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1657 m->m_pkthdr.csum_data = 0xffff; 1658 } 1659 } 1660 1661 if (rxvlan & RL_RDESC_VLANCTL_TAG) 1662 VLAN_INPUT_TAG(ifp, m, 1663 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)), continue); 1664 (*ifp->if_input)(ifp, m); 1665 } 1666 1667 /* Flush the RX DMA ring */ 1668 1669 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1670 sc->rl_ldata.rl_rx_list_map, 1671 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1672 1673 sc->rl_ldata.rl_rx_prodidx = i; 1674 1675 return; 1676 } 1677 1678 static void 1679 re_txeof(sc) 1680 struct rl_softc *sc; 1681 { 1682 struct ifnet *ifp; 1683 u_int32_t txstat; 1684 int idx; 1685 1686 ifp = &sc->arpcom.ac_if; 1687 idx = sc->rl_ldata.rl_tx_considx; 1688 1689 /* Invalidate the TX descriptor list */ 1690 1691 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1692 sc->rl_ldata.rl_tx_list_map, 1693 BUS_DMASYNC_POSTREAD); 1694 1695 while (idx != sc->rl_ldata.rl_tx_prodidx) { 1696 1697 txstat = le32toh(sc->rl_ldata.rl_tx_list[idx].rl_cmdstat); 1698 if (txstat & RL_TDESC_CMD_OWN) 1699 break; 1700 1701 /* 1702 * We only stash mbufs in the last descriptor 1703 * in a fragment chain, which also happens to 1704 * be the only place where the TX status bits 1705 * are valid. 1706 */ 1707 1708 if (txstat & RL_TDESC_CMD_EOF) { 1709 m_freem(sc->rl_ldata.rl_tx_mbuf[idx]); 1710 sc->rl_ldata.rl_tx_mbuf[idx] = NULL; 1711 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1712 sc->rl_ldata.rl_tx_dmamap[idx]); 1713 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 1714 RL_TDESC_STAT_COLCNT)) 1715 ifp->if_collisions++; 1716 if (txstat & RL_TDESC_STAT_TXERRSUM) 1717 ifp->if_oerrors++; 1718 else 1719 ifp->if_opackets++; 1720 } 1721 sc->rl_ldata.rl_tx_free++; 1722 RL_DESC_INC(idx); 1723 } 1724 1725 /* No changes made to the TX ring, so no flush needed */ 1726 1727 if (idx != sc->rl_ldata.rl_tx_considx) { 1728 sc->rl_ldata.rl_tx_considx = idx; 1729 ifp->if_flags &= ~IFF_OACTIVE; 1730 ifp->if_timer = 0; 1731 } 1732 1733 /* 1734 * If not all descriptors have been released reaped yet, 1735 * reload the timer so that we will eventually get another 1736 * interrupt that will cause us to re-enter this routine. 1737 * This is done in case the transmitter has gone idle. 1738 */ 1739 if (sc->rl_ldata.rl_tx_free != RL_TX_DESC_CNT) 1740 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 1741 1742 return; 1743 } 1744 1745 static void 1746 re_tick(xsc) 1747 void *xsc; 1748 { 1749 struct rl_softc *sc; 1750 struct mii_data *mii; 1751 1752 sc = xsc; 1753 RL_LOCK(sc); 1754 mii = device_get_softc(sc->rl_miibus); 1755 1756 mii_tick(mii); 1757 1758 sc->rl_stat_ch = timeout(re_tick, sc, hz); 1759 RL_UNLOCK(sc); 1760 1761 return; 1762 } 1763 1764 #ifdef DEVICE_POLLING 1765 static void 1766 re_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1767 { 1768 struct rl_softc *sc = ifp->if_softc; 1769 1770 RL_LOCK(sc); 1771 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1772 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 1773 goto done; 1774 } 1775 1776 sc->rxcycles = count; 1777 re_rxeof(sc); 1778 re_txeof(sc); 1779 1780 if (ifp->if_snd.ifq_head != NULL) 1781 (*ifp->if_start)(ifp); 1782 1783 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1784 u_int16_t status; 1785 1786 status = CSR_READ_2(sc, RL_ISR); 1787 if (status == 0xffff) 1788 goto done; 1789 if (status) 1790 CSR_WRITE_2(sc, RL_ISR, status); 1791 1792 /* 1793 * XXX check behaviour on receiver stalls. 1794 */ 1795 1796 if (status & RL_ISR_SYSTEM_ERR) { 1797 re_reset(sc); 1798 re_init(sc); 1799 } 1800 } 1801 done: 1802 RL_UNLOCK(sc); 1803 } 1804 #endif /* DEVICE_POLLING */ 1805 1806 static void 1807 re_intr(arg) 1808 void *arg; 1809 { 1810 struct rl_softc *sc; 1811 struct ifnet *ifp; 1812 u_int16_t status; 1813 1814 sc = arg; 1815 1816 if (sc->suspended) { 1817 return; 1818 } 1819 1820 RL_LOCK(sc); 1821 ifp = &sc->arpcom.ac_if; 1822 1823 if (!(ifp->if_flags & IFF_UP)) { 1824 RL_UNLOCK(sc); 1825 return; 1826 } 1827 1828 #ifdef DEVICE_POLLING 1829 if (ifp->if_flags & IFF_POLLING) 1830 goto done; 1831 if (ether_poll_register(re_poll, ifp)) { /* ok, disable interrupts */ 1832 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1833 re_poll(ifp, 0, 1); 1834 goto done; 1835 } 1836 #endif /* DEVICE_POLLING */ 1837 1838 for (;;) { 1839 1840 status = CSR_READ_2(sc, RL_ISR); 1841 /* If the card has gone away the read returns 0xffff. */ 1842 if (status == 0xffff) 1843 break; 1844 if (status) 1845 CSR_WRITE_2(sc, RL_ISR, status); 1846 1847 if ((status & RL_INTRS_CPLUS) == 0) 1848 break; 1849 1850 if (status & RL_ISR_RX_OK) 1851 re_rxeof(sc); 1852 1853 if (status & RL_ISR_RX_ERR) 1854 re_rxeof(sc); 1855 1856 if ((status & RL_ISR_TIMEOUT_EXPIRED) || 1857 (status & RL_ISR_TX_ERR) || 1858 (status & RL_ISR_TX_DESC_UNAVAIL)) 1859 re_txeof(sc); 1860 1861 if (status & RL_ISR_SYSTEM_ERR) { 1862 re_reset(sc); 1863 re_init(sc); 1864 } 1865 1866 if (status & RL_ISR_LINKCHG) { 1867 untimeout(re_tick, sc, sc->rl_stat_ch); 1868 re_tick(sc); 1869 } 1870 } 1871 1872 if (ifp->if_snd.ifq_head != NULL) 1873 (*ifp->if_start)(ifp); 1874 1875 #ifdef DEVICE_POLLING 1876 done: 1877 #endif 1878 RL_UNLOCK(sc); 1879 1880 return; 1881 } 1882 1883 static int 1884 re_encap(sc, m_head, idx) 1885 struct rl_softc *sc; 1886 struct mbuf *m_head; 1887 int *idx; 1888 { 1889 struct mbuf *m_new = NULL; 1890 struct rl_dmaload_arg arg; 1891 bus_dmamap_t map; 1892 int error; 1893 struct m_tag *mtag; 1894 1895 if (sc->rl_ldata.rl_tx_free <= 4) 1896 return(EFBIG); 1897 1898 /* 1899 * Set up checksum offload. Note: checksum offload bits must 1900 * appear in all descriptors of a multi-descriptor transmit 1901 * attempt. (This is according to testing done with an 8169 1902 * chip. I'm not sure if this is a requirement or a bug.) 1903 */ 1904 1905 arg.rl_flags = 0; 1906 1907 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1908 arg.rl_flags |= RL_TDESC_CMD_IPCSUM; 1909 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1910 arg.rl_flags |= RL_TDESC_CMD_TCPCSUM; 1911 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1912 arg.rl_flags |= RL_TDESC_CMD_UDPCSUM; 1913 1914 arg.sc = sc; 1915 arg.rl_idx = *idx; 1916 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 1917 if (arg.rl_maxsegs > 4) 1918 arg.rl_maxsegs -= 4; 1919 arg.rl_ring = sc->rl_ldata.rl_tx_list; 1920 1921 map = sc->rl_ldata.rl_tx_dmamap[*idx]; 1922 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 1923 m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1924 1925 if (error && error != EFBIG) { 1926 printf("re%d: can't map mbuf (error %d)\n", sc->rl_unit, error); 1927 return(ENOBUFS); 1928 } 1929 1930 /* Too many segments to map, coalesce into a single mbuf */ 1931 1932 if (error || arg.rl_maxsegs == 0) { 1933 m_new = m_defrag(m_head, M_DONTWAIT); 1934 if (m_new == NULL) 1935 return(1); 1936 else 1937 m_head = m_new; 1938 1939 arg.sc = sc; 1940 arg.rl_idx = *idx; 1941 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 1942 arg.rl_ring = sc->rl_ldata.rl_tx_list; 1943 1944 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 1945 m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1946 if (error) { 1947 printf("re%d: can't map mbuf (error %d)\n", 1948 sc->rl_unit, error); 1949 return(EFBIG); 1950 } 1951 } 1952 1953 /* 1954 * Insure that the map for this transmission 1955 * is placed at the array index of the last descriptor 1956 * in this chain. 1957 */ 1958 sc->rl_ldata.rl_tx_dmamap[*idx] = 1959 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx]; 1960 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx] = map; 1961 1962 sc->rl_ldata.rl_tx_mbuf[arg.rl_idx] = m_head; 1963 sc->rl_ldata.rl_tx_free -= arg.rl_maxsegs; 1964 1965 /* 1966 * Set up hardware VLAN tagging. Note: vlan tag info must 1967 * appear in the first descriptor of a multi-descriptor 1968 * transmission attempt. 1969 */ 1970 1971 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m_head); 1972 if (mtag != NULL) 1973 sc->rl_ldata.rl_tx_list[*idx].rl_vlanctl = 1974 htole32(htons(VLAN_TAG_VALUE(mtag)) | RL_TDESC_VLANCTL_TAG); 1975 1976 /* Transfer ownership of packet to the chip. */ 1977 1978 sc->rl_ldata.rl_tx_list[arg.rl_idx].rl_cmdstat |= 1979 htole32(RL_TDESC_CMD_OWN); 1980 if (*idx != arg.rl_idx) 1981 sc->rl_ldata.rl_tx_list[*idx].rl_cmdstat |= 1982 htole32(RL_TDESC_CMD_OWN); 1983 1984 RL_DESC_INC(arg.rl_idx); 1985 *idx = arg.rl_idx; 1986 1987 return(0); 1988 } 1989 1990 /* 1991 * Main transmit routine for C+ and gigE NICs. 1992 */ 1993 1994 static void 1995 re_start(ifp) 1996 struct ifnet *ifp; 1997 { 1998 struct rl_softc *sc; 1999 struct mbuf *m_head = NULL; 2000 int idx; 2001 2002 sc = ifp->if_softc; 2003 RL_LOCK(sc); 2004 2005 idx = sc->rl_ldata.rl_tx_prodidx; 2006 2007 while (sc->rl_ldata.rl_tx_mbuf[idx] == NULL) { 2008 IF_DEQUEUE(&ifp->if_snd, m_head); 2009 if (m_head == NULL) 2010 break; 2011 2012 if (re_encap(sc, m_head, &idx)) { 2013 IF_PREPEND(&ifp->if_snd, m_head); 2014 ifp->if_flags |= IFF_OACTIVE; 2015 break; 2016 } 2017 2018 /* 2019 * If there's a BPF listener, bounce a copy of this frame 2020 * to him. 2021 */ 2022 BPF_MTAP(ifp, m_head); 2023 } 2024 2025 /* Flush the TX descriptors */ 2026 2027 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2028 sc->rl_ldata.rl_tx_list_map, 2029 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2030 2031 sc->rl_ldata.rl_tx_prodidx = idx; 2032 2033 /* 2034 * RealTek put the TX poll request register in a different 2035 * location on the 8169 gigE chip. I don't know why. 2036 */ 2037 2038 if (sc->rl_type == RL_8169) 2039 CSR_WRITE_2(sc, RL_GTXSTART, RL_TXSTART_START); 2040 else 2041 CSR_WRITE_2(sc, RL_TXSTART, RL_TXSTART_START); 2042 2043 /* 2044 * Use the countdown timer for interrupt moderation. 2045 * 'TX done' interrupts are disabled. Instead, we reset the 2046 * countdown timer, which will begin counting until it hits 2047 * the value in the TIMERINT register, and then trigger an 2048 * interrupt. Each time we write to the TIMERCNT register, 2049 * the timer count is reset to 0. 2050 */ 2051 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2052 2053 RL_UNLOCK(sc); 2054 2055 /* 2056 * Set a timeout in case the chip goes out to lunch. 2057 */ 2058 ifp->if_timer = 5; 2059 2060 return; 2061 } 2062 2063 static void 2064 re_init(xsc) 2065 void *xsc; 2066 { 2067 struct rl_softc *sc = xsc; 2068 struct ifnet *ifp = &sc->arpcom.ac_if; 2069 struct mii_data *mii; 2070 u_int32_t rxcfg = 0; 2071 2072 RL_LOCK(sc); 2073 mii = device_get_softc(sc->rl_miibus); 2074 2075 /* 2076 * Cancel pending I/O and free all RX/TX buffers. 2077 */ 2078 re_stop(sc); 2079 2080 /* 2081 * Enable C+ RX and TX mode, as well as VLAN stripping and 2082 * RX checksum offload. We must configure the C+ register 2083 * before all others. 2084 */ 2085 CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB| 2086 RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW| 2087 RL_CPLUSCMD_VLANSTRIP| 2088 (ifp->if_capenable & IFCAP_RXCSUM ? 2089 RL_CPLUSCMD_RXCSUM_ENB : 0)); 2090 2091 /* 2092 * Init our MAC address. Even though the chipset 2093 * documentation doesn't mention it, we need to enter "Config 2094 * register write enable" mode to modify the ID registers. 2095 */ 2096 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2097 CSR_WRITE_STREAM_4(sc, RL_IDR0, 2098 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 2099 CSR_WRITE_STREAM_4(sc, RL_IDR4, 2100 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 2101 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2102 2103 /* 2104 * For C+ mode, initialize the RX descriptors and mbufs. 2105 */ 2106 re_rx_list_init(sc); 2107 re_tx_list_init(sc); 2108 2109 /* 2110 * Enable transmit and receive. 2111 */ 2112 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2113 2114 /* 2115 * Set the initial TX and RX configuration. 2116 */ 2117 if (sc->rl_testmode) { 2118 if (sc->rl_type == RL_8169) 2119 CSR_WRITE_4(sc, RL_TXCFG, 2120 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2121 else 2122 CSR_WRITE_4(sc, RL_TXCFG, 2123 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2124 } else 2125 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2126 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 2127 2128 /* Set the individual bit to receive frames for this host only. */ 2129 rxcfg = CSR_READ_4(sc, RL_RXCFG); 2130 rxcfg |= RL_RXCFG_RX_INDIV; 2131 2132 /* If we want promiscuous mode, set the allframes bit. */ 2133 if (ifp->if_flags & IFF_PROMISC) { 2134 rxcfg |= RL_RXCFG_RX_ALLPHYS; 2135 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2136 } else { 2137 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 2138 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2139 } 2140 2141 /* 2142 * Set capture broadcast bit to capture broadcast frames. 2143 */ 2144 if (ifp->if_flags & IFF_BROADCAST) { 2145 rxcfg |= RL_RXCFG_RX_BROAD; 2146 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2147 } else { 2148 rxcfg &= ~RL_RXCFG_RX_BROAD; 2149 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2150 } 2151 2152 /* 2153 * Program the multicast filter, if necessary. 2154 */ 2155 re_setmulti(sc); 2156 2157 #ifdef DEVICE_POLLING 2158 /* 2159 * Disable interrupts if we are polling. 2160 */ 2161 if (ifp->if_flags & IFF_POLLING) 2162 CSR_WRITE_2(sc, RL_IMR, 0); 2163 else /* otherwise ... */ 2164 #endif /* DEVICE_POLLING */ 2165 /* 2166 * Enable interrupts. 2167 */ 2168 if (sc->rl_testmode) 2169 CSR_WRITE_2(sc, RL_IMR, 0); 2170 else 2171 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2172 2173 /* Set initial TX threshold */ 2174 sc->rl_txthresh = RL_TX_THRESH_INIT; 2175 2176 /* Start RX/TX process. */ 2177 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2178 #ifdef notdef 2179 /* Enable receiver and transmitter. */ 2180 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2181 #endif 2182 /* 2183 * Load the addresses of the RX and TX lists into the chip. 2184 */ 2185 2186 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2187 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2188 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2189 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2190 2191 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2192 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2193 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2194 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2195 2196 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2197 2198 /* 2199 * Initialize the timer interrupt register so that 2200 * a timer interrupt will be generated once the timer 2201 * reaches a certain number of ticks. The timer is 2202 * reloaded on each transmit. This gives us TX interrupt 2203 * moderation, which dramatically improves TX frame rate. 2204 */ 2205 2206 if (sc->rl_type == RL_8169) 2207 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2208 else 2209 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2210 2211 /* 2212 * For 8169 gigE NICs, set the max allowed RX packet 2213 * size so we can receive jumbo frames. 2214 */ 2215 if (sc->rl_type == RL_8169) 2216 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2217 2218 if (sc->rl_testmode) { 2219 RL_UNLOCK(sc); 2220 return; 2221 } 2222 2223 mii_mediachg(mii); 2224 2225 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 2226 2227 ifp->if_flags |= IFF_RUNNING; 2228 ifp->if_flags &= ~IFF_OACTIVE; 2229 2230 sc->rl_stat_ch = timeout(re_tick, sc, hz); 2231 RL_UNLOCK(sc); 2232 2233 return; 2234 } 2235 2236 /* 2237 * Set media options. 2238 */ 2239 static int 2240 re_ifmedia_upd(ifp) 2241 struct ifnet *ifp; 2242 { 2243 struct rl_softc *sc; 2244 struct mii_data *mii; 2245 2246 sc = ifp->if_softc; 2247 mii = device_get_softc(sc->rl_miibus); 2248 mii_mediachg(mii); 2249 2250 return(0); 2251 } 2252 2253 /* 2254 * Report current media status. 2255 */ 2256 static void 2257 re_ifmedia_sts(ifp, ifmr) 2258 struct ifnet *ifp; 2259 struct ifmediareq *ifmr; 2260 { 2261 struct rl_softc *sc; 2262 struct mii_data *mii; 2263 2264 sc = ifp->if_softc; 2265 mii = device_get_softc(sc->rl_miibus); 2266 2267 mii_pollstat(mii); 2268 ifmr->ifm_active = mii->mii_media_active; 2269 ifmr->ifm_status = mii->mii_media_status; 2270 2271 return; 2272 } 2273 2274 static int 2275 re_ioctl(ifp, command, data) 2276 struct ifnet *ifp; 2277 u_long command; 2278 caddr_t data; 2279 { 2280 struct rl_softc *sc = ifp->if_softc; 2281 struct ifreq *ifr = (struct ifreq *) data; 2282 struct mii_data *mii; 2283 int error = 0; 2284 2285 RL_LOCK(sc); 2286 2287 switch(command) { 2288 case SIOCSIFMTU: 2289 if (ifr->ifr_mtu > RL_JUMBO_MTU) 2290 error = EINVAL; 2291 ifp->if_mtu = ifr->ifr_mtu; 2292 break; 2293 case SIOCSIFFLAGS: 2294 if (ifp->if_flags & IFF_UP) { 2295 re_init(sc); 2296 } else { 2297 if (ifp->if_flags & IFF_RUNNING) 2298 re_stop(sc); 2299 } 2300 error = 0; 2301 break; 2302 case SIOCADDMULTI: 2303 case SIOCDELMULTI: 2304 re_setmulti(sc); 2305 error = 0; 2306 break; 2307 case SIOCGIFMEDIA: 2308 case SIOCSIFMEDIA: 2309 mii = device_get_softc(sc->rl_miibus); 2310 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2311 break; 2312 case SIOCSIFCAP: 2313 ifp->if_capenable = ifr->ifr_reqcap; 2314 if (ifp->if_capenable & IFCAP_TXCSUM) 2315 ifp->if_hwassist = RE_CSUM_FEATURES; 2316 else 2317 ifp->if_hwassist = 0; 2318 if (ifp->if_flags & IFF_RUNNING) 2319 re_init(sc); 2320 break; 2321 default: 2322 error = ether_ioctl(ifp, command, data); 2323 break; 2324 } 2325 2326 RL_UNLOCK(sc); 2327 2328 return(error); 2329 } 2330 2331 static void 2332 re_watchdog(ifp) 2333 struct ifnet *ifp; 2334 { 2335 struct rl_softc *sc; 2336 2337 sc = ifp->if_softc; 2338 RL_LOCK(sc); 2339 printf("re%d: watchdog timeout\n", sc->rl_unit); 2340 ifp->if_oerrors++; 2341 2342 re_txeof(sc); 2343 re_rxeof(sc); 2344 2345 re_init(sc); 2346 2347 RL_UNLOCK(sc); 2348 2349 return; 2350 } 2351 2352 /* 2353 * Stop the adapter and free any mbufs allocated to the 2354 * RX and TX lists. 2355 */ 2356 static void 2357 re_stop(sc) 2358 struct rl_softc *sc; 2359 { 2360 register int i; 2361 struct ifnet *ifp; 2362 2363 RL_LOCK(sc); 2364 ifp = &sc->arpcom.ac_if; 2365 ifp->if_timer = 0; 2366 2367 untimeout(re_tick, sc, sc->rl_stat_ch); 2368 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2369 #ifdef DEVICE_POLLING 2370 ether_poll_deregister(ifp); 2371 #endif /* DEVICE_POLLING */ 2372 2373 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2374 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2375 2376 if (sc->rl_head != NULL) { 2377 m_freem(sc->rl_head); 2378 sc->rl_head = sc->rl_tail = NULL; 2379 } 2380 2381 /* Free the TX list buffers. */ 2382 2383 for (i = 0; i < RL_TX_DESC_CNT; i++) { 2384 if (sc->rl_ldata.rl_tx_mbuf[i] != NULL) { 2385 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2386 sc->rl_ldata.rl_tx_dmamap[i]); 2387 m_freem(sc->rl_ldata.rl_tx_mbuf[i]); 2388 sc->rl_ldata.rl_tx_mbuf[i] = NULL; 2389 } 2390 } 2391 2392 /* Free the RX list buffers. */ 2393 2394 for (i = 0; i < RL_RX_DESC_CNT; i++) { 2395 if (sc->rl_ldata.rl_rx_mbuf[i] != NULL) { 2396 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2397 sc->rl_ldata.rl_rx_dmamap[i]); 2398 m_freem(sc->rl_ldata.rl_rx_mbuf[i]); 2399 sc->rl_ldata.rl_rx_mbuf[i] = NULL; 2400 } 2401 } 2402 2403 RL_UNLOCK(sc); 2404 return; 2405 } 2406 2407 /* 2408 * Device suspend routine. Stop the interface and save some PCI 2409 * settings in case the BIOS doesn't restore them properly on 2410 * resume. 2411 */ 2412 static int 2413 re_suspend(dev) 2414 device_t dev; 2415 { 2416 register int i; 2417 struct rl_softc *sc; 2418 2419 sc = device_get_softc(dev); 2420 2421 re_stop(sc); 2422 2423 for (i = 0; i < 5; i++) 2424 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 2425 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 2426 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 2427 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2428 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2429 2430 sc->suspended = 1; 2431 2432 return (0); 2433 } 2434 2435 /* 2436 * Device resume routine. Restore some PCI settings in case the BIOS 2437 * doesn't, re-enable busmastering, and restart the interface if 2438 * appropriate. 2439 */ 2440 static int 2441 re_resume(dev) 2442 device_t dev; 2443 { 2444 register int i; 2445 struct rl_softc *sc; 2446 struct ifnet *ifp; 2447 2448 sc = device_get_softc(dev); 2449 ifp = &sc->arpcom.ac_if; 2450 2451 /* better way to do this? */ 2452 for (i = 0; i < 5; i++) 2453 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 2454 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 2455 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 2456 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 2457 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 2458 2459 /* reenable busmastering */ 2460 pci_enable_busmaster(dev); 2461 pci_enable_io(dev, RL_RES); 2462 2463 /* reinitialize interface if necessary */ 2464 if (ifp->if_flags & IFF_UP) 2465 re_init(sc); 2466 2467 sc->suspended = 0; 2468 2469 return (0); 2470 } 2471 2472 /* 2473 * Stop all chip I/O so that the kernel's probe routines don't 2474 * get confused by errant DMAs when rebooting. 2475 */ 2476 static void 2477 re_shutdown(dev) 2478 device_t dev; 2479 { 2480 struct rl_softc *sc; 2481 2482 sc = device_get_softc(dev); 2483 2484 re_stop(sc); 2485 2486 return; 2487 } 2488