1 /* 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44 /* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S 48 * and the RTL8110S. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7.5K, so the max MTU possible with this 108 * driver is 7500 bytes. 109 */ 110 111 #include <sys/param.h> 112 #include <sys/endian.h> 113 #include <sys/systm.h> 114 #include <sys/sockio.h> 115 #include <sys/mbuf.h> 116 #include <sys/malloc.h> 117 #include <sys/module.h> 118 #include <sys/kernel.h> 119 #include <sys/socket.h> 120 121 #include <net/if.h> 122 #include <net/if_arp.h> 123 #include <net/ethernet.h> 124 #include <net/if_dl.h> 125 #include <net/if_media.h> 126 #include <net/if_vlan_var.h> 127 128 #include <net/bpf.h> 129 130 #include <machine/bus_pio.h> 131 #include <machine/bus_memio.h> 132 #include <machine/bus.h> 133 #include <machine/resource.h> 134 #include <sys/bus.h> 135 #include <sys/rman.h> 136 137 #include <dev/mii/mii.h> 138 #include <dev/mii/miivar.h> 139 140 #include <dev/pci/pcireg.h> 141 #include <dev/pci/pcivar.h> 142 143 MODULE_DEPEND(re, pci, 1, 1, 1); 144 MODULE_DEPEND(re, ether, 1, 1, 1); 145 MODULE_DEPEND(re, miibus, 1, 1, 1); 146 147 /* "controller miibus0" required. See GENERIC if you get errors here. */ 148 #include "miibus_if.h" 149 150 /* 151 * Default to using PIO access for this driver. 152 */ 153 #define RE_USEIOSPACE 154 155 #include <pci/if_rlreg.h> 156 157 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 158 159 /* 160 * Various supported device vendors/types and their names. 161 */ 162 static struct rl_type re_devs[] = { 163 { RT_VENDORID, RT_DEVICEID_8139, RL_HWREV_8139CPLUS, 164 "RealTek 8139C+ 10/100BaseTX" }, 165 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169, 166 "RealTek 8169 Gigabit Ethernet" }, 167 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169S, 168 "RealTek 8169S Single-chip Gigabit Ethernet" }, 169 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8110S, 170 "RealTek 8110S Single-chip Gigabit Ethernet" }, 171 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, RL_HWREV_8169S, 172 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 173 { 0, 0, 0, NULL } 174 }; 175 176 static struct rl_hwrev re_hwrevs[] = { 177 { RL_HWREV_8139, RL_8139, "" }, 178 { RL_HWREV_8139A, RL_8139, "A" }, 179 { RL_HWREV_8139AG, RL_8139, "A-G" }, 180 { RL_HWREV_8139B, RL_8139, "B" }, 181 { RL_HWREV_8130, RL_8139, "8130" }, 182 { RL_HWREV_8139C, RL_8139, "C" }, 183 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 184 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 185 { RL_HWREV_8169, RL_8169, "8169"}, 186 { RL_HWREV_8169S, RL_8169, "8169S"}, 187 { RL_HWREV_8110S, RL_8169, "8110S"}, 188 { RL_HWREV_8100, RL_8139, "8100"}, 189 { RL_HWREV_8101, RL_8139, "8101"}, 190 { 0, 0, NULL } 191 }; 192 193 static int re_probe (device_t); 194 static int re_attach (device_t); 195 static int re_detach (device_t); 196 197 static int re_encap (struct rl_softc *, struct mbuf *, int *); 198 199 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 200 static void re_dma_map_desc (void *, bus_dma_segment_t *, int, 201 bus_size_t, int); 202 static int re_allocmem (device_t, struct rl_softc *); 203 static int re_newbuf (struct rl_softc *, int, struct mbuf *); 204 static int re_rx_list_init (struct rl_softc *); 205 static int re_tx_list_init (struct rl_softc *); 206 static void re_rxeof (struct rl_softc *); 207 static void re_txeof (struct rl_softc *); 208 static void re_intr (void *); 209 static void re_tick (void *); 210 static void re_start (struct ifnet *); 211 static int re_ioctl (struct ifnet *, u_long, caddr_t); 212 static void re_init (void *); 213 static void re_stop (struct rl_softc *); 214 static void re_watchdog (struct ifnet *); 215 static int re_suspend (device_t); 216 static int re_resume (device_t); 217 static void re_shutdown (device_t); 218 static int re_ifmedia_upd (struct ifnet *); 219 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 220 221 static void re_eeprom_putbyte (struct rl_softc *, int); 222 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 223 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int, int); 224 static int re_gmii_readreg (device_t, int, int); 225 static int re_gmii_writereg (device_t, int, int, int); 226 227 static int re_miibus_readreg (device_t, int, int); 228 static int re_miibus_writereg (device_t, int, int, int); 229 static void re_miibus_statchg (device_t); 230 231 static void re_setmulti (struct rl_softc *); 232 static void re_reset (struct rl_softc *); 233 234 static int re_diag (struct rl_softc *); 235 236 #ifdef RE_USEIOSPACE 237 #define RL_RES SYS_RES_IOPORT 238 #define RL_RID RL_PCI_LOIO 239 #else 240 #define RL_RES SYS_RES_MEMORY 241 #define RL_RID RL_PCI_LOMEM 242 #endif 243 244 static device_method_t re_methods[] = { 245 /* Device interface */ 246 DEVMETHOD(device_probe, re_probe), 247 DEVMETHOD(device_attach, re_attach), 248 DEVMETHOD(device_detach, re_detach), 249 DEVMETHOD(device_suspend, re_suspend), 250 DEVMETHOD(device_resume, re_resume), 251 DEVMETHOD(device_shutdown, re_shutdown), 252 253 /* bus interface */ 254 DEVMETHOD(bus_print_child, bus_generic_print_child), 255 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 256 257 /* MII interface */ 258 DEVMETHOD(miibus_readreg, re_miibus_readreg), 259 DEVMETHOD(miibus_writereg, re_miibus_writereg), 260 DEVMETHOD(miibus_statchg, re_miibus_statchg), 261 262 { 0, 0 } 263 }; 264 265 static driver_t re_driver = { 266 "re", 267 re_methods, 268 sizeof(struct rl_softc) 269 }; 270 271 static devclass_t re_devclass; 272 273 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 274 DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0); 275 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 276 277 #define EE_SET(x) \ 278 CSR_WRITE_1(sc, RL_EECMD, \ 279 CSR_READ_1(sc, RL_EECMD) | x) 280 281 #define EE_CLR(x) \ 282 CSR_WRITE_1(sc, RL_EECMD, \ 283 CSR_READ_1(sc, RL_EECMD) & ~x) 284 285 /* 286 * Send a read command and address to the EEPROM, check for ACK. 287 */ 288 static void 289 re_eeprom_putbyte(sc, addr) 290 struct rl_softc *sc; 291 int addr; 292 { 293 register int d, i; 294 295 d = addr | sc->rl_eecmd_read; 296 297 /* 298 * Feed in each bit and strobe the clock. 299 */ 300 for (i = 0x400; i; i >>= 1) { 301 if (d & i) { 302 EE_SET(RL_EE_DATAIN); 303 } else { 304 EE_CLR(RL_EE_DATAIN); 305 } 306 DELAY(100); 307 EE_SET(RL_EE_CLK); 308 DELAY(150); 309 EE_CLR(RL_EE_CLK); 310 DELAY(100); 311 } 312 } 313 314 /* 315 * Read a word of data stored in the EEPROM at address 'addr.' 316 */ 317 static void 318 re_eeprom_getword(sc, addr, dest) 319 struct rl_softc *sc; 320 int addr; 321 u_int16_t *dest; 322 { 323 register int i; 324 u_int16_t word = 0; 325 326 /* Enter EEPROM access mode. */ 327 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 328 329 /* 330 * Send address of word we want to read. 331 */ 332 re_eeprom_putbyte(sc, addr); 333 334 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 335 336 /* 337 * Start reading bits from EEPROM. 338 */ 339 for (i = 0x8000; i; i >>= 1) { 340 EE_SET(RL_EE_CLK); 341 DELAY(100); 342 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 343 word |= i; 344 EE_CLR(RL_EE_CLK); 345 DELAY(100); 346 } 347 348 /* Turn off EEPROM access mode. */ 349 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 350 351 *dest = word; 352 } 353 354 /* 355 * Read a sequence of words from the EEPROM. 356 */ 357 static void 358 re_read_eeprom(sc, dest, off, cnt, swap) 359 struct rl_softc *sc; 360 caddr_t dest; 361 int off; 362 int cnt; 363 int swap; 364 { 365 int i; 366 u_int16_t word = 0, *ptr; 367 368 for (i = 0; i < cnt; i++) { 369 re_eeprom_getword(sc, off + i, &word); 370 ptr = (u_int16_t *)(dest + (i * 2)); 371 if (swap) 372 *ptr = ntohs(word); 373 else 374 *ptr = word; 375 } 376 } 377 378 static int 379 re_gmii_readreg(dev, phy, reg) 380 device_t dev; 381 int phy, reg; 382 { 383 struct rl_softc *sc; 384 u_int32_t rval; 385 int i; 386 387 if (phy != 1) 388 return (0); 389 390 sc = device_get_softc(dev); 391 392 /* Let the rgephy driver read the GMEDIASTAT register */ 393 394 if (reg == RL_GMEDIASTAT) { 395 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 396 return (rval); 397 } 398 399 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 400 DELAY(1000); 401 402 for (i = 0; i < RL_TIMEOUT; i++) { 403 rval = CSR_READ_4(sc, RL_PHYAR); 404 if (rval & RL_PHYAR_BUSY) 405 break; 406 DELAY(100); 407 } 408 409 if (i == RL_TIMEOUT) { 410 printf ("re%d: PHY read failed\n", sc->rl_unit); 411 return (0); 412 } 413 414 return (rval & RL_PHYAR_PHYDATA); 415 } 416 417 static int 418 re_gmii_writereg(dev, phy, reg, data) 419 device_t dev; 420 int phy, reg, data; 421 { 422 struct rl_softc *sc; 423 u_int32_t rval; 424 int i; 425 426 sc = device_get_softc(dev); 427 428 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 429 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 430 DELAY(1000); 431 432 for (i = 0; i < RL_TIMEOUT; i++) { 433 rval = CSR_READ_4(sc, RL_PHYAR); 434 if (!(rval & RL_PHYAR_BUSY)) 435 break; 436 DELAY(100); 437 } 438 439 if (i == RL_TIMEOUT) { 440 printf ("re%d: PHY write failed\n", sc->rl_unit); 441 return (0); 442 } 443 444 return (0); 445 } 446 447 static int 448 re_miibus_readreg(dev, phy, reg) 449 device_t dev; 450 int phy, reg; 451 { 452 struct rl_softc *sc; 453 u_int16_t rval = 0; 454 u_int16_t re8139_reg = 0; 455 456 sc = device_get_softc(dev); 457 RL_LOCK(sc); 458 459 if (sc->rl_type == RL_8169) { 460 rval = re_gmii_readreg(dev, phy, reg); 461 RL_UNLOCK(sc); 462 return (rval); 463 } 464 465 /* Pretend the internal PHY is only at address 0 */ 466 if (phy) { 467 RL_UNLOCK(sc); 468 return (0); 469 } 470 switch (reg) { 471 case MII_BMCR: 472 re8139_reg = RL_BMCR; 473 break; 474 case MII_BMSR: 475 re8139_reg = RL_BMSR; 476 break; 477 case MII_ANAR: 478 re8139_reg = RL_ANAR; 479 break; 480 case MII_ANER: 481 re8139_reg = RL_ANER; 482 break; 483 case MII_ANLPAR: 484 re8139_reg = RL_LPAR; 485 break; 486 case MII_PHYIDR1: 487 case MII_PHYIDR2: 488 RL_UNLOCK(sc); 489 return (0); 490 /* 491 * Allow the rlphy driver to read the media status 492 * register. If we have a link partner which does not 493 * support NWAY, this is the register which will tell 494 * us the results of parallel detection. 495 */ 496 case RL_MEDIASTAT: 497 rval = CSR_READ_1(sc, RL_MEDIASTAT); 498 RL_UNLOCK(sc); 499 return (rval); 500 default: 501 printf("re%d: bad phy register\n", sc->rl_unit); 502 RL_UNLOCK(sc); 503 return (0); 504 } 505 rval = CSR_READ_2(sc, re8139_reg); 506 RL_UNLOCK(sc); 507 return (rval); 508 } 509 510 static int 511 re_miibus_writereg(dev, phy, reg, data) 512 device_t dev; 513 int phy, reg, data; 514 { 515 struct rl_softc *sc; 516 u_int16_t re8139_reg = 0; 517 int rval = 0; 518 519 sc = device_get_softc(dev); 520 RL_LOCK(sc); 521 522 if (sc->rl_type == RL_8169) { 523 rval = re_gmii_writereg(dev, phy, reg, data); 524 RL_UNLOCK(sc); 525 return (rval); 526 } 527 528 /* Pretend the internal PHY is only at address 0 */ 529 if (phy) { 530 RL_UNLOCK(sc); 531 return (0); 532 } 533 switch (reg) { 534 case MII_BMCR: 535 re8139_reg = RL_BMCR; 536 break; 537 case MII_BMSR: 538 re8139_reg = RL_BMSR; 539 break; 540 case MII_ANAR: 541 re8139_reg = RL_ANAR; 542 break; 543 case MII_ANER: 544 re8139_reg = RL_ANER; 545 break; 546 case MII_ANLPAR: 547 re8139_reg = RL_LPAR; 548 break; 549 case MII_PHYIDR1: 550 case MII_PHYIDR2: 551 RL_UNLOCK(sc); 552 return (0); 553 break; 554 default: 555 printf("re%d: bad phy register\n", sc->rl_unit); 556 RL_UNLOCK(sc); 557 return (0); 558 } 559 CSR_WRITE_2(sc, re8139_reg, data); 560 RL_UNLOCK(sc); 561 return (0); 562 } 563 564 static void 565 re_miibus_statchg(dev) 566 device_t dev; 567 { 568 569 } 570 571 /* 572 * Program the 64-bit multicast hash filter. 573 */ 574 static void 575 re_setmulti(sc) 576 struct rl_softc *sc; 577 { 578 struct ifnet *ifp; 579 int h = 0; 580 u_int32_t hashes[2] = { 0, 0 }; 581 struct ifmultiaddr *ifma; 582 u_int32_t rxfilt; 583 int mcnt = 0; 584 585 ifp = &sc->arpcom.ac_if; 586 587 rxfilt = CSR_READ_4(sc, RL_RXCFG); 588 589 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 590 rxfilt |= RL_RXCFG_RX_MULTI; 591 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 592 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 593 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 594 return; 595 } 596 597 /* first, zot all the existing hash bits */ 598 CSR_WRITE_4(sc, RL_MAR0, 0); 599 CSR_WRITE_4(sc, RL_MAR4, 0); 600 601 /* now program new ones */ 602 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 603 if (ifma->ifma_addr->sa_family != AF_LINK) 604 continue; 605 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 606 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 607 if (h < 32) 608 hashes[0] |= (1 << h); 609 else 610 hashes[1] |= (1 << (h - 32)); 611 mcnt++; 612 } 613 614 if (mcnt) 615 rxfilt |= RL_RXCFG_RX_MULTI; 616 else 617 rxfilt &= ~RL_RXCFG_RX_MULTI; 618 619 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 620 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 621 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 622 } 623 624 static void 625 re_reset(sc) 626 struct rl_softc *sc; 627 { 628 register int i; 629 630 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 631 632 for (i = 0; i < RL_TIMEOUT; i++) { 633 DELAY(10); 634 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 635 break; 636 } 637 if (i == RL_TIMEOUT) 638 printf("re%d: reset never completed!\n", sc->rl_unit); 639 640 CSR_WRITE_1(sc, 0x82, 1); 641 } 642 643 /* 644 * The following routine is designed to test for a defect on some 645 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 646 * lines connected to the bus, however for a 32-bit only card, they 647 * should be pulled high. The result of this defect is that the 648 * NIC will not work right if you plug it into a 64-bit slot: DMA 649 * operations will be done with 64-bit transfers, which will fail 650 * because the 64-bit data lines aren't connected. 651 * 652 * There's no way to work around this (short of talking a soldering 653 * iron to the board), however we can detect it. The method we use 654 * here is to put the NIC into digital loopback mode, set the receiver 655 * to promiscuous mode, and then try to send a frame. We then compare 656 * the frame data we sent to what was received. If the data matches, 657 * then the NIC is working correctly, otherwise we know the user has 658 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 659 * slot. In the latter case, there's no way the NIC can work correctly, 660 * so we print out a message on the console and abort the device attach. 661 */ 662 663 static int 664 re_diag(sc) 665 struct rl_softc *sc; 666 { 667 struct ifnet *ifp = &sc->arpcom.ac_if; 668 struct mbuf *m0; 669 struct ether_header *eh; 670 struct rl_desc *cur_rx; 671 u_int16_t status; 672 u_int32_t rxstat; 673 int total_len, i, error = 0; 674 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 675 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 676 677 /* Allocate a single mbuf */ 678 679 MGETHDR(m0, M_DONTWAIT, MT_DATA); 680 if (m0 == NULL) 681 return (ENOBUFS); 682 683 /* 684 * Initialize the NIC in test mode. This sets the chip up 685 * so that it can send and receive frames, but performs the 686 * following special functions: 687 * - Puts receiver in promiscuous mode 688 * - Enables digital loopback mode 689 * - Leaves interrupts turned off 690 */ 691 692 ifp->if_flags |= IFF_PROMISC; 693 sc->rl_testmode = 1; 694 re_init(sc); 695 re_stop(sc); 696 DELAY(100000); 697 re_init(sc); 698 699 /* Put some data in the mbuf */ 700 701 eh = mtod(m0, struct ether_header *); 702 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 703 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 704 eh->ether_type = htons(ETHERTYPE_IP); 705 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 706 707 /* 708 * Queue the packet, start transmission. 709 * Note: IF_HANDOFF() ultimately calls re_start() for us. 710 */ 711 712 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 713 IF_HANDOFF(&ifp->if_snd, m0, ifp); 714 m0 = NULL; 715 716 /* Wait for it to propagate through the chip */ 717 718 DELAY(100000); 719 for (i = 0; i < RL_TIMEOUT; i++) { 720 status = CSR_READ_2(sc, RL_ISR); 721 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 722 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 723 break; 724 DELAY(10); 725 } 726 727 if (i == RL_TIMEOUT) { 728 printf("re%d: diagnostic failed, failed to receive packet " 729 "in loopback mode\n", sc->rl_unit); 730 error = EIO; 731 goto done; 732 } 733 734 /* 735 * The packet should have been dumped into the first 736 * entry in the RX DMA ring. Grab it from there. 737 */ 738 739 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 740 sc->rl_ldata.rl_rx_list_map, 741 BUS_DMASYNC_POSTREAD); 742 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 743 sc->rl_ldata.rl_rx_dmamap[0], 744 BUS_DMASYNC_POSTWRITE); 745 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 746 sc->rl_ldata.rl_rx_dmamap[0]); 747 748 m0 = sc->rl_ldata.rl_rx_mbuf[0]; 749 sc->rl_ldata.rl_rx_mbuf[0] = NULL; 750 eh = mtod(m0, struct ether_header *); 751 752 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 753 total_len = RL_RXBYTES(cur_rx); 754 rxstat = le32toh(cur_rx->rl_cmdstat); 755 756 if (total_len != ETHER_MIN_LEN) { 757 printf("re%d: diagnostic failed, received short packet\n", 758 sc->rl_unit); 759 error = EIO; 760 goto done; 761 } 762 763 /* Test that the received packet data matches what we sent. */ 764 765 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 766 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 767 ntohs(eh->ether_type) != ETHERTYPE_IP) { 768 printf("re%d: WARNING, DMA FAILURE!\n", sc->rl_unit); 769 printf("re%d: expected TX data: %6D/%6D/0x%x\n", sc->rl_unit, 770 dst, ":", src, ":", ETHERTYPE_IP); 771 printf("re%d: received RX data: %6D/%6D/0x%x\n", sc->rl_unit, 772 eh->ether_dhost, ":", eh->ether_shost, ":", 773 ntohs(eh->ether_type)); 774 printf("re%d: You may have a defective 32-bit NIC plugged " 775 "into a 64-bit PCI slot.\n", sc->rl_unit); 776 printf("re%d: Please re-install the NIC in a 32-bit slot " 777 "for proper operation.\n", sc->rl_unit); 778 printf("re%d: Read the re(4) man page for more details.\n", 779 sc->rl_unit); 780 error = EIO; 781 } 782 783 done: 784 /* Turn interface off, release resources */ 785 786 sc->rl_testmode = 0; 787 ifp->if_flags &= ~IFF_PROMISC; 788 re_stop(sc); 789 if (m0 != NULL) 790 m_freem(m0); 791 792 return (error); 793 } 794 795 /* 796 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 797 * IDs against our list and return a device name if we find a match. 798 */ 799 static int 800 re_probe(dev) 801 device_t dev; 802 { 803 struct rl_type *t; 804 struct rl_softc *sc; 805 int rid; 806 u_int32_t hwrev; 807 808 t = re_devs; 809 sc = device_get_softc(dev); 810 811 while (t->rl_name != NULL) { 812 if ((pci_get_vendor(dev) == t->rl_vid) && 813 (pci_get_device(dev) == t->rl_did)) { 814 815 /* 816 * Temporarily map the I/O space 817 * so we can read the chip ID register. 818 */ 819 rid = RL_RID; 820 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 821 RF_ACTIVE); 822 if (sc->rl_res == NULL) { 823 device_printf(dev, 824 "couldn't map ports/memory\n"); 825 return (ENXIO); 826 } 827 sc->rl_btag = rman_get_bustag(sc->rl_res); 828 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 829 mtx_init(&sc->rl_mtx, 830 device_get_nameunit(dev), 831 MTX_NETWORK_LOCK, MTX_DEF); 832 RL_LOCK(sc); 833 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 834 bus_release_resource(dev, RL_RES, 835 RL_RID, sc->rl_res); 836 RL_UNLOCK(sc); 837 mtx_destroy(&sc->rl_mtx); 838 if (t->rl_basetype == hwrev) { 839 device_set_desc(dev, t->rl_name); 840 return (0); 841 } 842 } 843 t++; 844 } 845 846 return (ENXIO); 847 } 848 849 /* 850 * This routine takes the segment list provided as the result of 851 * a bus_dma_map_load() operation and assigns the addresses/lengths 852 * to RealTek DMA descriptors. This can be called either by the RX 853 * code or the TX code. In the RX case, we'll probably wind up mapping 854 * at most one segment. For the TX case, there could be any number of 855 * segments since TX packets may span multiple mbufs. In either case, 856 * if the number of segments is larger than the rl_maxsegs limit 857 * specified by the caller, we abort the mapping operation. Sadly, 858 * whoever designed the buffer mapping API did not provide a way to 859 * return an error from here, so we have to fake it a bit. 860 */ 861 862 static void 863 re_dma_map_desc(arg, segs, nseg, mapsize, error) 864 void *arg; 865 bus_dma_segment_t *segs; 866 int nseg; 867 bus_size_t mapsize; 868 int error; 869 { 870 struct rl_dmaload_arg *ctx; 871 struct rl_desc *d = NULL; 872 int i = 0, idx; 873 874 if (error) 875 return; 876 877 ctx = arg; 878 879 /* Signal error to caller if there's too many segments */ 880 if (nseg > ctx->rl_maxsegs) { 881 ctx->rl_maxsegs = 0; 882 return; 883 } 884 885 /* 886 * Map the segment array into descriptors. Note that we set the 887 * start-of-frame and end-of-frame markers for either TX or RX, but 888 * they really only have meaning in the TX case. (In the RX case, 889 * it's the chip that tells us where packets begin and end.) 890 * We also keep track of the end of the ring and set the 891 * end-of-ring bits as needed, and we set the ownership bits 892 * in all except the very first descriptor. (The caller will 893 * set this descriptor later when it start transmission or 894 * reception.) 895 */ 896 idx = ctx->rl_idx; 897 for (;;) { 898 u_int32_t cmdstat; 899 d = &ctx->rl_ring[idx]; 900 if (le32toh(d->rl_cmdstat) & RL_RDESC_STAT_OWN) { 901 ctx->rl_maxsegs = 0; 902 return; 903 } 904 cmdstat = segs[i].ds_len; 905 d->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 906 d->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 907 if (i == 0) 908 cmdstat |= RL_TDESC_CMD_SOF; 909 else 910 cmdstat |= RL_TDESC_CMD_OWN; 911 if (idx == (RL_RX_DESC_CNT - 1)) 912 cmdstat |= RL_TDESC_CMD_EOR; 913 d->rl_cmdstat = htole32(cmdstat | ctx->rl_flags); 914 i++; 915 if (i == nseg) 916 break; 917 RL_DESC_INC(idx); 918 } 919 920 d->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 921 ctx->rl_maxsegs = nseg; 922 ctx->rl_idx = idx; 923 } 924 925 /* 926 * Map a single buffer address. 927 */ 928 929 static void 930 re_dma_map_addr(arg, segs, nseg, error) 931 void *arg; 932 bus_dma_segment_t *segs; 933 int nseg; 934 int error; 935 { 936 u_int32_t *addr; 937 938 if (error) 939 return; 940 941 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 942 addr = arg; 943 *addr = segs->ds_addr; 944 } 945 946 static int 947 re_allocmem(dev, sc) 948 device_t dev; 949 struct rl_softc *sc; 950 { 951 int error; 952 int nseg; 953 int i; 954 955 /* 956 * Allocate map for RX mbufs. 957 */ 958 nseg = 32; 959 error = bus_dma_tag_create(sc->rl_parent_tag, ETHER_ALIGN, 0, 960 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 961 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 962 NULL, NULL, &sc->rl_ldata.rl_mtag); 963 if (error) { 964 device_printf(dev, "could not allocate dma tag\n"); 965 return (ENOMEM); 966 } 967 968 /* 969 * Allocate map for TX descriptor list. 970 */ 971 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 972 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 973 NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 974 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 975 if (error) { 976 device_printf(dev, "could not allocate dma tag\n"); 977 return (ENOMEM); 978 } 979 980 /* Allocate DMA'able memory for the TX ring */ 981 982 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 983 (void **)&sc->rl_ldata.rl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 984 &sc->rl_ldata.rl_tx_list_map); 985 if (error) 986 return (ENOMEM); 987 988 /* Load the map for the TX ring. */ 989 990 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 991 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 992 RL_TX_LIST_SZ, re_dma_map_addr, 993 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 994 995 /* Create DMA maps for TX buffers */ 996 997 for (i = 0; i < RL_TX_DESC_CNT; i++) { 998 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 999 &sc->rl_ldata.rl_tx_dmamap[i]); 1000 if (error) { 1001 device_printf(dev, "can't create DMA map for TX\n"); 1002 return (ENOMEM); 1003 } 1004 } 1005 1006 /* 1007 * Allocate map for RX descriptor list. 1008 */ 1009 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1010 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1011 NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 1012 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1013 if (error) { 1014 device_printf(dev, "could not allocate dma tag\n"); 1015 return (ENOMEM); 1016 } 1017 1018 /* Allocate DMA'able memory for the RX ring */ 1019 1020 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1021 (void **)&sc->rl_ldata.rl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1022 &sc->rl_ldata.rl_rx_list_map); 1023 if (error) 1024 return (ENOMEM); 1025 1026 /* Load the map for the RX ring. */ 1027 1028 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1029 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1030 RL_TX_LIST_SZ, re_dma_map_addr, 1031 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1032 1033 /* Create DMA maps for RX buffers */ 1034 1035 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1036 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1037 &sc->rl_ldata.rl_rx_dmamap[i]); 1038 if (error) { 1039 device_printf(dev, "can't create DMA map for RX\n"); 1040 return (ENOMEM); 1041 } 1042 } 1043 1044 return (0); 1045 } 1046 1047 /* 1048 * Attach the interface. Allocate softc structures, do ifmedia 1049 * setup and ethernet/BPF attach. 1050 */ 1051 static int 1052 re_attach(dev) 1053 device_t dev; 1054 { 1055 u_char eaddr[ETHER_ADDR_LEN]; 1056 u_int16_t as[3]; 1057 struct rl_softc *sc; 1058 struct ifnet *ifp; 1059 struct rl_hwrev *hw_rev; 1060 int hwrev; 1061 u_int16_t re_did = 0; 1062 int unit, error = 0, rid, i; 1063 1064 sc = device_get_softc(dev); 1065 unit = device_get_unit(dev); 1066 1067 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1068 MTX_DEF | MTX_RECURSE); 1069 /* 1070 * Map control/status registers. 1071 */ 1072 pci_enable_busmaster(dev); 1073 1074 rid = RL_RID; 1075 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 1076 RF_ACTIVE); 1077 1078 if (sc->rl_res == NULL) { 1079 printf ("re%d: couldn't map ports/memory\n", unit); 1080 error = ENXIO; 1081 goto fail; 1082 } 1083 1084 sc->rl_btag = rman_get_bustag(sc->rl_res); 1085 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1086 1087 /* Allocate interrupt */ 1088 rid = 0; 1089 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1090 RF_SHAREABLE | RF_ACTIVE); 1091 1092 if (sc->rl_irq == NULL) { 1093 printf("re%d: couldn't map interrupt\n", unit); 1094 error = ENXIO; 1095 goto fail; 1096 } 1097 1098 /* Reset the adapter. */ 1099 re_reset(sc); 1100 1101 hw_rev = re_hwrevs; 1102 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 1103 while (hw_rev->rl_desc != NULL) { 1104 if (hw_rev->rl_rev == hwrev) { 1105 sc->rl_type = hw_rev->rl_type; 1106 break; 1107 } 1108 hw_rev++; 1109 } 1110 1111 if (sc->rl_type == RL_8169) { 1112 1113 /* Set RX length mask */ 1114 1115 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1116 1117 /* Force station address autoload from the EEPROM */ 1118 1119 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_AUTOLOAD); 1120 for (i = 0; i < RL_TIMEOUT; i++) { 1121 if (!(CSR_READ_1(sc, RL_EECMD) & RL_EEMODE_AUTOLOAD)) 1122 break; 1123 DELAY(100); 1124 } 1125 if (i == RL_TIMEOUT) 1126 printf ("re%d: eeprom autoload timed out\n", unit); 1127 1128 for (i = 0; i < ETHER_ADDR_LEN; i++) 1129 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1130 } else { 1131 1132 /* Set RX length mask */ 1133 1134 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1135 1136 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 1137 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1, 0); 1138 if (re_did != 0x8129) 1139 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 1140 1141 /* 1142 * Get station address from the EEPROM. 1143 */ 1144 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0); 1145 for (i = 0; i < 3; i++) { 1146 eaddr[(i * 2) + 0] = as[i] & 0xff; 1147 eaddr[(i * 2) + 1] = as[i] >> 8; 1148 } 1149 } 1150 1151 sc->rl_unit = unit; 1152 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 1153 1154 /* 1155 * Allocate the parent bus DMA tag appropriate for PCI. 1156 */ 1157 #define RL_NSEG_NEW 32 1158 error = bus_dma_tag_create(NULL, /* parent */ 1159 1, 0, /* alignment, boundary */ 1160 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1161 BUS_SPACE_MAXADDR, /* highaddr */ 1162 NULL, NULL, /* filter, filterarg */ 1163 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 1164 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1165 BUS_DMA_ALLOCNOW, /* flags */ 1166 NULL, NULL, /* lockfunc, lockarg */ 1167 &sc->rl_parent_tag); 1168 if (error) 1169 goto fail; 1170 1171 error = re_allocmem(dev, sc); 1172 1173 if (error) 1174 goto fail; 1175 1176 /* Do MII setup */ 1177 if (mii_phy_probe(dev, &sc->rl_miibus, 1178 re_ifmedia_upd, re_ifmedia_sts)) { 1179 printf("re%d: MII without any phy!\n", sc->rl_unit); 1180 error = ENXIO; 1181 goto fail; 1182 } 1183 1184 ifp = &sc->arpcom.ac_if; 1185 ifp->if_softc = sc; 1186 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1187 ifp->if_mtu = ETHERMTU; 1188 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1189 ifp->if_ioctl = re_ioctl; 1190 ifp->if_capabilities = IFCAP_VLAN_MTU; 1191 ifp->if_start = re_start; 1192 ifp->if_hwassist = RE_CSUM_FEATURES; 1193 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1194 #ifdef DEVICE_POLLING 1195 ifp->if_capabilities |= IFCAP_POLLING; 1196 #endif 1197 ifp->if_watchdog = re_watchdog; 1198 ifp->if_init = re_init; 1199 if (sc->rl_type == RL_8169) 1200 ifp->if_baudrate = 1000000000; 1201 else 1202 ifp->if_baudrate = 100000000; 1203 ifp->if_snd.ifq_maxlen = RL_IFQ_MAXLEN; 1204 ifp->if_capenable = ifp->if_capabilities; 1205 1206 callout_handle_init(&sc->rl_stat_ch); 1207 1208 /* 1209 * Call MI attach routine. 1210 */ 1211 ether_ifattach(ifp, eaddr); 1212 1213 /* Perform hardware diagnostic. */ 1214 error = re_diag(sc); 1215 1216 if (error) { 1217 printf("re%d: attach aborted due to hardware diag failure\n", 1218 unit); 1219 ether_ifdetach(ifp); 1220 goto fail; 1221 } 1222 1223 /* Hook interrupt last to avoid having to lock softc */ 1224 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET, 1225 re_intr, sc, &sc->rl_intrhand); 1226 1227 if (error) { 1228 printf("re%d: couldn't set up irq\n", unit); 1229 ether_ifdetach(ifp); 1230 goto fail; 1231 } 1232 1233 fail: 1234 if (error) 1235 re_detach(dev); 1236 1237 return (error); 1238 } 1239 1240 /* 1241 * Shutdown hardware and free up resources. This can be called any 1242 * time after the mutex has been initialized. It is called in both 1243 * the error case in attach and the normal detach case so it needs 1244 * to be careful about only freeing resources that have actually been 1245 * allocated. 1246 */ 1247 static int 1248 re_detach(dev) 1249 device_t dev; 1250 { 1251 struct rl_softc *sc; 1252 struct ifnet *ifp; 1253 int i; 1254 1255 sc = device_get_softc(dev); 1256 KASSERT(mtx_initialized(&sc->rl_mtx), ("rl mutex not initialized")); 1257 RL_LOCK(sc); 1258 ifp = &sc->arpcom.ac_if; 1259 1260 /* These should only be active if attach succeeded */ 1261 if (device_is_attached(dev)) { 1262 re_stop(sc); 1263 /* 1264 * Force off the IFF_UP flag here, in case someone 1265 * still had a BPF descriptor attached to this 1266 * interface. If they do, ether_ifattach() will cause 1267 * the BPF code to try and clear the promisc mode 1268 * flag, which will bubble down to re_ioctl(), 1269 * which will try to call re_init() again. This will 1270 * turn the NIC back on and restart the MII ticker, 1271 * which will panic the system when the kernel tries 1272 * to invoke the re_tick() function that isn't there 1273 * anymore. 1274 */ 1275 ifp->if_flags &= ~IFF_UP; 1276 ether_ifdetach(ifp); 1277 } 1278 if (sc->rl_miibus) 1279 device_delete_child(dev, sc->rl_miibus); 1280 bus_generic_detach(dev); 1281 1282 if (sc->rl_intrhand) 1283 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1284 if (sc->rl_irq) 1285 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1286 if (sc->rl_res) 1287 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1288 1289 1290 /* Unload and free the RX DMA ring memory and map */ 1291 1292 if (sc->rl_ldata.rl_rx_list_tag) { 1293 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1294 sc->rl_ldata.rl_rx_list_map); 1295 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1296 sc->rl_ldata.rl_rx_list, 1297 sc->rl_ldata.rl_rx_list_map); 1298 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1299 } 1300 1301 /* Unload and free the TX DMA ring memory and map */ 1302 1303 if (sc->rl_ldata.rl_tx_list_tag) { 1304 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1305 sc->rl_ldata.rl_tx_list_map); 1306 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1307 sc->rl_ldata.rl_tx_list, 1308 sc->rl_ldata.rl_tx_list_map); 1309 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1310 } 1311 1312 /* Destroy all the RX and TX buffer maps */ 1313 1314 if (sc->rl_ldata.rl_mtag) { 1315 for (i = 0; i < RL_TX_DESC_CNT; i++) 1316 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1317 sc->rl_ldata.rl_tx_dmamap[i]); 1318 for (i = 0; i < RL_RX_DESC_CNT; i++) 1319 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1320 sc->rl_ldata.rl_rx_dmamap[i]); 1321 bus_dma_tag_destroy(sc->rl_ldata.rl_mtag); 1322 } 1323 1324 /* Unload and free the stats buffer and map */ 1325 1326 if (sc->rl_ldata.rl_stag) { 1327 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1328 sc->rl_ldata.rl_rx_list_map); 1329 bus_dmamem_free(sc->rl_ldata.rl_stag, 1330 sc->rl_ldata.rl_stats, 1331 sc->rl_ldata.rl_smap); 1332 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1333 } 1334 1335 if (sc->rl_parent_tag) 1336 bus_dma_tag_destroy(sc->rl_parent_tag); 1337 1338 RL_UNLOCK(sc); 1339 mtx_destroy(&sc->rl_mtx); 1340 1341 return (0); 1342 } 1343 1344 static int 1345 re_newbuf(sc, idx, m) 1346 struct rl_softc *sc; 1347 int idx; 1348 struct mbuf *m; 1349 { 1350 struct rl_dmaload_arg arg; 1351 struct mbuf *n = NULL; 1352 int error; 1353 1354 if (m == NULL) { 1355 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1356 if (n == NULL) 1357 return (ENOBUFS); 1358 m = n; 1359 } else 1360 m->m_data = m->m_ext.ext_buf; 1361 1362 /* 1363 * Initialize mbuf length fields and fixup 1364 * alignment so that the frame payload is 1365 * longword aligned. 1366 */ 1367 m->m_len = m->m_pkthdr.len = MCLBYTES; 1368 m_adj(m, ETHER_ALIGN); 1369 1370 arg.sc = sc; 1371 arg.rl_idx = idx; 1372 arg.rl_maxsegs = 1; 1373 arg.rl_flags = 0; 1374 arg.rl_ring = sc->rl_ldata.rl_rx_list; 1375 1376 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, 1377 sc->rl_ldata.rl_rx_dmamap[idx], m, re_dma_map_desc, 1378 &arg, BUS_DMA_NOWAIT); 1379 if (error || arg.rl_maxsegs != 1) { 1380 if (n != NULL) 1381 m_freem(n); 1382 return (ENOMEM); 1383 } 1384 1385 sc->rl_ldata.rl_rx_list[idx].rl_cmdstat |= htole32(RL_RDESC_CMD_OWN); 1386 sc->rl_ldata.rl_rx_mbuf[idx] = m; 1387 1388 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1389 sc->rl_ldata.rl_rx_dmamap[idx], 1390 BUS_DMASYNC_PREREAD); 1391 1392 return (0); 1393 } 1394 1395 static int 1396 re_tx_list_init(sc) 1397 struct rl_softc *sc; 1398 { 1399 bzero ((char *)sc->rl_ldata.rl_tx_list, RL_TX_LIST_SZ); 1400 bzero ((char *)&sc->rl_ldata.rl_tx_mbuf, 1401 (RL_TX_DESC_CNT * sizeof(struct mbuf *))); 1402 1403 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1404 sc->rl_ldata.rl_tx_list_map, BUS_DMASYNC_PREWRITE); 1405 sc->rl_ldata.rl_tx_prodidx = 0; 1406 sc->rl_ldata.rl_tx_considx = 0; 1407 sc->rl_ldata.rl_tx_free = RL_TX_DESC_CNT; 1408 1409 return (0); 1410 } 1411 1412 static int 1413 re_rx_list_init(sc) 1414 struct rl_softc *sc; 1415 { 1416 int i; 1417 1418 bzero ((char *)sc->rl_ldata.rl_rx_list, RL_RX_LIST_SZ); 1419 bzero ((char *)&sc->rl_ldata.rl_rx_mbuf, 1420 (RL_RX_DESC_CNT * sizeof(struct mbuf *))); 1421 1422 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1423 if (re_newbuf(sc, i, NULL) == ENOBUFS) 1424 return (ENOBUFS); 1425 } 1426 1427 /* Flush the RX descriptors */ 1428 1429 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1430 sc->rl_ldata.rl_rx_list_map, 1431 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1432 1433 sc->rl_ldata.rl_rx_prodidx = 0; 1434 sc->rl_head = sc->rl_tail = NULL; 1435 1436 return (0); 1437 } 1438 1439 /* 1440 * RX handler for C+ and 8169. For the gigE chips, we support 1441 * the reception of jumbo frames that have been fragmented 1442 * across multiple 2K mbuf cluster buffers. 1443 */ 1444 static void 1445 re_rxeof(sc) 1446 struct rl_softc *sc; 1447 { 1448 struct mbuf *m; 1449 struct ifnet *ifp; 1450 int i, total_len; 1451 struct rl_desc *cur_rx; 1452 u_int32_t rxstat, rxvlan; 1453 1454 RL_LOCK_ASSERT(sc); 1455 1456 ifp = &sc->arpcom.ac_if; 1457 i = sc->rl_ldata.rl_rx_prodidx; 1458 1459 /* Invalidate the descriptor memory */ 1460 1461 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1462 sc->rl_ldata.rl_rx_list_map, 1463 BUS_DMASYNC_POSTREAD); 1464 1465 while (!RL_OWN(&sc->rl_ldata.rl_rx_list[i])) { 1466 1467 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1468 m = sc->rl_ldata.rl_rx_mbuf[i]; 1469 total_len = RL_RXBYTES(cur_rx); 1470 rxstat = le32toh(cur_rx->rl_cmdstat); 1471 rxvlan = le32toh(cur_rx->rl_vlanctl); 1472 1473 /* Invalidate the RX mbuf and unload its map */ 1474 1475 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1476 sc->rl_ldata.rl_rx_dmamap[i], 1477 BUS_DMASYNC_POSTWRITE); 1478 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1479 sc->rl_ldata.rl_rx_dmamap[i]); 1480 1481 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1482 m->m_len = MCLBYTES - ETHER_ALIGN; 1483 if (sc->rl_head == NULL) 1484 sc->rl_head = sc->rl_tail = m; 1485 else { 1486 m->m_flags &= ~M_PKTHDR; 1487 sc->rl_tail->m_next = m; 1488 sc->rl_tail = m; 1489 } 1490 re_newbuf(sc, i, NULL); 1491 RL_DESC_INC(i); 1492 continue; 1493 } 1494 1495 /* 1496 * NOTE: for the 8139C+, the frame length field 1497 * is always 12 bits in size, but for the gigE chips, 1498 * it is 13 bits (since the max RX frame length is 16K). 1499 * Unfortunately, all 32 bits in the status word 1500 * were already used, so to make room for the extra 1501 * length bit, RealTek took out the 'frame alignment 1502 * error' bit and shifted the other status bits 1503 * over one slot. The OWN, EOR, FS and LS bits are 1504 * still in the same places. We have already extracted 1505 * the frame length and checked the OWN bit, so rather 1506 * than using an alternate bit mapping, we shift the 1507 * status bits one space to the right so we can evaluate 1508 * them using the 8169 status as though it was in the 1509 * same format as that of the 8139C+. 1510 */ 1511 if (sc->rl_type == RL_8169) 1512 rxstat >>= 1; 1513 1514 if (rxstat & RL_RDESC_STAT_RXERRSUM) { 1515 ifp->if_ierrors++; 1516 /* 1517 * If this is part of a multi-fragment packet, 1518 * discard all the pieces. 1519 */ 1520 if (sc->rl_head != NULL) { 1521 m_freem(sc->rl_head); 1522 sc->rl_head = sc->rl_tail = NULL; 1523 } 1524 re_newbuf(sc, i, m); 1525 RL_DESC_INC(i); 1526 continue; 1527 } 1528 1529 /* 1530 * If allocating a replacement mbuf fails, 1531 * reload the current one. 1532 */ 1533 1534 if (re_newbuf(sc, i, NULL)) { 1535 ifp->if_ierrors++; 1536 if (sc->rl_head != NULL) { 1537 m_freem(sc->rl_head); 1538 sc->rl_head = sc->rl_tail = NULL; 1539 } 1540 re_newbuf(sc, i, m); 1541 RL_DESC_INC(i); 1542 continue; 1543 } 1544 1545 RL_DESC_INC(i); 1546 1547 if (sc->rl_head != NULL) { 1548 m->m_len = total_len % (MCLBYTES - ETHER_ALIGN); 1549 /* 1550 * Special case: if there's 4 bytes or less 1551 * in this buffer, the mbuf can be discarded: 1552 * the last 4 bytes is the CRC, which we don't 1553 * care about anyway. 1554 */ 1555 if (m->m_len <= ETHER_CRC_LEN) { 1556 sc->rl_tail->m_len -= 1557 (ETHER_CRC_LEN - m->m_len); 1558 m_freem(m); 1559 } else { 1560 m->m_len -= ETHER_CRC_LEN; 1561 m->m_flags &= ~M_PKTHDR; 1562 sc->rl_tail->m_next = m; 1563 } 1564 m = sc->rl_head; 1565 sc->rl_head = sc->rl_tail = NULL; 1566 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1567 } else 1568 m->m_pkthdr.len = m->m_len = 1569 (total_len - ETHER_CRC_LEN); 1570 1571 ifp->if_ipackets++; 1572 m->m_pkthdr.rcvif = ifp; 1573 1574 /* Do RX checksumming if enabled */ 1575 1576 if (ifp->if_capenable & IFCAP_RXCSUM) { 1577 1578 /* Check IP header checksum */ 1579 if (rxstat & RL_RDESC_STAT_PROTOID) 1580 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1581 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1582 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1583 1584 /* Check TCP/UDP checksum */ 1585 if ((RL_TCPPKT(rxstat) && 1586 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1587 (RL_UDPPKT(rxstat) && 1588 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1589 m->m_pkthdr.csum_flags |= 1590 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1591 m->m_pkthdr.csum_data = 0xffff; 1592 } 1593 } 1594 1595 if (rxvlan & RL_RDESC_VLANCTL_TAG) 1596 VLAN_INPUT_TAG(ifp, m, 1597 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)), continue); 1598 RL_UNLOCK(sc); 1599 (*ifp->if_input)(ifp, m); 1600 RL_LOCK(sc); 1601 } 1602 1603 /* Flush the RX DMA ring */ 1604 1605 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1606 sc->rl_ldata.rl_rx_list_map, 1607 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1608 1609 sc->rl_ldata.rl_rx_prodidx = i; 1610 } 1611 1612 static void 1613 re_txeof(sc) 1614 struct rl_softc *sc; 1615 { 1616 struct ifnet *ifp; 1617 u_int32_t txstat; 1618 int idx; 1619 1620 ifp = &sc->arpcom.ac_if; 1621 idx = sc->rl_ldata.rl_tx_considx; 1622 1623 /* Invalidate the TX descriptor list */ 1624 1625 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1626 sc->rl_ldata.rl_tx_list_map, 1627 BUS_DMASYNC_POSTREAD); 1628 1629 while (idx != sc->rl_ldata.rl_tx_prodidx) { 1630 1631 txstat = le32toh(sc->rl_ldata.rl_tx_list[idx].rl_cmdstat); 1632 if (txstat & RL_TDESC_CMD_OWN) 1633 break; 1634 1635 /* 1636 * We only stash mbufs in the last descriptor 1637 * in a fragment chain, which also happens to 1638 * be the only place where the TX status bits 1639 * are valid. 1640 */ 1641 1642 if (txstat & RL_TDESC_CMD_EOF) { 1643 m_freem(sc->rl_ldata.rl_tx_mbuf[idx]); 1644 sc->rl_ldata.rl_tx_mbuf[idx] = NULL; 1645 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1646 sc->rl_ldata.rl_tx_dmamap[idx]); 1647 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 1648 RL_TDESC_STAT_COLCNT)) 1649 ifp->if_collisions++; 1650 if (txstat & RL_TDESC_STAT_TXERRSUM) 1651 ifp->if_oerrors++; 1652 else 1653 ifp->if_opackets++; 1654 } 1655 sc->rl_ldata.rl_tx_free++; 1656 RL_DESC_INC(idx); 1657 } 1658 1659 /* No changes made to the TX ring, so no flush needed */ 1660 1661 if (idx != sc->rl_ldata.rl_tx_considx) { 1662 sc->rl_ldata.rl_tx_considx = idx; 1663 ifp->if_flags &= ~IFF_OACTIVE; 1664 ifp->if_timer = 0; 1665 } 1666 1667 /* 1668 * If not all descriptors have been released reaped yet, 1669 * reload the timer so that we will eventually get another 1670 * interrupt that will cause us to re-enter this routine. 1671 * This is done in case the transmitter has gone idle. 1672 */ 1673 if (sc->rl_ldata.rl_tx_free != RL_TX_DESC_CNT) 1674 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 1675 } 1676 1677 static void 1678 re_tick(xsc) 1679 void *xsc; 1680 { 1681 struct rl_softc *sc; 1682 struct mii_data *mii; 1683 1684 sc = xsc; 1685 RL_LOCK(sc); 1686 mii = device_get_softc(sc->rl_miibus); 1687 1688 mii_tick(mii); 1689 1690 sc->rl_stat_ch = timeout(re_tick, sc, hz); 1691 RL_UNLOCK(sc); 1692 } 1693 1694 #ifdef DEVICE_POLLING 1695 static void 1696 re_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1697 { 1698 struct rl_softc *sc = ifp->if_softc; 1699 1700 RL_LOCK(sc); 1701 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1702 ether_poll_deregister(ifp); 1703 cmd = POLL_DEREGISTER; 1704 } 1705 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1706 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 1707 goto done; 1708 } 1709 1710 sc->rxcycles = count; 1711 re_rxeof(sc); 1712 re_txeof(sc); 1713 1714 if (ifp->if_snd.ifq_head != NULL) 1715 (*ifp->if_start)(ifp); 1716 1717 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1718 u_int16_t status; 1719 1720 status = CSR_READ_2(sc, RL_ISR); 1721 if (status == 0xffff) 1722 goto done; 1723 if (status) 1724 CSR_WRITE_2(sc, RL_ISR, status); 1725 1726 /* 1727 * XXX check behaviour on receiver stalls. 1728 */ 1729 1730 if (status & RL_ISR_SYSTEM_ERR) { 1731 re_reset(sc); 1732 re_init(sc); 1733 } 1734 } 1735 done: 1736 RL_UNLOCK(sc); 1737 } 1738 #endif /* DEVICE_POLLING */ 1739 1740 static void 1741 re_intr(arg) 1742 void *arg; 1743 { 1744 struct rl_softc *sc; 1745 struct ifnet *ifp; 1746 u_int16_t status; 1747 1748 sc = arg; 1749 1750 if (sc->suspended) { 1751 return; 1752 } 1753 1754 RL_LOCK(sc); 1755 ifp = &sc->arpcom.ac_if; 1756 1757 if (!(ifp->if_flags & IFF_UP)) { 1758 RL_UNLOCK(sc); 1759 return; 1760 } 1761 1762 #ifdef DEVICE_POLLING 1763 if (ifp->if_flags & IFF_POLLING) 1764 goto done; 1765 if ((ifp->if_capenable & IFCAP_POLLING) && 1766 ether_poll_register(re_poll, ifp)) { /* ok, disable interrupts */ 1767 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1768 re_poll(ifp, 0, 1); 1769 goto done; 1770 } 1771 #endif /* DEVICE_POLLING */ 1772 1773 for (;;) { 1774 1775 status = CSR_READ_2(sc, RL_ISR); 1776 /* If the card has gone away the read returns 0xffff. */ 1777 if (status == 0xffff) 1778 break; 1779 if (status) 1780 CSR_WRITE_2(sc, RL_ISR, status); 1781 1782 if ((status & RL_INTRS_CPLUS) == 0) 1783 break; 1784 1785 if (status & RL_ISR_RX_OK) 1786 re_rxeof(sc); 1787 1788 if (status & RL_ISR_RX_ERR) 1789 re_rxeof(sc); 1790 1791 if ((status & RL_ISR_TIMEOUT_EXPIRED) || 1792 (status & RL_ISR_TX_ERR) || 1793 (status & RL_ISR_TX_DESC_UNAVAIL)) 1794 re_txeof(sc); 1795 1796 if (status & RL_ISR_SYSTEM_ERR) { 1797 re_reset(sc); 1798 re_init(sc); 1799 } 1800 1801 if (status & RL_ISR_LINKCHG) { 1802 untimeout(re_tick, sc, sc->rl_stat_ch); 1803 re_tick(sc); 1804 } 1805 } 1806 1807 if (ifp->if_snd.ifq_head != NULL) 1808 (*ifp->if_start)(ifp); 1809 1810 #ifdef DEVICE_POLLING 1811 done: 1812 #endif 1813 RL_UNLOCK(sc); 1814 } 1815 1816 static int 1817 re_encap(sc, m_head, idx) 1818 struct rl_softc *sc; 1819 struct mbuf *m_head; 1820 int *idx; 1821 { 1822 struct mbuf *m_new = NULL; 1823 struct rl_dmaload_arg arg; 1824 bus_dmamap_t map; 1825 int error; 1826 struct m_tag *mtag; 1827 1828 if (sc->rl_ldata.rl_tx_free <= 4) 1829 return (EFBIG); 1830 1831 /* 1832 * Set up checksum offload. Note: checksum offload bits must 1833 * appear in all descriptors of a multi-descriptor transmit 1834 * attempt. (This is according to testing done with an 8169 1835 * chip. I'm not sure if this is a requirement or a bug.) 1836 */ 1837 1838 arg.rl_flags = 0; 1839 1840 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1841 arg.rl_flags |= RL_TDESC_CMD_IPCSUM; 1842 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1843 arg.rl_flags |= RL_TDESC_CMD_TCPCSUM; 1844 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1845 arg.rl_flags |= RL_TDESC_CMD_UDPCSUM; 1846 1847 arg.sc = sc; 1848 arg.rl_idx = *idx; 1849 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 1850 if (arg.rl_maxsegs > 4) 1851 arg.rl_maxsegs -= 4; 1852 arg.rl_ring = sc->rl_ldata.rl_tx_list; 1853 1854 map = sc->rl_ldata.rl_tx_dmamap[*idx]; 1855 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 1856 m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1857 1858 if (error && error != EFBIG) { 1859 printf("re%d: can't map mbuf (error %d)\n", sc->rl_unit, error); 1860 return (ENOBUFS); 1861 } 1862 1863 /* Too many segments to map, coalesce into a single mbuf */ 1864 1865 if (error || arg.rl_maxsegs == 0) { 1866 m_new = m_defrag(m_head, M_DONTWAIT); 1867 if (m_new == NULL) 1868 return (1); 1869 else 1870 m_head = m_new; 1871 1872 arg.sc = sc; 1873 arg.rl_idx = *idx; 1874 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 1875 arg.rl_ring = sc->rl_ldata.rl_tx_list; 1876 1877 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 1878 m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1879 if (error) { 1880 printf("re%d: can't map mbuf (error %d)\n", 1881 sc->rl_unit, error); 1882 return (EFBIG); 1883 } 1884 } 1885 1886 /* 1887 * Insure that the map for this transmission 1888 * is placed at the array index of the last descriptor 1889 * in this chain. 1890 */ 1891 sc->rl_ldata.rl_tx_dmamap[*idx] = 1892 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx]; 1893 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx] = map; 1894 1895 sc->rl_ldata.rl_tx_mbuf[arg.rl_idx] = m_head; 1896 sc->rl_ldata.rl_tx_free -= arg.rl_maxsegs; 1897 1898 /* 1899 * Set up hardware VLAN tagging. Note: vlan tag info must 1900 * appear in the first descriptor of a multi-descriptor 1901 * transmission attempt. 1902 */ 1903 1904 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m_head); 1905 if (mtag != NULL) 1906 sc->rl_ldata.rl_tx_list[*idx].rl_vlanctl = 1907 htole32(htons(VLAN_TAG_VALUE(mtag)) | RL_TDESC_VLANCTL_TAG); 1908 1909 /* Transfer ownership of packet to the chip. */ 1910 1911 sc->rl_ldata.rl_tx_list[arg.rl_idx].rl_cmdstat |= 1912 htole32(RL_TDESC_CMD_OWN); 1913 if (*idx != arg.rl_idx) 1914 sc->rl_ldata.rl_tx_list[*idx].rl_cmdstat |= 1915 htole32(RL_TDESC_CMD_OWN); 1916 1917 RL_DESC_INC(arg.rl_idx); 1918 *idx = arg.rl_idx; 1919 1920 return (0); 1921 } 1922 1923 /* 1924 * Main transmit routine for C+ and gigE NICs. 1925 */ 1926 1927 static void 1928 re_start(ifp) 1929 struct ifnet *ifp; 1930 { 1931 struct rl_softc *sc; 1932 struct mbuf *m_head = NULL; 1933 int idx; 1934 1935 sc = ifp->if_softc; 1936 RL_LOCK(sc); 1937 1938 idx = sc->rl_ldata.rl_tx_prodidx; 1939 1940 while (sc->rl_ldata.rl_tx_mbuf[idx] == NULL) { 1941 IF_DEQUEUE(&ifp->if_snd, m_head); 1942 if (m_head == NULL) 1943 break; 1944 1945 if (re_encap(sc, m_head, &idx)) { 1946 IF_PREPEND(&ifp->if_snd, m_head); 1947 ifp->if_flags |= IFF_OACTIVE; 1948 break; 1949 } 1950 1951 /* 1952 * If there's a BPF listener, bounce a copy of this frame 1953 * to him. 1954 */ 1955 BPF_MTAP(ifp, m_head); 1956 } 1957 1958 /* Flush the TX descriptors */ 1959 1960 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1961 sc->rl_ldata.rl_tx_list_map, 1962 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1963 1964 sc->rl_ldata.rl_tx_prodidx = idx; 1965 1966 /* 1967 * RealTek put the TX poll request register in a different 1968 * location on the 8169 gigE chip. I don't know why. 1969 */ 1970 1971 if (sc->rl_type == RL_8169) 1972 CSR_WRITE_2(sc, RL_GTXSTART, RL_TXSTART_START); 1973 else 1974 CSR_WRITE_2(sc, RL_TXSTART, RL_TXSTART_START); 1975 1976 /* 1977 * Use the countdown timer for interrupt moderation. 1978 * 'TX done' interrupts are disabled. Instead, we reset the 1979 * countdown timer, which will begin counting until it hits 1980 * the value in the TIMERINT register, and then trigger an 1981 * interrupt. Each time we write to the TIMERCNT register, 1982 * the timer count is reset to 0. 1983 */ 1984 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 1985 1986 RL_UNLOCK(sc); 1987 1988 /* 1989 * Set a timeout in case the chip goes out to lunch. 1990 */ 1991 ifp->if_timer = 5; 1992 } 1993 1994 static void 1995 re_init(xsc) 1996 void *xsc; 1997 { 1998 struct rl_softc *sc = xsc; 1999 struct ifnet *ifp = &sc->arpcom.ac_if; 2000 struct mii_data *mii; 2001 u_int32_t rxcfg = 0; 2002 2003 RL_LOCK(sc); 2004 mii = device_get_softc(sc->rl_miibus); 2005 2006 /* 2007 * Cancel pending I/O and free all RX/TX buffers. 2008 */ 2009 re_stop(sc); 2010 2011 /* 2012 * Enable C+ RX and TX mode, as well as VLAN stripping and 2013 * RX checksum offload. We must configure the C+ register 2014 * before all others. 2015 */ 2016 CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB| 2017 RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW| 2018 RL_CPLUSCMD_VLANSTRIP| 2019 (ifp->if_capenable & IFCAP_RXCSUM ? 2020 RL_CPLUSCMD_RXCSUM_ENB : 0)); 2021 2022 /* 2023 * Init our MAC address. Even though the chipset 2024 * documentation doesn't mention it, we need to enter "Config 2025 * register write enable" mode to modify the ID registers. 2026 */ 2027 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2028 CSR_WRITE_STREAM_4(sc, RL_IDR0, 2029 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 2030 CSR_WRITE_STREAM_4(sc, RL_IDR4, 2031 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 2032 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2033 2034 /* 2035 * For C+ mode, initialize the RX descriptors and mbufs. 2036 */ 2037 re_rx_list_init(sc); 2038 re_tx_list_init(sc); 2039 2040 /* 2041 * Enable transmit and receive. 2042 */ 2043 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2044 2045 /* 2046 * Set the initial TX and RX configuration. 2047 */ 2048 if (sc->rl_testmode) { 2049 if (sc->rl_type == RL_8169) 2050 CSR_WRITE_4(sc, RL_TXCFG, 2051 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2052 else 2053 CSR_WRITE_4(sc, RL_TXCFG, 2054 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2055 } else 2056 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2057 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 2058 2059 /* Set the individual bit to receive frames for this host only. */ 2060 rxcfg = CSR_READ_4(sc, RL_RXCFG); 2061 rxcfg |= RL_RXCFG_RX_INDIV; 2062 2063 /* If we want promiscuous mode, set the allframes bit. */ 2064 if (ifp->if_flags & IFF_PROMISC) { 2065 rxcfg |= RL_RXCFG_RX_ALLPHYS; 2066 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2067 } else { 2068 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 2069 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2070 } 2071 2072 /* 2073 * Set capture broadcast bit to capture broadcast frames. 2074 */ 2075 if (ifp->if_flags & IFF_BROADCAST) { 2076 rxcfg |= RL_RXCFG_RX_BROAD; 2077 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2078 } else { 2079 rxcfg &= ~RL_RXCFG_RX_BROAD; 2080 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2081 } 2082 2083 /* 2084 * Program the multicast filter, if necessary. 2085 */ 2086 re_setmulti(sc); 2087 2088 #ifdef DEVICE_POLLING 2089 /* 2090 * Disable interrupts if we are polling. 2091 */ 2092 if (ifp->if_flags & IFF_POLLING) 2093 CSR_WRITE_2(sc, RL_IMR, 0); 2094 else /* otherwise ... */ 2095 #endif /* DEVICE_POLLING */ 2096 /* 2097 * Enable interrupts. 2098 */ 2099 if (sc->rl_testmode) 2100 CSR_WRITE_2(sc, RL_IMR, 0); 2101 else 2102 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2103 2104 /* Set initial TX threshold */ 2105 sc->rl_txthresh = RL_TX_THRESH_INIT; 2106 2107 /* Start RX/TX process. */ 2108 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2109 #ifdef notdef 2110 /* Enable receiver and transmitter. */ 2111 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2112 #endif 2113 /* 2114 * Load the addresses of the RX and TX lists into the chip. 2115 */ 2116 2117 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2118 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2119 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2120 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2121 2122 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2123 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2124 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2125 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2126 2127 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2128 2129 /* 2130 * Initialize the timer interrupt register so that 2131 * a timer interrupt will be generated once the timer 2132 * reaches a certain number of ticks. The timer is 2133 * reloaded on each transmit. This gives us TX interrupt 2134 * moderation, which dramatically improves TX frame rate. 2135 */ 2136 2137 if (sc->rl_type == RL_8169) 2138 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2139 else 2140 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2141 2142 /* 2143 * For 8169 gigE NICs, set the max allowed RX packet 2144 * size so we can receive jumbo frames. 2145 */ 2146 if (sc->rl_type == RL_8169) 2147 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2148 2149 if (sc->rl_testmode) { 2150 RL_UNLOCK(sc); 2151 return; 2152 } 2153 2154 mii_mediachg(mii); 2155 2156 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 2157 2158 ifp->if_flags |= IFF_RUNNING; 2159 ifp->if_flags &= ~IFF_OACTIVE; 2160 2161 sc->rl_stat_ch = timeout(re_tick, sc, hz); 2162 RL_UNLOCK(sc); 2163 } 2164 2165 /* 2166 * Set media options. 2167 */ 2168 static int 2169 re_ifmedia_upd(ifp) 2170 struct ifnet *ifp; 2171 { 2172 struct rl_softc *sc; 2173 struct mii_data *mii; 2174 2175 sc = ifp->if_softc; 2176 mii = device_get_softc(sc->rl_miibus); 2177 mii_mediachg(mii); 2178 2179 return (0); 2180 } 2181 2182 /* 2183 * Report current media status. 2184 */ 2185 static void 2186 re_ifmedia_sts(ifp, ifmr) 2187 struct ifnet *ifp; 2188 struct ifmediareq *ifmr; 2189 { 2190 struct rl_softc *sc; 2191 struct mii_data *mii; 2192 2193 sc = ifp->if_softc; 2194 mii = device_get_softc(sc->rl_miibus); 2195 2196 mii_pollstat(mii); 2197 ifmr->ifm_active = mii->mii_media_active; 2198 ifmr->ifm_status = mii->mii_media_status; 2199 } 2200 2201 static int 2202 re_ioctl(ifp, command, data) 2203 struct ifnet *ifp; 2204 u_long command; 2205 caddr_t data; 2206 { 2207 struct rl_softc *sc = ifp->if_softc; 2208 struct ifreq *ifr = (struct ifreq *) data; 2209 struct mii_data *mii; 2210 int error = 0; 2211 2212 RL_LOCK(sc); 2213 2214 switch (command) { 2215 case SIOCSIFMTU: 2216 if (ifr->ifr_mtu > RL_JUMBO_MTU) 2217 error = EINVAL; 2218 ifp->if_mtu = ifr->ifr_mtu; 2219 break; 2220 case SIOCSIFFLAGS: 2221 if (ifp->if_flags & IFF_UP) { 2222 re_init(sc); 2223 } else { 2224 if (ifp->if_flags & IFF_RUNNING) 2225 re_stop(sc); 2226 } 2227 error = 0; 2228 break; 2229 case SIOCADDMULTI: 2230 case SIOCDELMULTI: 2231 re_setmulti(sc); 2232 error = 0; 2233 break; 2234 case SIOCGIFMEDIA: 2235 case SIOCSIFMEDIA: 2236 mii = device_get_softc(sc->rl_miibus); 2237 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2238 break; 2239 case SIOCSIFCAP: 2240 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_POLLING); 2241 ifp->if_capenable |= 2242 ifr->ifr_reqcap & (IFCAP_HWCSUM | IFCAP_POLLING); 2243 if (ifp->if_capenable & IFCAP_TXCSUM) 2244 ifp->if_hwassist = RE_CSUM_FEATURES; 2245 else 2246 ifp->if_hwassist = 0; 2247 if (ifp->if_flags & IFF_RUNNING) 2248 re_init(sc); 2249 break; 2250 default: 2251 error = ether_ioctl(ifp, command, data); 2252 break; 2253 } 2254 2255 RL_UNLOCK(sc); 2256 2257 return (error); 2258 } 2259 2260 static void 2261 re_watchdog(ifp) 2262 struct ifnet *ifp; 2263 { 2264 struct rl_softc *sc; 2265 2266 sc = ifp->if_softc; 2267 RL_LOCK(sc); 2268 printf("re%d: watchdog timeout\n", sc->rl_unit); 2269 ifp->if_oerrors++; 2270 2271 re_txeof(sc); 2272 re_rxeof(sc); 2273 2274 re_init(sc); 2275 2276 RL_UNLOCK(sc); 2277 } 2278 2279 /* 2280 * Stop the adapter and free any mbufs allocated to the 2281 * RX and TX lists. 2282 */ 2283 static void 2284 re_stop(sc) 2285 struct rl_softc *sc; 2286 { 2287 register int i; 2288 struct ifnet *ifp; 2289 2290 RL_LOCK(sc); 2291 ifp = &sc->arpcom.ac_if; 2292 ifp->if_timer = 0; 2293 2294 untimeout(re_tick, sc, sc->rl_stat_ch); 2295 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2296 #ifdef DEVICE_POLLING 2297 ether_poll_deregister(ifp); 2298 #endif /* DEVICE_POLLING */ 2299 2300 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2301 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2302 2303 if (sc->rl_head != NULL) { 2304 m_freem(sc->rl_head); 2305 sc->rl_head = sc->rl_tail = NULL; 2306 } 2307 2308 /* Free the TX list buffers. */ 2309 2310 for (i = 0; i < RL_TX_DESC_CNT; i++) { 2311 if (sc->rl_ldata.rl_tx_mbuf[i] != NULL) { 2312 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2313 sc->rl_ldata.rl_tx_dmamap[i]); 2314 m_freem(sc->rl_ldata.rl_tx_mbuf[i]); 2315 sc->rl_ldata.rl_tx_mbuf[i] = NULL; 2316 } 2317 } 2318 2319 /* Free the RX list buffers. */ 2320 2321 for (i = 0; i < RL_RX_DESC_CNT; i++) { 2322 if (sc->rl_ldata.rl_rx_mbuf[i] != NULL) { 2323 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2324 sc->rl_ldata.rl_rx_dmamap[i]); 2325 m_freem(sc->rl_ldata.rl_rx_mbuf[i]); 2326 sc->rl_ldata.rl_rx_mbuf[i] = NULL; 2327 } 2328 } 2329 2330 RL_UNLOCK(sc); 2331 } 2332 2333 /* 2334 * Device suspend routine. Stop the interface and save some PCI 2335 * settings in case the BIOS doesn't restore them properly on 2336 * resume. 2337 */ 2338 static int 2339 re_suspend(dev) 2340 device_t dev; 2341 { 2342 struct rl_softc *sc; 2343 2344 sc = device_get_softc(dev); 2345 2346 re_stop(sc); 2347 sc->suspended = 1; 2348 2349 return (0); 2350 } 2351 2352 /* 2353 * Device resume routine. Restore some PCI settings in case the BIOS 2354 * doesn't, re-enable busmastering, and restart the interface if 2355 * appropriate. 2356 */ 2357 static int 2358 re_resume(dev) 2359 device_t dev; 2360 { 2361 struct rl_softc *sc; 2362 struct ifnet *ifp; 2363 2364 sc = device_get_softc(dev); 2365 ifp = &sc->arpcom.ac_if; 2366 2367 /* reinitialize interface if necessary */ 2368 if (ifp->if_flags & IFF_UP) 2369 re_init(sc); 2370 2371 sc->suspended = 0; 2372 2373 return (0); 2374 } 2375 2376 /* 2377 * Stop all chip I/O so that the kernel's probe routines don't 2378 * get confused by errant DMAs when rebooting. 2379 */ 2380 static void 2381 re_shutdown(dev) 2382 device_t dev; 2383 { 2384 struct rl_softc *sc; 2385 2386 sc = device_get_softc(dev); 2387 2388 re_stop(sc); 2389 } 2390