1 /*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44 /* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111 #ifdef HAVE_KERNEL_OPTION_HEADERS 112 #include "opt_device_polling.h" 113 #endif 114 115 #include <sys/param.h> 116 #include <sys/endian.h> 117 #include <sys/systm.h> 118 #include <sys/sockio.h> 119 #include <sys/mbuf.h> 120 #include <sys/malloc.h> 121 #include <sys/module.h> 122 #include <sys/kernel.h> 123 #include <sys/socket.h> 124 #include <sys/lock.h> 125 #include <sys/mutex.h> 126 #include <sys/sysctl.h> 127 #include <sys/taskqueue.h> 128 129 #include <net/if.h> 130 #include <net/if_arp.h> 131 #include <net/ethernet.h> 132 #include <net/if_dl.h> 133 #include <net/if_media.h> 134 #include <net/if_types.h> 135 #include <net/if_vlan_var.h> 136 137 #include <net/bpf.h> 138 139 #include <machine/bus.h> 140 #include <machine/resource.h> 141 #include <sys/bus.h> 142 #include <sys/rman.h> 143 144 #include <dev/mii/mii.h> 145 #include <dev/mii/miivar.h> 146 147 #include <dev/pci/pcireg.h> 148 #include <dev/pci/pcivar.h> 149 150 #include <pci/if_rlreg.h> 151 152 MODULE_DEPEND(re, pci, 1, 1, 1); 153 MODULE_DEPEND(re, ether, 1, 1, 1); 154 MODULE_DEPEND(re, miibus, 1, 1, 1); 155 156 /* "device miibus" required. See GENERIC if you get errors here. */ 157 #include "miibus_if.h" 158 159 /* Tunables. */ 160 static int intr_filter = 0; 161 TUNABLE_INT("hw.re.intr_filter", &intr_filter); 162 static int msi_disable = 0; 163 TUNABLE_INT("hw.re.msi_disable", &msi_disable); 164 static int msix_disable = 0; 165 TUNABLE_INT("hw.re.msix_disable", &msix_disable); 166 static int prefer_iomap = 0; 167 TUNABLE_INT("hw.re.prefer_iomap", &prefer_iomap); 168 169 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 170 171 /* 172 * Various supported device vendors/types and their names. 173 */ 174 static const struct rl_type re_devs[] = { 175 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0, 176 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 177 { DLINK_VENDORID, DLINK_DEVICEID_530T_REVC, 0, 178 "D-Link DGE-530(T) Gigabit Ethernet Adapter" }, 179 { RT_VENDORID, RT_DEVICEID_8139, 0, 180 "RealTek 8139C+ 10/100BaseTX" }, 181 { RT_VENDORID, RT_DEVICEID_8101E, 0, 182 "RealTek 810xE PCIe 10/100baseTX" }, 183 { RT_VENDORID, RT_DEVICEID_8168, 0, 184 "RealTek 8168/8111 B/C/CP/D/DP/E/F PCIe Gigabit Ethernet" }, 185 { RT_VENDORID, RT_DEVICEID_8169, 0, 186 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" }, 187 { RT_VENDORID, RT_DEVICEID_8169SC, 0, 188 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 189 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0, 190 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 191 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0, 192 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 193 { USR_VENDORID, USR_DEVICEID_997902, 0, 194 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 195 }; 196 197 static const struct rl_hwrev re_hwrevs[] = { 198 { RL_HWREV_8139, RL_8139, "", RL_MTU }, 199 { RL_HWREV_8139A, RL_8139, "A", RL_MTU }, 200 { RL_HWREV_8139AG, RL_8139, "A-G", RL_MTU }, 201 { RL_HWREV_8139B, RL_8139, "B", RL_MTU }, 202 { RL_HWREV_8130, RL_8139, "8130", RL_MTU }, 203 { RL_HWREV_8139C, RL_8139, "C", RL_MTU }, 204 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C", RL_MTU }, 205 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+", RL_MTU }, 206 { RL_HWREV_8168B_SPIN1, RL_8169, "8168", RL_JUMBO_MTU }, 207 { RL_HWREV_8169, RL_8169, "8169", RL_JUMBO_MTU }, 208 { RL_HWREV_8169S, RL_8169, "8169S", RL_JUMBO_MTU }, 209 { RL_HWREV_8110S, RL_8169, "8110S", RL_JUMBO_MTU }, 210 { RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB", RL_JUMBO_MTU }, 211 { RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU }, 212 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL", RL_JUMBO_MTU }, 213 { RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU }, 214 { RL_HWREV_8100, RL_8139, "8100", RL_MTU }, 215 { RL_HWREV_8101, RL_8139, "8101", RL_MTU }, 216 { RL_HWREV_8100E, RL_8169, "8100E", RL_MTU }, 217 { RL_HWREV_8101E, RL_8169, "8101E", RL_MTU }, 218 { RL_HWREV_8102E, RL_8169, "8102E", RL_MTU }, 219 { RL_HWREV_8102EL, RL_8169, "8102EL", RL_MTU }, 220 { RL_HWREV_8102EL_SPIN1, RL_8169, "8102EL", RL_MTU }, 221 { RL_HWREV_8103E, RL_8169, "8103E", RL_MTU }, 222 { RL_HWREV_8401E, RL_8169, "8401E", RL_MTU }, 223 { RL_HWREV_8402, RL_8169, "8402", RL_MTU }, 224 { RL_HWREV_8105E, RL_8169, "8105E", RL_MTU }, 225 { RL_HWREV_8105E_SPIN1, RL_8169, "8105E", RL_MTU }, 226 { RL_HWREV_8168B_SPIN2, RL_8169, "8168", RL_JUMBO_MTU }, 227 { RL_HWREV_8168B_SPIN3, RL_8169, "8168", RL_JUMBO_MTU }, 228 { RL_HWREV_8168C, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K }, 229 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K }, 230 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP", RL_JUMBO_MTU_6K }, 231 { RL_HWREV_8168D, RL_8169, "8168D/8111D", RL_JUMBO_MTU_9K }, 232 { RL_HWREV_8168DP, RL_8169, "8168DP/8111DP", RL_JUMBO_MTU_9K }, 233 { RL_HWREV_8168E, RL_8169, "8168E/8111E", RL_JUMBO_MTU_9K}, 234 { RL_HWREV_8168E_VL, RL_8169, "8168E/8111E-VL", RL_JUMBO_MTU_6K}, 235 { RL_HWREV_8168F, RL_8169, "8168F/8111F", RL_JUMBO_MTU_9K}, 236 { RL_HWREV_8411, RL_8169, "8411", RL_JUMBO_MTU_9K}, 237 { 0, 0, NULL, 0 } 238 }; 239 240 static int re_probe (device_t); 241 static int re_attach (device_t); 242 static int re_detach (device_t); 243 244 static int re_encap (struct rl_softc *, struct mbuf **); 245 246 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 247 static int re_allocmem (device_t, struct rl_softc *); 248 static __inline void re_discard_rxbuf 249 (struct rl_softc *, int); 250 static int re_newbuf (struct rl_softc *, int); 251 static int re_jumbo_newbuf (struct rl_softc *, int); 252 static int re_rx_list_init (struct rl_softc *); 253 static int re_jrx_list_init (struct rl_softc *); 254 static int re_tx_list_init (struct rl_softc *); 255 #ifdef RE_FIXUP_RX 256 static __inline void re_fixup_rx 257 (struct mbuf *); 258 #endif 259 static int re_rxeof (struct rl_softc *, int *); 260 static void re_txeof (struct rl_softc *); 261 #ifdef DEVICE_POLLING 262 static int re_poll (struct ifnet *, enum poll_cmd, int); 263 static int re_poll_locked (struct ifnet *, enum poll_cmd, int); 264 #endif 265 static int re_intr (void *); 266 static void re_intr_msi (void *); 267 static void re_tick (void *); 268 static void re_int_task (void *, int); 269 static void re_start (struct ifnet *); 270 static void re_start_locked (struct ifnet *); 271 static int re_ioctl (struct ifnet *, u_long, caddr_t); 272 static void re_init (void *); 273 static void re_init_locked (struct rl_softc *); 274 static void re_stop (struct rl_softc *); 275 static void re_watchdog (struct rl_softc *); 276 static int re_suspend (device_t); 277 static int re_resume (device_t); 278 static int re_shutdown (device_t); 279 static int re_ifmedia_upd (struct ifnet *); 280 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 281 282 static void re_eeprom_putbyte (struct rl_softc *, int); 283 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 284 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 285 static int re_gmii_readreg (device_t, int, int); 286 static int re_gmii_writereg (device_t, int, int, int); 287 288 static int re_miibus_readreg (device_t, int, int); 289 static int re_miibus_writereg (device_t, int, int, int); 290 static void re_miibus_statchg (device_t); 291 292 static void re_set_jumbo (struct rl_softc *, int); 293 static void re_set_rxmode (struct rl_softc *); 294 static void re_reset (struct rl_softc *); 295 static void re_setwol (struct rl_softc *); 296 static void re_clrwol (struct rl_softc *); 297 static void re_set_linkspeed (struct rl_softc *); 298 299 #ifdef DEV_NETMAP /* see ixgbe.c for details */ 300 #include <dev/netmap/if_re_netmap.h> 301 #endif /* !DEV_NETMAP */ 302 303 #ifdef RE_DIAG 304 static int re_diag (struct rl_softc *); 305 #endif 306 307 static void re_add_sysctls (struct rl_softc *); 308 static int re_sysctl_stats (SYSCTL_HANDLER_ARGS); 309 static int sysctl_int_range (SYSCTL_HANDLER_ARGS, int, int); 310 static int sysctl_hw_re_int_mod (SYSCTL_HANDLER_ARGS); 311 312 static device_method_t re_methods[] = { 313 /* Device interface */ 314 DEVMETHOD(device_probe, re_probe), 315 DEVMETHOD(device_attach, re_attach), 316 DEVMETHOD(device_detach, re_detach), 317 DEVMETHOD(device_suspend, re_suspend), 318 DEVMETHOD(device_resume, re_resume), 319 DEVMETHOD(device_shutdown, re_shutdown), 320 321 /* MII interface */ 322 DEVMETHOD(miibus_readreg, re_miibus_readreg), 323 DEVMETHOD(miibus_writereg, re_miibus_writereg), 324 DEVMETHOD(miibus_statchg, re_miibus_statchg), 325 326 DEVMETHOD_END 327 }; 328 329 static driver_t re_driver = { 330 "re", 331 re_methods, 332 sizeof(struct rl_softc) 333 }; 334 335 static devclass_t re_devclass; 336 337 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 338 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 339 340 #define EE_SET(x) \ 341 CSR_WRITE_1(sc, RL_EECMD, \ 342 CSR_READ_1(sc, RL_EECMD) | x) 343 344 #define EE_CLR(x) \ 345 CSR_WRITE_1(sc, RL_EECMD, \ 346 CSR_READ_1(sc, RL_EECMD) & ~x) 347 348 /* 349 * Send a read command and address to the EEPROM, check for ACK. 350 */ 351 static void 352 re_eeprom_putbyte(struct rl_softc *sc, int addr) 353 { 354 int d, i; 355 356 d = addr | (RL_9346_READ << sc->rl_eewidth); 357 358 /* 359 * Feed in each bit and strobe the clock. 360 */ 361 362 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 363 if (d & i) { 364 EE_SET(RL_EE_DATAIN); 365 } else { 366 EE_CLR(RL_EE_DATAIN); 367 } 368 DELAY(100); 369 EE_SET(RL_EE_CLK); 370 DELAY(150); 371 EE_CLR(RL_EE_CLK); 372 DELAY(100); 373 } 374 } 375 376 /* 377 * Read a word of data stored in the EEPROM at address 'addr.' 378 */ 379 static void 380 re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest) 381 { 382 int i; 383 u_int16_t word = 0; 384 385 /* 386 * Send address of word we want to read. 387 */ 388 re_eeprom_putbyte(sc, addr); 389 390 /* 391 * Start reading bits from EEPROM. 392 */ 393 for (i = 0x8000; i; i >>= 1) { 394 EE_SET(RL_EE_CLK); 395 DELAY(100); 396 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 397 word |= i; 398 EE_CLR(RL_EE_CLK); 399 DELAY(100); 400 } 401 402 *dest = word; 403 } 404 405 /* 406 * Read a sequence of words from the EEPROM. 407 */ 408 static void 409 re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt) 410 { 411 int i; 412 u_int16_t word = 0, *ptr; 413 414 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 415 416 DELAY(100); 417 418 for (i = 0; i < cnt; i++) { 419 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 420 re_eeprom_getword(sc, off + i, &word); 421 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 422 ptr = (u_int16_t *)(dest + (i * 2)); 423 *ptr = word; 424 } 425 426 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 427 } 428 429 static int 430 re_gmii_readreg(device_t dev, int phy, int reg) 431 { 432 struct rl_softc *sc; 433 u_int32_t rval; 434 int i; 435 436 sc = device_get_softc(dev); 437 438 /* Let the rgephy driver read the GMEDIASTAT register */ 439 440 if (reg == RL_GMEDIASTAT) { 441 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 442 return (rval); 443 } 444 445 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 446 447 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 448 rval = CSR_READ_4(sc, RL_PHYAR); 449 if (rval & RL_PHYAR_BUSY) 450 break; 451 DELAY(25); 452 } 453 454 if (i == RL_PHY_TIMEOUT) { 455 device_printf(sc->rl_dev, "PHY read failed\n"); 456 return (0); 457 } 458 459 /* 460 * Controller requires a 20us delay to process next MDIO request. 461 */ 462 DELAY(20); 463 464 return (rval & RL_PHYAR_PHYDATA); 465 } 466 467 static int 468 re_gmii_writereg(device_t dev, int phy, int reg, int data) 469 { 470 struct rl_softc *sc; 471 u_int32_t rval; 472 int i; 473 474 sc = device_get_softc(dev); 475 476 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 477 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 478 479 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 480 rval = CSR_READ_4(sc, RL_PHYAR); 481 if (!(rval & RL_PHYAR_BUSY)) 482 break; 483 DELAY(25); 484 } 485 486 if (i == RL_PHY_TIMEOUT) { 487 device_printf(sc->rl_dev, "PHY write failed\n"); 488 return (0); 489 } 490 491 /* 492 * Controller requires a 20us delay to process next MDIO request. 493 */ 494 DELAY(20); 495 496 return (0); 497 } 498 499 static int 500 re_miibus_readreg(device_t dev, int phy, int reg) 501 { 502 struct rl_softc *sc; 503 u_int16_t rval = 0; 504 u_int16_t re8139_reg = 0; 505 506 sc = device_get_softc(dev); 507 508 if (sc->rl_type == RL_8169) { 509 rval = re_gmii_readreg(dev, phy, reg); 510 return (rval); 511 } 512 513 switch (reg) { 514 case MII_BMCR: 515 re8139_reg = RL_BMCR; 516 break; 517 case MII_BMSR: 518 re8139_reg = RL_BMSR; 519 break; 520 case MII_ANAR: 521 re8139_reg = RL_ANAR; 522 break; 523 case MII_ANER: 524 re8139_reg = RL_ANER; 525 break; 526 case MII_ANLPAR: 527 re8139_reg = RL_LPAR; 528 break; 529 case MII_PHYIDR1: 530 case MII_PHYIDR2: 531 return (0); 532 /* 533 * Allow the rlphy driver to read the media status 534 * register. If we have a link partner which does not 535 * support NWAY, this is the register which will tell 536 * us the results of parallel detection. 537 */ 538 case RL_MEDIASTAT: 539 rval = CSR_READ_1(sc, RL_MEDIASTAT); 540 return (rval); 541 default: 542 device_printf(sc->rl_dev, "bad phy register\n"); 543 return (0); 544 } 545 rval = CSR_READ_2(sc, re8139_reg); 546 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 547 /* 8139C+ has different bit layout. */ 548 rval &= ~(BMCR_LOOP | BMCR_ISO); 549 } 550 return (rval); 551 } 552 553 static int 554 re_miibus_writereg(device_t dev, int phy, int reg, int data) 555 { 556 struct rl_softc *sc; 557 u_int16_t re8139_reg = 0; 558 int rval = 0; 559 560 sc = device_get_softc(dev); 561 562 if (sc->rl_type == RL_8169) { 563 rval = re_gmii_writereg(dev, phy, reg, data); 564 return (rval); 565 } 566 567 switch (reg) { 568 case MII_BMCR: 569 re8139_reg = RL_BMCR; 570 if (sc->rl_type == RL_8139CPLUS) { 571 /* 8139C+ has different bit layout. */ 572 data &= ~(BMCR_LOOP | BMCR_ISO); 573 } 574 break; 575 case MII_BMSR: 576 re8139_reg = RL_BMSR; 577 break; 578 case MII_ANAR: 579 re8139_reg = RL_ANAR; 580 break; 581 case MII_ANER: 582 re8139_reg = RL_ANER; 583 break; 584 case MII_ANLPAR: 585 re8139_reg = RL_LPAR; 586 break; 587 case MII_PHYIDR1: 588 case MII_PHYIDR2: 589 return (0); 590 break; 591 default: 592 device_printf(sc->rl_dev, "bad phy register\n"); 593 return (0); 594 } 595 CSR_WRITE_2(sc, re8139_reg, data); 596 return (0); 597 } 598 599 static void 600 re_miibus_statchg(device_t dev) 601 { 602 struct rl_softc *sc; 603 struct ifnet *ifp; 604 struct mii_data *mii; 605 606 sc = device_get_softc(dev); 607 mii = device_get_softc(sc->rl_miibus); 608 ifp = sc->rl_ifp; 609 if (mii == NULL || ifp == NULL || 610 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 611 return; 612 613 sc->rl_flags &= ~RL_FLAG_LINK; 614 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 615 (IFM_ACTIVE | IFM_AVALID)) { 616 switch (IFM_SUBTYPE(mii->mii_media_active)) { 617 case IFM_10_T: 618 case IFM_100_TX: 619 sc->rl_flags |= RL_FLAG_LINK; 620 break; 621 case IFM_1000_T: 622 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0) 623 break; 624 sc->rl_flags |= RL_FLAG_LINK; 625 break; 626 default: 627 break; 628 } 629 } 630 /* 631 * RealTek controllers does not provide any interface to 632 * Tx/Rx MACs for resolved speed, duplex and flow-control 633 * parameters. 634 */ 635 } 636 637 /* 638 * Set the RX configuration and 64-bit multicast hash filter. 639 */ 640 static void 641 re_set_rxmode(struct rl_softc *sc) 642 { 643 struct ifnet *ifp; 644 struct ifmultiaddr *ifma; 645 uint32_t hashes[2] = { 0, 0 }; 646 uint32_t h, rxfilt; 647 648 RL_LOCK_ASSERT(sc); 649 650 ifp = sc->rl_ifp; 651 652 rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD; 653 654 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 655 if (ifp->if_flags & IFF_PROMISC) 656 rxfilt |= RL_RXCFG_RX_ALLPHYS; 657 /* 658 * Unlike other hardwares, we have to explicitly set 659 * RL_RXCFG_RX_MULTI to receive multicast frames in 660 * promiscuous mode. 661 */ 662 rxfilt |= RL_RXCFG_RX_MULTI; 663 hashes[0] = hashes[1] = 0xffffffff; 664 goto done; 665 } 666 667 if_maddr_rlock(ifp); 668 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 669 if (ifma->ifma_addr->sa_family != AF_LINK) 670 continue; 671 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 672 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 673 if (h < 32) 674 hashes[0] |= (1 << h); 675 else 676 hashes[1] |= (1 << (h - 32)); 677 } 678 if_maddr_runlock(ifp); 679 680 if (hashes[0] != 0 || hashes[1] != 0) { 681 /* 682 * For some unfathomable reason, RealTek decided to 683 * reverse the order of the multicast hash registers 684 * in the PCI Express parts. This means we have to 685 * write the hash pattern in reverse order for those 686 * devices. 687 */ 688 if ((sc->rl_flags & RL_FLAG_PCIE) != 0) { 689 h = bswap32(hashes[0]); 690 hashes[0] = bswap32(hashes[1]); 691 hashes[1] = h; 692 } 693 rxfilt |= RL_RXCFG_RX_MULTI; 694 } 695 696 done: 697 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 698 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 699 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 700 } 701 702 static void 703 re_reset(struct rl_softc *sc) 704 { 705 int i; 706 707 RL_LOCK_ASSERT(sc); 708 709 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 710 711 for (i = 0; i < RL_TIMEOUT; i++) { 712 DELAY(10); 713 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 714 break; 715 } 716 if (i == RL_TIMEOUT) 717 device_printf(sc->rl_dev, "reset never completed!\n"); 718 719 if ((sc->rl_flags & RL_FLAG_MACRESET) != 0) 720 CSR_WRITE_1(sc, 0x82, 1); 721 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169S) 722 re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0); 723 } 724 725 #ifdef RE_DIAG 726 727 /* 728 * The following routine is designed to test for a defect on some 729 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 730 * lines connected to the bus, however for a 32-bit only card, they 731 * should be pulled high. The result of this defect is that the 732 * NIC will not work right if you plug it into a 64-bit slot: DMA 733 * operations will be done with 64-bit transfers, which will fail 734 * because the 64-bit data lines aren't connected. 735 * 736 * There's no way to work around this (short of talking a soldering 737 * iron to the board), however we can detect it. The method we use 738 * here is to put the NIC into digital loopback mode, set the receiver 739 * to promiscuous mode, and then try to send a frame. We then compare 740 * the frame data we sent to what was received. If the data matches, 741 * then the NIC is working correctly, otherwise we know the user has 742 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 743 * slot. In the latter case, there's no way the NIC can work correctly, 744 * so we print out a message on the console and abort the device attach. 745 */ 746 747 static int 748 re_diag(struct rl_softc *sc) 749 { 750 struct ifnet *ifp = sc->rl_ifp; 751 struct mbuf *m0; 752 struct ether_header *eh; 753 struct rl_desc *cur_rx; 754 u_int16_t status; 755 u_int32_t rxstat; 756 int total_len, i, error = 0, phyaddr; 757 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 758 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 759 760 /* Allocate a single mbuf */ 761 MGETHDR(m0, M_NOWAIT, MT_DATA); 762 if (m0 == NULL) 763 return (ENOBUFS); 764 765 RL_LOCK(sc); 766 767 /* 768 * Initialize the NIC in test mode. This sets the chip up 769 * so that it can send and receive frames, but performs the 770 * following special functions: 771 * - Puts receiver in promiscuous mode 772 * - Enables digital loopback mode 773 * - Leaves interrupts turned off 774 */ 775 776 ifp->if_flags |= IFF_PROMISC; 777 sc->rl_testmode = 1; 778 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 779 re_init_locked(sc); 780 sc->rl_flags |= RL_FLAG_LINK; 781 if (sc->rl_type == RL_8169) 782 phyaddr = 1; 783 else 784 phyaddr = 0; 785 786 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 787 for (i = 0; i < RL_TIMEOUT; i++) { 788 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 789 if (!(status & BMCR_RESET)) 790 break; 791 } 792 793 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 794 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 795 796 DELAY(100000); 797 798 /* Put some data in the mbuf */ 799 800 eh = mtod(m0, struct ether_header *); 801 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 802 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 803 eh->ether_type = htons(ETHERTYPE_IP); 804 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 805 806 /* 807 * Queue the packet, start transmission. 808 * Note: IF_HANDOFF() ultimately calls re_start() for us. 809 */ 810 811 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 812 RL_UNLOCK(sc); 813 /* XXX: re_diag must not be called when in ALTQ mode */ 814 IF_HANDOFF(&ifp->if_snd, m0, ifp); 815 RL_LOCK(sc); 816 m0 = NULL; 817 818 /* Wait for it to propagate through the chip */ 819 820 DELAY(100000); 821 for (i = 0; i < RL_TIMEOUT; i++) { 822 status = CSR_READ_2(sc, RL_ISR); 823 CSR_WRITE_2(sc, RL_ISR, status); 824 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 825 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 826 break; 827 DELAY(10); 828 } 829 830 if (i == RL_TIMEOUT) { 831 device_printf(sc->rl_dev, 832 "diagnostic failed, failed to receive packet in" 833 " loopback mode\n"); 834 error = EIO; 835 goto done; 836 } 837 838 /* 839 * The packet should have been dumped into the first 840 * entry in the RX DMA ring. Grab it from there. 841 */ 842 843 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 844 sc->rl_ldata.rl_rx_list_map, 845 BUS_DMASYNC_POSTREAD); 846 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 847 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 848 BUS_DMASYNC_POSTREAD); 849 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 850 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 851 852 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 853 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 854 eh = mtod(m0, struct ether_header *); 855 856 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 857 total_len = RL_RXBYTES(cur_rx); 858 rxstat = le32toh(cur_rx->rl_cmdstat); 859 860 if (total_len != ETHER_MIN_LEN) { 861 device_printf(sc->rl_dev, 862 "diagnostic failed, received short packet\n"); 863 error = EIO; 864 goto done; 865 } 866 867 /* Test that the received packet data matches what we sent. */ 868 869 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 870 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 871 ntohs(eh->ether_type) != ETHERTYPE_IP) { 872 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 873 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 874 dst, ":", src, ":", ETHERTYPE_IP); 875 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 876 eh->ether_dhost, ":", eh->ether_shost, ":", 877 ntohs(eh->ether_type)); 878 device_printf(sc->rl_dev, "You may have a defective 32-bit " 879 "NIC plugged into a 64-bit PCI slot.\n"); 880 device_printf(sc->rl_dev, "Please re-install the NIC in a " 881 "32-bit slot for proper operation.\n"); 882 device_printf(sc->rl_dev, "Read the re(4) man page for more " 883 "details.\n"); 884 error = EIO; 885 } 886 887 done: 888 /* Turn interface off, release resources */ 889 890 sc->rl_testmode = 0; 891 sc->rl_flags &= ~RL_FLAG_LINK; 892 ifp->if_flags &= ~IFF_PROMISC; 893 re_stop(sc); 894 if (m0 != NULL) 895 m_freem(m0); 896 897 RL_UNLOCK(sc); 898 899 return (error); 900 } 901 902 #endif 903 904 /* 905 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 906 * IDs against our list and return a device name if we find a match. 907 */ 908 static int 909 re_probe(device_t dev) 910 { 911 const struct rl_type *t; 912 uint16_t devid, vendor; 913 uint16_t revid, sdevid; 914 int i; 915 916 vendor = pci_get_vendor(dev); 917 devid = pci_get_device(dev); 918 revid = pci_get_revid(dev); 919 sdevid = pci_get_subdevice(dev); 920 921 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 922 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 923 /* 924 * Only attach to rev. 3 of the Linksys EG1032 adapter. 925 * Rev. 2 is supported by sk(4). 926 */ 927 return (ENXIO); 928 } 929 } 930 931 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 932 if (revid != 0x20) { 933 /* 8139, let rl(4) take care of this device. */ 934 return (ENXIO); 935 } 936 } 937 938 t = re_devs; 939 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) { 940 if (vendor == t->rl_vid && devid == t->rl_did) { 941 device_set_desc(dev, t->rl_name); 942 return (BUS_PROBE_DEFAULT); 943 } 944 } 945 946 return (ENXIO); 947 } 948 949 /* 950 * Map a single buffer address. 951 */ 952 953 static void 954 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 955 { 956 bus_addr_t *addr; 957 958 if (error) 959 return; 960 961 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 962 addr = arg; 963 *addr = segs->ds_addr; 964 } 965 966 static int 967 re_allocmem(device_t dev, struct rl_softc *sc) 968 { 969 bus_addr_t lowaddr; 970 bus_size_t rx_list_size, tx_list_size; 971 int error; 972 int i; 973 974 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 975 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 976 977 /* 978 * Allocate the parent bus DMA tag appropriate for PCI. 979 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD 980 * register should be set. However some RealTek chips are known 981 * to be buggy on DAC handling, therefore disable DAC by limiting 982 * DMA address space to 32bit. PCIe variants of RealTek chips 983 * may not have the limitation. 984 */ 985 lowaddr = BUS_SPACE_MAXADDR; 986 if ((sc->rl_flags & RL_FLAG_PCIE) == 0) 987 lowaddr = BUS_SPACE_MAXADDR_32BIT; 988 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 989 lowaddr, BUS_SPACE_MAXADDR, NULL, NULL, 990 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 991 NULL, NULL, &sc->rl_parent_tag); 992 if (error) { 993 device_printf(dev, "could not allocate parent DMA tag\n"); 994 return (error); 995 } 996 997 /* 998 * Allocate map for TX mbufs. 999 */ 1000 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 1001 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1002 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 1003 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 1004 if (error) { 1005 device_printf(dev, "could not allocate TX DMA tag\n"); 1006 return (error); 1007 } 1008 1009 /* 1010 * Allocate map for RX mbufs. 1011 */ 1012 1013 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 1014 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 1015 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1016 MJUM9BYTES, 1, MJUM9BYTES, 0, NULL, NULL, 1017 &sc->rl_ldata.rl_jrx_mtag); 1018 if (error) { 1019 device_printf(dev, 1020 "could not allocate jumbo RX DMA tag\n"); 1021 return (error); 1022 } 1023 } 1024 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 1025 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1026 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 1027 if (error) { 1028 device_printf(dev, "could not allocate RX DMA tag\n"); 1029 return (error); 1030 } 1031 1032 /* 1033 * Allocate map for TX descriptor list. 1034 */ 1035 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1036 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1037 NULL, tx_list_size, 1, tx_list_size, 0, 1038 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1039 if (error) { 1040 device_printf(dev, "could not allocate TX DMA ring tag\n"); 1041 return (error); 1042 } 1043 1044 /* Allocate DMA'able memory for the TX ring */ 1045 1046 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1047 (void **)&sc->rl_ldata.rl_tx_list, 1048 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1049 &sc->rl_ldata.rl_tx_list_map); 1050 if (error) { 1051 device_printf(dev, "could not allocate TX DMA ring\n"); 1052 return (error); 1053 } 1054 1055 /* Load the map for the TX ring. */ 1056 1057 sc->rl_ldata.rl_tx_list_addr = 0; 1058 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1059 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1060 tx_list_size, re_dma_map_addr, 1061 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1062 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 1063 device_printf(dev, "could not load TX DMA ring\n"); 1064 return (ENOMEM); 1065 } 1066 1067 /* Create DMA maps for TX buffers */ 1068 1069 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1070 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1071 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1072 if (error) { 1073 device_printf(dev, "could not create DMA map for TX\n"); 1074 return (error); 1075 } 1076 } 1077 1078 /* 1079 * Allocate map for RX descriptor list. 1080 */ 1081 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1082 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1083 NULL, rx_list_size, 1, rx_list_size, 0, 1084 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1085 if (error) { 1086 device_printf(dev, "could not create RX DMA ring tag\n"); 1087 return (error); 1088 } 1089 1090 /* Allocate DMA'able memory for the RX ring */ 1091 1092 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1093 (void **)&sc->rl_ldata.rl_rx_list, 1094 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1095 &sc->rl_ldata.rl_rx_list_map); 1096 if (error) { 1097 device_printf(dev, "could not allocate RX DMA ring\n"); 1098 return (error); 1099 } 1100 1101 /* Load the map for the RX ring. */ 1102 1103 sc->rl_ldata.rl_rx_list_addr = 0; 1104 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1105 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1106 rx_list_size, re_dma_map_addr, 1107 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1108 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1109 device_printf(dev, "could not load RX DMA ring\n"); 1110 return (ENOMEM); 1111 } 1112 1113 /* Create DMA maps for RX buffers */ 1114 1115 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 1116 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0, 1117 &sc->rl_ldata.rl_jrx_sparemap); 1118 if (error) { 1119 device_printf(dev, 1120 "could not create spare DMA map for jumbo RX\n"); 1121 return (error); 1122 } 1123 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1124 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0, 1125 &sc->rl_ldata.rl_jrx_desc[i].rx_dmamap); 1126 if (error) { 1127 device_printf(dev, 1128 "could not create DMA map for jumbo RX\n"); 1129 return (error); 1130 } 1131 } 1132 } 1133 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1134 &sc->rl_ldata.rl_rx_sparemap); 1135 if (error) { 1136 device_printf(dev, "could not create spare DMA map for RX\n"); 1137 return (error); 1138 } 1139 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1140 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1141 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1142 if (error) { 1143 device_printf(dev, "could not create DMA map for RX\n"); 1144 return (error); 1145 } 1146 } 1147 1148 /* Create DMA map for statistics. */ 1149 error = bus_dma_tag_create(sc->rl_parent_tag, RL_DUMP_ALIGN, 0, 1150 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1151 sizeof(struct rl_stats), 1, sizeof(struct rl_stats), 0, NULL, NULL, 1152 &sc->rl_ldata.rl_stag); 1153 if (error) { 1154 device_printf(dev, "could not create statistics DMA tag\n"); 1155 return (error); 1156 } 1157 /* Allocate DMA'able memory for statistics. */ 1158 error = bus_dmamem_alloc(sc->rl_ldata.rl_stag, 1159 (void **)&sc->rl_ldata.rl_stats, 1160 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1161 &sc->rl_ldata.rl_smap); 1162 if (error) { 1163 device_printf(dev, 1164 "could not allocate statistics DMA memory\n"); 1165 return (error); 1166 } 1167 /* Load the map for statistics. */ 1168 sc->rl_ldata.rl_stats_addr = 0; 1169 error = bus_dmamap_load(sc->rl_ldata.rl_stag, sc->rl_ldata.rl_smap, 1170 sc->rl_ldata.rl_stats, sizeof(struct rl_stats), re_dma_map_addr, 1171 &sc->rl_ldata.rl_stats_addr, BUS_DMA_NOWAIT); 1172 if (error != 0 || sc->rl_ldata.rl_stats_addr == 0) { 1173 device_printf(dev, "could not load statistics DMA memory\n"); 1174 return (ENOMEM); 1175 } 1176 1177 return (0); 1178 } 1179 1180 /* 1181 * Attach the interface. Allocate softc structures, do ifmedia 1182 * setup and ethernet/BPF attach. 1183 */ 1184 static int 1185 re_attach(device_t dev) 1186 { 1187 u_char eaddr[ETHER_ADDR_LEN]; 1188 u_int16_t as[ETHER_ADDR_LEN / 2]; 1189 struct rl_softc *sc; 1190 struct ifnet *ifp; 1191 const struct rl_hwrev *hw_rev; 1192 u_int32_t cap, ctl; 1193 int hwrev; 1194 u_int16_t devid, re_did = 0; 1195 int error = 0, i, phy, rid; 1196 int msic, msixc, reg; 1197 uint8_t cfg; 1198 1199 sc = device_get_softc(dev); 1200 sc->rl_dev = dev; 1201 1202 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1203 MTX_DEF); 1204 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1205 1206 /* 1207 * Map control/status registers. 1208 */ 1209 pci_enable_busmaster(dev); 1210 1211 devid = pci_get_device(dev); 1212 /* 1213 * Prefer memory space register mapping over IO space. 1214 * Because RTL8169SC does not seem to work when memory mapping 1215 * is used always activate io mapping. 1216 */ 1217 if (devid == RT_DEVICEID_8169SC) 1218 prefer_iomap = 1; 1219 if (prefer_iomap == 0) { 1220 sc->rl_res_id = PCIR_BAR(1); 1221 sc->rl_res_type = SYS_RES_MEMORY; 1222 /* RTL8168/8101E seems to use different BARs. */ 1223 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E) 1224 sc->rl_res_id = PCIR_BAR(2); 1225 } else { 1226 sc->rl_res_id = PCIR_BAR(0); 1227 sc->rl_res_type = SYS_RES_IOPORT; 1228 } 1229 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1230 &sc->rl_res_id, RF_ACTIVE); 1231 if (sc->rl_res == NULL && prefer_iomap == 0) { 1232 sc->rl_res_id = PCIR_BAR(0); 1233 sc->rl_res_type = SYS_RES_IOPORT; 1234 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1235 &sc->rl_res_id, RF_ACTIVE); 1236 } 1237 if (sc->rl_res == NULL) { 1238 device_printf(dev, "couldn't map ports/memory\n"); 1239 error = ENXIO; 1240 goto fail; 1241 } 1242 1243 sc->rl_btag = rman_get_bustag(sc->rl_res); 1244 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1245 1246 msic = pci_msi_count(dev); 1247 msixc = pci_msix_count(dev); 1248 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 1249 sc->rl_flags |= RL_FLAG_PCIE; 1250 sc->rl_expcap = reg; 1251 } 1252 if (bootverbose) { 1253 device_printf(dev, "MSI count : %d\n", msic); 1254 device_printf(dev, "MSI-X count : %d\n", msixc); 1255 } 1256 if (msix_disable > 0) 1257 msixc = 0; 1258 if (msi_disable > 0) 1259 msic = 0; 1260 /* Prefer MSI-X to MSI. */ 1261 if (msixc > 0) { 1262 msixc = 1; 1263 rid = PCIR_BAR(4); 1264 sc->rl_res_pba = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1265 &rid, RF_ACTIVE); 1266 if (sc->rl_res_pba == NULL) { 1267 device_printf(sc->rl_dev, 1268 "could not allocate MSI-X PBA resource\n"); 1269 } 1270 if (sc->rl_res_pba != NULL && 1271 pci_alloc_msix(dev, &msixc) == 0) { 1272 if (msixc == 1) { 1273 device_printf(dev, "Using %d MSI-X message\n", 1274 msixc); 1275 sc->rl_flags |= RL_FLAG_MSIX; 1276 } else 1277 pci_release_msi(dev); 1278 } 1279 if ((sc->rl_flags & RL_FLAG_MSIX) == 0) { 1280 if (sc->rl_res_pba != NULL) 1281 bus_release_resource(dev, SYS_RES_MEMORY, rid, 1282 sc->rl_res_pba); 1283 sc->rl_res_pba = NULL; 1284 msixc = 0; 1285 } 1286 } 1287 /* Prefer MSI to INTx. */ 1288 if (msixc == 0 && msic > 0) { 1289 msic = 1; 1290 if (pci_alloc_msi(dev, &msic) == 0) { 1291 if (msic == RL_MSI_MESSAGES) { 1292 device_printf(dev, "Using %d MSI message\n", 1293 msic); 1294 sc->rl_flags |= RL_FLAG_MSI; 1295 /* Explicitly set MSI enable bit. */ 1296 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1297 cfg = CSR_READ_1(sc, RL_CFG2); 1298 cfg |= RL_CFG2_MSI; 1299 CSR_WRITE_1(sc, RL_CFG2, cfg); 1300 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1301 } else 1302 pci_release_msi(dev); 1303 } 1304 if ((sc->rl_flags & RL_FLAG_MSI) == 0) 1305 msic = 0; 1306 } 1307 1308 /* Allocate interrupt */ 1309 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) { 1310 rid = 0; 1311 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1312 RF_SHAREABLE | RF_ACTIVE); 1313 if (sc->rl_irq[0] == NULL) { 1314 device_printf(dev, "couldn't allocate IRQ resources\n"); 1315 error = ENXIO; 1316 goto fail; 1317 } 1318 } else { 1319 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1320 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1321 SYS_RES_IRQ, &rid, RF_ACTIVE); 1322 if (sc->rl_irq[i] == NULL) { 1323 device_printf(dev, 1324 "couldn't llocate IRQ resources for " 1325 "message %d\n", rid); 1326 error = ENXIO; 1327 goto fail; 1328 } 1329 } 1330 } 1331 1332 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1333 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1334 cfg = CSR_READ_1(sc, RL_CFG2); 1335 if ((cfg & RL_CFG2_MSI) != 0) { 1336 device_printf(dev, "turning off MSI enable bit.\n"); 1337 cfg &= ~RL_CFG2_MSI; 1338 CSR_WRITE_1(sc, RL_CFG2, cfg); 1339 } 1340 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1341 } 1342 1343 /* Disable ASPM L0S/L1. */ 1344 if (sc->rl_expcap != 0) { 1345 cap = pci_read_config(dev, sc->rl_expcap + 1346 PCIER_LINK_CAP, 2); 1347 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { 1348 ctl = pci_read_config(dev, sc->rl_expcap + 1349 PCIER_LINK_CTL, 2); 1350 if ((ctl & PCIEM_LINK_CTL_ASPMC) != 0) { 1351 ctl &= ~PCIEM_LINK_CTL_ASPMC; 1352 pci_write_config(dev, sc->rl_expcap + 1353 PCIER_LINK_CTL, ctl, 2); 1354 device_printf(dev, "ASPM disabled\n"); 1355 } 1356 } else 1357 device_printf(dev, "no ASPM capability\n"); 1358 } 1359 1360 hw_rev = re_hwrevs; 1361 hwrev = CSR_READ_4(sc, RL_TXCFG); 1362 switch (hwrev & 0x70000000) { 1363 case 0x00000000: 1364 case 0x10000000: 1365 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000); 1366 hwrev &= (RL_TXCFG_HWREV | 0x80000000); 1367 break; 1368 default: 1369 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000); 1370 hwrev &= RL_TXCFG_HWREV; 1371 break; 1372 } 1373 device_printf(dev, "MAC rev. 0x%08x\n", hwrev & 0x00700000); 1374 while (hw_rev->rl_desc != NULL) { 1375 if (hw_rev->rl_rev == hwrev) { 1376 sc->rl_type = hw_rev->rl_type; 1377 sc->rl_hwrev = hw_rev; 1378 break; 1379 } 1380 hw_rev++; 1381 } 1382 if (hw_rev->rl_desc == NULL) { 1383 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev); 1384 error = ENXIO; 1385 goto fail; 1386 } 1387 1388 switch (hw_rev->rl_rev) { 1389 case RL_HWREV_8139CPLUS: 1390 sc->rl_flags |= RL_FLAG_FASTETHER | RL_FLAG_AUTOPAD; 1391 break; 1392 case RL_HWREV_8100E: 1393 case RL_HWREV_8101E: 1394 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_FASTETHER; 1395 break; 1396 case RL_HWREV_8102E: 1397 case RL_HWREV_8102EL: 1398 case RL_HWREV_8102EL_SPIN1: 1399 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1400 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | 1401 RL_FLAG_AUTOPAD; 1402 break; 1403 case RL_HWREV_8103E: 1404 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1405 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | 1406 RL_FLAG_AUTOPAD | RL_FLAG_MACSLEEP; 1407 break; 1408 case RL_HWREV_8401E: 1409 case RL_HWREV_8105E: 1410 case RL_HWREV_8105E_SPIN1: 1411 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1412 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1413 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD; 1414 break; 1415 case RL_HWREV_8402: 1416 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1417 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1418 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | 1419 RL_FLAG_CMDSTOP_WAIT_TXQ; 1420 break; 1421 case RL_HWREV_8168B_SPIN1: 1422 case RL_HWREV_8168B_SPIN2: 1423 sc->rl_flags |= RL_FLAG_WOLRXENB; 1424 /* FALLTHROUGH */ 1425 case RL_HWREV_8168B_SPIN3: 1426 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT; 1427 break; 1428 case RL_HWREV_8168C_SPIN2: 1429 sc->rl_flags |= RL_FLAG_MACSLEEP; 1430 /* FALLTHROUGH */ 1431 case RL_HWREV_8168C: 1432 if ((hwrev & 0x00700000) == 0x00200000) 1433 sc->rl_flags |= RL_FLAG_MACSLEEP; 1434 /* FALLTHROUGH */ 1435 case RL_HWREV_8168CP: 1436 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1437 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1438 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK; 1439 break; 1440 case RL_HWREV_8168D: 1441 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1442 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1443 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1444 RL_FLAG_WOL_MANLINK; 1445 break; 1446 case RL_HWREV_8168DP: 1447 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1448 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_AUTOPAD | 1449 RL_FLAG_JUMBOV2 | RL_FLAG_WAIT_TXPOLL | RL_FLAG_WOL_MANLINK; 1450 break; 1451 case RL_HWREV_8168E: 1452 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1453 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1454 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1455 RL_FLAG_WOL_MANLINK; 1456 break; 1457 case RL_HWREV_8168E_VL: 1458 case RL_HWREV_8168F: 1459 case RL_HWREV_8411: 1460 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1461 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1462 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1463 RL_FLAG_CMDSTOP_WAIT_TXQ | RL_FLAG_WOL_MANLINK; 1464 break; 1465 case RL_HWREV_8169_8110SB: 1466 case RL_HWREV_8169_8110SBL: 1467 case RL_HWREV_8169_8110SC: 1468 case RL_HWREV_8169_8110SCE: 1469 sc->rl_flags |= RL_FLAG_PHYWAKE; 1470 /* FALLTHROUGH */ 1471 case RL_HWREV_8169: 1472 case RL_HWREV_8169S: 1473 case RL_HWREV_8110S: 1474 sc->rl_flags |= RL_FLAG_MACRESET; 1475 break; 1476 default: 1477 break; 1478 } 1479 1480 if (sc->rl_hwrev->rl_rev == RL_HWREV_8139CPLUS) { 1481 sc->rl_cfg0 = RL_8139_CFG0; 1482 sc->rl_cfg1 = RL_8139_CFG1; 1483 sc->rl_cfg2 = 0; 1484 sc->rl_cfg3 = RL_8139_CFG3; 1485 sc->rl_cfg4 = RL_8139_CFG4; 1486 sc->rl_cfg5 = RL_8139_CFG5; 1487 } else { 1488 sc->rl_cfg0 = RL_CFG0; 1489 sc->rl_cfg1 = RL_CFG1; 1490 sc->rl_cfg2 = RL_CFG2; 1491 sc->rl_cfg3 = RL_CFG3; 1492 sc->rl_cfg4 = RL_CFG4; 1493 sc->rl_cfg5 = RL_CFG5; 1494 } 1495 1496 /* Reset the adapter. */ 1497 RL_LOCK(sc); 1498 re_reset(sc); 1499 RL_UNLOCK(sc); 1500 1501 /* Enable PME. */ 1502 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1503 cfg = CSR_READ_1(sc, sc->rl_cfg1); 1504 cfg |= RL_CFG1_PME; 1505 CSR_WRITE_1(sc, sc->rl_cfg1, cfg); 1506 cfg = CSR_READ_1(sc, sc->rl_cfg5); 1507 cfg &= RL_CFG5_PME_STS; 1508 CSR_WRITE_1(sc, sc->rl_cfg5, cfg); 1509 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1510 1511 if ((sc->rl_flags & RL_FLAG_PAR) != 0) { 1512 /* 1513 * XXX Should have a better way to extract station 1514 * address from EEPROM. 1515 */ 1516 for (i = 0; i < ETHER_ADDR_LEN; i++) 1517 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1518 } else { 1519 sc->rl_eewidth = RL_9356_ADDR_LEN; 1520 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1521 if (re_did != 0x8129) 1522 sc->rl_eewidth = RL_9346_ADDR_LEN; 1523 1524 /* 1525 * Get station address from the EEPROM. 1526 */ 1527 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1528 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1529 as[i] = le16toh(as[i]); 1530 bcopy(as, eaddr, ETHER_ADDR_LEN); 1531 } 1532 1533 if (sc->rl_type == RL_8169) { 1534 /* Set RX length mask and number of descriptors. */ 1535 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1536 sc->rl_txstart = RL_GTXSTART; 1537 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1538 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1539 } else { 1540 /* Set RX length mask and number of descriptors. */ 1541 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1542 sc->rl_txstart = RL_TXSTART; 1543 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1544 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1545 } 1546 1547 error = re_allocmem(dev, sc); 1548 if (error) 1549 goto fail; 1550 re_add_sysctls(sc); 1551 1552 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1553 if (ifp == NULL) { 1554 device_printf(dev, "can not if_alloc()\n"); 1555 error = ENOSPC; 1556 goto fail; 1557 } 1558 1559 /* Take controller out of deep sleep mode. */ 1560 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 1561 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 1562 CSR_WRITE_1(sc, RL_GPIO, 1563 CSR_READ_1(sc, RL_GPIO) | 0x01); 1564 else 1565 CSR_WRITE_1(sc, RL_GPIO, 1566 CSR_READ_1(sc, RL_GPIO) & ~0x01); 1567 } 1568 1569 /* Take PHY out of power down mode. */ 1570 if ((sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) { 1571 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80); 1572 if (hw_rev->rl_rev == RL_HWREV_8401E) 1573 CSR_WRITE_1(sc, 0xD1, CSR_READ_1(sc, 0xD1) & ~0x08); 1574 } 1575 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) { 1576 re_gmii_writereg(dev, 1, 0x1f, 0); 1577 re_gmii_writereg(dev, 1, 0x0e, 0); 1578 } 1579 1580 ifp->if_softc = sc; 1581 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1582 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1583 ifp->if_ioctl = re_ioctl; 1584 ifp->if_start = re_start; 1585 /* 1586 * RTL8168/8111C generates wrong IP checksummed frame if the 1587 * packet has IP options so disable TX IP checksum offloading. 1588 */ 1589 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168C || 1590 sc->rl_hwrev->rl_rev == RL_HWREV_8168C_SPIN2 || 1591 sc->rl_hwrev->rl_rev == RL_HWREV_8168CP) 1592 ifp->if_hwassist = CSUM_TCP | CSUM_UDP; 1593 else 1594 ifp->if_hwassist = CSUM_IP | CSUM_TCP | CSUM_UDP; 1595 ifp->if_hwassist |= CSUM_TSO; 1596 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 1597 ifp->if_capenable = ifp->if_capabilities; 1598 ifp->if_init = re_init; 1599 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1600 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1601 IFQ_SET_READY(&ifp->if_snd); 1602 1603 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1604 1605 #define RE_PHYAD_INTERNAL 0 1606 1607 /* Do MII setup. */ 1608 phy = RE_PHYAD_INTERNAL; 1609 if (sc->rl_type == RL_8169) 1610 phy = 1; 1611 error = mii_attach(dev, &sc->rl_miibus, ifp, re_ifmedia_upd, 1612 re_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, MIIF_DOPAUSE); 1613 if (error != 0) { 1614 device_printf(dev, "attaching PHYs failed\n"); 1615 goto fail; 1616 } 1617 1618 /* 1619 * Call MI attach routine. 1620 */ 1621 ether_ifattach(ifp, eaddr); 1622 1623 /* VLAN capability setup */ 1624 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1625 if (ifp->if_capabilities & IFCAP_HWCSUM) 1626 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1627 /* Enable WOL if PM is supported. */ 1628 if (pci_find_cap(sc->rl_dev, PCIY_PMG, ®) == 0) 1629 ifp->if_capabilities |= IFCAP_WOL; 1630 ifp->if_capenable = ifp->if_capabilities; 1631 ifp->if_capenable &= ~(IFCAP_WOL_UCAST | IFCAP_WOL_MCAST); 1632 /* 1633 * Don't enable TSO by default. It is known to generate 1634 * corrupted TCP segments(bad TCP options) under certain 1635 * circumtances. 1636 */ 1637 ifp->if_hwassist &= ~CSUM_TSO; 1638 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO); 1639 #ifdef DEVICE_POLLING 1640 ifp->if_capabilities |= IFCAP_POLLING; 1641 #endif 1642 /* 1643 * Tell the upper layer(s) we support long frames. 1644 * Must appear after the call to ether_ifattach() because 1645 * ether_ifattach() sets ifi_hdrlen to the default value. 1646 */ 1647 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1648 1649 #ifdef DEV_NETMAP 1650 re_netmap_attach(sc); 1651 #endif /* DEV_NETMAP */ 1652 #ifdef RE_DIAG 1653 /* 1654 * Perform hardware diagnostic on the original RTL8169. 1655 * Some 32-bit cards were incorrectly wired and would 1656 * malfunction if plugged into a 64-bit slot. 1657 */ 1658 1659 if (hwrev == RL_HWREV_8169) { 1660 error = re_diag(sc); 1661 if (error) { 1662 device_printf(dev, 1663 "attach aborted due to hardware diag failure\n"); 1664 ether_ifdetach(ifp); 1665 goto fail; 1666 } 1667 } 1668 #endif 1669 1670 #ifdef RE_TX_MODERATION 1671 intr_filter = 1; 1672 #endif 1673 /* Hook interrupt last to avoid having to lock softc */ 1674 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 && 1675 intr_filter == 0) { 1676 error = bus_setup_intr(dev, sc->rl_irq[0], 1677 INTR_TYPE_NET | INTR_MPSAFE, NULL, re_intr_msi, sc, 1678 &sc->rl_intrhand[0]); 1679 } else { 1680 error = bus_setup_intr(dev, sc->rl_irq[0], 1681 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1682 &sc->rl_intrhand[0]); 1683 } 1684 if (error) { 1685 device_printf(dev, "couldn't set up irq\n"); 1686 ether_ifdetach(ifp); 1687 } 1688 1689 fail: 1690 1691 if (error) 1692 re_detach(dev); 1693 1694 return (error); 1695 } 1696 1697 /* 1698 * Shutdown hardware and free up resources. This can be called any 1699 * time after the mutex has been initialized. It is called in both 1700 * the error case in attach and the normal detach case so it needs 1701 * to be careful about only freeing resources that have actually been 1702 * allocated. 1703 */ 1704 static int 1705 re_detach(device_t dev) 1706 { 1707 struct rl_softc *sc; 1708 struct ifnet *ifp; 1709 int i, rid; 1710 1711 sc = device_get_softc(dev); 1712 ifp = sc->rl_ifp; 1713 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1714 1715 /* These should only be active if attach succeeded */ 1716 if (device_is_attached(dev)) { 1717 #ifdef DEVICE_POLLING 1718 if (ifp->if_capenable & IFCAP_POLLING) 1719 ether_poll_deregister(ifp); 1720 #endif 1721 RL_LOCK(sc); 1722 #if 0 1723 sc->suspended = 1; 1724 #endif 1725 re_stop(sc); 1726 RL_UNLOCK(sc); 1727 callout_drain(&sc->rl_stat_callout); 1728 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1729 /* 1730 * Force off the IFF_UP flag here, in case someone 1731 * still had a BPF descriptor attached to this 1732 * interface. If they do, ether_ifdetach() will cause 1733 * the BPF code to try and clear the promisc mode 1734 * flag, which will bubble down to re_ioctl(), 1735 * which will try to call re_init() again. This will 1736 * turn the NIC back on and restart the MII ticker, 1737 * which will panic the system when the kernel tries 1738 * to invoke the re_tick() function that isn't there 1739 * anymore. 1740 */ 1741 ifp->if_flags &= ~IFF_UP; 1742 ether_ifdetach(ifp); 1743 } 1744 if (sc->rl_miibus) 1745 device_delete_child(dev, sc->rl_miibus); 1746 bus_generic_detach(dev); 1747 1748 /* 1749 * The rest is resource deallocation, so we should already be 1750 * stopped here. 1751 */ 1752 1753 if (sc->rl_intrhand[0] != NULL) { 1754 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]); 1755 sc->rl_intrhand[0] = NULL; 1756 } 1757 if (ifp != NULL) { 1758 #ifdef DEV_NETMAP 1759 netmap_detach(ifp); 1760 #endif /* DEV_NETMAP */ 1761 if_free(ifp); 1762 } 1763 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) 1764 rid = 0; 1765 else 1766 rid = 1; 1767 if (sc->rl_irq[0] != NULL) { 1768 bus_release_resource(dev, SYS_RES_IRQ, rid, sc->rl_irq[0]); 1769 sc->rl_irq[0] = NULL; 1770 } 1771 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0) 1772 pci_release_msi(dev); 1773 if (sc->rl_res_pba) { 1774 rid = PCIR_BAR(4); 1775 bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->rl_res_pba); 1776 } 1777 if (sc->rl_res) 1778 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, 1779 sc->rl_res); 1780 1781 /* Unload and free the RX DMA ring memory and map */ 1782 1783 if (sc->rl_ldata.rl_rx_list_tag) { 1784 if (sc->rl_ldata.rl_rx_list_map) 1785 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1786 sc->rl_ldata.rl_rx_list_map); 1787 if (sc->rl_ldata.rl_rx_list_map && sc->rl_ldata.rl_rx_list) 1788 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1789 sc->rl_ldata.rl_rx_list, 1790 sc->rl_ldata.rl_rx_list_map); 1791 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1792 } 1793 1794 /* Unload and free the TX DMA ring memory and map */ 1795 1796 if (sc->rl_ldata.rl_tx_list_tag) { 1797 if (sc->rl_ldata.rl_tx_list_map) 1798 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1799 sc->rl_ldata.rl_tx_list_map); 1800 if (sc->rl_ldata.rl_tx_list_map && sc->rl_ldata.rl_tx_list) 1801 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1802 sc->rl_ldata.rl_tx_list, 1803 sc->rl_ldata.rl_tx_list_map); 1804 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1805 } 1806 1807 /* Destroy all the RX and TX buffer maps */ 1808 1809 if (sc->rl_ldata.rl_tx_mtag) { 1810 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1811 if (sc->rl_ldata.rl_tx_desc[i].tx_dmamap) 1812 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1813 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1814 } 1815 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1816 } 1817 if (sc->rl_ldata.rl_rx_mtag) { 1818 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1819 if (sc->rl_ldata.rl_rx_desc[i].rx_dmamap) 1820 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1821 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1822 } 1823 if (sc->rl_ldata.rl_rx_sparemap) 1824 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1825 sc->rl_ldata.rl_rx_sparemap); 1826 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1827 } 1828 if (sc->rl_ldata.rl_jrx_mtag) { 1829 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1830 if (sc->rl_ldata.rl_jrx_desc[i].rx_dmamap) 1831 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag, 1832 sc->rl_ldata.rl_jrx_desc[i].rx_dmamap); 1833 } 1834 if (sc->rl_ldata.rl_jrx_sparemap) 1835 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag, 1836 sc->rl_ldata.rl_jrx_sparemap); 1837 bus_dma_tag_destroy(sc->rl_ldata.rl_jrx_mtag); 1838 } 1839 /* Unload and free the stats buffer and map */ 1840 1841 if (sc->rl_ldata.rl_stag) { 1842 if (sc->rl_ldata.rl_smap) 1843 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1844 sc->rl_ldata.rl_smap); 1845 if (sc->rl_ldata.rl_smap && sc->rl_ldata.rl_stats) 1846 bus_dmamem_free(sc->rl_ldata.rl_stag, 1847 sc->rl_ldata.rl_stats, sc->rl_ldata.rl_smap); 1848 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1849 } 1850 1851 if (sc->rl_parent_tag) 1852 bus_dma_tag_destroy(sc->rl_parent_tag); 1853 1854 mtx_destroy(&sc->rl_mtx); 1855 1856 return (0); 1857 } 1858 1859 static __inline void 1860 re_discard_rxbuf(struct rl_softc *sc, int idx) 1861 { 1862 struct rl_desc *desc; 1863 struct rl_rxdesc *rxd; 1864 uint32_t cmdstat; 1865 1866 if (sc->rl_ifp->if_mtu > RL_MTU && 1867 (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) 1868 rxd = &sc->rl_ldata.rl_jrx_desc[idx]; 1869 else 1870 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1871 desc = &sc->rl_ldata.rl_rx_list[idx]; 1872 desc->rl_vlanctl = 0; 1873 cmdstat = rxd->rx_size; 1874 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1875 cmdstat |= RL_RDESC_CMD_EOR; 1876 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1877 } 1878 1879 static int 1880 re_newbuf(struct rl_softc *sc, int idx) 1881 { 1882 struct mbuf *m; 1883 struct rl_rxdesc *rxd; 1884 bus_dma_segment_t segs[1]; 1885 bus_dmamap_t map; 1886 struct rl_desc *desc; 1887 uint32_t cmdstat; 1888 int error, nsegs; 1889 1890 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1891 if (m == NULL) 1892 return (ENOBUFS); 1893 1894 m->m_len = m->m_pkthdr.len = MCLBYTES; 1895 #ifdef RE_FIXUP_RX 1896 /* 1897 * This is part of an evil trick to deal with non-x86 platforms. 1898 * The RealTek chip requires RX buffers to be aligned on 64-bit 1899 * boundaries, but that will hose non-x86 machines. To get around 1900 * this, we leave some empty space at the start of each buffer 1901 * and for non-x86 hosts, we copy the buffer back six bytes 1902 * to achieve word alignment. This is slightly more efficient 1903 * than allocating a new buffer, copying the contents, and 1904 * discarding the old buffer. 1905 */ 1906 m_adj(m, RE_ETHER_ALIGN); 1907 #endif 1908 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1909 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1910 if (error != 0) { 1911 m_freem(m); 1912 return (ENOBUFS); 1913 } 1914 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1915 1916 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1917 if (rxd->rx_m != NULL) { 1918 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1919 BUS_DMASYNC_POSTREAD); 1920 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1921 } 1922 1923 rxd->rx_m = m; 1924 map = rxd->rx_dmamap; 1925 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1926 rxd->rx_size = segs[0].ds_len; 1927 sc->rl_ldata.rl_rx_sparemap = map; 1928 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1929 BUS_DMASYNC_PREREAD); 1930 1931 desc = &sc->rl_ldata.rl_rx_list[idx]; 1932 desc->rl_vlanctl = 0; 1933 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1934 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1935 cmdstat = segs[0].ds_len; 1936 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1937 cmdstat |= RL_RDESC_CMD_EOR; 1938 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1939 1940 return (0); 1941 } 1942 1943 static int 1944 re_jumbo_newbuf(struct rl_softc *sc, int idx) 1945 { 1946 struct mbuf *m; 1947 struct rl_rxdesc *rxd; 1948 bus_dma_segment_t segs[1]; 1949 bus_dmamap_t map; 1950 struct rl_desc *desc; 1951 uint32_t cmdstat; 1952 int error, nsegs; 1953 1954 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 1955 if (m == NULL) 1956 return (ENOBUFS); 1957 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1958 #ifdef RE_FIXUP_RX 1959 m_adj(m, RE_ETHER_ALIGN); 1960 #endif 1961 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_jrx_mtag, 1962 sc->rl_ldata.rl_jrx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1963 if (error != 0) { 1964 m_freem(m); 1965 return (ENOBUFS); 1966 } 1967 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1968 1969 rxd = &sc->rl_ldata.rl_jrx_desc[idx]; 1970 if (rxd->rx_m != NULL) { 1971 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap, 1972 BUS_DMASYNC_POSTREAD); 1973 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap); 1974 } 1975 1976 rxd->rx_m = m; 1977 map = rxd->rx_dmamap; 1978 rxd->rx_dmamap = sc->rl_ldata.rl_jrx_sparemap; 1979 rxd->rx_size = segs[0].ds_len; 1980 sc->rl_ldata.rl_jrx_sparemap = map; 1981 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap, 1982 BUS_DMASYNC_PREREAD); 1983 1984 desc = &sc->rl_ldata.rl_rx_list[idx]; 1985 desc->rl_vlanctl = 0; 1986 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1987 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1988 cmdstat = segs[0].ds_len; 1989 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1990 cmdstat |= RL_RDESC_CMD_EOR; 1991 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1992 1993 return (0); 1994 } 1995 1996 #ifdef RE_FIXUP_RX 1997 static __inline void 1998 re_fixup_rx(struct mbuf *m) 1999 { 2000 int i; 2001 uint16_t *src, *dst; 2002 2003 src = mtod(m, uint16_t *); 2004 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 2005 2006 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 2007 *dst++ = *src++; 2008 2009 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 2010 } 2011 #endif 2012 2013 static int 2014 re_tx_list_init(struct rl_softc *sc) 2015 { 2016 struct rl_desc *desc; 2017 int i; 2018 2019 RL_LOCK_ASSERT(sc); 2020 2021 bzero(sc->rl_ldata.rl_tx_list, 2022 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 2023 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 2024 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 2025 #ifdef DEV_NETMAP 2026 re_netmap_tx_init(sc); 2027 #endif /* DEV_NETMAP */ 2028 /* Set EOR. */ 2029 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 2030 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 2031 2032 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2033 sc->rl_ldata.rl_tx_list_map, 2034 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2035 2036 sc->rl_ldata.rl_tx_prodidx = 0; 2037 sc->rl_ldata.rl_tx_considx = 0; 2038 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 2039 2040 return (0); 2041 } 2042 2043 static int 2044 re_rx_list_init(struct rl_softc *sc) 2045 { 2046 int error, i; 2047 2048 bzero(sc->rl_ldata.rl_rx_list, 2049 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 2050 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2051 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 2052 if ((error = re_newbuf(sc, i)) != 0) 2053 return (error); 2054 } 2055 #ifdef DEV_NETMAP 2056 re_netmap_rx_init(sc); 2057 #endif /* DEV_NETMAP */ 2058 2059 /* Flush the RX descriptors */ 2060 2061 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2062 sc->rl_ldata.rl_rx_list_map, 2063 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2064 2065 sc->rl_ldata.rl_rx_prodidx = 0; 2066 sc->rl_head = sc->rl_tail = NULL; 2067 sc->rl_int_rx_act = 0; 2068 2069 return (0); 2070 } 2071 2072 static int 2073 re_jrx_list_init(struct rl_softc *sc) 2074 { 2075 int error, i; 2076 2077 bzero(sc->rl_ldata.rl_rx_list, 2078 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 2079 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2080 sc->rl_ldata.rl_jrx_desc[i].rx_m = NULL; 2081 if ((error = re_jumbo_newbuf(sc, i)) != 0) 2082 return (error); 2083 } 2084 2085 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2086 sc->rl_ldata.rl_rx_list_map, 2087 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2088 2089 sc->rl_ldata.rl_rx_prodidx = 0; 2090 sc->rl_head = sc->rl_tail = NULL; 2091 sc->rl_int_rx_act = 0; 2092 2093 return (0); 2094 } 2095 2096 /* 2097 * RX handler for C+ and 8169. For the gigE chips, we support 2098 * the reception of jumbo frames that have been fragmented 2099 * across multiple 2K mbuf cluster buffers. 2100 */ 2101 static int 2102 re_rxeof(struct rl_softc *sc, int *rx_npktsp) 2103 { 2104 struct mbuf *m; 2105 struct ifnet *ifp; 2106 int i, rxerr, total_len; 2107 struct rl_desc *cur_rx; 2108 u_int32_t rxstat, rxvlan; 2109 int jumbo, maxpkt = 16, rx_npkts = 0; 2110 2111 RL_LOCK_ASSERT(sc); 2112 2113 ifp = sc->rl_ifp; 2114 #ifdef DEV_NETMAP 2115 if (ifp->if_capenable & IFCAP_NETMAP) { 2116 NA(ifp)->rx_rings[0].nr_kflags |= NKR_PENDINTR; 2117 selwakeuppri(&NA(ifp)->rx_rings[0].si, PI_NET); 2118 return 0; 2119 } 2120 #endif /* DEV_NETMAP */ 2121 if (ifp->if_mtu > RL_MTU && (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) 2122 jumbo = 1; 2123 else 2124 jumbo = 0; 2125 2126 /* Invalidate the descriptor memory */ 2127 2128 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2129 sc->rl_ldata.rl_rx_list_map, 2130 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2131 2132 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 2133 i = RL_RX_DESC_NXT(sc, i)) { 2134 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2135 break; 2136 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 2137 rxstat = le32toh(cur_rx->rl_cmdstat); 2138 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 2139 break; 2140 total_len = rxstat & sc->rl_rxlenmask; 2141 rxvlan = le32toh(cur_rx->rl_vlanctl); 2142 if (jumbo != 0) 2143 m = sc->rl_ldata.rl_jrx_desc[i].rx_m; 2144 else 2145 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 2146 2147 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 2148 (rxstat & (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) != 2149 (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) { 2150 /* 2151 * RTL8168C or later controllers do not 2152 * support multi-fragment packet. 2153 */ 2154 re_discard_rxbuf(sc, i); 2155 continue; 2156 } else if ((rxstat & RL_RDESC_STAT_EOF) == 0) { 2157 if (re_newbuf(sc, i) != 0) { 2158 /* 2159 * If this is part of a multi-fragment packet, 2160 * discard all the pieces. 2161 */ 2162 if (sc->rl_head != NULL) { 2163 m_freem(sc->rl_head); 2164 sc->rl_head = sc->rl_tail = NULL; 2165 } 2166 re_discard_rxbuf(sc, i); 2167 continue; 2168 } 2169 m->m_len = RE_RX_DESC_BUFLEN; 2170 if (sc->rl_head == NULL) 2171 sc->rl_head = sc->rl_tail = m; 2172 else { 2173 m->m_flags &= ~M_PKTHDR; 2174 sc->rl_tail->m_next = m; 2175 sc->rl_tail = m; 2176 } 2177 continue; 2178 } 2179 2180 /* 2181 * NOTE: for the 8139C+, the frame length field 2182 * is always 12 bits in size, but for the gigE chips, 2183 * it is 13 bits (since the max RX frame length is 16K). 2184 * Unfortunately, all 32 bits in the status word 2185 * were already used, so to make room for the extra 2186 * length bit, RealTek took out the 'frame alignment 2187 * error' bit and shifted the other status bits 2188 * over one slot. The OWN, EOR, FS and LS bits are 2189 * still in the same places. We have already extracted 2190 * the frame length and checked the OWN bit, so rather 2191 * than using an alternate bit mapping, we shift the 2192 * status bits one space to the right so we can evaluate 2193 * them using the 8169 status as though it was in the 2194 * same format as that of the 8139C+. 2195 */ 2196 if (sc->rl_type == RL_8169) 2197 rxstat >>= 1; 2198 2199 /* 2200 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 2201 * set, but if CRC is clear, it will still be a valid frame. 2202 */ 2203 if ((rxstat & RL_RDESC_STAT_RXERRSUM) != 0) { 2204 rxerr = 1; 2205 if ((sc->rl_flags & RL_FLAG_JUMBOV2) == 0 && 2206 total_len > 8191 && 2207 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT) 2208 rxerr = 0; 2209 if (rxerr != 0) { 2210 ifp->if_ierrors++; 2211 /* 2212 * If this is part of a multi-fragment packet, 2213 * discard all the pieces. 2214 */ 2215 if (sc->rl_head != NULL) { 2216 m_freem(sc->rl_head); 2217 sc->rl_head = sc->rl_tail = NULL; 2218 } 2219 re_discard_rxbuf(sc, i); 2220 continue; 2221 } 2222 } 2223 2224 /* 2225 * If allocating a replacement mbuf fails, 2226 * reload the current one. 2227 */ 2228 if (jumbo != 0) 2229 rxerr = re_jumbo_newbuf(sc, i); 2230 else 2231 rxerr = re_newbuf(sc, i); 2232 if (rxerr != 0) { 2233 ifp->if_iqdrops++; 2234 if (sc->rl_head != NULL) { 2235 m_freem(sc->rl_head); 2236 sc->rl_head = sc->rl_tail = NULL; 2237 } 2238 re_discard_rxbuf(sc, i); 2239 continue; 2240 } 2241 2242 if (sc->rl_head != NULL) { 2243 if (jumbo != 0) 2244 m->m_len = total_len; 2245 else { 2246 m->m_len = total_len % RE_RX_DESC_BUFLEN; 2247 if (m->m_len == 0) 2248 m->m_len = RE_RX_DESC_BUFLEN; 2249 } 2250 /* 2251 * Special case: if there's 4 bytes or less 2252 * in this buffer, the mbuf can be discarded: 2253 * the last 4 bytes is the CRC, which we don't 2254 * care about anyway. 2255 */ 2256 if (m->m_len <= ETHER_CRC_LEN) { 2257 sc->rl_tail->m_len -= 2258 (ETHER_CRC_LEN - m->m_len); 2259 m_freem(m); 2260 } else { 2261 m->m_len -= ETHER_CRC_LEN; 2262 m->m_flags &= ~M_PKTHDR; 2263 sc->rl_tail->m_next = m; 2264 } 2265 m = sc->rl_head; 2266 sc->rl_head = sc->rl_tail = NULL; 2267 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 2268 } else 2269 m->m_pkthdr.len = m->m_len = 2270 (total_len - ETHER_CRC_LEN); 2271 2272 #ifdef RE_FIXUP_RX 2273 re_fixup_rx(m); 2274 #endif 2275 ifp->if_ipackets++; 2276 m->m_pkthdr.rcvif = ifp; 2277 2278 /* Do RX checksumming if enabled */ 2279 2280 if (ifp->if_capenable & IFCAP_RXCSUM) { 2281 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2282 /* Check IP header checksum */ 2283 if (rxstat & RL_RDESC_STAT_PROTOID) 2284 m->m_pkthdr.csum_flags |= 2285 CSUM_IP_CHECKED; 2286 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 2287 m->m_pkthdr.csum_flags |= 2288 CSUM_IP_VALID; 2289 2290 /* Check TCP/UDP checksum */ 2291 if ((RL_TCPPKT(rxstat) && 2292 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 2293 (RL_UDPPKT(rxstat) && 2294 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 2295 m->m_pkthdr.csum_flags |= 2296 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2297 m->m_pkthdr.csum_data = 0xffff; 2298 } 2299 } else { 2300 /* 2301 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP 2302 */ 2303 if ((rxstat & RL_RDESC_STAT_PROTOID) && 2304 (rxvlan & RL_RDESC_IPV4)) 2305 m->m_pkthdr.csum_flags |= 2306 CSUM_IP_CHECKED; 2307 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) && 2308 (rxvlan & RL_RDESC_IPV4)) 2309 m->m_pkthdr.csum_flags |= 2310 CSUM_IP_VALID; 2311 if (((rxstat & RL_RDESC_STAT_TCP) && 2312 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 2313 ((rxstat & RL_RDESC_STAT_UDP) && 2314 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 2315 m->m_pkthdr.csum_flags |= 2316 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2317 m->m_pkthdr.csum_data = 0xffff; 2318 } 2319 } 2320 } 2321 maxpkt--; 2322 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 2323 m->m_pkthdr.ether_vtag = 2324 bswap16((rxvlan & RL_RDESC_VLANCTL_DATA)); 2325 m->m_flags |= M_VLANTAG; 2326 } 2327 RL_UNLOCK(sc); 2328 (*ifp->if_input)(ifp, m); 2329 RL_LOCK(sc); 2330 rx_npkts++; 2331 } 2332 2333 /* Flush the RX DMA ring */ 2334 2335 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2336 sc->rl_ldata.rl_rx_list_map, 2337 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2338 2339 sc->rl_ldata.rl_rx_prodidx = i; 2340 2341 if (rx_npktsp != NULL) 2342 *rx_npktsp = rx_npkts; 2343 if (maxpkt) 2344 return (EAGAIN); 2345 2346 return (0); 2347 } 2348 2349 static void 2350 re_txeof(struct rl_softc *sc) 2351 { 2352 struct ifnet *ifp; 2353 struct rl_txdesc *txd; 2354 u_int32_t txstat; 2355 int cons; 2356 2357 cons = sc->rl_ldata.rl_tx_considx; 2358 if (cons == sc->rl_ldata.rl_tx_prodidx) 2359 return; 2360 2361 ifp = sc->rl_ifp; 2362 #ifdef DEV_NETMAP 2363 if (ifp->if_capenable & IFCAP_NETMAP) { 2364 selwakeuppri(&NA(ifp)->tx_rings[0].si, PI_NET); 2365 return; 2366 } 2367 #endif /* DEV_NETMAP */ 2368 /* Invalidate the TX descriptor list */ 2369 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2370 sc->rl_ldata.rl_tx_list_map, 2371 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2372 2373 for (; cons != sc->rl_ldata.rl_tx_prodidx; 2374 cons = RL_TX_DESC_NXT(sc, cons)) { 2375 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 2376 if (txstat & RL_TDESC_STAT_OWN) 2377 break; 2378 /* 2379 * We only stash mbufs in the last descriptor 2380 * in a fragment chain, which also happens to 2381 * be the only place where the TX status bits 2382 * are valid. 2383 */ 2384 if (txstat & RL_TDESC_CMD_EOF) { 2385 txd = &sc->rl_ldata.rl_tx_desc[cons]; 2386 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2387 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2388 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2389 txd->tx_dmamap); 2390 KASSERT(txd->tx_m != NULL, 2391 ("%s: freeing NULL mbufs!", __func__)); 2392 m_freem(txd->tx_m); 2393 txd->tx_m = NULL; 2394 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 2395 RL_TDESC_STAT_COLCNT)) 2396 ifp->if_collisions++; 2397 if (txstat & RL_TDESC_STAT_TXERRSUM) 2398 ifp->if_oerrors++; 2399 else 2400 ifp->if_opackets++; 2401 } 2402 sc->rl_ldata.rl_tx_free++; 2403 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2404 } 2405 sc->rl_ldata.rl_tx_considx = cons; 2406 2407 /* No changes made to the TX ring, so no flush needed */ 2408 2409 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 2410 #ifdef RE_TX_MODERATION 2411 /* 2412 * If not all descriptors have been reaped yet, reload 2413 * the timer so that we will eventually get another 2414 * interrupt that will cause us to re-enter this routine. 2415 * This is done in case the transmitter has gone idle. 2416 */ 2417 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2418 #endif 2419 } else 2420 sc->rl_watchdog_timer = 0; 2421 } 2422 2423 static void 2424 re_tick(void *xsc) 2425 { 2426 struct rl_softc *sc; 2427 struct mii_data *mii; 2428 2429 sc = xsc; 2430 2431 RL_LOCK_ASSERT(sc); 2432 2433 mii = device_get_softc(sc->rl_miibus); 2434 mii_tick(mii); 2435 if ((sc->rl_flags & RL_FLAG_LINK) == 0) 2436 re_miibus_statchg(sc->rl_dev); 2437 /* 2438 * Reclaim transmitted frames here. Technically it is not 2439 * necessary to do here but it ensures periodic reclamation 2440 * regardless of Tx completion interrupt which seems to be 2441 * lost on PCIe based controllers under certain situations. 2442 */ 2443 re_txeof(sc); 2444 re_watchdog(sc); 2445 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2446 } 2447 2448 #ifdef DEVICE_POLLING 2449 static int 2450 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2451 { 2452 struct rl_softc *sc = ifp->if_softc; 2453 int rx_npkts = 0; 2454 2455 RL_LOCK(sc); 2456 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2457 rx_npkts = re_poll_locked(ifp, cmd, count); 2458 RL_UNLOCK(sc); 2459 return (rx_npkts); 2460 } 2461 2462 static int 2463 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2464 { 2465 struct rl_softc *sc = ifp->if_softc; 2466 int rx_npkts; 2467 2468 RL_LOCK_ASSERT(sc); 2469 2470 sc->rxcycles = count; 2471 re_rxeof(sc, &rx_npkts); 2472 re_txeof(sc); 2473 2474 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2475 re_start_locked(ifp); 2476 2477 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2478 u_int16_t status; 2479 2480 status = CSR_READ_2(sc, RL_ISR); 2481 if (status == 0xffff) 2482 return (rx_npkts); 2483 if (status) 2484 CSR_WRITE_2(sc, RL_ISR, status); 2485 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2486 (sc->rl_flags & RL_FLAG_PCIE)) 2487 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2488 2489 /* 2490 * XXX check behaviour on receiver stalls. 2491 */ 2492 2493 if (status & RL_ISR_SYSTEM_ERR) { 2494 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2495 re_init_locked(sc); 2496 } 2497 } 2498 return (rx_npkts); 2499 } 2500 #endif /* DEVICE_POLLING */ 2501 2502 static int 2503 re_intr(void *arg) 2504 { 2505 struct rl_softc *sc; 2506 uint16_t status; 2507 2508 sc = arg; 2509 2510 status = CSR_READ_2(sc, RL_ISR); 2511 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2512 return (FILTER_STRAY); 2513 CSR_WRITE_2(sc, RL_IMR, 0); 2514 2515 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2516 2517 return (FILTER_HANDLED); 2518 } 2519 2520 static void 2521 re_int_task(void *arg, int npending) 2522 { 2523 struct rl_softc *sc; 2524 struct ifnet *ifp; 2525 u_int16_t status; 2526 int rval = 0; 2527 2528 sc = arg; 2529 ifp = sc->rl_ifp; 2530 2531 RL_LOCK(sc); 2532 2533 status = CSR_READ_2(sc, RL_ISR); 2534 CSR_WRITE_2(sc, RL_ISR, status); 2535 2536 if (sc->suspended || 2537 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2538 RL_UNLOCK(sc); 2539 return; 2540 } 2541 2542 #ifdef DEVICE_POLLING 2543 if (ifp->if_capenable & IFCAP_POLLING) { 2544 RL_UNLOCK(sc); 2545 return; 2546 } 2547 #endif 2548 2549 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2550 rval = re_rxeof(sc, NULL); 2551 2552 /* 2553 * Some chips will ignore a second TX request issued 2554 * while an existing transmission is in progress. If 2555 * the transmitter goes idle but there are still 2556 * packets waiting to be sent, we need to restart the 2557 * channel here to flush them out. This only seems to 2558 * be required with the PCIe devices. 2559 */ 2560 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2561 (sc->rl_flags & RL_FLAG_PCIE)) 2562 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2563 if (status & ( 2564 #ifdef RE_TX_MODERATION 2565 RL_ISR_TIMEOUT_EXPIRED| 2566 #else 2567 RL_ISR_TX_OK| 2568 #endif 2569 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2570 re_txeof(sc); 2571 2572 if (status & RL_ISR_SYSTEM_ERR) { 2573 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2574 re_init_locked(sc); 2575 } 2576 2577 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2578 re_start_locked(ifp); 2579 2580 RL_UNLOCK(sc); 2581 2582 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2583 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2584 return; 2585 } 2586 2587 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2588 } 2589 2590 static void 2591 re_intr_msi(void *xsc) 2592 { 2593 struct rl_softc *sc; 2594 struct ifnet *ifp; 2595 uint16_t intrs, status; 2596 2597 sc = xsc; 2598 RL_LOCK(sc); 2599 2600 ifp = sc->rl_ifp; 2601 #ifdef DEVICE_POLLING 2602 if (ifp->if_capenable & IFCAP_POLLING) { 2603 RL_UNLOCK(sc); 2604 return; 2605 } 2606 #endif 2607 /* Disable interrupts. */ 2608 CSR_WRITE_2(sc, RL_IMR, 0); 2609 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2610 RL_UNLOCK(sc); 2611 return; 2612 } 2613 2614 intrs = RL_INTRS_CPLUS; 2615 status = CSR_READ_2(sc, RL_ISR); 2616 CSR_WRITE_2(sc, RL_ISR, status); 2617 if (sc->rl_int_rx_act > 0) { 2618 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW | 2619 RL_ISR_RX_OVERRUN); 2620 status &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW | 2621 RL_ISR_RX_OVERRUN); 2622 } 2623 2624 if (status & (RL_ISR_TIMEOUT_EXPIRED | RL_ISR_RX_OK | RL_ISR_RX_ERR | 2625 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) { 2626 re_rxeof(sc, NULL); 2627 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2628 if (sc->rl_int_rx_mod != 0 && 2629 (status & (RL_ISR_RX_OK | RL_ISR_RX_ERR | 2630 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) != 0) { 2631 /* Rearm one-shot timer. */ 2632 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2633 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | 2634 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN); 2635 sc->rl_int_rx_act = 1; 2636 } else { 2637 intrs |= RL_ISR_RX_OK | RL_ISR_RX_ERR | 2638 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN; 2639 sc->rl_int_rx_act = 0; 2640 } 2641 } 2642 } 2643 2644 /* 2645 * Some chips will ignore a second TX request issued 2646 * while an existing transmission is in progress. If 2647 * the transmitter goes idle but there are still 2648 * packets waiting to be sent, we need to restart the 2649 * channel here to flush them out. This only seems to 2650 * be required with the PCIe devices. 2651 */ 2652 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2653 (sc->rl_flags & RL_FLAG_PCIE)) 2654 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2655 if (status & (RL_ISR_TX_OK | RL_ISR_TX_ERR | RL_ISR_TX_DESC_UNAVAIL)) 2656 re_txeof(sc); 2657 2658 if (status & RL_ISR_SYSTEM_ERR) { 2659 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2660 re_init_locked(sc); 2661 } 2662 2663 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2664 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2665 re_start_locked(ifp); 2666 CSR_WRITE_2(sc, RL_IMR, intrs); 2667 } 2668 RL_UNLOCK(sc); 2669 } 2670 2671 static int 2672 re_encap(struct rl_softc *sc, struct mbuf **m_head) 2673 { 2674 struct rl_txdesc *txd, *txd_last; 2675 bus_dma_segment_t segs[RL_NTXSEGS]; 2676 bus_dmamap_t map; 2677 struct mbuf *m_new; 2678 struct rl_desc *desc; 2679 int nsegs, prod; 2680 int i, error, ei, si; 2681 int padlen; 2682 uint32_t cmdstat, csum_flags, vlanctl; 2683 2684 RL_LOCK_ASSERT(sc); 2685 M_ASSERTPKTHDR((*m_head)); 2686 2687 /* 2688 * With some of the RealTek chips, using the checksum offload 2689 * support in conjunction with the autopadding feature results 2690 * in the transmission of corrupt frames. For example, if we 2691 * need to send a really small IP fragment that's less than 60 2692 * bytes in size, and IP header checksumming is enabled, the 2693 * resulting ethernet frame that appears on the wire will 2694 * have garbled payload. To work around this, if TX IP checksum 2695 * offload is enabled, we always manually pad short frames out 2696 * to the minimum ethernet frame size. 2697 */ 2698 if ((sc->rl_flags & RL_FLAG_AUTOPAD) == 0 && 2699 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN && 2700 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) { 2701 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2702 if (M_WRITABLE(*m_head) == 0) { 2703 /* Get a writable copy. */ 2704 m_new = m_dup(*m_head, M_NOWAIT); 2705 m_freem(*m_head); 2706 if (m_new == NULL) { 2707 *m_head = NULL; 2708 return (ENOBUFS); 2709 } 2710 *m_head = m_new; 2711 } 2712 if ((*m_head)->m_next != NULL || 2713 M_TRAILINGSPACE(*m_head) < padlen) { 2714 m_new = m_defrag(*m_head, M_NOWAIT); 2715 if (m_new == NULL) { 2716 m_freem(*m_head); 2717 *m_head = NULL; 2718 return (ENOBUFS); 2719 } 2720 } else 2721 m_new = *m_head; 2722 2723 /* 2724 * Manually pad short frames, and zero the pad space 2725 * to avoid leaking data. 2726 */ 2727 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2728 m_new->m_pkthdr.len += padlen; 2729 m_new->m_len = m_new->m_pkthdr.len; 2730 *m_head = m_new; 2731 } 2732 2733 prod = sc->rl_ldata.rl_tx_prodidx; 2734 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2735 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2736 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2737 if (error == EFBIG) { 2738 m_new = m_collapse(*m_head, M_NOWAIT, RL_NTXSEGS); 2739 if (m_new == NULL) { 2740 m_freem(*m_head); 2741 *m_head = NULL; 2742 return (ENOBUFS); 2743 } 2744 *m_head = m_new; 2745 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2746 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2747 if (error != 0) { 2748 m_freem(*m_head); 2749 *m_head = NULL; 2750 return (error); 2751 } 2752 } else if (error != 0) 2753 return (error); 2754 if (nsegs == 0) { 2755 m_freem(*m_head); 2756 *m_head = NULL; 2757 return (EIO); 2758 } 2759 2760 /* Check for number of available descriptors. */ 2761 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2762 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2763 return (ENOBUFS); 2764 } 2765 2766 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2767 BUS_DMASYNC_PREWRITE); 2768 2769 /* 2770 * Set up checksum offload. Note: checksum offload bits must 2771 * appear in all descriptors of a multi-descriptor transmit 2772 * attempt. This is according to testing done with an 8169 2773 * chip. This is a requirement. 2774 */ 2775 vlanctl = 0; 2776 csum_flags = 0; 2777 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2778 if ((sc->rl_flags & RL_FLAG_DESCV2) != 0) { 2779 csum_flags |= RL_TDESC_CMD_LGSEND; 2780 vlanctl |= ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2781 RL_TDESC_CMD_MSSVALV2_SHIFT); 2782 } else { 2783 csum_flags |= RL_TDESC_CMD_LGSEND | 2784 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2785 RL_TDESC_CMD_MSSVAL_SHIFT); 2786 } 2787 } else { 2788 /* 2789 * Unconditionally enable IP checksum if TCP or UDP 2790 * checksum is required. Otherwise, TCP/UDP checksum 2791 * does't make effects. 2792 */ 2793 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) { 2794 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2795 csum_flags |= RL_TDESC_CMD_IPCSUM; 2796 if (((*m_head)->m_pkthdr.csum_flags & 2797 CSUM_TCP) != 0) 2798 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2799 if (((*m_head)->m_pkthdr.csum_flags & 2800 CSUM_UDP) != 0) 2801 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2802 } else { 2803 vlanctl |= RL_TDESC_CMD_IPCSUMV2; 2804 if (((*m_head)->m_pkthdr.csum_flags & 2805 CSUM_TCP) != 0) 2806 vlanctl |= RL_TDESC_CMD_TCPCSUMV2; 2807 if (((*m_head)->m_pkthdr.csum_flags & 2808 CSUM_UDP) != 0) 2809 vlanctl |= RL_TDESC_CMD_UDPCSUMV2; 2810 } 2811 } 2812 } 2813 2814 /* 2815 * Set up hardware VLAN tagging. Note: vlan tag info must 2816 * appear in all descriptors of a multi-descriptor 2817 * transmission attempt. 2818 */ 2819 if ((*m_head)->m_flags & M_VLANTAG) 2820 vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) | 2821 RL_TDESC_VLANCTL_TAG; 2822 2823 si = prod; 2824 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2825 desc = &sc->rl_ldata.rl_tx_list[prod]; 2826 desc->rl_vlanctl = htole32(vlanctl); 2827 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2828 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2829 cmdstat = segs[i].ds_len; 2830 if (i != 0) 2831 cmdstat |= RL_TDESC_CMD_OWN; 2832 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2833 cmdstat |= RL_TDESC_CMD_EOR; 2834 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2835 sc->rl_ldata.rl_tx_free--; 2836 } 2837 /* Update producer index. */ 2838 sc->rl_ldata.rl_tx_prodidx = prod; 2839 2840 /* Set EOF on the last descriptor. */ 2841 ei = RL_TX_DESC_PRV(sc, prod); 2842 desc = &sc->rl_ldata.rl_tx_list[ei]; 2843 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2844 2845 desc = &sc->rl_ldata.rl_tx_list[si]; 2846 /* Set SOF and transfer ownership of packet to the chip. */ 2847 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2848 2849 /* 2850 * Insure that the map for this transmission 2851 * is placed at the array index of the last descriptor 2852 * in this chain. (Swap last and first dmamaps.) 2853 */ 2854 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2855 map = txd->tx_dmamap; 2856 txd->tx_dmamap = txd_last->tx_dmamap; 2857 txd_last->tx_dmamap = map; 2858 txd_last->tx_m = *m_head; 2859 2860 return (0); 2861 } 2862 2863 static void 2864 re_start(struct ifnet *ifp) 2865 { 2866 struct rl_softc *sc; 2867 2868 sc = ifp->if_softc; 2869 RL_LOCK(sc); 2870 re_start_locked(ifp); 2871 RL_UNLOCK(sc); 2872 } 2873 2874 /* 2875 * Main transmit routine for C+ and gigE NICs. 2876 */ 2877 static void 2878 re_start_locked(struct ifnet *ifp) 2879 { 2880 struct rl_softc *sc; 2881 struct mbuf *m_head; 2882 int queued; 2883 2884 sc = ifp->if_softc; 2885 2886 #ifdef DEV_NETMAP 2887 /* XXX is this necessary ? */ 2888 if (ifp->if_capenable & IFCAP_NETMAP) { 2889 struct netmap_kring *kring = &NA(ifp)->tx_rings[0]; 2890 if (sc->rl_ldata.rl_tx_prodidx != kring->nr_hwcur) { 2891 /* kick the tx unit */ 2892 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2893 #ifdef RE_TX_MODERATION 2894 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2895 #endif 2896 sc->rl_watchdog_timer = 5; 2897 } 2898 return; 2899 } 2900 #endif /* DEV_NETMAP */ 2901 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2902 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) 2903 return; 2904 2905 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2906 sc->rl_ldata.rl_tx_free > 1;) { 2907 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2908 if (m_head == NULL) 2909 break; 2910 2911 if (re_encap(sc, &m_head) != 0) { 2912 if (m_head == NULL) 2913 break; 2914 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2915 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2916 break; 2917 } 2918 2919 /* 2920 * If there's a BPF listener, bounce a copy of this frame 2921 * to him. 2922 */ 2923 ETHER_BPF_MTAP(ifp, m_head); 2924 2925 queued++; 2926 } 2927 2928 if (queued == 0) { 2929 #ifdef RE_TX_MODERATION 2930 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2931 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2932 #endif 2933 return; 2934 } 2935 2936 /* Flush the TX descriptors */ 2937 2938 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2939 sc->rl_ldata.rl_tx_list_map, 2940 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2941 2942 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2943 2944 #ifdef RE_TX_MODERATION 2945 /* 2946 * Use the countdown timer for interrupt moderation. 2947 * 'TX done' interrupts are disabled. Instead, we reset the 2948 * countdown timer, which will begin counting until it hits 2949 * the value in the TIMERINT register, and then trigger an 2950 * interrupt. Each time we write to the TIMERCNT register, 2951 * the timer count is reset to 0. 2952 */ 2953 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2954 #endif 2955 2956 /* 2957 * Set a timeout in case the chip goes out to lunch. 2958 */ 2959 sc->rl_watchdog_timer = 5; 2960 } 2961 2962 static void 2963 re_set_jumbo(struct rl_softc *sc, int jumbo) 2964 { 2965 2966 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168E_VL) { 2967 pci_set_max_read_req(sc->rl_dev, 4096); 2968 return; 2969 } 2970 2971 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2972 if (jumbo != 0) { 2973 CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) | 2974 RL_CFG3_JUMBO_EN0); 2975 switch (sc->rl_hwrev->rl_rev) { 2976 case RL_HWREV_8168DP: 2977 break; 2978 case RL_HWREV_8168E: 2979 CSR_WRITE_1(sc, sc->rl_cfg4, 2980 CSR_READ_1(sc, sc->rl_cfg4) | 0x01); 2981 break; 2982 default: 2983 CSR_WRITE_1(sc, sc->rl_cfg4, 2984 CSR_READ_1(sc, sc->rl_cfg4) | RL_CFG4_JUMBO_EN1); 2985 } 2986 } else { 2987 CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) & 2988 ~RL_CFG3_JUMBO_EN0); 2989 switch (sc->rl_hwrev->rl_rev) { 2990 case RL_HWREV_8168DP: 2991 break; 2992 case RL_HWREV_8168E: 2993 CSR_WRITE_1(sc, sc->rl_cfg4, 2994 CSR_READ_1(sc, sc->rl_cfg4) & ~0x01); 2995 break; 2996 default: 2997 CSR_WRITE_1(sc, sc->rl_cfg4, 2998 CSR_READ_1(sc, sc->rl_cfg4) & ~RL_CFG4_JUMBO_EN1); 2999 } 3000 } 3001 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3002 3003 switch (sc->rl_hwrev->rl_rev) { 3004 case RL_HWREV_8168DP: 3005 pci_set_max_read_req(sc->rl_dev, 4096); 3006 break; 3007 default: 3008 if (jumbo != 0) 3009 pci_set_max_read_req(sc->rl_dev, 512); 3010 else 3011 pci_set_max_read_req(sc->rl_dev, 4096); 3012 } 3013 } 3014 3015 static void 3016 re_init(void *xsc) 3017 { 3018 struct rl_softc *sc = xsc; 3019 3020 RL_LOCK(sc); 3021 re_init_locked(sc); 3022 RL_UNLOCK(sc); 3023 } 3024 3025 static void 3026 re_init_locked(struct rl_softc *sc) 3027 { 3028 struct ifnet *ifp = sc->rl_ifp; 3029 struct mii_data *mii; 3030 uint32_t reg; 3031 uint16_t cfg; 3032 union { 3033 uint32_t align_dummy; 3034 u_char eaddr[ETHER_ADDR_LEN]; 3035 } eaddr; 3036 3037 RL_LOCK_ASSERT(sc); 3038 3039 mii = device_get_softc(sc->rl_miibus); 3040 3041 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3042 return; 3043 3044 /* 3045 * Cancel pending I/O and free all RX/TX buffers. 3046 */ 3047 re_stop(sc); 3048 3049 /* Put controller into known state. */ 3050 re_reset(sc); 3051 3052 /* 3053 * For C+ mode, initialize the RX descriptors and mbufs. 3054 */ 3055 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3056 if (ifp->if_mtu > RL_MTU) { 3057 if (re_jrx_list_init(sc) != 0) { 3058 device_printf(sc->rl_dev, 3059 "no memory for jumbo RX buffers\n"); 3060 re_stop(sc); 3061 return; 3062 } 3063 /* Disable checksum offloading for jumbo frames. */ 3064 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_TSO4); 3065 ifp->if_hwassist &= ~(RE_CSUM_FEATURES | CSUM_TSO); 3066 } else { 3067 if (re_rx_list_init(sc) != 0) { 3068 device_printf(sc->rl_dev, 3069 "no memory for RX buffers\n"); 3070 re_stop(sc); 3071 return; 3072 } 3073 } 3074 re_set_jumbo(sc, ifp->if_mtu > RL_MTU); 3075 } else { 3076 if (re_rx_list_init(sc) != 0) { 3077 device_printf(sc->rl_dev, "no memory for RX buffers\n"); 3078 re_stop(sc); 3079 return; 3080 } 3081 if ((sc->rl_flags & RL_FLAG_PCIE) != 0 && 3082 pci_get_device(sc->rl_dev) != RT_DEVICEID_8101E) { 3083 if (ifp->if_mtu > RL_MTU) 3084 pci_set_max_read_req(sc->rl_dev, 512); 3085 else 3086 pci_set_max_read_req(sc->rl_dev, 4096); 3087 } 3088 } 3089 re_tx_list_init(sc); 3090 3091 /* 3092 * Enable C+ RX and TX mode, as well as VLAN stripping and 3093 * RX checksum offload. We must configure the C+ register 3094 * before all others. 3095 */ 3096 cfg = RL_CPLUSCMD_PCI_MRW; 3097 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 3098 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 3099 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3100 cfg |= RL_CPLUSCMD_VLANSTRIP; 3101 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) { 3102 cfg |= RL_CPLUSCMD_MACSTAT_DIS; 3103 /* XXX magic. */ 3104 cfg |= 0x0001; 3105 } else 3106 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB; 3107 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg); 3108 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SC || 3109 sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) { 3110 reg = 0x000fff00; 3111 if ((CSR_READ_1(sc, sc->rl_cfg2) & RL_CFG2_PCI66MHZ) != 0) 3112 reg |= 0x000000ff; 3113 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) 3114 reg |= 0x00f00000; 3115 CSR_WRITE_4(sc, 0x7c, reg); 3116 /* Disable interrupt mitigation. */ 3117 CSR_WRITE_2(sc, 0xe2, 0); 3118 } 3119 /* 3120 * Disable TSO if interface MTU size is greater than MSS 3121 * allowed in controller. 3122 */ 3123 if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) { 3124 ifp->if_capenable &= ~IFCAP_TSO4; 3125 ifp->if_hwassist &= ~CSUM_TSO; 3126 } 3127 3128 /* 3129 * Init our MAC address. Even though the chipset 3130 * documentation doesn't mention it, we need to enter "Config 3131 * register write enable" mode to modify the ID registers. 3132 */ 3133 /* Copy MAC address on stack to align. */ 3134 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 3135 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 3136 CSR_WRITE_4(sc, RL_IDR0, 3137 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 3138 CSR_WRITE_4(sc, RL_IDR4, 3139 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 3140 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3141 3142 /* 3143 * Load the addresses of the RX and TX lists into the chip. 3144 */ 3145 3146 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 3147 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 3148 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 3149 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 3150 3151 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 3152 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 3153 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 3154 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 3155 3156 /* 3157 * Enable transmit and receive. 3158 */ 3159 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 3160 3161 /* 3162 * Set the initial TX configuration. 3163 */ 3164 if (sc->rl_testmode) { 3165 if (sc->rl_type == RL_8169) 3166 CSR_WRITE_4(sc, RL_TXCFG, 3167 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 3168 else 3169 CSR_WRITE_4(sc, RL_TXCFG, 3170 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 3171 } else 3172 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 3173 3174 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 3175 3176 /* 3177 * Set the initial RX configuration. 3178 */ 3179 re_set_rxmode(sc); 3180 3181 /* Configure interrupt moderation. */ 3182 if (sc->rl_type == RL_8169) { 3183 /* Magic from vendor. */ 3184 CSR_WRITE_2(sc, RL_INTRMOD, 0x5100); 3185 } 3186 3187 #ifdef DEVICE_POLLING 3188 /* 3189 * Disable interrupts if we are polling. 3190 */ 3191 if (ifp->if_capenable & IFCAP_POLLING) 3192 CSR_WRITE_2(sc, RL_IMR, 0); 3193 else /* otherwise ... */ 3194 #endif 3195 3196 /* 3197 * Enable interrupts. 3198 */ 3199 if (sc->rl_testmode) 3200 CSR_WRITE_2(sc, RL_IMR, 0); 3201 else 3202 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 3203 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 3204 3205 /* Set initial TX threshold */ 3206 sc->rl_txthresh = RL_TX_THRESH_INIT; 3207 3208 /* Start RX/TX process. */ 3209 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 3210 #ifdef notdef 3211 /* Enable receiver and transmitter. */ 3212 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 3213 #endif 3214 3215 /* 3216 * Initialize the timer interrupt register so that 3217 * a timer interrupt will be generated once the timer 3218 * reaches a certain number of ticks. The timer is 3219 * reloaded on each transmit. 3220 */ 3221 #ifdef RE_TX_MODERATION 3222 /* 3223 * Use timer interrupt register to moderate TX interrupt 3224 * moderation, which dramatically improves TX frame rate. 3225 */ 3226 if (sc->rl_type == RL_8169) 3227 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 3228 else 3229 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 3230 #else 3231 /* 3232 * Use timer interrupt register to moderate RX interrupt 3233 * moderation. 3234 */ 3235 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 && 3236 intr_filter == 0) { 3237 if (sc->rl_type == RL_8169) 3238 CSR_WRITE_4(sc, RL_TIMERINT_8169, 3239 RL_USECS(sc->rl_int_rx_mod)); 3240 } else { 3241 if (sc->rl_type == RL_8169) 3242 CSR_WRITE_4(sc, RL_TIMERINT_8169, RL_USECS(0)); 3243 } 3244 #endif 3245 3246 /* 3247 * For 8169 gigE NICs, set the max allowed RX packet 3248 * size so we can receive jumbo frames. 3249 */ 3250 if (sc->rl_type == RL_8169) { 3251 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3252 /* 3253 * For controllers that use new jumbo frame scheme, 3254 * set maximum size of jumbo frame depedning on 3255 * controller revisions. 3256 */ 3257 if (ifp->if_mtu > RL_MTU) 3258 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 3259 sc->rl_hwrev->rl_max_mtu + 3260 ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN + 3261 ETHER_CRC_LEN); 3262 else 3263 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 3264 RE_RX_DESC_BUFLEN); 3265 } else if ((sc->rl_flags & RL_FLAG_PCIE) != 0 && 3266 sc->rl_hwrev->rl_max_mtu == RL_MTU) { 3267 /* RTL810x has no jumbo frame support. */ 3268 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, RE_RX_DESC_BUFLEN); 3269 } else 3270 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 3271 } 3272 3273 if (sc->rl_testmode) 3274 return; 3275 3276 CSR_WRITE_1(sc, sc->rl_cfg1, CSR_READ_1(sc, sc->rl_cfg1) | 3277 RL_CFG1_DRVLOAD); 3278 3279 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3280 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3281 3282 sc->rl_flags &= ~RL_FLAG_LINK; 3283 mii_mediachg(mii); 3284 3285 sc->rl_watchdog_timer = 0; 3286 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 3287 } 3288 3289 /* 3290 * Set media options. 3291 */ 3292 static int 3293 re_ifmedia_upd(struct ifnet *ifp) 3294 { 3295 struct rl_softc *sc; 3296 struct mii_data *mii; 3297 int error; 3298 3299 sc = ifp->if_softc; 3300 mii = device_get_softc(sc->rl_miibus); 3301 RL_LOCK(sc); 3302 error = mii_mediachg(mii); 3303 RL_UNLOCK(sc); 3304 3305 return (error); 3306 } 3307 3308 /* 3309 * Report current media status. 3310 */ 3311 static void 3312 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3313 { 3314 struct rl_softc *sc; 3315 struct mii_data *mii; 3316 3317 sc = ifp->if_softc; 3318 mii = device_get_softc(sc->rl_miibus); 3319 3320 RL_LOCK(sc); 3321 mii_pollstat(mii); 3322 ifmr->ifm_active = mii->mii_media_active; 3323 ifmr->ifm_status = mii->mii_media_status; 3324 RL_UNLOCK(sc); 3325 } 3326 3327 static int 3328 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3329 { 3330 struct rl_softc *sc = ifp->if_softc; 3331 struct ifreq *ifr = (struct ifreq *) data; 3332 struct mii_data *mii; 3333 uint32_t rev; 3334 int error = 0; 3335 3336 switch (command) { 3337 case SIOCSIFMTU: 3338 if (ifr->ifr_mtu < ETHERMIN || 3339 ifr->ifr_mtu > sc->rl_hwrev->rl_max_mtu) { 3340 error = EINVAL; 3341 break; 3342 } 3343 RL_LOCK(sc); 3344 if (ifp->if_mtu != ifr->ifr_mtu) { 3345 ifp->if_mtu = ifr->ifr_mtu; 3346 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 3347 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3348 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3349 re_init_locked(sc); 3350 } 3351 if (ifp->if_mtu > RL_TSO_MTU && 3352 (ifp->if_capenable & IFCAP_TSO4) != 0) { 3353 ifp->if_capenable &= ~(IFCAP_TSO4 | 3354 IFCAP_VLAN_HWTSO); 3355 ifp->if_hwassist &= ~CSUM_TSO; 3356 } 3357 VLAN_CAPABILITIES(ifp); 3358 } 3359 RL_UNLOCK(sc); 3360 break; 3361 case SIOCSIFFLAGS: 3362 RL_LOCK(sc); 3363 if ((ifp->if_flags & IFF_UP) != 0) { 3364 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3365 if (((ifp->if_flags ^ sc->rl_if_flags) 3366 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 3367 re_set_rxmode(sc); 3368 } else 3369 re_init_locked(sc); 3370 } else { 3371 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3372 re_stop(sc); 3373 } 3374 sc->rl_if_flags = ifp->if_flags; 3375 RL_UNLOCK(sc); 3376 break; 3377 case SIOCADDMULTI: 3378 case SIOCDELMULTI: 3379 RL_LOCK(sc); 3380 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3381 re_set_rxmode(sc); 3382 RL_UNLOCK(sc); 3383 break; 3384 case SIOCGIFMEDIA: 3385 case SIOCSIFMEDIA: 3386 mii = device_get_softc(sc->rl_miibus); 3387 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3388 break; 3389 case SIOCSIFCAP: 3390 { 3391 int mask, reinit; 3392 3393 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3394 reinit = 0; 3395 #ifdef DEVICE_POLLING 3396 if (mask & IFCAP_POLLING) { 3397 if (ifr->ifr_reqcap & IFCAP_POLLING) { 3398 error = ether_poll_register(re_poll, ifp); 3399 if (error) 3400 return (error); 3401 RL_LOCK(sc); 3402 /* Disable interrupts */ 3403 CSR_WRITE_2(sc, RL_IMR, 0x0000); 3404 ifp->if_capenable |= IFCAP_POLLING; 3405 RL_UNLOCK(sc); 3406 } else { 3407 error = ether_poll_deregister(ifp); 3408 /* Enable interrupts. */ 3409 RL_LOCK(sc); 3410 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 3411 ifp->if_capenable &= ~IFCAP_POLLING; 3412 RL_UNLOCK(sc); 3413 } 3414 } 3415 #endif /* DEVICE_POLLING */ 3416 RL_LOCK(sc); 3417 if ((mask & IFCAP_TXCSUM) != 0 && 3418 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 3419 ifp->if_capenable ^= IFCAP_TXCSUM; 3420 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) { 3421 rev = sc->rl_hwrev->rl_rev; 3422 if (rev == RL_HWREV_8168C || 3423 rev == RL_HWREV_8168C_SPIN2 || 3424 rev == RL_HWREV_8168CP) 3425 ifp->if_hwassist |= CSUM_TCP | CSUM_UDP; 3426 else 3427 ifp->if_hwassist |= RE_CSUM_FEATURES; 3428 } else 3429 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 3430 reinit = 1; 3431 } 3432 if ((mask & IFCAP_RXCSUM) != 0 && 3433 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 3434 ifp->if_capenable ^= IFCAP_RXCSUM; 3435 reinit = 1; 3436 } 3437 if ((mask & IFCAP_TSO4) != 0 && 3438 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 3439 ifp->if_capenable ^= IFCAP_TSO4; 3440 if ((IFCAP_TSO4 & ifp->if_capenable) != 0) 3441 ifp->if_hwassist |= CSUM_TSO; 3442 else 3443 ifp->if_hwassist &= ~CSUM_TSO; 3444 if (ifp->if_mtu > RL_TSO_MTU && 3445 (ifp->if_capenable & IFCAP_TSO4) != 0) { 3446 ifp->if_capenable &= ~IFCAP_TSO4; 3447 ifp->if_hwassist &= ~CSUM_TSO; 3448 } 3449 } 3450 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 3451 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 3452 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 3453 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3454 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 3455 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 3456 /* TSO over VLAN requires VLAN hardware tagging. */ 3457 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 3458 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 3459 reinit = 1; 3460 } 3461 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 3462 (mask & (IFCAP_HWCSUM | IFCAP_TSO4 | 3463 IFCAP_VLAN_HWTSO)) != 0) 3464 reinit = 1; 3465 if ((mask & IFCAP_WOL) != 0 && 3466 (ifp->if_capabilities & IFCAP_WOL) != 0) { 3467 if ((mask & IFCAP_WOL_UCAST) != 0) 3468 ifp->if_capenable ^= IFCAP_WOL_UCAST; 3469 if ((mask & IFCAP_WOL_MCAST) != 0) 3470 ifp->if_capenable ^= IFCAP_WOL_MCAST; 3471 if ((mask & IFCAP_WOL_MAGIC) != 0) 3472 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 3473 } 3474 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) { 3475 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3476 re_init_locked(sc); 3477 } 3478 RL_UNLOCK(sc); 3479 VLAN_CAPABILITIES(ifp); 3480 } 3481 break; 3482 default: 3483 error = ether_ioctl(ifp, command, data); 3484 break; 3485 } 3486 3487 return (error); 3488 } 3489 3490 static void 3491 re_watchdog(struct rl_softc *sc) 3492 { 3493 struct ifnet *ifp; 3494 3495 RL_LOCK_ASSERT(sc); 3496 3497 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 3498 return; 3499 3500 ifp = sc->rl_ifp; 3501 re_txeof(sc); 3502 if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) { 3503 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 3504 "-- recovering\n"); 3505 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3506 re_start_locked(ifp); 3507 return; 3508 } 3509 3510 if_printf(ifp, "watchdog timeout\n"); 3511 ifp->if_oerrors++; 3512 3513 re_rxeof(sc, NULL); 3514 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3515 re_init_locked(sc); 3516 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3517 re_start_locked(ifp); 3518 } 3519 3520 /* 3521 * Stop the adapter and free any mbufs allocated to the 3522 * RX and TX lists. 3523 */ 3524 static void 3525 re_stop(struct rl_softc *sc) 3526 { 3527 int i; 3528 struct ifnet *ifp; 3529 struct rl_txdesc *txd; 3530 struct rl_rxdesc *rxd; 3531 3532 RL_LOCK_ASSERT(sc); 3533 3534 ifp = sc->rl_ifp; 3535 3536 sc->rl_watchdog_timer = 0; 3537 callout_stop(&sc->rl_stat_callout); 3538 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3539 3540 /* 3541 * Disable accepting frames to put RX MAC into idle state. 3542 * Otherwise it's possible to get frames while stop command 3543 * execution is in progress and controller can DMA the frame 3544 * to already freed RX buffer during that period. 3545 */ 3546 CSR_WRITE_4(sc, RL_RXCFG, CSR_READ_4(sc, RL_RXCFG) & 3547 ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_MULTI | 3548 RL_RXCFG_RX_BROAD)); 3549 3550 if ((sc->rl_flags & RL_FLAG_WAIT_TXPOLL) != 0) { 3551 for (i = RL_TIMEOUT; i > 0; i--) { 3552 if ((CSR_READ_1(sc, sc->rl_txstart) & 3553 RL_TXSTART_START) == 0) 3554 break; 3555 DELAY(20); 3556 } 3557 if (i == 0) 3558 device_printf(sc->rl_dev, 3559 "stopping TX poll timed out!\n"); 3560 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 3561 } else if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0) { 3562 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB | 3563 RL_CMD_RX_ENB); 3564 if ((sc->rl_flags & RL_FLAG_CMDSTOP_WAIT_TXQ) != 0) { 3565 for (i = RL_TIMEOUT; i > 0; i--) { 3566 if ((CSR_READ_4(sc, RL_TXCFG) & 3567 RL_TXCFG_QUEUE_EMPTY) != 0) 3568 break; 3569 DELAY(100); 3570 } 3571 if (i == 0) 3572 device_printf(sc->rl_dev, 3573 "stopping TXQ timed out!\n"); 3574 } 3575 } else 3576 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 3577 DELAY(1000); 3578 CSR_WRITE_2(sc, RL_IMR, 0x0000); 3579 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 3580 3581 if (sc->rl_head != NULL) { 3582 m_freem(sc->rl_head); 3583 sc->rl_head = sc->rl_tail = NULL; 3584 } 3585 3586 /* Free the TX list buffers. */ 3587 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 3588 txd = &sc->rl_ldata.rl_tx_desc[i]; 3589 if (txd->tx_m != NULL) { 3590 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 3591 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3592 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 3593 txd->tx_dmamap); 3594 m_freem(txd->tx_m); 3595 txd->tx_m = NULL; 3596 } 3597 } 3598 3599 /* Free the RX list buffers. */ 3600 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 3601 rxd = &sc->rl_ldata.rl_rx_desc[i]; 3602 if (rxd->rx_m != NULL) { 3603 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 3604 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3605 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 3606 rxd->rx_dmamap); 3607 m_freem(rxd->rx_m); 3608 rxd->rx_m = NULL; 3609 } 3610 } 3611 3612 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3613 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 3614 rxd = &sc->rl_ldata.rl_jrx_desc[i]; 3615 if (rxd->rx_m != NULL) { 3616 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, 3617 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3618 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, 3619 rxd->rx_dmamap); 3620 m_freem(rxd->rx_m); 3621 rxd->rx_m = NULL; 3622 } 3623 } 3624 } 3625 } 3626 3627 /* 3628 * Device suspend routine. Stop the interface and save some PCI 3629 * settings in case the BIOS doesn't restore them properly on 3630 * resume. 3631 */ 3632 static int 3633 re_suspend(device_t dev) 3634 { 3635 struct rl_softc *sc; 3636 3637 sc = device_get_softc(dev); 3638 3639 RL_LOCK(sc); 3640 re_stop(sc); 3641 re_setwol(sc); 3642 sc->suspended = 1; 3643 RL_UNLOCK(sc); 3644 3645 return (0); 3646 } 3647 3648 /* 3649 * Device resume routine. Restore some PCI settings in case the BIOS 3650 * doesn't, re-enable busmastering, and restart the interface if 3651 * appropriate. 3652 */ 3653 static int 3654 re_resume(device_t dev) 3655 { 3656 struct rl_softc *sc; 3657 struct ifnet *ifp; 3658 3659 sc = device_get_softc(dev); 3660 3661 RL_LOCK(sc); 3662 3663 ifp = sc->rl_ifp; 3664 /* Take controller out of sleep mode. */ 3665 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3666 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3667 CSR_WRITE_1(sc, RL_GPIO, 3668 CSR_READ_1(sc, RL_GPIO) | 0x01); 3669 } 3670 3671 /* 3672 * Clear WOL matching such that normal Rx filtering 3673 * wouldn't interfere with WOL patterns. 3674 */ 3675 re_clrwol(sc); 3676 3677 /* reinitialize interface if necessary */ 3678 if (ifp->if_flags & IFF_UP) 3679 re_init_locked(sc); 3680 3681 sc->suspended = 0; 3682 RL_UNLOCK(sc); 3683 3684 return (0); 3685 } 3686 3687 /* 3688 * Stop all chip I/O so that the kernel's probe routines don't 3689 * get confused by errant DMAs when rebooting. 3690 */ 3691 static int 3692 re_shutdown(device_t dev) 3693 { 3694 struct rl_softc *sc; 3695 3696 sc = device_get_softc(dev); 3697 3698 RL_LOCK(sc); 3699 re_stop(sc); 3700 /* 3701 * Mark interface as down since otherwise we will panic if 3702 * interrupt comes in later on, which can happen in some 3703 * cases. 3704 */ 3705 sc->rl_ifp->if_flags &= ~IFF_UP; 3706 re_setwol(sc); 3707 RL_UNLOCK(sc); 3708 3709 return (0); 3710 } 3711 3712 static void 3713 re_set_linkspeed(struct rl_softc *sc) 3714 { 3715 struct mii_softc *miisc; 3716 struct mii_data *mii; 3717 int aneg, i, phyno; 3718 3719 RL_LOCK_ASSERT(sc); 3720 3721 mii = device_get_softc(sc->rl_miibus); 3722 mii_pollstat(mii); 3723 aneg = 0; 3724 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 3725 (IFM_ACTIVE | IFM_AVALID)) { 3726 switch IFM_SUBTYPE(mii->mii_media_active) { 3727 case IFM_10_T: 3728 case IFM_100_TX: 3729 return; 3730 case IFM_1000_T: 3731 aneg++; 3732 break; 3733 default: 3734 break; 3735 } 3736 } 3737 miisc = LIST_FIRST(&mii->mii_phys); 3738 phyno = miisc->mii_phy; 3739 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 3740 PHY_RESET(miisc); 3741 re_miibus_writereg(sc->rl_dev, phyno, MII_100T2CR, 0); 3742 re_miibus_writereg(sc->rl_dev, phyno, 3743 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 3744 re_miibus_writereg(sc->rl_dev, phyno, 3745 MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 3746 DELAY(1000); 3747 if (aneg != 0) { 3748 /* 3749 * Poll link state until re(4) get a 10/100Mbps link. 3750 */ 3751 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 3752 mii_pollstat(mii); 3753 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 3754 == (IFM_ACTIVE | IFM_AVALID)) { 3755 switch (IFM_SUBTYPE(mii->mii_media_active)) { 3756 case IFM_10_T: 3757 case IFM_100_TX: 3758 return; 3759 default: 3760 break; 3761 } 3762 } 3763 RL_UNLOCK(sc); 3764 pause("relnk", hz); 3765 RL_LOCK(sc); 3766 } 3767 if (i == MII_ANEGTICKS_GIGE) 3768 device_printf(sc->rl_dev, 3769 "establishing a link failed, WOL may not work!"); 3770 } 3771 /* 3772 * No link, force MAC to have 100Mbps, full-duplex link. 3773 * MAC does not require reprogramming on resolved speed/duplex, 3774 * so this is just for completeness. 3775 */ 3776 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 3777 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 3778 } 3779 3780 static void 3781 re_setwol(struct rl_softc *sc) 3782 { 3783 struct ifnet *ifp; 3784 int pmc; 3785 uint16_t pmstat; 3786 uint8_t v; 3787 3788 RL_LOCK_ASSERT(sc); 3789 3790 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3791 return; 3792 3793 ifp = sc->rl_ifp; 3794 /* Put controller into sleep mode. */ 3795 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3796 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3797 CSR_WRITE_1(sc, RL_GPIO, 3798 CSR_READ_1(sc, RL_GPIO) & ~0x01); 3799 } 3800 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 3801 re_set_rxmode(sc); 3802 if ((sc->rl_flags & RL_FLAG_WOL_MANLINK) != 0) 3803 re_set_linkspeed(sc); 3804 if ((sc->rl_flags & RL_FLAG_WOLRXENB) != 0) 3805 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB); 3806 } 3807 /* Enable config register write. */ 3808 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3809 3810 /* Enable PME. */ 3811 v = CSR_READ_1(sc, sc->rl_cfg1); 3812 v &= ~RL_CFG1_PME; 3813 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3814 v |= RL_CFG1_PME; 3815 CSR_WRITE_1(sc, sc->rl_cfg1, v); 3816 3817 v = CSR_READ_1(sc, sc->rl_cfg3); 3818 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3819 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3820 v |= RL_CFG3_WOL_MAGIC; 3821 CSR_WRITE_1(sc, sc->rl_cfg3, v); 3822 3823 v = CSR_READ_1(sc, sc->rl_cfg5); 3824 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST | 3825 RL_CFG5_WOL_LANWAKE); 3826 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 3827 v |= RL_CFG5_WOL_UCAST; 3828 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 3829 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 3830 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3831 v |= RL_CFG5_WOL_LANWAKE; 3832 CSR_WRITE_1(sc, sc->rl_cfg5, v); 3833 3834 /* Config register write done. */ 3835 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3836 3837 if ((ifp->if_capenable & IFCAP_WOL) == 0 && 3838 (sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) 3839 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) & ~0x80); 3840 /* 3841 * It seems that hardware resets its link speed to 100Mbps in 3842 * power down mode so switching to 100Mbps in driver is not 3843 * needed. 3844 */ 3845 3846 /* Request PME if WOL is requested. */ 3847 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 3848 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3849 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3850 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3851 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 3852 } 3853 3854 static void 3855 re_clrwol(struct rl_softc *sc) 3856 { 3857 int pmc; 3858 uint8_t v; 3859 3860 RL_LOCK_ASSERT(sc); 3861 3862 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3863 return; 3864 3865 /* Enable config register write. */ 3866 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3867 3868 v = CSR_READ_1(sc, sc->rl_cfg3); 3869 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3870 CSR_WRITE_1(sc, sc->rl_cfg3, v); 3871 3872 /* Config register write done. */ 3873 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3874 3875 v = CSR_READ_1(sc, sc->rl_cfg5); 3876 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3877 v &= ~RL_CFG5_WOL_LANWAKE; 3878 CSR_WRITE_1(sc, sc->rl_cfg5, v); 3879 } 3880 3881 static void 3882 re_add_sysctls(struct rl_softc *sc) 3883 { 3884 struct sysctl_ctx_list *ctx; 3885 struct sysctl_oid_list *children; 3886 int error; 3887 3888 ctx = device_get_sysctl_ctx(sc->rl_dev); 3889 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev)); 3890 3891 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "stats", 3892 CTLTYPE_INT | CTLFLAG_RW, sc, 0, re_sysctl_stats, "I", 3893 "Statistics Information"); 3894 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) 3895 return; 3896 3897 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "int_rx_mod", 3898 CTLTYPE_INT | CTLFLAG_RW, &sc->rl_int_rx_mod, 0, 3899 sysctl_hw_re_int_mod, "I", "re RX interrupt moderation"); 3900 /* Pull in device tunables. */ 3901 sc->rl_int_rx_mod = RL_TIMER_DEFAULT; 3902 error = resource_int_value(device_get_name(sc->rl_dev), 3903 device_get_unit(sc->rl_dev), "int_rx_mod", &sc->rl_int_rx_mod); 3904 if (error == 0) { 3905 if (sc->rl_int_rx_mod < RL_TIMER_MIN || 3906 sc->rl_int_rx_mod > RL_TIMER_MAX) { 3907 device_printf(sc->rl_dev, "int_rx_mod value out of " 3908 "range; using default: %d\n", 3909 RL_TIMER_DEFAULT); 3910 sc->rl_int_rx_mod = RL_TIMER_DEFAULT; 3911 } 3912 } 3913 3914 } 3915 3916 static int 3917 re_sysctl_stats(SYSCTL_HANDLER_ARGS) 3918 { 3919 struct rl_softc *sc; 3920 struct rl_stats *stats; 3921 int error, i, result; 3922 3923 result = -1; 3924 error = sysctl_handle_int(oidp, &result, 0, req); 3925 if (error || req->newptr == NULL) 3926 return (error); 3927 3928 if (result == 1) { 3929 sc = (struct rl_softc *)arg1; 3930 RL_LOCK(sc); 3931 if ((sc->rl_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 3932 RL_UNLOCK(sc); 3933 goto done; 3934 } 3935 bus_dmamap_sync(sc->rl_ldata.rl_stag, 3936 sc->rl_ldata.rl_smap, BUS_DMASYNC_PREREAD); 3937 CSR_WRITE_4(sc, RL_DUMPSTATS_HI, 3938 RL_ADDR_HI(sc->rl_ldata.rl_stats_addr)); 3939 CSR_WRITE_4(sc, RL_DUMPSTATS_LO, 3940 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr)); 3941 CSR_WRITE_4(sc, RL_DUMPSTATS_LO, 3942 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr | 3943 RL_DUMPSTATS_START)); 3944 for (i = RL_TIMEOUT; i > 0; i--) { 3945 if ((CSR_READ_4(sc, RL_DUMPSTATS_LO) & 3946 RL_DUMPSTATS_START) == 0) 3947 break; 3948 DELAY(1000); 3949 } 3950 bus_dmamap_sync(sc->rl_ldata.rl_stag, 3951 sc->rl_ldata.rl_smap, BUS_DMASYNC_POSTREAD); 3952 RL_UNLOCK(sc); 3953 if (i == 0) { 3954 device_printf(sc->rl_dev, 3955 "DUMP statistics request timedout\n"); 3956 return (ETIMEDOUT); 3957 } 3958 done: 3959 stats = sc->rl_ldata.rl_stats; 3960 printf("%s statistics:\n", device_get_nameunit(sc->rl_dev)); 3961 printf("Tx frames : %ju\n", 3962 (uintmax_t)le64toh(stats->rl_tx_pkts)); 3963 printf("Rx frames : %ju\n", 3964 (uintmax_t)le64toh(stats->rl_rx_pkts)); 3965 printf("Tx errors : %ju\n", 3966 (uintmax_t)le64toh(stats->rl_tx_errs)); 3967 printf("Rx errors : %u\n", 3968 le32toh(stats->rl_rx_errs)); 3969 printf("Rx missed frames : %u\n", 3970 (uint32_t)le16toh(stats->rl_missed_pkts)); 3971 printf("Rx frame alignment errs : %u\n", 3972 (uint32_t)le16toh(stats->rl_rx_framealign_errs)); 3973 printf("Tx single collisions : %u\n", 3974 le32toh(stats->rl_tx_onecoll)); 3975 printf("Tx multiple collisions : %u\n", 3976 le32toh(stats->rl_tx_multicolls)); 3977 printf("Rx unicast frames : %ju\n", 3978 (uintmax_t)le64toh(stats->rl_rx_ucasts)); 3979 printf("Rx broadcast frames : %ju\n", 3980 (uintmax_t)le64toh(stats->rl_rx_bcasts)); 3981 printf("Rx multicast frames : %u\n", 3982 le32toh(stats->rl_rx_mcasts)); 3983 printf("Tx aborts : %u\n", 3984 (uint32_t)le16toh(stats->rl_tx_aborts)); 3985 printf("Tx underruns : %u\n", 3986 (uint32_t)le16toh(stats->rl_rx_underruns)); 3987 } 3988 3989 return (error); 3990 } 3991 3992 static int 3993 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3994 { 3995 int error, value; 3996 3997 if (arg1 == NULL) 3998 return (EINVAL); 3999 value = *(int *)arg1; 4000 error = sysctl_handle_int(oidp, &value, 0, req); 4001 if (error || req->newptr == NULL) 4002 return (error); 4003 if (value < low || value > high) 4004 return (EINVAL); 4005 *(int *)arg1 = value; 4006 4007 return (0); 4008 } 4009 4010 static int 4011 sysctl_hw_re_int_mod(SYSCTL_HANDLER_ARGS) 4012 { 4013 4014 return (sysctl_int_range(oidp, arg1, arg2, req, RL_TIMER_MIN, 4015 RL_TIMER_MAX)); 4016 } 4017