1 /*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44 /* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111 #ifdef HAVE_KERNEL_OPTION_HEADERS 112 #include "opt_device_polling.h" 113 #endif 114 115 #include <sys/param.h> 116 #include <sys/endian.h> 117 #include <sys/systm.h> 118 #include <sys/sockio.h> 119 #include <sys/mbuf.h> 120 #include <sys/malloc.h> 121 #include <sys/module.h> 122 #include <sys/kernel.h> 123 #include <sys/socket.h> 124 #include <sys/lock.h> 125 #include <sys/mutex.h> 126 #include <sys/taskqueue.h> 127 128 #include <net/if.h> 129 #include <net/if_arp.h> 130 #include <net/ethernet.h> 131 #include <net/if_dl.h> 132 #include <net/if_media.h> 133 #include <net/if_types.h> 134 #include <net/if_vlan_var.h> 135 136 #include <net/bpf.h> 137 138 #include <machine/bus.h> 139 #include <machine/resource.h> 140 #include <sys/bus.h> 141 #include <sys/rman.h> 142 143 #include <dev/mii/mii.h> 144 #include <dev/mii/miivar.h> 145 146 #include <dev/pci/pcireg.h> 147 #include <dev/pci/pcivar.h> 148 149 #include <pci/if_rlreg.h> 150 151 MODULE_DEPEND(re, pci, 1, 1, 1); 152 MODULE_DEPEND(re, ether, 1, 1, 1); 153 MODULE_DEPEND(re, miibus, 1, 1, 1); 154 155 /* "device miibus" required. See GENERIC if you get errors here. */ 156 #include "miibus_if.h" 157 158 /* 159 * Default to using PIO access for this driver. 160 */ 161 #define RE_USEIOSPACE 162 163 /* Tunables. */ 164 static int msi_disable = 1; 165 TUNABLE_INT("hw.re.msi_disable", &msi_disable); 166 167 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 168 169 /* 170 * Various supported device vendors/types and their names. 171 */ 172 static struct rl_type re_devs[] = { 173 { DLINK_VENDORID, DLINK_DEVICEID_528T, RL_HWREV_8169S, 174 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 175 { DLINK_VENDORID, DLINK_DEVICEID_528T, RL_HWREV_8169_8110SB, 176 "D-Link DGE-528(T) Rev.B1 Gigabit Ethernet Adapter" }, 177 { RT_VENDORID, RT_DEVICEID_8139, RL_HWREV_8139CPLUS, 178 "RealTek 8139C+ 10/100BaseTX" }, 179 { RT_VENDORID, RT_DEVICEID_8101E, RL_HWREV_8101E, 180 "RealTek 8101E PCIe 10/100baseTX" }, 181 { RT_VENDORID, RT_DEVICEID_8168, RL_HWREV_8168_SPIN1, 182 "RealTek 8168/8111B PCIe Gigabit Ethernet" }, 183 { RT_VENDORID, RT_DEVICEID_8168, RL_HWREV_8168_SPIN2, 184 "RealTek 8168/8111B PCIe Gigabit Ethernet" }, 185 { RT_VENDORID, RT_DEVICEID_8168, RL_HWREV_8168_SPIN3, 186 "RealTek 8168/8111B PCIe Gigabit Ethernet" }, 187 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169, 188 "RealTek 8169 Gigabit Ethernet" }, 189 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169S, 190 "RealTek 8169S Single-chip Gigabit Ethernet" }, 191 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169_8110SB, 192 "RealTek 8169SB/8110SB Single-chip Gigabit Ethernet" }, 193 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169_8110SC, 194 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 195 { RT_VENDORID, RT_DEVICEID_8169SC, RL_HWREV_8169_8110SC, 196 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 197 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8110S, 198 "RealTek 8110S Single-chip Gigabit Ethernet" }, 199 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, RL_HWREV_8169S, 200 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 201 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, RL_HWREV_8169S, 202 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 203 { USR_VENDORID, USR_DEVICEID_997902, RL_HWREV_8169S, 204 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 205 }; 206 207 static struct rl_hwrev re_hwrevs[] = { 208 { RL_HWREV_8139, RL_8139, "" }, 209 { RL_HWREV_8139A, RL_8139, "A" }, 210 { RL_HWREV_8139AG, RL_8139, "A-G" }, 211 { RL_HWREV_8139B, RL_8139, "B" }, 212 { RL_HWREV_8130, RL_8139, "8130" }, 213 { RL_HWREV_8139C, RL_8139, "C" }, 214 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 215 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 216 { RL_HWREV_8168_SPIN1, RL_8169, "8168"}, 217 { RL_HWREV_8169, RL_8169, "8169"}, 218 { RL_HWREV_8169S, RL_8169, "8169S"}, 219 { RL_HWREV_8110S, RL_8169, "8110S"}, 220 { RL_HWREV_8169_8110SB, RL_8169, "8169SB"}, 221 { RL_HWREV_8169_8110SC, RL_8169, "8169SC"}, 222 { RL_HWREV_8100, RL_8139, "8100"}, 223 { RL_HWREV_8101, RL_8139, "8101"}, 224 { RL_HWREV_8100E, RL_8169, "8100E"}, 225 { RL_HWREV_8101E, RL_8169, "8101E"}, 226 { RL_HWREV_8168_SPIN2, RL_8169, "8168"}, 227 { RL_HWREV_8168_SPIN3, RL_8169, "8168"}, 228 { 0, 0, NULL } 229 }; 230 231 static int re_probe (device_t); 232 static int re_attach (device_t); 233 static int re_detach (device_t); 234 235 static int re_encap (struct rl_softc *, struct mbuf **); 236 237 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 238 static int re_allocmem (device_t, struct rl_softc *); 239 static __inline void re_discard_rxbuf 240 (struct rl_softc *, int); 241 static int re_newbuf (struct rl_softc *, int); 242 static int re_rx_list_init (struct rl_softc *); 243 static int re_tx_list_init (struct rl_softc *); 244 #ifdef RE_FIXUP_RX 245 static __inline void re_fixup_rx 246 (struct mbuf *); 247 #endif 248 static int re_rxeof (struct rl_softc *); 249 static void re_txeof (struct rl_softc *); 250 #ifdef DEVICE_POLLING 251 static void re_poll (struct ifnet *, enum poll_cmd, int); 252 static void re_poll_locked (struct ifnet *, enum poll_cmd, int); 253 #endif 254 static int re_intr (void *); 255 static void re_tick (void *); 256 static void re_tx_task (void *, int); 257 static void re_int_task (void *, int); 258 static void re_start (struct ifnet *); 259 static int re_ioctl (struct ifnet *, u_long, caddr_t); 260 static void re_init (void *); 261 static void re_init_locked (struct rl_softc *); 262 static void re_stop (struct rl_softc *); 263 static void re_watchdog (struct rl_softc *); 264 static int re_suspend (device_t); 265 static int re_resume (device_t); 266 static int re_shutdown (device_t); 267 static int re_ifmedia_upd (struct ifnet *); 268 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 269 270 static void re_eeprom_putbyte (struct rl_softc *, int); 271 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 272 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 273 static int re_gmii_readreg (device_t, int, int); 274 static int re_gmii_writereg (device_t, int, int, int); 275 276 static int re_miibus_readreg (device_t, int, int); 277 static int re_miibus_writereg (device_t, int, int, int); 278 static void re_miibus_statchg (device_t); 279 280 static void re_setmulti (struct rl_softc *); 281 static void re_reset (struct rl_softc *); 282 static void re_setwol (struct rl_softc *); 283 static void re_clrwol (struct rl_softc *); 284 285 #ifdef RE_DIAG 286 static int re_diag (struct rl_softc *); 287 #endif 288 289 #ifdef RE_USEIOSPACE 290 #define RL_RES SYS_RES_IOPORT 291 #define RL_RID RL_PCI_LOIO 292 #else 293 #define RL_RES SYS_RES_MEMORY 294 #define RL_RID RL_PCI_LOMEM 295 #endif 296 297 static device_method_t re_methods[] = { 298 /* Device interface */ 299 DEVMETHOD(device_probe, re_probe), 300 DEVMETHOD(device_attach, re_attach), 301 DEVMETHOD(device_detach, re_detach), 302 DEVMETHOD(device_suspend, re_suspend), 303 DEVMETHOD(device_resume, re_resume), 304 DEVMETHOD(device_shutdown, re_shutdown), 305 306 /* bus interface */ 307 DEVMETHOD(bus_print_child, bus_generic_print_child), 308 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 309 310 /* MII interface */ 311 DEVMETHOD(miibus_readreg, re_miibus_readreg), 312 DEVMETHOD(miibus_writereg, re_miibus_writereg), 313 DEVMETHOD(miibus_statchg, re_miibus_statchg), 314 315 { 0, 0 } 316 }; 317 318 static driver_t re_driver = { 319 "re", 320 re_methods, 321 sizeof(struct rl_softc) 322 }; 323 324 static devclass_t re_devclass; 325 326 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 327 DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0); 328 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 329 330 #define EE_SET(x) \ 331 CSR_WRITE_1(sc, RL_EECMD, \ 332 CSR_READ_1(sc, RL_EECMD) | x) 333 334 #define EE_CLR(x) \ 335 CSR_WRITE_1(sc, RL_EECMD, \ 336 CSR_READ_1(sc, RL_EECMD) & ~x) 337 338 /* 339 * Send a read command and address to the EEPROM, check for ACK. 340 */ 341 static void 342 re_eeprom_putbyte(sc, addr) 343 struct rl_softc *sc; 344 int addr; 345 { 346 register int d, i; 347 348 d = addr | (RL_9346_READ << sc->rl_eewidth); 349 350 /* 351 * Feed in each bit and strobe the clock. 352 */ 353 354 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 355 if (d & i) { 356 EE_SET(RL_EE_DATAIN); 357 } else { 358 EE_CLR(RL_EE_DATAIN); 359 } 360 DELAY(100); 361 EE_SET(RL_EE_CLK); 362 DELAY(150); 363 EE_CLR(RL_EE_CLK); 364 DELAY(100); 365 } 366 367 return; 368 } 369 370 /* 371 * Read a word of data stored in the EEPROM at address 'addr.' 372 */ 373 static void 374 re_eeprom_getword(sc, addr, dest) 375 struct rl_softc *sc; 376 int addr; 377 u_int16_t *dest; 378 { 379 register int i; 380 u_int16_t word = 0; 381 382 /* 383 * Send address of word we want to read. 384 */ 385 re_eeprom_putbyte(sc, addr); 386 387 /* 388 * Start reading bits from EEPROM. 389 */ 390 for (i = 0x8000; i; i >>= 1) { 391 EE_SET(RL_EE_CLK); 392 DELAY(100); 393 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 394 word |= i; 395 EE_CLR(RL_EE_CLK); 396 DELAY(100); 397 } 398 399 *dest = word; 400 401 return; 402 } 403 404 /* 405 * Read a sequence of words from the EEPROM. 406 */ 407 static void 408 re_read_eeprom(sc, dest, off, cnt) 409 struct rl_softc *sc; 410 caddr_t dest; 411 int off; 412 int cnt; 413 { 414 int i; 415 u_int16_t word = 0, *ptr; 416 417 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 418 419 DELAY(100); 420 421 for (i = 0; i < cnt; i++) { 422 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 423 re_eeprom_getword(sc, off + i, &word); 424 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 425 ptr = (u_int16_t *)(dest + (i * 2)); 426 *ptr = word; 427 } 428 429 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 430 431 return; 432 } 433 434 static int 435 re_gmii_readreg(dev, phy, reg) 436 device_t dev; 437 int phy, reg; 438 { 439 struct rl_softc *sc; 440 u_int32_t rval; 441 int i; 442 443 if (phy != 1) 444 return (0); 445 446 sc = device_get_softc(dev); 447 448 /* Let the rgephy driver read the GMEDIASTAT register */ 449 450 if (reg == RL_GMEDIASTAT) { 451 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 452 return (rval); 453 } 454 455 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 456 DELAY(1000); 457 458 for (i = 0; i < RL_TIMEOUT; i++) { 459 rval = CSR_READ_4(sc, RL_PHYAR); 460 if (rval & RL_PHYAR_BUSY) 461 break; 462 DELAY(100); 463 } 464 465 if (i == RL_TIMEOUT) { 466 device_printf(sc->rl_dev, "PHY read failed\n"); 467 return (0); 468 } 469 470 return (rval & RL_PHYAR_PHYDATA); 471 } 472 473 static int 474 re_gmii_writereg(dev, phy, reg, data) 475 device_t dev; 476 int phy, reg, data; 477 { 478 struct rl_softc *sc; 479 u_int32_t rval; 480 int i; 481 482 sc = device_get_softc(dev); 483 484 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 485 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 486 DELAY(1000); 487 488 for (i = 0; i < RL_TIMEOUT; i++) { 489 rval = CSR_READ_4(sc, RL_PHYAR); 490 if (!(rval & RL_PHYAR_BUSY)) 491 break; 492 DELAY(100); 493 } 494 495 if (i == RL_TIMEOUT) { 496 device_printf(sc->rl_dev, "PHY write failed\n"); 497 return (0); 498 } 499 500 return (0); 501 } 502 503 static int 504 re_miibus_readreg(dev, phy, reg) 505 device_t dev; 506 int phy, reg; 507 { 508 struct rl_softc *sc; 509 u_int16_t rval = 0; 510 u_int16_t re8139_reg = 0; 511 512 sc = device_get_softc(dev); 513 514 if (sc->rl_type == RL_8169) { 515 rval = re_gmii_readreg(dev, phy, reg); 516 return (rval); 517 } 518 519 /* Pretend the internal PHY is only at address 0 */ 520 if (phy) { 521 return (0); 522 } 523 switch (reg) { 524 case MII_BMCR: 525 re8139_reg = RL_BMCR; 526 break; 527 case MII_BMSR: 528 re8139_reg = RL_BMSR; 529 break; 530 case MII_ANAR: 531 re8139_reg = RL_ANAR; 532 break; 533 case MII_ANER: 534 re8139_reg = RL_ANER; 535 break; 536 case MII_ANLPAR: 537 re8139_reg = RL_LPAR; 538 break; 539 case MII_PHYIDR1: 540 case MII_PHYIDR2: 541 return (0); 542 /* 543 * Allow the rlphy driver to read the media status 544 * register. If we have a link partner which does not 545 * support NWAY, this is the register which will tell 546 * us the results of parallel detection. 547 */ 548 case RL_MEDIASTAT: 549 rval = CSR_READ_1(sc, RL_MEDIASTAT); 550 return (rval); 551 default: 552 device_printf(sc->rl_dev, "bad phy register\n"); 553 return (0); 554 } 555 rval = CSR_READ_2(sc, re8139_reg); 556 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 557 /* 8139C+ has different bit layout. */ 558 rval &= ~(BMCR_LOOP | BMCR_ISO); 559 } 560 return (rval); 561 } 562 563 static int 564 re_miibus_writereg(dev, phy, reg, data) 565 device_t dev; 566 int phy, reg, data; 567 { 568 struct rl_softc *sc; 569 u_int16_t re8139_reg = 0; 570 int rval = 0; 571 572 sc = device_get_softc(dev); 573 574 if (sc->rl_type == RL_8169) { 575 rval = re_gmii_writereg(dev, phy, reg, data); 576 return (rval); 577 } 578 579 /* Pretend the internal PHY is only at address 0 */ 580 if (phy) 581 return (0); 582 583 switch (reg) { 584 case MII_BMCR: 585 re8139_reg = RL_BMCR; 586 if (sc->rl_type == RL_8139CPLUS) { 587 /* 8139C+ has different bit layout. */ 588 data &= ~(BMCR_LOOP | BMCR_ISO); 589 } 590 break; 591 case MII_BMSR: 592 re8139_reg = RL_BMSR; 593 break; 594 case MII_ANAR: 595 re8139_reg = RL_ANAR; 596 break; 597 case MII_ANER: 598 re8139_reg = RL_ANER; 599 break; 600 case MII_ANLPAR: 601 re8139_reg = RL_LPAR; 602 break; 603 case MII_PHYIDR1: 604 case MII_PHYIDR2: 605 return (0); 606 break; 607 default: 608 device_printf(sc->rl_dev, "bad phy register\n"); 609 return (0); 610 } 611 CSR_WRITE_2(sc, re8139_reg, data); 612 return (0); 613 } 614 615 static void 616 re_miibus_statchg(dev) 617 device_t dev; 618 { 619 620 } 621 622 /* 623 * Program the 64-bit multicast hash filter. 624 */ 625 static void 626 re_setmulti(sc) 627 struct rl_softc *sc; 628 { 629 struct ifnet *ifp; 630 int h = 0; 631 u_int32_t hashes[2] = { 0, 0 }; 632 struct ifmultiaddr *ifma; 633 u_int32_t rxfilt; 634 int mcnt = 0; 635 u_int32_t hwrev; 636 637 RL_LOCK_ASSERT(sc); 638 639 ifp = sc->rl_ifp; 640 641 642 rxfilt = CSR_READ_4(sc, RL_RXCFG); 643 rxfilt &= ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_MULTI); 644 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 645 if (ifp->if_flags & IFF_PROMISC) 646 rxfilt |= RL_RXCFG_RX_ALLPHYS; 647 /* 648 * Unlike other hardwares, we have to explicitly set 649 * RL_RXCFG_RX_MULTI to receive multicast frames in 650 * promiscuous mode. 651 */ 652 rxfilt |= RL_RXCFG_RX_MULTI; 653 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 654 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 655 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 656 return; 657 } 658 659 /* first, zot all the existing hash bits */ 660 CSR_WRITE_4(sc, RL_MAR0, 0); 661 CSR_WRITE_4(sc, RL_MAR4, 0); 662 663 /* now program new ones */ 664 IF_ADDR_LOCK(ifp); 665 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 666 if (ifma->ifma_addr->sa_family != AF_LINK) 667 continue; 668 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 669 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 670 if (h < 32) 671 hashes[0] |= (1 << h); 672 else 673 hashes[1] |= (1 << (h - 32)); 674 mcnt++; 675 } 676 IF_ADDR_UNLOCK(ifp); 677 678 if (mcnt) 679 rxfilt |= RL_RXCFG_RX_MULTI; 680 else 681 rxfilt &= ~RL_RXCFG_RX_MULTI; 682 683 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 684 685 /* 686 * For some unfathomable reason, RealTek decided to reverse 687 * the order of the multicast hash registers in the PCI Express 688 * parts. This means we have to write the hash pattern in reverse 689 * order for those devices. 690 */ 691 692 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 693 694 switch (hwrev) { 695 case RL_HWREV_8100E: 696 case RL_HWREV_8101E: 697 case RL_HWREV_8168_SPIN1: 698 case RL_HWREV_8168_SPIN2: 699 case RL_HWREV_8168_SPIN3: 700 CSR_WRITE_4(sc, RL_MAR0, bswap32(hashes[1])); 701 CSR_WRITE_4(sc, RL_MAR4, bswap32(hashes[0])); 702 break; 703 default: 704 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 705 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 706 break; 707 } 708 } 709 710 static void 711 re_reset(sc) 712 struct rl_softc *sc; 713 { 714 register int i; 715 716 RL_LOCK_ASSERT(sc); 717 718 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 719 720 for (i = 0; i < RL_TIMEOUT; i++) { 721 DELAY(10); 722 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 723 break; 724 } 725 if (i == RL_TIMEOUT) 726 device_printf(sc->rl_dev, "reset never completed!\n"); 727 728 CSR_WRITE_1(sc, 0x82, 1); 729 } 730 731 #ifdef RE_DIAG 732 733 /* 734 * The following routine is designed to test for a defect on some 735 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 736 * lines connected to the bus, however for a 32-bit only card, they 737 * should be pulled high. The result of this defect is that the 738 * NIC will not work right if you plug it into a 64-bit slot: DMA 739 * operations will be done with 64-bit transfers, which will fail 740 * because the 64-bit data lines aren't connected. 741 * 742 * There's no way to work around this (short of talking a soldering 743 * iron to the board), however we can detect it. The method we use 744 * here is to put the NIC into digital loopback mode, set the receiver 745 * to promiscuous mode, and then try to send a frame. We then compare 746 * the frame data we sent to what was received. If the data matches, 747 * then the NIC is working correctly, otherwise we know the user has 748 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 749 * slot. In the latter case, there's no way the NIC can work correctly, 750 * so we print out a message on the console and abort the device attach. 751 */ 752 753 static int 754 re_diag(sc) 755 struct rl_softc *sc; 756 { 757 struct ifnet *ifp = sc->rl_ifp; 758 struct mbuf *m0; 759 struct ether_header *eh; 760 struct rl_desc *cur_rx; 761 u_int16_t status; 762 u_int32_t rxstat; 763 int total_len, i, error = 0, phyaddr; 764 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 765 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 766 767 /* Allocate a single mbuf */ 768 MGETHDR(m0, M_DONTWAIT, MT_DATA); 769 if (m0 == NULL) 770 return (ENOBUFS); 771 772 RL_LOCK(sc); 773 774 /* 775 * Initialize the NIC in test mode. This sets the chip up 776 * so that it can send and receive frames, but performs the 777 * following special functions: 778 * - Puts receiver in promiscuous mode 779 * - Enables digital loopback mode 780 * - Leaves interrupts turned off 781 */ 782 783 ifp->if_flags |= IFF_PROMISC; 784 sc->rl_testmode = 1; 785 re_reset(sc); 786 re_init_locked(sc); 787 sc->rl_link = 1; 788 if (sc->rl_type == RL_8169) 789 phyaddr = 1; 790 else 791 phyaddr = 0; 792 793 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 794 for (i = 0; i < RL_TIMEOUT; i++) { 795 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 796 if (!(status & BMCR_RESET)) 797 break; 798 } 799 800 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 801 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 802 803 DELAY(100000); 804 805 /* Put some data in the mbuf */ 806 807 eh = mtod(m0, struct ether_header *); 808 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 809 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 810 eh->ether_type = htons(ETHERTYPE_IP); 811 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 812 813 /* 814 * Queue the packet, start transmission. 815 * Note: IF_HANDOFF() ultimately calls re_start() for us. 816 */ 817 818 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 819 RL_UNLOCK(sc); 820 /* XXX: re_diag must not be called when in ALTQ mode */ 821 IF_HANDOFF(&ifp->if_snd, m0, ifp); 822 RL_LOCK(sc); 823 m0 = NULL; 824 825 /* Wait for it to propagate through the chip */ 826 827 DELAY(100000); 828 for (i = 0; i < RL_TIMEOUT; i++) { 829 status = CSR_READ_2(sc, RL_ISR); 830 CSR_WRITE_2(sc, RL_ISR, status); 831 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 832 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 833 break; 834 DELAY(10); 835 } 836 837 if (i == RL_TIMEOUT) { 838 device_printf(sc->rl_dev, 839 "diagnostic failed, failed to receive packet in" 840 " loopback mode\n"); 841 error = EIO; 842 goto done; 843 } 844 845 /* 846 * The packet should have been dumped into the first 847 * entry in the RX DMA ring. Grab it from there. 848 */ 849 850 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 851 sc->rl_ldata.rl_rx_list_map, 852 BUS_DMASYNC_POSTREAD); 853 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 854 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 855 BUS_DMASYNC_POSTREAD); 856 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 857 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 858 859 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 860 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 861 eh = mtod(m0, struct ether_header *); 862 863 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 864 total_len = RL_RXBYTES(cur_rx); 865 rxstat = le32toh(cur_rx->rl_cmdstat); 866 867 if (total_len != ETHER_MIN_LEN) { 868 device_printf(sc->rl_dev, 869 "diagnostic failed, received short packet\n"); 870 error = EIO; 871 goto done; 872 } 873 874 /* Test that the received packet data matches what we sent. */ 875 876 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 877 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 878 ntohs(eh->ether_type) != ETHERTYPE_IP) { 879 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 880 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 881 dst, ":", src, ":", ETHERTYPE_IP); 882 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 883 eh->ether_dhost, ":", eh->ether_shost, ":", 884 ntohs(eh->ether_type)); 885 device_printf(sc->rl_dev, "You may have a defective 32-bit " 886 "NIC plugged into a 64-bit PCI slot.\n"); 887 device_printf(sc->rl_dev, "Please re-install the NIC in a " 888 "32-bit slot for proper operation.\n"); 889 device_printf(sc->rl_dev, "Read the re(4) man page for more " 890 "details.\n"); 891 error = EIO; 892 } 893 894 done: 895 /* Turn interface off, release resources */ 896 897 sc->rl_testmode = 0; 898 sc->rl_link = 0; 899 ifp->if_flags &= ~IFF_PROMISC; 900 re_stop(sc); 901 if (m0 != NULL) 902 m_freem(m0); 903 904 RL_UNLOCK(sc); 905 906 return (error); 907 } 908 909 #endif 910 911 /* 912 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 913 * IDs against our list and return a device name if we find a match. 914 */ 915 static int 916 re_probe(dev) 917 device_t dev; 918 { 919 struct rl_type *t; 920 uint16_t devid, vendor; 921 uint16_t revid, sdevid; 922 int i; 923 924 vendor = pci_get_vendor(dev); 925 devid = pci_get_device(dev); 926 revid = pci_get_revid(dev); 927 sdevid = pci_get_subdevice(dev); 928 929 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 930 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 931 /* 932 * Only attach to rev. 3 of the Linksys EG1032 adapter. 933 * Rev. 2 is supported by sk(4). 934 */ 935 return (ENXIO); 936 } 937 } 938 939 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 940 if (revid != 0x20) { 941 /* 8139, let rl(4) take care of this device. */ 942 return (ENXIO); 943 } 944 } 945 946 t = re_devs; 947 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) { 948 if (vendor == t->rl_vid && devid == t->rl_did) { 949 device_set_desc(dev, t->rl_name); 950 return (BUS_PROBE_DEFAULT); 951 } 952 } 953 954 return (ENXIO); 955 } 956 957 /* 958 * Map a single buffer address. 959 */ 960 961 static void 962 re_dma_map_addr(arg, segs, nseg, error) 963 void *arg; 964 bus_dma_segment_t *segs; 965 int nseg; 966 int error; 967 { 968 bus_addr_t *addr; 969 970 if (error) 971 return; 972 973 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 974 addr = arg; 975 *addr = segs->ds_addr; 976 } 977 978 static int 979 re_allocmem(dev, sc) 980 device_t dev; 981 struct rl_softc *sc; 982 { 983 bus_size_t rx_list_size, tx_list_size; 984 int error; 985 int i; 986 987 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 988 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 989 990 /* 991 * Allocate the parent bus DMA tag appropriate for PCI. 992 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD 993 * register should be set. However some RealTek chips are known 994 * to be buggy on DAC handling, therefore disable DAC by limiting 995 * DMA address space to 32bit. PCIe variants of RealTek chips 996 * may not have the limitation but I took safer path. 997 */ 998 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 999 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1000 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 1001 NULL, NULL, &sc->rl_parent_tag); 1002 if (error) { 1003 device_printf(dev, "could not allocate parent DMA tag\n"); 1004 return (error); 1005 } 1006 1007 /* 1008 * Allocate map for TX mbufs. 1009 */ 1010 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 1011 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1012 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 1013 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 1014 if (error) { 1015 device_printf(dev, "could not allocate TX DMA tag\n"); 1016 return (error); 1017 } 1018 1019 /* 1020 * Allocate map for RX mbufs. 1021 */ 1022 1023 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 1024 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1025 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 1026 if (error) { 1027 device_printf(dev, "could not allocate RX DMA tag\n"); 1028 return (error); 1029 } 1030 1031 /* 1032 * Allocate map for TX descriptor list. 1033 */ 1034 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1035 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1036 NULL, tx_list_size, 1, tx_list_size, 0, 1037 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1038 if (error) { 1039 device_printf(dev, "could not allocate TX DMA ring tag\n"); 1040 return (error); 1041 } 1042 1043 /* Allocate DMA'able memory for the TX ring */ 1044 1045 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1046 (void **)&sc->rl_ldata.rl_tx_list, 1047 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1048 &sc->rl_ldata.rl_tx_list_map); 1049 if (error) { 1050 device_printf(dev, "could not allocate TX DMA ring\n"); 1051 return (error); 1052 } 1053 1054 /* Load the map for the TX ring. */ 1055 1056 sc->rl_ldata.rl_tx_list_addr = 0; 1057 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1058 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1059 tx_list_size, re_dma_map_addr, 1060 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1061 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 1062 device_printf(dev, "could not load TX DMA ring\n"); 1063 return (ENOMEM); 1064 } 1065 1066 /* Create DMA maps for TX buffers */ 1067 1068 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1069 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1070 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1071 if (error) { 1072 device_printf(dev, "could not create DMA map for TX\n"); 1073 return (error); 1074 } 1075 } 1076 1077 /* 1078 * Allocate map for RX descriptor list. 1079 */ 1080 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1081 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1082 NULL, rx_list_size, 1, rx_list_size, 0, 1083 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1084 if (error) { 1085 device_printf(dev, "could not create RX DMA ring tag\n"); 1086 return (error); 1087 } 1088 1089 /* Allocate DMA'able memory for the RX ring */ 1090 1091 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1092 (void **)&sc->rl_ldata.rl_rx_list, 1093 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1094 &sc->rl_ldata.rl_rx_list_map); 1095 if (error) { 1096 device_printf(dev, "could not allocate RX DMA ring\n"); 1097 return (error); 1098 } 1099 1100 /* Load the map for the RX ring. */ 1101 1102 sc->rl_ldata.rl_rx_list_addr = 0; 1103 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1104 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1105 rx_list_size, re_dma_map_addr, 1106 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1107 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1108 device_printf(dev, "could not load RX DMA ring\n"); 1109 return (ENOMEM); 1110 } 1111 1112 /* Create DMA maps for RX buffers */ 1113 1114 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1115 &sc->rl_ldata.rl_rx_sparemap); 1116 if (error) { 1117 device_printf(dev, "could not create spare DMA map for RX\n"); 1118 return (error); 1119 } 1120 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1121 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1122 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1123 if (error) { 1124 device_printf(dev, "could not create DMA map for RX\n"); 1125 return (error); 1126 } 1127 } 1128 1129 return (0); 1130 } 1131 1132 /* 1133 * Attach the interface. Allocate softc structures, do ifmedia 1134 * setup and ethernet/BPF attach. 1135 */ 1136 static int 1137 re_attach(dev) 1138 device_t dev; 1139 { 1140 u_char eaddr[ETHER_ADDR_LEN]; 1141 u_int16_t as[ETHER_ADDR_LEN / 2]; 1142 struct rl_softc *sc; 1143 struct ifnet *ifp; 1144 struct rl_hwrev *hw_rev; 1145 int hwrev; 1146 u_int16_t re_did = 0; 1147 int error = 0, rid, i; 1148 int msic, reg; 1149 uint8_t cfg; 1150 1151 sc = device_get_softc(dev); 1152 sc->rl_dev = dev; 1153 1154 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1155 MTX_DEF); 1156 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1157 1158 /* 1159 * Map control/status registers. 1160 */ 1161 pci_enable_busmaster(dev); 1162 1163 rid = RL_RID; 1164 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 1165 RF_ACTIVE); 1166 1167 if (sc->rl_res == NULL) { 1168 device_printf(dev, "couldn't map ports/memory\n"); 1169 error = ENXIO; 1170 goto fail; 1171 } 1172 1173 sc->rl_btag = rman_get_bustag(sc->rl_res); 1174 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1175 1176 msic = 0; 1177 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 1178 msic = pci_msi_count(dev); 1179 if (bootverbose) 1180 device_printf(dev, "MSI count : %d\n", msic); 1181 } 1182 if (msic == RL_MSI_MESSAGES && msi_disable == 0) { 1183 if (pci_alloc_msi(dev, &msic) == 0) { 1184 if (msic == RL_MSI_MESSAGES) { 1185 device_printf(dev, "Using %d MSI messages\n", 1186 msic); 1187 sc->rl_msi = 1; 1188 /* Explicitly set MSI enable bit. */ 1189 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1190 cfg = CSR_READ_1(sc, RL_CFG2); 1191 cfg |= RL_CFG2_MSI; 1192 CSR_WRITE_1(sc, RL_CFG2, cfg); 1193 CSR_WRITE_1(sc, RL_EECMD, 0); 1194 } else 1195 pci_release_msi(dev); 1196 } 1197 } 1198 1199 /* Allocate interrupt */ 1200 if (sc->rl_msi == 0) { 1201 rid = 0; 1202 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1203 RF_SHAREABLE | RF_ACTIVE); 1204 if (sc->rl_irq[0] == NULL) { 1205 device_printf(dev, "couldn't allocate IRQ resources\n"); 1206 error = ENXIO; 1207 goto fail; 1208 } 1209 } else { 1210 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1211 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1212 SYS_RES_IRQ, &rid, RF_ACTIVE); 1213 if (sc->rl_irq[i] == NULL) { 1214 device_printf(dev, 1215 "couldn't llocate IRQ resources for " 1216 "message %d\n", rid); 1217 error = ENXIO; 1218 goto fail; 1219 } 1220 } 1221 } 1222 1223 /* Reset the adapter. */ 1224 RL_LOCK(sc); 1225 re_reset(sc); 1226 RL_UNLOCK(sc); 1227 1228 hw_rev = re_hwrevs; 1229 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 1230 while (hw_rev->rl_desc != NULL) { 1231 if (hw_rev->rl_rev == hwrev) { 1232 sc->rl_type = hw_rev->rl_type; 1233 break; 1234 } 1235 hw_rev++; 1236 } 1237 if (hw_rev->rl_desc == NULL) { 1238 device_printf(dev, "Unknown H/W revision: %08x\n", hwrev); 1239 error = ENXIO; 1240 goto fail; 1241 } 1242 1243 sc->rl_eewidth = RL_9356_ADDR_LEN; 1244 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1245 if (re_did != 0x8129) 1246 sc->rl_eewidth = RL_9346_ADDR_LEN; 1247 1248 /* 1249 * Get station address from the EEPROM. 1250 */ 1251 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1252 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1253 as[i] = le16toh(as[i]); 1254 bcopy(as, eaddr, sizeof(eaddr)); 1255 1256 if (sc->rl_type == RL_8169) { 1257 /* Set RX length mask and number of descriptors. */ 1258 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1259 sc->rl_txstart = RL_GTXSTART; 1260 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1261 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1262 } else { 1263 /* Set RX length mask and number of descriptors. */ 1264 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1265 sc->rl_txstart = RL_TXSTART; 1266 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1267 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1268 } 1269 if (hw_rev->rl_desc == NULL) { 1270 device_printf(dev, "Unsupported revision : 0x%08x\n", hwrev); 1271 error = ENXIO; 1272 goto fail; 1273 } 1274 1275 error = re_allocmem(dev, sc); 1276 if (error) 1277 goto fail; 1278 1279 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1280 if (ifp == NULL) { 1281 device_printf(dev, "can not if_alloc()\n"); 1282 error = ENOSPC; 1283 goto fail; 1284 } 1285 1286 /* Do MII setup */ 1287 if (mii_phy_probe(dev, &sc->rl_miibus, 1288 re_ifmedia_upd, re_ifmedia_sts)) { 1289 device_printf(dev, "MII without any phy!\n"); 1290 error = ENXIO; 1291 goto fail; 1292 } 1293 1294 /* Take PHY out of power down mode. */ 1295 if (sc->rl_type == RL_8169) { 1296 uint32_t rev; 1297 1298 rev = CSR_READ_4(sc, RL_TXCFG); 1299 /* HWVERID 0, 1 and 2 : bit26-30, bit23 */ 1300 rev &= 0x7c800000; 1301 if (rev != 0) { 1302 /* RTL8169S single chip */ 1303 switch (rev) { 1304 case RL_HWREV_8169_8110SB: 1305 case RL_HWREV_8169_8110SC: 1306 case RL_HWREV_8168_SPIN2: 1307 case RL_HWREV_8168_SPIN3: 1308 re_gmii_writereg(dev, 1, 0x1f, 0); 1309 re_gmii_writereg(dev, 1, 0x0e, 0); 1310 break; 1311 default: 1312 break; 1313 } 1314 } 1315 } 1316 1317 ifp->if_softc = sc; 1318 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1319 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1320 ifp->if_ioctl = re_ioctl; 1321 ifp->if_start = re_start; 1322 ifp->if_hwassist = RE_CSUM_FEATURES | CSUM_TSO; 1323 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 1324 ifp->if_capenable = ifp->if_capabilities; 1325 ifp->if_init = re_init; 1326 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1327 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1328 IFQ_SET_READY(&ifp->if_snd); 1329 1330 TASK_INIT(&sc->rl_txtask, 1, re_tx_task, ifp); 1331 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1332 1333 /* 1334 * Call MI attach routine. 1335 */ 1336 ether_ifattach(ifp, eaddr); 1337 1338 /* VLAN capability setup */ 1339 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1340 if (ifp->if_capabilities & IFCAP_HWCSUM) 1341 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1342 /* Enable WOL if PM is supported. */ 1343 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, ®) == 0) 1344 ifp->if_capabilities |= IFCAP_WOL; 1345 ifp->if_capenable = ifp->if_capabilities; 1346 #ifdef DEVICE_POLLING 1347 ifp->if_capabilities |= IFCAP_POLLING; 1348 #endif 1349 /* 1350 * Tell the upper layer(s) we support long frames. 1351 * Must appear after the call to ether_ifattach() because 1352 * ether_ifattach() sets ifi_hdrlen to the default value. 1353 */ 1354 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1355 1356 #ifdef RE_DIAG 1357 /* 1358 * Perform hardware diagnostic on the original RTL8169. 1359 * Some 32-bit cards were incorrectly wired and would 1360 * malfunction if plugged into a 64-bit slot. 1361 */ 1362 1363 if (hwrev == RL_HWREV_8169) { 1364 error = re_diag(sc); 1365 if (error) { 1366 device_printf(dev, 1367 "attach aborted due to hardware diag failure\n"); 1368 ether_ifdetach(ifp); 1369 goto fail; 1370 } 1371 } 1372 #endif 1373 1374 /* Hook interrupt last to avoid having to lock softc */ 1375 if (sc->rl_msi == 0) 1376 error = bus_setup_intr(dev, sc->rl_irq[0], 1377 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1378 &sc->rl_intrhand[0]); 1379 else { 1380 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1381 error = bus_setup_intr(dev, sc->rl_irq[i], 1382 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1383 &sc->rl_intrhand[i]); 1384 if (error != 0) 1385 break; 1386 } 1387 } 1388 if (error) { 1389 device_printf(dev, "couldn't set up irq\n"); 1390 ether_ifdetach(ifp); 1391 } 1392 1393 fail: 1394 1395 if (error) 1396 re_detach(dev); 1397 1398 return (error); 1399 } 1400 1401 /* 1402 * Shutdown hardware and free up resources. This can be called any 1403 * time after the mutex has been initialized. It is called in both 1404 * the error case in attach and the normal detach case so it needs 1405 * to be careful about only freeing resources that have actually been 1406 * allocated. 1407 */ 1408 static int 1409 re_detach(dev) 1410 device_t dev; 1411 { 1412 struct rl_softc *sc; 1413 struct ifnet *ifp; 1414 int i, rid; 1415 1416 sc = device_get_softc(dev); 1417 ifp = sc->rl_ifp; 1418 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1419 1420 #ifdef DEVICE_POLLING 1421 if (ifp->if_capenable & IFCAP_POLLING) 1422 ether_poll_deregister(ifp); 1423 #endif 1424 /* These should only be active if attach succeeded */ 1425 if (device_is_attached(dev)) { 1426 RL_LOCK(sc); 1427 #if 0 1428 sc->suspended = 1; 1429 #endif 1430 re_stop(sc); 1431 RL_UNLOCK(sc); 1432 callout_drain(&sc->rl_stat_callout); 1433 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1434 taskqueue_drain(taskqueue_fast, &sc->rl_txtask); 1435 /* 1436 * Force off the IFF_UP flag here, in case someone 1437 * still had a BPF descriptor attached to this 1438 * interface. If they do, ether_ifdetach() will cause 1439 * the BPF code to try and clear the promisc mode 1440 * flag, which will bubble down to re_ioctl(), 1441 * which will try to call re_init() again. This will 1442 * turn the NIC back on and restart the MII ticker, 1443 * which will panic the system when the kernel tries 1444 * to invoke the re_tick() function that isn't there 1445 * anymore. 1446 */ 1447 ifp->if_flags &= ~IFF_UP; 1448 ether_ifdetach(ifp); 1449 } 1450 if (sc->rl_miibus) 1451 device_delete_child(dev, sc->rl_miibus); 1452 bus_generic_detach(dev); 1453 1454 /* 1455 * The rest is resource deallocation, so we should already be 1456 * stopped here. 1457 */ 1458 1459 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1460 if (sc->rl_intrhand[i] != NULL) { 1461 bus_teardown_intr(dev, sc->rl_irq[i], 1462 sc->rl_intrhand[i]); 1463 sc->rl_intrhand[i] = NULL; 1464 } 1465 } 1466 if (ifp != NULL) 1467 if_free(ifp); 1468 if (sc->rl_msi == 0) { 1469 if (sc->rl_irq[0] != NULL) { 1470 bus_release_resource(dev, SYS_RES_IRQ, 0, 1471 sc->rl_irq[0]); 1472 sc->rl_irq[0] = NULL; 1473 } 1474 } else { 1475 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1476 if (sc->rl_irq[i] != NULL) { 1477 bus_release_resource(dev, SYS_RES_IRQ, rid, 1478 sc->rl_irq[i]); 1479 sc->rl_irq[i] = NULL; 1480 } 1481 } 1482 pci_release_msi(dev); 1483 } 1484 if (sc->rl_res) 1485 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1486 1487 /* Unload and free the RX DMA ring memory and map */ 1488 1489 if (sc->rl_ldata.rl_rx_list_tag) { 1490 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1491 sc->rl_ldata.rl_rx_list_map); 1492 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1493 sc->rl_ldata.rl_rx_list, 1494 sc->rl_ldata.rl_rx_list_map); 1495 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1496 } 1497 1498 /* Unload and free the TX DMA ring memory and map */ 1499 1500 if (sc->rl_ldata.rl_tx_list_tag) { 1501 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1502 sc->rl_ldata.rl_tx_list_map); 1503 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1504 sc->rl_ldata.rl_tx_list, 1505 sc->rl_ldata.rl_tx_list_map); 1506 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1507 } 1508 1509 /* Destroy all the RX and TX buffer maps */ 1510 1511 if (sc->rl_ldata.rl_tx_mtag) { 1512 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1513 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1514 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1515 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1516 } 1517 if (sc->rl_ldata.rl_rx_mtag) { 1518 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) 1519 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1520 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1521 if (sc->rl_ldata.rl_rx_sparemap) 1522 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1523 sc->rl_ldata.rl_rx_sparemap); 1524 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1525 } 1526 1527 /* Unload and free the stats buffer and map */ 1528 1529 if (sc->rl_ldata.rl_stag) { 1530 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1531 sc->rl_ldata.rl_rx_list_map); 1532 bus_dmamem_free(sc->rl_ldata.rl_stag, 1533 sc->rl_ldata.rl_stats, 1534 sc->rl_ldata.rl_smap); 1535 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1536 } 1537 1538 if (sc->rl_parent_tag) 1539 bus_dma_tag_destroy(sc->rl_parent_tag); 1540 1541 mtx_destroy(&sc->rl_mtx); 1542 1543 return (0); 1544 } 1545 1546 static __inline void 1547 re_discard_rxbuf(sc, idx) 1548 struct rl_softc *sc; 1549 int idx; 1550 { 1551 struct rl_desc *desc; 1552 struct rl_rxdesc *rxd; 1553 uint32_t cmdstat; 1554 1555 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1556 desc = &sc->rl_ldata.rl_rx_list[idx]; 1557 desc->rl_vlanctl = 0; 1558 cmdstat = rxd->rx_size; 1559 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1560 cmdstat |= RL_RDESC_CMD_EOR; 1561 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1562 } 1563 1564 static int 1565 re_newbuf(sc, idx) 1566 struct rl_softc *sc; 1567 int idx; 1568 { 1569 struct mbuf *m; 1570 struct rl_rxdesc *rxd; 1571 bus_dma_segment_t segs[1]; 1572 bus_dmamap_t map; 1573 struct rl_desc *desc; 1574 uint32_t cmdstat; 1575 int error, nsegs; 1576 1577 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1578 if (m == NULL) 1579 return (ENOBUFS); 1580 1581 m->m_len = m->m_pkthdr.len = MCLBYTES; 1582 #ifdef RE_FIXUP_RX 1583 /* 1584 * This is part of an evil trick to deal with non-x86 platforms. 1585 * The RealTek chip requires RX buffers to be aligned on 64-bit 1586 * boundaries, but that will hose non-x86 machines. To get around 1587 * this, we leave some empty space at the start of each buffer 1588 * and for non-x86 hosts, we copy the buffer back six bytes 1589 * to achieve word alignment. This is slightly more efficient 1590 * than allocating a new buffer, copying the contents, and 1591 * discarding the old buffer. 1592 */ 1593 m_adj(m, RE_ETHER_ALIGN); 1594 #endif 1595 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1596 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1597 if (error != 0) { 1598 m_freem(m); 1599 return (ENOBUFS); 1600 } 1601 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1602 1603 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1604 if (rxd->rx_m != NULL) { 1605 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1606 BUS_DMASYNC_POSTREAD); 1607 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1608 } 1609 1610 rxd->rx_m = m; 1611 map = rxd->rx_dmamap; 1612 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1613 rxd->rx_size = segs[0].ds_len; 1614 sc->rl_ldata.rl_rx_sparemap = map; 1615 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1616 BUS_DMASYNC_PREREAD); 1617 1618 desc = &sc->rl_ldata.rl_rx_list[idx]; 1619 desc->rl_vlanctl = 0; 1620 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1621 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1622 cmdstat = segs[0].ds_len; 1623 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1624 cmdstat |= RL_RDESC_CMD_EOR; 1625 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1626 1627 return (0); 1628 } 1629 1630 #ifdef RE_FIXUP_RX 1631 static __inline void 1632 re_fixup_rx(m) 1633 struct mbuf *m; 1634 { 1635 int i; 1636 uint16_t *src, *dst; 1637 1638 src = mtod(m, uint16_t *); 1639 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1640 1641 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1642 *dst++ = *src++; 1643 1644 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1645 1646 return; 1647 } 1648 #endif 1649 1650 static int 1651 re_tx_list_init(sc) 1652 struct rl_softc *sc; 1653 { 1654 struct rl_desc *desc; 1655 int i; 1656 1657 RL_LOCK_ASSERT(sc); 1658 1659 bzero(sc->rl_ldata.rl_tx_list, 1660 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 1661 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1662 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 1663 /* Set EOR. */ 1664 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 1665 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 1666 1667 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1668 sc->rl_ldata.rl_tx_list_map, 1669 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1670 1671 sc->rl_ldata.rl_tx_prodidx = 0; 1672 sc->rl_ldata.rl_tx_considx = 0; 1673 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 1674 1675 return (0); 1676 } 1677 1678 static int 1679 re_rx_list_init(sc) 1680 struct rl_softc *sc; 1681 { 1682 int error, i; 1683 1684 bzero(sc->rl_ldata.rl_rx_list, 1685 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 1686 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1687 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 1688 if ((error = re_newbuf(sc, i)) != 0) 1689 return (error); 1690 } 1691 1692 /* Flush the RX descriptors */ 1693 1694 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1695 sc->rl_ldata.rl_rx_list_map, 1696 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1697 1698 sc->rl_ldata.rl_rx_prodidx = 0; 1699 sc->rl_head = sc->rl_tail = NULL; 1700 1701 return (0); 1702 } 1703 1704 /* 1705 * RX handler for C+ and 8169. For the gigE chips, we support 1706 * the reception of jumbo frames that have been fragmented 1707 * across multiple 2K mbuf cluster buffers. 1708 */ 1709 static int 1710 re_rxeof(sc) 1711 struct rl_softc *sc; 1712 { 1713 struct mbuf *m; 1714 struct ifnet *ifp; 1715 int i, total_len; 1716 struct rl_desc *cur_rx; 1717 u_int32_t rxstat, rxvlan; 1718 int maxpkt = 16; 1719 1720 RL_LOCK_ASSERT(sc); 1721 1722 ifp = sc->rl_ifp; 1723 1724 /* Invalidate the descriptor memory */ 1725 1726 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1727 sc->rl_ldata.rl_rx_list_map, 1728 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1729 1730 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 1731 i = RL_RX_DESC_NXT(sc, i)) { 1732 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1733 rxstat = le32toh(cur_rx->rl_cmdstat); 1734 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 1735 break; 1736 total_len = rxstat & sc->rl_rxlenmask; 1737 rxvlan = le32toh(cur_rx->rl_vlanctl); 1738 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 1739 1740 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1741 if (re_newbuf(sc, i) != 0) { 1742 /* 1743 * If this is part of a multi-fragment packet, 1744 * discard all the pieces. 1745 */ 1746 if (sc->rl_head != NULL) { 1747 m_freem(sc->rl_head); 1748 sc->rl_head = sc->rl_tail = NULL; 1749 } 1750 re_discard_rxbuf(sc, i); 1751 continue; 1752 } 1753 m->m_len = RE_RX_DESC_BUFLEN; 1754 if (sc->rl_head == NULL) 1755 sc->rl_head = sc->rl_tail = m; 1756 else { 1757 m->m_flags &= ~M_PKTHDR; 1758 sc->rl_tail->m_next = m; 1759 sc->rl_tail = m; 1760 } 1761 continue; 1762 } 1763 1764 /* 1765 * NOTE: for the 8139C+, the frame length field 1766 * is always 12 bits in size, but for the gigE chips, 1767 * it is 13 bits (since the max RX frame length is 16K). 1768 * Unfortunately, all 32 bits in the status word 1769 * were already used, so to make room for the extra 1770 * length bit, RealTek took out the 'frame alignment 1771 * error' bit and shifted the other status bits 1772 * over one slot. The OWN, EOR, FS and LS bits are 1773 * still in the same places. We have already extracted 1774 * the frame length and checked the OWN bit, so rather 1775 * than using an alternate bit mapping, we shift the 1776 * status bits one space to the right so we can evaluate 1777 * them using the 8169 status as though it was in the 1778 * same format as that of the 8139C+. 1779 */ 1780 if (sc->rl_type == RL_8169) 1781 rxstat >>= 1; 1782 1783 /* 1784 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 1785 * set, but if CRC is clear, it will still be a valid frame. 1786 */ 1787 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 && 1788 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) { 1789 ifp->if_ierrors++; 1790 /* 1791 * If this is part of a multi-fragment packet, 1792 * discard all the pieces. 1793 */ 1794 if (sc->rl_head != NULL) { 1795 m_freem(sc->rl_head); 1796 sc->rl_head = sc->rl_tail = NULL; 1797 } 1798 re_discard_rxbuf(sc, i); 1799 continue; 1800 } 1801 1802 /* 1803 * If allocating a replacement mbuf fails, 1804 * reload the current one. 1805 */ 1806 1807 if (re_newbuf(sc, i) != 0) { 1808 ifp->if_iqdrops++; 1809 if (sc->rl_head != NULL) { 1810 m_freem(sc->rl_head); 1811 sc->rl_head = sc->rl_tail = NULL; 1812 } 1813 re_discard_rxbuf(sc, i); 1814 continue; 1815 } 1816 1817 if (sc->rl_head != NULL) { 1818 m->m_len = total_len % RE_RX_DESC_BUFLEN; 1819 if (m->m_len == 0) 1820 m->m_len = RE_RX_DESC_BUFLEN; 1821 /* 1822 * Special case: if there's 4 bytes or less 1823 * in this buffer, the mbuf can be discarded: 1824 * the last 4 bytes is the CRC, which we don't 1825 * care about anyway. 1826 */ 1827 if (m->m_len <= ETHER_CRC_LEN) { 1828 sc->rl_tail->m_len -= 1829 (ETHER_CRC_LEN - m->m_len); 1830 m_freem(m); 1831 } else { 1832 m->m_len -= ETHER_CRC_LEN; 1833 m->m_flags &= ~M_PKTHDR; 1834 sc->rl_tail->m_next = m; 1835 } 1836 m = sc->rl_head; 1837 sc->rl_head = sc->rl_tail = NULL; 1838 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1839 } else 1840 m->m_pkthdr.len = m->m_len = 1841 (total_len - ETHER_CRC_LEN); 1842 1843 #ifdef RE_FIXUP_RX 1844 re_fixup_rx(m); 1845 #endif 1846 ifp->if_ipackets++; 1847 m->m_pkthdr.rcvif = ifp; 1848 1849 /* Do RX checksumming if enabled */ 1850 1851 if (ifp->if_capenable & IFCAP_RXCSUM) { 1852 1853 /* Check IP header checksum */ 1854 if (rxstat & RL_RDESC_STAT_PROTOID) 1855 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1856 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1857 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1858 1859 /* Check TCP/UDP checksum */ 1860 if ((RL_TCPPKT(rxstat) && 1861 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1862 (RL_UDPPKT(rxstat) && 1863 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1864 m->m_pkthdr.csum_flags |= 1865 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1866 m->m_pkthdr.csum_data = 0xffff; 1867 } 1868 } 1869 maxpkt--; 1870 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 1871 m->m_pkthdr.ether_vtag = 1872 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)); 1873 m->m_flags |= M_VLANTAG; 1874 } 1875 RL_UNLOCK(sc); 1876 (*ifp->if_input)(ifp, m); 1877 RL_LOCK(sc); 1878 } 1879 1880 /* Flush the RX DMA ring */ 1881 1882 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1883 sc->rl_ldata.rl_rx_list_map, 1884 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1885 1886 sc->rl_ldata.rl_rx_prodidx = i; 1887 1888 if (maxpkt) 1889 return(EAGAIN); 1890 1891 return(0); 1892 } 1893 1894 static void 1895 re_txeof(sc) 1896 struct rl_softc *sc; 1897 { 1898 struct ifnet *ifp; 1899 struct rl_txdesc *txd; 1900 u_int32_t txstat; 1901 int cons; 1902 1903 cons = sc->rl_ldata.rl_tx_considx; 1904 if (cons == sc->rl_ldata.rl_tx_prodidx) 1905 return; 1906 1907 ifp = sc->rl_ifp; 1908 /* Invalidate the TX descriptor list */ 1909 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1910 sc->rl_ldata.rl_tx_list_map, 1911 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1912 1913 for (; cons != sc->rl_ldata.rl_tx_prodidx; 1914 cons = RL_TX_DESC_NXT(sc, cons)) { 1915 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 1916 if (txstat & RL_TDESC_STAT_OWN) 1917 break; 1918 /* 1919 * We only stash mbufs in the last descriptor 1920 * in a fragment chain, which also happens to 1921 * be the only place where the TX status bits 1922 * are valid. 1923 */ 1924 if (txstat & RL_TDESC_CMD_EOF) { 1925 txd = &sc->rl_ldata.rl_tx_desc[cons]; 1926 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 1927 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 1928 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 1929 txd->tx_dmamap); 1930 KASSERT(txd->tx_m != NULL, 1931 ("%s: freeing NULL mbufs!", __func__)); 1932 m_freem(txd->tx_m); 1933 txd->tx_m = NULL; 1934 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 1935 RL_TDESC_STAT_COLCNT)) 1936 ifp->if_collisions++; 1937 if (txstat & RL_TDESC_STAT_TXERRSUM) 1938 ifp->if_oerrors++; 1939 else 1940 ifp->if_opackets++; 1941 } 1942 sc->rl_ldata.rl_tx_free++; 1943 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1944 } 1945 sc->rl_ldata.rl_tx_considx = cons; 1946 1947 /* No changes made to the TX ring, so no flush needed */ 1948 1949 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 1950 /* 1951 * Some chips will ignore a second TX request issued 1952 * while an existing transmission is in progress. If 1953 * the transmitter goes idle but there are still 1954 * packets waiting to be sent, we need to restart the 1955 * channel here to flush them out. This only seems to 1956 * be required with the PCIe devices. 1957 */ 1958 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 1959 1960 #ifdef RE_TX_MODERATION 1961 /* 1962 * If not all descriptors have been reaped yet, reload 1963 * the timer so that we will eventually get another 1964 * interrupt that will cause us to re-enter this routine. 1965 * This is done in case the transmitter has gone idle. 1966 */ 1967 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 1968 #endif 1969 } else 1970 sc->rl_watchdog_timer = 0; 1971 } 1972 1973 static void 1974 re_tick(xsc) 1975 void *xsc; 1976 { 1977 struct rl_softc *sc; 1978 struct mii_data *mii; 1979 struct ifnet *ifp; 1980 1981 sc = xsc; 1982 ifp = sc->rl_ifp; 1983 1984 RL_LOCK_ASSERT(sc); 1985 1986 re_watchdog(sc); 1987 1988 mii = device_get_softc(sc->rl_miibus); 1989 mii_tick(mii); 1990 if (sc->rl_link) { 1991 if (!(mii->mii_media_status & IFM_ACTIVE)) 1992 sc->rl_link = 0; 1993 } else { 1994 if (mii->mii_media_status & IFM_ACTIVE && 1995 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1996 sc->rl_link = 1; 1997 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1998 taskqueue_enqueue_fast(taskqueue_fast, 1999 &sc->rl_txtask); 2000 } 2001 } 2002 2003 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2004 } 2005 2006 #ifdef DEVICE_POLLING 2007 static void 2008 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2009 { 2010 struct rl_softc *sc = ifp->if_softc; 2011 2012 RL_LOCK(sc); 2013 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2014 re_poll_locked(ifp, cmd, count); 2015 RL_UNLOCK(sc); 2016 } 2017 2018 static void 2019 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2020 { 2021 struct rl_softc *sc = ifp->if_softc; 2022 2023 RL_LOCK_ASSERT(sc); 2024 2025 sc->rxcycles = count; 2026 re_rxeof(sc); 2027 re_txeof(sc); 2028 2029 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2030 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2031 2032 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2033 u_int16_t status; 2034 2035 status = CSR_READ_2(sc, RL_ISR); 2036 if (status == 0xffff) 2037 return; 2038 if (status) 2039 CSR_WRITE_2(sc, RL_ISR, status); 2040 2041 /* 2042 * XXX check behaviour on receiver stalls. 2043 */ 2044 2045 if (status & RL_ISR_SYSTEM_ERR) { 2046 re_reset(sc); 2047 re_init_locked(sc); 2048 } 2049 } 2050 } 2051 #endif /* DEVICE_POLLING */ 2052 2053 static int 2054 re_intr(arg) 2055 void *arg; 2056 { 2057 struct rl_softc *sc; 2058 uint16_t status; 2059 2060 sc = arg; 2061 2062 status = CSR_READ_2(sc, RL_ISR); 2063 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2064 return (FILTER_STRAY); 2065 CSR_WRITE_2(sc, RL_IMR, 0); 2066 2067 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2068 2069 return (FILTER_HANDLED); 2070 } 2071 2072 static void 2073 re_int_task(arg, npending) 2074 void *arg; 2075 int npending; 2076 { 2077 struct rl_softc *sc; 2078 struct ifnet *ifp; 2079 u_int16_t status; 2080 int rval = 0; 2081 2082 sc = arg; 2083 ifp = sc->rl_ifp; 2084 2085 RL_LOCK(sc); 2086 2087 status = CSR_READ_2(sc, RL_ISR); 2088 CSR_WRITE_2(sc, RL_ISR, status); 2089 2090 if (sc->suspended || 2091 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2092 RL_UNLOCK(sc); 2093 return; 2094 } 2095 2096 #ifdef DEVICE_POLLING 2097 if (ifp->if_capenable & IFCAP_POLLING) { 2098 RL_UNLOCK(sc); 2099 return; 2100 } 2101 #endif 2102 2103 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2104 rval = re_rxeof(sc); 2105 2106 #ifdef RE_TX_MODERATION 2107 if (status & (RL_ISR_TIMEOUT_EXPIRED| 2108 #else 2109 if (status & (RL_ISR_TX_OK| 2110 #endif 2111 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2112 re_txeof(sc); 2113 2114 if (status & RL_ISR_SYSTEM_ERR) { 2115 re_reset(sc); 2116 re_init_locked(sc); 2117 } 2118 2119 if (status & RL_ISR_LINKCHG) { 2120 callout_stop(&sc->rl_stat_callout); 2121 re_tick(sc); 2122 } 2123 2124 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2125 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2126 2127 RL_UNLOCK(sc); 2128 2129 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2130 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2131 return; 2132 } 2133 2134 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2135 2136 return; 2137 } 2138 2139 static int 2140 re_encap(sc, m_head) 2141 struct rl_softc *sc; 2142 struct mbuf **m_head; 2143 { 2144 struct rl_txdesc *txd, *txd_last; 2145 bus_dma_segment_t segs[RL_NTXSEGS]; 2146 bus_dmamap_t map; 2147 struct mbuf *m_new; 2148 struct rl_desc *desc; 2149 int nsegs, prod; 2150 int i, error, ei, si; 2151 int padlen; 2152 uint32_t cmdstat, csum_flags, vlanctl; 2153 2154 RL_LOCK_ASSERT(sc); 2155 M_ASSERTPKTHDR((*m_head)); 2156 2157 /* 2158 * With some of the RealTek chips, using the checksum offload 2159 * support in conjunction with the autopadding feature results 2160 * in the transmission of corrupt frames. For example, if we 2161 * need to send a really small IP fragment that's less than 60 2162 * bytes in size, and IP header checksumming is enabled, the 2163 * resulting ethernet frame that appears on the wire will 2164 * have garbled payload. To work around this, if TX IP checksum 2165 * offload is enabled, we always manually pad short frames out 2166 * to the minimum ethernet frame size. 2167 */ 2168 if ((*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN && 2169 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) { 2170 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2171 if (M_WRITABLE(*m_head) == 0) { 2172 /* Get a writable copy. */ 2173 m_new = m_dup(*m_head, M_DONTWAIT); 2174 m_freem(*m_head); 2175 if (m_new == NULL) { 2176 *m_head = NULL; 2177 return (ENOBUFS); 2178 } 2179 *m_head = m_new; 2180 } 2181 if ((*m_head)->m_next != NULL || 2182 M_TRAILINGSPACE(*m_head) < padlen) { 2183 m_new = m_defrag(*m_head, M_DONTWAIT); 2184 if (m_new == NULL) { 2185 m_freem(*m_head); 2186 *m_head = NULL; 2187 return (ENOBUFS); 2188 } 2189 } else 2190 m_new = *m_head; 2191 2192 /* 2193 * Manually pad short frames, and zero the pad space 2194 * to avoid leaking data. 2195 */ 2196 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2197 m_new->m_pkthdr.len += padlen; 2198 m_new->m_len = m_new->m_pkthdr.len; 2199 *m_head = m_new; 2200 } 2201 2202 prod = sc->rl_ldata.rl_tx_prodidx; 2203 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2204 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2205 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2206 if (error == EFBIG) { 2207 m_new = m_collapse(*m_head, M_DONTWAIT, RL_NTXSEGS); 2208 if (m_new == NULL) { 2209 m_freem(*m_head); 2210 *m_head = NULL; 2211 return (ENOBUFS); 2212 } 2213 *m_head = m_new; 2214 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2215 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2216 if (error != 0) { 2217 m_freem(*m_head); 2218 *m_head = NULL; 2219 return (error); 2220 } 2221 } else if (error != 0) 2222 return (error); 2223 if (nsegs == 0) { 2224 m_freem(*m_head); 2225 *m_head = NULL; 2226 return (EIO); 2227 } 2228 2229 /* Check for number of available descriptors. */ 2230 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2231 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2232 return (ENOBUFS); 2233 } 2234 2235 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2236 BUS_DMASYNC_PREWRITE); 2237 2238 /* 2239 * Set up checksum offload. Note: checksum offload bits must 2240 * appear in all descriptors of a multi-descriptor transmit 2241 * attempt. This is according to testing done with an 8169 2242 * chip. This is a requirement. 2243 */ 2244 csum_flags = 0; 2245 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) 2246 csum_flags = RL_TDESC_CMD_LGSEND | 2247 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2248 RL_TDESC_CMD_MSSVAL_SHIFT); 2249 else { 2250 /* 2251 * Unconditionally enable IP checksum if TCP or UDP 2252 * checksum is required. Otherwise, TCP/UDP checksum 2253 * does't make effects. 2254 */ 2255 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) { 2256 csum_flags |= RL_TDESC_CMD_IPCSUM; 2257 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2258 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2259 if (((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2260 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2261 } 2262 } 2263 2264 /* 2265 * Set up hardware VLAN tagging. Note: vlan tag info must 2266 * appear in all descriptors of a multi-descriptor 2267 * transmission attempt. 2268 */ 2269 vlanctl = 0; 2270 if ((*m_head)->m_flags & M_VLANTAG) 2271 vlanctl = 2272 htole32(htons((*m_head)->m_pkthdr.ether_vtag) | 2273 RL_TDESC_VLANCTL_TAG); 2274 2275 si = prod; 2276 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2277 desc = &sc->rl_ldata.rl_tx_list[prod]; 2278 desc->rl_vlanctl = vlanctl; 2279 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2280 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2281 cmdstat = segs[i].ds_len; 2282 if (i != 0) 2283 cmdstat |= RL_TDESC_CMD_OWN; 2284 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2285 cmdstat |= RL_TDESC_CMD_EOR; 2286 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2287 sc->rl_ldata.rl_tx_free--; 2288 } 2289 /* Update producer index. */ 2290 sc->rl_ldata.rl_tx_prodidx = prod; 2291 2292 /* Set EOF on the last descriptor. */ 2293 ei = RL_TX_DESC_PRV(sc, prod); 2294 desc = &sc->rl_ldata.rl_tx_list[ei]; 2295 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2296 2297 desc = &sc->rl_ldata.rl_tx_list[si]; 2298 /* Set SOF and transfer ownership of packet to the chip. */ 2299 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2300 2301 /* 2302 * Insure that the map for this transmission 2303 * is placed at the array index of the last descriptor 2304 * in this chain. (Swap last and first dmamaps.) 2305 */ 2306 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2307 map = txd->tx_dmamap; 2308 txd->tx_dmamap = txd_last->tx_dmamap; 2309 txd_last->tx_dmamap = map; 2310 txd_last->tx_m = *m_head; 2311 2312 return (0); 2313 } 2314 2315 static void 2316 re_tx_task(arg, npending) 2317 void *arg; 2318 int npending; 2319 { 2320 struct ifnet *ifp; 2321 2322 ifp = arg; 2323 re_start(ifp); 2324 2325 return; 2326 } 2327 2328 /* 2329 * Main transmit routine for C+ and gigE NICs. 2330 */ 2331 static void 2332 re_start(ifp) 2333 struct ifnet *ifp; 2334 { 2335 struct rl_softc *sc; 2336 struct mbuf *m_head; 2337 int queued; 2338 2339 sc = ifp->if_softc; 2340 2341 RL_LOCK(sc); 2342 2343 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2344 IFF_DRV_RUNNING || sc->rl_link == 0) { 2345 RL_UNLOCK(sc); 2346 return; 2347 } 2348 2349 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2350 sc->rl_ldata.rl_tx_free > 1;) { 2351 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2352 if (m_head == NULL) 2353 break; 2354 2355 if (re_encap(sc, &m_head) != 0) { 2356 if (m_head == NULL) 2357 break; 2358 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2359 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2360 break; 2361 } 2362 2363 /* 2364 * If there's a BPF listener, bounce a copy of this frame 2365 * to him. 2366 */ 2367 ETHER_BPF_MTAP(ifp, m_head); 2368 2369 queued++; 2370 } 2371 2372 if (queued == 0) { 2373 #ifdef RE_TX_MODERATION 2374 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2375 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2376 #endif 2377 RL_UNLOCK(sc); 2378 return; 2379 } 2380 2381 /* Flush the TX descriptors */ 2382 2383 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2384 sc->rl_ldata.rl_tx_list_map, 2385 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2386 2387 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2388 2389 #ifdef RE_TX_MODERATION 2390 /* 2391 * Use the countdown timer for interrupt moderation. 2392 * 'TX done' interrupts are disabled. Instead, we reset the 2393 * countdown timer, which will begin counting until it hits 2394 * the value in the TIMERINT register, and then trigger an 2395 * interrupt. Each time we write to the TIMERCNT register, 2396 * the timer count is reset to 0. 2397 */ 2398 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2399 #endif 2400 2401 /* 2402 * Set a timeout in case the chip goes out to lunch. 2403 */ 2404 sc->rl_watchdog_timer = 5; 2405 2406 RL_UNLOCK(sc); 2407 2408 return; 2409 } 2410 2411 static void 2412 re_init(xsc) 2413 void *xsc; 2414 { 2415 struct rl_softc *sc = xsc; 2416 2417 RL_LOCK(sc); 2418 re_init_locked(sc); 2419 RL_UNLOCK(sc); 2420 } 2421 2422 static void 2423 re_init_locked(sc) 2424 struct rl_softc *sc; 2425 { 2426 struct ifnet *ifp = sc->rl_ifp; 2427 struct mii_data *mii; 2428 u_int32_t rxcfg = 0; 2429 uint16_t cfg; 2430 union { 2431 uint32_t align_dummy; 2432 u_char eaddr[ETHER_ADDR_LEN]; 2433 } eaddr; 2434 2435 RL_LOCK_ASSERT(sc); 2436 2437 mii = device_get_softc(sc->rl_miibus); 2438 2439 /* 2440 * Cancel pending I/O and free all RX/TX buffers. 2441 */ 2442 re_stop(sc); 2443 2444 /* 2445 * Enable C+ RX and TX mode, as well as VLAN stripping and 2446 * RX checksum offload. We must configure the C+ register 2447 * before all others. 2448 */ 2449 cfg = RL_CPLUSCMD_PCI_MRW; 2450 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2451 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 2452 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2453 cfg |= RL_CPLUSCMD_VLANSTRIP; 2454 CSR_WRITE_2(sc, RL_CPLUS_CMD, 2455 cfg | RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB); 2456 2457 /* 2458 * Init our MAC address. Even though the chipset 2459 * documentation doesn't mention it, we need to enter "Config 2460 * register write enable" mode to modify the ID registers. 2461 */ 2462 /* Copy MAC address on stack to align. */ 2463 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 2464 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2465 CSR_WRITE_4(sc, RL_IDR0, 2466 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 2467 CSR_WRITE_4(sc, RL_IDR4, 2468 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 2469 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2470 2471 /* 2472 * For C+ mode, initialize the RX descriptors and mbufs. 2473 */ 2474 re_rx_list_init(sc); 2475 re_tx_list_init(sc); 2476 2477 /* 2478 * Load the addresses of the RX and TX lists into the chip. 2479 */ 2480 2481 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2482 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2483 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2484 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2485 2486 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2487 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2488 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2489 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2490 2491 /* 2492 * Enable transmit and receive. 2493 */ 2494 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2495 2496 /* 2497 * Set the initial TX and RX configuration. 2498 */ 2499 if (sc->rl_testmode) { 2500 if (sc->rl_type == RL_8169) 2501 CSR_WRITE_4(sc, RL_TXCFG, 2502 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2503 else 2504 CSR_WRITE_4(sc, RL_TXCFG, 2505 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2506 } else 2507 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2508 2509 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2510 2511 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 2512 2513 /* Set the individual bit to receive frames for this host only. */ 2514 rxcfg = CSR_READ_4(sc, RL_RXCFG); 2515 rxcfg |= RL_RXCFG_RX_INDIV; 2516 2517 /* If we want promiscuous mode, set the allframes bit. */ 2518 if (ifp->if_flags & IFF_PROMISC) 2519 rxcfg |= RL_RXCFG_RX_ALLPHYS; 2520 else 2521 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 2522 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2523 2524 /* 2525 * Set capture broadcast bit to capture broadcast frames. 2526 */ 2527 if (ifp->if_flags & IFF_BROADCAST) 2528 rxcfg |= RL_RXCFG_RX_BROAD; 2529 else 2530 rxcfg &= ~RL_RXCFG_RX_BROAD; 2531 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2532 2533 /* 2534 * Program the multicast filter, if necessary. 2535 */ 2536 re_setmulti(sc); 2537 2538 #ifdef DEVICE_POLLING 2539 /* 2540 * Disable interrupts if we are polling. 2541 */ 2542 if (ifp->if_capenable & IFCAP_POLLING) 2543 CSR_WRITE_2(sc, RL_IMR, 0); 2544 else /* otherwise ... */ 2545 #endif 2546 2547 /* 2548 * Enable interrupts. 2549 */ 2550 if (sc->rl_testmode) 2551 CSR_WRITE_2(sc, RL_IMR, 0); 2552 else 2553 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2554 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 2555 2556 /* Set initial TX threshold */ 2557 sc->rl_txthresh = RL_TX_THRESH_INIT; 2558 2559 /* Start RX/TX process. */ 2560 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2561 #ifdef notdef 2562 /* Enable receiver and transmitter. */ 2563 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2564 #endif 2565 2566 #ifdef RE_TX_MODERATION 2567 /* 2568 * Initialize the timer interrupt register so that 2569 * a timer interrupt will be generated once the timer 2570 * reaches a certain number of ticks. The timer is 2571 * reloaded on each transmit. This gives us TX interrupt 2572 * moderation, which dramatically improves TX frame rate. 2573 */ 2574 if (sc->rl_type == RL_8169) 2575 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2576 else 2577 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2578 #endif 2579 2580 /* 2581 * For 8169 gigE NICs, set the max allowed RX packet 2582 * size so we can receive jumbo frames. 2583 */ 2584 if (sc->rl_type == RL_8169) 2585 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2586 2587 if (sc->rl_testmode) 2588 return; 2589 2590 mii_mediachg(mii); 2591 2592 CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD); 2593 2594 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2595 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2596 2597 sc->rl_link = 0; 2598 sc->rl_watchdog_timer = 0; 2599 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2600 } 2601 2602 /* 2603 * Set media options. 2604 */ 2605 static int 2606 re_ifmedia_upd(ifp) 2607 struct ifnet *ifp; 2608 { 2609 struct rl_softc *sc; 2610 struct mii_data *mii; 2611 2612 sc = ifp->if_softc; 2613 mii = device_get_softc(sc->rl_miibus); 2614 RL_LOCK(sc); 2615 mii_mediachg(mii); 2616 RL_UNLOCK(sc); 2617 2618 return (0); 2619 } 2620 2621 /* 2622 * Report current media status. 2623 */ 2624 static void 2625 re_ifmedia_sts(ifp, ifmr) 2626 struct ifnet *ifp; 2627 struct ifmediareq *ifmr; 2628 { 2629 struct rl_softc *sc; 2630 struct mii_data *mii; 2631 2632 sc = ifp->if_softc; 2633 mii = device_get_softc(sc->rl_miibus); 2634 2635 RL_LOCK(sc); 2636 mii_pollstat(mii); 2637 RL_UNLOCK(sc); 2638 ifmr->ifm_active = mii->mii_media_active; 2639 ifmr->ifm_status = mii->mii_media_status; 2640 } 2641 2642 static int 2643 re_ioctl(ifp, command, data) 2644 struct ifnet *ifp; 2645 u_long command; 2646 caddr_t data; 2647 { 2648 struct rl_softc *sc = ifp->if_softc; 2649 struct ifreq *ifr = (struct ifreq *) data; 2650 struct mii_data *mii; 2651 int error = 0; 2652 2653 switch (command) { 2654 case SIOCSIFMTU: 2655 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > RL_JUMBO_MTU) { 2656 error = EINVAL; 2657 break; 2658 } 2659 if (sc->rl_type == RL_8139CPLUS && 2660 ifr->ifr_mtu > RL_MAX_FRAMELEN) { 2661 error = EINVAL; 2662 break; 2663 } 2664 RL_LOCK(sc); 2665 if (ifp->if_mtu != ifr->ifr_mtu) 2666 ifp->if_mtu = ifr->ifr_mtu; 2667 RL_UNLOCK(sc); 2668 break; 2669 case SIOCSIFFLAGS: 2670 RL_LOCK(sc); 2671 if ((ifp->if_flags & IFF_UP) != 0) { 2672 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2673 if (((ifp->if_flags ^ sc->rl_if_flags) 2674 & IFF_PROMISC) != 0) 2675 re_setmulti(sc); 2676 } else 2677 re_init_locked(sc); 2678 } else { 2679 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2680 re_stop(sc); 2681 } 2682 sc->rl_if_flags = ifp->if_flags; 2683 RL_UNLOCK(sc); 2684 break; 2685 case SIOCADDMULTI: 2686 case SIOCDELMULTI: 2687 RL_LOCK(sc); 2688 re_setmulti(sc); 2689 RL_UNLOCK(sc); 2690 break; 2691 case SIOCGIFMEDIA: 2692 case SIOCSIFMEDIA: 2693 mii = device_get_softc(sc->rl_miibus); 2694 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2695 break; 2696 case SIOCSIFCAP: 2697 { 2698 int mask, reinit; 2699 2700 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2701 reinit = 0; 2702 #ifdef DEVICE_POLLING 2703 if (mask & IFCAP_POLLING) { 2704 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2705 error = ether_poll_register(re_poll, ifp); 2706 if (error) 2707 return(error); 2708 RL_LOCK(sc); 2709 /* Disable interrupts */ 2710 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2711 ifp->if_capenable |= IFCAP_POLLING; 2712 RL_UNLOCK(sc); 2713 } else { 2714 error = ether_poll_deregister(ifp); 2715 /* Enable interrupts. */ 2716 RL_LOCK(sc); 2717 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2718 ifp->if_capenable &= ~IFCAP_POLLING; 2719 RL_UNLOCK(sc); 2720 } 2721 } 2722 #endif /* DEVICE_POLLING */ 2723 if (mask & IFCAP_HWCSUM) { 2724 ifp->if_capenable ^= IFCAP_HWCSUM; 2725 if (ifp->if_capenable & IFCAP_TXCSUM) 2726 ifp->if_hwassist |= RE_CSUM_FEATURES; 2727 else 2728 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 2729 reinit = 1; 2730 } 2731 if (mask & IFCAP_VLAN_HWTAGGING) { 2732 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2733 reinit = 1; 2734 } 2735 if (mask & IFCAP_TSO4) { 2736 ifp->if_capenable ^= IFCAP_TSO4; 2737 if ((IFCAP_TSO4 & ifp->if_capenable) && 2738 (IFCAP_TSO4 & ifp->if_capabilities)) 2739 ifp->if_hwassist |= CSUM_TSO; 2740 else 2741 ifp->if_hwassist &= ~CSUM_TSO; 2742 } 2743 if ((mask & IFCAP_WOL) != 0 && 2744 (ifp->if_capabilities & IFCAP_WOL) != 0) { 2745 if ((mask & IFCAP_WOL_UCAST) != 0) 2746 ifp->if_capenable ^= IFCAP_WOL_UCAST; 2747 if ((mask & IFCAP_WOL_MCAST) != 0) 2748 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2749 if ((mask & IFCAP_WOL_MAGIC) != 0) 2750 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2751 } 2752 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) 2753 re_init(sc); 2754 VLAN_CAPABILITIES(ifp); 2755 } 2756 break; 2757 default: 2758 error = ether_ioctl(ifp, command, data); 2759 break; 2760 } 2761 2762 return (error); 2763 } 2764 2765 static void 2766 re_watchdog(sc) 2767 struct rl_softc *sc; 2768 { 2769 2770 RL_LOCK_ASSERT(sc); 2771 2772 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 2773 return; 2774 2775 device_printf(sc->rl_dev, "watchdog timeout\n"); 2776 sc->rl_ifp->if_oerrors++; 2777 2778 re_txeof(sc); 2779 re_rxeof(sc); 2780 re_init_locked(sc); 2781 } 2782 2783 /* 2784 * Stop the adapter and free any mbufs allocated to the 2785 * RX and TX lists. 2786 */ 2787 static void 2788 re_stop(sc) 2789 struct rl_softc *sc; 2790 { 2791 register int i; 2792 struct ifnet *ifp; 2793 struct rl_txdesc *txd; 2794 struct rl_rxdesc *rxd; 2795 2796 RL_LOCK_ASSERT(sc); 2797 2798 ifp = sc->rl_ifp; 2799 2800 sc->rl_watchdog_timer = 0; 2801 callout_stop(&sc->rl_stat_callout); 2802 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2803 2804 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2805 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2806 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 2807 2808 if (sc->rl_head != NULL) { 2809 m_freem(sc->rl_head); 2810 sc->rl_head = sc->rl_tail = NULL; 2811 } 2812 2813 /* Free the TX list buffers. */ 2814 2815 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 2816 txd = &sc->rl_ldata.rl_tx_desc[i]; 2817 if (txd->tx_m != NULL) { 2818 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2819 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2820 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2821 txd->tx_dmamap); 2822 m_freem(txd->tx_m); 2823 txd->tx_m = NULL; 2824 } 2825 } 2826 2827 /* Free the RX list buffers. */ 2828 2829 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2830 rxd = &sc->rl_ldata.rl_rx_desc[i]; 2831 if (rxd->rx_m != NULL) { 2832 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2833 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2834 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 2835 rxd->rx_dmamap); 2836 m_freem(rxd->rx_m); 2837 rxd->rx_m = NULL; 2838 } 2839 } 2840 } 2841 2842 /* 2843 * Device suspend routine. Stop the interface and save some PCI 2844 * settings in case the BIOS doesn't restore them properly on 2845 * resume. 2846 */ 2847 static int 2848 re_suspend(dev) 2849 device_t dev; 2850 { 2851 struct rl_softc *sc; 2852 2853 sc = device_get_softc(dev); 2854 2855 RL_LOCK(sc); 2856 re_stop(sc); 2857 re_setwol(sc); 2858 sc->suspended = 1; 2859 RL_UNLOCK(sc); 2860 2861 return (0); 2862 } 2863 2864 /* 2865 * Device resume routine. Restore some PCI settings in case the BIOS 2866 * doesn't, re-enable busmastering, and restart the interface if 2867 * appropriate. 2868 */ 2869 static int 2870 re_resume(dev) 2871 device_t dev; 2872 { 2873 struct rl_softc *sc; 2874 struct ifnet *ifp; 2875 2876 sc = device_get_softc(dev); 2877 2878 RL_LOCK(sc); 2879 2880 ifp = sc->rl_ifp; 2881 2882 /* reinitialize interface if necessary */ 2883 if (ifp->if_flags & IFF_UP) 2884 re_init_locked(sc); 2885 2886 /* 2887 * Clear WOL matching such that normal Rx filtering 2888 * wouldn't interfere with WOL patterns. 2889 */ 2890 re_clrwol(sc); 2891 sc->suspended = 0; 2892 RL_UNLOCK(sc); 2893 2894 return (0); 2895 } 2896 2897 /* 2898 * Stop all chip I/O so that the kernel's probe routines don't 2899 * get confused by errant DMAs when rebooting. 2900 */ 2901 static int 2902 re_shutdown(dev) 2903 device_t dev; 2904 { 2905 struct rl_softc *sc; 2906 2907 sc = device_get_softc(dev); 2908 2909 RL_LOCK(sc); 2910 re_stop(sc); 2911 /* 2912 * Mark interface as down since otherwise we will panic if 2913 * interrupt comes in later on, which can happen in some 2914 * cases. 2915 */ 2916 sc->rl_ifp->if_flags &= ~IFF_UP; 2917 re_setwol(sc); 2918 RL_UNLOCK(sc); 2919 2920 return (0); 2921 } 2922 2923 static void 2924 re_setwol(sc) 2925 struct rl_softc *sc; 2926 { 2927 struct ifnet *ifp; 2928 int pmc; 2929 uint16_t pmstat; 2930 uint8_t v; 2931 2932 RL_LOCK_ASSERT(sc); 2933 2934 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 2935 return; 2936 2937 ifp = sc->rl_ifp; 2938 /* Enable config register write. */ 2939 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 2940 2941 /* Enable PME. */ 2942 v = CSR_READ_1(sc, RL_CFG1); 2943 v &= ~RL_CFG1_PME; 2944 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2945 v |= RL_CFG1_PME; 2946 CSR_WRITE_1(sc, RL_CFG1, v); 2947 2948 v = CSR_READ_1(sc, RL_CFG3); 2949 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 2950 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2951 v |= RL_CFG3_WOL_MAGIC; 2952 CSR_WRITE_1(sc, RL_CFG3, v); 2953 2954 /* Config register write done. */ 2955 CSR_WRITE_1(sc, RL_EECMD, 0); 2956 2957 v = CSR_READ_1(sc, RL_CFG5); 2958 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 2959 v &= ~RL_CFG5_WOL_LANWAKE; 2960 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 2961 v |= RL_CFG5_WOL_UCAST; 2962 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 2963 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 2964 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2965 v |= RL_CFG5_WOL_LANWAKE; 2966 CSR_WRITE_1(sc, RL_CFG5, v); 2967 2968 /* 2969 * It seems that hardware resets its link speed to 100Mbps in 2970 * power down mode so switching to 100Mbps in driver is not 2971 * needed. 2972 */ 2973 2974 /* Request PME if WOL is requested. */ 2975 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 2976 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2977 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2978 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2979 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 2980 } 2981 2982 static void 2983 re_clrwol(sc) 2984 struct rl_softc *sc; 2985 { 2986 int pmc; 2987 uint8_t v; 2988 2989 RL_LOCK_ASSERT(sc); 2990 2991 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 2992 return; 2993 2994 /* Enable config register write. */ 2995 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 2996 2997 v = CSR_READ_1(sc, RL_CFG3); 2998 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 2999 CSR_WRITE_1(sc, RL_CFG3, v); 3000 3001 /* Config register write done. */ 3002 CSR_WRITE_1(sc, RL_EECMD, 0); 3003 3004 v = CSR_READ_1(sc, RL_CFG5); 3005 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3006 v &= ~RL_CFG5_WOL_LANWAKE; 3007 CSR_WRITE_1(sc, RL_CFG5, v); 3008 } 3009