1 /*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44 /* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111 #ifdef HAVE_KERNEL_OPTION_HEADERS 112 #include "opt_device_polling.h" 113 #endif 114 115 #include <sys/param.h> 116 #include <sys/endian.h> 117 #include <sys/systm.h> 118 #include <sys/sockio.h> 119 #include <sys/mbuf.h> 120 #include <sys/malloc.h> 121 #include <sys/module.h> 122 #include <sys/kernel.h> 123 #include <sys/socket.h> 124 #include <sys/lock.h> 125 #include <sys/mutex.h> 126 #include <sys/sysctl.h> 127 #include <sys/taskqueue.h> 128 129 #include <net/if.h> 130 #include <net/if_arp.h> 131 #include <net/ethernet.h> 132 #include <net/if_dl.h> 133 #include <net/if_media.h> 134 #include <net/if_types.h> 135 #include <net/if_vlan_var.h> 136 137 #include <net/bpf.h> 138 139 #include <machine/bus.h> 140 #include <machine/resource.h> 141 #include <sys/bus.h> 142 #include <sys/rman.h> 143 144 #include <dev/mii/mii.h> 145 #include <dev/mii/miivar.h> 146 147 #include <dev/pci/pcireg.h> 148 #include <dev/pci/pcivar.h> 149 150 #include <pci/if_rlreg.h> 151 152 MODULE_DEPEND(re, pci, 1, 1, 1); 153 MODULE_DEPEND(re, ether, 1, 1, 1); 154 MODULE_DEPEND(re, miibus, 1, 1, 1); 155 156 /* "device miibus" required. See GENERIC if you get errors here. */ 157 #include "miibus_if.h" 158 159 /* Tunables. */ 160 static int intr_filter = 0; 161 TUNABLE_INT("hw.re.intr_filter", &intr_filter); 162 static int msi_disable = 0; 163 TUNABLE_INT("hw.re.msi_disable", &msi_disable); 164 static int msix_disable = 0; 165 TUNABLE_INT("hw.re.msix_disable", &msix_disable); 166 static int prefer_iomap = 0; 167 TUNABLE_INT("hw.re.prefer_iomap", &prefer_iomap); 168 169 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 170 171 /* 172 * Various supported device vendors/types and their names. 173 */ 174 static const struct rl_type const re_devs[] = { 175 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0, 176 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 177 { DLINK_VENDORID, DLINK_DEVICEID_530T_REVC, 0, 178 "D-Link DGE-530(T) Gigabit Ethernet Adapter" }, 179 { RT_VENDORID, RT_DEVICEID_8139, 0, 180 "RealTek 8139C+ 10/100BaseTX" }, 181 { RT_VENDORID, RT_DEVICEID_8101E, 0, 182 "RealTek 810xE PCIe 10/100baseTX" }, 183 { RT_VENDORID, RT_DEVICEID_8168, 0, 184 "RealTek 8168/8111 B/C/CP/D/DP/E/F PCIe Gigabit Ethernet" }, 185 { RT_VENDORID, RT_DEVICEID_8169, 0, 186 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" }, 187 { RT_VENDORID, RT_DEVICEID_8169SC, 0, 188 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 189 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0, 190 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 191 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0, 192 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 193 { USR_VENDORID, USR_DEVICEID_997902, 0, 194 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 195 }; 196 197 static const struct rl_hwrev const re_hwrevs[] = { 198 { RL_HWREV_8139, RL_8139, "", RL_MTU }, 199 { RL_HWREV_8139A, RL_8139, "A", RL_MTU }, 200 { RL_HWREV_8139AG, RL_8139, "A-G", RL_MTU }, 201 { RL_HWREV_8139B, RL_8139, "B", RL_MTU }, 202 { RL_HWREV_8130, RL_8139, "8130", RL_MTU }, 203 { RL_HWREV_8139C, RL_8139, "C", RL_MTU }, 204 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C", RL_MTU }, 205 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+", RL_MTU }, 206 { RL_HWREV_8168B_SPIN1, RL_8169, "8168", RL_JUMBO_MTU }, 207 { RL_HWREV_8169, RL_8169, "8169", RL_JUMBO_MTU }, 208 { RL_HWREV_8169S, RL_8169, "8169S", RL_JUMBO_MTU }, 209 { RL_HWREV_8110S, RL_8169, "8110S", RL_JUMBO_MTU }, 210 { RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB", RL_JUMBO_MTU }, 211 { RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU }, 212 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL", RL_JUMBO_MTU }, 213 { RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU }, 214 { RL_HWREV_8100, RL_8139, "8100", RL_MTU }, 215 { RL_HWREV_8101, RL_8139, "8101", RL_MTU }, 216 { RL_HWREV_8100E, RL_8169, "8100E", RL_MTU }, 217 { RL_HWREV_8101E, RL_8169, "8101E", RL_MTU }, 218 { RL_HWREV_8102E, RL_8169, "8102E", RL_MTU }, 219 { RL_HWREV_8102EL, RL_8169, "8102EL", RL_MTU }, 220 { RL_HWREV_8102EL_SPIN1, RL_8169, "8102EL", RL_MTU }, 221 { RL_HWREV_8103E, RL_8169, "8103E", RL_MTU }, 222 { RL_HWREV_8401E, RL_8169, "8401E", RL_MTU }, 223 { RL_HWREV_8402, RL_8169, "8402", RL_MTU }, 224 { RL_HWREV_8105E, RL_8169, "8105E", RL_MTU }, 225 { RL_HWREV_8105E_SPIN1, RL_8169, "8105E", RL_MTU }, 226 { RL_HWREV_8168B_SPIN2, RL_8169, "8168", RL_JUMBO_MTU }, 227 { RL_HWREV_8168B_SPIN3, RL_8169, "8168", RL_JUMBO_MTU }, 228 { RL_HWREV_8168C, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K }, 229 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K }, 230 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP", RL_JUMBO_MTU_6K }, 231 { RL_HWREV_8168D, RL_8169, "8168D/8111D", RL_JUMBO_MTU_9K }, 232 { RL_HWREV_8168DP, RL_8169, "8168DP/8111DP", RL_JUMBO_MTU_9K }, 233 { RL_HWREV_8168E, RL_8169, "8168E/8111E", RL_JUMBO_MTU_9K}, 234 { RL_HWREV_8168E_VL, RL_8169, "8168E/8111E-VL", RL_JUMBO_MTU_6K}, 235 { RL_HWREV_8168F, RL_8169, "8168F/8111F", RL_JUMBO_MTU_9K}, 236 { RL_HWREV_8411, RL_8169, "8411", RL_JUMBO_MTU_9K}, 237 { 0, 0, NULL, 0 } 238 }; 239 240 static int re_probe (device_t); 241 static int re_attach (device_t); 242 static int re_detach (device_t); 243 244 static int re_encap (struct rl_softc *, struct mbuf **); 245 246 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 247 static int re_allocmem (device_t, struct rl_softc *); 248 static __inline void re_discard_rxbuf 249 (struct rl_softc *, int); 250 static int re_newbuf (struct rl_softc *, int); 251 static int re_jumbo_newbuf (struct rl_softc *, int); 252 static int re_rx_list_init (struct rl_softc *); 253 static int re_jrx_list_init (struct rl_softc *); 254 static int re_tx_list_init (struct rl_softc *); 255 #ifdef RE_FIXUP_RX 256 static __inline void re_fixup_rx 257 (struct mbuf *); 258 #endif 259 static int re_rxeof (struct rl_softc *, int *); 260 static void re_txeof (struct rl_softc *); 261 #ifdef DEVICE_POLLING 262 static int re_poll (struct ifnet *, enum poll_cmd, int); 263 static int re_poll_locked (struct ifnet *, enum poll_cmd, int); 264 #endif 265 static int re_intr (void *); 266 static void re_intr_msi (void *); 267 static void re_tick (void *); 268 static void re_int_task (void *, int); 269 static void re_start (struct ifnet *); 270 static void re_start_locked (struct ifnet *); 271 static int re_ioctl (struct ifnet *, u_long, caddr_t); 272 static void re_init (void *); 273 static void re_init_locked (struct rl_softc *); 274 static void re_stop (struct rl_softc *); 275 static void re_watchdog (struct rl_softc *); 276 static int re_suspend (device_t); 277 static int re_resume (device_t); 278 static int re_shutdown (device_t); 279 static int re_ifmedia_upd (struct ifnet *); 280 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 281 282 static void re_eeprom_putbyte (struct rl_softc *, int); 283 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 284 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 285 static int re_gmii_readreg (device_t, int, int); 286 static int re_gmii_writereg (device_t, int, int, int); 287 288 static int re_miibus_readreg (device_t, int, int); 289 static int re_miibus_writereg (device_t, int, int, int); 290 static void re_miibus_statchg (device_t); 291 292 static void re_set_jumbo (struct rl_softc *, int); 293 static void re_set_rxmode (struct rl_softc *); 294 static void re_reset (struct rl_softc *); 295 static void re_setwol (struct rl_softc *); 296 static void re_clrwol (struct rl_softc *); 297 static void re_set_linkspeed (struct rl_softc *); 298 299 #ifdef DEV_NETMAP /* see ixgbe.c for details */ 300 #include <dev/netmap/if_re_netmap.h> 301 #endif /* !DEV_NETMAP */ 302 303 #ifdef RE_DIAG 304 static int re_diag (struct rl_softc *); 305 #endif 306 307 static void re_add_sysctls (struct rl_softc *); 308 static int re_sysctl_stats (SYSCTL_HANDLER_ARGS); 309 static int sysctl_int_range (SYSCTL_HANDLER_ARGS, int, int); 310 static int sysctl_hw_re_int_mod (SYSCTL_HANDLER_ARGS); 311 312 static device_method_t re_methods[] = { 313 /* Device interface */ 314 DEVMETHOD(device_probe, re_probe), 315 DEVMETHOD(device_attach, re_attach), 316 DEVMETHOD(device_detach, re_detach), 317 DEVMETHOD(device_suspend, re_suspend), 318 DEVMETHOD(device_resume, re_resume), 319 DEVMETHOD(device_shutdown, re_shutdown), 320 321 /* MII interface */ 322 DEVMETHOD(miibus_readreg, re_miibus_readreg), 323 DEVMETHOD(miibus_writereg, re_miibus_writereg), 324 DEVMETHOD(miibus_statchg, re_miibus_statchg), 325 326 DEVMETHOD_END 327 }; 328 329 static driver_t re_driver = { 330 "re", 331 re_methods, 332 sizeof(struct rl_softc) 333 }; 334 335 static devclass_t re_devclass; 336 337 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 338 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 339 340 #define EE_SET(x) \ 341 CSR_WRITE_1(sc, RL_EECMD, \ 342 CSR_READ_1(sc, RL_EECMD) | x) 343 344 #define EE_CLR(x) \ 345 CSR_WRITE_1(sc, RL_EECMD, \ 346 CSR_READ_1(sc, RL_EECMD) & ~x) 347 348 /* 349 * Send a read command and address to the EEPROM, check for ACK. 350 */ 351 static void 352 re_eeprom_putbyte(struct rl_softc *sc, int addr) 353 { 354 int d, i; 355 356 d = addr | (RL_9346_READ << sc->rl_eewidth); 357 358 /* 359 * Feed in each bit and strobe the clock. 360 */ 361 362 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 363 if (d & i) { 364 EE_SET(RL_EE_DATAIN); 365 } else { 366 EE_CLR(RL_EE_DATAIN); 367 } 368 DELAY(100); 369 EE_SET(RL_EE_CLK); 370 DELAY(150); 371 EE_CLR(RL_EE_CLK); 372 DELAY(100); 373 } 374 } 375 376 /* 377 * Read a word of data stored in the EEPROM at address 'addr.' 378 */ 379 static void 380 re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest) 381 { 382 int i; 383 u_int16_t word = 0; 384 385 /* 386 * Send address of word we want to read. 387 */ 388 re_eeprom_putbyte(sc, addr); 389 390 /* 391 * Start reading bits from EEPROM. 392 */ 393 for (i = 0x8000; i; i >>= 1) { 394 EE_SET(RL_EE_CLK); 395 DELAY(100); 396 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 397 word |= i; 398 EE_CLR(RL_EE_CLK); 399 DELAY(100); 400 } 401 402 *dest = word; 403 } 404 405 /* 406 * Read a sequence of words from the EEPROM. 407 */ 408 static void 409 re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt) 410 { 411 int i; 412 u_int16_t word = 0, *ptr; 413 414 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 415 416 DELAY(100); 417 418 for (i = 0; i < cnt; i++) { 419 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 420 re_eeprom_getword(sc, off + i, &word); 421 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 422 ptr = (u_int16_t *)(dest + (i * 2)); 423 *ptr = word; 424 } 425 426 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 427 } 428 429 static int 430 re_gmii_readreg(device_t dev, int phy, int reg) 431 { 432 struct rl_softc *sc; 433 u_int32_t rval; 434 int i; 435 436 sc = device_get_softc(dev); 437 438 /* Let the rgephy driver read the GMEDIASTAT register */ 439 440 if (reg == RL_GMEDIASTAT) { 441 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 442 return (rval); 443 } 444 445 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 446 447 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 448 rval = CSR_READ_4(sc, RL_PHYAR); 449 if (rval & RL_PHYAR_BUSY) 450 break; 451 DELAY(25); 452 } 453 454 if (i == RL_PHY_TIMEOUT) { 455 device_printf(sc->rl_dev, "PHY read failed\n"); 456 return (0); 457 } 458 459 /* 460 * Controller requires a 20us delay to process next MDIO request. 461 */ 462 DELAY(20); 463 464 return (rval & RL_PHYAR_PHYDATA); 465 } 466 467 static int 468 re_gmii_writereg(device_t dev, int phy, int reg, int data) 469 { 470 struct rl_softc *sc; 471 u_int32_t rval; 472 int i; 473 474 sc = device_get_softc(dev); 475 476 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 477 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 478 479 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 480 rval = CSR_READ_4(sc, RL_PHYAR); 481 if (!(rval & RL_PHYAR_BUSY)) 482 break; 483 DELAY(25); 484 } 485 486 if (i == RL_PHY_TIMEOUT) { 487 device_printf(sc->rl_dev, "PHY write failed\n"); 488 return (0); 489 } 490 491 /* 492 * Controller requires a 20us delay to process next MDIO request. 493 */ 494 DELAY(20); 495 496 return (0); 497 } 498 499 static int 500 re_miibus_readreg(device_t dev, int phy, int reg) 501 { 502 struct rl_softc *sc; 503 u_int16_t rval = 0; 504 u_int16_t re8139_reg = 0; 505 506 sc = device_get_softc(dev); 507 508 if (sc->rl_type == RL_8169) { 509 rval = re_gmii_readreg(dev, phy, reg); 510 return (rval); 511 } 512 513 switch (reg) { 514 case MII_BMCR: 515 re8139_reg = RL_BMCR; 516 break; 517 case MII_BMSR: 518 re8139_reg = RL_BMSR; 519 break; 520 case MII_ANAR: 521 re8139_reg = RL_ANAR; 522 break; 523 case MII_ANER: 524 re8139_reg = RL_ANER; 525 break; 526 case MII_ANLPAR: 527 re8139_reg = RL_LPAR; 528 break; 529 case MII_PHYIDR1: 530 case MII_PHYIDR2: 531 return (0); 532 /* 533 * Allow the rlphy driver to read the media status 534 * register. If we have a link partner which does not 535 * support NWAY, this is the register which will tell 536 * us the results of parallel detection. 537 */ 538 case RL_MEDIASTAT: 539 rval = CSR_READ_1(sc, RL_MEDIASTAT); 540 return (rval); 541 default: 542 device_printf(sc->rl_dev, "bad phy register\n"); 543 return (0); 544 } 545 rval = CSR_READ_2(sc, re8139_reg); 546 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 547 /* 8139C+ has different bit layout. */ 548 rval &= ~(BMCR_LOOP | BMCR_ISO); 549 } 550 return (rval); 551 } 552 553 static int 554 re_miibus_writereg(device_t dev, int phy, int reg, int data) 555 { 556 struct rl_softc *sc; 557 u_int16_t re8139_reg = 0; 558 int rval = 0; 559 560 sc = device_get_softc(dev); 561 562 if (sc->rl_type == RL_8169) { 563 rval = re_gmii_writereg(dev, phy, reg, data); 564 return (rval); 565 } 566 567 switch (reg) { 568 case MII_BMCR: 569 re8139_reg = RL_BMCR; 570 if (sc->rl_type == RL_8139CPLUS) { 571 /* 8139C+ has different bit layout. */ 572 data &= ~(BMCR_LOOP | BMCR_ISO); 573 } 574 break; 575 case MII_BMSR: 576 re8139_reg = RL_BMSR; 577 break; 578 case MII_ANAR: 579 re8139_reg = RL_ANAR; 580 break; 581 case MII_ANER: 582 re8139_reg = RL_ANER; 583 break; 584 case MII_ANLPAR: 585 re8139_reg = RL_LPAR; 586 break; 587 case MII_PHYIDR1: 588 case MII_PHYIDR2: 589 return (0); 590 break; 591 default: 592 device_printf(sc->rl_dev, "bad phy register\n"); 593 return (0); 594 } 595 CSR_WRITE_2(sc, re8139_reg, data); 596 return (0); 597 } 598 599 static void 600 re_miibus_statchg(device_t dev) 601 { 602 struct rl_softc *sc; 603 struct ifnet *ifp; 604 struct mii_data *mii; 605 606 sc = device_get_softc(dev); 607 mii = device_get_softc(sc->rl_miibus); 608 ifp = sc->rl_ifp; 609 if (mii == NULL || ifp == NULL || 610 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 611 return; 612 613 sc->rl_flags &= ~RL_FLAG_LINK; 614 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 615 (IFM_ACTIVE | IFM_AVALID)) { 616 switch (IFM_SUBTYPE(mii->mii_media_active)) { 617 case IFM_10_T: 618 case IFM_100_TX: 619 sc->rl_flags |= RL_FLAG_LINK; 620 break; 621 case IFM_1000_T: 622 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0) 623 break; 624 sc->rl_flags |= RL_FLAG_LINK; 625 break; 626 default: 627 break; 628 } 629 } 630 /* 631 * RealTek controllers does not provide any interface to 632 * Tx/Rx MACs for resolved speed, duplex and flow-control 633 * parameters. 634 */ 635 } 636 637 /* 638 * Set the RX configuration and 64-bit multicast hash filter. 639 */ 640 static void 641 re_set_rxmode(struct rl_softc *sc) 642 { 643 struct ifnet *ifp; 644 struct ifmultiaddr *ifma; 645 uint32_t hashes[2] = { 0, 0 }; 646 uint32_t h, rxfilt; 647 648 RL_LOCK_ASSERT(sc); 649 650 ifp = sc->rl_ifp; 651 652 rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD; 653 654 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 655 if (ifp->if_flags & IFF_PROMISC) 656 rxfilt |= RL_RXCFG_RX_ALLPHYS; 657 /* 658 * Unlike other hardwares, we have to explicitly set 659 * RL_RXCFG_RX_MULTI to receive multicast frames in 660 * promiscuous mode. 661 */ 662 rxfilt |= RL_RXCFG_RX_MULTI; 663 hashes[0] = hashes[1] = 0xffffffff; 664 goto done; 665 } 666 667 if_maddr_rlock(ifp); 668 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 669 if (ifma->ifma_addr->sa_family != AF_LINK) 670 continue; 671 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 672 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 673 if (h < 32) 674 hashes[0] |= (1 << h); 675 else 676 hashes[1] |= (1 << (h - 32)); 677 } 678 if_maddr_runlock(ifp); 679 680 if (hashes[0] != 0 || hashes[1] != 0) { 681 /* 682 * For some unfathomable reason, RealTek decided to 683 * reverse the order of the multicast hash registers 684 * in the PCI Express parts. This means we have to 685 * write the hash pattern in reverse order for those 686 * devices. 687 */ 688 if ((sc->rl_flags & RL_FLAG_PCIE) != 0) { 689 h = bswap32(hashes[0]); 690 hashes[0] = bswap32(hashes[1]); 691 hashes[1] = h; 692 } 693 rxfilt |= RL_RXCFG_RX_MULTI; 694 } 695 696 done: 697 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 698 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 699 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 700 } 701 702 static void 703 re_reset(struct rl_softc *sc) 704 { 705 int i; 706 707 RL_LOCK_ASSERT(sc); 708 709 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 710 711 for (i = 0; i < RL_TIMEOUT; i++) { 712 DELAY(10); 713 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 714 break; 715 } 716 if (i == RL_TIMEOUT) 717 device_printf(sc->rl_dev, "reset never completed!\n"); 718 719 if ((sc->rl_flags & RL_FLAG_MACRESET) != 0) 720 CSR_WRITE_1(sc, 0x82, 1); 721 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169S) 722 re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0); 723 } 724 725 #ifdef RE_DIAG 726 727 /* 728 * The following routine is designed to test for a defect on some 729 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 730 * lines connected to the bus, however for a 32-bit only card, they 731 * should be pulled high. The result of this defect is that the 732 * NIC will not work right if you plug it into a 64-bit slot: DMA 733 * operations will be done with 64-bit transfers, which will fail 734 * because the 64-bit data lines aren't connected. 735 * 736 * There's no way to work around this (short of talking a soldering 737 * iron to the board), however we can detect it. The method we use 738 * here is to put the NIC into digital loopback mode, set the receiver 739 * to promiscuous mode, and then try to send a frame. We then compare 740 * the frame data we sent to what was received. If the data matches, 741 * then the NIC is working correctly, otherwise we know the user has 742 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 743 * slot. In the latter case, there's no way the NIC can work correctly, 744 * so we print out a message on the console and abort the device attach. 745 */ 746 747 static int 748 re_diag(struct rl_softc *sc) 749 { 750 struct ifnet *ifp = sc->rl_ifp; 751 struct mbuf *m0; 752 struct ether_header *eh; 753 struct rl_desc *cur_rx; 754 u_int16_t status; 755 u_int32_t rxstat; 756 int total_len, i, error = 0, phyaddr; 757 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 758 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 759 760 /* Allocate a single mbuf */ 761 MGETHDR(m0, M_DONTWAIT, MT_DATA); 762 if (m0 == NULL) 763 return (ENOBUFS); 764 765 RL_LOCK(sc); 766 767 /* 768 * Initialize the NIC in test mode. This sets the chip up 769 * so that it can send and receive frames, but performs the 770 * following special functions: 771 * - Puts receiver in promiscuous mode 772 * - Enables digital loopback mode 773 * - Leaves interrupts turned off 774 */ 775 776 ifp->if_flags |= IFF_PROMISC; 777 sc->rl_testmode = 1; 778 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 779 re_init_locked(sc); 780 sc->rl_flags |= RL_FLAG_LINK; 781 if (sc->rl_type == RL_8169) 782 phyaddr = 1; 783 else 784 phyaddr = 0; 785 786 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 787 for (i = 0; i < RL_TIMEOUT; i++) { 788 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 789 if (!(status & BMCR_RESET)) 790 break; 791 } 792 793 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 794 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 795 796 DELAY(100000); 797 798 /* Put some data in the mbuf */ 799 800 eh = mtod(m0, struct ether_header *); 801 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 802 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 803 eh->ether_type = htons(ETHERTYPE_IP); 804 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 805 806 /* 807 * Queue the packet, start transmission. 808 * Note: IF_HANDOFF() ultimately calls re_start() for us. 809 */ 810 811 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 812 RL_UNLOCK(sc); 813 /* XXX: re_diag must not be called when in ALTQ mode */ 814 IF_HANDOFF(&ifp->if_snd, m0, ifp); 815 RL_LOCK(sc); 816 m0 = NULL; 817 818 /* Wait for it to propagate through the chip */ 819 820 DELAY(100000); 821 for (i = 0; i < RL_TIMEOUT; i++) { 822 status = CSR_READ_2(sc, RL_ISR); 823 CSR_WRITE_2(sc, RL_ISR, status); 824 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 825 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 826 break; 827 DELAY(10); 828 } 829 830 if (i == RL_TIMEOUT) { 831 device_printf(sc->rl_dev, 832 "diagnostic failed, failed to receive packet in" 833 " loopback mode\n"); 834 error = EIO; 835 goto done; 836 } 837 838 /* 839 * The packet should have been dumped into the first 840 * entry in the RX DMA ring. Grab it from there. 841 */ 842 843 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 844 sc->rl_ldata.rl_rx_list_map, 845 BUS_DMASYNC_POSTREAD); 846 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 847 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 848 BUS_DMASYNC_POSTREAD); 849 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 850 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 851 852 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 853 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 854 eh = mtod(m0, struct ether_header *); 855 856 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 857 total_len = RL_RXBYTES(cur_rx); 858 rxstat = le32toh(cur_rx->rl_cmdstat); 859 860 if (total_len != ETHER_MIN_LEN) { 861 device_printf(sc->rl_dev, 862 "diagnostic failed, received short packet\n"); 863 error = EIO; 864 goto done; 865 } 866 867 /* Test that the received packet data matches what we sent. */ 868 869 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 870 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 871 ntohs(eh->ether_type) != ETHERTYPE_IP) { 872 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 873 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 874 dst, ":", src, ":", ETHERTYPE_IP); 875 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 876 eh->ether_dhost, ":", eh->ether_shost, ":", 877 ntohs(eh->ether_type)); 878 device_printf(sc->rl_dev, "You may have a defective 32-bit " 879 "NIC plugged into a 64-bit PCI slot.\n"); 880 device_printf(sc->rl_dev, "Please re-install the NIC in a " 881 "32-bit slot for proper operation.\n"); 882 device_printf(sc->rl_dev, "Read the re(4) man page for more " 883 "details.\n"); 884 error = EIO; 885 } 886 887 done: 888 /* Turn interface off, release resources */ 889 890 sc->rl_testmode = 0; 891 sc->rl_flags &= ~RL_FLAG_LINK; 892 ifp->if_flags &= ~IFF_PROMISC; 893 re_stop(sc); 894 if (m0 != NULL) 895 m_freem(m0); 896 897 RL_UNLOCK(sc); 898 899 return (error); 900 } 901 902 #endif 903 904 /* 905 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 906 * IDs against our list and return a device name if we find a match. 907 */ 908 static int 909 re_probe(device_t dev) 910 { 911 const struct rl_type *t; 912 uint16_t devid, vendor; 913 uint16_t revid, sdevid; 914 int i; 915 916 vendor = pci_get_vendor(dev); 917 devid = pci_get_device(dev); 918 revid = pci_get_revid(dev); 919 sdevid = pci_get_subdevice(dev); 920 921 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 922 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 923 /* 924 * Only attach to rev. 3 of the Linksys EG1032 adapter. 925 * Rev. 2 is supported by sk(4). 926 */ 927 return (ENXIO); 928 } 929 } 930 931 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 932 if (revid != 0x20) { 933 /* 8139, let rl(4) take care of this device. */ 934 return (ENXIO); 935 } 936 } 937 938 t = re_devs; 939 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) { 940 if (vendor == t->rl_vid && devid == t->rl_did) { 941 device_set_desc(dev, t->rl_name); 942 return (BUS_PROBE_DEFAULT); 943 } 944 } 945 946 return (ENXIO); 947 } 948 949 /* 950 * Map a single buffer address. 951 */ 952 953 static void 954 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 955 { 956 bus_addr_t *addr; 957 958 if (error) 959 return; 960 961 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 962 addr = arg; 963 *addr = segs->ds_addr; 964 } 965 966 static int 967 re_allocmem(device_t dev, struct rl_softc *sc) 968 { 969 bus_addr_t lowaddr; 970 bus_size_t rx_list_size, tx_list_size; 971 int error; 972 int i; 973 974 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 975 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 976 977 /* 978 * Allocate the parent bus DMA tag appropriate for PCI. 979 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD 980 * register should be set. However some RealTek chips are known 981 * to be buggy on DAC handling, therefore disable DAC by limiting 982 * DMA address space to 32bit. PCIe variants of RealTek chips 983 * may not have the limitation. 984 */ 985 lowaddr = BUS_SPACE_MAXADDR; 986 if ((sc->rl_flags & RL_FLAG_PCIE) == 0) 987 lowaddr = BUS_SPACE_MAXADDR_32BIT; 988 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 989 lowaddr, BUS_SPACE_MAXADDR, NULL, NULL, 990 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 991 NULL, NULL, &sc->rl_parent_tag); 992 if (error) { 993 device_printf(dev, "could not allocate parent DMA tag\n"); 994 return (error); 995 } 996 997 /* 998 * Allocate map for TX mbufs. 999 */ 1000 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 1001 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1002 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 1003 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 1004 if (error) { 1005 device_printf(dev, "could not allocate TX DMA tag\n"); 1006 return (error); 1007 } 1008 1009 /* 1010 * Allocate map for RX mbufs. 1011 */ 1012 1013 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 1014 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 1015 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1016 MJUM9BYTES, 1, MJUM9BYTES, 0, NULL, NULL, 1017 &sc->rl_ldata.rl_jrx_mtag); 1018 if (error) { 1019 device_printf(dev, 1020 "could not allocate jumbo RX DMA tag\n"); 1021 return (error); 1022 } 1023 } 1024 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 1025 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1026 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 1027 if (error) { 1028 device_printf(dev, "could not allocate RX DMA tag\n"); 1029 return (error); 1030 } 1031 1032 /* 1033 * Allocate map for TX descriptor list. 1034 */ 1035 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1036 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1037 NULL, tx_list_size, 1, tx_list_size, 0, 1038 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1039 if (error) { 1040 device_printf(dev, "could not allocate TX DMA ring tag\n"); 1041 return (error); 1042 } 1043 1044 /* Allocate DMA'able memory for the TX ring */ 1045 1046 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1047 (void **)&sc->rl_ldata.rl_tx_list, 1048 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1049 &sc->rl_ldata.rl_tx_list_map); 1050 if (error) { 1051 device_printf(dev, "could not allocate TX DMA ring\n"); 1052 return (error); 1053 } 1054 1055 /* Load the map for the TX ring. */ 1056 1057 sc->rl_ldata.rl_tx_list_addr = 0; 1058 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1059 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1060 tx_list_size, re_dma_map_addr, 1061 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1062 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 1063 device_printf(dev, "could not load TX DMA ring\n"); 1064 return (ENOMEM); 1065 } 1066 1067 /* Create DMA maps for TX buffers */ 1068 1069 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1070 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1071 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1072 if (error) { 1073 device_printf(dev, "could not create DMA map for TX\n"); 1074 return (error); 1075 } 1076 } 1077 1078 /* 1079 * Allocate map for RX descriptor list. 1080 */ 1081 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1082 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1083 NULL, rx_list_size, 1, rx_list_size, 0, 1084 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1085 if (error) { 1086 device_printf(dev, "could not create RX DMA ring tag\n"); 1087 return (error); 1088 } 1089 1090 /* Allocate DMA'able memory for the RX ring */ 1091 1092 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1093 (void **)&sc->rl_ldata.rl_rx_list, 1094 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1095 &sc->rl_ldata.rl_rx_list_map); 1096 if (error) { 1097 device_printf(dev, "could not allocate RX DMA ring\n"); 1098 return (error); 1099 } 1100 1101 /* Load the map for the RX ring. */ 1102 1103 sc->rl_ldata.rl_rx_list_addr = 0; 1104 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1105 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1106 rx_list_size, re_dma_map_addr, 1107 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1108 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1109 device_printf(dev, "could not load RX DMA ring\n"); 1110 return (ENOMEM); 1111 } 1112 1113 /* Create DMA maps for RX buffers */ 1114 1115 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 1116 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0, 1117 &sc->rl_ldata.rl_jrx_sparemap); 1118 if (error) { 1119 device_printf(dev, 1120 "could not create spare DMA map for jumbo RX\n"); 1121 return (error); 1122 } 1123 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1124 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0, 1125 &sc->rl_ldata.rl_jrx_desc[i].rx_dmamap); 1126 if (error) { 1127 device_printf(dev, 1128 "could not create DMA map for jumbo RX\n"); 1129 return (error); 1130 } 1131 } 1132 } 1133 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1134 &sc->rl_ldata.rl_rx_sparemap); 1135 if (error) { 1136 device_printf(dev, "could not create spare DMA map for RX\n"); 1137 return (error); 1138 } 1139 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1140 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1141 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1142 if (error) { 1143 device_printf(dev, "could not create DMA map for RX\n"); 1144 return (error); 1145 } 1146 } 1147 1148 /* Create DMA map for statistics. */ 1149 error = bus_dma_tag_create(sc->rl_parent_tag, RL_DUMP_ALIGN, 0, 1150 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1151 sizeof(struct rl_stats), 1, sizeof(struct rl_stats), 0, NULL, NULL, 1152 &sc->rl_ldata.rl_stag); 1153 if (error) { 1154 device_printf(dev, "could not create statistics DMA tag\n"); 1155 return (error); 1156 } 1157 /* Allocate DMA'able memory for statistics. */ 1158 error = bus_dmamem_alloc(sc->rl_ldata.rl_stag, 1159 (void **)&sc->rl_ldata.rl_stats, 1160 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1161 &sc->rl_ldata.rl_smap); 1162 if (error) { 1163 device_printf(dev, 1164 "could not allocate statistics DMA memory\n"); 1165 return (error); 1166 } 1167 /* Load the map for statistics. */ 1168 sc->rl_ldata.rl_stats_addr = 0; 1169 error = bus_dmamap_load(sc->rl_ldata.rl_stag, sc->rl_ldata.rl_smap, 1170 sc->rl_ldata.rl_stats, sizeof(struct rl_stats), re_dma_map_addr, 1171 &sc->rl_ldata.rl_stats_addr, BUS_DMA_NOWAIT); 1172 if (error != 0 || sc->rl_ldata.rl_stats_addr == 0) { 1173 device_printf(dev, "could not load statistics DMA memory\n"); 1174 return (ENOMEM); 1175 } 1176 1177 return (0); 1178 } 1179 1180 /* 1181 * Attach the interface. Allocate softc structures, do ifmedia 1182 * setup and ethernet/BPF attach. 1183 */ 1184 static int 1185 re_attach(device_t dev) 1186 { 1187 u_char eaddr[ETHER_ADDR_LEN]; 1188 u_int16_t as[ETHER_ADDR_LEN / 2]; 1189 struct rl_softc *sc; 1190 struct ifnet *ifp; 1191 const struct rl_hwrev *hw_rev; 1192 u_int32_t cap, ctl; 1193 int hwrev; 1194 u_int16_t devid, re_did = 0; 1195 int error = 0, i, phy, rid; 1196 int msic, msixc, reg; 1197 uint8_t cfg; 1198 1199 sc = device_get_softc(dev); 1200 sc->rl_dev = dev; 1201 1202 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1203 MTX_DEF); 1204 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1205 1206 /* 1207 * Map control/status registers. 1208 */ 1209 pci_enable_busmaster(dev); 1210 1211 devid = pci_get_device(dev); 1212 /* 1213 * Prefer memory space register mapping over IO space. 1214 * Because RTL8169SC does not seem to work when memory mapping 1215 * is used always activate io mapping. 1216 */ 1217 if (devid == RT_DEVICEID_8169SC) 1218 prefer_iomap = 1; 1219 if (prefer_iomap == 0) { 1220 sc->rl_res_id = PCIR_BAR(1); 1221 sc->rl_res_type = SYS_RES_MEMORY; 1222 /* RTL8168/8101E seems to use different BARs. */ 1223 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E) 1224 sc->rl_res_id = PCIR_BAR(2); 1225 } else { 1226 sc->rl_res_id = PCIR_BAR(0); 1227 sc->rl_res_type = SYS_RES_IOPORT; 1228 } 1229 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1230 &sc->rl_res_id, RF_ACTIVE); 1231 if (sc->rl_res == NULL && prefer_iomap == 0) { 1232 sc->rl_res_id = PCIR_BAR(0); 1233 sc->rl_res_type = SYS_RES_IOPORT; 1234 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1235 &sc->rl_res_id, RF_ACTIVE); 1236 } 1237 if (sc->rl_res == NULL) { 1238 device_printf(dev, "couldn't map ports/memory\n"); 1239 error = ENXIO; 1240 goto fail; 1241 } 1242 1243 sc->rl_btag = rman_get_bustag(sc->rl_res); 1244 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1245 1246 msic = pci_msi_count(dev); 1247 msixc = pci_msix_count(dev); 1248 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 1249 sc->rl_flags |= RL_FLAG_PCIE; 1250 sc->rl_expcap = reg; 1251 } 1252 if (bootverbose) { 1253 device_printf(dev, "MSI count : %d\n", msic); 1254 device_printf(dev, "MSI-X count : %d\n", msixc); 1255 } 1256 if (msix_disable > 0) 1257 msixc = 0; 1258 if (msi_disable > 0) 1259 msic = 0; 1260 /* Prefer MSI-X to MSI. */ 1261 if (msixc > 0) { 1262 msixc = 1; 1263 rid = PCIR_BAR(4); 1264 sc->rl_res_pba = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1265 &rid, RF_ACTIVE); 1266 if (sc->rl_res_pba == NULL) { 1267 device_printf(sc->rl_dev, 1268 "could not allocate MSI-X PBA resource\n"); 1269 } 1270 if (sc->rl_res_pba != NULL && 1271 pci_alloc_msix(dev, &msixc) == 0) { 1272 if (msixc == 1) { 1273 device_printf(dev, "Using %d MSI-X message\n", 1274 msixc); 1275 sc->rl_flags |= RL_FLAG_MSIX; 1276 } else 1277 pci_release_msi(dev); 1278 } 1279 if ((sc->rl_flags & RL_FLAG_MSIX) == 0) { 1280 if (sc->rl_res_pba != NULL) 1281 bus_release_resource(dev, SYS_RES_MEMORY, rid, 1282 sc->rl_res_pba); 1283 sc->rl_res_pba = NULL; 1284 msixc = 0; 1285 } 1286 } 1287 /* Prefer MSI to INTx. */ 1288 if (msixc == 0 && msic > 0) { 1289 msic = 1; 1290 if (pci_alloc_msi(dev, &msic) == 0) { 1291 if (msic == RL_MSI_MESSAGES) { 1292 device_printf(dev, "Using %d MSI message\n", 1293 msic); 1294 sc->rl_flags |= RL_FLAG_MSI; 1295 /* Explicitly set MSI enable bit. */ 1296 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1297 cfg = CSR_READ_1(sc, RL_CFG2); 1298 cfg |= RL_CFG2_MSI; 1299 CSR_WRITE_1(sc, RL_CFG2, cfg); 1300 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1301 } else 1302 pci_release_msi(dev); 1303 } 1304 if ((sc->rl_flags & RL_FLAG_MSI) == 0) 1305 msic = 0; 1306 } 1307 1308 /* Allocate interrupt */ 1309 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) { 1310 rid = 0; 1311 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1312 RF_SHAREABLE | RF_ACTIVE); 1313 if (sc->rl_irq[0] == NULL) { 1314 device_printf(dev, "couldn't allocate IRQ resources\n"); 1315 error = ENXIO; 1316 goto fail; 1317 } 1318 } else { 1319 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1320 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1321 SYS_RES_IRQ, &rid, RF_ACTIVE); 1322 if (sc->rl_irq[i] == NULL) { 1323 device_printf(dev, 1324 "couldn't llocate IRQ resources for " 1325 "message %d\n", rid); 1326 error = ENXIO; 1327 goto fail; 1328 } 1329 } 1330 } 1331 1332 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1333 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1334 cfg = CSR_READ_1(sc, RL_CFG2); 1335 if ((cfg & RL_CFG2_MSI) != 0) { 1336 device_printf(dev, "turning off MSI enable bit.\n"); 1337 cfg &= ~RL_CFG2_MSI; 1338 CSR_WRITE_1(sc, RL_CFG2, cfg); 1339 } 1340 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1341 } 1342 1343 /* Disable ASPM L0S/L1. */ 1344 if (sc->rl_expcap != 0) { 1345 cap = pci_read_config(dev, sc->rl_expcap + 1346 PCIR_EXPRESS_LINK_CAP, 2); 1347 if ((cap & PCIM_LINK_CAP_ASPM) != 0) { 1348 ctl = pci_read_config(dev, sc->rl_expcap + 1349 PCIR_EXPRESS_LINK_CTL, 2); 1350 if ((ctl & 0x0003) != 0) { 1351 ctl &= ~0x0003; 1352 pci_write_config(dev, sc->rl_expcap + 1353 PCIR_EXPRESS_LINK_CTL, ctl, 2); 1354 device_printf(dev, "ASPM disabled\n"); 1355 } 1356 } else 1357 device_printf(dev, "no ASPM capability\n"); 1358 } 1359 1360 hw_rev = re_hwrevs; 1361 hwrev = CSR_READ_4(sc, RL_TXCFG); 1362 switch (hwrev & 0x70000000) { 1363 case 0x00000000: 1364 case 0x10000000: 1365 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000); 1366 hwrev &= (RL_TXCFG_HWREV | 0x80000000); 1367 break; 1368 default: 1369 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000); 1370 hwrev &= RL_TXCFG_HWREV; 1371 break; 1372 } 1373 device_printf(dev, "MAC rev. 0x%08x\n", hwrev & 0x00700000); 1374 while (hw_rev->rl_desc != NULL) { 1375 if (hw_rev->rl_rev == hwrev) { 1376 sc->rl_type = hw_rev->rl_type; 1377 sc->rl_hwrev = hw_rev; 1378 break; 1379 } 1380 hw_rev++; 1381 } 1382 if (hw_rev->rl_desc == NULL) { 1383 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev); 1384 error = ENXIO; 1385 goto fail; 1386 } 1387 1388 switch (hw_rev->rl_rev) { 1389 case RL_HWREV_8139CPLUS: 1390 sc->rl_flags |= RL_FLAG_FASTETHER | RL_FLAG_AUTOPAD; 1391 break; 1392 case RL_HWREV_8100E: 1393 case RL_HWREV_8101E: 1394 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_FASTETHER; 1395 break; 1396 case RL_HWREV_8102E: 1397 case RL_HWREV_8102EL: 1398 case RL_HWREV_8102EL_SPIN1: 1399 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1400 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | 1401 RL_FLAG_AUTOPAD; 1402 break; 1403 case RL_HWREV_8103E: 1404 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1405 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | 1406 RL_FLAG_AUTOPAD | RL_FLAG_MACSLEEP; 1407 break; 1408 case RL_HWREV_8401E: 1409 case RL_HWREV_8105E: 1410 case RL_HWREV_8105E_SPIN1: 1411 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1412 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1413 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD; 1414 break; 1415 case RL_HWREV_8402: 1416 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1417 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1418 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | 1419 RL_FLAG_CMDSTOP_WAIT_TXQ; 1420 break; 1421 case RL_HWREV_8168B_SPIN1: 1422 case RL_HWREV_8168B_SPIN2: 1423 sc->rl_flags |= RL_FLAG_WOLRXENB; 1424 /* FALLTHROUGH */ 1425 case RL_HWREV_8168B_SPIN3: 1426 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT; 1427 break; 1428 case RL_HWREV_8168C_SPIN2: 1429 sc->rl_flags |= RL_FLAG_MACSLEEP; 1430 /* FALLTHROUGH */ 1431 case RL_HWREV_8168C: 1432 if ((hwrev & 0x00700000) == 0x00200000) 1433 sc->rl_flags |= RL_FLAG_MACSLEEP; 1434 /* FALLTHROUGH */ 1435 case RL_HWREV_8168CP: 1436 case RL_HWREV_8168D: 1437 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1438 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1439 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK; 1440 break; 1441 case RL_HWREV_8168DP: 1442 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1443 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_AUTOPAD | 1444 RL_FLAG_JUMBOV2 | RL_FLAG_WAIT_TXPOLL | RL_FLAG_WOL_MANLINK; 1445 break; 1446 case RL_HWREV_8168E: 1447 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1448 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1449 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1450 RL_FLAG_WOL_MANLINK; 1451 break; 1452 case RL_HWREV_8168E_VL: 1453 case RL_HWREV_8168F: 1454 case RL_HWREV_8411: 1455 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1456 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1457 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1458 RL_FLAG_CMDSTOP_WAIT_TXQ | RL_FLAG_WOL_MANLINK; 1459 break; 1460 case RL_HWREV_8169_8110SB: 1461 case RL_HWREV_8169_8110SBL: 1462 case RL_HWREV_8169_8110SC: 1463 case RL_HWREV_8169_8110SCE: 1464 sc->rl_flags |= RL_FLAG_PHYWAKE; 1465 /* FALLTHROUGH */ 1466 case RL_HWREV_8169: 1467 case RL_HWREV_8169S: 1468 case RL_HWREV_8110S: 1469 sc->rl_flags |= RL_FLAG_MACRESET; 1470 break; 1471 default: 1472 break; 1473 } 1474 1475 /* Reset the adapter. */ 1476 RL_LOCK(sc); 1477 re_reset(sc); 1478 RL_UNLOCK(sc); 1479 1480 /* Enable PME. */ 1481 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1482 cfg = CSR_READ_1(sc, RL_CFG1); 1483 cfg |= RL_CFG1_PME; 1484 CSR_WRITE_1(sc, RL_CFG1, cfg); 1485 cfg = CSR_READ_1(sc, RL_CFG5); 1486 cfg &= RL_CFG5_PME_STS; 1487 CSR_WRITE_1(sc, RL_CFG5, cfg); 1488 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1489 1490 if ((sc->rl_flags & RL_FLAG_PAR) != 0) { 1491 /* 1492 * XXX Should have a better way to extract station 1493 * address from EEPROM. 1494 */ 1495 for (i = 0; i < ETHER_ADDR_LEN; i++) 1496 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1497 } else { 1498 sc->rl_eewidth = RL_9356_ADDR_LEN; 1499 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1500 if (re_did != 0x8129) 1501 sc->rl_eewidth = RL_9346_ADDR_LEN; 1502 1503 /* 1504 * Get station address from the EEPROM. 1505 */ 1506 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1507 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1508 as[i] = le16toh(as[i]); 1509 bcopy(as, eaddr, sizeof(eaddr)); 1510 } 1511 1512 if (sc->rl_type == RL_8169) { 1513 /* Set RX length mask and number of descriptors. */ 1514 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1515 sc->rl_txstart = RL_GTXSTART; 1516 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1517 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1518 } else { 1519 /* Set RX length mask and number of descriptors. */ 1520 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1521 sc->rl_txstart = RL_TXSTART; 1522 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1523 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1524 } 1525 1526 error = re_allocmem(dev, sc); 1527 if (error) 1528 goto fail; 1529 re_add_sysctls(sc); 1530 1531 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1532 if (ifp == NULL) { 1533 device_printf(dev, "can not if_alloc()\n"); 1534 error = ENOSPC; 1535 goto fail; 1536 } 1537 1538 /* Take controller out of deep sleep mode. */ 1539 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 1540 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 1541 CSR_WRITE_1(sc, RL_GPIO, 1542 CSR_READ_1(sc, RL_GPIO) | 0x01); 1543 else 1544 CSR_WRITE_1(sc, RL_GPIO, 1545 CSR_READ_1(sc, RL_GPIO) & ~0x01); 1546 } 1547 1548 /* Take PHY out of power down mode. */ 1549 if ((sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) { 1550 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80); 1551 if (hw_rev->rl_rev == RL_HWREV_8401E) 1552 CSR_WRITE_1(sc, 0xD1, CSR_READ_1(sc, 0xD1) & ~0x08); 1553 } 1554 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) { 1555 re_gmii_writereg(dev, 1, 0x1f, 0); 1556 re_gmii_writereg(dev, 1, 0x0e, 0); 1557 } 1558 1559 #define RE_PHYAD_INTERNAL 0 1560 1561 /* Do MII setup. */ 1562 phy = RE_PHYAD_INTERNAL; 1563 if (sc->rl_type == RL_8169) 1564 phy = 1; 1565 error = mii_attach(dev, &sc->rl_miibus, ifp, re_ifmedia_upd, 1566 re_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, MIIF_DOPAUSE); 1567 if (error != 0) { 1568 device_printf(dev, "attaching PHYs failed\n"); 1569 goto fail; 1570 } 1571 1572 ifp->if_softc = sc; 1573 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1574 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1575 ifp->if_ioctl = re_ioctl; 1576 ifp->if_start = re_start; 1577 /* 1578 * RTL8168/8111C generates wrong IP checksummed frame if the 1579 * packet has IP options so disable TX IP checksum offloading. 1580 */ 1581 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168C || 1582 sc->rl_hwrev->rl_rev == RL_HWREV_8168C_SPIN2) 1583 ifp->if_hwassist = CSUM_TCP | CSUM_UDP; 1584 else 1585 ifp->if_hwassist = CSUM_IP | CSUM_TCP | CSUM_UDP; 1586 ifp->if_hwassist |= CSUM_TSO; 1587 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 1588 ifp->if_capenable = ifp->if_capabilities; 1589 ifp->if_init = re_init; 1590 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1591 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1592 IFQ_SET_READY(&ifp->if_snd); 1593 1594 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1595 1596 /* 1597 * Call MI attach routine. 1598 */ 1599 ether_ifattach(ifp, eaddr); 1600 1601 /* VLAN capability setup */ 1602 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1603 if (ifp->if_capabilities & IFCAP_HWCSUM) 1604 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1605 /* Enable WOL if PM is supported. */ 1606 if (pci_find_cap(sc->rl_dev, PCIY_PMG, ®) == 0) 1607 ifp->if_capabilities |= IFCAP_WOL; 1608 ifp->if_capenable = ifp->if_capabilities; 1609 ifp->if_capenable &= ~(IFCAP_WOL_UCAST | IFCAP_WOL_MCAST); 1610 /* 1611 * Don't enable TSO by default. It is known to generate 1612 * corrupted TCP segments(bad TCP options) under certain 1613 * circumtances. 1614 */ 1615 ifp->if_hwassist &= ~CSUM_TSO; 1616 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO); 1617 #ifdef DEVICE_POLLING 1618 ifp->if_capabilities |= IFCAP_POLLING; 1619 #endif 1620 /* 1621 * Tell the upper layer(s) we support long frames. 1622 * Must appear after the call to ether_ifattach() because 1623 * ether_ifattach() sets ifi_hdrlen to the default value. 1624 */ 1625 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1626 1627 #ifdef DEV_NETMAP 1628 re_netmap_attach(sc); 1629 #endif /* DEV_NETMAP */ 1630 #ifdef RE_DIAG 1631 /* 1632 * Perform hardware diagnostic on the original RTL8169. 1633 * Some 32-bit cards were incorrectly wired and would 1634 * malfunction if plugged into a 64-bit slot. 1635 */ 1636 1637 if (hwrev == RL_HWREV_8169) { 1638 error = re_diag(sc); 1639 if (error) { 1640 device_printf(dev, 1641 "attach aborted due to hardware diag failure\n"); 1642 ether_ifdetach(ifp); 1643 goto fail; 1644 } 1645 } 1646 #endif 1647 1648 #ifdef RE_TX_MODERATION 1649 intr_filter = 1; 1650 #endif 1651 /* Hook interrupt last to avoid having to lock softc */ 1652 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 && 1653 intr_filter == 0) { 1654 error = bus_setup_intr(dev, sc->rl_irq[0], 1655 INTR_TYPE_NET | INTR_MPSAFE, NULL, re_intr_msi, sc, 1656 &sc->rl_intrhand[0]); 1657 } else { 1658 error = bus_setup_intr(dev, sc->rl_irq[0], 1659 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1660 &sc->rl_intrhand[0]); 1661 } 1662 if (error) { 1663 device_printf(dev, "couldn't set up irq\n"); 1664 ether_ifdetach(ifp); 1665 } 1666 1667 fail: 1668 1669 if (error) 1670 re_detach(dev); 1671 1672 return (error); 1673 } 1674 1675 /* 1676 * Shutdown hardware and free up resources. This can be called any 1677 * time after the mutex has been initialized. It is called in both 1678 * the error case in attach and the normal detach case so it needs 1679 * to be careful about only freeing resources that have actually been 1680 * allocated. 1681 */ 1682 static int 1683 re_detach(device_t dev) 1684 { 1685 struct rl_softc *sc; 1686 struct ifnet *ifp; 1687 int i, rid; 1688 1689 sc = device_get_softc(dev); 1690 ifp = sc->rl_ifp; 1691 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1692 1693 /* These should only be active if attach succeeded */ 1694 if (device_is_attached(dev)) { 1695 #ifdef DEVICE_POLLING 1696 if (ifp->if_capenable & IFCAP_POLLING) 1697 ether_poll_deregister(ifp); 1698 #endif 1699 RL_LOCK(sc); 1700 #if 0 1701 sc->suspended = 1; 1702 #endif 1703 re_stop(sc); 1704 RL_UNLOCK(sc); 1705 callout_drain(&sc->rl_stat_callout); 1706 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1707 /* 1708 * Force off the IFF_UP flag here, in case someone 1709 * still had a BPF descriptor attached to this 1710 * interface. If they do, ether_ifdetach() will cause 1711 * the BPF code to try and clear the promisc mode 1712 * flag, which will bubble down to re_ioctl(), 1713 * which will try to call re_init() again. This will 1714 * turn the NIC back on and restart the MII ticker, 1715 * which will panic the system when the kernel tries 1716 * to invoke the re_tick() function that isn't there 1717 * anymore. 1718 */ 1719 ifp->if_flags &= ~IFF_UP; 1720 ether_ifdetach(ifp); 1721 } 1722 if (sc->rl_miibus) 1723 device_delete_child(dev, sc->rl_miibus); 1724 bus_generic_detach(dev); 1725 1726 /* 1727 * The rest is resource deallocation, so we should already be 1728 * stopped here. 1729 */ 1730 1731 if (sc->rl_intrhand[0] != NULL) { 1732 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]); 1733 sc->rl_intrhand[0] = NULL; 1734 } 1735 if (ifp != NULL) 1736 if_free(ifp); 1737 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) 1738 rid = 0; 1739 else 1740 rid = 1; 1741 if (sc->rl_irq[0] != NULL) { 1742 bus_release_resource(dev, SYS_RES_IRQ, rid, sc->rl_irq[0]); 1743 sc->rl_irq[0] = NULL; 1744 } 1745 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0) 1746 pci_release_msi(dev); 1747 if (sc->rl_res_pba) { 1748 rid = PCIR_BAR(4); 1749 bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->rl_res_pba); 1750 } 1751 if (sc->rl_res) 1752 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, 1753 sc->rl_res); 1754 1755 /* Unload and free the RX DMA ring memory and map */ 1756 1757 if (sc->rl_ldata.rl_rx_list_tag) { 1758 if (sc->rl_ldata.rl_rx_list_map) 1759 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1760 sc->rl_ldata.rl_rx_list_map); 1761 if (sc->rl_ldata.rl_rx_list_map && sc->rl_ldata.rl_rx_list) 1762 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1763 sc->rl_ldata.rl_rx_list, 1764 sc->rl_ldata.rl_rx_list_map); 1765 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1766 } 1767 1768 /* Unload and free the TX DMA ring memory and map */ 1769 1770 if (sc->rl_ldata.rl_tx_list_tag) { 1771 if (sc->rl_ldata.rl_tx_list_map) 1772 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1773 sc->rl_ldata.rl_tx_list_map); 1774 if (sc->rl_ldata.rl_tx_list_map && sc->rl_ldata.rl_tx_list) 1775 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1776 sc->rl_ldata.rl_tx_list, 1777 sc->rl_ldata.rl_tx_list_map); 1778 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1779 } 1780 1781 /* Destroy all the RX and TX buffer maps */ 1782 1783 if (sc->rl_ldata.rl_tx_mtag) { 1784 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1785 if (sc->rl_ldata.rl_tx_desc[i].tx_dmamap) 1786 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1787 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1788 } 1789 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1790 } 1791 if (sc->rl_ldata.rl_rx_mtag) { 1792 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1793 if (sc->rl_ldata.rl_rx_desc[i].rx_dmamap) 1794 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1795 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1796 } 1797 if (sc->rl_ldata.rl_rx_sparemap) 1798 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1799 sc->rl_ldata.rl_rx_sparemap); 1800 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1801 } 1802 if (sc->rl_ldata.rl_jrx_mtag) { 1803 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1804 if (sc->rl_ldata.rl_jrx_desc[i].rx_dmamap) 1805 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag, 1806 sc->rl_ldata.rl_jrx_desc[i].rx_dmamap); 1807 } 1808 if (sc->rl_ldata.rl_jrx_sparemap) 1809 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag, 1810 sc->rl_ldata.rl_jrx_sparemap); 1811 bus_dma_tag_destroy(sc->rl_ldata.rl_jrx_mtag); 1812 } 1813 /* Unload and free the stats buffer and map */ 1814 1815 if (sc->rl_ldata.rl_stag) { 1816 if (sc->rl_ldata.rl_smap) 1817 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1818 sc->rl_ldata.rl_smap); 1819 if (sc->rl_ldata.rl_smap && sc->rl_ldata.rl_stats) 1820 bus_dmamem_free(sc->rl_ldata.rl_stag, 1821 sc->rl_ldata.rl_stats, sc->rl_ldata.rl_smap); 1822 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1823 } 1824 1825 #ifdef DEV_NETMAP 1826 netmap_detach(ifp); 1827 #endif /* DEV_NETMAP */ 1828 if (sc->rl_parent_tag) 1829 bus_dma_tag_destroy(sc->rl_parent_tag); 1830 1831 mtx_destroy(&sc->rl_mtx); 1832 1833 return (0); 1834 } 1835 1836 static __inline void 1837 re_discard_rxbuf(struct rl_softc *sc, int idx) 1838 { 1839 struct rl_desc *desc; 1840 struct rl_rxdesc *rxd; 1841 uint32_t cmdstat; 1842 1843 if (sc->rl_ifp->if_mtu > RL_MTU && 1844 (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) 1845 rxd = &sc->rl_ldata.rl_jrx_desc[idx]; 1846 else 1847 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1848 desc = &sc->rl_ldata.rl_rx_list[idx]; 1849 desc->rl_vlanctl = 0; 1850 cmdstat = rxd->rx_size; 1851 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1852 cmdstat |= RL_RDESC_CMD_EOR; 1853 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1854 } 1855 1856 static int 1857 re_newbuf(struct rl_softc *sc, int idx) 1858 { 1859 struct mbuf *m; 1860 struct rl_rxdesc *rxd; 1861 bus_dma_segment_t segs[1]; 1862 bus_dmamap_t map; 1863 struct rl_desc *desc; 1864 uint32_t cmdstat; 1865 int error, nsegs; 1866 1867 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1868 if (m == NULL) 1869 return (ENOBUFS); 1870 1871 m->m_len = m->m_pkthdr.len = MCLBYTES; 1872 #ifdef RE_FIXUP_RX 1873 /* 1874 * This is part of an evil trick to deal with non-x86 platforms. 1875 * The RealTek chip requires RX buffers to be aligned on 64-bit 1876 * boundaries, but that will hose non-x86 machines. To get around 1877 * this, we leave some empty space at the start of each buffer 1878 * and for non-x86 hosts, we copy the buffer back six bytes 1879 * to achieve word alignment. This is slightly more efficient 1880 * than allocating a new buffer, copying the contents, and 1881 * discarding the old buffer. 1882 */ 1883 m_adj(m, RE_ETHER_ALIGN); 1884 #endif 1885 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1886 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1887 if (error != 0) { 1888 m_freem(m); 1889 return (ENOBUFS); 1890 } 1891 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1892 1893 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1894 if (rxd->rx_m != NULL) { 1895 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1896 BUS_DMASYNC_POSTREAD); 1897 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1898 } 1899 1900 rxd->rx_m = m; 1901 map = rxd->rx_dmamap; 1902 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1903 rxd->rx_size = segs[0].ds_len; 1904 sc->rl_ldata.rl_rx_sparemap = map; 1905 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1906 BUS_DMASYNC_PREREAD); 1907 1908 desc = &sc->rl_ldata.rl_rx_list[idx]; 1909 desc->rl_vlanctl = 0; 1910 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1911 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1912 cmdstat = segs[0].ds_len; 1913 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1914 cmdstat |= RL_RDESC_CMD_EOR; 1915 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1916 1917 return (0); 1918 } 1919 1920 static int 1921 re_jumbo_newbuf(struct rl_softc *sc, int idx) 1922 { 1923 struct mbuf *m; 1924 struct rl_rxdesc *rxd; 1925 bus_dma_segment_t segs[1]; 1926 bus_dmamap_t map; 1927 struct rl_desc *desc; 1928 uint32_t cmdstat; 1929 int error, nsegs; 1930 1931 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 1932 if (m == NULL) 1933 return (ENOBUFS); 1934 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1935 #ifdef RE_FIXUP_RX 1936 m_adj(m, RE_ETHER_ALIGN); 1937 #endif 1938 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_jrx_mtag, 1939 sc->rl_ldata.rl_jrx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1940 if (error != 0) { 1941 m_freem(m); 1942 return (ENOBUFS); 1943 } 1944 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1945 1946 rxd = &sc->rl_ldata.rl_jrx_desc[idx]; 1947 if (rxd->rx_m != NULL) { 1948 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap, 1949 BUS_DMASYNC_POSTREAD); 1950 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap); 1951 } 1952 1953 rxd->rx_m = m; 1954 map = rxd->rx_dmamap; 1955 rxd->rx_dmamap = sc->rl_ldata.rl_jrx_sparemap; 1956 rxd->rx_size = segs[0].ds_len; 1957 sc->rl_ldata.rl_jrx_sparemap = map; 1958 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap, 1959 BUS_DMASYNC_PREREAD); 1960 1961 desc = &sc->rl_ldata.rl_rx_list[idx]; 1962 desc->rl_vlanctl = 0; 1963 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1964 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1965 cmdstat = segs[0].ds_len; 1966 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1967 cmdstat |= RL_RDESC_CMD_EOR; 1968 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1969 1970 return (0); 1971 } 1972 1973 #ifdef RE_FIXUP_RX 1974 static __inline void 1975 re_fixup_rx(struct mbuf *m) 1976 { 1977 int i; 1978 uint16_t *src, *dst; 1979 1980 src = mtod(m, uint16_t *); 1981 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1982 1983 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1984 *dst++ = *src++; 1985 1986 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1987 } 1988 #endif 1989 1990 static int 1991 re_tx_list_init(struct rl_softc *sc) 1992 { 1993 struct rl_desc *desc; 1994 int i; 1995 1996 RL_LOCK_ASSERT(sc); 1997 1998 bzero(sc->rl_ldata.rl_tx_list, 1999 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 2000 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 2001 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 2002 #ifdef DEV_NETMAP 2003 re_netmap_tx_init(sc); 2004 #endif /* DEV_NETMAP */ 2005 /* Set EOR. */ 2006 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 2007 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 2008 2009 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2010 sc->rl_ldata.rl_tx_list_map, 2011 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2012 2013 sc->rl_ldata.rl_tx_prodidx = 0; 2014 sc->rl_ldata.rl_tx_considx = 0; 2015 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 2016 2017 return (0); 2018 } 2019 2020 static int 2021 re_rx_list_init(struct rl_softc *sc) 2022 { 2023 int error, i; 2024 2025 bzero(sc->rl_ldata.rl_rx_list, 2026 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 2027 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2028 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 2029 if ((error = re_newbuf(sc, i)) != 0) 2030 return (error); 2031 } 2032 #ifdef DEV_NETMAP 2033 re_netmap_rx_init(sc); 2034 #endif /* DEV_NETMAP */ 2035 2036 /* Flush the RX descriptors */ 2037 2038 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2039 sc->rl_ldata.rl_rx_list_map, 2040 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2041 2042 sc->rl_ldata.rl_rx_prodidx = 0; 2043 sc->rl_head = sc->rl_tail = NULL; 2044 sc->rl_int_rx_act = 0; 2045 2046 return (0); 2047 } 2048 2049 static int 2050 re_jrx_list_init(struct rl_softc *sc) 2051 { 2052 int error, i; 2053 2054 bzero(sc->rl_ldata.rl_rx_list, 2055 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 2056 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2057 sc->rl_ldata.rl_jrx_desc[i].rx_m = NULL; 2058 if ((error = re_jumbo_newbuf(sc, i)) != 0) 2059 return (error); 2060 } 2061 2062 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2063 sc->rl_ldata.rl_rx_list_map, 2064 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2065 2066 sc->rl_ldata.rl_rx_prodidx = 0; 2067 sc->rl_head = sc->rl_tail = NULL; 2068 sc->rl_int_rx_act = 0; 2069 2070 return (0); 2071 } 2072 2073 /* 2074 * RX handler for C+ and 8169. For the gigE chips, we support 2075 * the reception of jumbo frames that have been fragmented 2076 * across multiple 2K mbuf cluster buffers. 2077 */ 2078 static int 2079 re_rxeof(struct rl_softc *sc, int *rx_npktsp) 2080 { 2081 struct mbuf *m; 2082 struct ifnet *ifp; 2083 int i, rxerr, total_len; 2084 struct rl_desc *cur_rx; 2085 u_int32_t rxstat, rxvlan; 2086 int jumbo, maxpkt = 16, rx_npkts = 0; 2087 2088 RL_LOCK_ASSERT(sc); 2089 2090 ifp = sc->rl_ifp; 2091 #ifdef DEV_NETMAP 2092 if (ifp->if_capenable & IFCAP_NETMAP) { 2093 selwakeuppri(&NA(ifp)->rx_rings->si, PI_NET); 2094 return 0; 2095 } 2096 #endif /* DEV_NETMAP */ 2097 if (ifp->if_mtu > RL_MTU && (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) 2098 jumbo = 1; 2099 else 2100 jumbo = 0; 2101 2102 /* Invalidate the descriptor memory */ 2103 2104 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2105 sc->rl_ldata.rl_rx_list_map, 2106 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2107 2108 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 2109 i = RL_RX_DESC_NXT(sc, i)) { 2110 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2111 break; 2112 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 2113 rxstat = le32toh(cur_rx->rl_cmdstat); 2114 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 2115 break; 2116 total_len = rxstat & sc->rl_rxlenmask; 2117 rxvlan = le32toh(cur_rx->rl_vlanctl); 2118 if (jumbo != 0) 2119 m = sc->rl_ldata.rl_jrx_desc[i].rx_m; 2120 else 2121 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 2122 2123 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 2124 (rxstat & (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) != 2125 (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) { 2126 /* 2127 * RTL8168C or later controllers do not 2128 * support multi-fragment packet. 2129 */ 2130 re_discard_rxbuf(sc, i); 2131 continue; 2132 } else if ((rxstat & RL_RDESC_STAT_EOF) == 0) { 2133 if (re_newbuf(sc, i) != 0) { 2134 /* 2135 * If this is part of a multi-fragment packet, 2136 * discard all the pieces. 2137 */ 2138 if (sc->rl_head != NULL) { 2139 m_freem(sc->rl_head); 2140 sc->rl_head = sc->rl_tail = NULL; 2141 } 2142 re_discard_rxbuf(sc, i); 2143 continue; 2144 } 2145 m->m_len = RE_RX_DESC_BUFLEN; 2146 if (sc->rl_head == NULL) 2147 sc->rl_head = sc->rl_tail = m; 2148 else { 2149 m->m_flags &= ~M_PKTHDR; 2150 sc->rl_tail->m_next = m; 2151 sc->rl_tail = m; 2152 } 2153 continue; 2154 } 2155 2156 /* 2157 * NOTE: for the 8139C+, the frame length field 2158 * is always 12 bits in size, but for the gigE chips, 2159 * it is 13 bits (since the max RX frame length is 16K). 2160 * Unfortunately, all 32 bits in the status word 2161 * were already used, so to make room for the extra 2162 * length bit, RealTek took out the 'frame alignment 2163 * error' bit and shifted the other status bits 2164 * over one slot. The OWN, EOR, FS and LS bits are 2165 * still in the same places. We have already extracted 2166 * the frame length and checked the OWN bit, so rather 2167 * than using an alternate bit mapping, we shift the 2168 * status bits one space to the right so we can evaluate 2169 * them using the 8169 status as though it was in the 2170 * same format as that of the 8139C+. 2171 */ 2172 if (sc->rl_type == RL_8169) 2173 rxstat >>= 1; 2174 2175 /* 2176 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 2177 * set, but if CRC is clear, it will still be a valid frame. 2178 */ 2179 if ((rxstat & RL_RDESC_STAT_RXERRSUM) != 0) { 2180 rxerr = 1; 2181 if ((sc->rl_flags & RL_FLAG_JUMBOV2) == 0 && 2182 total_len > 8191 && 2183 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT) 2184 rxerr = 0; 2185 if (rxerr != 0) { 2186 ifp->if_ierrors++; 2187 /* 2188 * If this is part of a multi-fragment packet, 2189 * discard all the pieces. 2190 */ 2191 if (sc->rl_head != NULL) { 2192 m_freem(sc->rl_head); 2193 sc->rl_head = sc->rl_tail = NULL; 2194 } 2195 re_discard_rxbuf(sc, i); 2196 continue; 2197 } 2198 } 2199 2200 /* 2201 * If allocating a replacement mbuf fails, 2202 * reload the current one. 2203 */ 2204 if (jumbo != 0) 2205 rxerr = re_jumbo_newbuf(sc, i); 2206 else 2207 rxerr = re_newbuf(sc, i); 2208 if (rxerr != 0) { 2209 ifp->if_iqdrops++; 2210 if (sc->rl_head != NULL) { 2211 m_freem(sc->rl_head); 2212 sc->rl_head = sc->rl_tail = NULL; 2213 } 2214 re_discard_rxbuf(sc, i); 2215 continue; 2216 } 2217 2218 if (sc->rl_head != NULL) { 2219 if (jumbo != 0) 2220 m->m_len = total_len; 2221 else { 2222 m->m_len = total_len % RE_RX_DESC_BUFLEN; 2223 if (m->m_len == 0) 2224 m->m_len = RE_RX_DESC_BUFLEN; 2225 } 2226 /* 2227 * Special case: if there's 4 bytes or less 2228 * in this buffer, the mbuf can be discarded: 2229 * the last 4 bytes is the CRC, which we don't 2230 * care about anyway. 2231 */ 2232 if (m->m_len <= ETHER_CRC_LEN) { 2233 sc->rl_tail->m_len -= 2234 (ETHER_CRC_LEN - m->m_len); 2235 m_freem(m); 2236 } else { 2237 m->m_len -= ETHER_CRC_LEN; 2238 m->m_flags &= ~M_PKTHDR; 2239 sc->rl_tail->m_next = m; 2240 } 2241 m = sc->rl_head; 2242 sc->rl_head = sc->rl_tail = NULL; 2243 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 2244 } else 2245 m->m_pkthdr.len = m->m_len = 2246 (total_len - ETHER_CRC_LEN); 2247 2248 #ifdef RE_FIXUP_RX 2249 re_fixup_rx(m); 2250 #endif 2251 ifp->if_ipackets++; 2252 m->m_pkthdr.rcvif = ifp; 2253 2254 /* Do RX checksumming if enabled */ 2255 2256 if (ifp->if_capenable & IFCAP_RXCSUM) { 2257 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2258 /* Check IP header checksum */ 2259 if (rxstat & RL_RDESC_STAT_PROTOID) 2260 m->m_pkthdr.csum_flags |= 2261 CSUM_IP_CHECKED; 2262 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 2263 m->m_pkthdr.csum_flags |= 2264 CSUM_IP_VALID; 2265 2266 /* Check TCP/UDP checksum */ 2267 if ((RL_TCPPKT(rxstat) && 2268 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 2269 (RL_UDPPKT(rxstat) && 2270 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 2271 m->m_pkthdr.csum_flags |= 2272 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2273 m->m_pkthdr.csum_data = 0xffff; 2274 } 2275 } else { 2276 /* 2277 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP 2278 */ 2279 if ((rxstat & RL_RDESC_STAT_PROTOID) && 2280 (rxvlan & RL_RDESC_IPV4)) 2281 m->m_pkthdr.csum_flags |= 2282 CSUM_IP_CHECKED; 2283 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) && 2284 (rxvlan & RL_RDESC_IPV4)) 2285 m->m_pkthdr.csum_flags |= 2286 CSUM_IP_VALID; 2287 if (((rxstat & RL_RDESC_STAT_TCP) && 2288 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 2289 ((rxstat & RL_RDESC_STAT_UDP) && 2290 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 2291 m->m_pkthdr.csum_flags |= 2292 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2293 m->m_pkthdr.csum_data = 0xffff; 2294 } 2295 } 2296 } 2297 maxpkt--; 2298 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 2299 m->m_pkthdr.ether_vtag = 2300 bswap16((rxvlan & RL_RDESC_VLANCTL_DATA)); 2301 m->m_flags |= M_VLANTAG; 2302 } 2303 RL_UNLOCK(sc); 2304 (*ifp->if_input)(ifp, m); 2305 RL_LOCK(sc); 2306 rx_npkts++; 2307 } 2308 2309 /* Flush the RX DMA ring */ 2310 2311 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2312 sc->rl_ldata.rl_rx_list_map, 2313 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2314 2315 sc->rl_ldata.rl_rx_prodidx = i; 2316 2317 if (rx_npktsp != NULL) 2318 *rx_npktsp = rx_npkts; 2319 if (maxpkt) 2320 return (EAGAIN); 2321 2322 return (0); 2323 } 2324 2325 static void 2326 re_txeof(struct rl_softc *sc) 2327 { 2328 struct ifnet *ifp; 2329 struct rl_txdesc *txd; 2330 u_int32_t txstat; 2331 int cons; 2332 2333 cons = sc->rl_ldata.rl_tx_considx; 2334 if (cons == sc->rl_ldata.rl_tx_prodidx) 2335 return; 2336 2337 ifp = sc->rl_ifp; 2338 #ifdef DEV_NETMAP 2339 if (ifp->if_capenable & IFCAP_NETMAP) { 2340 selwakeuppri(&NA(ifp)->tx_rings[0].si, PI_NET); 2341 return; 2342 } 2343 #endif /* DEV_NETMAP */ 2344 /* Invalidate the TX descriptor list */ 2345 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2346 sc->rl_ldata.rl_tx_list_map, 2347 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2348 2349 for (; cons != sc->rl_ldata.rl_tx_prodidx; 2350 cons = RL_TX_DESC_NXT(sc, cons)) { 2351 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 2352 if (txstat & RL_TDESC_STAT_OWN) 2353 break; 2354 /* 2355 * We only stash mbufs in the last descriptor 2356 * in a fragment chain, which also happens to 2357 * be the only place where the TX status bits 2358 * are valid. 2359 */ 2360 if (txstat & RL_TDESC_CMD_EOF) { 2361 txd = &sc->rl_ldata.rl_tx_desc[cons]; 2362 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2363 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2364 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2365 txd->tx_dmamap); 2366 KASSERT(txd->tx_m != NULL, 2367 ("%s: freeing NULL mbufs!", __func__)); 2368 m_freem(txd->tx_m); 2369 txd->tx_m = NULL; 2370 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 2371 RL_TDESC_STAT_COLCNT)) 2372 ifp->if_collisions++; 2373 if (txstat & RL_TDESC_STAT_TXERRSUM) 2374 ifp->if_oerrors++; 2375 else 2376 ifp->if_opackets++; 2377 } 2378 sc->rl_ldata.rl_tx_free++; 2379 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2380 } 2381 sc->rl_ldata.rl_tx_considx = cons; 2382 2383 /* No changes made to the TX ring, so no flush needed */ 2384 2385 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 2386 #ifdef RE_TX_MODERATION 2387 /* 2388 * If not all descriptors have been reaped yet, reload 2389 * the timer so that we will eventually get another 2390 * interrupt that will cause us to re-enter this routine. 2391 * This is done in case the transmitter has gone idle. 2392 */ 2393 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2394 #endif 2395 } else 2396 sc->rl_watchdog_timer = 0; 2397 } 2398 2399 static void 2400 re_tick(void *xsc) 2401 { 2402 struct rl_softc *sc; 2403 struct mii_data *mii; 2404 2405 sc = xsc; 2406 2407 RL_LOCK_ASSERT(sc); 2408 2409 mii = device_get_softc(sc->rl_miibus); 2410 mii_tick(mii); 2411 if ((sc->rl_flags & RL_FLAG_LINK) == 0) 2412 re_miibus_statchg(sc->rl_dev); 2413 /* 2414 * Reclaim transmitted frames here. Technically it is not 2415 * necessary to do here but it ensures periodic reclamation 2416 * regardless of Tx completion interrupt which seems to be 2417 * lost on PCIe based controllers under certain situations. 2418 */ 2419 re_txeof(sc); 2420 re_watchdog(sc); 2421 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2422 } 2423 2424 #ifdef DEVICE_POLLING 2425 static int 2426 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2427 { 2428 struct rl_softc *sc = ifp->if_softc; 2429 int rx_npkts = 0; 2430 2431 RL_LOCK(sc); 2432 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2433 rx_npkts = re_poll_locked(ifp, cmd, count); 2434 RL_UNLOCK(sc); 2435 return (rx_npkts); 2436 } 2437 2438 static int 2439 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2440 { 2441 struct rl_softc *sc = ifp->if_softc; 2442 int rx_npkts; 2443 2444 RL_LOCK_ASSERT(sc); 2445 2446 sc->rxcycles = count; 2447 re_rxeof(sc, &rx_npkts); 2448 re_txeof(sc); 2449 2450 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2451 re_start_locked(ifp); 2452 2453 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2454 u_int16_t status; 2455 2456 status = CSR_READ_2(sc, RL_ISR); 2457 if (status == 0xffff) 2458 return (rx_npkts); 2459 if (status) 2460 CSR_WRITE_2(sc, RL_ISR, status); 2461 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2462 (sc->rl_flags & RL_FLAG_PCIE)) 2463 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2464 2465 /* 2466 * XXX check behaviour on receiver stalls. 2467 */ 2468 2469 if (status & RL_ISR_SYSTEM_ERR) { 2470 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2471 re_init_locked(sc); 2472 } 2473 } 2474 return (rx_npkts); 2475 } 2476 #endif /* DEVICE_POLLING */ 2477 2478 static int 2479 re_intr(void *arg) 2480 { 2481 struct rl_softc *sc; 2482 uint16_t status; 2483 2484 sc = arg; 2485 2486 status = CSR_READ_2(sc, RL_ISR); 2487 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2488 return (FILTER_STRAY); 2489 CSR_WRITE_2(sc, RL_IMR, 0); 2490 2491 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2492 2493 return (FILTER_HANDLED); 2494 } 2495 2496 static void 2497 re_int_task(void *arg, int npending) 2498 { 2499 struct rl_softc *sc; 2500 struct ifnet *ifp; 2501 u_int16_t status; 2502 int rval = 0; 2503 2504 sc = arg; 2505 ifp = sc->rl_ifp; 2506 2507 RL_LOCK(sc); 2508 2509 status = CSR_READ_2(sc, RL_ISR); 2510 CSR_WRITE_2(sc, RL_ISR, status); 2511 2512 if (sc->suspended || 2513 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2514 RL_UNLOCK(sc); 2515 return; 2516 } 2517 2518 #ifdef DEVICE_POLLING 2519 if (ifp->if_capenable & IFCAP_POLLING) { 2520 RL_UNLOCK(sc); 2521 return; 2522 } 2523 #endif 2524 2525 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2526 rval = re_rxeof(sc, NULL); 2527 2528 /* 2529 * Some chips will ignore a second TX request issued 2530 * while an existing transmission is in progress. If 2531 * the transmitter goes idle but there are still 2532 * packets waiting to be sent, we need to restart the 2533 * channel here to flush them out. This only seems to 2534 * be required with the PCIe devices. 2535 */ 2536 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2537 (sc->rl_flags & RL_FLAG_PCIE)) 2538 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2539 if (status & ( 2540 #ifdef RE_TX_MODERATION 2541 RL_ISR_TIMEOUT_EXPIRED| 2542 #else 2543 RL_ISR_TX_OK| 2544 #endif 2545 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2546 re_txeof(sc); 2547 2548 if (status & RL_ISR_SYSTEM_ERR) { 2549 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2550 re_init_locked(sc); 2551 } 2552 2553 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2554 re_start_locked(ifp); 2555 2556 RL_UNLOCK(sc); 2557 2558 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2559 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2560 return; 2561 } 2562 2563 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2564 } 2565 2566 static void 2567 re_intr_msi(void *xsc) 2568 { 2569 struct rl_softc *sc; 2570 struct ifnet *ifp; 2571 uint16_t intrs, status; 2572 2573 sc = xsc; 2574 RL_LOCK(sc); 2575 2576 ifp = sc->rl_ifp; 2577 #ifdef DEVICE_POLLING 2578 if (ifp->if_capenable & IFCAP_POLLING) { 2579 RL_UNLOCK(sc); 2580 return; 2581 } 2582 #endif 2583 /* Disable interrupts. */ 2584 CSR_WRITE_2(sc, RL_IMR, 0); 2585 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2586 RL_UNLOCK(sc); 2587 return; 2588 } 2589 2590 intrs = RL_INTRS_CPLUS; 2591 status = CSR_READ_2(sc, RL_ISR); 2592 CSR_WRITE_2(sc, RL_ISR, status); 2593 if (sc->rl_int_rx_act > 0) { 2594 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW | 2595 RL_ISR_RX_OVERRUN); 2596 status &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW | 2597 RL_ISR_RX_OVERRUN); 2598 } 2599 2600 if (status & (RL_ISR_TIMEOUT_EXPIRED | RL_ISR_RX_OK | RL_ISR_RX_ERR | 2601 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) { 2602 re_rxeof(sc, NULL); 2603 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2604 if (sc->rl_int_rx_mod != 0 && 2605 (status & (RL_ISR_RX_OK | RL_ISR_RX_ERR | 2606 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) != 0) { 2607 /* Rearm one-shot timer. */ 2608 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2609 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | 2610 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN); 2611 sc->rl_int_rx_act = 1; 2612 } else { 2613 intrs |= RL_ISR_RX_OK | RL_ISR_RX_ERR | 2614 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN; 2615 sc->rl_int_rx_act = 0; 2616 } 2617 } 2618 } 2619 2620 /* 2621 * Some chips will ignore a second TX request issued 2622 * while an existing transmission is in progress. If 2623 * the transmitter goes idle but there are still 2624 * packets waiting to be sent, we need to restart the 2625 * channel here to flush them out. This only seems to 2626 * be required with the PCIe devices. 2627 */ 2628 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2629 (sc->rl_flags & RL_FLAG_PCIE)) 2630 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2631 if (status & (RL_ISR_TX_OK | RL_ISR_TX_ERR | RL_ISR_TX_DESC_UNAVAIL)) 2632 re_txeof(sc); 2633 2634 if (status & RL_ISR_SYSTEM_ERR) { 2635 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2636 re_init_locked(sc); 2637 } 2638 2639 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2640 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2641 re_start_locked(ifp); 2642 CSR_WRITE_2(sc, RL_IMR, intrs); 2643 } 2644 RL_UNLOCK(sc); 2645 } 2646 2647 static int 2648 re_encap(struct rl_softc *sc, struct mbuf **m_head) 2649 { 2650 struct rl_txdesc *txd, *txd_last; 2651 bus_dma_segment_t segs[RL_NTXSEGS]; 2652 bus_dmamap_t map; 2653 struct mbuf *m_new; 2654 struct rl_desc *desc; 2655 int nsegs, prod; 2656 int i, error, ei, si; 2657 int padlen; 2658 uint32_t cmdstat, csum_flags, vlanctl; 2659 2660 RL_LOCK_ASSERT(sc); 2661 M_ASSERTPKTHDR((*m_head)); 2662 2663 /* 2664 * With some of the RealTek chips, using the checksum offload 2665 * support in conjunction with the autopadding feature results 2666 * in the transmission of corrupt frames. For example, if we 2667 * need to send a really small IP fragment that's less than 60 2668 * bytes in size, and IP header checksumming is enabled, the 2669 * resulting ethernet frame that appears on the wire will 2670 * have garbled payload. To work around this, if TX IP checksum 2671 * offload is enabled, we always manually pad short frames out 2672 * to the minimum ethernet frame size. 2673 */ 2674 if ((sc->rl_flags & RL_FLAG_AUTOPAD) == 0 && 2675 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN && 2676 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) { 2677 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2678 if (M_WRITABLE(*m_head) == 0) { 2679 /* Get a writable copy. */ 2680 m_new = m_dup(*m_head, M_DONTWAIT); 2681 m_freem(*m_head); 2682 if (m_new == NULL) { 2683 *m_head = NULL; 2684 return (ENOBUFS); 2685 } 2686 *m_head = m_new; 2687 } 2688 if ((*m_head)->m_next != NULL || 2689 M_TRAILINGSPACE(*m_head) < padlen) { 2690 m_new = m_defrag(*m_head, M_DONTWAIT); 2691 if (m_new == NULL) { 2692 m_freem(*m_head); 2693 *m_head = NULL; 2694 return (ENOBUFS); 2695 } 2696 } else 2697 m_new = *m_head; 2698 2699 /* 2700 * Manually pad short frames, and zero the pad space 2701 * to avoid leaking data. 2702 */ 2703 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2704 m_new->m_pkthdr.len += padlen; 2705 m_new->m_len = m_new->m_pkthdr.len; 2706 *m_head = m_new; 2707 } 2708 2709 prod = sc->rl_ldata.rl_tx_prodidx; 2710 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2711 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2712 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2713 if (error == EFBIG) { 2714 m_new = m_collapse(*m_head, M_DONTWAIT, RL_NTXSEGS); 2715 if (m_new == NULL) { 2716 m_freem(*m_head); 2717 *m_head = NULL; 2718 return (ENOBUFS); 2719 } 2720 *m_head = m_new; 2721 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2722 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2723 if (error != 0) { 2724 m_freem(*m_head); 2725 *m_head = NULL; 2726 return (error); 2727 } 2728 } else if (error != 0) 2729 return (error); 2730 if (nsegs == 0) { 2731 m_freem(*m_head); 2732 *m_head = NULL; 2733 return (EIO); 2734 } 2735 2736 /* Check for number of available descriptors. */ 2737 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2738 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2739 return (ENOBUFS); 2740 } 2741 2742 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2743 BUS_DMASYNC_PREWRITE); 2744 2745 /* 2746 * Set up checksum offload. Note: checksum offload bits must 2747 * appear in all descriptors of a multi-descriptor transmit 2748 * attempt. This is according to testing done with an 8169 2749 * chip. This is a requirement. 2750 */ 2751 vlanctl = 0; 2752 csum_flags = 0; 2753 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2754 if ((sc->rl_flags & RL_FLAG_DESCV2) != 0) { 2755 csum_flags |= RL_TDESC_CMD_LGSEND; 2756 vlanctl |= ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2757 RL_TDESC_CMD_MSSVALV2_SHIFT); 2758 } else { 2759 csum_flags |= RL_TDESC_CMD_LGSEND | 2760 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2761 RL_TDESC_CMD_MSSVAL_SHIFT); 2762 } 2763 } else { 2764 /* 2765 * Unconditionally enable IP checksum if TCP or UDP 2766 * checksum is required. Otherwise, TCP/UDP checksum 2767 * does't make effects. 2768 */ 2769 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) { 2770 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2771 csum_flags |= RL_TDESC_CMD_IPCSUM; 2772 if (((*m_head)->m_pkthdr.csum_flags & 2773 CSUM_TCP) != 0) 2774 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2775 if (((*m_head)->m_pkthdr.csum_flags & 2776 CSUM_UDP) != 0) 2777 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2778 } else { 2779 vlanctl |= RL_TDESC_CMD_IPCSUMV2; 2780 if (((*m_head)->m_pkthdr.csum_flags & 2781 CSUM_TCP) != 0) 2782 vlanctl |= RL_TDESC_CMD_TCPCSUMV2; 2783 if (((*m_head)->m_pkthdr.csum_flags & 2784 CSUM_UDP) != 0) 2785 vlanctl |= RL_TDESC_CMD_UDPCSUMV2; 2786 } 2787 } 2788 } 2789 2790 /* 2791 * Set up hardware VLAN tagging. Note: vlan tag info must 2792 * appear in all descriptors of a multi-descriptor 2793 * transmission attempt. 2794 */ 2795 if ((*m_head)->m_flags & M_VLANTAG) 2796 vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) | 2797 RL_TDESC_VLANCTL_TAG; 2798 2799 si = prod; 2800 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2801 desc = &sc->rl_ldata.rl_tx_list[prod]; 2802 desc->rl_vlanctl = htole32(vlanctl); 2803 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2804 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2805 cmdstat = segs[i].ds_len; 2806 if (i != 0) 2807 cmdstat |= RL_TDESC_CMD_OWN; 2808 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2809 cmdstat |= RL_TDESC_CMD_EOR; 2810 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2811 sc->rl_ldata.rl_tx_free--; 2812 } 2813 /* Update producer index. */ 2814 sc->rl_ldata.rl_tx_prodidx = prod; 2815 2816 /* Set EOF on the last descriptor. */ 2817 ei = RL_TX_DESC_PRV(sc, prod); 2818 desc = &sc->rl_ldata.rl_tx_list[ei]; 2819 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2820 2821 desc = &sc->rl_ldata.rl_tx_list[si]; 2822 /* Set SOF and transfer ownership of packet to the chip. */ 2823 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2824 2825 /* 2826 * Insure that the map for this transmission 2827 * is placed at the array index of the last descriptor 2828 * in this chain. (Swap last and first dmamaps.) 2829 */ 2830 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2831 map = txd->tx_dmamap; 2832 txd->tx_dmamap = txd_last->tx_dmamap; 2833 txd_last->tx_dmamap = map; 2834 txd_last->tx_m = *m_head; 2835 2836 return (0); 2837 } 2838 2839 static void 2840 re_start(struct ifnet *ifp) 2841 { 2842 struct rl_softc *sc; 2843 2844 sc = ifp->if_softc; 2845 RL_LOCK(sc); 2846 re_start_locked(ifp); 2847 RL_UNLOCK(sc); 2848 } 2849 2850 /* 2851 * Main transmit routine for C+ and gigE NICs. 2852 */ 2853 static void 2854 re_start_locked(struct ifnet *ifp) 2855 { 2856 struct rl_softc *sc; 2857 struct mbuf *m_head; 2858 int queued; 2859 2860 sc = ifp->if_softc; 2861 2862 #ifdef DEV_NETMAP 2863 /* XXX is this necessary ? */ 2864 if (ifp->if_capenable & IFCAP_NETMAP) { 2865 struct netmap_kring *kring = &NA(ifp)->tx_rings[0]; 2866 if (sc->rl_ldata.rl_tx_prodidx != kring->nr_hwcur) { 2867 /* kick the tx unit */ 2868 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2869 #ifdef RE_TX_MODERATION 2870 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2871 #endif 2872 sc->rl_watchdog_timer = 5; 2873 } 2874 return; 2875 } 2876 #endif /* DEV_NETMAP */ 2877 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2878 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) 2879 return; 2880 2881 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2882 sc->rl_ldata.rl_tx_free > 1;) { 2883 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2884 if (m_head == NULL) 2885 break; 2886 2887 if (re_encap(sc, &m_head) != 0) { 2888 if (m_head == NULL) 2889 break; 2890 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2891 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2892 break; 2893 } 2894 2895 /* 2896 * If there's a BPF listener, bounce a copy of this frame 2897 * to him. 2898 */ 2899 ETHER_BPF_MTAP(ifp, m_head); 2900 2901 queued++; 2902 } 2903 2904 if (queued == 0) { 2905 #ifdef RE_TX_MODERATION 2906 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2907 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2908 #endif 2909 return; 2910 } 2911 2912 /* Flush the TX descriptors */ 2913 2914 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2915 sc->rl_ldata.rl_tx_list_map, 2916 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2917 2918 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2919 2920 #ifdef RE_TX_MODERATION 2921 /* 2922 * Use the countdown timer for interrupt moderation. 2923 * 'TX done' interrupts are disabled. Instead, we reset the 2924 * countdown timer, which will begin counting until it hits 2925 * the value in the TIMERINT register, and then trigger an 2926 * interrupt. Each time we write to the TIMERCNT register, 2927 * the timer count is reset to 0. 2928 */ 2929 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2930 #endif 2931 2932 /* 2933 * Set a timeout in case the chip goes out to lunch. 2934 */ 2935 sc->rl_watchdog_timer = 5; 2936 } 2937 2938 static void 2939 re_set_jumbo(struct rl_softc *sc, int jumbo) 2940 { 2941 2942 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168E_VL) { 2943 pci_set_max_read_req(sc->rl_dev, 4096); 2944 return; 2945 } 2946 2947 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2948 if (jumbo != 0) { 2949 CSR_WRITE_1(sc, RL_CFG3, CSR_READ_1(sc, RL_CFG3) | 2950 RL_CFG3_JUMBO_EN0); 2951 switch (sc->rl_hwrev->rl_rev) { 2952 case RL_HWREV_8168DP: 2953 break; 2954 case RL_HWREV_8168E: 2955 CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) | 2956 0x01); 2957 break; 2958 default: 2959 CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) | 2960 RL_CFG4_JUMBO_EN1); 2961 } 2962 } else { 2963 CSR_WRITE_1(sc, RL_CFG3, CSR_READ_1(sc, RL_CFG3) & 2964 ~RL_CFG3_JUMBO_EN0); 2965 switch (sc->rl_hwrev->rl_rev) { 2966 case RL_HWREV_8168DP: 2967 break; 2968 case RL_HWREV_8168E: 2969 CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) & 2970 ~0x01); 2971 break; 2972 default: 2973 CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) & 2974 ~RL_CFG4_JUMBO_EN1); 2975 } 2976 } 2977 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2978 2979 switch (sc->rl_hwrev->rl_rev) { 2980 case RL_HWREV_8168DP: 2981 pci_set_max_read_req(sc->rl_dev, 4096); 2982 break; 2983 default: 2984 if (jumbo != 0) 2985 pci_set_max_read_req(sc->rl_dev, 512); 2986 else 2987 pci_set_max_read_req(sc->rl_dev, 4096); 2988 } 2989 } 2990 2991 static void 2992 re_init(void *xsc) 2993 { 2994 struct rl_softc *sc = xsc; 2995 2996 RL_LOCK(sc); 2997 re_init_locked(sc); 2998 RL_UNLOCK(sc); 2999 } 3000 3001 static void 3002 re_init_locked(struct rl_softc *sc) 3003 { 3004 struct ifnet *ifp = sc->rl_ifp; 3005 struct mii_data *mii; 3006 uint32_t reg; 3007 uint16_t cfg; 3008 union { 3009 uint32_t align_dummy; 3010 u_char eaddr[ETHER_ADDR_LEN]; 3011 } eaddr; 3012 3013 RL_LOCK_ASSERT(sc); 3014 3015 mii = device_get_softc(sc->rl_miibus); 3016 3017 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3018 return; 3019 3020 /* 3021 * Cancel pending I/O and free all RX/TX buffers. 3022 */ 3023 re_stop(sc); 3024 3025 /* Put controller into known state. */ 3026 re_reset(sc); 3027 3028 /* 3029 * For C+ mode, initialize the RX descriptors and mbufs. 3030 */ 3031 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3032 if (ifp->if_mtu > RL_MTU) { 3033 if (re_jrx_list_init(sc) != 0) { 3034 device_printf(sc->rl_dev, 3035 "no memory for jumbo RX buffers\n"); 3036 re_stop(sc); 3037 return; 3038 } 3039 /* Disable checksum offloading for jumbo frames. */ 3040 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_TSO4); 3041 ifp->if_hwassist &= ~(RE_CSUM_FEATURES | CSUM_TSO); 3042 } else { 3043 if (re_rx_list_init(sc) != 0) { 3044 device_printf(sc->rl_dev, 3045 "no memory for RX buffers\n"); 3046 re_stop(sc); 3047 return; 3048 } 3049 } 3050 re_set_jumbo(sc, ifp->if_mtu > RL_MTU); 3051 } else { 3052 if (re_rx_list_init(sc) != 0) { 3053 device_printf(sc->rl_dev, "no memory for RX buffers\n"); 3054 re_stop(sc); 3055 return; 3056 } 3057 if ((sc->rl_flags & RL_FLAG_PCIE) != 0 && 3058 pci_get_device(sc->rl_dev) != RT_DEVICEID_8101E) { 3059 if (ifp->if_mtu > RL_MTU) 3060 pci_set_max_read_req(sc->rl_dev, 512); 3061 else 3062 pci_set_max_read_req(sc->rl_dev, 4096); 3063 } 3064 } 3065 re_tx_list_init(sc); 3066 3067 /* 3068 * Enable C+ RX and TX mode, as well as VLAN stripping and 3069 * RX checksum offload. We must configure the C+ register 3070 * before all others. 3071 */ 3072 cfg = RL_CPLUSCMD_PCI_MRW; 3073 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 3074 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 3075 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3076 cfg |= RL_CPLUSCMD_VLANSTRIP; 3077 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) { 3078 cfg |= RL_CPLUSCMD_MACSTAT_DIS; 3079 /* XXX magic. */ 3080 cfg |= 0x0001; 3081 } else 3082 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB; 3083 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg); 3084 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SC || 3085 sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) { 3086 reg = 0x000fff00; 3087 if ((CSR_READ_1(sc, RL_CFG2) & RL_CFG2_PCI66MHZ) != 0) 3088 reg |= 0x000000ff; 3089 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) 3090 reg |= 0x00f00000; 3091 CSR_WRITE_4(sc, 0x7c, reg); 3092 /* Disable interrupt mitigation. */ 3093 CSR_WRITE_2(sc, 0xe2, 0); 3094 } 3095 /* 3096 * Disable TSO if interface MTU size is greater than MSS 3097 * allowed in controller. 3098 */ 3099 if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) { 3100 ifp->if_capenable &= ~IFCAP_TSO4; 3101 ifp->if_hwassist &= ~CSUM_TSO; 3102 } 3103 3104 /* 3105 * Init our MAC address. Even though the chipset 3106 * documentation doesn't mention it, we need to enter "Config 3107 * register write enable" mode to modify the ID registers. 3108 */ 3109 /* Copy MAC address on stack to align. */ 3110 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 3111 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 3112 CSR_WRITE_4(sc, RL_IDR0, 3113 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 3114 CSR_WRITE_4(sc, RL_IDR4, 3115 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 3116 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3117 3118 /* 3119 * Load the addresses of the RX and TX lists into the chip. 3120 */ 3121 3122 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 3123 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 3124 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 3125 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 3126 3127 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 3128 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 3129 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 3130 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 3131 3132 /* 3133 * Enable transmit and receive. 3134 */ 3135 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 3136 3137 /* 3138 * Set the initial TX configuration. 3139 */ 3140 if (sc->rl_testmode) { 3141 if (sc->rl_type == RL_8169) 3142 CSR_WRITE_4(sc, RL_TXCFG, 3143 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 3144 else 3145 CSR_WRITE_4(sc, RL_TXCFG, 3146 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 3147 } else 3148 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 3149 3150 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 3151 3152 /* 3153 * Set the initial RX configuration. 3154 */ 3155 re_set_rxmode(sc); 3156 3157 /* Configure interrupt moderation. */ 3158 if (sc->rl_type == RL_8169) { 3159 /* Magic from vendor. */ 3160 CSR_WRITE_2(sc, RL_INTRMOD, 0x5100); 3161 } 3162 3163 #ifdef DEVICE_POLLING 3164 /* 3165 * Disable interrupts if we are polling. 3166 */ 3167 if (ifp->if_capenable & IFCAP_POLLING) 3168 CSR_WRITE_2(sc, RL_IMR, 0); 3169 else /* otherwise ... */ 3170 #endif 3171 3172 /* 3173 * Enable interrupts. 3174 */ 3175 if (sc->rl_testmode) 3176 CSR_WRITE_2(sc, RL_IMR, 0); 3177 else 3178 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 3179 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 3180 3181 /* Set initial TX threshold */ 3182 sc->rl_txthresh = RL_TX_THRESH_INIT; 3183 3184 /* Start RX/TX process. */ 3185 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 3186 #ifdef notdef 3187 /* Enable receiver and transmitter. */ 3188 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 3189 #endif 3190 3191 /* 3192 * Initialize the timer interrupt register so that 3193 * a timer interrupt will be generated once the timer 3194 * reaches a certain number of ticks. The timer is 3195 * reloaded on each transmit. 3196 */ 3197 #ifdef RE_TX_MODERATION 3198 /* 3199 * Use timer interrupt register to moderate TX interrupt 3200 * moderation, which dramatically improves TX frame rate. 3201 */ 3202 if (sc->rl_type == RL_8169) 3203 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 3204 else 3205 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 3206 #else 3207 /* 3208 * Use timer interrupt register to moderate RX interrupt 3209 * moderation. 3210 */ 3211 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 && 3212 intr_filter == 0) { 3213 if (sc->rl_type == RL_8169) 3214 CSR_WRITE_4(sc, RL_TIMERINT_8169, 3215 RL_USECS(sc->rl_int_rx_mod)); 3216 } else { 3217 if (sc->rl_type == RL_8169) 3218 CSR_WRITE_4(sc, RL_TIMERINT_8169, RL_USECS(0)); 3219 } 3220 #endif 3221 3222 /* 3223 * For 8169 gigE NICs, set the max allowed RX packet 3224 * size so we can receive jumbo frames. 3225 */ 3226 if (sc->rl_type == RL_8169) { 3227 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3228 /* 3229 * For controllers that use new jumbo frame scheme, 3230 * set maximum size of jumbo frame depedning on 3231 * controller revisions. 3232 */ 3233 if (ifp->if_mtu > RL_MTU) 3234 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 3235 sc->rl_hwrev->rl_max_mtu + 3236 ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN + 3237 ETHER_CRC_LEN); 3238 else 3239 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 3240 RE_RX_DESC_BUFLEN); 3241 } else if ((sc->rl_flags & RL_FLAG_PCIE) != 0 && 3242 sc->rl_hwrev->rl_max_mtu == RL_MTU) { 3243 /* RTL810x has no jumbo frame support. */ 3244 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, RE_RX_DESC_BUFLEN); 3245 } else 3246 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 3247 } 3248 3249 if (sc->rl_testmode) 3250 return; 3251 3252 CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD); 3253 3254 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3255 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3256 3257 sc->rl_flags &= ~RL_FLAG_LINK; 3258 mii_mediachg(mii); 3259 3260 sc->rl_watchdog_timer = 0; 3261 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 3262 } 3263 3264 /* 3265 * Set media options. 3266 */ 3267 static int 3268 re_ifmedia_upd(struct ifnet *ifp) 3269 { 3270 struct rl_softc *sc; 3271 struct mii_data *mii; 3272 int error; 3273 3274 sc = ifp->if_softc; 3275 mii = device_get_softc(sc->rl_miibus); 3276 RL_LOCK(sc); 3277 error = mii_mediachg(mii); 3278 RL_UNLOCK(sc); 3279 3280 return (error); 3281 } 3282 3283 /* 3284 * Report current media status. 3285 */ 3286 static void 3287 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3288 { 3289 struct rl_softc *sc; 3290 struct mii_data *mii; 3291 3292 sc = ifp->if_softc; 3293 mii = device_get_softc(sc->rl_miibus); 3294 3295 RL_LOCK(sc); 3296 mii_pollstat(mii); 3297 ifmr->ifm_active = mii->mii_media_active; 3298 ifmr->ifm_status = mii->mii_media_status; 3299 RL_UNLOCK(sc); 3300 } 3301 3302 static int 3303 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3304 { 3305 struct rl_softc *sc = ifp->if_softc; 3306 struct ifreq *ifr = (struct ifreq *) data; 3307 struct mii_data *mii; 3308 uint32_t rev; 3309 int error = 0; 3310 3311 switch (command) { 3312 case SIOCSIFMTU: 3313 if (ifr->ifr_mtu < ETHERMIN || 3314 ifr->ifr_mtu > sc->rl_hwrev->rl_max_mtu) { 3315 error = EINVAL; 3316 break; 3317 } 3318 RL_LOCK(sc); 3319 if (ifp->if_mtu != ifr->ifr_mtu) { 3320 ifp->if_mtu = ifr->ifr_mtu; 3321 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 3322 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3323 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3324 re_init_locked(sc); 3325 } 3326 if (ifp->if_mtu > RL_TSO_MTU && 3327 (ifp->if_capenable & IFCAP_TSO4) != 0) { 3328 ifp->if_capenable &= ~(IFCAP_TSO4 | 3329 IFCAP_VLAN_HWTSO); 3330 ifp->if_hwassist &= ~CSUM_TSO; 3331 } 3332 VLAN_CAPABILITIES(ifp); 3333 } 3334 RL_UNLOCK(sc); 3335 break; 3336 case SIOCSIFFLAGS: 3337 RL_LOCK(sc); 3338 if ((ifp->if_flags & IFF_UP) != 0) { 3339 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3340 if (((ifp->if_flags ^ sc->rl_if_flags) 3341 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 3342 re_set_rxmode(sc); 3343 } else 3344 re_init_locked(sc); 3345 } else { 3346 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3347 re_stop(sc); 3348 } 3349 sc->rl_if_flags = ifp->if_flags; 3350 RL_UNLOCK(sc); 3351 break; 3352 case SIOCADDMULTI: 3353 case SIOCDELMULTI: 3354 RL_LOCK(sc); 3355 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3356 re_set_rxmode(sc); 3357 RL_UNLOCK(sc); 3358 break; 3359 case SIOCGIFMEDIA: 3360 case SIOCSIFMEDIA: 3361 mii = device_get_softc(sc->rl_miibus); 3362 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3363 break; 3364 case SIOCSIFCAP: 3365 { 3366 int mask, reinit; 3367 3368 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3369 reinit = 0; 3370 #ifdef DEVICE_POLLING 3371 if (mask & IFCAP_POLLING) { 3372 if (ifr->ifr_reqcap & IFCAP_POLLING) { 3373 error = ether_poll_register(re_poll, ifp); 3374 if (error) 3375 return (error); 3376 RL_LOCK(sc); 3377 /* Disable interrupts */ 3378 CSR_WRITE_2(sc, RL_IMR, 0x0000); 3379 ifp->if_capenable |= IFCAP_POLLING; 3380 RL_UNLOCK(sc); 3381 } else { 3382 error = ether_poll_deregister(ifp); 3383 /* Enable interrupts. */ 3384 RL_LOCK(sc); 3385 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 3386 ifp->if_capenable &= ~IFCAP_POLLING; 3387 RL_UNLOCK(sc); 3388 } 3389 } 3390 #endif /* DEVICE_POLLING */ 3391 RL_LOCK(sc); 3392 if ((mask & IFCAP_TXCSUM) != 0 && 3393 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 3394 ifp->if_capenable ^= IFCAP_TXCSUM; 3395 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) { 3396 rev = sc->rl_hwrev->rl_rev; 3397 if (rev == RL_HWREV_8168C || 3398 rev == RL_HWREV_8168C_SPIN2) 3399 ifp->if_hwassist |= CSUM_TCP | CSUM_UDP; 3400 else 3401 ifp->if_hwassist |= RE_CSUM_FEATURES; 3402 } else 3403 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 3404 reinit = 1; 3405 } 3406 if ((mask & IFCAP_RXCSUM) != 0 && 3407 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 3408 ifp->if_capenable ^= IFCAP_RXCSUM; 3409 reinit = 1; 3410 } 3411 if ((mask & IFCAP_TSO4) != 0 && 3412 (ifp->if_capabilities & IFCAP_TSO) != 0) { 3413 ifp->if_capenable ^= IFCAP_TSO4; 3414 if ((IFCAP_TSO4 & ifp->if_capenable) != 0) 3415 ifp->if_hwassist |= CSUM_TSO; 3416 else 3417 ifp->if_hwassist &= ~CSUM_TSO; 3418 if (ifp->if_mtu > RL_TSO_MTU && 3419 (ifp->if_capenable & IFCAP_TSO4) != 0) { 3420 ifp->if_capenable &= ~IFCAP_TSO4; 3421 ifp->if_hwassist &= ~CSUM_TSO; 3422 } 3423 } 3424 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 3425 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 3426 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 3427 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3428 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 3429 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 3430 /* TSO over VLAN requires VLAN hardware tagging. */ 3431 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 3432 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 3433 reinit = 1; 3434 } 3435 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 3436 (mask & (IFCAP_HWCSUM | IFCAP_TSO4 | 3437 IFCAP_VLAN_HWTSO)) != 0) 3438 reinit = 1; 3439 if ((mask & IFCAP_WOL) != 0 && 3440 (ifp->if_capabilities & IFCAP_WOL) != 0) { 3441 if ((mask & IFCAP_WOL_UCAST) != 0) 3442 ifp->if_capenable ^= IFCAP_WOL_UCAST; 3443 if ((mask & IFCAP_WOL_MCAST) != 0) 3444 ifp->if_capenable ^= IFCAP_WOL_MCAST; 3445 if ((mask & IFCAP_WOL_MAGIC) != 0) 3446 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 3447 } 3448 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) { 3449 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3450 re_init_locked(sc); 3451 } 3452 RL_UNLOCK(sc); 3453 VLAN_CAPABILITIES(ifp); 3454 } 3455 break; 3456 default: 3457 error = ether_ioctl(ifp, command, data); 3458 break; 3459 } 3460 3461 return (error); 3462 } 3463 3464 static void 3465 re_watchdog(struct rl_softc *sc) 3466 { 3467 struct ifnet *ifp; 3468 3469 RL_LOCK_ASSERT(sc); 3470 3471 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 3472 return; 3473 3474 ifp = sc->rl_ifp; 3475 re_txeof(sc); 3476 if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) { 3477 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 3478 "-- recovering\n"); 3479 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3480 re_start_locked(ifp); 3481 return; 3482 } 3483 3484 if_printf(ifp, "watchdog timeout\n"); 3485 ifp->if_oerrors++; 3486 3487 re_rxeof(sc, NULL); 3488 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3489 re_init_locked(sc); 3490 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3491 re_start_locked(ifp); 3492 } 3493 3494 /* 3495 * Stop the adapter and free any mbufs allocated to the 3496 * RX and TX lists. 3497 */ 3498 static void 3499 re_stop(struct rl_softc *sc) 3500 { 3501 int i; 3502 struct ifnet *ifp; 3503 struct rl_txdesc *txd; 3504 struct rl_rxdesc *rxd; 3505 3506 RL_LOCK_ASSERT(sc); 3507 3508 ifp = sc->rl_ifp; 3509 3510 sc->rl_watchdog_timer = 0; 3511 callout_stop(&sc->rl_stat_callout); 3512 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3513 3514 /* 3515 * Disable accepting frames to put RX MAC into idle state. 3516 * Otherwise it's possible to get frames while stop command 3517 * execution is in progress and controller can DMA the frame 3518 * to already freed RX buffer during that period. 3519 */ 3520 CSR_WRITE_4(sc, RL_RXCFG, CSR_READ_4(sc, RL_RXCFG) & 3521 ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_MULTI | 3522 RL_RXCFG_RX_BROAD)); 3523 3524 if ((sc->rl_flags & RL_FLAG_WAIT_TXPOLL) != 0) { 3525 for (i = RL_TIMEOUT; i > 0; i--) { 3526 if ((CSR_READ_1(sc, sc->rl_txstart) & 3527 RL_TXSTART_START) == 0) 3528 break; 3529 DELAY(20); 3530 } 3531 if (i == 0) 3532 device_printf(sc->rl_dev, 3533 "stopping TX poll timed out!\n"); 3534 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 3535 } else if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0) { 3536 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB | 3537 RL_CMD_RX_ENB); 3538 if ((sc->rl_flags & RL_FLAG_CMDSTOP_WAIT_TXQ) != 0) { 3539 for (i = RL_TIMEOUT; i > 0; i--) { 3540 if ((CSR_READ_4(sc, RL_TXCFG) & 3541 RL_TXCFG_QUEUE_EMPTY) != 0) 3542 break; 3543 DELAY(100); 3544 } 3545 if (i == 0) 3546 device_printf(sc->rl_dev, 3547 "stopping TXQ timed out!\n"); 3548 } 3549 } else 3550 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 3551 DELAY(1000); 3552 CSR_WRITE_2(sc, RL_IMR, 0x0000); 3553 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 3554 3555 if (sc->rl_head != NULL) { 3556 m_freem(sc->rl_head); 3557 sc->rl_head = sc->rl_tail = NULL; 3558 } 3559 3560 /* Free the TX list buffers. */ 3561 3562 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 3563 txd = &sc->rl_ldata.rl_tx_desc[i]; 3564 if (txd->tx_m != NULL) { 3565 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 3566 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3567 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 3568 txd->tx_dmamap); 3569 m_freem(txd->tx_m); 3570 txd->tx_m = NULL; 3571 } 3572 } 3573 3574 /* Free the RX list buffers. */ 3575 3576 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 3577 rxd = &sc->rl_ldata.rl_rx_desc[i]; 3578 if (rxd->rx_m != NULL) { 3579 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 3580 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3581 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 3582 rxd->rx_dmamap); 3583 m_freem(rxd->rx_m); 3584 rxd->rx_m = NULL; 3585 } 3586 } 3587 } 3588 3589 /* 3590 * Device suspend routine. Stop the interface and save some PCI 3591 * settings in case the BIOS doesn't restore them properly on 3592 * resume. 3593 */ 3594 static int 3595 re_suspend(device_t dev) 3596 { 3597 struct rl_softc *sc; 3598 3599 sc = device_get_softc(dev); 3600 3601 RL_LOCK(sc); 3602 re_stop(sc); 3603 re_setwol(sc); 3604 sc->suspended = 1; 3605 RL_UNLOCK(sc); 3606 3607 return (0); 3608 } 3609 3610 /* 3611 * Device resume routine. Restore some PCI settings in case the BIOS 3612 * doesn't, re-enable busmastering, and restart the interface if 3613 * appropriate. 3614 */ 3615 static int 3616 re_resume(device_t dev) 3617 { 3618 struct rl_softc *sc; 3619 struct ifnet *ifp; 3620 3621 sc = device_get_softc(dev); 3622 3623 RL_LOCK(sc); 3624 3625 ifp = sc->rl_ifp; 3626 /* Take controller out of sleep mode. */ 3627 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3628 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3629 CSR_WRITE_1(sc, RL_GPIO, 3630 CSR_READ_1(sc, RL_GPIO) | 0x01); 3631 } 3632 3633 /* 3634 * Clear WOL matching such that normal Rx filtering 3635 * wouldn't interfere with WOL patterns. 3636 */ 3637 re_clrwol(sc); 3638 3639 /* reinitialize interface if necessary */ 3640 if (ifp->if_flags & IFF_UP) 3641 re_init_locked(sc); 3642 3643 sc->suspended = 0; 3644 RL_UNLOCK(sc); 3645 3646 return (0); 3647 } 3648 3649 /* 3650 * Stop all chip I/O so that the kernel's probe routines don't 3651 * get confused by errant DMAs when rebooting. 3652 */ 3653 static int 3654 re_shutdown(device_t dev) 3655 { 3656 struct rl_softc *sc; 3657 3658 sc = device_get_softc(dev); 3659 3660 RL_LOCK(sc); 3661 re_stop(sc); 3662 /* 3663 * Mark interface as down since otherwise we will panic if 3664 * interrupt comes in later on, which can happen in some 3665 * cases. 3666 */ 3667 sc->rl_ifp->if_flags &= ~IFF_UP; 3668 re_setwol(sc); 3669 RL_UNLOCK(sc); 3670 3671 return (0); 3672 } 3673 3674 static void 3675 re_set_linkspeed(struct rl_softc *sc) 3676 { 3677 struct mii_softc *miisc; 3678 struct mii_data *mii; 3679 int aneg, i, phyno; 3680 3681 RL_LOCK_ASSERT(sc); 3682 3683 mii = device_get_softc(sc->rl_miibus); 3684 mii_pollstat(mii); 3685 aneg = 0; 3686 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 3687 (IFM_ACTIVE | IFM_AVALID)) { 3688 switch IFM_SUBTYPE(mii->mii_media_active) { 3689 case IFM_10_T: 3690 case IFM_100_TX: 3691 return; 3692 case IFM_1000_T: 3693 aneg++; 3694 break; 3695 default: 3696 break; 3697 } 3698 } 3699 miisc = LIST_FIRST(&mii->mii_phys); 3700 phyno = miisc->mii_phy; 3701 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 3702 PHY_RESET(miisc); 3703 re_miibus_writereg(sc->rl_dev, phyno, MII_100T2CR, 0); 3704 re_miibus_writereg(sc->rl_dev, phyno, 3705 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 3706 re_miibus_writereg(sc->rl_dev, phyno, 3707 MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 3708 DELAY(1000); 3709 if (aneg != 0) { 3710 /* 3711 * Poll link state until re(4) get a 10/100Mbps link. 3712 */ 3713 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 3714 mii_pollstat(mii); 3715 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 3716 == (IFM_ACTIVE | IFM_AVALID)) { 3717 switch (IFM_SUBTYPE(mii->mii_media_active)) { 3718 case IFM_10_T: 3719 case IFM_100_TX: 3720 return; 3721 default: 3722 break; 3723 } 3724 } 3725 RL_UNLOCK(sc); 3726 pause("relnk", hz); 3727 RL_LOCK(sc); 3728 } 3729 if (i == MII_ANEGTICKS_GIGE) 3730 device_printf(sc->rl_dev, 3731 "establishing a link failed, WOL may not work!"); 3732 } 3733 /* 3734 * No link, force MAC to have 100Mbps, full-duplex link. 3735 * MAC does not require reprogramming on resolved speed/duplex, 3736 * so this is just for completeness. 3737 */ 3738 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 3739 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 3740 } 3741 3742 static void 3743 re_setwol(struct rl_softc *sc) 3744 { 3745 struct ifnet *ifp; 3746 int pmc; 3747 uint16_t pmstat; 3748 uint8_t v; 3749 3750 RL_LOCK_ASSERT(sc); 3751 3752 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3753 return; 3754 3755 ifp = sc->rl_ifp; 3756 /* Put controller into sleep mode. */ 3757 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3758 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3759 CSR_WRITE_1(sc, RL_GPIO, 3760 CSR_READ_1(sc, RL_GPIO) & ~0x01); 3761 } 3762 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 3763 re_set_rxmode(sc); 3764 if ((sc->rl_flags & RL_FLAG_WOL_MANLINK) != 0) 3765 re_set_linkspeed(sc); 3766 if ((sc->rl_flags & RL_FLAG_WOLRXENB) != 0) 3767 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB); 3768 } 3769 /* Enable config register write. */ 3770 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3771 3772 /* Enable PME. */ 3773 v = CSR_READ_1(sc, RL_CFG1); 3774 v &= ~RL_CFG1_PME; 3775 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3776 v |= RL_CFG1_PME; 3777 CSR_WRITE_1(sc, RL_CFG1, v); 3778 3779 v = CSR_READ_1(sc, RL_CFG3); 3780 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3781 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3782 v |= RL_CFG3_WOL_MAGIC; 3783 CSR_WRITE_1(sc, RL_CFG3, v); 3784 3785 v = CSR_READ_1(sc, RL_CFG5); 3786 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST | 3787 RL_CFG5_WOL_LANWAKE); 3788 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 3789 v |= RL_CFG5_WOL_UCAST; 3790 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 3791 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 3792 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3793 v |= RL_CFG5_WOL_LANWAKE; 3794 CSR_WRITE_1(sc, RL_CFG5, v); 3795 3796 /* Config register write done. */ 3797 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3798 3799 if ((ifp->if_capenable & IFCAP_WOL) != 0 && 3800 (sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) 3801 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) & ~0x80); 3802 /* 3803 * It seems that hardware resets its link speed to 100Mbps in 3804 * power down mode so switching to 100Mbps in driver is not 3805 * needed. 3806 */ 3807 3808 /* Request PME if WOL is requested. */ 3809 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 3810 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3811 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3812 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3813 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 3814 } 3815 3816 static void 3817 re_clrwol(struct rl_softc *sc) 3818 { 3819 int pmc; 3820 uint8_t v; 3821 3822 RL_LOCK_ASSERT(sc); 3823 3824 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3825 return; 3826 3827 /* Enable config register write. */ 3828 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3829 3830 v = CSR_READ_1(sc, RL_CFG3); 3831 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3832 CSR_WRITE_1(sc, RL_CFG3, v); 3833 3834 /* Config register write done. */ 3835 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3836 3837 v = CSR_READ_1(sc, RL_CFG5); 3838 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3839 v &= ~RL_CFG5_WOL_LANWAKE; 3840 CSR_WRITE_1(sc, RL_CFG5, v); 3841 } 3842 3843 static void 3844 re_add_sysctls(struct rl_softc *sc) 3845 { 3846 struct sysctl_ctx_list *ctx; 3847 struct sysctl_oid_list *children; 3848 int error; 3849 3850 ctx = device_get_sysctl_ctx(sc->rl_dev); 3851 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev)); 3852 3853 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "stats", 3854 CTLTYPE_INT | CTLFLAG_RW, sc, 0, re_sysctl_stats, "I", 3855 "Statistics Information"); 3856 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) 3857 return; 3858 3859 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "int_rx_mod", 3860 CTLTYPE_INT | CTLFLAG_RW, &sc->rl_int_rx_mod, 0, 3861 sysctl_hw_re_int_mod, "I", "re RX interrupt moderation"); 3862 /* Pull in device tunables. */ 3863 sc->rl_int_rx_mod = RL_TIMER_DEFAULT; 3864 error = resource_int_value(device_get_name(sc->rl_dev), 3865 device_get_unit(sc->rl_dev), "int_rx_mod", &sc->rl_int_rx_mod); 3866 if (error == 0) { 3867 if (sc->rl_int_rx_mod < RL_TIMER_MIN || 3868 sc->rl_int_rx_mod > RL_TIMER_MAX) { 3869 device_printf(sc->rl_dev, "int_rx_mod value out of " 3870 "range; using default: %d\n", 3871 RL_TIMER_DEFAULT); 3872 sc->rl_int_rx_mod = RL_TIMER_DEFAULT; 3873 } 3874 } 3875 3876 } 3877 3878 static int 3879 re_sysctl_stats(SYSCTL_HANDLER_ARGS) 3880 { 3881 struct rl_softc *sc; 3882 struct rl_stats *stats; 3883 int error, i, result; 3884 3885 result = -1; 3886 error = sysctl_handle_int(oidp, &result, 0, req); 3887 if (error || req->newptr == NULL) 3888 return (error); 3889 3890 if (result == 1) { 3891 sc = (struct rl_softc *)arg1; 3892 RL_LOCK(sc); 3893 if ((sc->rl_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 3894 RL_UNLOCK(sc); 3895 goto done; 3896 } 3897 bus_dmamap_sync(sc->rl_ldata.rl_stag, 3898 sc->rl_ldata.rl_smap, BUS_DMASYNC_PREREAD); 3899 CSR_WRITE_4(sc, RL_DUMPSTATS_HI, 3900 RL_ADDR_HI(sc->rl_ldata.rl_stats_addr)); 3901 CSR_WRITE_4(sc, RL_DUMPSTATS_LO, 3902 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr)); 3903 CSR_WRITE_4(sc, RL_DUMPSTATS_LO, 3904 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr | 3905 RL_DUMPSTATS_START)); 3906 for (i = RL_TIMEOUT; i > 0; i--) { 3907 if ((CSR_READ_4(sc, RL_DUMPSTATS_LO) & 3908 RL_DUMPSTATS_START) == 0) 3909 break; 3910 DELAY(1000); 3911 } 3912 bus_dmamap_sync(sc->rl_ldata.rl_stag, 3913 sc->rl_ldata.rl_smap, BUS_DMASYNC_POSTREAD); 3914 RL_UNLOCK(sc); 3915 if (i == 0) { 3916 device_printf(sc->rl_dev, 3917 "DUMP statistics request timedout\n"); 3918 return (ETIMEDOUT); 3919 } 3920 done: 3921 stats = sc->rl_ldata.rl_stats; 3922 printf("%s statistics:\n", device_get_nameunit(sc->rl_dev)); 3923 printf("Tx frames : %ju\n", 3924 (uintmax_t)le64toh(stats->rl_tx_pkts)); 3925 printf("Rx frames : %ju\n", 3926 (uintmax_t)le64toh(stats->rl_rx_pkts)); 3927 printf("Tx errors : %ju\n", 3928 (uintmax_t)le64toh(stats->rl_tx_errs)); 3929 printf("Rx errors : %u\n", 3930 le32toh(stats->rl_rx_errs)); 3931 printf("Rx missed frames : %u\n", 3932 (uint32_t)le16toh(stats->rl_missed_pkts)); 3933 printf("Rx frame alignment errs : %u\n", 3934 (uint32_t)le16toh(stats->rl_rx_framealign_errs)); 3935 printf("Tx single collisions : %u\n", 3936 le32toh(stats->rl_tx_onecoll)); 3937 printf("Tx multiple collisions : %u\n", 3938 le32toh(stats->rl_tx_multicolls)); 3939 printf("Rx unicast frames : %ju\n", 3940 (uintmax_t)le64toh(stats->rl_rx_ucasts)); 3941 printf("Rx broadcast frames : %ju\n", 3942 (uintmax_t)le64toh(stats->rl_rx_bcasts)); 3943 printf("Rx multicast frames : %u\n", 3944 le32toh(stats->rl_rx_mcasts)); 3945 printf("Tx aborts : %u\n", 3946 (uint32_t)le16toh(stats->rl_tx_aborts)); 3947 printf("Tx underruns : %u\n", 3948 (uint32_t)le16toh(stats->rl_rx_underruns)); 3949 } 3950 3951 return (error); 3952 } 3953 3954 static int 3955 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3956 { 3957 int error, value; 3958 3959 if (arg1 == NULL) 3960 return (EINVAL); 3961 value = *(int *)arg1; 3962 error = sysctl_handle_int(oidp, &value, 0, req); 3963 if (error || req->newptr == NULL) 3964 return (error); 3965 if (value < low || value > high) 3966 return (EINVAL); 3967 *(int *)arg1 = value; 3968 3969 return (0); 3970 } 3971 3972 static int 3973 sysctl_hw_re_int_mod(SYSCTL_HANDLER_ARGS) 3974 { 3975 3976 return (sysctl_int_range(oidp, arg1, arg2, req, RL_TIMER_MIN, 3977 RL_TIMER_MAX)); 3978 } 3979