1 /*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44 /* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111 #ifdef HAVE_KERNEL_OPTION_HEADERS 112 #include "opt_device_polling.h" 113 #endif 114 115 #include <sys/param.h> 116 #include <sys/endian.h> 117 #include <sys/systm.h> 118 #include <sys/sockio.h> 119 #include <sys/mbuf.h> 120 #include <sys/malloc.h> 121 #include <sys/module.h> 122 #include <sys/kernel.h> 123 #include <sys/socket.h> 124 #include <sys/lock.h> 125 #include <sys/mutex.h> 126 #include <sys/sysctl.h> 127 #include <sys/taskqueue.h> 128 129 #include <net/if.h> 130 #include <net/if_var.h> 131 #include <net/if_arp.h> 132 #include <net/ethernet.h> 133 #include <net/if_dl.h> 134 #include <net/if_media.h> 135 #include <net/if_types.h> 136 #include <net/if_vlan_var.h> 137 138 #include <net/bpf.h> 139 140 #include <machine/bus.h> 141 #include <machine/resource.h> 142 #include <sys/bus.h> 143 #include <sys/rman.h> 144 145 #include <dev/mii/mii.h> 146 #include <dev/mii/miivar.h> 147 148 #include <dev/pci/pcireg.h> 149 #include <dev/pci/pcivar.h> 150 151 #include <pci/if_rlreg.h> 152 153 MODULE_DEPEND(re, pci, 1, 1, 1); 154 MODULE_DEPEND(re, ether, 1, 1, 1); 155 MODULE_DEPEND(re, miibus, 1, 1, 1); 156 157 /* "device miibus" required. See GENERIC if you get errors here. */ 158 #include "miibus_if.h" 159 160 /* Tunables. */ 161 static int intr_filter = 0; 162 TUNABLE_INT("hw.re.intr_filter", &intr_filter); 163 static int msi_disable = 0; 164 TUNABLE_INT("hw.re.msi_disable", &msi_disable); 165 static int msix_disable = 0; 166 TUNABLE_INT("hw.re.msix_disable", &msix_disable); 167 static int prefer_iomap = 0; 168 TUNABLE_INT("hw.re.prefer_iomap", &prefer_iomap); 169 170 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 171 172 /* 173 * Various supported device vendors/types and their names. 174 */ 175 static const struct rl_type re_devs[] = { 176 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0, 177 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 178 { DLINK_VENDORID, DLINK_DEVICEID_530T_REVC, 0, 179 "D-Link DGE-530(T) Gigabit Ethernet Adapter" }, 180 { RT_VENDORID, RT_DEVICEID_8139, 0, 181 "RealTek 8139C+ 10/100BaseTX" }, 182 { RT_VENDORID, RT_DEVICEID_8101E, 0, 183 "RealTek 810xE PCIe 10/100baseTX" }, 184 { RT_VENDORID, RT_DEVICEID_8168, 0, 185 "RealTek 8168/8111 B/C/CP/D/DP/E/F/G PCIe Gigabit Ethernet" }, 186 { RT_VENDORID, RT_DEVICEID_8169, 0, 187 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" }, 188 { RT_VENDORID, RT_DEVICEID_8169SC, 0, 189 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 190 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0, 191 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 192 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0, 193 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 194 { USR_VENDORID, USR_DEVICEID_997902, 0, 195 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 196 }; 197 198 static const struct rl_hwrev re_hwrevs[] = { 199 { RL_HWREV_8139, RL_8139, "", RL_MTU }, 200 { RL_HWREV_8139A, RL_8139, "A", RL_MTU }, 201 { RL_HWREV_8139AG, RL_8139, "A-G", RL_MTU }, 202 { RL_HWREV_8139B, RL_8139, "B", RL_MTU }, 203 { RL_HWREV_8130, RL_8139, "8130", RL_MTU }, 204 { RL_HWREV_8139C, RL_8139, "C", RL_MTU }, 205 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C", RL_MTU }, 206 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+", RL_MTU }, 207 { RL_HWREV_8168B_SPIN1, RL_8169, "8168", RL_JUMBO_MTU }, 208 { RL_HWREV_8169, RL_8169, "8169", RL_JUMBO_MTU }, 209 { RL_HWREV_8169S, RL_8169, "8169S", RL_JUMBO_MTU }, 210 { RL_HWREV_8110S, RL_8169, "8110S", RL_JUMBO_MTU }, 211 { RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB", RL_JUMBO_MTU }, 212 { RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU }, 213 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL", RL_JUMBO_MTU }, 214 { RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU }, 215 { RL_HWREV_8100, RL_8139, "8100", RL_MTU }, 216 { RL_HWREV_8101, RL_8139, "8101", RL_MTU }, 217 { RL_HWREV_8100E, RL_8169, "8100E", RL_MTU }, 218 { RL_HWREV_8101E, RL_8169, "8101E", RL_MTU }, 219 { RL_HWREV_8102E, RL_8169, "8102E", RL_MTU }, 220 { RL_HWREV_8102EL, RL_8169, "8102EL", RL_MTU }, 221 { RL_HWREV_8102EL_SPIN1, RL_8169, "8102EL", RL_MTU }, 222 { RL_HWREV_8103E, RL_8169, "8103E", RL_MTU }, 223 { RL_HWREV_8401E, RL_8169, "8401E", RL_MTU }, 224 { RL_HWREV_8402, RL_8169, "8402", RL_MTU }, 225 { RL_HWREV_8105E, RL_8169, "8105E", RL_MTU }, 226 { RL_HWREV_8105E_SPIN1, RL_8169, "8105E", RL_MTU }, 227 { RL_HWREV_8106E, RL_8169, "8106E", RL_MTU }, 228 { RL_HWREV_8168B_SPIN2, RL_8169, "8168", RL_JUMBO_MTU }, 229 { RL_HWREV_8168B_SPIN3, RL_8169, "8168", RL_JUMBO_MTU }, 230 { RL_HWREV_8168C, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K }, 231 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K }, 232 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP", RL_JUMBO_MTU_6K }, 233 { RL_HWREV_8168D, RL_8169, "8168D/8111D", RL_JUMBO_MTU_9K }, 234 { RL_HWREV_8168DP, RL_8169, "8168DP/8111DP", RL_JUMBO_MTU_9K }, 235 { RL_HWREV_8168E, RL_8169, "8168E/8111E", RL_JUMBO_MTU_9K}, 236 { RL_HWREV_8168E_VL, RL_8169, "8168E/8111E-VL", RL_JUMBO_MTU_6K}, 237 { RL_HWREV_8168EP, RL_8169, "8168EP/8111EP", RL_JUMBO_MTU_9K}, 238 { RL_HWREV_8168F, RL_8169, "8168F/8111F", RL_JUMBO_MTU_9K}, 239 { RL_HWREV_8168G, RL_8169, "8168G/8111G", RL_JUMBO_MTU_9K}, 240 { RL_HWREV_8168GU, RL_8169, "8168GU/8111GU", RL_JUMBO_MTU_9K}, 241 { RL_HWREV_8411, RL_8169, "8411", RL_JUMBO_MTU_9K}, 242 { RL_HWREV_8411B, RL_8169, "8411B", RL_JUMBO_MTU_9K}, 243 { 0, 0, NULL, 0 } 244 }; 245 246 static int re_probe (device_t); 247 static int re_attach (device_t); 248 static int re_detach (device_t); 249 250 static int re_encap (struct rl_softc *, struct mbuf **); 251 252 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 253 static int re_allocmem (device_t, struct rl_softc *); 254 static __inline void re_discard_rxbuf 255 (struct rl_softc *, int); 256 static int re_newbuf (struct rl_softc *, int); 257 static int re_jumbo_newbuf (struct rl_softc *, int); 258 static int re_rx_list_init (struct rl_softc *); 259 static int re_jrx_list_init (struct rl_softc *); 260 static int re_tx_list_init (struct rl_softc *); 261 #ifdef RE_FIXUP_RX 262 static __inline void re_fixup_rx 263 (struct mbuf *); 264 #endif 265 static int re_rxeof (struct rl_softc *, int *); 266 static void re_txeof (struct rl_softc *); 267 #ifdef DEVICE_POLLING 268 static int re_poll (struct ifnet *, enum poll_cmd, int); 269 static int re_poll_locked (struct ifnet *, enum poll_cmd, int); 270 #endif 271 static int re_intr (void *); 272 static void re_intr_msi (void *); 273 static void re_tick (void *); 274 static void re_int_task (void *, int); 275 static void re_start (struct ifnet *); 276 static void re_start_locked (struct ifnet *); 277 static int re_ioctl (struct ifnet *, u_long, caddr_t); 278 static void re_init (void *); 279 static void re_init_locked (struct rl_softc *); 280 static void re_stop (struct rl_softc *); 281 static void re_watchdog (struct rl_softc *); 282 static int re_suspend (device_t); 283 static int re_resume (device_t); 284 static int re_shutdown (device_t); 285 static int re_ifmedia_upd (struct ifnet *); 286 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 287 288 static void re_eeprom_putbyte (struct rl_softc *, int); 289 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 290 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 291 static int re_gmii_readreg (device_t, int, int); 292 static int re_gmii_writereg (device_t, int, int, int); 293 294 static int re_miibus_readreg (device_t, int, int); 295 static int re_miibus_writereg (device_t, int, int, int); 296 static void re_miibus_statchg (device_t); 297 298 static void re_set_jumbo (struct rl_softc *, int); 299 static void re_set_rxmode (struct rl_softc *); 300 static void re_reset (struct rl_softc *); 301 static void re_setwol (struct rl_softc *); 302 static void re_clrwol (struct rl_softc *); 303 static void re_set_linkspeed (struct rl_softc *); 304 305 #ifdef DEV_NETMAP /* see ixgbe.c for details */ 306 #include <dev/netmap/if_re_netmap.h> 307 #endif /* !DEV_NETMAP */ 308 309 #ifdef RE_DIAG 310 static int re_diag (struct rl_softc *); 311 #endif 312 313 static void re_add_sysctls (struct rl_softc *); 314 static int re_sysctl_stats (SYSCTL_HANDLER_ARGS); 315 static int sysctl_int_range (SYSCTL_HANDLER_ARGS, int, int); 316 static int sysctl_hw_re_int_mod (SYSCTL_HANDLER_ARGS); 317 318 static device_method_t re_methods[] = { 319 /* Device interface */ 320 DEVMETHOD(device_probe, re_probe), 321 DEVMETHOD(device_attach, re_attach), 322 DEVMETHOD(device_detach, re_detach), 323 DEVMETHOD(device_suspend, re_suspend), 324 DEVMETHOD(device_resume, re_resume), 325 DEVMETHOD(device_shutdown, re_shutdown), 326 327 /* MII interface */ 328 DEVMETHOD(miibus_readreg, re_miibus_readreg), 329 DEVMETHOD(miibus_writereg, re_miibus_writereg), 330 DEVMETHOD(miibus_statchg, re_miibus_statchg), 331 332 DEVMETHOD_END 333 }; 334 335 static driver_t re_driver = { 336 "re", 337 re_methods, 338 sizeof(struct rl_softc) 339 }; 340 341 static devclass_t re_devclass; 342 343 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 344 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 345 346 #define EE_SET(x) \ 347 CSR_WRITE_1(sc, RL_EECMD, \ 348 CSR_READ_1(sc, RL_EECMD) | x) 349 350 #define EE_CLR(x) \ 351 CSR_WRITE_1(sc, RL_EECMD, \ 352 CSR_READ_1(sc, RL_EECMD) & ~x) 353 354 /* 355 * Send a read command and address to the EEPROM, check for ACK. 356 */ 357 static void 358 re_eeprom_putbyte(struct rl_softc *sc, int addr) 359 { 360 int d, i; 361 362 d = addr | (RL_9346_READ << sc->rl_eewidth); 363 364 /* 365 * Feed in each bit and strobe the clock. 366 */ 367 368 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 369 if (d & i) { 370 EE_SET(RL_EE_DATAIN); 371 } else { 372 EE_CLR(RL_EE_DATAIN); 373 } 374 DELAY(100); 375 EE_SET(RL_EE_CLK); 376 DELAY(150); 377 EE_CLR(RL_EE_CLK); 378 DELAY(100); 379 } 380 } 381 382 /* 383 * Read a word of data stored in the EEPROM at address 'addr.' 384 */ 385 static void 386 re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest) 387 { 388 int i; 389 u_int16_t word = 0; 390 391 /* 392 * Send address of word we want to read. 393 */ 394 re_eeprom_putbyte(sc, addr); 395 396 /* 397 * Start reading bits from EEPROM. 398 */ 399 for (i = 0x8000; i; i >>= 1) { 400 EE_SET(RL_EE_CLK); 401 DELAY(100); 402 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 403 word |= i; 404 EE_CLR(RL_EE_CLK); 405 DELAY(100); 406 } 407 408 *dest = word; 409 } 410 411 /* 412 * Read a sequence of words from the EEPROM. 413 */ 414 static void 415 re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt) 416 { 417 int i; 418 u_int16_t word = 0, *ptr; 419 420 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 421 422 DELAY(100); 423 424 for (i = 0; i < cnt; i++) { 425 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 426 re_eeprom_getword(sc, off + i, &word); 427 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 428 ptr = (u_int16_t *)(dest + (i * 2)); 429 *ptr = word; 430 } 431 432 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 433 } 434 435 static int 436 re_gmii_readreg(device_t dev, int phy, int reg) 437 { 438 struct rl_softc *sc; 439 u_int32_t rval; 440 int i; 441 442 sc = device_get_softc(dev); 443 444 /* Let the rgephy driver read the GMEDIASTAT register */ 445 446 if (reg == RL_GMEDIASTAT) { 447 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 448 return (rval); 449 } 450 451 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 452 453 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 454 rval = CSR_READ_4(sc, RL_PHYAR); 455 if (rval & RL_PHYAR_BUSY) 456 break; 457 DELAY(25); 458 } 459 460 if (i == RL_PHY_TIMEOUT) { 461 device_printf(sc->rl_dev, "PHY read failed\n"); 462 return (0); 463 } 464 465 /* 466 * Controller requires a 20us delay to process next MDIO request. 467 */ 468 DELAY(20); 469 470 return (rval & RL_PHYAR_PHYDATA); 471 } 472 473 static int 474 re_gmii_writereg(device_t dev, int phy, int reg, int data) 475 { 476 struct rl_softc *sc; 477 u_int32_t rval; 478 int i; 479 480 sc = device_get_softc(dev); 481 482 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 483 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 484 485 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 486 rval = CSR_READ_4(sc, RL_PHYAR); 487 if (!(rval & RL_PHYAR_BUSY)) 488 break; 489 DELAY(25); 490 } 491 492 if (i == RL_PHY_TIMEOUT) { 493 device_printf(sc->rl_dev, "PHY write failed\n"); 494 return (0); 495 } 496 497 /* 498 * Controller requires a 20us delay to process next MDIO request. 499 */ 500 DELAY(20); 501 502 return (0); 503 } 504 505 static int 506 re_miibus_readreg(device_t dev, int phy, int reg) 507 { 508 struct rl_softc *sc; 509 u_int16_t rval = 0; 510 u_int16_t re8139_reg = 0; 511 512 sc = device_get_softc(dev); 513 514 if (sc->rl_type == RL_8169) { 515 rval = re_gmii_readreg(dev, phy, reg); 516 return (rval); 517 } 518 519 switch (reg) { 520 case MII_BMCR: 521 re8139_reg = RL_BMCR; 522 break; 523 case MII_BMSR: 524 re8139_reg = RL_BMSR; 525 break; 526 case MII_ANAR: 527 re8139_reg = RL_ANAR; 528 break; 529 case MII_ANER: 530 re8139_reg = RL_ANER; 531 break; 532 case MII_ANLPAR: 533 re8139_reg = RL_LPAR; 534 break; 535 case MII_PHYIDR1: 536 case MII_PHYIDR2: 537 return (0); 538 /* 539 * Allow the rlphy driver to read the media status 540 * register. If we have a link partner which does not 541 * support NWAY, this is the register which will tell 542 * us the results of parallel detection. 543 */ 544 case RL_MEDIASTAT: 545 rval = CSR_READ_1(sc, RL_MEDIASTAT); 546 return (rval); 547 default: 548 device_printf(sc->rl_dev, "bad phy register\n"); 549 return (0); 550 } 551 rval = CSR_READ_2(sc, re8139_reg); 552 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 553 /* 8139C+ has different bit layout. */ 554 rval &= ~(BMCR_LOOP | BMCR_ISO); 555 } 556 return (rval); 557 } 558 559 static int 560 re_miibus_writereg(device_t dev, int phy, int reg, int data) 561 { 562 struct rl_softc *sc; 563 u_int16_t re8139_reg = 0; 564 int rval = 0; 565 566 sc = device_get_softc(dev); 567 568 if (sc->rl_type == RL_8169) { 569 rval = re_gmii_writereg(dev, phy, reg, data); 570 return (rval); 571 } 572 573 switch (reg) { 574 case MII_BMCR: 575 re8139_reg = RL_BMCR; 576 if (sc->rl_type == RL_8139CPLUS) { 577 /* 8139C+ has different bit layout. */ 578 data &= ~(BMCR_LOOP | BMCR_ISO); 579 } 580 break; 581 case MII_BMSR: 582 re8139_reg = RL_BMSR; 583 break; 584 case MII_ANAR: 585 re8139_reg = RL_ANAR; 586 break; 587 case MII_ANER: 588 re8139_reg = RL_ANER; 589 break; 590 case MII_ANLPAR: 591 re8139_reg = RL_LPAR; 592 break; 593 case MII_PHYIDR1: 594 case MII_PHYIDR2: 595 return (0); 596 break; 597 default: 598 device_printf(sc->rl_dev, "bad phy register\n"); 599 return (0); 600 } 601 CSR_WRITE_2(sc, re8139_reg, data); 602 return (0); 603 } 604 605 static void 606 re_miibus_statchg(device_t dev) 607 { 608 struct rl_softc *sc; 609 struct ifnet *ifp; 610 struct mii_data *mii; 611 612 sc = device_get_softc(dev); 613 mii = device_get_softc(sc->rl_miibus); 614 ifp = sc->rl_ifp; 615 if (mii == NULL || ifp == NULL || 616 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 617 return; 618 619 sc->rl_flags &= ~RL_FLAG_LINK; 620 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 621 (IFM_ACTIVE | IFM_AVALID)) { 622 switch (IFM_SUBTYPE(mii->mii_media_active)) { 623 case IFM_10_T: 624 case IFM_100_TX: 625 sc->rl_flags |= RL_FLAG_LINK; 626 break; 627 case IFM_1000_T: 628 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0) 629 break; 630 sc->rl_flags |= RL_FLAG_LINK; 631 break; 632 default: 633 break; 634 } 635 } 636 /* 637 * RealTek controllers does not provide any interface to 638 * Tx/Rx MACs for resolved speed, duplex and flow-control 639 * parameters. 640 */ 641 } 642 643 /* 644 * Set the RX configuration and 64-bit multicast hash filter. 645 */ 646 static void 647 re_set_rxmode(struct rl_softc *sc) 648 { 649 struct ifnet *ifp; 650 struct ifmultiaddr *ifma; 651 uint32_t hashes[2] = { 0, 0 }; 652 uint32_t h, rxfilt; 653 654 RL_LOCK_ASSERT(sc); 655 656 ifp = sc->rl_ifp; 657 658 rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD; 659 if ((sc->rl_flags & RL_FLAG_EARLYOFF) != 0) 660 rxfilt |= RL_RXCFG_EARLYOFF; 661 else if ((sc->rl_flags & RL_FLAG_EARLYOFFV2) != 0) 662 rxfilt |= RL_RXCFG_EARLYOFFV2; 663 664 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 665 if (ifp->if_flags & IFF_PROMISC) 666 rxfilt |= RL_RXCFG_RX_ALLPHYS; 667 /* 668 * Unlike other hardwares, we have to explicitly set 669 * RL_RXCFG_RX_MULTI to receive multicast frames in 670 * promiscuous mode. 671 */ 672 rxfilt |= RL_RXCFG_RX_MULTI; 673 hashes[0] = hashes[1] = 0xffffffff; 674 goto done; 675 } 676 677 if_maddr_rlock(ifp); 678 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 679 if (ifma->ifma_addr->sa_family != AF_LINK) 680 continue; 681 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 682 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 683 if (h < 32) 684 hashes[0] |= (1 << h); 685 else 686 hashes[1] |= (1 << (h - 32)); 687 } 688 if_maddr_runlock(ifp); 689 690 if (hashes[0] != 0 || hashes[1] != 0) { 691 /* 692 * For some unfathomable reason, RealTek decided to 693 * reverse the order of the multicast hash registers 694 * in the PCI Express parts. This means we have to 695 * write the hash pattern in reverse order for those 696 * devices. 697 */ 698 if ((sc->rl_flags & RL_FLAG_PCIE) != 0) { 699 h = bswap32(hashes[0]); 700 hashes[0] = bswap32(hashes[1]); 701 hashes[1] = h; 702 } 703 rxfilt |= RL_RXCFG_RX_MULTI; 704 } 705 706 done: 707 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 708 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 709 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 710 } 711 712 static void 713 re_reset(struct rl_softc *sc) 714 { 715 int i; 716 717 RL_LOCK_ASSERT(sc); 718 719 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 720 721 for (i = 0; i < RL_TIMEOUT; i++) { 722 DELAY(10); 723 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 724 break; 725 } 726 if (i == RL_TIMEOUT) 727 device_printf(sc->rl_dev, "reset never completed!\n"); 728 729 if ((sc->rl_flags & RL_FLAG_MACRESET) != 0) 730 CSR_WRITE_1(sc, 0x82, 1); 731 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169S) 732 re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0); 733 } 734 735 #ifdef RE_DIAG 736 737 /* 738 * The following routine is designed to test for a defect on some 739 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 740 * lines connected to the bus, however for a 32-bit only card, they 741 * should be pulled high. The result of this defect is that the 742 * NIC will not work right if you plug it into a 64-bit slot: DMA 743 * operations will be done with 64-bit transfers, which will fail 744 * because the 64-bit data lines aren't connected. 745 * 746 * There's no way to work around this (short of talking a soldering 747 * iron to the board), however we can detect it. The method we use 748 * here is to put the NIC into digital loopback mode, set the receiver 749 * to promiscuous mode, and then try to send a frame. We then compare 750 * the frame data we sent to what was received. If the data matches, 751 * then the NIC is working correctly, otherwise we know the user has 752 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 753 * slot. In the latter case, there's no way the NIC can work correctly, 754 * so we print out a message on the console and abort the device attach. 755 */ 756 757 static int 758 re_diag(struct rl_softc *sc) 759 { 760 struct ifnet *ifp = sc->rl_ifp; 761 struct mbuf *m0; 762 struct ether_header *eh; 763 struct rl_desc *cur_rx; 764 u_int16_t status; 765 u_int32_t rxstat; 766 int total_len, i, error = 0, phyaddr; 767 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 768 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 769 770 /* Allocate a single mbuf */ 771 MGETHDR(m0, M_NOWAIT, MT_DATA); 772 if (m0 == NULL) 773 return (ENOBUFS); 774 775 RL_LOCK(sc); 776 777 /* 778 * Initialize the NIC in test mode. This sets the chip up 779 * so that it can send and receive frames, but performs the 780 * following special functions: 781 * - Puts receiver in promiscuous mode 782 * - Enables digital loopback mode 783 * - Leaves interrupts turned off 784 */ 785 786 ifp->if_flags |= IFF_PROMISC; 787 sc->rl_testmode = 1; 788 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 789 re_init_locked(sc); 790 sc->rl_flags |= RL_FLAG_LINK; 791 if (sc->rl_type == RL_8169) 792 phyaddr = 1; 793 else 794 phyaddr = 0; 795 796 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 797 for (i = 0; i < RL_TIMEOUT; i++) { 798 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 799 if (!(status & BMCR_RESET)) 800 break; 801 } 802 803 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 804 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 805 806 DELAY(100000); 807 808 /* Put some data in the mbuf */ 809 810 eh = mtod(m0, struct ether_header *); 811 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 812 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 813 eh->ether_type = htons(ETHERTYPE_IP); 814 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 815 816 /* 817 * Queue the packet, start transmission. 818 * Note: IF_HANDOFF() ultimately calls re_start() for us. 819 */ 820 821 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 822 RL_UNLOCK(sc); 823 /* XXX: re_diag must not be called when in ALTQ mode */ 824 IF_HANDOFF(&ifp->if_snd, m0, ifp); 825 RL_LOCK(sc); 826 m0 = NULL; 827 828 /* Wait for it to propagate through the chip */ 829 830 DELAY(100000); 831 for (i = 0; i < RL_TIMEOUT; i++) { 832 status = CSR_READ_2(sc, RL_ISR); 833 CSR_WRITE_2(sc, RL_ISR, status); 834 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 835 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 836 break; 837 DELAY(10); 838 } 839 840 if (i == RL_TIMEOUT) { 841 device_printf(sc->rl_dev, 842 "diagnostic failed, failed to receive packet in" 843 " loopback mode\n"); 844 error = EIO; 845 goto done; 846 } 847 848 /* 849 * The packet should have been dumped into the first 850 * entry in the RX DMA ring. Grab it from there. 851 */ 852 853 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 854 sc->rl_ldata.rl_rx_list_map, 855 BUS_DMASYNC_POSTREAD); 856 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 857 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 858 BUS_DMASYNC_POSTREAD); 859 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 860 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 861 862 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 863 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 864 eh = mtod(m0, struct ether_header *); 865 866 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 867 total_len = RL_RXBYTES(cur_rx); 868 rxstat = le32toh(cur_rx->rl_cmdstat); 869 870 if (total_len != ETHER_MIN_LEN) { 871 device_printf(sc->rl_dev, 872 "diagnostic failed, received short packet\n"); 873 error = EIO; 874 goto done; 875 } 876 877 /* Test that the received packet data matches what we sent. */ 878 879 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 880 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 881 ntohs(eh->ether_type) != ETHERTYPE_IP) { 882 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 883 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 884 dst, ":", src, ":", ETHERTYPE_IP); 885 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 886 eh->ether_dhost, ":", eh->ether_shost, ":", 887 ntohs(eh->ether_type)); 888 device_printf(sc->rl_dev, "You may have a defective 32-bit " 889 "NIC plugged into a 64-bit PCI slot.\n"); 890 device_printf(sc->rl_dev, "Please re-install the NIC in a " 891 "32-bit slot for proper operation.\n"); 892 device_printf(sc->rl_dev, "Read the re(4) man page for more " 893 "details.\n"); 894 error = EIO; 895 } 896 897 done: 898 /* Turn interface off, release resources */ 899 900 sc->rl_testmode = 0; 901 sc->rl_flags &= ~RL_FLAG_LINK; 902 ifp->if_flags &= ~IFF_PROMISC; 903 re_stop(sc); 904 if (m0 != NULL) 905 m_freem(m0); 906 907 RL_UNLOCK(sc); 908 909 return (error); 910 } 911 912 #endif 913 914 /* 915 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 916 * IDs against our list and return a device name if we find a match. 917 */ 918 static int 919 re_probe(device_t dev) 920 { 921 const struct rl_type *t; 922 uint16_t devid, vendor; 923 uint16_t revid, sdevid; 924 int i; 925 926 vendor = pci_get_vendor(dev); 927 devid = pci_get_device(dev); 928 revid = pci_get_revid(dev); 929 sdevid = pci_get_subdevice(dev); 930 931 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 932 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 933 /* 934 * Only attach to rev. 3 of the Linksys EG1032 adapter. 935 * Rev. 2 is supported by sk(4). 936 */ 937 return (ENXIO); 938 } 939 } 940 941 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 942 if (revid != 0x20) { 943 /* 8139, let rl(4) take care of this device. */ 944 return (ENXIO); 945 } 946 } 947 948 t = re_devs; 949 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) { 950 if (vendor == t->rl_vid && devid == t->rl_did) { 951 device_set_desc(dev, t->rl_name); 952 return (BUS_PROBE_DEFAULT); 953 } 954 } 955 956 return (ENXIO); 957 } 958 959 /* 960 * Map a single buffer address. 961 */ 962 963 static void 964 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 965 { 966 bus_addr_t *addr; 967 968 if (error) 969 return; 970 971 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 972 addr = arg; 973 *addr = segs->ds_addr; 974 } 975 976 static int 977 re_allocmem(device_t dev, struct rl_softc *sc) 978 { 979 bus_addr_t lowaddr; 980 bus_size_t rx_list_size, tx_list_size; 981 int error; 982 int i; 983 984 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 985 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 986 987 /* 988 * Allocate the parent bus DMA tag appropriate for PCI. 989 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD 990 * register should be set. However some RealTek chips are known 991 * to be buggy on DAC handling, therefore disable DAC by limiting 992 * DMA address space to 32bit. PCIe variants of RealTek chips 993 * may not have the limitation. 994 */ 995 lowaddr = BUS_SPACE_MAXADDR; 996 if ((sc->rl_flags & RL_FLAG_PCIE) == 0) 997 lowaddr = BUS_SPACE_MAXADDR_32BIT; 998 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 999 lowaddr, BUS_SPACE_MAXADDR, NULL, NULL, 1000 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 1001 NULL, NULL, &sc->rl_parent_tag); 1002 if (error) { 1003 device_printf(dev, "could not allocate parent DMA tag\n"); 1004 return (error); 1005 } 1006 1007 /* 1008 * Allocate map for TX mbufs. 1009 */ 1010 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 1011 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1012 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 1013 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 1014 if (error) { 1015 device_printf(dev, "could not allocate TX DMA tag\n"); 1016 return (error); 1017 } 1018 1019 /* 1020 * Allocate map for RX mbufs. 1021 */ 1022 1023 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 1024 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 1025 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1026 MJUM9BYTES, 1, MJUM9BYTES, 0, NULL, NULL, 1027 &sc->rl_ldata.rl_jrx_mtag); 1028 if (error) { 1029 device_printf(dev, 1030 "could not allocate jumbo RX DMA tag\n"); 1031 return (error); 1032 } 1033 } 1034 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 1035 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1036 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 1037 if (error) { 1038 device_printf(dev, "could not allocate RX DMA tag\n"); 1039 return (error); 1040 } 1041 1042 /* 1043 * Allocate map for TX descriptor list. 1044 */ 1045 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1046 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1047 NULL, tx_list_size, 1, tx_list_size, 0, 1048 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1049 if (error) { 1050 device_printf(dev, "could not allocate TX DMA ring tag\n"); 1051 return (error); 1052 } 1053 1054 /* Allocate DMA'able memory for the TX ring */ 1055 1056 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1057 (void **)&sc->rl_ldata.rl_tx_list, 1058 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1059 &sc->rl_ldata.rl_tx_list_map); 1060 if (error) { 1061 device_printf(dev, "could not allocate TX DMA ring\n"); 1062 return (error); 1063 } 1064 1065 /* Load the map for the TX ring. */ 1066 1067 sc->rl_ldata.rl_tx_list_addr = 0; 1068 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1069 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1070 tx_list_size, re_dma_map_addr, 1071 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1072 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 1073 device_printf(dev, "could not load TX DMA ring\n"); 1074 return (ENOMEM); 1075 } 1076 1077 /* Create DMA maps for TX buffers */ 1078 1079 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1080 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1081 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1082 if (error) { 1083 device_printf(dev, "could not create DMA map for TX\n"); 1084 return (error); 1085 } 1086 } 1087 1088 /* 1089 * Allocate map for RX descriptor list. 1090 */ 1091 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1092 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1093 NULL, rx_list_size, 1, rx_list_size, 0, 1094 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1095 if (error) { 1096 device_printf(dev, "could not create RX DMA ring tag\n"); 1097 return (error); 1098 } 1099 1100 /* Allocate DMA'able memory for the RX ring */ 1101 1102 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1103 (void **)&sc->rl_ldata.rl_rx_list, 1104 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1105 &sc->rl_ldata.rl_rx_list_map); 1106 if (error) { 1107 device_printf(dev, "could not allocate RX DMA ring\n"); 1108 return (error); 1109 } 1110 1111 /* Load the map for the RX ring. */ 1112 1113 sc->rl_ldata.rl_rx_list_addr = 0; 1114 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1115 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1116 rx_list_size, re_dma_map_addr, 1117 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1118 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1119 device_printf(dev, "could not load RX DMA ring\n"); 1120 return (ENOMEM); 1121 } 1122 1123 /* Create DMA maps for RX buffers */ 1124 1125 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 1126 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0, 1127 &sc->rl_ldata.rl_jrx_sparemap); 1128 if (error) { 1129 device_printf(dev, 1130 "could not create spare DMA map for jumbo RX\n"); 1131 return (error); 1132 } 1133 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1134 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0, 1135 &sc->rl_ldata.rl_jrx_desc[i].rx_dmamap); 1136 if (error) { 1137 device_printf(dev, 1138 "could not create DMA map for jumbo RX\n"); 1139 return (error); 1140 } 1141 } 1142 } 1143 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1144 &sc->rl_ldata.rl_rx_sparemap); 1145 if (error) { 1146 device_printf(dev, "could not create spare DMA map for RX\n"); 1147 return (error); 1148 } 1149 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1150 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1151 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1152 if (error) { 1153 device_printf(dev, "could not create DMA map for RX\n"); 1154 return (error); 1155 } 1156 } 1157 1158 /* Create DMA map for statistics. */ 1159 error = bus_dma_tag_create(sc->rl_parent_tag, RL_DUMP_ALIGN, 0, 1160 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1161 sizeof(struct rl_stats), 1, sizeof(struct rl_stats), 0, NULL, NULL, 1162 &sc->rl_ldata.rl_stag); 1163 if (error) { 1164 device_printf(dev, "could not create statistics DMA tag\n"); 1165 return (error); 1166 } 1167 /* Allocate DMA'able memory for statistics. */ 1168 error = bus_dmamem_alloc(sc->rl_ldata.rl_stag, 1169 (void **)&sc->rl_ldata.rl_stats, 1170 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1171 &sc->rl_ldata.rl_smap); 1172 if (error) { 1173 device_printf(dev, 1174 "could not allocate statistics DMA memory\n"); 1175 return (error); 1176 } 1177 /* Load the map for statistics. */ 1178 sc->rl_ldata.rl_stats_addr = 0; 1179 error = bus_dmamap_load(sc->rl_ldata.rl_stag, sc->rl_ldata.rl_smap, 1180 sc->rl_ldata.rl_stats, sizeof(struct rl_stats), re_dma_map_addr, 1181 &sc->rl_ldata.rl_stats_addr, BUS_DMA_NOWAIT); 1182 if (error != 0 || sc->rl_ldata.rl_stats_addr == 0) { 1183 device_printf(dev, "could not load statistics DMA memory\n"); 1184 return (ENOMEM); 1185 } 1186 1187 return (0); 1188 } 1189 1190 /* 1191 * Attach the interface. Allocate softc structures, do ifmedia 1192 * setup and ethernet/BPF attach. 1193 */ 1194 static int 1195 re_attach(device_t dev) 1196 { 1197 u_char eaddr[ETHER_ADDR_LEN]; 1198 u_int16_t as[ETHER_ADDR_LEN / 2]; 1199 struct rl_softc *sc; 1200 struct ifnet *ifp; 1201 const struct rl_hwrev *hw_rev; 1202 u_int32_t cap, ctl; 1203 int hwrev; 1204 u_int16_t devid, re_did = 0; 1205 int error = 0, i, phy, rid; 1206 int msic, msixc, reg; 1207 uint8_t cfg; 1208 1209 sc = device_get_softc(dev); 1210 sc->rl_dev = dev; 1211 1212 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1213 MTX_DEF); 1214 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1215 1216 /* 1217 * Map control/status registers. 1218 */ 1219 pci_enable_busmaster(dev); 1220 1221 devid = pci_get_device(dev); 1222 /* 1223 * Prefer memory space register mapping over IO space. 1224 * Because RTL8169SC does not seem to work when memory mapping 1225 * is used always activate io mapping. 1226 */ 1227 if (devid == RT_DEVICEID_8169SC) 1228 prefer_iomap = 1; 1229 if (prefer_iomap == 0) { 1230 sc->rl_res_id = PCIR_BAR(1); 1231 sc->rl_res_type = SYS_RES_MEMORY; 1232 /* RTL8168/8101E seems to use different BARs. */ 1233 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E) 1234 sc->rl_res_id = PCIR_BAR(2); 1235 } else { 1236 sc->rl_res_id = PCIR_BAR(0); 1237 sc->rl_res_type = SYS_RES_IOPORT; 1238 } 1239 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1240 &sc->rl_res_id, RF_ACTIVE); 1241 if (sc->rl_res == NULL && prefer_iomap == 0) { 1242 sc->rl_res_id = PCIR_BAR(0); 1243 sc->rl_res_type = SYS_RES_IOPORT; 1244 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1245 &sc->rl_res_id, RF_ACTIVE); 1246 } 1247 if (sc->rl_res == NULL) { 1248 device_printf(dev, "couldn't map ports/memory\n"); 1249 error = ENXIO; 1250 goto fail; 1251 } 1252 1253 sc->rl_btag = rman_get_bustag(sc->rl_res); 1254 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1255 1256 msic = pci_msi_count(dev); 1257 msixc = pci_msix_count(dev); 1258 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 1259 sc->rl_flags |= RL_FLAG_PCIE; 1260 sc->rl_expcap = reg; 1261 } 1262 if (bootverbose) { 1263 device_printf(dev, "MSI count : %d\n", msic); 1264 device_printf(dev, "MSI-X count : %d\n", msixc); 1265 } 1266 if (msix_disable > 0) 1267 msixc = 0; 1268 if (msi_disable > 0) 1269 msic = 0; 1270 /* Prefer MSI-X to MSI. */ 1271 if (msixc > 0) { 1272 msixc = RL_MSI_MESSAGES; 1273 rid = PCIR_BAR(4); 1274 sc->rl_res_pba = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1275 &rid, RF_ACTIVE); 1276 if (sc->rl_res_pba == NULL) { 1277 device_printf(sc->rl_dev, 1278 "could not allocate MSI-X PBA resource\n"); 1279 } 1280 if (sc->rl_res_pba != NULL && 1281 pci_alloc_msix(dev, &msixc) == 0) { 1282 if (msixc == RL_MSI_MESSAGES) { 1283 device_printf(dev, "Using %d MSI-X message\n", 1284 msixc); 1285 sc->rl_flags |= RL_FLAG_MSIX; 1286 } else 1287 pci_release_msi(dev); 1288 } 1289 if ((sc->rl_flags & RL_FLAG_MSIX) == 0) { 1290 if (sc->rl_res_pba != NULL) 1291 bus_release_resource(dev, SYS_RES_MEMORY, rid, 1292 sc->rl_res_pba); 1293 sc->rl_res_pba = NULL; 1294 msixc = 0; 1295 } 1296 } 1297 /* Prefer MSI to INTx. */ 1298 if (msixc == 0 && msic > 0) { 1299 msic = RL_MSI_MESSAGES; 1300 if (pci_alloc_msi(dev, &msic) == 0) { 1301 if (msic == RL_MSI_MESSAGES) { 1302 device_printf(dev, "Using %d MSI message\n", 1303 msic); 1304 sc->rl_flags |= RL_FLAG_MSI; 1305 /* Explicitly set MSI enable bit. */ 1306 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1307 cfg = CSR_READ_1(sc, RL_CFG2); 1308 cfg |= RL_CFG2_MSI; 1309 CSR_WRITE_1(sc, RL_CFG2, cfg); 1310 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1311 } else 1312 pci_release_msi(dev); 1313 } 1314 if ((sc->rl_flags & RL_FLAG_MSI) == 0) 1315 msic = 0; 1316 } 1317 1318 /* Allocate interrupt */ 1319 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) { 1320 rid = 0; 1321 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1322 RF_SHAREABLE | RF_ACTIVE); 1323 if (sc->rl_irq[0] == NULL) { 1324 device_printf(dev, "couldn't allocate IRQ resources\n"); 1325 error = ENXIO; 1326 goto fail; 1327 } 1328 } else { 1329 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1330 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1331 SYS_RES_IRQ, &rid, RF_ACTIVE); 1332 if (sc->rl_irq[i] == NULL) { 1333 device_printf(dev, 1334 "couldn't allocate IRQ resources for " 1335 "message %d\n", rid); 1336 error = ENXIO; 1337 goto fail; 1338 } 1339 } 1340 } 1341 1342 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1343 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1344 cfg = CSR_READ_1(sc, RL_CFG2); 1345 if ((cfg & RL_CFG2_MSI) != 0) { 1346 device_printf(dev, "turning off MSI enable bit.\n"); 1347 cfg &= ~RL_CFG2_MSI; 1348 CSR_WRITE_1(sc, RL_CFG2, cfg); 1349 } 1350 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1351 } 1352 1353 /* Disable ASPM L0S/L1. */ 1354 if (sc->rl_expcap != 0) { 1355 cap = pci_read_config(dev, sc->rl_expcap + 1356 PCIER_LINK_CAP, 2); 1357 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { 1358 ctl = pci_read_config(dev, sc->rl_expcap + 1359 PCIER_LINK_CTL, 2); 1360 if ((ctl & PCIEM_LINK_CTL_ASPMC) != 0) { 1361 ctl &= ~PCIEM_LINK_CTL_ASPMC; 1362 pci_write_config(dev, sc->rl_expcap + 1363 PCIER_LINK_CTL, ctl, 2); 1364 device_printf(dev, "ASPM disabled\n"); 1365 } 1366 } else 1367 device_printf(dev, "no ASPM capability\n"); 1368 } 1369 1370 hw_rev = re_hwrevs; 1371 hwrev = CSR_READ_4(sc, RL_TXCFG); 1372 switch (hwrev & 0x70000000) { 1373 case 0x00000000: 1374 case 0x10000000: 1375 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000); 1376 hwrev &= (RL_TXCFG_HWREV | 0x80000000); 1377 break; 1378 default: 1379 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000); 1380 sc->rl_macrev = hwrev & 0x00700000; 1381 hwrev &= RL_TXCFG_HWREV; 1382 break; 1383 } 1384 device_printf(dev, "MAC rev. 0x%08x\n", sc->rl_macrev); 1385 while (hw_rev->rl_desc != NULL) { 1386 if (hw_rev->rl_rev == hwrev) { 1387 sc->rl_type = hw_rev->rl_type; 1388 sc->rl_hwrev = hw_rev; 1389 break; 1390 } 1391 hw_rev++; 1392 } 1393 if (hw_rev->rl_desc == NULL) { 1394 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev); 1395 error = ENXIO; 1396 goto fail; 1397 } 1398 1399 switch (hw_rev->rl_rev) { 1400 case RL_HWREV_8139CPLUS: 1401 sc->rl_flags |= RL_FLAG_FASTETHER | RL_FLAG_AUTOPAD; 1402 break; 1403 case RL_HWREV_8100E: 1404 case RL_HWREV_8101E: 1405 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_FASTETHER; 1406 break; 1407 case RL_HWREV_8102E: 1408 case RL_HWREV_8102EL: 1409 case RL_HWREV_8102EL_SPIN1: 1410 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1411 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | 1412 RL_FLAG_AUTOPAD; 1413 break; 1414 case RL_HWREV_8103E: 1415 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1416 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | 1417 RL_FLAG_AUTOPAD | RL_FLAG_MACSLEEP; 1418 break; 1419 case RL_HWREV_8401E: 1420 case RL_HWREV_8105E: 1421 case RL_HWREV_8105E_SPIN1: 1422 case RL_HWREV_8106E: 1423 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1424 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1425 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD; 1426 break; 1427 case RL_HWREV_8402: 1428 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1429 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1430 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | 1431 RL_FLAG_CMDSTOP_WAIT_TXQ; 1432 break; 1433 case RL_HWREV_8168B_SPIN1: 1434 case RL_HWREV_8168B_SPIN2: 1435 sc->rl_flags |= RL_FLAG_WOLRXENB; 1436 /* FALLTHROUGH */ 1437 case RL_HWREV_8168B_SPIN3: 1438 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT; 1439 break; 1440 case RL_HWREV_8168C_SPIN2: 1441 sc->rl_flags |= RL_FLAG_MACSLEEP; 1442 /* FALLTHROUGH */ 1443 case RL_HWREV_8168C: 1444 if (sc->rl_macrev == 0x00200000) 1445 sc->rl_flags |= RL_FLAG_MACSLEEP; 1446 /* FALLTHROUGH */ 1447 case RL_HWREV_8168CP: 1448 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1449 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1450 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK; 1451 break; 1452 case RL_HWREV_8168D: 1453 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1454 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1455 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1456 RL_FLAG_WOL_MANLINK; 1457 break; 1458 case RL_HWREV_8168DP: 1459 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1460 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_AUTOPAD | 1461 RL_FLAG_JUMBOV2 | RL_FLAG_WAIT_TXPOLL | RL_FLAG_WOL_MANLINK; 1462 break; 1463 case RL_HWREV_8168E: 1464 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1465 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1466 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1467 RL_FLAG_WOL_MANLINK; 1468 break; 1469 case RL_HWREV_8168E_VL: 1470 case RL_HWREV_8168F: 1471 sc->rl_flags |= RL_FLAG_EARLYOFF; 1472 /* FALLTHROUGH */ 1473 case RL_HWREV_8411: 1474 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1475 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1476 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1477 RL_FLAG_CMDSTOP_WAIT_TXQ | RL_FLAG_WOL_MANLINK; 1478 break; 1479 case RL_HWREV_8168EP: 1480 case RL_HWREV_8168G: 1481 case RL_HWREV_8411B: 1482 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1483 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1484 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1485 RL_FLAG_CMDSTOP_WAIT_TXQ | RL_FLAG_WOL_MANLINK | 1486 RL_FLAG_EARLYOFFV2 | RL_FLAG_RXDV_GATED; 1487 break; 1488 case RL_HWREV_8168GU: 1489 if (pci_get_device(dev) == RT_DEVICEID_8101E) { 1490 /* RTL8106EUS */ 1491 sc->rl_flags |= RL_FLAG_FASTETHER; 1492 } else 1493 sc->rl_flags |= RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK; 1494 1495 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1496 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1497 RL_FLAG_AUTOPAD | RL_FLAG_CMDSTOP_WAIT_TXQ | 1498 RL_FLAG_EARLYOFFV2 | RL_FLAG_RXDV_GATED; 1499 break; 1500 case RL_HWREV_8169_8110SB: 1501 case RL_HWREV_8169_8110SBL: 1502 case RL_HWREV_8169_8110SC: 1503 case RL_HWREV_8169_8110SCE: 1504 sc->rl_flags |= RL_FLAG_PHYWAKE; 1505 /* FALLTHROUGH */ 1506 case RL_HWREV_8169: 1507 case RL_HWREV_8169S: 1508 case RL_HWREV_8110S: 1509 sc->rl_flags |= RL_FLAG_MACRESET; 1510 break; 1511 default: 1512 break; 1513 } 1514 1515 if (sc->rl_hwrev->rl_rev == RL_HWREV_8139CPLUS) { 1516 sc->rl_cfg0 = RL_8139_CFG0; 1517 sc->rl_cfg1 = RL_8139_CFG1; 1518 sc->rl_cfg2 = 0; 1519 sc->rl_cfg3 = RL_8139_CFG3; 1520 sc->rl_cfg4 = RL_8139_CFG4; 1521 sc->rl_cfg5 = RL_8139_CFG5; 1522 } else { 1523 sc->rl_cfg0 = RL_CFG0; 1524 sc->rl_cfg1 = RL_CFG1; 1525 sc->rl_cfg2 = RL_CFG2; 1526 sc->rl_cfg3 = RL_CFG3; 1527 sc->rl_cfg4 = RL_CFG4; 1528 sc->rl_cfg5 = RL_CFG5; 1529 } 1530 1531 /* Reset the adapter. */ 1532 RL_LOCK(sc); 1533 re_reset(sc); 1534 RL_UNLOCK(sc); 1535 1536 /* Enable PME. */ 1537 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1538 cfg = CSR_READ_1(sc, sc->rl_cfg1); 1539 cfg |= RL_CFG1_PME; 1540 CSR_WRITE_1(sc, sc->rl_cfg1, cfg); 1541 cfg = CSR_READ_1(sc, sc->rl_cfg5); 1542 cfg &= RL_CFG5_PME_STS; 1543 CSR_WRITE_1(sc, sc->rl_cfg5, cfg); 1544 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1545 1546 if ((sc->rl_flags & RL_FLAG_PAR) != 0) { 1547 /* 1548 * XXX Should have a better way to extract station 1549 * address from EEPROM. 1550 */ 1551 for (i = 0; i < ETHER_ADDR_LEN; i++) 1552 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1553 } else { 1554 sc->rl_eewidth = RL_9356_ADDR_LEN; 1555 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1556 if (re_did != 0x8129) 1557 sc->rl_eewidth = RL_9346_ADDR_LEN; 1558 1559 /* 1560 * Get station address from the EEPROM. 1561 */ 1562 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1563 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1564 as[i] = le16toh(as[i]); 1565 bcopy(as, eaddr, ETHER_ADDR_LEN); 1566 } 1567 1568 if (sc->rl_type == RL_8169) { 1569 /* Set RX length mask and number of descriptors. */ 1570 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1571 sc->rl_txstart = RL_GTXSTART; 1572 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1573 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1574 } else { 1575 /* Set RX length mask and number of descriptors. */ 1576 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1577 sc->rl_txstart = RL_TXSTART; 1578 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1579 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1580 } 1581 1582 error = re_allocmem(dev, sc); 1583 if (error) 1584 goto fail; 1585 re_add_sysctls(sc); 1586 1587 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1588 if (ifp == NULL) { 1589 device_printf(dev, "can not if_alloc()\n"); 1590 error = ENOSPC; 1591 goto fail; 1592 } 1593 1594 /* Take controller out of deep sleep mode. */ 1595 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 1596 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 1597 CSR_WRITE_1(sc, RL_GPIO, 1598 CSR_READ_1(sc, RL_GPIO) | 0x01); 1599 else 1600 CSR_WRITE_1(sc, RL_GPIO, 1601 CSR_READ_1(sc, RL_GPIO) & ~0x01); 1602 } 1603 1604 /* Take PHY out of power down mode. */ 1605 if ((sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) { 1606 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80); 1607 if (hw_rev->rl_rev == RL_HWREV_8401E) 1608 CSR_WRITE_1(sc, 0xD1, CSR_READ_1(sc, 0xD1) & ~0x08); 1609 } 1610 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) { 1611 re_gmii_writereg(dev, 1, 0x1f, 0); 1612 re_gmii_writereg(dev, 1, 0x0e, 0); 1613 } 1614 1615 ifp->if_softc = sc; 1616 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1617 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1618 ifp->if_ioctl = re_ioctl; 1619 ifp->if_start = re_start; 1620 /* 1621 * RTL8168/8111C generates wrong IP checksummed frame if the 1622 * packet has IP options so disable TX checksum offloading. 1623 */ 1624 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168C || 1625 sc->rl_hwrev->rl_rev == RL_HWREV_8168C_SPIN2 || 1626 sc->rl_hwrev->rl_rev == RL_HWREV_8168CP) { 1627 ifp->if_hwassist = 0; 1628 ifp->if_capabilities = IFCAP_RXCSUM | IFCAP_TSO4; 1629 } else { 1630 ifp->if_hwassist = CSUM_IP | CSUM_TCP | CSUM_UDP; 1631 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 1632 } 1633 ifp->if_hwassist |= CSUM_TSO; 1634 ifp->if_capenable = ifp->if_capabilities; 1635 ifp->if_init = re_init; 1636 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1637 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1638 IFQ_SET_READY(&ifp->if_snd); 1639 1640 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1641 1642 #define RE_PHYAD_INTERNAL 0 1643 1644 /* Do MII setup. */ 1645 phy = RE_PHYAD_INTERNAL; 1646 if (sc->rl_type == RL_8169) 1647 phy = 1; 1648 error = mii_attach(dev, &sc->rl_miibus, ifp, re_ifmedia_upd, 1649 re_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, MIIF_DOPAUSE); 1650 if (error != 0) { 1651 device_printf(dev, "attaching PHYs failed\n"); 1652 goto fail; 1653 } 1654 1655 /* 1656 * Call MI attach routine. 1657 */ 1658 ether_ifattach(ifp, eaddr); 1659 1660 /* VLAN capability setup */ 1661 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1662 if (ifp->if_capabilities & IFCAP_HWCSUM) 1663 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1664 /* Enable WOL if PM is supported. */ 1665 if (pci_find_cap(sc->rl_dev, PCIY_PMG, ®) == 0) 1666 ifp->if_capabilities |= IFCAP_WOL; 1667 ifp->if_capenable = ifp->if_capabilities; 1668 ifp->if_capenable &= ~(IFCAP_WOL_UCAST | IFCAP_WOL_MCAST); 1669 /* 1670 * Don't enable TSO by default. It is known to generate 1671 * corrupted TCP segments(bad TCP options) under certain 1672 * circumstances. 1673 */ 1674 ifp->if_hwassist &= ~CSUM_TSO; 1675 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO); 1676 #ifdef DEVICE_POLLING 1677 ifp->if_capabilities |= IFCAP_POLLING; 1678 #endif 1679 /* 1680 * Tell the upper layer(s) we support long frames. 1681 * Must appear after the call to ether_ifattach() because 1682 * ether_ifattach() sets ifi_hdrlen to the default value. 1683 */ 1684 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 1685 1686 #ifdef DEV_NETMAP 1687 re_netmap_attach(sc); 1688 #endif /* DEV_NETMAP */ 1689 #ifdef RE_DIAG 1690 /* 1691 * Perform hardware diagnostic on the original RTL8169. 1692 * Some 32-bit cards were incorrectly wired and would 1693 * malfunction if plugged into a 64-bit slot. 1694 */ 1695 1696 if (hwrev == RL_HWREV_8169) { 1697 error = re_diag(sc); 1698 if (error) { 1699 device_printf(dev, 1700 "attach aborted due to hardware diag failure\n"); 1701 ether_ifdetach(ifp); 1702 goto fail; 1703 } 1704 } 1705 #endif 1706 1707 #ifdef RE_TX_MODERATION 1708 intr_filter = 1; 1709 #endif 1710 /* Hook interrupt last to avoid having to lock softc */ 1711 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 && 1712 intr_filter == 0) { 1713 error = bus_setup_intr(dev, sc->rl_irq[0], 1714 INTR_TYPE_NET | INTR_MPSAFE, NULL, re_intr_msi, sc, 1715 &sc->rl_intrhand[0]); 1716 } else { 1717 error = bus_setup_intr(dev, sc->rl_irq[0], 1718 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1719 &sc->rl_intrhand[0]); 1720 } 1721 if (error) { 1722 device_printf(dev, "couldn't set up irq\n"); 1723 ether_ifdetach(ifp); 1724 } 1725 1726 fail: 1727 1728 if (error) 1729 re_detach(dev); 1730 1731 return (error); 1732 } 1733 1734 /* 1735 * Shutdown hardware and free up resources. This can be called any 1736 * time after the mutex has been initialized. It is called in both 1737 * the error case in attach and the normal detach case so it needs 1738 * to be careful about only freeing resources that have actually been 1739 * allocated. 1740 */ 1741 static int 1742 re_detach(device_t dev) 1743 { 1744 struct rl_softc *sc; 1745 struct ifnet *ifp; 1746 int i, rid; 1747 1748 sc = device_get_softc(dev); 1749 ifp = sc->rl_ifp; 1750 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1751 1752 /* These should only be active if attach succeeded */ 1753 if (device_is_attached(dev)) { 1754 #ifdef DEVICE_POLLING 1755 if (ifp->if_capenable & IFCAP_POLLING) 1756 ether_poll_deregister(ifp); 1757 #endif 1758 RL_LOCK(sc); 1759 #if 0 1760 sc->suspended = 1; 1761 #endif 1762 re_stop(sc); 1763 RL_UNLOCK(sc); 1764 callout_drain(&sc->rl_stat_callout); 1765 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1766 /* 1767 * Force off the IFF_UP flag here, in case someone 1768 * still had a BPF descriptor attached to this 1769 * interface. If they do, ether_ifdetach() will cause 1770 * the BPF code to try and clear the promisc mode 1771 * flag, which will bubble down to re_ioctl(), 1772 * which will try to call re_init() again. This will 1773 * turn the NIC back on and restart the MII ticker, 1774 * which will panic the system when the kernel tries 1775 * to invoke the re_tick() function that isn't there 1776 * anymore. 1777 */ 1778 ifp->if_flags &= ~IFF_UP; 1779 ether_ifdetach(ifp); 1780 } 1781 if (sc->rl_miibus) 1782 device_delete_child(dev, sc->rl_miibus); 1783 bus_generic_detach(dev); 1784 1785 /* 1786 * The rest is resource deallocation, so we should already be 1787 * stopped here. 1788 */ 1789 1790 if (sc->rl_intrhand[0] != NULL) { 1791 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]); 1792 sc->rl_intrhand[0] = NULL; 1793 } 1794 if (ifp != NULL) { 1795 #ifdef DEV_NETMAP 1796 netmap_detach(ifp); 1797 #endif /* DEV_NETMAP */ 1798 if_free(ifp); 1799 } 1800 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) 1801 rid = 0; 1802 else 1803 rid = 1; 1804 if (sc->rl_irq[0] != NULL) { 1805 bus_release_resource(dev, SYS_RES_IRQ, rid, sc->rl_irq[0]); 1806 sc->rl_irq[0] = NULL; 1807 } 1808 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0) 1809 pci_release_msi(dev); 1810 if (sc->rl_res_pba) { 1811 rid = PCIR_BAR(4); 1812 bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->rl_res_pba); 1813 } 1814 if (sc->rl_res) 1815 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, 1816 sc->rl_res); 1817 1818 /* Unload and free the RX DMA ring memory and map */ 1819 1820 if (sc->rl_ldata.rl_rx_list_tag) { 1821 if (sc->rl_ldata.rl_rx_list_addr) 1822 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1823 sc->rl_ldata.rl_rx_list_map); 1824 if (sc->rl_ldata.rl_rx_list) 1825 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1826 sc->rl_ldata.rl_rx_list, 1827 sc->rl_ldata.rl_rx_list_map); 1828 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1829 } 1830 1831 /* Unload and free the TX DMA ring memory and map */ 1832 1833 if (sc->rl_ldata.rl_tx_list_tag) { 1834 if (sc->rl_ldata.rl_tx_list_addr) 1835 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1836 sc->rl_ldata.rl_tx_list_map); 1837 if (sc->rl_ldata.rl_tx_list) 1838 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1839 sc->rl_ldata.rl_tx_list, 1840 sc->rl_ldata.rl_tx_list_map); 1841 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1842 } 1843 1844 /* Destroy all the RX and TX buffer maps */ 1845 1846 if (sc->rl_ldata.rl_tx_mtag) { 1847 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1848 if (sc->rl_ldata.rl_tx_desc[i].tx_dmamap) 1849 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1850 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1851 } 1852 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1853 } 1854 if (sc->rl_ldata.rl_rx_mtag) { 1855 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1856 if (sc->rl_ldata.rl_rx_desc[i].rx_dmamap) 1857 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1858 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1859 } 1860 if (sc->rl_ldata.rl_rx_sparemap) 1861 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1862 sc->rl_ldata.rl_rx_sparemap); 1863 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1864 } 1865 if (sc->rl_ldata.rl_jrx_mtag) { 1866 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1867 if (sc->rl_ldata.rl_jrx_desc[i].rx_dmamap) 1868 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag, 1869 sc->rl_ldata.rl_jrx_desc[i].rx_dmamap); 1870 } 1871 if (sc->rl_ldata.rl_jrx_sparemap) 1872 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag, 1873 sc->rl_ldata.rl_jrx_sparemap); 1874 bus_dma_tag_destroy(sc->rl_ldata.rl_jrx_mtag); 1875 } 1876 /* Unload and free the stats buffer and map */ 1877 1878 if (sc->rl_ldata.rl_stag) { 1879 if (sc->rl_ldata.rl_stats_addr) 1880 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1881 sc->rl_ldata.rl_smap); 1882 if (sc->rl_ldata.rl_stats) 1883 bus_dmamem_free(sc->rl_ldata.rl_stag, 1884 sc->rl_ldata.rl_stats, sc->rl_ldata.rl_smap); 1885 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1886 } 1887 1888 if (sc->rl_parent_tag) 1889 bus_dma_tag_destroy(sc->rl_parent_tag); 1890 1891 mtx_destroy(&sc->rl_mtx); 1892 1893 return (0); 1894 } 1895 1896 static __inline void 1897 re_discard_rxbuf(struct rl_softc *sc, int idx) 1898 { 1899 struct rl_desc *desc; 1900 struct rl_rxdesc *rxd; 1901 uint32_t cmdstat; 1902 1903 if (sc->rl_ifp->if_mtu > RL_MTU && 1904 (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) 1905 rxd = &sc->rl_ldata.rl_jrx_desc[idx]; 1906 else 1907 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1908 desc = &sc->rl_ldata.rl_rx_list[idx]; 1909 desc->rl_vlanctl = 0; 1910 cmdstat = rxd->rx_size; 1911 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1912 cmdstat |= RL_RDESC_CMD_EOR; 1913 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1914 } 1915 1916 static int 1917 re_newbuf(struct rl_softc *sc, int idx) 1918 { 1919 struct mbuf *m; 1920 struct rl_rxdesc *rxd; 1921 bus_dma_segment_t segs[1]; 1922 bus_dmamap_t map; 1923 struct rl_desc *desc; 1924 uint32_t cmdstat; 1925 int error, nsegs; 1926 1927 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1928 if (m == NULL) 1929 return (ENOBUFS); 1930 1931 m->m_len = m->m_pkthdr.len = MCLBYTES; 1932 #ifdef RE_FIXUP_RX 1933 /* 1934 * This is part of an evil trick to deal with non-x86 platforms. 1935 * The RealTek chip requires RX buffers to be aligned on 64-bit 1936 * boundaries, but that will hose non-x86 machines. To get around 1937 * this, we leave some empty space at the start of each buffer 1938 * and for non-x86 hosts, we copy the buffer back six bytes 1939 * to achieve word alignment. This is slightly more efficient 1940 * than allocating a new buffer, copying the contents, and 1941 * discarding the old buffer. 1942 */ 1943 m_adj(m, RE_ETHER_ALIGN); 1944 #endif 1945 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1946 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1947 if (error != 0) { 1948 m_freem(m); 1949 return (ENOBUFS); 1950 } 1951 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1952 1953 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1954 if (rxd->rx_m != NULL) { 1955 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1956 BUS_DMASYNC_POSTREAD); 1957 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1958 } 1959 1960 rxd->rx_m = m; 1961 map = rxd->rx_dmamap; 1962 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1963 rxd->rx_size = segs[0].ds_len; 1964 sc->rl_ldata.rl_rx_sparemap = map; 1965 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1966 BUS_DMASYNC_PREREAD); 1967 1968 desc = &sc->rl_ldata.rl_rx_list[idx]; 1969 desc->rl_vlanctl = 0; 1970 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1971 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1972 cmdstat = segs[0].ds_len; 1973 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1974 cmdstat |= RL_RDESC_CMD_EOR; 1975 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1976 1977 return (0); 1978 } 1979 1980 static int 1981 re_jumbo_newbuf(struct rl_softc *sc, int idx) 1982 { 1983 struct mbuf *m; 1984 struct rl_rxdesc *rxd; 1985 bus_dma_segment_t segs[1]; 1986 bus_dmamap_t map; 1987 struct rl_desc *desc; 1988 uint32_t cmdstat; 1989 int error, nsegs; 1990 1991 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 1992 if (m == NULL) 1993 return (ENOBUFS); 1994 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1995 #ifdef RE_FIXUP_RX 1996 m_adj(m, RE_ETHER_ALIGN); 1997 #endif 1998 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_jrx_mtag, 1999 sc->rl_ldata.rl_jrx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 2000 if (error != 0) { 2001 m_freem(m); 2002 return (ENOBUFS); 2003 } 2004 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 2005 2006 rxd = &sc->rl_ldata.rl_jrx_desc[idx]; 2007 if (rxd->rx_m != NULL) { 2008 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap, 2009 BUS_DMASYNC_POSTREAD); 2010 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap); 2011 } 2012 2013 rxd->rx_m = m; 2014 map = rxd->rx_dmamap; 2015 rxd->rx_dmamap = sc->rl_ldata.rl_jrx_sparemap; 2016 rxd->rx_size = segs[0].ds_len; 2017 sc->rl_ldata.rl_jrx_sparemap = map; 2018 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap, 2019 BUS_DMASYNC_PREREAD); 2020 2021 desc = &sc->rl_ldata.rl_rx_list[idx]; 2022 desc->rl_vlanctl = 0; 2023 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 2024 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 2025 cmdstat = segs[0].ds_len; 2026 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 2027 cmdstat |= RL_RDESC_CMD_EOR; 2028 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 2029 2030 return (0); 2031 } 2032 2033 #ifdef RE_FIXUP_RX 2034 static __inline void 2035 re_fixup_rx(struct mbuf *m) 2036 { 2037 int i; 2038 uint16_t *src, *dst; 2039 2040 src = mtod(m, uint16_t *); 2041 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 2042 2043 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 2044 *dst++ = *src++; 2045 2046 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 2047 } 2048 #endif 2049 2050 static int 2051 re_tx_list_init(struct rl_softc *sc) 2052 { 2053 struct rl_desc *desc; 2054 int i; 2055 2056 RL_LOCK_ASSERT(sc); 2057 2058 bzero(sc->rl_ldata.rl_tx_list, 2059 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 2060 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 2061 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 2062 #ifdef DEV_NETMAP 2063 re_netmap_tx_init(sc); 2064 #endif /* DEV_NETMAP */ 2065 /* Set EOR. */ 2066 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 2067 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 2068 2069 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2070 sc->rl_ldata.rl_tx_list_map, 2071 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2072 2073 sc->rl_ldata.rl_tx_prodidx = 0; 2074 sc->rl_ldata.rl_tx_considx = 0; 2075 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 2076 2077 return (0); 2078 } 2079 2080 static int 2081 re_rx_list_init(struct rl_softc *sc) 2082 { 2083 int error, i; 2084 2085 bzero(sc->rl_ldata.rl_rx_list, 2086 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 2087 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2088 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 2089 if ((error = re_newbuf(sc, i)) != 0) 2090 return (error); 2091 } 2092 #ifdef DEV_NETMAP 2093 re_netmap_rx_init(sc); 2094 #endif /* DEV_NETMAP */ 2095 2096 /* Flush the RX descriptors */ 2097 2098 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2099 sc->rl_ldata.rl_rx_list_map, 2100 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2101 2102 sc->rl_ldata.rl_rx_prodidx = 0; 2103 sc->rl_head = sc->rl_tail = NULL; 2104 sc->rl_int_rx_act = 0; 2105 2106 return (0); 2107 } 2108 2109 static int 2110 re_jrx_list_init(struct rl_softc *sc) 2111 { 2112 int error, i; 2113 2114 bzero(sc->rl_ldata.rl_rx_list, 2115 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 2116 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2117 sc->rl_ldata.rl_jrx_desc[i].rx_m = NULL; 2118 if ((error = re_jumbo_newbuf(sc, i)) != 0) 2119 return (error); 2120 } 2121 2122 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2123 sc->rl_ldata.rl_rx_list_map, 2124 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2125 2126 sc->rl_ldata.rl_rx_prodidx = 0; 2127 sc->rl_head = sc->rl_tail = NULL; 2128 sc->rl_int_rx_act = 0; 2129 2130 return (0); 2131 } 2132 2133 /* 2134 * RX handler for C+ and 8169. For the gigE chips, we support 2135 * the reception of jumbo frames that have been fragmented 2136 * across multiple 2K mbuf cluster buffers. 2137 */ 2138 static int 2139 re_rxeof(struct rl_softc *sc, int *rx_npktsp) 2140 { 2141 struct mbuf *m; 2142 struct ifnet *ifp; 2143 int i, rxerr, total_len; 2144 struct rl_desc *cur_rx; 2145 u_int32_t rxstat, rxvlan; 2146 int jumbo, maxpkt = 16, rx_npkts = 0; 2147 2148 RL_LOCK_ASSERT(sc); 2149 2150 ifp = sc->rl_ifp; 2151 #ifdef DEV_NETMAP 2152 if (netmap_rx_irq(ifp, 0, &rx_npkts)) 2153 return 0; 2154 #endif /* DEV_NETMAP */ 2155 if (ifp->if_mtu > RL_MTU && (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) 2156 jumbo = 1; 2157 else 2158 jumbo = 0; 2159 2160 /* Invalidate the descriptor memory */ 2161 2162 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2163 sc->rl_ldata.rl_rx_list_map, 2164 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2165 2166 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 2167 i = RL_RX_DESC_NXT(sc, i)) { 2168 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2169 break; 2170 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 2171 rxstat = le32toh(cur_rx->rl_cmdstat); 2172 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 2173 break; 2174 total_len = rxstat & sc->rl_rxlenmask; 2175 rxvlan = le32toh(cur_rx->rl_vlanctl); 2176 if (jumbo != 0) 2177 m = sc->rl_ldata.rl_jrx_desc[i].rx_m; 2178 else 2179 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 2180 2181 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 2182 (rxstat & (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) != 2183 (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) { 2184 /* 2185 * RTL8168C or later controllers do not 2186 * support multi-fragment packet. 2187 */ 2188 re_discard_rxbuf(sc, i); 2189 continue; 2190 } else if ((rxstat & RL_RDESC_STAT_EOF) == 0) { 2191 if (re_newbuf(sc, i) != 0) { 2192 /* 2193 * If this is part of a multi-fragment packet, 2194 * discard all the pieces. 2195 */ 2196 if (sc->rl_head != NULL) { 2197 m_freem(sc->rl_head); 2198 sc->rl_head = sc->rl_tail = NULL; 2199 } 2200 re_discard_rxbuf(sc, i); 2201 continue; 2202 } 2203 m->m_len = RE_RX_DESC_BUFLEN; 2204 if (sc->rl_head == NULL) 2205 sc->rl_head = sc->rl_tail = m; 2206 else { 2207 m->m_flags &= ~M_PKTHDR; 2208 sc->rl_tail->m_next = m; 2209 sc->rl_tail = m; 2210 } 2211 continue; 2212 } 2213 2214 /* 2215 * NOTE: for the 8139C+, the frame length field 2216 * is always 12 bits in size, but for the gigE chips, 2217 * it is 13 bits (since the max RX frame length is 16K). 2218 * Unfortunately, all 32 bits in the status word 2219 * were already used, so to make room for the extra 2220 * length bit, RealTek took out the 'frame alignment 2221 * error' bit and shifted the other status bits 2222 * over one slot. The OWN, EOR, FS and LS bits are 2223 * still in the same places. We have already extracted 2224 * the frame length and checked the OWN bit, so rather 2225 * than using an alternate bit mapping, we shift the 2226 * status bits one space to the right so we can evaluate 2227 * them using the 8169 status as though it was in the 2228 * same format as that of the 8139C+. 2229 */ 2230 if (sc->rl_type == RL_8169) 2231 rxstat >>= 1; 2232 2233 /* 2234 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 2235 * set, but if CRC is clear, it will still be a valid frame. 2236 */ 2237 if ((rxstat & RL_RDESC_STAT_RXERRSUM) != 0) { 2238 rxerr = 1; 2239 if ((sc->rl_flags & RL_FLAG_JUMBOV2) == 0 && 2240 total_len > 8191 && 2241 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT) 2242 rxerr = 0; 2243 if (rxerr != 0) { 2244 ifp->if_ierrors++; 2245 /* 2246 * If this is part of a multi-fragment packet, 2247 * discard all the pieces. 2248 */ 2249 if (sc->rl_head != NULL) { 2250 m_freem(sc->rl_head); 2251 sc->rl_head = sc->rl_tail = NULL; 2252 } 2253 re_discard_rxbuf(sc, i); 2254 continue; 2255 } 2256 } 2257 2258 /* 2259 * If allocating a replacement mbuf fails, 2260 * reload the current one. 2261 */ 2262 if (jumbo != 0) 2263 rxerr = re_jumbo_newbuf(sc, i); 2264 else 2265 rxerr = re_newbuf(sc, i); 2266 if (rxerr != 0) { 2267 ifp->if_iqdrops++; 2268 if (sc->rl_head != NULL) { 2269 m_freem(sc->rl_head); 2270 sc->rl_head = sc->rl_tail = NULL; 2271 } 2272 re_discard_rxbuf(sc, i); 2273 continue; 2274 } 2275 2276 if (sc->rl_head != NULL) { 2277 if (jumbo != 0) 2278 m->m_len = total_len; 2279 else { 2280 m->m_len = total_len % RE_RX_DESC_BUFLEN; 2281 if (m->m_len == 0) 2282 m->m_len = RE_RX_DESC_BUFLEN; 2283 } 2284 /* 2285 * Special case: if there's 4 bytes or less 2286 * in this buffer, the mbuf can be discarded: 2287 * the last 4 bytes is the CRC, which we don't 2288 * care about anyway. 2289 */ 2290 if (m->m_len <= ETHER_CRC_LEN) { 2291 sc->rl_tail->m_len -= 2292 (ETHER_CRC_LEN - m->m_len); 2293 m_freem(m); 2294 } else { 2295 m->m_len -= ETHER_CRC_LEN; 2296 m->m_flags &= ~M_PKTHDR; 2297 sc->rl_tail->m_next = m; 2298 } 2299 m = sc->rl_head; 2300 sc->rl_head = sc->rl_tail = NULL; 2301 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 2302 } else 2303 m->m_pkthdr.len = m->m_len = 2304 (total_len - ETHER_CRC_LEN); 2305 2306 #ifdef RE_FIXUP_RX 2307 re_fixup_rx(m); 2308 #endif 2309 ifp->if_ipackets++; 2310 m->m_pkthdr.rcvif = ifp; 2311 2312 /* Do RX checksumming if enabled */ 2313 2314 if (ifp->if_capenable & IFCAP_RXCSUM) { 2315 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2316 /* Check IP header checksum */ 2317 if (rxstat & RL_RDESC_STAT_PROTOID) 2318 m->m_pkthdr.csum_flags |= 2319 CSUM_IP_CHECKED; 2320 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 2321 m->m_pkthdr.csum_flags |= 2322 CSUM_IP_VALID; 2323 2324 /* Check TCP/UDP checksum */ 2325 if ((RL_TCPPKT(rxstat) && 2326 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 2327 (RL_UDPPKT(rxstat) && 2328 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 2329 m->m_pkthdr.csum_flags |= 2330 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2331 m->m_pkthdr.csum_data = 0xffff; 2332 } 2333 } else { 2334 /* 2335 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP 2336 */ 2337 if ((rxstat & RL_RDESC_STAT_PROTOID) && 2338 (rxvlan & RL_RDESC_IPV4)) 2339 m->m_pkthdr.csum_flags |= 2340 CSUM_IP_CHECKED; 2341 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) && 2342 (rxvlan & RL_RDESC_IPV4)) 2343 m->m_pkthdr.csum_flags |= 2344 CSUM_IP_VALID; 2345 if (((rxstat & RL_RDESC_STAT_TCP) && 2346 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 2347 ((rxstat & RL_RDESC_STAT_UDP) && 2348 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 2349 m->m_pkthdr.csum_flags |= 2350 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2351 m->m_pkthdr.csum_data = 0xffff; 2352 } 2353 } 2354 } 2355 maxpkt--; 2356 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 2357 m->m_pkthdr.ether_vtag = 2358 bswap16((rxvlan & RL_RDESC_VLANCTL_DATA)); 2359 m->m_flags |= M_VLANTAG; 2360 } 2361 RL_UNLOCK(sc); 2362 (*ifp->if_input)(ifp, m); 2363 RL_LOCK(sc); 2364 rx_npkts++; 2365 } 2366 2367 /* Flush the RX DMA ring */ 2368 2369 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2370 sc->rl_ldata.rl_rx_list_map, 2371 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2372 2373 sc->rl_ldata.rl_rx_prodidx = i; 2374 2375 if (rx_npktsp != NULL) 2376 *rx_npktsp = rx_npkts; 2377 if (maxpkt) 2378 return (EAGAIN); 2379 2380 return (0); 2381 } 2382 2383 static void 2384 re_txeof(struct rl_softc *sc) 2385 { 2386 struct ifnet *ifp; 2387 struct rl_txdesc *txd; 2388 u_int32_t txstat; 2389 int cons; 2390 2391 cons = sc->rl_ldata.rl_tx_considx; 2392 if (cons == sc->rl_ldata.rl_tx_prodidx) 2393 return; 2394 2395 ifp = sc->rl_ifp; 2396 #ifdef DEV_NETMAP 2397 if (netmap_tx_irq(ifp, 0)) 2398 return; 2399 #endif /* DEV_NETMAP */ 2400 /* Invalidate the TX descriptor list */ 2401 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2402 sc->rl_ldata.rl_tx_list_map, 2403 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2404 2405 for (; cons != sc->rl_ldata.rl_tx_prodidx; 2406 cons = RL_TX_DESC_NXT(sc, cons)) { 2407 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 2408 if (txstat & RL_TDESC_STAT_OWN) 2409 break; 2410 /* 2411 * We only stash mbufs in the last descriptor 2412 * in a fragment chain, which also happens to 2413 * be the only place where the TX status bits 2414 * are valid. 2415 */ 2416 if (txstat & RL_TDESC_CMD_EOF) { 2417 txd = &sc->rl_ldata.rl_tx_desc[cons]; 2418 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2419 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2420 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2421 txd->tx_dmamap); 2422 KASSERT(txd->tx_m != NULL, 2423 ("%s: freeing NULL mbufs!", __func__)); 2424 m_freem(txd->tx_m); 2425 txd->tx_m = NULL; 2426 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 2427 RL_TDESC_STAT_COLCNT)) 2428 ifp->if_collisions++; 2429 if (txstat & RL_TDESC_STAT_TXERRSUM) 2430 ifp->if_oerrors++; 2431 else 2432 ifp->if_opackets++; 2433 } 2434 sc->rl_ldata.rl_tx_free++; 2435 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2436 } 2437 sc->rl_ldata.rl_tx_considx = cons; 2438 2439 /* No changes made to the TX ring, so no flush needed */ 2440 2441 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 2442 #ifdef RE_TX_MODERATION 2443 /* 2444 * If not all descriptors have been reaped yet, reload 2445 * the timer so that we will eventually get another 2446 * interrupt that will cause us to re-enter this routine. 2447 * This is done in case the transmitter has gone idle. 2448 */ 2449 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2450 #endif 2451 } else 2452 sc->rl_watchdog_timer = 0; 2453 } 2454 2455 static void 2456 re_tick(void *xsc) 2457 { 2458 struct rl_softc *sc; 2459 struct mii_data *mii; 2460 2461 sc = xsc; 2462 2463 RL_LOCK_ASSERT(sc); 2464 2465 mii = device_get_softc(sc->rl_miibus); 2466 mii_tick(mii); 2467 if ((sc->rl_flags & RL_FLAG_LINK) == 0) 2468 re_miibus_statchg(sc->rl_dev); 2469 /* 2470 * Reclaim transmitted frames here. Technically it is not 2471 * necessary to do here but it ensures periodic reclamation 2472 * regardless of Tx completion interrupt which seems to be 2473 * lost on PCIe based controllers under certain situations. 2474 */ 2475 re_txeof(sc); 2476 re_watchdog(sc); 2477 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2478 } 2479 2480 #ifdef DEVICE_POLLING 2481 static int 2482 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2483 { 2484 struct rl_softc *sc = ifp->if_softc; 2485 int rx_npkts = 0; 2486 2487 RL_LOCK(sc); 2488 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2489 rx_npkts = re_poll_locked(ifp, cmd, count); 2490 RL_UNLOCK(sc); 2491 return (rx_npkts); 2492 } 2493 2494 static int 2495 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2496 { 2497 struct rl_softc *sc = ifp->if_softc; 2498 int rx_npkts; 2499 2500 RL_LOCK_ASSERT(sc); 2501 2502 sc->rxcycles = count; 2503 re_rxeof(sc, &rx_npkts); 2504 re_txeof(sc); 2505 2506 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2507 re_start_locked(ifp); 2508 2509 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2510 u_int16_t status; 2511 2512 status = CSR_READ_2(sc, RL_ISR); 2513 if (status == 0xffff) 2514 return (rx_npkts); 2515 if (status) 2516 CSR_WRITE_2(sc, RL_ISR, status); 2517 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2518 (sc->rl_flags & RL_FLAG_PCIE)) 2519 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2520 2521 /* 2522 * XXX check behaviour on receiver stalls. 2523 */ 2524 2525 if (status & RL_ISR_SYSTEM_ERR) { 2526 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2527 re_init_locked(sc); 2528 } 2529 } 2530 return (rx_npkts); 2531 } 2532 #endif /* DEVICE_POLLING */ 2533 2534 static int 2535 re_intr(void *arg) 2536 { 2537 struct rl_softc *sc; 2538 uint16_t status; 2539 2540 sc = arg; 2541 2542 status = CSR_READ_2(sc, RL_ISR); 2543 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2544 return (FILTER_STRAY); 2545 CSR_WRITE_2(sc, RL_IMR, 0); 2546 2547 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2548 2549 return (FILTER_HANDLED); 2550 } 2551 2552 static void 2553 re_int_task(void *arg, int npending) 2554 { 2555 struct rl_softc *sc; 2556 struct ifnet *ifp; 2557 u_int16_t status; 2558 int rval = 0; 2559 2560 sc = arg; 2561 ifp = sc->rl_ifp; 2562 2563 RL_LOCK(sc); 2564 2565 status = CSR_READ_2(sc, RL_ISR); 2566 CSR_WRITE_2(sc, RL_ISR, status); 2567 2568 if (sc->suspended || 2569 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2570 RL_UNLOCK(sc); 2571 return; 2572 } 2573 2574 #ifdef DEVICE_POLLING 2575 if (ifp->if_capenable & IFCAP_POLLING) { 2576 RL_UNLOCK(sc); 2577 return; 2578 } 2579 #endif 2580 2581 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2582 rval = re_rxeof(sc, NULL); 2583 2584 /* 2585 * Some chips will ignore a second TX request issued 2586 * while an existing transmission is in progress. If 2587 * the transmitter goes idle but there are still 2588 * packets waiting to be sent, we need to restart the 2589 * channel here to flush them out. This only seems to 2590 * be required with the PCIe devices. 2591 */ 2592 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2593 (sc->rl_flags & RL_FLAG_PCIE)) 2594 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2595 if (status & ( 2596 #ifdef RE_TX_MODERATION 2597 RL_ISR_TIMEOUT_EXPIRED| 2598 #else 2599 RL_ISR_TX_OK| 2600 #endif 2601 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2602 re_txeof(sc); 2603 2604 if (status & RL_ISR_SYSTEM_ERR) { 2605 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2606 re_init_locked(sc); 2607 } 2608 2609 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2610 re_start_locked(ifp); 2611 2612 RL_UNLOCK(sc); 2613 2614 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2615 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2616 return; 2617 } 2618 2619 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2620 } 2621 2622 static void 2623 re_intr_msi(void *xsc) 2624 { 2625 struct rl_softc *sc; 2626 struct ifnet *ifp; 2627 uint16_t intrs, status; 2628 2629 sc = xsc; 2630 RL_LOCK(sc); 2631 2632 ifp = sc->rl_ifp; 2633 #ifdef DEVICE_POLLING 2634 if (ifp->if_capenable & IFCAP_POLLING) { 2635 RL_UNLOCK(sc); 2636 return; 2637 } 2638 #endif 2639 /* Disable interrupts. */ 2640 CSR_WRITE_2(sc, RL_IMR, 0); 2641 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2642 RL_UNLOCK(sc); 2643 return; 2644 } 2645 2646 intrs = RL_INTRS_CPLUS; 2647 status = CSR_READ_2(sc, RL_ISR); 2648 CSR_WRITE_2(sc, RL_ISR, status); 2649 if (sc->rl_int_rx_act > 0) { 2650 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW | 2651 RL_ISR_RX_OVERRUN); 2652 status &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW | 2653 RL_ISR_RX_OVERRUN); 2654 } 2655 2656 if (status & (RL_ISR_TIMEOUT_EXPIRED | RL_ISR_RX_OK | RL_ISR_RX_ERR | 2657 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) { 2658 re_rxeof(sc, NULL); 2659 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2660 if (sc->rl_int_rx_mod != 0 && 2661 (status & (RL_ISR_RX_OK | RL_ISR_RX_ERR | 2662 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) != 0) { 2663 /* Rearm one-shot timer. */ 2664 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2665 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | 2666 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN); 2667 sc->rl_int_rx_act = 1; 2668 } else { 2669 intrs |= RL_ISR_RX_OK | RL_ISR_RX_ERR | 2670 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN; 2671 sc->rl_int_rx_act = 0; 2672 } 2673 } 2674 } 2675 2676 /* 2677 * Some chips will ignore a second TX request issued 2678 * while an existing transmission is in progress. If 2679 * the transmitter goes idle but there are still 2680 * packets waiting to be sent, we need to restart the 2681 * channel here to flush them out. This only seems to 2682 * be required with the PCIe devices. 2683 */ 2684 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2685 (sc->rl_flags & RL_FLAG_PCIE)) 2686 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2687 if (status & (RL_ISR_TX_OK | RL_ISR_TX_ERR | RL_ISR_TX_DESC_UNAVAIL)) 2688 re_txeof(sc); 2689 2690 if (status & RL_ISR_SYSTEM_ERR) { 2691 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2692 re_init_locked(sc); 2693 } 2694 2695 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2696 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2697 re_start_locked(ifp); 2698 CSR_WRITE_2(sc, RL_IMR, intrs); 2699 } 2700 RL_UNLOCK(sc); 2701 } 2702 2703 static int 2704 re_encap(struct rl_softc *sc, struct mbuf **m_head) 2705 { 2706 struct rl_txdesc *txd, *txd_last; 2707 bus_dma_segment_t segs[RL_NTXSEGS]; 2708 bus_dmamap_t map; 2709 struct mbuf *m_new; 2710 struct rl_desc *desc; 2711 int nsegs, prod; 2712 int i, error, ei, si; 2713 int padlen; 2714 uint32_t cmdstat, csum_flags, vlanctl; 2715 2716 RL_LOCK_ASSERT(sc); 2717 M_ASSERTPKTHDR((*m_head)); 2718 2719 /* 2720 * With some of the RealTek chips, using the checksum offload 2721 * support in conjunction with the autopadding feature results 2722 * in the transmission of corrupt frames. For example, if we 2723 * need to send a really small IP fragment that's less than 60 2724 * bytes in size, and IP header checksumming is enabled, the 2725 * resulting ethernet frame that appears on the wire will 2726 * have garbled payload. To work around this, if TX IP checksum 2727 * offload is enabled, we always manually pad short frames out 2728 * to the minimum ethernet frame size. 2729 */ 2730 if ((sc->rl_flags & RL_FLAG_AUTOPAD) == 0 && 2731 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN && 2732 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) { 2733 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2734 if (M_WRITABLE(*m_head) == 0) { 2735 /* Get a writable copy. */ 2736 m_new = m_dup(*m_head, M_NOWAIT); 2737 m_freem(*m_head); 2738 if (m_new == NULL) { 2739 *m_head = NULL; 2740 return (ENOBUFS); 2741 } 2742 *m_head = m_new; 2743 } 2744 if ((*m_head)->m_next != NULL || 2745 M_TRAILINGSPACE(*m_head) < padlen) { 2746 m_new = m_defrag(*m_head, M_NOWAIT); 2747 if (m_new == NULL) { 2748 m_freem(*m_head); 2749 *m_head = NULL; 2750 return (ENOBUFS); 2751 } 2752 } else 2753 m_new = *m_head; 2754 2755 /* 2756 * Manually pad short frames, and zero the pad space 2757 * to avoid leaking data. 2758 */ 2759 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2760 m_new->m_pkthdr.len += padlen; 2761 m_new->m_len = m_new->m_pkthdr.len; 2762 *m_head = m_new; 2763 } 2764 2765 prod = sc->rl_ldata.rl_tx_prodidx; 2766 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2767 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2768 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2769 if (error == EFBIG) { 2770 m_new = m_collapse(*m_head, M_NOWAIT, RL_NTXSEGS); 2771 if (m_new == NULL) { 2772 m_freem(*m_head); 2773 *m_head = NULL; 2774 return (ENOBUFS); 2775 } 2776 *m_head = m_new; 2777 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2778 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2779 if (error != 0) { 2780 m_freem(*m_head); 2781 *m_head = NULL; 2782 return (error); 2783 } 2784 } else if (error != 0) 2785 return (error); 2786 if (nsegs == 0) { 2787 m_freem(*m_head); 2788 *m_head = NULL; 2789 return (EIO); 2790 } 2791 2792 /* Check for number of available descriptors. */ 2793 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2794 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2795 return (ENOBUFS); 2796 } 2797 2798 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2799 BUS_DMASYNC_PREWRITE); 2800 2801 /* 2802 * Set up checksum offload. Note: checksum offload bits must 2803 * appear in all descriptors of a multi-descriptor transmit 2804 * attempt. This is according to testing done with an 8169 2805 * chip. This is a requirement. 2806 */ 2807 vlanctl = 0; 2808 csum_flags = 0; 2809 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2810 if ((sc->rl_flags & RL_FLAG_DESCV2) != 0) { 2811 csum_flags |= RL_TDESC_CMD_LGSEND; 2812 vlanctl |= ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2813 RL_TDESC_CMD_MSSVALV2_SHIFT); 2814 } else { 2815 csum_flags |= RL_TDESC_CMD_LGSEND | 2816 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2817 RL_TDESC_CMD_MSSVAL_SHIFT); 2818 } 2819 } else { 2820 /* 2821 * Unconditionally enable IP checksum if TCP or UDP 2822 * checksum is required. Otherwise, TCP/UDP checksum 2823 * doesn't make effects. 2824 */ 2825 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) { 2826 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2827 csum_flags |= RL_TDESC_CMD_IPCSUM; 2828 if (((*m_head)->m_pkthdr.csum_flags & 2829 CSUM_TCP) != 0) 2830 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2831 if (((*m_head)->m_pkthdr.csum_flags & 2832 CSUM_UDP) != 0) 2833 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2834 } else { 2835 vlanctl |= RL_TDESC_CMD_IPCSUMV2; 2836 if (((*m_head)->m_pkthdr.csum_flags & 2837 CSUM_TCP) != 0) 2838 vlanctl |= RL_TDESC_CMD_TCPCSUMV2; 2839 if (((*m_head)->m_pkthdr.csum_flags & 2840 CSUM_UDP) != 0) 2841 vlanctl |= RL_TDESC_CMD_UDPCSUMV2; 2842 } 2843 } 2844 } 2845 2846 /* 2847 * Set up hardware VLAN tagging. Note: vlan tag info must 2848 * appear in all descriptors of a multi-descriptor 2849 * transmission attempt. 2850 */ 2851 if ((*m_head)->m_flags & M_VLANTAG) 2852 vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) | 2853 RL_TDESC_VLANCTL_TAG; 2854 2855 si = prod; 2856 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2857 desc = &sc->rl_ldata.rl_tx_list[prod]; 2858 desc->rl_vlanctl = htole32(vlanctl); 2859 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2860 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2861 cmdstat = segs[i].ds_len; 2862 if (i != 0) 2863 cmdstat |= RL_TDESC_CMD_OWN; 2864 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2865 cmdstat |= RL_TDESC_CMD_EOR; 2866 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2867 sc->rl_ldata.rl_tx_free--; 2868 } 2869 /* Update producer index. */ 2870 sc->rl_ldata.rl_tx_prodidx = prod; 2871 2872 /* Set EOF on the last descriptor. */ 2873 ei = RL_TX_DESC_PRV(sc, prod); 2874 desc = &sc->rl_ldata.rl_tx_list[ei]; 2875 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2876 2877 desc = &sc->rl_ldata.rl_tx_list[si]; 2878 /* Set SOF and transfer ownership of packet to the chip. */ 2879 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2880 2881 /* 2882 * Insure that the map for this transmission 2883 * is placed at the array index of the last descriptor 2884 * in this chain. (Swap last and first dmamaps.) 2885 */ 2886 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2887 map = txd->tx_dmamap; 2888 txd->tx_dmamap = txd_last->tx_dmamap; 2889 txd_last->tx_dmamap = map; 2890 txd_last->tx_m = *m_head; 2891 2892 return (0); 2893 } 2894 2895 static void 2896 re_start(struct ifnet *ifp) 2897 { 2898 struct rl_softc *sc; 2899 2900 sc = ifp->if_softc; 2901 RL_LOCK(sc); 2902 re_start_locked(ifp); 2903 RL_UNLOCK(sc); 2904 } 2905 2906 /* 2907 * Main transmit routine for C+ and gigE NICs. 2908 */ 2909 static void 2910 re_start_locked(struct ifnet *ifp) 2911 { 2912 struct rl_softc *sc; 2913 struct mbuf *m_head; 2914 int queued; 2915 2916 sc = ifp->if_softc; 2917 2918 #ifdef DEV_NETMAP 2919 /* XXX is this necessary ? */ 2920 if (ifp->if_capenable & IFCAP_NETMAP) { 2921 struct netmap_kring *kring = &NA(ifp)->tx_rings[0]; 2922 if (sc->rl_ldata.rl_tx_prodidx != kring->nr_hwcur) { 2923 /* kick the tx unit */ 2924 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2925 #ifdef RE_TX_MODERATION 2926 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2927 #endif 2928 sc->rl_watchdog_timer = 5; 2929 } 2930 return; 2931 } 2932 #endif /* DEV_NETMAP */ 2933 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2934 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) 2935 return; 2936 2937 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2938 sc->rl_ldata.rl_tx_free > 1;) { 2939 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2940 if (m_head == NULL) 2941 break; 2942 2943 if (re_encap(sc, &m_head) != 0) { 2944 if (m_head == NULL) 2945 break; 2946 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2947 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2948 break; 2949 } 2950 2951 /* 2952 * If there's a BPF listener, bounce a copy of this frame 2953 * to him. 2954 */ 2955 ETHER_BPF_MTAP(ifp, m_head); 2956 2957 queued++; 2958 } 2959 2960 if (queued == 0) { 2961 #ifdef RE_TX_MODERATION 2962 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2963 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2964 #endif 2965 return; 2966 } 2967 2968 /* Flush the TX descriptors */ 2969 2970 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2971 sc->rl_ldata.rl_tx_list_map, 2972 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2973 2974 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2975 2976 #ifdef RE_TX_MODERATION 2977 /* 2978 * Use the countdown timer for interrupt moderation. 2979 * 'TX done' interrupts are disabled. Instead, we reset the 2980 * countdown timer, which will begin counting until it hits 2981 * the value in the TIMERINT register, and then trigger an 2982 * interrupt. Each time we write to the TIMERCNT register, 2983 * the timer count is reset to 0. 2984 */ 2985 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2986 #endif 2987 2988 /* 2989 * Set a timeout in case the chip goes out to lunch. 2990 */ 2991 sc->rl_watchdog_timer = 5; 2992 } 2993 2994 static void 2995 re_set_jumbo(struct rl_softc *sc, int jumbo) 2996 { 2997 2998 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168E_VL) { 2999 pci_set_max_read_req(sc->rl_dev, 4096); 3000 return; 3001 } 3002 3003 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 3004 if (jumbo != 0) { 3005 CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) | 3006 RL_CFG3_JUMBO_EN0); 3007 switch (sc->rl_hwrev->rl_rev) { 3008 case RL_HWREV_8168DP: 3009 break; 3010 case RL_HWREV_8168E: 3011 CSR_WRITE_1(sc, sc->rl_cfg4, 3012 CSR_READ_1(sc, sc->rl_cfg4) | 0x01); 3013 break; 3014 default: 3015 CSR_WRITE_1(sc, sc->rl_cfg4, 3016 CSR_READ_1(sc, sc->rl_cfg4) | RL_CFG4_JUMBO_EN1); 3017 } 3018 } else { 3019 CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) & 3020 ~RL_CFG3_JUMBO_EN0); 3021 switch (sc->rl_hwrev->rl_rev) { 3022 case RL_HWREV_8168DP: 3023 break; 3024 case RL_HWREV_8168E: 3025 CSR_WRITE_1(sc, sc->rl_cfg4, 3026 CSR_READ_1(sc, sc->rl_cfg4) & ~0x01); 3027 break; 3028 default: 3029 CSR_WRITE_1(sc, sc->rl_cfg4, 3030 CSR_READ_1(sc, sc->rl_cfg4) & ~RL_CFG4_JUMBO_EN1); 3031 } 3032 } 3033 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3034 3035 switch (sc->rl_hwrev->rl_rev) { 3036 case RL_HWREV_8168DP: 3037 pci_set_max_read_req(sc->rl_dev, 4096); 3038 break; 3039 default: 3040 if (jumbo != 0) 3041 pci_set_max_read_req(sc->rl_dev, 512); 3042 else 3043 pci_set_max_read_req(sc->rl_dev, 4096); 3044 } 3045 } 3046 3047 static void 3048 re_init(void *xsc) 3049 { 3050 struct rl_softc *sc = xsc; 3051 3052 RL_LOCK(sc); 3053 re_init_locked(sc); 3054 RL_UNLOCK(sc); 3055 } 3056 3057 static void 3058 re_init_locked(struct rl_softc *sc) 3059 { 3060 struct ifnet *ifp = sc->rl_ifp; 3061 struct mii_data *mii; 3062 uint32_t reg; 3063 uint16_t cfg; 3064 union { 3065 uint32_t align_dummy; 3066 u_char eaddr[ETHER_ADDR_LEN]; 3067 } eaddr; 3068 3069 RL_LOCK_ASSERT(sc); 3070 3071 mii = device_get_softc(sc->rl_miibus); 3072 3073 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3074 return; 3075 3076 /* 3077 * Cancel pending I/O and free all RX/TX buffers. 3078 */ 3079 re_stop(sc); 3080 3081 /* Put controller into known state. */ 3082 re_reset(sc); 3083 3084 /* 3085 * For C+ mode, initialize the RX descriptors and mbufs. 3086 */ 3087 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3088 if (ifp->if_mtu > RL_MTU) { 3089 if (re_jrx_list_init(sc) != 0) { 3090 device_printf(sc->rl_dev, 3091 "no memory for jumbo RX buffers\n"); 3092 re_stop(sc); 3093 return; 3094 } 3095 /* Disable checksum offloading for jumbo frames. */ 3096 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_TSO4); 3097 ifp->if_hwassist &= ~(RE_CSUM_FEATURES | CSUM_TSO); 3098 } else { 3099 if (re_rx_list_init(sc) != 0) { 3100 device_printf(sc->rl_dev, 3101 "no memory for RX buffers\n"); 3102 re_stop(sc); 3103 return; 3104 } 3105 } 3106 re_set_jumbo(sc, ifp->if_mtu > RL_MTU); 3107 } else { 3108 if (re_rx_list_init(sc) != 0) { 3109 device_printf(sc->rl_dev, "no memory for RX buffers\n"); 3110 re_stop(sc); 3111 return; 3112 } 3113 if ((sc->rl_flags & RL_FLAG_PCIE) != 0 && 3114 pci_get_device(sc->rl_dev) != RT_DEVICEID_8101E) { 3115 if (ifp->if_mtu > RL_MTU) 3116 pci_set_max_read_req(sc->rl_dev, 512); 3117 else 3118 pci_set_max_read_req(sc->rl_dev, 4096); 3119 } 3120 } 3121 re_tx_list_init(sc); 3122 3123 /* 3124 * Enable C+ RX and TX mode, as well as VLAN stripping and 3125 * RX checksum offload. We must configure the C+ register 3126 * before all others. 3127 */ 3128 cfg = RL_CPLUSCMD_PCI_MRW; 3129 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 3130 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 3131 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3132 cfg |= RL_CPLUSCMD_VLANSTRIP; 3133 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) { 3134 cfg |= RL_CPLUSCMD_MACSTAT_DIS; 3135 /* XXX magic. */ 3136 cfg |= 0x0001; 3137 } else 3138 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB; 3139 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg); 3140 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SC || 3141 sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) { 3142 reg = 0x000fff00; 3143 if ((CSR_READ_1(sc, sc->rl_cfg2) & RL_CFG2_PCI66MHZ) != 0) 3144 reg |= 0x000000ff; 3145 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) 3146 reg |= 0x00f00000; 3147 CSR_WRITE_4(sc, 0x7c, reg); 3148 /* Disable interrupt mitigation. */ 3149 CSR_WRITE_2(sc, 0xe2, 0); 3150 } 3151 /* 3152 * Disable TSO if interface MTU size is greater than MSS 3153 * allowed in controller. 3154 */ 3155 if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) { 3156 ifp->if_capenable &= ~IFCAP_TSO4; 3157 ifp->if_hwassist &= ~CSUM_TSO; 3158 } 3159 3160 /* 3161 * Init our MAC address. Even though the chipset 3162 * documentation doesn't mention it, we need to enter "Config 3163 * register write enable" mode to modify the ID registers. 3164 */ 3165 /* Copy MAC address on stack to align. */ 3166 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 3167 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 3168 CSR_WRITE_4(sc, RL_IDR0, 3169 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 3170 CSR_WRITE_4(sc, RL_IDR4, 3171 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 3172 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3173 3174 /* 3175 * Load the addresses of the RX and TX lists into the chip. 3176 */ 3177 3178 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 3179 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 3180 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 3181 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 3182 3183 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 3184 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 3185 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 3186 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 3187 3188 if ((sc->rl_flags & RL_FLAG_RXDV_GATED) != 0) 3189 CSR_WRITE_4(sc, RL_MISC, CSR_READ_4(sc, RL_MISC) & 3190 ~0x00080000); 3191 3192 /* 3193 * Enable transmit and receive. 3194 */ 3195 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 3196 3197 /* 3198 * Set the initial TX configuration. 3199 */ 3200 if (sc->rl_testmode) { 3201 if (sc->rl_type == RL_8169) 3202 CSR_WRITE_4(sc, RL_TXCFG, 3203 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 3204 else 3205 CSR_WRITE_4(sc, RL_TXCFG, 3206 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 3207 } else 3208 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 3209 3210 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 3211 3212 /* 3213 * Set the initial RX configuration. 3214 */ 3215 re_set_rxmode(sc); 3216 3217 /* Configure interrupt moderation. */ 3218 if (sc->rl_type == RL_8169) { 3219 /* Magic from vendor. */ 3220 CSR_WRITE_2(sc, RL_INTRMOD, 0x5100); 3221 } 3222 3223 #ifdef DEVICE_POLLING 3224 /* 3225 * Disable interrupts if we are polling. 3226 */ 3227 if (ifp->if_capenable & IFCAP_POLLING) 3228 CSR_WRITE_2(sc, RL_IMR, 0); 3229 else /* otherwise ... */ 3230 #endif 3231 3232 /* 3233 * Enable interrupts. 3234 */ 3235 if (sc->rl_testmode) 3236 CSR_WRITE_2(sc, RL_IMR, 0); 3237 else 3238 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 3239 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 3240 3241 /* Set initial TX threshold */ 3242 sc->rl_txthresh = RL_TX_THRESH_INIT; 3243 3244 /* Start RX/TX process. */ 3245 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 3246 #ifdef notdef 3247 /* Enable receiver and transmitter. */ 3248 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 3249 #endif 3250 3251 /* 3252 * Initialize the timer interrupt register so that 3253 * a timer interrupt will be generated once the timer 3254 * reaches a certain number of ticks. The timer is 3255 * reloaded on each transmit. 3256 */ 3257 #ifdef RE_TX_MODERATION 3258 /* 3259 * Use timer interrupt register to moderate TX interrupt 3260 * moderation, which dramatically improves TX frame rate. 3261 */ 3262 if (sc->rl_type == RL_8169) 3263 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 3264 else 3265 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 3266 #else 3267 /* 3268 * Use timer interrupt register to moderate RX interrupt 3269 * moderation. 3270 */ 3271 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 && 3272 intr_filter == 0) { 3273 if (sc->rl_type == RL_8169) 3274 CSR_WRITE_4(sc, RL_TIMERINT_8169, 3275 RL_USECS(sc->rl_int_rx_mod)); 3276 } else { 3277 if (sc->rl_type == RL_8169) 3278 CSR_WRITE_4(sc, RL_TIMERINT_8169, RL_USECS(0)); 3279 } 3280 #endif 3281 3282 /* 3283 * For 8169 gigE NICs, set the max allowed RX packet 3284 * size so we can receive jumbo frames. 3285 */ 3286 if (sc->rl_type == RL_8169) { 3287 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3288 /* 3289 * For controllers that use new jumbo frame scheme, 3290 * set maximum size of jumbo frame depending on 3291 * controller revisions. 3292 */ 3293 if (ifp->if_mtu > RL_MTU) 3294 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 3295 sc->rl_hwrev->rl_max_mtu + 3296 ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN + 3297 ETHER_CRC_LEN); 3298 else 3299 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 3300 RE_RX_DESC_BUFLEN); 3301 } else if ((sc->rl_flags & RL_FLAG_PCIE) != 0 && 3302 sc->rl_hwrev->rl_max_mtu == RL_MTU) { 3303 /* RTL810x has no jumbo frame support. */ 3304 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, RE_RX_DESC_BUFLEN); 3305 } else 3306 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 3307 } 3308 3309 if (sc->rl_testmode) 3310 return; 3311 3312 CSR_WRITE_1(sc, sc->rl_cfg1, CSR_READ_1(sc, sc->rl_cfg1) | 3313 RL_CFG1_DRVLOAD); 3314 3315 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3316 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3317 3318 sc->rl_flags &= ~RL_FLAG_LINK; 3319 mii_mediachg(mii); 3320 3321 sc->rl_watchdog_timer = 0; 3322 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 3323 } 3324 3325 /* 3326 * Set media options. 3327 */ 3328 static int 3329 re_ifmedia_upd(struct ifnet *ifp) 3330 { 3331 struct rl_softc *sc; 3332 struct mii_data *mii; 3333 int error; 3334 3335 sc = ifp->if_softc; 3336 mii = device_get_softc(sc->rl_miibus); 3337 RL_LOCK(sc); 3338 error = mii_mediachg(mii); 3339 RL_UNLOCK(sc); 3340 3341 return (error); 3342 } 3343 3344 /* 3345 * Report current media status. 3346 */ 3347 static void 3348 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3349 { 3350 struct rl_softc *sc; 3351 struct mii_data *mii; 3352 3353 sc = ifp->if_softc; 3354 mii = device_get_softc(sc->rl_miibus); 3355 3356 RL_LOCK(sc); 3357 mii_pollstat(mii); 3358 ifmr->ifm_active = mii->mii_media_active; 3359 ifmr->ifm_status = mii->mii_media_status; 3360 RL_UNLOCK(sc); 3361 } 3362 3363 static int 3364 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3365 { 3366 struct rl_softc *sc = ifp->if_softc; 3367 struct ifreq *ifr = (struct ifreq *) data; 3368 struct mii_data *mii; 3369 int error = 0; 3370 3371 switch (command) { 3372 case SIOCSIFMTU: 3373 if (ifr->ifr_mtu < ETHERMIN || 3374 ifr->ifr_mtu > sc->rl_hwrev->rl_max_mtu || 3375 ((sc->rl_flags & RL_FLAG_FASTETHER) != 0 && 3376 ifr->ifr_mtu > RL_MTU)) { 3377 error = EINVAL; 3378 break; 3379 } 3380 RL_LOCK(sc); 3381 if (ifp->if_mtu != ifr->ifr_mtu) { 3382 ifp->if_mtu = ifr->ifr_mtu; 3383 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 3384 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3385 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3386 re_init_locked(sc); 3387 } 3388 if (ifp->if_mtu > RL_TSO_MTU && 3389 (ifp->if_capenable & IFCAP_TSO4) != 0) { 3390 ifp->if_capenable &= ~(IFCAP_TSO4 | 3391 IFCAP_VLAN_HWTSO); 3392 ifp->if_hwassist &= ~CSUM_TSO; 3393 } 3394 VLAN_CAPABILITIES(ifp); 3395 } 3396 RL_UNLOCK(sc); 3397 break; 3398 case SIOCSIFFLAGS: 3399 RL_LOCK(sc); 3400 if ((ifp->if_flags & IFF_UP) != 0) { 3401 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3402 if (((ifp->if_flags ^ sc->rl_if_flags) 3403 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 3404 re_set_rxmode(sc); 3405 } else 3406 re_init_locked(sc); 3407 } else { 3408 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3409 re_stop(sc); 3410 } 3411 sc->rl_if_flags = ifp->if_flags; 3412 RL_UNLOCK(sc); 3413 break; 3414 case SIOCADDMULTI: 3415 case SIOCDELMULTI: 3416 RL_LOCK(sc); 3417 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3418 re_set_rxmode(sc); 3419 RL_UNLOCK(sc); 3420 break; 3421 case SIOCGIFMEDIA: 3422 case SIOCSIFMEDIA: 3423 mii = device_get_softc(sc->rl_miibus); 3424 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3425 break; 3426 case SIOCSIFCAP: 3427 { 3428 int mask, reinit; 3429 3430 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3431 reinit = 0; 3432 #ifdef DEVICE_POLLING 3433 if (mask & IFCAP_POLLING) { 3434 if (ifr->ifr_reqcap & IFCAP_POLLING) { 3435 error = ether_poll_register(re_poll, ifp); 3436 if (error) 3437 return (error); 3438 RL_LOCK(sc); 3439 /* Disable interrupts */ 3440 CSR_WRITE_2(sc, RL_IMR, 0x0000); 3441 ifp->if_capenable |= IFCAP_POLLING; 3442 RL_UNLOCK(sc); 3443 } else { 3444 error = ether_poll_deregister(ifp); 3445 /* Enable interrupts. */ 3446 RL_LOCK(sc); 3447 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 3448 ifp->if_capenable &= ~IFCAP_POLLING; 3449 RL_UNLOCK(sc); 3450 } 3451 } 3452 #endif /* DEVICE_POLLING */ 3453 RL_LOCK(sc); 3454 if ((mask & IFCAP_TXCSUM) != 0 && 3455 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 3456 ifp->if_capenable ^= IFCAP_TXCSUM; 3457 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 3458 ifp->if_hwassist |= RE_CSUM_FEATURES; 3459 else 3460 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 3461 reinit = 1; 3462 } 3463 if ((mask & IFCAP_RXCSUM) != 0 && 3464 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 3465 ifp->if_capenable ^= IFCAP_RXCSUM; 3466 reinit = 1; 3467 } 3468 if ((mask & IFCAP_TSO4) != 0 && 3469 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 3470 ifp->if_capenable ^= IFCAP_TSO4; 3471 if ((IFCAP_TSO4 & ifp->if_capenable) != 0) 3472 ifp->if_hwassist |= CSUM_TSO; 3473 else 3474 ifp->if_hwassist &= ~CSUM_TSO; 3475 if (ifp->if_mtu > RL_TSO_MTU && 3476 (ifp->if_capenable & IFCAP_TSO4) != 0) { 3477 ifp->if_capenable &= ~IFCAP_TSO4; 3478 ifp->if_hwassist &= ~CSUM_TSO; 3479 } 3480 } 3481 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 3482 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 3483 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 3484 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3485 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 3486 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 3487 /* TSO over VLAN requires VLAN hardware tagging. */ 3488 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 3489 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 3490 reinit = 1; 3491 } 3492 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 3493 (mask & (IFCAP_HWCSUM | IFCAP_TSO4 | 3494 IFCAP_VLAN_HWTSO)) != 0) 3495 reinit = 1; 3496 if ((mask & IFCAP_WOL) != 0 && 3497 (ifp->if_capabilities & IFCAP_WOL) != 0) { 3498 if ((mask & IFCAP_WOL_UCAST) != 0) 3499 ifp->if_capenable ^= IFCAP_WOL_UCAST; 3500 if ((mask & IFCAP_WOL_MCAST) != 0) 3501 ifp->if_capenable ^= IFCAP_WOL_MCAST; 3502 if ((mask & IFCAP_WOL_MAGIC) != 0) 3503 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 3504 } 3505 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) { 3506 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3507 re_init_locked(sc); 3508 } 3509 RL_UNLOCK(sc); 3510 VLAN_CAPABILITIES(ifp); 3511 } 3512 break; 3513 default: 3514 error = ether_ioctl(ifp, command, data); 3515 break; 3516 } 3517 3518 return (error); 3519 } 3520 3521 static void 3522 re_watchdog(struct rl_softc *sc) 3523 { 3524 struct ifnet *ifp; 3525 3526 RL_LOCK_ASSERT(sc); 3527 3528 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 3529 return; 3530 3531 ifp = sc->rl_ifp; 3532 re_txeof(sc); 3533 if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) { 3534 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 3535 "-- recovering\n"); 3536 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3537 re_start_locked(ifp); 3538 return; 3539 } 3540 3541 if_printf(ifp, "watchdog timeout\n"); 3542 ifp->if_oerrors++; 3543 3544 re_rxeof(sc, NULL); 3545 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3546 re_init_locked(sc); 3547 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3548 re_start_locked(ifp); 3549 } 3550 3551 /* 3552 * Stop the adapter and free any mbufs allocated to the 3553 * RX and TX lists. 3554 */ 3555 static void 3556 re_stop(struct rl_softc *sc) 3557 { 3558 int i; 3559 struct ifnet *ifp; 3560 struct rl_txdesc *txd; 3561 struct rl_rxdesc *rxd; 3562 3563 RL_LOCK_ASSERT(sc); 3564 3565 ifp = sc->rl_ifp; 3566 3567 sc->rl_watchdog_timer = 0; 3568 callout_stop(&sc->rl_stat_callout); 3569 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3570 3571 /* 3572 * Disable accepting frames to put RX MAC into idle state. 3573 * Otherwise it's possible to get frames while stop command 3574 * execution is in progress and controller can DMA the frame 3575 * to already freed RX buffer during that period. 3576 */ 3577 CSR_WRITE_4(sc, RL_RXCFG, CSR_READ_4(sc, RL_RXCFG) & 3578 ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_MULTI | 3579 RL_RXCFG_RX_BROAD)); 3580 3581 if ((sc->rl_flags & RL_FLAG_WAIT_TXPOLL) != 0) { 3582 for (i = RL_TIMEOUT; i > 0; i--) { 3583 if ((CSR_READ_1(sc, sc->rl_txstart) & 3584 RL_TXSTART_START) == 0) 3585 break; 3586 DELAY(20); 3587 } 3588 if (i == 0) 3589 device_printf(sc->rl_dev, 3590 "stopping TX poll timed out!\n"); 3591 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 3592 } else if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0) { 3593 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB | 3594 RL_CMD_RX_ENB); 3595 if ((sc->rl_flags & RL_FLAG_CMDSTOP_WAIT_TXQ) != 0) { 3596 for (i = RL_TIMEOUT; i > 0; i--) { 3597 if ((CSR_READ_4(sc, RL_TXCFG) & 3598 RL_TXCFG_QUEUE_EMPTY) != 0) 3599 break; 3600 DELAY(100); 3601 } 3602 if (i == 0) 3603 device_printf(sc->rl_dev, 3604 "stopping TXQ timed out!\n"); 3605 } 3606 } else 3607 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 3608 DELAY(1000); 3609 CSR_WRITE_2(sc, RL_IMR, 0x0000); 3610 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 3611 3612 if (sc->rl_head != NULL) { 3613 m_freem(sc->rl_head); 3614 sc->rl_head = sc->rl_tail = NULL; 3615 } 3616 3617 /* Free the TX list buffers. */ 3618 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 3619 txd = &sc->rl_ldata.rl_tx_desc[i]; 3620 if (txd->tx_m != NULL) { 3621 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 3622 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3623 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 3624 txd->tx_dmamap); 3625 m_freem(txd->tx_m); 3626 txd->tx_m = NULL; 3627 } 3628 } 3629 3630 /* Free the RX list buffers. */ 3631 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 3632 rxd = &sc->rl_ldata.rl_rx_desc[i]; 3633 if (rxd->rx_m != NULL) { 3634 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 3635 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3636 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 3637 rxd->rx_dmamap); 3638 m_freem(rxd->rx_m); 3639 rxd->rx_m = NULL; 3640 } 3641 } 3642 3643 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3644 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 3645 rxd = &sc->rl_ldata.rl_jrx_desc[i]; 3646 if (rxd->rx_m != NULL) { 3647 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, 3648 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3649 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, 3650 rxd->rx_dmamap); 3651 m_freem(rxd->rx_m); 3652 rxd->rx_m = NULL; 3653 } 3654 } 3655 } 3656 } 3657 3658 /* 3659 * Device suspend routine. Stop the interface and save some PCI 3660 * settings in case the BIOS doesn't restore them properly on 3661 * resume. 3662 */ 3663 static int 3664 re_suspend(device_t dev) 3665 { 3666 struct rl_softc *sc; 3667 3668 sc = device_get_softc(dev); 3669 3670 RL_LOCK(sc); 3671 re_stop(sc); 3672 re_setwol(sc); 3673 sc->suspended = 1; 3674 RL_UNLOCK(sc); 3675 3676 return (0); 3677 } 3678 3679 /* 3680 * Device resume routine. Restore some PCI settings in case the BIOS 3681 * doesn't, re-enable busmastering, and restart the interface if 3682 * appropriate. 3683 */ 3684 static int 3685 re_resume(device_t dev) 3686 { 3687 struct rl_softc *sc; 3688 struct ifnet *ifp; 3689 3690 sc = device_get_softc(dev); 3691 3692 RL_LOCK(sc); 3693 3694 ifp = sc->rl_ifp; 3695 /* Take controller out of sleep mode. */ 3696 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3697 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3698 CSR_WRITE_1(sc, RL_GPIO, 3699 CSR_READ_1(sc, RL_GPIO) | 0x01); 3700 } 3701 3702 /* 3703 * Clear WOL matching such that normal Rx filtering 3704 * wouldn't interfere with WOL patterns. 3705 */ 3706 re_clrwol(sc); 3707 3708 /* reinitialize interface if necessary */ 3709 if (ifp->if_flags & IFF_UP) 3710 re_init_locked(sc); 3711 3712 sc->suspended = 0; 3713 RL_UNLOCK(sc); 3714 3715 return (0); 3716 } 3717 3718 /* 3719 * Stop all chip I/O so that the kernel's probe routines don't 3720 * get confused by errant DMAs when rebooting. 3721 */ 3722 static int 3723 re_shutdown(device_t dev) 3724 { 3725 struct rl_softc *sc; 3726 3727 sc = device_get_softc(dev); 3728 3729 RL_LOCK(sc); 3730 re_stop(sc); 3731 /* 3732 * Mark interface as down since otherwise we will panic if 3733 * interrupt comes in later on, which can happen in some 3734 * cases. 3735 */ 3736 sc->rl_ifp->if_flags &= ~IFF_UP; 3737 re_setwol(sc); 3738 RL_UNLOCK(sc); 3739 3740 return (0); 3741 } 3742 3743 static void 3744 re_set_linkspeed(struct rl_softc *sc) 3745 { 3746 struct mii_softc *miisc; 3747 struct mii_data *mii; 3748 int aneg, i, phyno; 3749 3750 RL_LOCK_ASSERT(sc); 3751 3752 mii = device_get_softc(sc->rl_miibus); 3753 mii_pollstat(mii); 3754 aneg = 0; 3755 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 3756 (IFM_ACTIVE | IFM_AVALID)) { 3757 switch IFM_SUBTYPE(mii->mii_media_active) { 3758 case IFM_10_T: 3759 case IFM_100_TX: 3760 return; 3761 case IFM_1000_T: 3762 aneg++; 3763 break; 3764 default: 3765 break; 3766 } 3767 } 3768 miisc = LIST_FIRST(&mii->mii_phys); 3769 phyno = miisc->mii_phy; 3770 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 3771 PHY_RESET(miisc); 3772 re_miibus_writereg(sc->rl_dev, phyno, MII_100T2CR, 0); 3773 re_miibus_writereg(sc->rl_dev, phyno, 3774 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 3775 re_miibus_writereg(sc->rl_dev, phyno, 3776 MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 3777 DELAY(1000); 3778 if (aneg != 0) { 3779 /* 3780 * Poll link state until re(4) get a 10/100Mbps link. 3781 */ 3782 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 3783 mii_pollstat(mii); 3784 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 3785 == (IFM_ACTIVE | IFM_AVALID)) { 3786 switch (IFM_SUBTYPE(mii->mii_media_active)) { 3787 case IFM_10_T: 3788 case IFM_100_TX: 3789 return; 3790 default: 3791 break; 3792 } 3793 } 3794 RL_UNLOCK(sc); 3795 pause("relnk", hz); 3796 RL_LOCK(sc); 3797 } 3798 if (i == MII_ANEGTICKS_GIGE) 3799 device_printf(sc->rl_dev, 3800 "establishing a link failed, WOL may not work!"); 3801 } 3802 /* 3803 * No link, force MAC to have 100Mbps, full-duplex link. 3804 * MAC does not require reprogramming on resolved speed/duplex, 3805 * so this is just for completeness. 3806 */ 3807 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 3808 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 3809 } 3810 3811 static void 3812 re_setwol(struct rl_softc *sc) 3813 { 3814 struct ifnet *ifp; 3815 int pmc; 3816 uint16_t pmstat; 3817 uint8_t v; 3818 3819 RL_LOCK_ASSERT(sc); 3820 3821 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3822 return; 3823 3824 ifp = sc->rl_ifp; 3825 /* Put controller into sleep mode. */ 3826 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3827 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3828 CSR_WRITE_1(sc, RL_GPIO, 3829 CSR_READ_1(sc, RL_GPIO) & ~0x01); 3830 } 3831 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 3832 re_set_rxmode(sc); 3833 if ((sc->rl_flags & RL_FLAG_WOL_MANLINK) != 0) 3834 re_set_linkspeed(sc); 3835 if ((sc->rl_flags & RL_FLAG_WOLRXENB) != 0) 3836 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB); 3837 } 3838 /* Enable config register write. */ 3839 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3840 3841 /* Enable PME. */ 3842 v = CSR_READ_1(sc, sc->rl_cfg1); 3843 v &= ~RL_CFG1_PME; 3844 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3845 v |= RL_CFG1_PME; 3846 CSR_WRITE_1(sc, sc->rl_cfg1, v); 3847 3848 v = CSR_READ_1(sc, sc->rl_cfg3); 3849 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3850 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3851 v |= RL_CFG3_WOL_MAGIC; 3852 CSR_WRITE_1(sc, sc->rl_cfg3, v); 3853 3854 v = CSR_READ_1(sc, sc->rl_cfg5); 3855 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST | 3856 RL_CFG5_WOL_LANWAKE); 3857 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 3858 v |= RL_CFG5_WOL_UCAST; 3859 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 3860 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 3861 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3862 v |= RL_CFG5_WOL_LANWAKE; 3863 CSR_WRITE_1(sc, sc->rl_cfg5, v); 3864 3865 /* Config register write done. */ 3866 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3867 3868 if ((ifp->if_capenable & IFCAP_WOL) == 0 && 3869 (sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) 3870 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) & ~0x80); 3871 /* 3872 * It seems that hardware resets its link speed to 100Mbps in 3873 * power down mode so switching to 100Mbps in driver is not 3874 * needed. 3875 */ 3876 3877 /* Request PME if WOL is requested. */ 3878 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 3879 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3880 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3881 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3882 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 3883 } 3884 3885 static void 3886 re_clrwol(struct rl_softc *sc) 3887 { 3888 int pmc; 3889 uint8_t v; 3890 3891 RL_LOCK_ASSERT(sc); 3892 3893 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3894 return; 3895 3896 /* Enable config register write. */ 3897 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3898 3899 v = CSR_READ_1(sc, sc->rl_cfg3); 3900 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3901 CSR_WRITE_1(sc, sc->rl_cfg3, v); 3902 3903 /* Config register write done. */ 3904 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3905 3906 v = CSR_READ_1(sc, sc->rl_cfg5); 3907 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3908 v &= ~RL_CFG5_WOL_LANWAKE; 3909 CSR_WRITE_1(sc, sc->rl_cfg5, v); 3910 } 3911 3912 static void 3913 re_add_sysctls(struct rl_softc *sc) 3914 { 3915 struct sysctl_ctx_list *ctx; 3916 struct sysctl_oid_list *children; 3917 int error; 3918 3919 ctx = device_get_sysctl_ctx(sc->rl_dev); 3920 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev)); 3921 3922 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "stats", 3923 CTLTYPE_INT | CTLFLAG_RW, sc, 0, re_sysctl_stats, "I", 3924 "Statistics Information"); 3925 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) 3926 return; 3927 3928 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "int_rx_mod", 3929 CTLTYPE_INT | CTLFLAG_RW, &sc->rl_int_rx_mod, 0, 3930 sysctl_hw_re_int_mod, "I", "re RX interrupt moderation"); 3931 /* Pull in device tunables. */ 3932 sc->rl_int_rx_mod = RL_TIMER_DEFAULT; 3933 error = resource_int_value(device_get_name(sc->rl_dev), 3934 device_get_unit(sc->rl_dev), "int_rx_mod", &sc->rl_int_rx_mod); 3935 if (error == 0) { 3936 if (sc->rl_int_rx_mod < RL_TIMER_MIN || 3937 sc->rl_int_rx_mod > RL_TIMER_MAX) { 3938 device_printf(sc->rl_dev, "int_rx_mod value out of " 3939 "range; using default: %d\n", 3940 RL_TIMER_DEFAULT); 3941 sc->rl_int_rx_mod = RL_TIMER_DEFAULT; 3942 } 3943 } 3944 3945 } 3946 3947 static int 3948 re_sysctl_stats(SYSCTL_HANDLER_ARGS) 3949 { 3950 struct rl_softc *sc; 3951 struct rl_stats *stats; 3952 int error, i, result; 3953 3954 result = -1; 3955 error = sysctl_handle_int(oidp, &result, 0, req); 3956 if (error || req->newptr == NULL) 3957 return (error); 3958 3959 if (result == 1) { 3960 sc = (struct rl_softc *)arg1; 3961 RL_LOCK(sc); 3962 if ((sc->rl_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 3963 RL_UNLOCK(sc); 3964 goto done; 3965 } 3966 bus_dmamap_sync(sc->rl_ldata.rl_stag, 3967 sc->rl_ldata.rl_smap, BUS_DMASYNC_PREREAD); 3968 CSR_WRITE_4(sc, RL_DUMPSTATS_HI, 3969 RL_ADDR_HI(sc->rl_ldata.rl_stats_addr)); 3970 CSR_WRITE_4(sc, RL_DUMPSTATS_LO, 3971 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr)); 3972 CSR_WRITE_4(sc, RL_DUMPSTATS_LO, 3973 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr | 3974 RL_DUMPSTATS_START)); 3975 for (i = RL_TIMEOUT; i > 0; i--) { 3976 if ((CSR_READ_4(sc, RL_DUMPSTATS_LO) & 3977 RL_DUMPSTATS_START) == 0) 3978 break; 3979 DELAY(1000); 3980 } 3981 bus_dmamap_sync(sc->rl_ldata.rl_stag, 3982 sc->rl_ldata.rl_smap, BUS_DMASYNC_POSTREAD); 3983 RL_UNLOCK(sc); 3984 if (i == 0) { 3985 device_printf(sc->rl_dev, 3986 "DUMP statistics request timed out\n"); 3987 return (ETIMEDOUT); 3988 } 3989 done: 3990 stats = sc->rl_ldata.rl_stats; 3991 printf("%s statistics:\n", device_get_nameunit(sc->rl_dev)); 3992 printf("Tx frames : %ju\n", 3993 (uintmax_t)le64toh(stats->rl_tx_pkts)); 3994 printf("Rx frames : %ju\n", 3995 (uintmax_t)le64toh(stats->rl_rx_pkts)); 3996 printf("Tx errors : %ju\n", 3997 (uintmax_t)le64toh(stats->rl_tx_errs)); 3998 printf("Rx errors : %u\n", 3999 le32toh(stats->rl_rx_errs)); 4000 printf("Rx missed frames : %u\n", 4001 (uint32_t)le16toh(stats->rl_missed_pkts)); 4002 printf("Rx frame alignment errs : %u\n", 4003 (uint32_t)le16toh(stats->rl_rx_framealign_errs)); 4004 printf("Tx single collisions : %u\n", 4005 le32toh(stats->rl_tx_onecoll)); 4006 printf("Tx multiple collisions : %u\n", 4007 le32toh(stats->rl_tx_multicolls)); 4008 printf("Rx unicast frames : %ju\n", 4009 (uintmax_t)le64toh(stats->rl_rx_ucasts)); 4010 printf("Rx broadcast frames : %ju\n", 4011 (uintmax_t)le64toh(stats->rl_rx_bcasts)); 4012 printf("Rx multicast frames : %u\n", 4013 le32toh(stats->rl_rx_mcasts)); 4014 printf("Tx aborts : %u\n", 4015 (uint32_t)le16toh(stats->rl_tx_aborts)); 4016 printf("Tx underruns : %u\n", 4017 (uint32_t)le16toh(stats->rl_rx_underruns)); 4018 } 4019 4020 return (error); 4021 } 4022 4023 static int 4024 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4025 { 4026 int error, value; 4027 4028 if (arg1 == NULL) 4029 return (EINVAL); 4030 value = *(int *)arg1; 4031 error = sysctl_handle_int(oidp, &value, 0, req); 4032 if (error || req->newptr == NULL) 4033 return (error); 4034 if (value < low || value > high) 4035 return (EINVAL); 4036 *(int *)arg1 = value; 4037 4038 return (0); 4039 } 4040 4041 static int 4042 sysctl_hw_re_int_mod(SYSCTL_HANDLER_ARGS) 4043 { 4044 4045 return (sysctl_int_range(oidp, arg1, arg2, req, RL_TIMER_MIN, 4046 RL_TIMER_MAX)); 4047 } 4048