1 /*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44 /* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111 #ifdef HAVE_KERNEL_OPTION_HEADERS 112 #include "opt_device_polling.h" 113 #endif 114 115 #include <sys/param.h> 116 #include <sys/endian.h> 117 #include <sys/systm.h> 118 #include <sys/sockio.h> 119 #include <sys/mbuf.h> 120 #include <sys/malloc.h> 121 #include <sys/module.h> 122 #include <sys/kernel.h> 123 #include <sys/socket.h> 124 #include <sys/lock.h> 125 #include <sys/mutex.h> 126 #include <sys/taskqueue.h> 127 128 #include <net/if.h> 129 #include <net/if_arp.h> 130 #include <net/ethernet.h> 131 #include <net/if_dl.h> 132 #include <net/if_media.h> 133 #include <net/if_types.h> 134 #include <net/if_vlan_var.h> 135 136 #include <net/bpf.h> 137 138 #include <machine/bus.h> 139 #include <machine/resource.h> 140 #include <sys/bus.h> 141 #include <sys/rman.h> 142 143 #include <dev/mii/mii.h> 144 #include <dev/mii/miivar.h> 145 146 #include <dev/pci/pcireg.h> 147 #include <dev/pci/pcivar.h> 148 149 #include <pci/if_rlreg.h> 150 151 MODULE_DEPEND(re, pci, 1, 1, 1); 152 MODULE_DEPEND(re, ether, 1, 1, 1); 153 MODULE_DEPEND(re, miibus, 1, 1, 1); 154 155 /* "device miibus" required. See GENERIC if you get errors here. */ 156 #include "miibus_if.h" 157 158 /* Tunables. */ 159 static int msi_disable = 1; 160 TUNABLE_INT("hw.re.msi_disable", &msi_disable); 161 162 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 163 164 /* 165 * Various supported device vendors/types and their names. 166 */ 167 static struct rl_type re_devs[] = { 168 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0, 169 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 170 { RT_VENDORID, RT_DEVICEID_8139, 0, 171 "RealTek 8139C+ 10/100BaseTX" }, 172 { RT_VENDORID, RT_DEVICEID_8101E, 0, 173 "RealTek 8101E/8102E/8102EL PCIe 10/100baseTX" }, 174 { RT_VENDORID, RT_DEVICEID_8168, 0, 175 "RealTek 8168/8168B/8168C/8168CP/8168D/8111B/8111C/8111CP PCIe " 176 "Gigabit Ethernet" }, 177 { RT_VENDORID, RT_DEVICEID_8169, 0, 178 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" }, 179 { RT_VENDORID, RT_DEVICEID_8169SC, 0, 180 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 181 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0, 182 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 183 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0, 184 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 185 { USR_VENDORID, USR_DEVICEID_997902, 0, 186 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 187 }; 188 189 static struct rl_hwrev re_hwrevs[] = { 190 { RL_HWREV_8139, RL_8139, "" }, 191 { RL_HWREV_8139A, RL_8139, "A" }, 192 { RL_HWREV_8139AG, RL_8139, "A-G" }, 193 { RL_HWREV_8139B, RL_8139, "B" }, 194 { RL_HWREV_8130, RL_8139, "8130" }, 195 { RL_HWREV_8139C, RL_8139, "C" }, 196 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 197 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 198 { RL_HWREV_8168_SPIN1, RL_8169, "8168"}, 199 { RL_HWREV_8169, RL_8169, "8169"}, 200 { RL_HWREV_8169S, RL_8169, "8169S"}, 201 { RL_HWREV_8110S, RL_8169, "8110S"}, 202 { RL_HWREV_8169_8110SB, RL_8169, "8169SB"}, 203 { RL_HWREV_8169_8110SC, RL_8169, "8169SC"}, 204 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL"}, 205 { RL_HWREV_8100, RL_8139, "8100"}, 206 { RL_HWREV_8101, RL_8139, "8101"}, 207 { RL_HWREV_8100E, RL_8169, "8100E"}, 208 { RL_HWREV_8101E, RL_8169, "8101E"}, 209 { RL_HWREV_8102E, RL_8169, "8102E"}, 210 { RL_HWREV_8102EL, RL_8169, "8102EL"}, 211 { RL_HWREV_8168_SPIN2, RL_8169, "8168"}, 212 { RL_HWREV_8168_SPIN3, RL_8169, "8168"}, 213 { RL_HWREV_8168C, RL_8169, "8168C/8111C"}, 214 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C"}, 215 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP"}, 216 { RL_HWREV_8168D, RL_8169, "8168D"}, 217 { 0, 0, NULL } 218 }; 219 220 static int re_probe (device_t); 221 static int re_attach (device_t); 222 static int re_detach (device_t); 223 224 static int re_encap (struct rl_softc *, struct mbuf **); 225 226 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 227 static int re_allocmem (device_t, struct rl_softc *); 228 static __inline void re_discard_rxbuf 229 (struct rl_softc *, int); 230 static int re_newbuf (struct rl_softc *, int); 231 static int re_rx_list_init (struct rl_softc *); 232 static int re_tx_list_init (struct rl_softc *); 233 #ifdef RE_FIXUP_RX 234 static __inline void re_fixup_rx 235 (struct mbuf *); 236 #endif 237 static int re_rxeof (struct rl_softc *); 238 static void re_txeof (struct rl_softc *); 239 #ifdef DEVICE_POLLING 240 static void re_poll (struct ifnet *, enum poll_cmd, int); 241 static void re_poll_locked (struct ifnet *, enum poll_cmd, int); 242 #endif 243 static int re_intr (void *); 244 static void re_tick (void *); 245 static void re_tx_task (void *, int); 246 static void re_int_task (void *, int); 247 static void re_start (struct ifnet *); 248 static int re_ioctl (struct ifnet *, u_long, caddr_t); 249 static void re_init (void *); 250 static void re_init_locked (struct rl_softc *); 251 static void re_stop (struct rl_softc *); 252 static void re_watchdog (struct rl_softc *); 253 static int re_suspend (device_t); 254 static int re_resume (device_t); 255 static int re_shutdown (device_t); 256 static int re_ifmedia_upd (struct ifnet *); 257 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 258 259 static void re_eeprom_putbyte (struct rl_softc *, int); 260 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 261 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 262 static int re_gmii_readreg (device_t, int, int); 263 static int re_gmii_writereg (device_t, int, int, int); 264 265 static int re_miibus_readreg (device_t, int, int); 266 static int re_miibus_writereg (device_t, int, int, int); 267 static void re_miibus_statchg (device_t); 268 269 static void re_setmulti (struct rl_softc *); 270 static void re_reset (struct rl_softc *); 271 static void re_setwol (struct rl_softc *); 272 static void re_clrwol (struct rl_softc *); 273 274 #ifdef RE_DIAG 275 static int re_diag (struct rl_softc *); 276 #endif 277 278 static device_method_t re_methods[] = { 279 /* Device interface */ 280 DEVMETHOD(device_probe, re_probe), 281 DEVMETHOD(device_attach, re_attach), 282 DEVMETHOD(device_detach, re_detach), 283 DEVMETHOD(device_suspend, re_suspend), 284 DEVMETHOD(device_resume, re_resume), 285 DEVMETHOD(device_shutdown, re_shutdown), 286 287 /* bus interface */ 288 DEVMETHOD(bus_print_child, bus_generic_print_child), 289 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 290 291 /* MII interface */ 292 DEVMETHOD(miibus_readreg, re_miibus_readreg), 293 DEVMETHOD(miibus_writereg, re_miibus_writereg), 294 DEVMETHOD(miibus_statchg, re_miibus_statchg), 295 296 { 0, 0 } 297 }; 298 299 static driver_t re_driver = { 300 "re", 301 re_methods, 302 sizeof(struct rl_softc) 303 }; 304 305 static devclass_t re_devclass; 306 307 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 308 DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0); 309 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 310 311 #define EE_SET(x) \ 312 CSR_WRITE_1(sc, RL_EECMD, \ 313 CSR_READ_1(sc, RL_EECMD) | x) 314 315 #define EE_CLR(x) \ 316 CSR_WRITE_1(sc, RL_EECMD, \ 317 CSR_READ_1(sc, RL_EECMD) & ~x) 318 319 /* 320 * Send a read command and address to the EEPROM, check for ACK. 321 */ 322 static void 323 re_eeprom_putbyte(struct rl_softc *sc, int addr) 324 { 325 int d, i; 326 327 d = addr | (RL_9346_READ << sc->rl_eewidth); 328 329 /* 330 * Feed in each bit and strobe the clock. 331 */ 332 333 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 334 if (d & i) { 335 EE_SET(RL_EE_DATAIN); 336 } else { 337 EE_CLR(RL_EE_DATAIN); 338 } 339 DELAY(100); 340 EE_SET(RL_EE_CLK); 341 DELAY(150); 342 EE_CLR(RL_EE_CLK); 343 DELAY(100); 344 } 345 } 346 347 /* 348 * Read a word of data stored in the EEPROM at address 'addr.' 349 */ 350 static void 351 re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest) 352 { 353 int i; 354 u_int16_t word = 0; 355 356 /* 357 * Send address of word we want to read. 358 */ 359 re_eeprom_putbyte(sc, addr); 360 361 /* 362 * Start reading bits from EEPROM. 363 */ 364 for (i = 0x8000; i; i >>= 1) { 365 EE_SET(RL_EE_CLK); 366 DELAY(100); 367 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 368 word |= i; 369 EE_CLR(RL_EE_CLK); 370 DELAY(100); 371 } 372 373 *dest = word; 374 } 375 376 /* 377 * Read a sequence of words from the EEPROM. 378 */ 379 static void 380 re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt) 381 { 382 int i; 383 u_int16_t word = 0, *ptr; 384 385 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 386 387 DELAY(100); 388 389 for (i = 0; i < cnt; i++) { 390 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 391 re_eeprom_getword(sc, off + i, &word); 392 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 393 ptr = (u_int16_t *)(dest + (i * 2)); 394 *ptr = word; 395 } 396 397 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 398 } 399 400 static int 401 re_gmii_readreg(device_t dev, int phy, int reg) 402 { 403 struct rl_softc *sc; 404 u_int32_t rval; 405 int i; 406 407 if (phy != 1) 408 return (0); 409 410 sc = device_get_softc(dev); 411 412 /* Let the rgephy driver read the GMEDIASTAT register */ 413 414 if (reg == RL_GMEDIASTAT) { 415 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 416 return (rval); 417 } 418 419 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 420 DELAY(1000); 421 422 for (i = 0; i < RL_TIMEOUT; i++) { 423 rval = CSR_READ_4(sc, RL_PHYAR); 424 if (rval & RL_PHYAR_BUSY) 425 break; 426 DELAY(100); 427 } 428 429 if (i == RL_TIMEOUT) { 430 device_printf(sc->rl_dev, "PHY read failed\n"); 431 return (0); 432 } 433 434 return (rval & RL_PHYAR_PHYDATA); 435 } 436 437 static int 438 re_gmii_writereg(device_t dev, int phy, int reg, int data) 439 { 440 struct rl_softc *sc; 441 u_int32_t rval; 442 int i; 443 444 sc = device_get_softc(dev); 445 446 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 447 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 448 DELAY(1000); 449 450 for (i = 0; i < RL_TIMEOUT; i++) { 451 rval = CSR_READ_4(sc, RL_PHYAR); 452 if (!(rval & RL_PHYAR_BUSY)) 453 break; 454 DELAY(100); 455 } 456 457 if (i == RL_TIMEOUT) { 458 device_printf(sc->rl_dev, "PHY write failed\n"); 459 return (0); 460 } 461 462 return (0); 463 } 464 465 static int 466 re_miibus_readreg(device_t dev, int phy, int reg) 467 { 468 struct rl_softc *sc; 469 u_int16_t rval = 0; 470 u_int16_t re8139_reg = 0; 471 472 sc = device_get_softc(dev); 473 474 if (sc->rl_type == RL_8169) { 475 rval = re_gmii_readreg(dev, phy, reg); 476 return (rval); 477 } 478 479 /* Pretend the internal PHY is only at address 0 */ 480 if (phy) { 481 return (0); 482 } 483 switch (reg) { 484 case MII_BMCR: 485 re8139_reg = RL_BMCR; 486 break; 487 case MII_BMSR: 488 re8139_reg = RL_BMSR; 489 break; 490 case MII_ANAR: 491 re8139_reg = RL_ANAR; 492 break; 493 case MII_ANER: 494 re8139_reg = RL_ANER; 495 break; 496 case MII_ANLPAR: 497 re8139_reg = RL_LPAR; 498 break; 499 case MII_PHYIDR1: 500 case MII_PHYIDR2: 501 return (0); 502 /* 503 * Allow the rlphy driver to read the media status 504 * register. If we have a link partner which does not 505 * support NWAY, this is the register which will tell 506 * us the results of parallel detection. 507 */ 508 case RL_MEDIASTAT: 509 rval = CSR_READ_1(sc, RL_MEDIASTAT); 510 return (rval); 511 default: 512 device_printf(sc->rl_dev, "bad phy register\n"); 513 return (0); 514 } 515 rval = CSR_READ_2(sc, re8139_reg); 516 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 517 /* 8139C+ has different bit layout. */ 518 rval &= ~(BMCR_LOOP | BMCR_ISO); 519 } 520 return (rval); 521 } 522 523 static int 524 re_miibus_writereg(device_t dev, int phy, int reg, int data) 525 { 526 struct rl_softc *sc; 527 u_int16_t re8139_reg = 0; 528 int rval = 0; 529 530 sc = device_get_softc(dev); 531 532 if (sc->rl_type == RL_8169) { 533 rval = re_gmii_writereg(dev, phy, reg, data); 534 return (rval); 535 } 536 537 /* Pretend the internal PHY is only at address 0 */ 538 if (phy) 539 return (0); 540 541 switch (reg) { 542 case MII_BMCR: 543 re8139_reg = RL_BMCR; 544 if (sc->rl_type == RL_8139CPLUS) { 545 /* 8139C+ has different bit layout. */ 546 data &= ~(BMCR_LOOP | BMCR_ISO); 547 } 548 break; 549 case MII_BMSR: 550 re8139_reg = RL_BMSR; 551 break; 552 case MII_ANAR: 553 re8139_reg = RL_ANAR; 554 break; 555 case MII_ANER: 556 re8139_reg = RL_ANER; 557 break; 558 case MII_ANLPAR: 559 re8139_reg = RL_LPAR; 560 break; 561 case MII_PHYIDR1: 562 case MII_PHYIDR2: 563 return (0); 564 break; 565 default: 566 device_printf(sc->rl_dev, "bad phy register\n"); 567 return (0); 568 } 569 CSR_WRITE_2(sc, re8139_reg, data); 570 return (0); 571 } 572 573 static void 574 re_miibus_statchg(device_t dev) 575 { 576 577 } 578 579 /* 580 * Program the 64-bit multicast hash filter. 581 */ 582 static void 583 re_setmulti(struct rl_softc *sc) 584 { 585 struct ifnet *ifp; 586 int h = 0; 587 u_int32_t hashes[2] = { 0, 0 }; 588 struct ifmultiaddr *ifma; 589 u_int32_t rxfilt; 590 int mcnt = 0; 591 592 RL_LOCK_ASSERT(sc); 593 594 ifp = sc->rl_ifp; 595 596 597 rxfilt = CSR_READ_4(sc, RL_RXCFG); 598 rxfilt &= ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_MULTI); 599 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 600 if (ifp->if_flags & IFF_PROMISC) 601 rxfilt |= RL_RXCFG_RX_ALLPHYS; 602 /* 603 * Unlike other hardwares, we have to explicitly set 604 * RL_RXCFG_RX_MULTI to receive multicast frames in 605 * promiscuous mode. 606 */ 607 rxfilt |= RL_RXCFG_RX_MULTI; 608 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 609 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 610 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 611 return; 612 } 613 614 /* first, zot all the existing hash bits */ 615 CSR_WRITE_4(sc, RL_MAR0, 0); 616 CSR_WRITE_4(sc, RL_MAR4, 0); 617 618 /* now program new ones */ 619 IF_ADDR_LOCK(ifp); 620 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 621 if (ifma->ifma_addr->sa_family != AF_LINK) 622 continue; 623 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 624 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 625 if (h < 32) 626 hashes[0] |= (1 << h); 627 else 628 hashes[1] |= (1 << (h - 32)); 629 mcnt++; 630 } 631 IF_ADDR_UNLOCK(ifp); 632 633 if (mcnt) 634 rxfilt |= RL_RXCFG_RX_MULTI; 635 else 636 rxfilt &= ~RL_RXCFG_RX_MULTI; 637 638 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 639 640 /* 641 * For some unfathomable reason, RealTek decided to reverse 642 * the order of the multicast hash registers in the PCI Express 643 * parts. This means we have to write the hash pattern in reverse 644 * order for those devices. 645 */ 646 647 if ((sc->rl_flags & RL_FLAG_INVMAR) != 0) { 648 CSR_WRITE_4(sc, RL_MAR0, bswap32(hashes[1])); 649 CSR_WRITE_4(sc, RL_MAR4, bswap32(hashes[0])); 650 } else { 651 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 652 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 653 } 654 } 655 656 static void 657 re_reset(struct rl_softc *sc) 658 { 659 int i; 660 661 RL_LOCK_ASSERT(sc); 662 663 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 664 665 for (i = 0; i < RL_TIMEOUT; i++) { 666 DELAY(10); 667 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 668 break; 669 } 670 if (i == RL_TIMEOUT) 671 device_printf(sc->rl_dev, "reset never completed!\n"); 672 673 CSR_WRITE_1(sc, 0x82, 1); 674 } 675 676 #ifdef RE_DIAG 677 678 /* 679 * The following routine is designed to test for a defect on some 680 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 681 * lines connected to the bus, however for a 32-bit only card, they 682 * should be pulled high. The result of this defect is that the 683 * NIC will not work right if you plug it into a 64-bit slot: DMA 684 * operations will be done with 64-bit transfers, which will fail 685 * because the 64-bit data lines aren't connected. 686 * 687 * There's no way to work around this (short of talking a soldering 688 * iron to the board), however we can detect it. The method we use 689 * here is to put the NIC into digital loopback mode, set the receiver 690 * to promiscuous mode, and then try to send a frame. We then compare 691 * the frame data we sent to what was received. If the data matches, 692 * then the NIC is working correctly, otherwise we know the user has 693 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 694 * slot. In the latter case, there's no way the NIC can work correctly, 695 * so we print out a message on the console and abort the device attach. 696 */ 697 698 static int 699 re_diag(struct rl_softc *sc) 700 { 701 struct ifnet *ifp = sc->rl_ifp; 702 struct mbuf *m0; 703 struct ether_header *eh; 704 struct rl_desc *cur_rx; 705 u_int16_t status; 706 u_int32_t rxstat; 707 int total_len, i, error = 0, phyaddr; 708 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 709 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 710 711 /* Allocate a single mbuf */ 712 MGETHDR(m0, M_DONTWAIT, MT_DATA); 713 if (m0 == NULL) 714 return (ENOBUFS); 715 716 RL_LOCK(sc); 717 718 /* 719 * Initialize the NIC in test mode. This sets the chip up 720 * so that it can send and receive frames, but performs the 721 * following special functions: 722 * - Puts receiver in promiscuous mode 723 * - Enables digital loopback mode 724 * - Leaves interrupts turned off 725 */ 726 727 ifp->if_flags |= IFF_PROMISC; 728 sc->rl_testmode = 1; 729 re_reset(sc); 730 re_init_locked(sc); 731 sc->rl_flags |= RL_FLAG_LINK; 732 if (sc->rl_type == RL_8169) 733 phyaddr = 1; 734 else 735 phyaddr = 0; 736 737 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 738 for (i = 0; i < RL_TIMEOUT; i++) { 739 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 740 if (!(status & BMCR_RESET)) 741 break; 742 } 743 744 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 745 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 746 747 DELAY(100000); 748 749 /* Put some data in the mbuf */ 750 751 eh = mtod(m0, struct ether_header *); 752 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 753 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 754 eh->ether_type = htons(ETHERTYPE_IP); 755 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 756 757 /* 758 * Queue the packet, start transmission. 759 * Note: IF_HANDOFF() ultimately calls re_start() for us. 760 */ 761 762 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 763 RL_UNLOCK(sc); 764 /* XXX: re_diag must not be called when in ALTQ mode */ 765 IF_HANDOFF(&ifp->if_snd, m0, ifp); 766 RL_LOCK(sc); 767 m0 = NULL; 768 769 /* Wait for it to propagate through the chip */ 770 771 DELAY(100000); 772 for (i = 0; i < RL_TIMEOUT; i++) { 773 status = CSR_READ_2(sc, RL_ISR); 774 CSR_WRITE_2(sc, RL_ISR, status); 775 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 776 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 777 break; 778 DELAY(10); 779 } 780 781 if (i == RL_TIMEOUT) { 782 device_printf(sc->rl_dev, 783 "diagnostic failed, failed to receive packet in" 784 " loopback mode\n"); 785 error = EIO; 786 goto done; 787 } 788 789 /* 790 * The packet should have been dumped into the first 791 * entry in the RX DMA ring. Grab it from there. 792 */ 793 794 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 795 sc->rl_ldata.rl_rx_list_map, 796 BUS_DMASYNC_POSTREAD); 797 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 798 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 799 BUS_DMASYNC_POSTREAD); 800 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 801 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 802 803 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 804 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 805 eh = mtod(m0, struct ether_header *); 806 807 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 808 total_len = RL_RXBYTES(cur_rx); 809 rxstat = le32toh(cur_rx->rl_cmdstat); 810 811 if (total_len != ETHER_MIN_LEN) { 812 device_printf(sc->rl_dev, 813 "diagnostic failed, received short packet\n"); 814 error = EIO; 815 goto done; 816 } 817 818 /* Test that the received packet data matches what we sent. */ 819 820 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 821 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 822 ntohs(eh->ether_type) != ETHERTYPE_IP) { 823 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 824 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 825 dst, ":", src, ":", ETHERTYPE_IP); 826 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 827 eh->ether_dhost, ":", eh->ether_shost, ":", 828 ntohs(eh->ether_type)); 829 device_printf(sc->rl_dev, "You may have a defective 32-bit " 830 "NIC plugged into a 64-bit PCI slot.\n"); 831 device_printf(sc->rl_dev, "Please re-install the NIC in a " 832 "32-bit slot for proper operation.\n"); 833 device_printf(sc->rl_dev, "Read the re(4) man page for more " 834 "details.\n"); 835 error = EIO; 836 } 837 838 done: 839 /* Turn interface off, release resources */ 840 841 sc->rl_testmode = 0; 842 sc->rl_flags &= ~RL_FLAG_LINK; 843 ifp->if_flags &= ~IFF_PROMISC; 844 re_stop(sc); 845 if (m0 != NULL) 846 m_freem(m0); 847 848 RL_UNLOCK(sc); 849 850 return (error); 851 } 852 853 #endif 854 855 /* 856 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 857 * IDs against our list and return a device name if we find a match. 858 */ 859 static int 860 re_probe(device_t dev) 861 { 862 struct rl_type *t; 863 uint16_t devid, vendor; 864 uint16_t revid, sdevid; 865 int i; 866 867 vendor = pci_get_vendor(dev); 868 devid = pci_get_device(dev); 869 revid = pci_get_revid(dev); 870 sdevid = pci_get_subdevice(dev); 871 872 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 873 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 874 /* 875 * Only attach to rev. 3 of the Linksys EG1032 adapter. 876 * Rev. 2 is supported by sk(4). 877 */ 878 return (ENXIO); 879 } 880 } 881 882 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 883 if (revid != 0x20) { 884 /* 8139, let rl(4) take care of this device. */ 885 return (ENXIO); 886 } 887 } 888 889 t = re_devs; 890 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) { 891 if (vendor == t->rl_vid && devid == t->rl_did) { 892 device_set_desc(dev, t->rl_name); 893 return (BUS_PROBE_DEFAULT); 894 } 895 } 896 897 return (ENXIO); 898 } 899 900 /* 901 * Map a single buffer address. 902 */ 903 904 static void 905 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 906 { 907 bus_addr_t *addr; 908 909 if (error) 910 return; 911 912 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 913 addr = arg; 914 *addr = segs->ds_addr; 915 } 916 917 static int 918 re_allocmem(device_t dev, struct rl_softc *sc) 919 { 920 bus_size_t rx_list_size, tx_list_size; 921 int error; 922 int i; 923 924 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 925 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 926 927 /* 928 * Allocate the parent bus DMA tag appropriate for PCI. 929 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD 930 * register should be set. However some RealTek chips are known 931 * to be buggy on DAC handling, therefore disable DAC by limiting 932 * DMA address space to 32bit. PCIe variants of RealTek chips 933 * may not have the limitation but I took safer path. 934 */ 935 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 936 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 937 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 938 NULL, NULL, &sc->rl_parent_tag); 939 if (error) { 940 device_printf(dev, "could not allocate parent DMA tag\n"); 941 return (error); 942 } 943 944 /* 945 * Allocate map for TX mbufs. 946 */ 947 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 948 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 949 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 950 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 951 if (error) { 952 device_printf(dev, "could not allocate TX DMA tag\n"); 953 return (error); 954 } 955 956 /* 957 * Allocate map for RX mbufs. 958 */ 959 960 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 961 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 962 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 963 if (error) { 964 device_printf(dev, "could not allocate RX DMA tag\n"); 965 return (error); 966 } 967 968 /* 969 * Allocate map for TX descriptor list. 970 */ 971 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 972 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 973 NULL, tx_list_size, 1, tx_list_size, 0, 974 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 975 if (error) { 976 device_printf(dev, "could not allocate TX DMA ring tag\n"); 977 return (error); 978 } 979 980 /* Allocate DMA'able memory for the TX ring */ 981 982 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 983 (void **)&sc->rl_ldata.rl_tx_list, 984 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 985 &sc->rl_ldata.rl_tx_list_map); 986 if (error) { 987 device_printf(dev, "could not allocate TX DMA ring\n"); 988 return (error); 989 } 990 991 /* Load the map for the TX ring. */ 992 993 sc->rl_ldata.rl_tx_list_addr = 0; 994 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 995 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 996 tx_list_size, re_dma_map_addr, 997 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 998 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 999 device_printf(dev, "could not load TX DMA ring\n"); 1000 return (ENOMEM); 1001 } 1002 1003 /* Create DMA maps for TX buffers */ 1004 1005 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1006 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1007 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1008 if (error) { 1009 device_printf(dev, "could not create DMA map for TX\n"); 1010 return (error); 1011 } 1012 } 1013 1014 /* 1015 * Allocate map for RX descriptor list. 1016 */ 1017 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1018 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1019 NULL, rx_list_size, 1, rx_list_size, 0, 1020 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1021 if (error) { 1022 device_printf(dev, "could not create RX DMA ring tag\n"); 1023 return (error); 1024 } 1025 1026 /* Allocate DMA'able memory for the RX ring */ 1027 1028 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1029 (void **)&sc->rl_ldata.rl_rx_list, 1030 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1031 &sc->rl_ldata.rl_rx_list_map); 1032 if (error) { 1033 device_printf(dev, "could not allocate RX DMA ring\n"); 1034 return (error); 1035 } 1036 1037 /* Load the map for the RX ring. */ 1038 1039 sc->rl_ldata.rl_rx_list_addr = 0; 1040 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1041 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1042 rx_list_size, re_dma_map_addr, 1043 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1044 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1045 device_printf(dev, "could not load RX DMA ring\n"); 1046 return (ENOMEM); 1047 } 1048 1049 /* Create DMA maps for RX buffers */ 1050 1051 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1052 &sc->rl_ldata.rl_rx_sparemap); 1053 if (error) { 1054 device_printf(dev, "could not create spare DMA map for RX\n"); 1055 return (error); 1056 } 1057 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1058 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1059 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1060 if (error) { 1061 device_printf(dev, "could not create DMA map for RX\n"); 1062 return (error); 1063 } 1064 } 1065 1066 return (0); 1067 } 1068 1069 /* 1070 * Attach the interface. Allocate softc structures, do ifmedia 1071 * setup and ethernet/BPF attach. 1072 */ 1073 static int 1074 re_attach(device_t dev) 1075 { 1076 u_char eaddr[ETHER_ADDR_LEN]; 1077 u_int16_t as[ETHER_ADDR_LEN / 2]; 1078 struct rl_softc *sc; 1079 struct ifnet *ifp; 1080 struct rl_hwrev *hw_rev; 1081 int hwrev; 1082 u_int16_t devid, re_did = 0; 1083 int error = 0, rid, i; 1084 int msic, reg; 1085 uint8_t cfg; 1086 1087 sc = device_get_softc(dev); 1088 sc->rl_dev = dev; 1089 1090 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1091 MTX_DEF); 1092 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1093 1094 /* 1095 * Map control/status registers. 1096 */ 1097 pci_enable_busmaster(dev); 1098 1099 devid = pci_get_device(dev); 1100 /* Prefer memory space register mapping over IO space. */ 1101 sc->rl_res_id = PCIR_BAR(1); 1102 sc->rl_res_type = SYS_RES_MEMORY; 1103 /* RTL8168/8101E seems to use different BARs. */ 1104 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E) 1105 sc->rl_res_id = PCIR_BAR(2); 1106 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1107 &sc->rl_res_id, RF_ACTIVE); 1108 1109 if (sc->rl_res == NULL) { 1110 sc->rl_res_id = PCIR_BAR(0); 1111 sc->rl_res_type = SYS_RES_IOPORT; 1112 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1113 &sc->rl_res_id, RF_ACTIVE); 1114 if (sc->rl_res == NULL) { 1115 device_printf(dev, "couldn't map ports/memory\n"); 1116 error = ENXIO; 1117 goto fail; 1118 } 1119 } 1120 1121 sc->rl_btag = rman_get_bustag(sc->rl_res); 1122 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1123 1124 msic = 0; 1125 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 1126 msic = pci_msi_count(dev); 1127 if (bootverbose) 1128 device_printf(dev, "MSI count : %d\n", msic); 1129 } 1130 if (msic == RL_MSI_MESSAGES && msi_disable == 0) { 1131 if (pci_alloc_msi(dev, &msic) == 0) { 1132 if (msic == RL_MSI_MESSAGES) { 1133 device_printf(dev, "Using %d MSI messages\n", 1134 msic); 1135 sc->rl_flags |= RL_FLAG_MSI; 1136 /* Explicitly set MSI enable bit. */ 1137 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1138 cfg = CSR_READ_1(sc, RL_CFG2); 1139 cfg |= RL_CFG2_MSI; 1140 CSR_WRITE_1(sc, RL_CFG2, cfg); 1141 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1142 } else 1143 pci_release_msi(dev); 1144 } 1145 } 1146 1147 /* Allocate interrupt */ 1148 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1149 rid = 0; 1150 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1151 RF_SHAREABLE | RF_ACTIVE); 1152 if (sc->rl_irq[0] == NULL) { 1153 device_printf(dev, "couldn't allocate IRQ resources\n"); 1154 error = ENXIO; 1155 goto fail; 1156 } 1157 } else { 1158 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1159 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1160 SYS_RES_IRQ, &rid, RF_ACTIVE); 1161 if (sc->rl_irq[i] == NULL) { 1162 device_printf(dev, 1163 "couldn't llocate IRQ resources for " 1164 "message %d\n", rid); 1165 error = ENXIO; 1166 goto fail; 1167 } 1168 } 1169 } 1170 1171 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1172 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1173 cfg = CSR_READ_1(sc, RL_CFG2); 1174 if ((cfg & RL_CFG2_MSI) != 0) { 1175 device_printf(dev, "turning off MSI enable bit.\n"); 1176 cfg &= ~RL_CFG2_MSI; 1177 CSR_WRITE_1(sc, RL_CFG2, cfg); 1178 } 1179 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1180 } 1181 1182 /* Reset the adapter. */ 1183 RL_LOCK(sc); 1184 re_reset(sc); 1185 RL_UNLOCK(sc); 1186 1187 hw_rev = re_hwrevs; 1188 hwrev = CSR_READ_4(sc, RL_TXCFG); 1189 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000); 1190 device_printf(dev, "MAC rev. 0x%08x\n", hwrev & 0x00700000); 1191 hwrev &= RL_TXCFG_HWREV; 1192 while (hw_rev->rl_desc != NULL) { 1193 if (hw_rev->rl_rev == hwrev) { 1194 sc->rl_type = hw_rev->rl_type; 1195 break; 1196 } 1197 hw_rev++; 1198 } 1199 if (hw_rev->rl_desc == NULL) { 1200 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev); 1201 error = ENXIO; 1202 goto fail; 1203 } 1204 1205 switch (hw_rev->rl_rev) { 1206 case RL_HWREV_8139CPLUS: 1207 sc->rl_flags |= RL_FLAG_NOJUMBO; 1208 break; 1209 case RL_HWREV_8100E: 1210 case RL_HWREV_8101E: 1211 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_INVMAR | 1212 RL_FLAG_PHYWAKE; 1213 break; 1214 case RL_HWREV_8102E: 1215 case RL_HWREV_8102EL: 1216 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_INVMAR | 1217 RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1218 RL_FLAG_MACSTAT; 1219 break; 1220 case RL_HWREV_8168_SPIN1: 1221 case RL_HWREV_8168_SPIN2: 1222 case RL_HWREV_8168_SPIN3: 1223 sc->rl_flags |= RL_FLAG_INVMAR | RL_FLAG_PHYWAKE | 1224 RL_FLAG_MACSTAT; 1225 break; 1226 case RL_HWREV_8168C: 1227 case RL_HWREV_8168C_SPIN2: 1228 case RL_HWREV_8168CP: 1229 case RL_HWREV_8168D: 1230 sc->rl_flags |= RL_FLAG_INVMAR | RL_FLAG_PHYWAKE | 1231 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT; 1232 /* 1233 * These controllers support jumbo frame but it seems 1234 * that enabling it requires touching additional magic 1235 * registers. Depending on MAC revisions some 1236 * controllers need to disable checksum offload. So 1237 * disable jumbo frame until I have better idea what 1238 * it really requires to make it support. 1239 * RTL8168C/CP : supports up to 6KB jumbo frame. 1240 * RTL8111C/CP : supports up to 9KB jumbo frame. 1241 */ 1242 sc->rl_flags |= RL_FLAG_NOJUMBO; 1243 break; 1244 case RL_HWREV_8169_8110SB: 1245 case RL_HWREV_8169_8110SC: 1246 case RL_HWREV_8169_8110SBL: 1247 sc->rl_flags |= RL_FLAG_PHYWAKE; 1248 break; 1249 default: 1250 break; 1251 } 1252 1253 /* Enable PME. */ 1254 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1255 cfg = CSR_READ_1(sc, RL_CFG1); 1256 cfg |= RL_CFG1_PME; 1257 CSR_WRITE_1(sc, RL_CFG1, cfg); 1258 cfg = CSR_READ_1(sc, RL_CFG5); 1259 cfg &= RL_CFG5_PME_STS; 1260 CSR_WRITE_1(sc, RL_CFG5, cfg); 1261 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1262 1263 if ((sc->rl_flags & RL_FLAG_PAR) != 0) { 1264 /* 1265 * XXX Should have a better way to extract station 1266 * address from EEPROM. 1267 */ 1268 for (i = 0; i < ETHER_ADDR_LEN; i++) 1269 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1270 } else { 1271 sc->rl_eewidth = RL_9356_ADDR_LEN; 1272 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1273 if (re_did != 0x8129) 1274 sc->rl_eewidth = RL_9346_ADDR_LEN; 1275 1276 /* 1277 * Get station address from the EEPROM. 1278 */ 1279 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1280 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1281 as[i] = le16toh(as[i]); 1282 bcopy(as, eaddr, sizeof(eaddr)); 1283 } 1284 1285 if (sc->rl_type == RL_8169) { 1286 /* Set RX length mask and number of descriptors. */ 1287 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1288 sc->rl_txstart = RL_GTXSTART; 1289 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1290 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1291 } else { 1292 /* Set RX length mask and number of descriptors. */ 1293 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1294 sc->rl_txstart = RL_TXSTART; 1295 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1296 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1297 } 1298 1299 error = re_allocmem(dev, sc); 1300 if (error) 1301 goto fail; 1302 1303 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1304 if (ifp == NULL) { 1305 device_printf(dev, "can not if_alloc()\n"); 1306 error = ENOSPC; 1307 goto fail; 1308 } 1309 1310 /* Take PHY out of power down mode. */ 1311 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) { 1312 re_gmii_writereg(dev, 1, 0x1f, 0); 1313 re_gmii_writereg(dev, 1, 0x0e, 0); 1314 } 1315 1316 /* Do MII setup */ 1317 if (mii_phy_probe(dev, &sc->rl_miibus, 1318 re_ifmedia_upd, re_ifmedia_sts)) { 1319 device_printf(dev, "MII without any phy!\n"); 1320 error = ENXIO; 1321 goto fail; 1322 } 1323 1324 ifp->if_softc = sc; 1325 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1326 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1327 ifp->if_ioctl = re_ioctl; 1328 ifp->if_start = re_start; 1329 ifp->if_hwassist = RE_CSUM_FEATURES; 1330 ifp->if_capabilities = IFCAP_HWCSUM; 1331 ifp->if_capenable = ifp->if_capabilities; 1332 ifp->if_init = re_init; 1333 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1334 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1335 IFQ_SET_READY(&ifp->if_snd); 1336 1337 TASK_INIT(&sc->rl_txtask, 1, re_tx_task, ifp); 1338 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1339 1340 /* 1341 * XXX 1342 * Still have no idea how to make TSO work on 8168C, 8168CP, 1343 * 8111C and 8111CP. 1344 */ 1345 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 1346 ifp->if_hwassist |= CSUM_TSO; 1347 ifp->if_capabilities |= IFCAP_TSO4; 1348 } 1349 1350 /* 1351 * Call MI attach routine. 1352 */ 1353 ether_ifattach(ifp, eaddr); 1354 1355 /* VLAN capability setup */ 1356 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1357 if (ifp->if_capabilities & IFCAP_HWCSUM) 1358 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1359 /* Enable WOL if PM is supported. */ 1360 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, ®) == 0) 1361 ifp->if_capabilities |= IFCAP_WOL; 1362 ifp->if_capenable = ifp->if_capabilities; 1363 /* 1364 * Don't enable TSO by default. Under certain 1365 * circumtances the controller generated corrupted 1366 * packets in TSO size. 1367 */ 1368 ifp->if_hwassist &= ~CSUM_TSO; 1369 ifp->if_capenable &= ~IFCAP_TSO4; 1370 #ifdef DEVICE_POLLING 1371 ifp->if_capabilities |= IFCAP_POLLING; 1372 #endif 1373 /* 1374 * Tell the upper layer(s) we support long frames. 1375 * Must appear after the call to ether_ifattach() because 1376 * ether_ifattach() sets ifi_hdrlen to the default value. 1377 */ 1378 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1379 1380 #ifdef RE_DIAG 1381 /* 1382 * Perform hardware diagnostic on the original RTL8169. 1383 * Some 32-bit cards were incorrectly wired and would 1384 * malfunction if plugged into a 64-bit slot. 1385 */ 1386 1387 if (hwrev == RL_HWREV_8169) { 1388 error = re_diag(sc); 1389 if (error) { 1390 device_printf(dev, 1391 "attach aborted due to hardware diag failure\n"); 1392 ether_ifdetach(ifp); 1393 goto fail; 1394 } 1395 } 1396 #endif 1397 1398 /* Hook interrupt last to avoid having to lock softc */ 1399 if ((sc->rl_flags & RL_FLAG_MSI) == 0) 1400 error = bus_setup_intr(dev, sc->rl_irq[0], 1401 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1402 &sc->rl_intrhand[0]); 1403 else { 1404 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1405 error = bus_setup_intr(dev, sc->rl_irq[i], 1406 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1407 &sc->rl_intrhand[i]); 1408 if (error != 0) 1409 break; 1410 } 1411 } 1412 if (error) { 1413 device_printf(dev, "couldn't set up irq\n"); 1414 ether_ifdetach(ifp); 1415 } 1416 1417 fail: 1418 1419 if (error) 1420 re_detach(dev); 1421 1422 return (error); 1423 } 1424 1425 /* 1426 * Shutdown hardware and free up resources. This can be called any 1427 * time after the mutex has been initialized. It is called in both 1428 * the error case in attach and the normal detach case so it needs 1429 * to be careful about only freeing resources that have actually been 1430 * allocated. 1431 */ 1432 static int 1433 re_detach(device_t dev) 1434 { 1435 struct rl_softc *sc; 1436 struct ifnet *ifp; 1437 int i, rid; 1438 1439 sc = device_get_softc(dev); 1440 ifp = sc->rl_ifp; 1441 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1442 1443 /* These should only be active if attach succeeded */ 1444 if (device_is_attached(dev)) { 1445 #ifdef DEVICE_POLLING 1446 if (ifp->if_capenable & IFCAP_POLLING) 1447 ether_poll_deregister(ifp); 1448 #endif 1449 RL_LOCK(sc); 1450 #if 0 1451 sc->suspended = 1; 1452 #endif 1453 re_stop(sc); 1454 RL_UNLOCK(sc); 1455 callout_drain(&sc->rl_stat_callout); 1456 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1457 taskqueue_drain(taskqueue_fast, &sc->rl_txtask); 1458 /* 1459 * Force off the IFF_UP flag here, in case someone 1460 * still had a BPF descriptor attached to this 1461 * interface. If they do, ether_ifdetach() will cause 1462 * the BPF code to try and clear the promisc mode 1463 * flag, which will bubble down to re_ioctl(), 1464 * which will try to call re_init() again. This will 1465 * turn the NIC back on and restart the MII ticker, 1466 * which will panic the system when the kernel tries 1467 * to invoke the re_tick() function that isn't there 1468 * anymore. 1469 */ 1470 ifp->if_flags &= ~IFF_UP; 1471 ether_ifdetach(ifp); 1472 } 1473 if (sc->rl_miibus) 1474 device_delete_child(dev, sc->rl_miibus); 1475 bus_generic_detach(dev); 1476 1477 /* 1478 * The rest is resource deallocation, so we should already be 1479 * stopped here. 1480 */ 1481 1482 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1483 if (sc->rl_intrhand[i] != NULL) { 1484 bus_teardown_intr(dev, sc->rl_irq[i], 1485 sc->rl_intrhand[i]); 1486 sc->rl_intrhand[i] = NULL; 1487 } 1488 } 1489 if (ifp != NULL) 1490 if_free(ifp); 1491 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1492 if (sc->rl_irq[0] != NULL) { 1493 bus_release_resource(dev, SYS_RES_IRQ, 0, 1494 sc->rl_irq[0]); 1495 sc->rl_irq[0] = NULL; 1496 } 1497 } else { 1498 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1499 if (sc->rl_irq[i] != NULL) { 1500 bus_release_resource(dev, SYS_RES_IRQ, rid, 1501 sc->rl_irq[i]); 1502 sc->rl_irq[i] = NULL; 1503 } 1504 } 1505 pci_release_msi(dev); 1506 } 1507 if (sc->rl_res) 1508 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, 1509 sc->rl_res); 1510 1511 /* Unload and free the RX DMA ring memory and map */ 1512 1513 if (sc->rl_ldata.rl_rx_list_tag) { 1514 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1515 sc->rl_ldata.rl_rx_list_map); 1516 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1517 sc->rl_ldata.rl_rx_list, 1518 sc->rl_ldata.rl_rx_list_map); 1519 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1520 } 1521 1522 /* Unload and free the TX DMA ring memory and map */ 1523 1524 if (sc->rl_ldata.rl_tx_list_tag) { 1525 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1526 sc->rl_ldata.rl_tx_list_map); 1527 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1528 sc->rl_ldata.rl_tx_list, 1529 sc->rl_ldata.rl_tx_list_map); 1530 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1531 } 1532 1533 /* Destroy all the RX and TX buffer maps */ 1534 1535 if (sc->rl_ldata.rl_tx_mtag) { 1536 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1537 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1538 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1539 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1540 } 1541 if (sc->rl_ldata.rl_rx_mtag) { 1542 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) 1543 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1544 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1545 if (sc->rl_ldata.rl_rx_sparemap) 1546 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1547 sc->rl_ldata.rl_rx_sparemap); 1548 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1549 } 1550 1551 /* Unload and free the stats buffer and map */ 1552 1553 if (sc->rl_ldata.rl_stag) { 1554 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1555 sc->rl_ldata.rl_rx_list_map); 1556 bus_dmamem_free(sc->rl_ldata.rl_stag, 1557 sc->rl_ldata.rl_stats, 1558 sc->rl_ldata.rl_smap); 1559 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1560 } 1561 1562 if (sc->rl_parent_tag) 1563 bus_dma_tag_destroy(sc->rl_parent_tag); 1564 1565 mtx_destroy(&sc->rl_mtx); 1566 1567 return (0); 1568 } 1569 1570 static __inline void 1571 re_discard_rxbuf(struct rl_softc *sc, int idx) 1572 { 1573 struct rl_desc *desc; 1574 struct rl_rxdesc *rxd; 1575 uint32_t cmdstat; 1576 1577 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1578 desc = &sc->rl_ldata.rl_rx_list[idx]; 1579 desc->rl_vlanctl = 0; 1580 cmdstat = rxd->rx_size; 1581 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1582 cmdstat |= RL_RDESC_CMD_EOR; 1583 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1584 } 1585 1586 static int 1587 re_newbuf(struct rl_softc *sc, int idx) 1588 { 1589 struct mbuf *m; 1590 struct rl_rxdesc *rxd; 1591 bus_dma_segment_t segs[1]; 1592 bus_dmamap_t map; 1593 struct rl_desc *desc; 1594 uint32_t cmdstat; 1595 int error, nsegs; 1596 1597 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1598 if (m == NULL) 1599 return (ENOBUFS); 1600 1601 m->m_len = m->m_pkthdr.len = MCLBYTES; 1602 #ifdef RE_FIXUP_RX 1603 /* 1604 * This is part of an evil trick to deal with non-x86 platforms. 1605 * The RealTek chip requires RX buffers to be aligned on 64-bit 1606 * boundaries, but that will hose non-x86 machines. To get around 1607 * this, we leave some empty space at the start of each buffer 1608 * and for non-x86 hosts, we copy the buffer back six bytes 1609 * to achieve word alignment. This is slightly more efficient 1610 * than allocating a new buffer, copying the contents, and 1611 * discarding the old buffer. 1612 */ 1613 m_adj(m, RE_ETHER_ALIGN); 1614 #endif 1615 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1616 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1617 if (error != 0) { 1618 m_freem(m); 1619 return (ENOBUFS); 1620 } 1621 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1622 1623 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1624 if (rxd->rx_m != NULL) { 1625 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1626 BUS_DMASYNC_POSTREAD); 1627 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1628 } 1629 1630 rxd->rx_m = m; 1631 map = rxd->rx_dmamap; 1632 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1633 rxd->rx_size = segs[0].ds_len; 1634 sc->rl_ldata.rl_rx_sparemap = map; 1635 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1636 BUS_DMASYNC_PREREAD); 1637 1638 desc = &sc->rl_ldata.rl_rx_list[idx]; 1639 desc->rl_vlanctl = 0; 1640 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1641 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1642 cmdstat = segs[0].ds_len; 1643 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1644 cmdstat |= RL_RDESC_CMD_EOR; 1645 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1646 1647 return (0); 1648 } 1649 1650 #ifdef RE_FIXUP_RX 1651 static __inline void 1652 re_fixup_rx(struct mbuf *m) 1653 { 1654 int i; 1655 uint16_t *src, *dst; 1656 1657 src = mtod(m, uint16_t *); 1658 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1659 1660 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1661 *dst++ = *src++; 1662 1663 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1664 } 1665 #endif 1666 1667 static int 1668 re_tx_list_init(struct rl_softc *sc) 1669 { 1670 struct rl_desc *desc; 1671 int i; 1672 1673 RL_LOCK_ASSERT(sc); 1674 1675 bzero(sc->rl_ldata.rl_tx_list, 1676 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 1677 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1678 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 1679 /* Set EOR. */ 1680 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 1681 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 1682 1683 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1684 sc->rl_ldata.rl_tx_list_map, 1685 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1686 1687 sc->rl_ldata.rl_tx_prodidx = 0; 1688 sc->rl_ldata.rl_tx_considx = 0; 1689 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 1690 1691 return (0); 1692 } 1693 1694 static int 1695 re_rx_list_init(struct rl_softc *sc) 1696 { 1697 int error, i; 1698 1699 bzero(sc->rl_ldata.rl_rx_list, 1700 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 1701 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1702 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 1703 if ((error = re_newbuf(sc, i)) != 0) 1704 return (error); 1705 } 1706 1707 /* Flush the RX descriptors */ 1708 1709 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1710 sc->rl_ldata.rl_rx_list_map, 1711 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1712 1713 sc->rl_ldata.rl_rx_prodidx = 0; 1714 sc->rl_head = sc->rl_tail = NULL; 1715 1716 return (0); 1717 } 1718 1719 /* 1720 * RX handler for C+ and 8169. For the gigE chips, we support 1721 * the reception of jumbo frames that have been fragmented 1722 * across multiple 2K mbuf cluster buffers. 1723 */ 1724 static int 1725 re_rxeof(struct rl_softc *sc) 1726 { 1727 struct mbuf *m; 1728 struct ifnet *ifp; 1729 int i, total_len; 1730 struct rl_desc *cur_rx; 1731 u_int32_t rxstat, rxvlan; 1732 int maxpkt = 16; 1733 1734 RL_LOCK_ASSERT(sc); 1735 1736 ifp = sc->rl_ifp; 1737 1738 /* Invalidate the descriptor memory */ 1739 1740 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1741 sc->rl_ldata.rl_rx_list_map, 1742 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1743 1744 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 1745 i = RL_RX_DESC_NXT(sc, i)) { 1746 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1747 rxstat = le32toh(cur_rx->rl_cmdstat); 1748 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 1749 break; 1750 total_len = rxstat & sc->rl_rxlenmask; 1751 rxvlan = le32toh(cur_rx->rl_vlanctl); 1752 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 1753 1754 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1755 if (re_newbuf(sc, i) != 0) { 1756 /* 1757 * If this is part of a multi-fragment packet, 1758 * discard all the pieces. 1759 */ 1760 if (sc->rl_head != NULL) { 1761 m_freem(sc->rl_head); 1762 sc->rl_head = sc->rl_tail = NULL; 1763 } 1764 re_discard_rxbuf(sc, i); 1765 continue; 1766 } 1767 m->m_len = RE_RX_DESC_BUFLEN; 1768 if (sc->rl_head == NULL) 1769 sc->rl_head = sc->rl_tail = m; 1770 else { 1771 m->m_flags &= ~M_PKTHDR; 1772 sc->rl_tail->m_next = m; 1773 sc->rl_tail = m; 1774 } 1775 continue; 1776 } 1777 1778 /* 1779 * NOTE: for the 8139C+, the frame length field 1780 * is always 12 bits in size, but for the gigE chips, 1781 * it is 13 bits (since the max RX frame length is 16K). 1782 * Unfortunately, all 32 bits in the status word 1783 * were already used, so to make room for the extra 1784 * length bit, RealTek took out the 'frame alignment 1785 * error' bit and shifted the other status bits 1786 * over one slot. The OWN, EOR, FS and LS bits are 1787 * still in the same places. We have already extracted 1788 * the frame length and checked the OWN bit, so rather 1789 * than using an alternate bit mapping, we shift the 1790 * status bits one space to the right so we can evaluate 1791 * them using the 8169 status as though it was in the 1792 * same format as that of the 8139C+. 1793 */ 1794 if (sc->rl_type == RL_8169) 1795 rxstat >>= 1; 1796 1797 /* 1798 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 1799 * set, but if CRC is clear, it will still be a valid frame. 1800 */ 1801 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 && 1802 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) { 1803 ifp->if_ierrors++; 1804 /* 1805 * If this is part of a multi-fragment packet, 1806 * discard all the pieces. 1807 */ 1808 if (sc->rl_head != NULL) { 1809 m_freem(sc->rl_head); 1810 sc->rl_head = sc->rl_tail = NULL; 1811 } 1812 re_discard_rxbuf(sc, i); 1813 continue; 1814 } 1815 1816 /* 1817 * If allocating a replacement mbuf fails, 1818 * reload the current one. 1819 */ 1820 1821 if (re_newbuf(sc, i) != 0) { 1822 ifp->if_iqdrops++; 1823 if (sc->rl_head != NULL) { 1824 m_freem(sc->rl_head); 1825 sc->rl_head = sc->rl_tail = NULL; 1826 } 1827 re_discard_rxbuf(sc, i); 1828 continue; 1829 } 1830 1831 if (sc->rl_head != NULL) { 1832 m->m_len = total_len % RE_RX_DESC_BUFLEN; 1833 if (m->m_len == 0) 1834 m->m_len = RE_RX_DESC_BUFLEN; 1835 /* 1836 * Special case: if there's 4 bytes or less 1837 * in this buffer, the mbuf can be discarded: 1838 * the last 4 bytes is the CRC, which we don't 1839 * care about anyway. 1840 */ 1841 if (m->m_len <= ETHER_CRC_LEN) { 1842 sc->rl_tail->m_len -= 1843 (ETHER_CRC_LEN - m->m_len); 1844 m_freem(m); 1845 } else { 1846 m->m_len -= ETHER_CRC_LEN; 1847 m->m_flags &= ~M_PKTHDR; 1848 sc->rl_tail->m_next = m; 1849 } 1850 m = sc->rl_head; 1851 sc->rl_head = sc->rl_tail = NULL; 1852 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1853 } else 1854 m->m_pkthdr.len = m->m_len = 1855 (total_len - ETHER_CRC_LEN); 1856 1857 #ifdef RE_FIXUP_RX 1858 re_fixup_rx(m); 1859 #endif 1860 ifp->if_ipackets++; 1861 m->m_pkthdr.rcvif = ifp; 1862 1863 /* Do RX checksumming if enabled */ 1864 1865 if (ifp->if_capenable & IFCAP_RXCSUM) { 1866 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 1867 /* Check IP header checksum */ 1868 if (rxstat & RL_RDESC_STAT_PROTOID) 1869 m->m_pkthdr.csum_flags |= 1870 CSUM_IP_CHECKED; 1871 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1872 m->m_pkthdr.csum_flags |= 1873 CSUM_IP_VALID; 1874 1875 /* Check TCP/UDP checksum */ 1876 if ((RL_TCPPKT(rxstat) && 1877 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1878 (RL_UDPPKT(rxstat) && 1879 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1880 m->m_pkthdr.csum_flags |= 1881 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1882 m->m_pkthdr.csum_data = 0xffff; 1883 } 1884 } else { 1885 /* 1886 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP 1887 */ 1888 if ((rxstat & RL_RDESC_STAT_PROTOID) && 1889 (rxvlan & RL_RDESC_IPV4)) 1890 m->m_pkthdr.csum_flags |= 1891 CSUM_IP_CHECKED; 1892 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) && 1893 (rxvlan & RL_RDESC_IPV4)) 1894 m->m_pkthdr.csum_flags |= 1895 CSUM_IP_VALID; 1896 if (((rxstat & RL_RDESC_STAT_TCP) && 1897 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1898 ((rxstat & RL_RDESC_STAT_UDP) && 1899 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1900 m->m_pkthdr.csum_flags |= 1901 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1902 m->m_pkthdr.csum_data = 0xffff; 1903 } 1904 } 1905 } 1906 maxpkt--; 1907 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 1908 m->m_pkthdr.ether_vtag = 1909 bswap16((rxvlan & RL_RDESC_VLANCTL_DATA)); 1910 m->m_flags |= M_VLANTAG; 1911 } 1912 RL_UNLOCK(sc); 1913 (*ifp->if_input)(ifp, m); 1914 RL_LOCK(sc); 1915 } 1916 1917 /* Flush the RX DMA ring */ 1918 1919 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1920 sc->rl_ldata.rl_rx_list_map, 1921 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1922 1923 sc->rl_ldata.rl_rx_prodidx = i; 1924 1925 if (maxpkt) 1926 return(EAGAIN); 1927 1928 return(0); 1929 } 1930 1931 static void 1932 re_txeof(struct rl_softc *sc) 1933 { 1934 struct ifnet *ifp; 1935 struct rl_txdesc *txd; 1936 u_int32_t txstat; 1937 int cons; 1938 1939 cons = sc->rl_ldata.rl_tx_considx; 1940 if (cons == sc->rl_ldata.rl_tx_prodidx) 1941 return; 1942 1943 ifp = sc->rl_ifp; 1944 /* Invalidate the TX descriptor list */ 1945 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1946 sc->rl_ldata.rl_tx_list_map, 1947 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1948 1949 for (; cons != sc->rl_ldata.rl_tx_prodidx; 1950 cons = RL_TX_DESC_NXT(sc, cons)) { 1951 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 1952 if (txstat & RL_TDESC_STAT_OWN) 1953 break; 1954 /* 1955 * We only stash mbufs in the last descriptor 1956 * in a fragment chain, which also happens to 1957 * be the only place where the TX status bits 1958 * are valid. 1959 */ 1960 if (txstat & RL_TDESC_CMD_EOF) { 1961 txd = &sc->rl_ldata.rl_tx_desc[cons]; 1962 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 1963 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 1964 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 1965 txd->tx_dmamap); 1966 KASSERT(txd->tx_m != NULL, 1967 ("%s: freeing NULL mbufs!", __func__)); 1968 m_freem(txd->tx_m); 1969 txd->tx_m = NULL; 1970 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 1971 RL_TDESC_STAT_COLCNT)) 1972 ifp->if_collisions++; 1973 if (txstat & RL_TDESC_STAT_TXERRSUM) 1974 ifp->if_oerrors++; 1975 else 1976 ifp->if_opackets++; 1977 } 1978 sc->rl_ldata.rl_tx_free++; 1979 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1980 } 1981 sc->rl_ldata.rl_tx_considx = cons; 1982 1983 /* No changes made to the TX ring, so no flush needed */ 1984 1985 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 1986 /* 1987 * Some chips will ignore a second TX request issued 1988 * while an existing transmission is in progress. If 1989 * the transmitter goes idle but there are still 1990 * packets waiting to be sent, we need to restart the 1991 * channel here to flush them out. This only seems to 1992 * be required with the PCIe devices. 1993 */ 1994 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 1995 1996 #ifdef RE_TX_MODERATION 1997 /* 1998 * If not all descriptors have been reaped yet, reload 1999 * the timer so that we will eventually get another 2000 * interrupt that will cause us to re-enter this routine. 2001 * This is done in case the transmitter has gone idle. 2002 */ 2003 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2004 #endif 2005 } else 2006 sc->rl_watchdog_timer = 0; 2007 } 2008 2009 static void 2010 re_tick(void *xsc) 2011 { 2012 struct rl_softc *sc; 2013 struct mii_data *mii; 2014 struct ifnet *ifp; 2015 2016 sc = xsc; 2017 ifp = sc->rl_ifp; 2018 2019 RL_LOCK_ASSERT(sc); 2020 2021 re_watchdog(sc); 2022 2023 mii = device_get_softc(sc->rl_miibus); 2024 mii_tick(mii); 2025 if ((sc->rl_flags & RL_FLAG_LINK) != 0) { 2026 if (!(mii->mii_media_status & IFM_ACTIVE)) 2027 sc->rl_flags &= ~RL_FLAG_LINK; 2028 } else { 2029 if (mii->mii_media_status & IFM_ACTIVE && 2030 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2031 sc->rl_flags |= RL_FLAG_LINK; 2032 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2033 taskqueue_enqueue_fast(taskqueue_fast, 2034 &sc->rl_txtask); 2035 } 2036 } 2037 2038 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2039 } 2040 2041 #ifdef DEVICE_POLLING 2042 static void 2043 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2044 { 2045 struct rl_softc *sc = ifp->if_softc; 2046 2047 RL_LOCK(sc); 2048 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2049 re_poll_locked(ifp, cmd, count); 2050 RL_UNLOCK(sc); 2051 } 2052 2053 static void 2054 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2055 { 2056 struct rl_softc *sc = ifp->if_softc; 2057 2058 RL_LOCK_ASSERT(sc); 2059 2060 sc->rxcycles = count; 2061 re_rxeof(sc); 2062 re_txeof(sc); 2063 2064 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2065 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2066 2067 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2068 u_int16_t status; 2069 2070 status = CSR_READ_2(sc, RL_ISR); 2071 if (status == 0xffff) 2072 return; 2073 if (status) 2074 CSR_WRITE_2(sc, RL_ISR, status); 2075 2076 /* 2077 * XXX check behaviour on receiver stalls. 2078 */ 2079 2080 if (status & RL_ISR_SYSTEM_ERR) { 2081 re_reset(sc); 2082 re_init_locked(sc); 2083 } 2084 } 2085 } 2086 #endif /* DEVICE_POLLING */ 2087 2088 static int 2089 re_intr(void *arg) 2090 { 2091 struct rl_softc *sc; 2092 uint16_t status; 2093 2094 sc = arg; 2095 2096 status = CSR_READ_2(sc, RL_ISR); 2097 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2098 return (FILTER_STRAY); 2099 CSR_WRITE_2(sc, RL_IMR, 0); 2100 2101 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2102 2103 return (FILTER_HANDLED); 2104 } 2105 2106 static void 2107 re_int_task(void *arg, int npending) 2108 { 2109 struct rl_softc *sc; 2110 struct ifnet *ifp; 2111 u_int16_t status; 2112 int rval = 0; 2113 2114 sc = arg; 2115 ifp = sc->rl_ifp; 2116 2117 RL_LOCK(sc); 2118 2119 status = CSR_READ_2(sc, RL_ISR); 2120 CSR_WRITE_2(sc, RL_ISR, status); 2121 2122 if (sc->suspended || 2123 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2124 RL_UNLOCK(sc); 2125 return; 2126 } 2127 2128 #ifdef DEVICE_POLLING 2129 if (ifp->if_capenable & IFCAP_POLLING) { 2130 RL_UNLOCK(sc); 2131 return; 2132 } 2133 #endif 2134 2135 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2136 rval = re_rxeof(sc); 2137 2138 if (status & ( 2139 #ifdef RE_TX_MODERATION 2140 RL_ISR_TIMEOUT_EXPIRED| 2141 #else 2142 RL_ISR_TX_OK| 2143 #endif 2144 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2145 re_txeof(sc); 2146 2147 if (status & RL_ISR_SYSTEM_ERR) { 2148 re_reset(sc); 2149 re_init_locked(sc); 2150 } 2151 2152 if (status & RL_ISR_LINKCHG) { 2153 callout_stop(&sc->rl_stat_callout); 2154 re_tick(sc); 2155 } 2156 2157 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2158 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2159 2160 RL_UNLOCK(sc); 2161 2162 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2163 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2164 return; 2165 } 2166 2167 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2168 } 2169 2170 static int 2171 re_encap(struct rl_softc *sc, struct mbuf **m_head) 2172 { 2173 struct rl_txdesc *txd, *txd_last; 2174 bus_dma_segment_t segs[RL_NTXSEGS]; 2175 bus_dmamap_t map; 2176 struct mbuf *m_new; 2177 struct rl_desc *desc; 2178 int nsegs, prod; 2179 int i, error, ei, si; 2180 int padlen; 2181 uint32_t cmdstat, csum_flags, vlanctl; 2182 2183 RL_LOCK_ASSERT(sc); 2184 M_ASSERTPKTHDR((*m_head)); 2185 2186 /* 2187 * With some of the RealTek chips, using the checksum offload 2188 * support in conjunction with the autopadding feature results 2189 * in the transmission of corrupt frames. For example, if we 2190 * need to send a really small IP fragment that's less than 60 2191 * bytes in size, and IP header checksumming is enabled, the 2192 * resulting ethernet frame that appears on the wire will 2193 * have garbled payload. To work around this, if TX IP checksum 2194 * offload is enabled, we always manually pad short frames out 2195 * to the minimum ethernet frame size. 2196 */ 2197 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0 && 2198 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN && 2199 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) { 2200 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2201 if (M_WRITABLE(*m_head) == 0) { 2202 /* Get a writable copy. */ 2203 m_new = m_dup(*m_head, M_DONTWAIT); 2204 m_freem(*m_head); 2205 if (m_new == NULL) { 2206 *m_head = NULL; 2207 return (ENOBUFS); 2208 } 2209 *m_head = m_new; 2210 } 2211 if ((*m_head)->m_next != NULL || 2212 M_TRAILINGSPACE(*m_head) < padlen) { 2213 m_new = m_defrag(*m_head, M_DONTWAIT); 2214 if (m_new == NULL) { 2215 m_freem(*m_head); 2216 *m_head = NULL; 2217 return (ENOBUFS); 2218 } 2219 } else 2220 m_new = *m_head; 2221 2222 /* 2223 * Manually pad short frames, and zero the pad space 2224 * to avoid leaking data. 2225 */ 2226 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2227 m_new->m_pkthdr.len += padlen; 2228 m_new->m_len = m_new->m_pkthdr.len; 2229 *m_head = m_new; 2230 } 2231 2232 prod = sc->rl_ldata.rl_tx_prodidx; 2233 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2234 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2235 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2236 if (error == EFBIG) { 2237 m_new = m_collapse(*m_head, M_DONTWAIT, RL_NTXSEGS); 2238 if (m_new == NULL) { 2239 m_freem(*m_head); 2240 *m_head = NULL; 2241 return (ENOBUFS); 2242 } 2243 *m_head = m_new; 2244 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2245 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2246 if (error != 0) { 2247 m_freem(*m_head); 2248 *m_head = NULL; 2249 return (error); 2250 } 2251 } else if (error != 0) 2252 return (error); 2253 if (nsegs == 0) { 2254 m_freem(*m_head); 2255 *m_head = NULL; 2256 return (EIO); 2257 } 2258 2259 /* Check for number of available descriptors. */ 2260 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2261 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2262 return (ENOBUFS); 2263 } 2264 2265 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2266 BUS_DMASYNC_PREWRITE); 2267 2268 /* 2269 * Set up checksum offload. Note: checksum offload bits must 2270 * appear in all descriptors of a multi-descriptor transmit 2271 * attempt. This is according to testing done with an 8169 2272 * chip. This is a requirement. 2273 */ 2274 vlanctl = 0; 2275 csum_flags = 0; 2276 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) 2277 csum_flags = RL_TDESC_CMD_LGSEND | 2278 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2279 RL_TDESC_CMD_MSSVAL_SHIFT); 2280 else { 2281 /* 2282 * Unconditionally enable IP checksum if TCP or UDP 2283 * checksum is required. Otherwise, TCP/UDP checksum 2284 * does't make effects. 2285 */ 2286 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) { 2287 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2288 csum_flags |= RL_TDESC_CMD_IPCSUM; 2289 if (((*m_head)->m_pkthdr.csum_flags & 2290 CSUM_TCP) != 0) 2291 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2292 if (((*m_head)->m_pkthdr.csum_flags & 2293 CSUM_UDP) != 0) 2294 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2295 } else { 2296 vlanctl |= RL_TDESC_CMD_IPCSUMV2; 2297 if (((*m_head)->m_pkthdr.csum_flags & 2298 CSUM_TCP) != 0) 2299 vlanctl |= RL_TDESC_CMD_TCPCSUMV2; 2300 if (((*m_head)->m_pkthdr.csum_flags & 2301 CSUM_UDP) != 0) 2302 vlanctl |= RL_TDESC_CMD_UDPCSUMV2; 2303 } 2304 } 2305 } 2306 2307 /* 2308 * Set up hardware VLAN tagging. Note: vlan tag info must 2309 * appear in all descriptors of a multi-descriptor 2310 * transmission attempt. 2311 */ 2312 if ((*m_head)->m_flags & M_VLANTAG) 2313 vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) | 2314 RL_TDESC_VLANCTL_TAG; 2315 2316 si = prod; 2317 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2318 desc = &sc->rl_ldata.rl_tx_list[prod]; 2319 desc->rl_vlanctl = htole32(vlanctl); 2320 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2321 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2322 cmdstat = segs[i].ds_len; 2323 if (i != 0) 2324 cmdstat |= RL_TDESC_CMD_OWN; 2325 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2326 cmdstat |= RL_TDESC_CMD_EOR; 2327 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2328 sc->rl_ldata.rl_tx_free--; 2329 } 2330 /* Update producer index. */ 2331 sc->rl_ldata.rl_tx_prodidx = prod; 2332 2333 /* Set EOF on the last descriptor. */ 2334 ei = RL_TX_DESC_PRV(sc, prod); 2335 desc = &sc->rl_ldata.rl_tx_list[ei]; 2336 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2337 2338 desc = &sc->rl_ldata.rl_tx_list[si]; 2339 /* Set SOF and transfer ownership of packet to the chip. */ 2340 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2341 2342 /* 2343 * Insure that the map for this transmission 2344 * is placed at the array index of the last descriptor 2345 * in this chain. (Swap last and first dmamaps.) 2346 */ 2347 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2348 map = txd->tx_dmamap; 2349 txd->tx_dmamap = txd_last->tx_dmamap; 2350 txd_last->tx_dmamap = map; 2351 txd_last->tx_m = *m_head; 2352 2353 return (0); 2354 } 2355 2356 static void 2357 re_tx_task(void *arg, int npending) 2358 { 2359 struct ifnet *ifp; 2360 2361 ifp = arg; 2362 re_start(ifp); 2363 } 2364 2365 /* 2366 * Main transmit routine for C+ and gigE NICs. 2367 */ 2368 static void 2369 re_start(struct ifnet *ifp) 2370 { 2371 struct rl_softc *sc; 2372 struct mbuf *m_head; 2373 int queued; 2374 2375 sc = ifp->if_softc; 2376 2377 RL_LOCK(sc); 2378 2379 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2380 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) { 2381 RL_UNLOCK(sc); 2382 return; 2383 } 2384 2385 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2386 sc->rl_ldata.rl_tx_free > 1;) { 2387 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2388 if (m_head == NULL) 2389 break; 2390 2391 if (re_encap(sc, &m_head) != 0) { 2392 if (m_head == NULL) 2393 break; 2394 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2395 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2396 break; 2397 } 2398 2399 /* 2400 * If there's a BPF listener, bounce a copy of this frame 2401 * to him. 2402 */ 2403 ETHER_BPF_MTAP(ifp, m_head); 2404 2405 queued++; 2406 } 2407 2408 if (queued == 0) { 2409 #ifdef RE_TX_MODERATION 2410 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2411 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2412 #endif 2413 RL_UNLOCK(sc); 2414 return; 2415 } 2416 2417 /* Flush the TX descriptors */ 2418 2419 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2420 sc->rl_ldata.rl_tx_list_map, 2421 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2422 2423 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2424 2425 #ifdef RE_TX_MODERATION 2426 /* 2427 * Use the countdown timer for interrupt moderation. 2428 * 'TX done' interrupts are disabled. Instead, we reset the 2429 * countdown timer, which will begin counting until it hits 2430 * the value in the TIMERINT register, and then trigger an 2431 * interrupt. Each time we write to the TIMERCNT register, 2432 * the timer count is reset to 0. 2433 */ 2434 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2435 #endif 2436 2437 /* 2438 * Set a timeout in case the chip goes out to lunch. 2439 */ 2440 sc->rl_watchdog_timer = 5; 2441 2442 RL_UNLOCK(sc); 2443 } 2444 2445 static void 2446 re_init(void *xsc) 2447 { 2448 struct rl_softc *sc = xsc; 2449 2450 RL_LOCK(sc); 2451 re_init_locked(sc); 2452 RL_UNLOCK(sc); 2453 } 2454 2455 static void 2456 re_init_locked(struct rl_softc *sc) 2457 { 2458 struct ifnet *ifp = sc->rl_ifp; 2459 struct mii_data *mii; 2460 u_int32_t rxcfg = 0; 2461 uint16_t cfg; 2462 union { 2463 uint32_t align_dummy; 2464 u_char eaddr[ETHER_ADDR_LEN]; 2465 } eaddr; 2466 2467 RL_LOCK_ASSERT(sc); 2468 2469 mii = device_get_softc(sc->rl_miibus); 2470 2471 /* 2472 * Cancel pending I/O and free all RX/TX buffers. 2473 */ 2474 re_stop(sc); 2475 2476 /* 2477 * Enable C+ RX and TX mode, as well as VLAN stripping and 2478 * RX checksum offload. We must configure the C+ register 2479 * before all others. 2480 */ 2481 cfg = RL_CPLUSCMD_PCI_MRW; 2482 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2483 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 2484 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2485 cfg |= RL_CPLUSCMD_VLANSTRIP; 2486 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) { 2487 cfg |= RL_CPLUSCMD_MACSTAT_DIS; 2488 /* XXX magic. */ 2489 cfg |= 0x0001; 2490 } else 2491 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB; 2492 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg); 2493 /* 2494 * Disable TSO if interface MTU size is greater than MSS 2495 * allowed in controller. 2496 */ 2497 if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) { 2498 ifp->if_capenable &= ~IFCAP_TSO4; 2499 ifp->if_hwassist &= ~CSUM_TSO; 2500 } 2501 2502 /* 2503 * Init our MAC address. Even though the chipset 2504 * documentation doesn't mention it, we need to enter "Config 2505 * register write enable" mode to modify the ID registers. 2506 */ 2507 /* Copy MAC address on stack to align. */ 2508 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 2509 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2510 CSR_WRITE_4(sc, RL_IDR0, 2511 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 2512 CSR_WRITE_4(sc, RL_IDR4, 2513 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 2514 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2515 2516 /* 2517 * For C+ mode, initialize the RX descriptors and mbufs. 2518 */ 2519 re_rx_list_init(sc); 2520 re_tx_list_init(sc); 2521 2522 /* 2523 * Load the addresses of the RX and TX lists into the chip. 2524 */ 2525 2526 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2527 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2528 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2529 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2530 2531 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2532 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2533 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2534 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2535 2536 /* 2537 * Enable transmit and receive. 2538 */ 2539 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2540 2541 /* 2542 * Set the initial TX and RX configuration. 2543 */ 2544 if (sc->rl_testmode) { 2545 if (sc->rl_type == RL_8169) 2546 CSR_WRITE_4(sc, RL_TXCFG, 2547 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2548 else 2549 CSR_WRITE_4(sc, RL_TXCFG, 2550 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2551 } else 2552 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2553 2554 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2555 2556 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 2557 2558 /* Set the individual bit to receive frames for this host only. */ 2559 rxcfg = CSR_READ_4(sc, RL_RXCFG); 2560 rxcfg |= RL_RXCFG_RX_INDIV; 2561 2562 /* If we want promiscuous mode, set the allframes bit. */ 2563 if (ifp->if_flags & IFF_PROMISC) 2564 rxcfg |= RL_RXCFG_RX_ALLPHYS; 2565 else 2566 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 2567 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2568 2569 /* 2570 * Set capture broadcast bit to capture broadcast frames. 2571 */ 2572 if (ifp->if_flags & IFF_BROADCAST) 2573 rxcfg |= RL_RXCFG_RX_BROAD; 2574 else 2575 rxcfg &= ~RL_RXCFG_RX_BROAD; 2576 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2577 2578 /* 2579 * Program the multicast filter, if necessary. 2580 */ 2581 re_setmulti(sc); 2582 2583 #ifdef DEVICE_POLLING 2584 /* 2585 * Disable interrupts if we are polling. 2586 */ 2587 if (ifp->if_capenable & IFCAP_POLLING) 2588 CSR_WRITE_2(sc, RL_IMR, 0); 2589 else /* otherwise ... */ 2590 #endif 2591 2592 /* 2593 * Enable interrupts. 2594 */ 2595 if (sc->rl_testmode) 2596 CSR_WRITE_2(sc, RL_IMR, 0); 2597 else 2598 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2599 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 2600 2601 /* Set initial TX threshold */ 2602 sc->rl_txthresh = RL_TX_THRESH_INIT; 2603 2604 /* Start RX/TX process. */ 2605 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2606 #ifdef notdef 2607 /* Enable receiver and transmitter. */ 2608 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2609 #endif 2610 2611 #ifdef RE_TX_MODERATION 2612 /* 2613 * Initialize the timer interrupt register so that 2614 * a timer interrupt will be generated once the timer 2615 * reaches a certain number of ticks. The timer is 2616 * reloaded on each transmit. This gives us TX interrupt 2617 * moderation, which dramatically improves TX frame rate. 2618 */ 2619 if (sc->rl_type == RL_8169) 2620 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2621 else 2622 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2623 #endif 2624 2625 /* 2626 * For 8169 gigE NICs, set the max allowed RX packet 2627 * size so we can receive jumbo frames. 2628 */ 2629 if (sc->rl_type == RL_8169) 2630 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2631 2632 if (sc->rl_testmode) 2633 return; 2634 2635 mii_mediachg(mii); 2636 2637 CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD); 2638 2639 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2640 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2641 2642 sc->rl_flags &= ~RL_FLAG_LINK; 2643 sc->rl_watchdog_timer = 0; 2644 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2645 } 2646 2647 /* 2648 * Set media options. 2649 */ 2650 static int 2651 re_ifmedia_upd(struct ifnet *ifp) 2652 { 2653 struct rl_softc *sc; 2654 struct mii_data *mii; 2655 2656 sc = ifp->if_softc; 2657 mii = device_get_softc(sc->rl_miibus); 2658 RL_LOCK(sc); 2659 mii_mediachg(mii); 2660 RL_UNLOCK(sc); 2661 2662 return (0); 2663 } 2664 2665 /* 2666 * Report current media status. 2667 */ 2668 static void 2669 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2670 { 2671 struct rl_softc *sc; 2672 struct mii_data *mii; 2673 2674 sc = ifp->if_softc; 2675 mii = device_get_softc(sc->rl_miibus); 2676 2677 RL_LOCK(sc); 2678 mii_pollstat(mii); 2679 RL_UNLOCK(sc); 2680 ifmr->ifm_active = mii->mii_media_active; 2681 ifmr->ifm_status = mii->mii_media_status; 2682 } 2683 2684 static int 2685 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2686 { 2687 struct rl_softc *sc = ifp->if_softc; 2688 struct ifreq *ifr = (struct ifreq *) data; 2689 struct mii_data *mii; 2690 int error = 0; 2691 2692 switch (command) { 2693 case SIOCSIFMTU: 2694 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > RL_JUMBO_MTU) { 2695 error = EINVAL; 2696 break; 2697 } 2698 if ((sc->rl_flags & RL_FLAG_NOJUMBO) != 0 && 2699 ifr->ifr_mtu > RL_MAX_FRAMELEN) { 2700 error = EINVAL; 2701 break; 2702 } 2703 RL_LOCK(sc); 2704 if (ifp->if_mtu != ifr->ifr_mtu) 2705 ifp->if_mtu = ifr->ifr_mtu; 2706 if (ifp->if_mtu > RL_TSO_MTU && 2707 (ifp->if_capenable & IFCAP_TSO4) != 0) { 2708 ifp->if_capenable &= ~IFCAP_TSO4; 2709 ifp->if_hwassist &= ~CSUM_TSO; 2710 } 2711 RL_UNLOCK(sc); 2712 break; 2713 case SIOCSIFFLAGS: 2714 RL_LOCK(sc); 2715 if ((ifp->if_flags & IFF_UP) != 0) { 2716 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2717 if (((ifp->if_flags ^ sc->rl_if_flags) 2718 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2719 re_setmulti(sc); 2720 } else 2721 re_init_locked(sc); 2722 } else { 2723 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2724 re_stop(sc); 2725 } 2726 sc->rl_if_flags = ifp->if_flags; 2727 RL_UNLOCK(sc); 2728 break; 2729 case SIOCADDMULTI: 2730 case SIOCDELMULTI: 2731 RL_LOCK(sc); 2732 re_setmulti(sc); 2733 RL_UNLOCK(sc); 2734 break; 2735 case SIOCGIFMEDIA: 2736 case SIOCSIFMEDIA: 2737 mii = device_get_softc(sc->rl_miibus); 2738 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2739 break; 2740 case SIOCSIFCAP: 2741 { 2742 int mask, reinit; 2743 2744 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2745 reinit = 0; 2746 #ifdef DEVICE_POLLING 2747 if (mask & IFCAP_POLLING) { 2748 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2749 error = ether_poll_register(re_poll, ifp); 2750 if (error) 2751 return(error); 2752 RL_LOCK(sc); 2753 /* Disable interrupts */ 2754 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2755 ifp->if_capenable |= IFCAP_POLLING; 2756 RL_UNLOCK(sc); 2757 } else { 2758 error = ether_poll_deregister(ifp); 2759 /* Enable interrupts. */ 2760 RL_LOCK(sc); 2761 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2762 ifp->if_capenable &= ~IFCAP_POLLING; 2763 RL_UNLOCK(sc); 2764 } 2765 } 2766 #endif /* DEVICE_POLLING */ 2767 if (mask & IFCAP_HWCSUM) { 2768 ifp->if_capenable ^= IFCAP_HWCSUM; 2769 if (ifp->if_capenable & IFCAP_TXCSUM) 2770 ifp->if_hwassist |= RE_CSUM_FEATURES; 2771 else 2772 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 2773 reinit = 1; 2774 } 2775 if (mask & IFCAP_VLAN_HWTAGGING) { 2776 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2777 reinit = 1; 2778 } 2779 if (mask & IFCAP_TSO4) { 2780 ifp->if_capenable ^= IFCAP_TSO4; 2781 if ((IFCAP_TSO4 & ifp->if_capenable) && 2782 (IFCAP_TSO4 & ifp->if_capabilities)) 2783 ifp->if_hwassist |= CSUM_TSO; 2784 else 2785 ifp->if_hwassist &= ~CSUM_TSO; 2786 if (ifp->if_mtu > RL_TSO_MTU && 2787 (ifp->if_capenable & IFCAP_TSO4) != 0) { 2788 ifp->if_capenable &= ~IFCAP_TSO4; 2789 ifp->if_hwassist &= ~CSUM_TSO; 2790 } 2791 } 2792 if ((mask & IFCAP_WOL) != 0 && 2793 (ifp->if_capabilities & IFCAP_WOL) != 0) { 2794 if ((mask & IFCAP_WOL_UCAST) != 0) 2795 ifp->if_capenable ^= IFCAP_WOL_UCAST; 2796 if ((mask & IFCAP_WOL_MCAST) != 0) 2797 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2798 if ((mask & IFCAP_WOL_MAGIC) != 0) 2799 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2800 } 2801 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) 2802 re_init(sc); 2803 VLAN_CAPABILITIES(ifp); 2804 } 2805 break; 2806 default: 2807 error = ether_ioctl(ifp, command, data); 2808 break; 2809 } 2810 2811 return (error); 2812 } 2813 2814 static void 2815 re_watchdog(struct rl_softc *sc) 2816 { 2817 2818 RL_LOCK_ASSERT(sc); 2819 2820 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 2821 return; 2822 2823 device_printf(sc->rl_dev, "watchdog timeout\n"); 2824 sc->rl_ifp->if_oerrors++; 2825 2826 re_txeof(sc); 2827 re_rxeof(sc); 2828 re_init_locked(sc); 2829 } 2830 2831 /* 2832 * Stop the adapter and free any mbufs allocated to the 2833 * RX and TX lists. 2834 */ 2835 static void 2836 re_stop(struct rl_softc *sc) 2837 { 2838 int i; 2839 struct ifnet *ifp; 2840 struct rl_txdesc *txd; 2841 struct rl_rxdesc *rxd; 2842 2843 RL_LOCK_ASSERT(sc); 2844 2845 ifp = sc->rl_ifp; 2846 2847 sc->rl_watchdog_timer = 0; 2848 callout_stop(&sc->rl_stat_callout); 2849 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2850 2851 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2852 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2853 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 2854 2855 if (sc->rl_head != NULL) { 2856 m_freem(sc->rl_head); 2857 sc->rl_head = sc->rl_tail = NULL; 2858 } 2859 2860 /* Free the TX list buffers. */ 2861 2862 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 2863 txd = &sc->rl_ldata.rl_tx_desc[i]; 2864 if (txd->tx_m != NULL) { 2865 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2866 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2867 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2868 txd->tx_dmamap); 2869 m_freem(txd->tx_m); 2870 txd->tx_m = NULL; 2871 } 2872 } 2873 2874 /* Free the RX list buffers. */ 2875 2876 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2877 rxd = &sc->rl_ldata.rl_rx_desc[i]; 2878 if (rxd->rx_m != NULL) { 2879 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2880 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2881 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 2882 rxd->rx_dmamap); 2883 m_freem(rxd->rx_m); 2884 rxd->rx_m = NULL; 2885 } 2886 } 2887 } 2888 2889 /* 2890 * Device suspend routine. Stop the interface and save some PCI 2891 * settings in case the BIOS doesn't restore them properly on 2892 * resume. 2893 */ 2894 static int 2895 re_suspend(device_t dev) 2896 { 2897 struct rl_softc *sc; 2898 2899 sc = device_get_softc(dev); 2900 2901 RL_LOCK(sc); 2902 re_stop(sc); 2903 re_setwol(sc); 2904 sc->suspended = 1; 2905 RL_UNLOCK(sc); 2906 2907 return (0); 2908 } 2909 2910 /* 2911 * Device resume routine. Restore some PCI settings in case the BIOS 2912 * doesn't, re-enable busmastering, and restart the interface if 2913 * appropriate. 2914 */ 2915 static int 2916 re_resume(device_t dev) 2917 { 2918 struct rl_softc *sc; 2919 struct ifnet *ifp; 2920 2921 sc = device_get_softc(dev); 2922 2923 RL_LOCK(sc); 2924 2925 ifp = sc->rl_ifp; 2926 2927 /* reinitialize interface if necessary */ 2928 if (ifp->if_flags & IFF_UP) 2929 re_init_locked(sc); 2930 2931 /* 2932 * Clear WOL matching such that normal Rx filtering 2933 * wouldn't interfere with WOL patterns. 2934 */ 2935 re_clrwol(sc); 2936 sc->suspended = 0; 2937 RL_UNLOCK(sc); 2938 2939 return (0); 2940 } 2941 2942 /* 2943 * Stop all chip I/O so that the kernel's probe routines don't 2944 * get confused by errant DMAs when rebooting. 2945 */ 2946 static int 2947 re_shutdown(device_t dev) 2948 { 2949 struct rl_softc *sc; 2950 2951 sc = device_get_softc(dev); 2952 2953 RL_LOCK(sc); 2954 re_stop(sc); 2955 /* 2956 * Mark interface as down since otherwise we will panic if 2957 * interrupt comes in later on, which can happen in some 2958 * cases. 2959 */ 2960 sc->rl_ifp->if_flags &= ~IFF_UP; 2961 re_setwol(sc); 2962 RL_UNLOCK(sc); 2963 2964 return (0); 2965 } 2966 2967 static void 2968 re_setwol(struct rl_softc *sc) 2969 { 2970 struct ifnet *ifp; 2971 int pmc; 2972 uint16_t pmstat; 2973 uint8_t v; 2974 2975 RL_LOCK_ASSERT(sc); 2976 2977 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 2978 return; 2979 2980 ifp = sc->rl_ifp; 2981 /* Enable config register write. */ 2982 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 2983 2984 /* Enable PME. */ 2985 v = CSR_READ_1(sc, RL_CFG1); 2986 v &= ~RL_CFG1_PME; 2987 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2988 v |= RL_CFG1_PME; 2989 CSR_WRITE_1(sc, RL_CFG1, v); 2990 2991 v = CSR_READ_1(sc, RL_CFG3); 2992 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 2993 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2994 v |= RL_CFG3_WOL_MAGIC; 2995 CSR_WRITE_1(sc, RL_CFG3, v); 2996 2997 /* Config register write done. */ 2998 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2999 3000 v = CSR_READ_1(sc, RL_CFG5); 3001 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3002 v &= ~RL_CFG5_WOL_LANWAKE; 3003 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 3004 v |= RL_CFG5_WOL_UCAST; 3005 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 3006 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 3007 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3008 v |= RL_CFG5_WOL_LANWAKE; 3009 CSR_WRITE_1(sc, RL_CFG5, v); 3010 3011 /* 3012 * It seems that hardware resets its link speed to 100Mbps in 3013 * power down mode so switching to 100Mbps in driver is not 3014 * needed. 3015 */ 3016 3017 /* Request PME if WOL is requested. */ 3018 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 3019 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3020 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3021 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3022 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 3023 } 3024 3025 static void 3026 re_clrwol(struct rl_softc *sc) 3027 { 3028 int pmc; 3029 uint8_t v; 3030 3031 RL_LOCK_ASSERT(sc); 3032 3033 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3034 return; 3035 3036 /* Enable config register write. */ 3037 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3038 3039 v = CSR_READ_1(sc, RL_CFG3); 3040 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3041 CSR_WRITE_1(sc, RL_CFG3, v); 3042 3043 /* Config register write done. */ 3044 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3045 3046 v = CSR_READ_1(sc, RL_CFG5); 3047 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3048 v &= ~RL_CFG5_WOL_LANWAKE; 3049 CSR_WRITE_1(sc, RL_CFG5, v); 3050 } 3051