1 /*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44 /* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111 #ifdef HAVE_KERNEL_OPTION_HEADERS 112 #include "opt_device_polling.h" 113 #endif 114 115 #include <sys/param.h> 116 #include <sys/endian.h> 117 #include <sys/systm.h> 118 #include <sys/sockio.h> 119 #include <sys/mbuf.h> 120 #include <sys/malloc.h> 121 #include <sys/module.h> 122 #include <sys/kernel.h> 123 #include <sys/socket.h> 124 #include <sys/lock.h> 125 #include <sys/mutex.h> 126 #include <sys/taskqueue.h> 127 128 #include <net/if.h> 129 #include <net/if_arp.h> 130 #include <net/ethernet.h> 131 #include <net/if_dl.h> 132 #include <net/if_media.h> 133 #include <net/if_types.h> 134 #include <net/if_vlan_var.h> 135 136 #include <net/bpf.h> 137 138 #include <machine/bus.h> 139 #include <machine/resource.h> 140 #include <sys/bus.h> 141 #include <sys/rman.h> 142 143 #include <dev/mii/mii.h> 144 #include <dev/mii/miivar.h> 145 146 #include <dev/pci/pcireg.h> 147 #include <dev/pci/pcivar.h> 148 149 #include <pci/if_rlreg.h> 150 151 MODULE_DEPEND(re, pci, 1, 1, 1); 152 MODULE_DEPEND(re, ether, 1, 1, 1); 153 MODULE_DEPEND(re, miibus, 1, 1, 1); 154 155 /* "device miibus" required. See GENERIC if you get errors here. */ 156 #include "miibus_if.h" 157 158 /* Tunables. */ 159 static int msi_disable = 0; 160 TUNABLE_INT("hw.re.msi_disable", &msi_disable); 161 static int prefer_iomap = 0; 162 TUNABLE_INT("hw.re.prefer_iomap", &prefer_iomap); 163 164 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 165 166 /* 167 * Various supported device vendors/types and their names. 168 */ 169 static struct rl_type re_devs[] = { 170 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0, 171 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 172 { RT_VENDORID, RT_DEVICEID_8139, 0, 173 "RealTek 8139C+ 10/100BaseTX" }, 174 { RT_VENDORID, RT_DEVICEID_8101E, 0, 175 "RealTek 8101E/8102E/8102EL/8103E PCIe 10/100baseTX" }, 176 { RT_VENDORID, RT_DEVICEID_8168, 0, 177 "RealTek 8168/8168B/8168C/8168CP/8168D/8168DP/" 178 "8111B/8111C/8111CP/8111DP PCIe Gigabit Ethernet" }, 179 { RT_VENDORID, RT_DEVICEID_8169, 0, 180 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" }, 181 { RT_VENDORID, RT_DEVICEID_8169SC, 0, 182 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 183 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0, 184 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 185 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0, 186 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 187 { USR_VENDORID, USR_DEVICEID_997902, 0, 188 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 189 }; 190 191 static struct rl_hwrev re_hwrevs[] = { 192 { RL_HWREV_8139, RL_8139, "" }, 193 { RL_HWREV_8139A, RL_8139, "A" }, 194 { RL_HWREV_8139AG, RL_8139, "A-G" }, 195 { RL_HWREV_8139B, RL_8139, "B" }, 196 { RL_HWREV_8130, RL_8139, "8130" }, 197 { RL_HWREV_8139C, RL_8139, "C" }, 198 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 199 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 200 { RL_HWREV_8168_SPIN1, RL_8169, "8168"}, 201 { RL_HWREV_8169, RL_8169, "8169"}, 202 { RL_HWREV_8169S, RL_8169, "8169S"}, 203 { RL_HWREV_8110S, RL_8169, "8110S"}, 204 { RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB"}, 205 { RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC"}, 206 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL"}, 207 { RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC"}, 208 { RL_HWREV_8100, RL_8139, "8100"}, 209 { RL_HWREV_8101, RL_8139, "8101"}, 210 { RL_HWREV_8100E, RL_8169, "8100E"}, 211 { RL_HWREV_8101E, RL_8169, "8101E"}, 212 { RL_HWREV_8102E, RL_8169, "8102E"}, 213 { RL_HWREV_8102EL, RL_8169, "8102EL"}, 214 { RL_HWREV_8102EL_SPIN1, RL_8169, "8102EL"}, 215 { RL_HWREV_8103E, RL_8169, "8103E"}, 216 { RL_HWREV_8168_SPIN2, RL_8169, "8168"}, 217 { RL_HWREV_8168_SPIN3, RL_8169, "8168"}, 218 { RL_HWREV_8168C, RL_8169, "8168C/8111C"}, 219 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C"}, 220 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP"}, 221 { RL_HWREV_8168D, RL_8169, "8168D/8111D"}, 222 { RL_HWREV_8168DP, RL_8169, "8168DP/8111DP"}, 223 { 0, 0, NULL } 224 }; 225 226 static int re_probe (device_t); 227 static int re_attach (device_t); 228 static int re_detach (device_t); 229 230 static int re_encap (struct rl_softc *, struct mbuf **); 231 232 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 233 static int re_allocmem (device_t, struct rl_softc *); 234 static __inline void re_discard_rxbuf 235 (struct rl_softc *, int); 236 static int re_newbuf (struct rl_softc *, int); 237 static int re_rx_list_init (struct rl_softc *); 238 static int re_tx_list_init (struct rl_softc *); 239 #ifdef RE_FIXUP_RX 240 static __inline void re_fixup_rx 241 (struct mbuf *); 242 #endif 243 static int re_rxeof (struct rl_softc *, int *); 244 static void re_txeof (struct rl_softc *); 245 #ifdef DEVICE_POLLING 246 static int re_poll (struct ifnet *, enum poll_cmd, int); 247 static int re_poll_locked (struct ifnet *, enum poll_cmd, int); 248 #endif 249 static int re_intr (void *); 250 static void re_tick (void *); 251 static void re_tx_task (void *, int); 252 static void re_int_task (void *, int); 253 static void re_start (struct ifnet *); 254 static int re_ioctl (struct ifnet *, u_long, caddr_t); 255 static void re_init (void *); 256 static void re_init_locked (struct rl_softc *); 257 static void re_stop (struct rl_softc *); 258 static void re_watchdog (struct rl_softc *); 259 static int re_suspend (device_t); 260 static int re_resume (device_t); 261 static int re_shutdown (device_t); 262 static int re_ifmedia_upd (struct ifnet *); 263 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 264 265 static void re_eeprom_putbyte (struct rl_softc *, int); 266 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 267 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 268 static int re_gmii_readreg (device_t, int, int); 269 static int re_gmii_writereg (device_t, int, int, int); 270 271 static int re_miibus_readreg (device_t, int, int); 272 static int re_miibus_writereg (device_t, int, int, int); 273 static void re_miibus_statchg (device_t); 274 275 static void re_set_rxmode (struct rl_softc *); 276 static void re_reset (struct rl_softc *); 277 static void re_setwol (struct rl_softc *); 278 static void re_clrwol (struct rl_softc *); 279 280 #ifdef RE_DIAG 281 static int re_diag (struct rl_softc *); 282 #endif 283 284 static device_method_t re_methods[] = { 285 /* Device interface */ 286 DEVMETHOD(device_probe, re_probe), 287 DEVMETHOD(device_attach, re_attach), 288 DEVMETHOD(device_detach, re_detach), 289 DEVMETHOD(device_suspend, re_suspend), 290 DEVMETHOD(device_resume, re_resume), 291 DEVMETHOD(device_shutdown, re_shutdown), 292 293 /* bus interface */ 294 DEVMETHOD(bus_print_child, bus_generic_print_child), 295 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 296 297 /* MII interface */ 298 DEVMETHOD(miibus_readreg, re_miibus_readreg), 299 DEVMETHOD(miibus_writereg, re_miibus_writereg), 300 DEVMETHOD(miibus_statchg, re_miibus_statchg), 301 302 { 0, 0 } 303 }; 304 305 static driver_t re_driver = { 306 "re", 307 re_methods, 308 sizeof(struct rl_softc) 309 }; 310 311 static devclass_t re_devclass; 312 313 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 314 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 315 316 #define EE_SET(x) \ 317 CSR_WRITE_1(sc, RL_EECMD, \ 318 CSR_READ_1(sc, RL_EECMD) | x) 319 320 #define EE_CLR(x) \ 321 CSR_WRITE_1(sc, RL_EECMD, \ 322 CSR_READ_1(sc, RL_EECMD) & ~x) 323 324 /* 325 * Send a read command and address to the EEPROM, check for ACK. 326 */ 327 static void 328 re_eeprom_putbyte(struct rl_softc *sc, int addr) 329 { 330 int d, i; 331 332 d = addr | (RL_9346_READ << sc->rl_eewidth); 333 334 /* 335 * Feed in each bit and strobe the clock. 336 */ 337 338 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 339 if (d & i) { 340 EE_SET(RL_EE_DATAIN); 341 } else { 342 EE_CLR(RL_EE_DATAIN); 343 } 344 DELAY(100); 345 EE_SET(RL_EE_CLK); 346 DELAY(150); 347 EE_CLR(RL_EE_CLK); 348 DELAY(100); 349 } 350 } 351 352 /* 353 * Read a word of data stored in the EEPROM at address 'addr.' 354 */ 355 static void 356 re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest) 357 { 358 int i; 359 u_int16_t word = 0; 360 361 /* 362 * Send address of word we want to read. 363 */ 364 re_eeprom_putbyte(sc, addr); 365 366 /* 367 * Start reading bits from EEPROM. 368 */ 369 for (i = 0x8000; i; i >>= 1) { 370 EE_SET(RL_EE_CLK); 371 DELAY(100); 372 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 373 word |= i; 374 EE_CLR(RL_EE_CLK); 375 DELAY(100); 376 } 377 378 *dest = word; 379 } 380 381 /* 382 * Read a sequence of words from the EEPROM. 383 */ 384 static void 385 re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt) 386 { 387 int i; 388 u_int16_t word = 0, *ptr; 389 390 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 391 392 DELAY(100); 393 394 for (i = 0; i < cnt; i++) { 395 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 396 re_eeprom_getword(sc, off + i, &word); 397 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 398 ptr = (u_int16_t *)(dest + (i * 2)); 399 *ptr = word; 400 } 401 402 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 403 } 404 405 static int 406 re_gmii_readreg(device_t dev, int phy, int reg) 407 { 408 struct rl_softc *sc; 409 u_int32_t rval; 410 int i; 411 412 if (phy != 1) 413 return (0); 414 415 sc = device_get_softc(dev); 416 417 /* Let the rgephy driver read the GMEDIASTAT register */ 418 419 if (reg == RL_GMEDIASTAT) { 420 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 421 return (rval); 422 } 423 424 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 425 DELAY(1000); 426 427 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 428 rval = CSR_READ_4(sc, RL_PHYAR); 429 if (rval & RL_PHYAR_BUSY) 430 break; 431 DELAY(100); 432 } 433 434 if (i == RL_PHY_TIMEOUT) { 435 device_printf(sc->rl_dev, "PHY read failed\n"); 436 return (0); 437 } 438 439 return (rval & RL_PHYAR_PHYDATA); 440 } 441 442 static int 443 re_gmii_writereg(device_t dev, int phy, int reg, int data) 444 { 445 struct rl_softc *sc; 446 u_int32_t rval; 447 int i; 448 449 sc = device_get_softc(dev); 450 451 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 452 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 453 DELAY(1000); 454 455 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 456 rval = CSR_READ_4(sc, RL_PHYAR); 457 if (!(rval & RL_PHYAR_BUSY)) 458 break; 459 DELAY(100); 460 } 461 462 if (i == RL_PHY_TIMEOUT) { 463 device_printf(sc->rl_dev, "PHY write failed\n"); 464 return (0); 465 } 466 467 return (0); 468 } 469 470 static int 471 re_miibus_readreg(device_t dev, int phy, int reg) 472 { 473 struct rl_softc *sc; 474 u_int16_t rval = 0; 475 u_int16_t re8139_reg = 0; 476 477 sc = device_get_softc(dev); 478 479 if (sc->rl_type == RL_8169) { 480 rval = re_gmii_readreg(dev, phy, reg); 481 return (rval); 482 } 483 484 /* Pretend the internal PHY is only at address 0 */ 485 if (phy) { 486 return (0); 487 } 488 switch (reg) { 489 case MII_BMCR: 490 re8139_reg = RL_BMCR; 491 break; 492 case MII_BMSR: 493 re8139_reg = RL_BMSR; 494 break; 495 case MII_ANAR: 496 re8139_reg = RL_ANAR; 497 break; 498 case MII_ANER: 499 re8139_reg = RL_ANER; 500 break; 501 case MII_ANLPAR: 502 re8139_reg = RL_LPAR; 503 break; 504 case MII_PHYIDR1: 505 case MII_PHYIDR2: 506 return (0); 507 /* 508 * Allow the rlphy driver to read the media status 509 * register. If we have a link partner which does not 510 * support NWAY, this is the register which will tell 511 * us the results of parallel detection. 512 */ 513 case RL_MEDIASTAT: 514 rval = CSR_READ_1(sc, RL_MEDIASTAT); 515 return (rval); 516 default: 517 device_printf(sc->rl_dev, "bad phy register\n"); 518 return (0); 519 } 520 rval = CSR_READ_2(sc, re8139_reg); 521 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 522 /* 8139C+ has different bit layout. */ 523 rval &= ~(BMCR_LOOP | BMCR_ISO); 524 } 525 return (rval); 526 } 527 528 static int 529 re_miibus_writereg(device_t dev, int phy, int reg, int data) 530 { 531 struct rl_softc *sc; 532 u_int16_t re8139_reg = 0; 533 int rval = 0; 534 535 sc = device_get_softc(dev); 536 537 if (sc->rl_type == RL_8169) { 538 rval = re_gmii_writereg(dev, phy, reg, data); 539 return (rval); 540 } 541 542 /* Pretend the internal PHY is only at address 0 */ 543 if (phy) 544 return (0); 545 546 switch (reg) { 547 case MII_BMCR: 548 re8139_reg = RL_BMCR; 549 if (sc->rl_type == RL_8139CPLUS) { 550 /* 8139C+ has different bit layout. */ 551 data &= ~(BMCR_LOOP | BMCR_ISO); 552 } 553 break; 554 case MII_BMSR: 555 re8139_reg = RL_BMSR; 556 break; 557 case MII_ANAR: 558 re8139_reg = RL_ANAR; 559 break; 560 case MII_ANER: 561 re8139_reg = RL_ANER; 562 break; 563 case MII_ANLPAR: 564 re8139_reg = RL_LPAR; 565 break; 566 case MII_PHYIDR1: 567 case MII_PHYIDR2: 568 return (0); 569 break; 570 default: 571 device_printf(sc->rl_dev, "bad phy register\n"); 572 return (0); 573 } 574 CSR_WRITE_2(sc, re8139_reg, data); 575 return (0); 576 } 577 578 static void 579 re_miibus_statchg(device_t dev) 580 { 581 struct rl_softc *sc; 582 struct ifnet *ifp; 583 struct mii_data *mii; 584 585 sc = device_get_softc(dev); 586 mii = device_get_softc(sc->rl_miibus); 587 ifp = sc->rl_ifp; 588 if (mii == NULL || ifp == NULL || 589 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 590 return; 591 592 sc->rl_flags &= ~RL_FLAG_LINK; 593 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 594 (IFM_ACTIVE | IFM_AVALID)) { 595 switch (IFM_SUBTYPE(mii->mii_media_active)) { 596 case IFM_10_T: 597 case IFM_100_TX: 598 sc->rl_flags |= RL_FLAG_LINK; 599 break; 600 case IFM_1000_T: 601 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0) 602 break; 603 sc->rl_flags |= RL_FLAG_LINK; 604 break; 605 default: 606 break; 607 } 608 } 609 /* 610 * RealTek controllers does not provide any interface to 611 * Tx/Rx MACs for resolved speed, duplex and flow-control 612 * parameters. 613 */ 614 } 615 616 /* 617 * Set the RX configuration and 64-bit multicast hash filter. 618 */ 619 static void 620 re_set_rxmode(struct rl_softc *sc) 621 { 622 struct ifnet *ifp; 623 struct ifmultiaddr *ifma; 624 uint32_t hashes[2] = { 0, 0 }; 625 uint32_t h, rxfilt; 626 627 RL_LOCK_ASSERT(sc); 628 629 ifp = sc->rl_ifp; 630 631 rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD; 632 633 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 634 if (ifp->if_flags & IFF_PROMISC) 635 rxfilt |= RL_RXCFG_RX_ALLPHYS; 636 /* 637 * Unlike other hardwares, we have to explicitly set 638 * RL_RXCFG_RX_MULTI to receive multicast frames in 639 * promiscuous mode. 640 */ 641 rxfilt |= RL_RXCFG_RX_MULTI; 642 hashes[0] = hashes[1] = 0xffffffff; 643 goto done; 644 } 645 646 if_maddr_rlock(ifp); 647 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 648 if (ifma->ifma_addr->sa_family != AF_LINK) 649 continue; 650 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 651 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 652 if (h < 32) 653 hashes[0] |= (1 << h); 654 else 655 hashes[1] |= (1 << (h - 32)); 656 } 657 if_maddr_runlock(ifp); 658 659 if (hashes[0] != 0 || hashes[1] != 0) { 660 /* 661 * For some unfathomable reason, RealTek decided to 662 * reverse the order of the multicast hash registers 663 * in the PCI Express parts. This means we have to 664 * write the hash pattern in reverse order for those 665 * devices. 666 */ 667 if ((sc->rl_flags & RL_FLAG_PCIE) != 0) { 668 h = bswap32(hashes[0]); 669 hashes[0] = bswap32(hashes[1]); 670 hashes[1] = h; 671 } 672 rxfilt |= RL_RXCFG_RX_MULTI; 673 } 674 675 done: 676 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 677 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 678 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 679 } 680 681 static void 682 re_reset(struct rl_softc *sc) 683 { 684 int i; 685 686 RL_LOCK_ASSERT(sc); 687 688 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 689 690 for (i = 0; i < RL_TIMEOUT; i++) { 691 DELAY(10); 692 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 693 break; 694 } 695 if (i == RL_TIMEOUT) 696 device_printf(sc->rl_dev, "reset never completed!\n"); 697 698 if ((sc->rl_flags & RL_FLAG_MACRESET) != 0) 699 CSR_WRITE_1(sc, 0x82, 1); 700 if (sc->rl_hwrev == RL_HWREV_8169S) 701 re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0); 702 } 703 704 #ifdef RE_DIAG 705 706 /* 707 * The following routine is designed to test for a defect on some 708 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 709 * lines connected to the bus, however for a 32-bit only card, they 710 * should be pulled high. The result of this defect is that the 711 * NIC will not work right if you plug it into a 64-bit slot: DMA 712 * operations will be done with 64-bit transfers, which will fail 713 * because the 64-bit data lines aren't connected. 714 * 715 * There's no way to work around this (short of talking a soldering 716 * iron to the board), however we can detect it. The method we use 717 * here is to put the NIC into digital loopback mode, set the receiver 718 * to promiscuous mode, and then try to send a frame. We then compare 719 * the frame data we sent to what was received. If the data matches, 720 * then the NIC is working correctly, otherwise we know the user has 721 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 722 * slot. In the latter case, there's no way the NIC can work correctly, 723 * so we print out a message on the console and abort the device attach. 724 */ 725 726 static int 727 re_diag(struct rl_softc *sc) 728 { 729 struct ifnet *ifp = sc->rl_ifp; 730 struct mbuf *m0; 731 struct ether_header *eh; 732 struct rl_desc *cur_rx; 733 u_int16_t status; 734 u_int32_t rxstat; 735 int total_len, i, error = 0, phyaddr; 736 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 737 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 738 739 /* Allocate a single mbuf */ 740 MGETHDR(m0, M_DONTWAIT, MT_DATA); 741 if (m0 == NULL) 742 return (ENOBUFS); 743 744 RL_LOCK(sc); 745 746 /* 747 * Initialize the NIC in test mode. This sets the chip up 748 * so that it can send and receive frames, but performs the 749 * following special functions: 750 * - Puts receiver in promiscuous mode 751 * - Enables digital loopback mode 752 * - Leaves interrupts turned off 753 */ 754 755 ifp->if_flags |= IFF_PROMISC; 756 sc->rl_testmode = 1; 757 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 758 re_init_locked(sc); 759 sc->rl_flags |= RL_FLAG_LINK; 760 if (sc->rl_type == RL_8169) 761 phyaddr = 1; 762 else 763 phyaddr = 0; 764 765 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 766 for (i = 0; i < RL_TIMEOUT; i++) { 767 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 768 if (!(status & BMCR_RESET)) 769 break; 770 } 771 772 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 773 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 774 775 DELAY(100000); 776 777 /* Put some data in the mbuf */ 778 779 eh = mtod(m0, struct ether_header *); 780 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 781 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 782 eh->ether_type = htons(ETHERTYPE_IP); 783 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 784 785 /* 786 * Queue the packet, start transmission. 787 * Note: IF_HANDOFF() ultimately calls re_start() for us. 788 */ 789 790 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 791 RL_UNLOCK(sc); 792 /* XXX: re_diag must not be called when in ALTQ mode */ 793 IF_HANDOFF(&ifp->if_snd, m0, ifp); 794 RL_LOCK(sc); 795 m0 = NULL; 796 797 /* Wait for it to propagate through the chip */ 798 799 DELAY(100000); 800 for (i = 0; i < RL_TIMEOUT; i++) { 801 status = CSR_READ_2(sc, RL_ISR); 802 CSR_WRITE_2(sc, RL_ISR, status); 803 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 804 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 805 break; 806 DELAY(10); 807 } 808 809 if (i == RL_TIMEOUT) { 810 device_printf(sc->rl_dev, 811 "diagnostic failed, failed to receive packet in" 812 " loopback mode\n"); 813 error = EIO; 814 goto done; 815 } 816 817 /* 818 * The packet should have been dumped into the first 819 * entry in the RX DMA ring. Grab it from there. 820 */ 821 822 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 823 sc->rl_ldata.rl_rx_list_map, 824 BUS_DMASYNC_POSTREAD); 825 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 826 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 827 BUS_DMASYNC_POSTREAD); 828 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 829 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 830 831 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 832 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 833 eh = mtod(m0, struct ether_header *); 834 835 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 836 total_len = RL_RXBYTES(cur_rx); 837 rxstat = le32toh(cur_rx->rl_cmdstat); 838 839 if (total_len != ETHER_MIN_LEN) { 840 device_printf(sc->rl_dev, 841 "diagnostic failed, received short packet\n"); 842 error = EIO; 843 goto done; 844 } 845 846 /* Test that the received packet data matches what we sent. */ 847 848 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 849 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 850 ntohs(eh->ether_type) != ETHERTYPE_IP) { 851 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 852 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 853 dst, ":", src, ":", ETHERTYPE_IP); 854 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 855 eh->ether_dhost, ":", eh->ether_shost, ":", 856 ntohs(eh->ether_type)); 857 device_printf(sc->rl_dev, "You may have a defective 32-bit " 858 "NIC plugged into a 64-bit PCI slot.\n"); 859 device_printf(sc->rl_dev, "Please re-install the NIC in a " 860 "32-bit slot for proper operation.\n"); 861 device_printf(sc->rl_dev, "Read the re(4) man page for more " 862 "details.\n"); 863 error = EIO; 864 } 865 866 done: 867 /* Turn interface off, release resources */ 868 869 sc->rl_testmode = 0; 870 sc->rl_flags &= ~RL_FLAG_LINK; 871 ifp->if_flags &= ~IFF_PROMISC; 872 re_stop(sc); 873 if (m0 != NULL) 874 m_freem(m0); 875 876 RL_UNLOCK(sc); 877 878 return (error); 879 } 880 881 #endif 882 883 /* 884 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 885 * IDs against our list and return a device name if we find a match. 886 */ 887 static int 888 re_probe(device_t dev) 889 { 890 struct rl_type *t; 891 uint16_t devid, vendor; 892 uint16_t revid, sdevid; 893 int i; 894 895 vendor = pci_get_vendor(dev); 896 devid = pci_get_device(dev); 897 revid = pci_get_revid(dev); 898 sdevid = pci_get_subdevice(dev); 899 900 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 901 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 902 /* 903 * Only attach to rev. 3 of the Linksys EG1032 adapter. 904 * Rev. 2 is supported by sk(4). 905 */ 906 return (ENXIO); 907 } 908 } 909 910 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 911 if (revid != 0x20) { 912 /* 8139, let rl(4) take care of this device. */ 913 return (ENXIO); 914 } 915 } 916 917 t = re_devs; 918 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) { 919 if (vendor == t->rl_vid && devid == t->rl_did) { 920 device_set_desc(dev, t->rl_name); 921 return (BUS_PROBE_DEFAULT); 922 } 923 } 924 925 return (ENXIO); 926 } 927 928 /* 929 * Map a single buffer address. 930 */ 931 932 static void 933 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 934 { 935 bus_addr_t *addr; 936 937 if (error) 938 return; 939 940 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 941 addr = arg; 942 *addr = segs->ds_addr; 943 } 944 945 static int 946 re_allocmem(device_t dev, struct rl_softc *sc) 947 { 948 bus_size_t rx_list_size, tx_list_size; 949 int error; 950 int i; 951 952 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 953 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 954 955 /* 956 * Allocate the parent bus DMA tag appropriate for PCI. 957 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD 958 * register should be set. However some RealTek chips are known 959 * to be buggy on DAC handling, therefore disable DAC by limiting 960 * DMA address space to 32bit. PCIe variants of RealTek chips 961 * may not have the limitation but I took safer path. 962 */ 963 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 964 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 965 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 966 NULL, NULL, &sc->rl_parent_tag); 967 if (error) { 968 device_printf(dev, "could not allocate parent DMA tag\n"); 969 return (error); 970 } 971 972 /* 973 * Allocate map for TX mbufs. 974 */ 975 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 976 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 977 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 978 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 979 if (error) { 980 device_printf(dev, "could not allocate TX DMA tag\n"); 981 return (error); 982 } 983 984 /* 985 * Allocate map for RX mbufs. 986 */ 987 988 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 989 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 990 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 991 if (error) { 992 device_printf(dev, "could not allocate RX DMA tag\n"); 993 return (error); 994 } 995 996 /* 997 * Allocate map for TX descriptor list. 998 */ 999 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1000 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1001 NULL, tx_list_size, 1, tx_list_size, 0, 1002 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1003 if (error) { 1004 device_printf(dev, "could not allocate TX DMA ring tag\n"); 1005 return (error); 1006 } 1007 1008 /* Allocate DMA'able memory for the TX ring */ 1009 1010 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1011 (void **)&sc->rl_ldata.rl_tx_list, 1012 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1013 &sc->rl_ldata.rl_tx_list_map); 1014 if (error) { 1015 device_printf(dev, "could not allocate TX DMA ring\n"); 1016 return (error); 1017 } 1018 1019 /* Load the map for the TX ring. */ 1020 1021 sc->rl_ldata.rl_tx_list_addr = 0; 1022 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1023 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1024 tx_list_size, re_dma_map_addr, 1025 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1026 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 1027 device_printf(dev, "could not load TX DMA ring\n"); 1028 return (ENOMEM); 1029 } 1030 1031 /* Create DMA maps for TX buffers */ 1032 1033 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1034 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1035 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1036 if (error) { 1037 device_printf(dev, "could not create DMA map for TX\n"); 1038 return (error); 1039 } 1040 } 1041 1042 /* 1043 * Allocate map for RX descriptor list. 1044 */ 1045 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1046 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1047 NULL, rx_list_size, 1, rx_list_size, 0, 1048 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1049 if (error) { 1050 device_printf(dev, "could not create RX DMA ring tag\n"); 1051 return (error); 1052 } 1053 1054 /* Allocate DMA'able memory for the RX ring */ 1055 1056 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1057 (void **)&sc->rl_ldata.rl_rx_list, 1058 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1059 &sc->rl_ldata.rl_rx_list_map); 1060 if (error) { 1061 device_printf(dev, "could not allocate RX DMA ring\n"); 1062 return (error); 1063 } 1064 1065 /* Load the map for the RX ring. */ 1066 1067 sc->rl_ldata.rl_rx_list_addr = 0; 1068 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1069 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1070 rx_list_size, re_dma_map_addr, 1071 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1072 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1073 device_printf(dev, "could not load RX DMA ring\n"); 1074 return (ENOMEM); 1075 } 1076 1077 /* Create DMA maps for RX buffers */ 1078 1079 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1080 &sc->rl_ldata.rl_rx_sparemap); 1081 if (error) { 1082 device_printf(dev, "could not create spare DMA map for RX\n"); 1083 return (error); 1084 } 1085 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1086 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1087 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1088 if (error) { 1089 device_printf(dev, "could not create DMA map for RX\n"); 1090 return (error); 1091 } 1092 } 1093 1094 return (0); 1095 } 1096 1097 /* 1098 * Attach the interface. Allocate softc structures, do ifmedia 1099 * setup and ethernet/BPF attach. 1100 */ 1101 static int 1102 re_attach(device_t dev) 1103 { 1104 u_char eaddr[ETHER_ADDR_LEN]; 1105 u_int16_t as[ETHER_ADDR_LEN / 2]; 1106 struct rl_softc *sc; 1107 struct ifnet *ifp; 1108 struct rl_hwrev *hw_rev; 1109 int hwrev; 1110 u_int16_t devid, re_did = 0; 1111 int error = 0, rid, i; 1112 int msic, reg; 1113 uint8_t cfg; 1114 1115 sc = device_get_softc(dev); 1116 sc->rl_dev = dev; 1117 1118 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1119 MTX_DEF); 1120 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1121 1122 /* 1123 * Map control/status registers. 1124 */ 1125 pci_enable_busmaster(dev); 1126 1127 devid = pci_get_device(dev); 1128 /* 1129 * Prefer memory space register mapping over IO space. 1130 * Because RTL8169SC does not seem to work when memory mapping 1131 * is used always activate io mapping. 1132 */ 1133 if (devid == RT_DEVICEID_8169SC) 1134 prefer_iomap = 1; 1135 if (prefer_iomap == 0) { 1136 sc->rl_res_id = PCIR_BAR(1); 1137 sc->rl_res_type = SYS_RES_MEMORY; 1138 /* RTL8168/8101E seems to use different BARs. */ 1139 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E) 1140 sc->rl_res_id = PCIR_BAR(2); 1141 } else { 1142 sc->rl_res_id = PCIR_BAR(0); 1143 sc->rl_res_type = SYS_RES_IOPORT; 1144 } 1145 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1146 &sc->rl_res_id, RF_ACTIVE); 1147 if (sc->rl_res == NULL && prefer_iomap == 0) { 1148 sc->rl_res_id = PCIR_BAR(0); 1149 sc->rl_res_type = SYS_RES_IOPORT; 1150 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1151 &sc->rl_res_id, RF_ACTIVE); 1152 } 1153 if (sc->rl_res == NULL) { 1154 device_printf(dev, "couldn't map ports/memory\n"); 1155 error = ENXIO; 1156 goto fail; 1157 } 1158 1159 sc->rl_btag = rman_get_bustag(sc->rl_res); 1160 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1161 1162 msic = 0; 1163 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 1164 sc->rl_flags |= RL_FLAG_PCIE; 1165 msic = pci_msi_count(dev); 1166 if (bootverbose) 1167 device_printf(dev, "MSI count : %d\n", msic); 1168 } 1169 if (msic > 0 && msi_disable == 0) { 1170 msic = 1; 1171 if (pci_alloc_msi(dev, &msic) == 0) { 1172 if (msic == RL_MSI_MESSAGES) { 1173 device_printf(dev, "Using %d MSI messages\n", 1174 msic); 1175 sc->rl_flags |= RL_FLAG_MSI; 1176 /* Explicitly set MSI enable bit. */ 1177 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1178 cfg = CSR_READ_1(sc, RL_CFG2); 1179 cfg |= RL_CFG2_MSI; 1180 CSR_WRITE_1(sc, RL_CFG2, cfg); 1181 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1182 } else 1183 pci_release_msi(dev); 1184 } 1185 } 1186 1187 /* Allocate interrupt */ 1188 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1189 rid = 0; 1190 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1191 RF_SHAREABLE | RF_ACTIVE); 1192 if (sc->rl_irq[0] == NULL) { 1193 device_printf(dev, "couldn't allocate IRQ resources\n"); 1194 error = ENXIO; 1195 goto fail; 1196 } 1197 } else { 1198 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1199 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1200 SYS_RES_IRQ, &rid, RF_ACTIVE); 1201 if (sc->rl_irq[i] == NULL) { 1202 device_printf(dev, 1203 "couldn't llocate IRQ resources for " 1204 "message %d\n", rid); 1205 error = ENXIO; 1206 goto fail; 1207 } 1208 } 1209 } 1210 1211 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1212 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1213 cfg = CSR_READ_1(sc, RL_CFG2); 1214 if ((cfg & RL_CFG2_MSI) != 0) { 1215 device_printf(dev, "turning off MSI enable bit.\n"); 1216 cfg &= ~RL_CFG2_MSI; 1217 CSR_WRITE_1(sc, RL_CFG2, cfg); 1218 } 1219 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1220 } 1221 1222 /* Reset the adapter. */ 1223 RL_LOCK(sc); 1224 re_reset(sc); 1225 RL_UNLOCK(sc); 1226 1227 hw_rev = re_hwrevs; 1228 hwrev = CSR_READ_4(sc, RL_TXCFG); 1229 switch (hwrev & 0x70000000) { 1230 case 0x00000000: 1231 case 0x10000000: 1232 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000); 1233 hwrev &= (RL_TXCFG_HWREV | 0x80000000); 1234 break; 1235 default: 1236 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000); 1237 hwrev &= RL_TXCFG_HWREV; 1238 break; 1239 } 1240 device_printf(dev, "MAC rev. 0x%08x\n", hwrev & 0x00700000); 1241 while (hw_rev->rl_desc != NULL) { 1242 if (hw_rev->rl_rev == hwrev) { 1243 sc->rl_type = hw_rev->rl_type; 1244 sc->rl_hwrev = hw_rev->rl_rev; 1245 break; 1246 } 1247 hw_rev++; 1248 } 1249 if (hw_rev->rl_desc == NULL) { 1250 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev); 1251 error = ENXIO; 1252 goto fail; 1253 } 1254 1255 switch (hw_rev->rl_rev) { 1256 case RL_HWREV_8139CPLUS: 1257 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_FASTETHER | 1258 RL_FLAG_AUTOPAD; 1259 break; 1260 case RL_HWREV_8100E: 1261 case RL_HWREV_8101E: 1262 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_PHYWAKE | 1263 RL_FLAG_FASTETHER; 1264 break; 1265 case RL_HWREV_8102E: 1266 case RL_HWREV_8102EL: 1267 case RL_HWREV_8102EL_SPIN1: 1268 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_PHYWAKE | 1269 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1270 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD; 1271 break; 1272 case RL_HWREV_8103E: 1273 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_PHYWAKE | 1274 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1275 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | 1276 RL_FLAG_MACSLEEP; 1277 break; 1278 case RL_HWREV_8168_SPIN1: 1279 case RL_HWREV_8168_SPIN2: 1280 sc->rl_flags |= RL_FLAG_WOLRXENB; 1281 /* FALLTHROUGH */ 1282 case RL_HWREV_8168_SPIN3: 1283 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT; 1284 break; 1285 case RL_HWREV_8168C_SPIN2: 1286 sc->rl_flags |= RL_FLAG_MACSLEEP; 1287 /* FALLTHROUGH */ 1288 case RL_HWREV_8168C: 1289 if ((hwrev & 0x00700000) == 0x00200000) 1290 sc->rl_flags |= RL_FLAG_MACSLEEP; 1291 /* FALLTHROUGH */ 1292 case RL_HWREV_8168CP: 1293 case RL_HWREV_8168D: 1294 case RL_HWREV_8168DP: 1295 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1296 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1297 RL_FLAG_AUTOPAD; 1298 /* 1299 * These controllers support jumbo frame but it seems 1300 * that enabling it requires touching additional magic 1301 * registers. Depending on MAC revisions some 1302 * controllers need to disable checksum offload. So 1303 * disable jumbo frame until I have better idea what 1304 * it really requires to make it support. 1305 * RTL8168C/CP : supports up to 6KB jumbo frame. 1306 * RTL8111C/CP : supports up to 9KB jumbo frame. 1307 */ 1308 sc->rl_flags |= RL_FLAG_NOJUMBO; 1309 break; 1310 case RL_HWREV_8169_8110SB: 1311 case RL_HWREV_8169_8110SBL: 1312 case RL_HWREV_8169_8110SC: 1313 case RL_HWREV_8169_8110SCE: 1314 sc->rl_flags |= RL_FLAG_PHYWAKE; 1315 /* FALLTHROUGH */ 1316 case RL_HWREV_8169: 1317 case RL_HWREV_8169S: 1318 case RL_HWREV_8110S: 1319 sc->rl_flags |= RL_FLAG_MACRESET; 1320 break; 1321 default: 1322 break; 1323 } 1324 1325 /* Enable PME. */ 1326 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1327 cfg = CSR_READ_1(sc, RL_CFG1); 1328 cfg |= RL_CFG1_PME; 1329 CSR_WRITE_1(sc, RL_CFG1, cfg); 1330 cfg = CSR_READ_1(sc, RL_CFG5); 1331 cfg &= RL_CFG5_PME_STS; 1332 CSR_WRITE_1(sc, RL_CFG5, cfg); 1333 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1334 1335 if ((sc->rl_flags & RL_FLAG_PAR) != 0) { 1336 /* 1337 * XXX Should have a better way to extract station 1338 * address from EEPROM. 1339 */ 1340 for (i = 0; i < ETHER_ADDR_LEN; i++) 1341 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1342 } else { 1343 sc->rl_eewidth = RL_9356_ADDR_LEN; 1344 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1345 if (re_did != 0x8129) 1346 sc->rl_eewidth = RL_9346_ADDR_LEN; 1347 1348 /* 1349 * Get station address from the EEPROM. 1350 */ 1351 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1352 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1353 as[i] = le16toh(as[i]); 1354 bcopy(as, eaddr, sizeof(eaddr)); 1355 } 1356 1357 if (sc->rl_type == RL_8169) { 1358 /* Set RX length mask and number of descriptors. */ 1359 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1360 sc->rl_txstart = RL_GTXSTART; 1361 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1362 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1363 } else { 1364 /* Set RX length mask and number of descriptors. */ 1365 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1366 sc->rl_txstart = RL_TXSTART; 1367 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1368 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1369 } 1370 1371 error = re_allocmem(dev, sc); 1372 if (error) 1373 goto fail; 1374 1375 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1376 if (ifp == NULL) { 1377 device_printf(dev, "can not if_alloc()\n"); 1378 error = ENOSPC; 1379 goto fail; 1380 } 1381 1382 /* Take controller out of deep sleep mode. */ 1383 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 1384 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 1385 CSR_WRITE_1(sc, RL_GPIO, 1386 CSR_READ_1(sc, RL_GPIO) | 0x01); 1387 else 1388 CSR_WRITE_1(sc, RL_GPIO, 1389 CSR_READ_1(sc, RL_GPIO) & ~0x01); 1390 } 1391 1392 /* Take PHY out of power down mode. */ 1393 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) { 1394 re_gmii_writereg(dev, 1, 0x1f, 0); 1395 re_gmii_writereg(dev, 1, 0x0e, 0); 1396 } 1397 1398 /* Do MII setup */ 1399 if (mii_phy_probe(dev, &sc->rl_miibus, 1400 re_ifmedia_upd, re_ifmedia_sts)) { 1401 device_printf(dev, "MII without any phy!\n"); 1402 error = ENXIO; 1403 goto fail; 1404 } 1405 1406 ifp->if_softc = sc; 1407 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1408 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1409 ifp->if_ioctl = re_ioctl; 1410 ifp->if_start = re_start; 1411 ifp->if_hwassist = RE_CSUM_FEATURES; 1412 ifp->if_capabilities = IFCAP_HWCSUM; 1413 ifp->if_capenable = ifp->if_capabilities; 1414 ifp->if_init = re_init; 1415 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1416 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1417 IFQ_SET_READY(&ifp->if_snd); 1418 1419 TASK_INIT(&sc->rl_txtask, 1, re_tx_task, ifp); 1420 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1421 1422 /* 1423 * XXX 1424 * Still have no idea how to make TSO work on 8168C, 8168CP, 1425 * 8111C and 8111CP. 1426 */ 1427 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 1428 ifp->if_hwassist |= CSUM_TSO; 1429 ifp->if_capabilities |= IFCAP_TSO4; 1430 } 1431 1432 /* 1433 * Call MI attach routine. 1434 */ 1435 ether_ifattach(ifp, eaddr); 1436 1437 /* VLAN capability setup */ 1438 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1439 if (ifp->if_capabilities & IFCAP_HWCSUM) 1440 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1441 /* Enable WOL if PM is supported. */ 1442 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, ®) == 0) 1443 ifp->if_capabilities |= IFCAP_WOL; 1444 ifp->if_capenable = ifp->if_capabilities; 1445 /* 1446 * Don't enable TSO by default. Under certain 1447 * circumtances the controller generated corrupted 1448 * packets in TSO size. 1449 */ 1450 ifp->if_hwassist &= ~CSUM_TSO; 1451 ifp->if_capenable &= ~IFCAP_TSO4; 1452 #ifdef DEVICE_POLLING 1453 ifp->if_capabilities |= IFCAP_POLLING; 1454 #endif 1455 /* 1456 * Tell the upper layer(s) we support long frames. 1457 * Must appear after the call to ether_ifattach() because 1458 * ether_ifattach() sets ifi_hdrlen to the default value. 1459 */ 1460 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1461 1462 #ifdef RE_DIAG 1463 /* 1464 * Perform hardware diagnostic on the original RTL8169. 1465 * Some 32-bit cards were incorrectly wired and would 1466 * malfunction if plugged into a 64-bit slot. 1467 */ 1468 1469 if (hwrev == RL_HWREV_8169) { 1470 error = re_diag(sc); 1471 if (error) { 1472 device_printf(dev, 1473 "attach aborted due to hardware diag failure\n"); 1474 ether_ifdetach(ifp); 1475 goto fail; 1476 } 1477 } 1478 #endif 1479 1480 /* Hook interrupt last to avoid having to lock softc */ 1481 if ((sc->rl_flags & RL_FLAG_MSI) == 0) 1482 error = bus_setup_intr(dev, sc->rl_irq[0], 1483 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1484 &sc->rl_intrhand[0]); 1485 else { 1486 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1487 error = bus_setup_intr(dev, sc->rl_irq[i], 1488 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1489 &sc->rl_intrhand[i]); 1490 if (error != 0) 1491 break; 1492 } 1493 } 1494 if (error) { 1495 device_printf(dev, "couldn't set up irq\n"); 1496 ether_ifdetach(ifp); 1497 } 1498 1499 fail: 1500 1501 if (error) 1502 re_detach(dev); 1503 1504 return (error); 1505 } 1506 1507 /* 1508 * Shutdown hardware and free up resources. This can be called any 1509 * time after the mutex has been initialized. It is called in both 1510 * the error case in attach and the normal detach case so it needs 1511 * to be careful about only freeing resources that have actually been 1512 * allocated. 1513 */ 1514 static int 1515 re_detach(device_t dev) 1516 { 1517 struct rl_softc *sc; 1518 struct ifnet *ifp; 1519 int i, rid; 1520 1521 sc = device_get_softc(dev); 1522 ifp = sc->rl_ifp; 1523 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1524 1525 /* These should only be active if attach succeeded */ 1526 if (device_is_attached(dev)) { 1527 #ifdef DEVICE_POLLING 1528 if (ifp->if_capenable & IFCAP_POLLING) 1529 ether_poll_deregister(ifp); 1530 #endif 1531 RL_LOCK(sc); 1532 #if 0 1533 sc->suspended = 1; 1534 #endif 1535 re_stop(sc); 1536 RL_UNLOCK(sc); 1537 callout_drain(&sc->rl_stat_callout); 1538 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1539 taskqueue_drain(taskqueue_fast, &sc->rl_txtask); 1540 /* 1541 * Force off the IFF_UP flag here, in case someone 1542 * still had a BPF descriptor attached to this 1543 * interface. If they do, ether_ifdetach() will cause 1544 * the BPF code to try and clear the promisc mode 1545 * flag, which will bubble down to re_ioctl(), 1546 * which will try to call re_init() again. This will 1547 * turn the NIC back on and restart the MII ticker, 1548 * which will panic the system when the kernel tries 1549 * to invoke the re_tick() function that isn't there 1550 * anymore. 1551 */ 1552 ifp->if_flags &= ~IFF_UP; 1553 ether_ifdetach(ifp); 1554 } 1555 if (sc->rl_miibus) 1556 device_delete_child(dev, sc->rl_miibus); 1557 bus_generic_detach(dev); 1558 1559 /* 1560 * The rest is resource deallocation, so we should already be 1561 * stopped here. 1562 */ 1563 1564 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1565 if (sc->rl_intrhand[i] != NULL) { 1566 bus_teardown_intr(dev, sc->rl_irq[i], 1567 sc->rl_intrhand[i]); 1568 sc->rl_intrhand[i] = NULL; 1569 } 1570 } 1571 if (ifp != NULL) 1572 if_free(ifp); 1573 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1574 if (sc->rl_irq[0] != NULL) { 1575 bus_release_resource(dev, SYS_RES_IRQ, 0, 1576 sc->rl_irq[0]); 1577 sc->rl_irq[0] = NULL; 1578 } 1579 } else { 1580 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1581 if (sc->rl_irq[i] != NULL) { 1582 bus_release_resource(dev, SYS_RES_IRQ, rid, 1583 sc->rl_irq[i]); 1584 sc->rl_irq[i] = NULL; 1585 } 1586 } 1587 pci_release_msi(dev); 1588 } 1589 if (sc->rl_res) 1590 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, 1591 sc->rl_res); 1592 1593 /* Unload and free the RX DMA ring memory and map */ 1594 1595 if (sc->rl_ldata.rl_rx_list_tag) { 1596 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1597 sc->rl_ldata.rl_rx_list_map); 1598 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1599 sc->rl_ldata.rl_rx_list, 1600 sc->rl_ldata.rl_rx_list_map); 1601 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1602 } 1603 1604 /* Unload and free the TX DMA ring memory and map */ 1605 1606 if (sc->rl_ldata.rl_tx_list_tag) { 1607 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1608 sc->rl_ldata.rl_tx_list_map); 1609 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1610 sc->rl_ldata.rl_tx_list, 1611 sc->rl_ldata.rl_tx_list_map); 1612 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1613 } 1614 1615 /* Destroy all the RX and TX buffer maps */ 1616 1617 if (sc->rl_ldata.rl_tx_mtag) { 1618 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1619 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1620 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1621 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1622 } 1623 if (sc->rl_ldata.rl_rx_mtag) { 1624 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) 1625 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1626 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1627 if (sc->rl_ldata.rl_rx_sparemap) 1628 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1629 sc->rl_ldata.rl_rx_sparemap); 1630 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1631 } 1632 1633 /* Unload and free the stats buffer and map */ 1634 1635 if (sc->rl_ldata.rl_stag) { 1636 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1637 sc->rl_ldata.rl_rx_list_map); 1638 bus_dmamem_free(sc->rl_ldata.rl_stag, 1639 sc->rl_ldata.rl_stats, 1640 sc->rl_ldata.rl_smap); 1641 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1642 } 1643 1644 if (sc->rl_parent_tag) 1645 bus_dma_tag_destroy(sc->rl_parent_tag); 1646 1647 mtx_destroy(&sc->rl_mtx); 1648 1649 return (0); 1650 } 1651 1652 static __inline void 1653 re_discard_rxbuf(struct rl_softc *sc, int idx) 1654 { 1655 struct rl_desc *desc; 1656 struct rl_rxdesc *rxd; 1657 uint32_t cmdstat; 1658 1659 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1660 desc = &sc->rl_ldata.rl_rx_list[idx]; 1661 desc->rl_vlanctl = 0; 1662 cmdstat = rxd->rx_size; 1663 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1664 cmdstat |= RL_RDESC_CMD_EOR; 1665 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1666 } 1667 1668 static int 1669 re_newbuf(struct rl_softc *sc, int idx) 1670 { 1671 struct mbuf *m; 1672 struct rl_rxdesc *rxd; 1673 bus_dma_segment_t segs[1]; 1674 bus_dmamap_t map; 1675 struct rl_desc *desc; 1676 uint32_t cmdstat; 1677 int error, nsegs; 1678 1679 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1680 if (m == NULL) 1681 return (ENOBUFS); 1682 1683 m->m_len = m->m_pkthdr.len = MCLBYTES; 1684 #ifdef RE_FIXUP_RX 1685 /* 1686 * This is part of an evil trick to deal with non-x86 platforms. 1687 * The RealTek chip requires RX buffers to be aligned on 64-bit 1688 * boundaries, but that will hose non-x86 machines. To get around 1689 * this, we leave some empty space at the start of each buffer 1690 * and for non-x86 hosts, we copy the buffer back six bytes 1691 * to achieve word alignment. This is slightly more efficient 1692 * than allocating a new buffer, copying the contents, and 1693 * discarding the old buffer. 1694 */ 1695 m_adj(m, RE_ETHER_ALIGN); 1696 #endif 1697 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1698 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1699 if (error != 0) { 1700 m_freem(m); 1701 return (ENOBUFS); 1702 } 1703 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1704 1705 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1706 if (rxd->rx_m != NULL) { 1707 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1708 BUS_DMASYNC_POSTREAD); 1709 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1710 } 1711 1712 rxd->rx_m = m; 1713 map = rxd->rx_dmamap; 1714 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1715 rxd->rx_size = segs[0].ds_len; 1716 sc->rl_ldata.rl_rx_sparemap = map; 1717 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1718 BUS_DMASYNC_PREREAD); 1719 1720 desc = &sc->rl_ldata.rl_rx_list[idx]; 1721 desc->rl_vlanctl = 0; 1722 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1723 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1724 cmdstat = segs[0].ds_len; 1725 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1726 cmdstat |= RL_RDESC_CMD_EOR; 1727 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1728 1729 return (0); 1730 } 1731 1732 #ifdef RE_FIXUP_RX 1733 static __inline void 1734 re_fixup_rx(struct mbuf *m) 1735 { 1736 int i; 1737 uint16_t *src, *dst; 1738 1739 src = mtod(m, uint16_t *); 1740 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1741 1742 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1743 *dst++ = *src++; 1744 1745 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1746 } 1747 #endif 1748 1749 static int 1750 re_tx_list_init(struct rl_softc *sc) 1751 { 1752 struct rl_desc *desc; 1753 int i; 1754 1755 RL_LOCK_ASSERT(sc); 1756 1757 bzero(sc->rl_ldata.rl_tx_list, 1758 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 1759 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1760 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 1761 /* Set EOR. */ 1762 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 1763 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 1764 1765 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1766 sc->rl_ldata.rl_tx_list_map, 1767 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1768 1769 sc->rl_ldata.rl_tx_prodidx = 0; 1770 sc->rl_ldata.rl_tx_considx = 0; 1771 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 1772 1773 return (0); 1774 } 1775 1776 static int 1777 re_rx_list_init(struct rl_softc *sc) 1778 { 1779 int error, i; 1780 1781 bzero(sc->rl_ldata.rl_rx_list, 1782 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 1783 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1784 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 1785 if ((error = re_newbuf(sc, i)) != 0) 1786 return (error); 1787 } 1788 1789 /* Flush the RX descriptors */ 1790 1791 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1792 sc->rl_ldata.rl_rx_list_map, 1793 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1794 1795 sc->rl_ldata.rl_rx_prodidx = 0; 1796 sc->rl_head = sc->rl_tail = NULL; 1797 1798 return (0); 1799 } 1800 1801 /* 1802 * RX handler for C+ and 8169. For the gigE chips, we support 1803 * the reception of jumbo frames that have been fragmented 1804 * across multiple 2K mbuf cluster buffers. 1805 */ 1806 static int 1807 re_rxeof(struct rl_softc *sc, int *rx_npktsp) 1808 { 1809 struct mbuf *m; 1810 struct ifnet *ifp; 1811 int i, total_len; 1812 struct rl_desc *cur_rx; 1813 u_int32_t rxstat, rxvlan; 1814 int maxpkt = 16, rx_npkts = 0; 1815 1816 RL_LOCK_ASSERT(sc); 1817 1818 ifp = sc->rl_ifp; 1819 1820 /* Invalidate the descriptor memory */ 1821 1822 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1823 sc->rl_ldata.rl_rx_list_map, 1824 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1825 1826 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 1827 i = RL_RX_DESC_NXT(sc, i)) { 1828 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1829 break; 1830 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1831 rxstat = le32toh(cur_rx->rl_cmdstat); 1832 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 1833 break; 1834 total_len = rxstat & sc->rl_rxlenmask; 1835 rxvlan = le32toh(cur_rx->rl_vlanctl); 1836 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 1837 1838 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1839 if (re_newbuf(sc, i) != 0) { 1840 /* 1841 * If this is part of a multi-fragment packet, 1842 * discard all the pieces. 1843 */ 1844 if (sc->rl_head != NULL) { 1845 m_freem(sc->rl_head); 1846 sc->rl_head = sc->rl_tail = NULL; 1847 } 1848 re_discard_rxbuf(sc, i); 1849 continue; 1850 } 1851 m->m_len = RE_RX_DESC_BUFLEN; 1852 if (sc->rl_head == NULL) 1853 sc->rl_head = sc->rl_tail = m; 1854 else { 1855 m->m_flags &= ~M_PKTHDR; 1856 sc->rl_tail->m_next = m; 1857 sc->rl_tail = m; 1858 } 1859 continue; 1860 } 1861 1862 /* 1863 * NOTE: for the 8139C+, the frame length field 1864 * is always 12 bits in size, but for the gigE chips, 1865 * it is 13 bits (since the max RX frame length is 16K). 1866 * Unfortunately, all 32 bits in the status word 1867 * were already used, so to make room for the extra 1868 * length bit, RealTek took out the 'frame alignment 1869 * error' bit and shifted the other status bits 1870 * over one slot. The OWN, EOR, FS and LS bits are 1871 * still in the same places. We have already extracted 1872 * the frame length and checked the OWN bit, so rather 1873 * than using an alternate bit mapping, we shift the 1874 * status bits one space to the right so we can evaluate 1875 * them using the 8169 status as though it was in the 1876 * same format as that of the 8139C+. 1877 */ 1878 if (sc->rl_type == RL_8169) 1879 rxstat >>= 1; 1880 1881 /* 1882 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 1883 * set, but if CRC is clear, it will still be a valid frame. 1884 */ 1885 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 && 1886 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) { 1887 ifp->if_ierrors++; 1888 /* 1889 * If this is part of a multi-fragment packet, 1890 * discard all the pieces. 1891 */ 1892 if (sc->rl_head != NULL) { 1893 m_freem(sc->rl_head); 1894 sc->rl_head = sc->rl_tail = NULL; 1895 } 1896 re_discard_rxbuf(sc, i); 1897 continue; 1898 } 1899 1900 /* 1901 * If allocating a replacement mbuf fails, 1902 * reload the current one. 1903 */ 1904 1905 if (re_newbuf(sc, i) != 0) { 1906 ifp->if_iqdrops++; 1907 if (sc->rl_head != NULL) { 1908 m_freem(sc->rl_head); 1909 sc->rl_head = sc->rl_tail = NULL; 1910 } 1911 re_discard_rxbuf(sc, i); 1912 continue; 1913 } 1914 1915 if (sc->rl_head != NULL) { 1916 m->m_len = total_len % RE_RX_DESC_BUFLEN; 1917 if (m->m_len == 0) 1918 m->m_len = RE_RX_DESC_BUFLEN; 1919 /* 1920 * Special case: if there's 4 bytes or less 1921 * in this buffer, the mbuf can be discarded: 1922 * the last 4 bytes is the CRC, which we don't 1923 * care about anyway. 1924 */ 1925 if (m->m_len <= ETHER_CRC_LEN) { 1926 sc->rl_tail->m_len -= 1927 (ETHER_CRC_LEN - m->m_len); 1928 m_freem(m); 1929 } else { 1930 m->m_len -= ETHER_CRC_LEN; 1931 m->m_flags &= ~M_PKTHDR; 1932 sc->rl_tail->m_next = m; 1933 } 1934 m = sc->rl_head; 1935 sc->rl_head = sc->rl_tail = NULL; 1936 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1937 } else 1938 m->m_pkthdr.len = m->m_len = 1939 (total_len - ETHER_CRC_LEN); 1940 1941 #ifdef RE_FIXUP_RX 1942 re_fixup_rx(m); 1943 #endif 1944 ifp->if_ipackets++; 1945 m->m_pkthdr.rcvif = ifp; 1946 1947 /* Do RX checksumming if enabled */ 1948 1949 if (ifp->if_capenable & IFCAP_RXCSUM) { 1950 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 1951 /* Check IP header checksum */ 1952 if (rxstat & RL_RDESC_STAT_PROTOID) 1953 m->m_pkthdr.csum_flags |= 1954 CSUM_IP_CHECKED; 1955 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1956 m->m_pkthdr.csum_flags |= 1957 CSUM_IP_VALID; 1958 1959 /* Check TCP/UDP checksum */ 1960 if ((RL_TCPPKT(rxstat) && 1961 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1962 (RL_UDPPKT(rxstat) && 1963 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1964 m->m_pkthdr.csum_flags |= 1965 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1966 m->m_pkthdr.csum_data = 0xffff; 1967 } 1968 } else { 1969 /* 1970 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP 1971 */ 1972 if ((rxstat & RL_RDESC_STAT_PROTOID) && 1973 (rxvlan & RL_RDESC_IPV4)) 1974 m->m_pkthdr.csum_flags |= 1975 CSUM_IP_CHECKED; 1976 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) && 1977 (rxvlan & RL_RDESC_IPV4)) 1978 m->m_pkthdr.csum_flags |= 1979 CSUM_IP_VALID; 1980 if (((rxstat & RL_RDESC_STAT_TCP) && 1981 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1982 ((rxstat & RL_RDESC_STAT_UDP) && 1983 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1984 m->m_pkthdr.csum_flags |= 1985 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1986 m->m_pkthdr.csum_data = 0xffff; 1987 } 1988 } 1989 } 1990 maxpkt--; 1991 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 1992 m->m_pkthdr.ether_vtag = 1993 bswap16((rxvlan & RL_RDESC_VLANCTL_DATA)); 1994 m->m_flags |= M_VLANTAG; 1995 } 1996 RL_UNLOCK(sc); 1997 (*ifp->if_input)(ifp, m); 1998 RL_LOCK(sc); 1999 rx_npkts++; 2000 } 2001 2002 /* Flush the RX DMA ring */ 2003 2004 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2005 sc->rl_ldata.rl_rx_list_map, 2006 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2007 2008 sc->rl_ldata.rl_rx_prodidx = i; 2009 2010 if (rx_npktsp != NULL) 2011 *rx_npktsp = rx_npkts; 2012 if (maxpkt) 2013 return(EAGAIN); 2014 2015 return(0); 2016 } 2017 2018 static void 2019 re_txeof(struct rl_softc *sc) 2020 { 2021 struct ifnet *ifp; 2022 struct rl_txdesc *txd; 2023 u_int32_t txstat; 2024 int cons; 2025 2026 cons = sc->rl_ldata.rl_tx_considx; 2027 if (cons == sc->rl_ldata.rl_tx_prodidx) 2028 return; 2029 2030 ifp = sc->rl_ifp; 2031 /* Invalidate the TX descriptor list */ 2032 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2033 sc->rl_ldata.rl_tx_list_map, 2034 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2035 2036 for (; cons != sc->rl_ldata.rl_tx_prodidx; 2037 cons = RL_TX_DESC_NXT(sc, cons)) { 2038 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 2039 if (txstat & RL_TDESC_STAT_OWN) 2040 break; 2041 /* 2042 * We only stash mbufs in the last descriptor 2043 * in a fragment chain, which also happens to 2044 * be the only place where the TX status bits 2045 * are valid. 2046 */ 2047 if (txstat & RL_TDESC_CMD_EOF) { 2048 txd = &sc->rl_ldata.rl_tx_desc[cons]; 2049 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2050 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2051 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2052 txd->tx_dmamap); 2053 KASSERT(txd->tx_m != NULL, 2054 ("%s: freeing NULL mbufs!", __func__)); 2055 m_freem(txd->tx_m); 2056 txd->tx_m = NULL; 2057 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 2058 RL_TDESC_STAT_COLCNT)) 2059 ifp->if_collisions++; 2060 if (txstat & RL_TDESC_STAT_TXERRSUM) 2061 ifp->if_oerrors++; 2062 else 2063 ifp->if_opackets++; 2064 } 2065 sc->rl_ldata.rl_tx_free++; 2066 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2067 } 2068 sc->rl_ldata.rl_tx_considx = cons; 2069 2070 /* No changes made to the TX ring, so no flush needed */ 2071 2072 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 2073 #ifdef RE_TX_MODERATION 2074 /* 2075 * If not all descriptors have been reaped yet, reload 2076 * the timer so that we will eventually get another 2077 * interrupt that will cause us to re-enter this routine. 2078 * This is done in case the transmitter has gone idle. 2079 */ 2080 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2081 #endif 2082 } else 2083 sc->rl_watchdog_timer = 0; 2084 } 2085 2086 static void 2087 re_tick(void *xsc) 2088 { 2089 struct rl_softc *sc; 2090 struct mii_data *mii; 2091 2092 sc = xsc; 2093 2094 RL_LOCK_ASSERT(sc); 2095 2096 mii = device_get_softc(sc->rl_miibus); 2097 mii_tick(mii); 2098 if ((sc->rl_flags & RL_FLAG_LINK) == 0) 2099 re_miibus_statchg(sc->rl_dev); 2100 /* 2101 * Reclaim transmitted frames here. Technically it is not 2102 * necessary to do here but it ensures periodic reclamation 2103 * regardless of Tx completion interrupt which seems to be 2104 * lost on PCIe based controllers under certain situations. 2105 */ 2106 re_txeof(sc); 2107 re_watchdog(sc); 2108 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2109 } 2110 2111 #ifdef DEVICE_POLLING 2112 static int 2113 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2114 { 2115 struct rl_softc *sc = ifp->if_softc; 2116 int rx_npkts = 0; 2117 2118 RL_LOCK(sc); 2119 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2120 rx_npkts = re_poll_locked(ifp, cmd, count); 2121 RL_UNLOCK(sc); 2122 return (rx_npkts); 2123 } 2124 2125 static int 2126 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2127 { 2128 struct rl_softc *sc = ifp->if_softc; 2129 int rx_npkts; 2130 2131 RL_LOCK_ASSERT(sc); 2132 2133 sc->rxcycles = count; 2134 re_rxeof(sc, &rx_npkts); 2135 re_txeof(sc); 2136 2137 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2138 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2139 2140 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2141 u_int16_t status; 2142 2143 status = CSR_READ_2(sc, RL_ISR); 2144 if (status == 0xffff) 2145 return (rx_npkts); 2146 if (status) 2147 CSR_WRITE_2(sc, RL_ISR, status); 2148 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2149 (sc->rl_flags & RL_FLAG_PCIE)) 2150 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2151 2152 /* 2153 * XXX check behaviour on receiver stalls. 2154 */ 2155 2156 if (status & RL_ISR_SYSTEM_ERR) { 2157 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2158 re_init_locked(sc); 2159 } 2160 } 2161 return (rx_npkts); 2162 } 2163 #endif /* DEVICE_POLLING */ 2164 2165 static int 2166 re_intr(void *arg) 2167 { 2168 struct rl_softc *sc; 2169 uint16_t status; 2170 2171 sc = arg; 2172 2173 status = CSR_READ_2(sc, RL_ISR); 2174 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2175 return (FILTER_STRAY); 2176 CSR_WRITE_2(sc, RL_IMR, 0); 2177 2178 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2179 2180 return (FILTER_HANDLED); 2181 } 2182 2183 static void 2184 re_int_task(void *arg, int npending) 2185 { 2186 struct rl_softc *sc; 2187 struct ifnet *ifp; 2188 u_int16_t status; 2189 int rval = 0; 2190 2191 sc = arg; 2192 ifp = sc->rl_ifp; 2193 2194 RL_LOCK(sc); 2195 2196 status = CSR_READ_2(sc, RL_ISR); 2197 CSR_WRITE_2(sc, RL_ISR, status); 2198 2199 if (sc->suspended || 2200 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2201 RL_UNLOCK(sc); 2202 return; 2203 } 2204 2205 #ifdef DEVICE_POLLING 2206 if (ifp->if_capenable & IFCAP_POLLING) { 2207 RL_UNLOCK(sc); 2208 return; 2209 } 2210 #endif 2211 2212 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2213 rval = re_rxeof(sc, NULL); 2214 2215 /* 2216 * Some chips will ignore a second TX request issued 2217 * while an existing transmission is in progress. If 2218 * the transmitter goes idle but there are still 2219 * packets waiting to be sent, we need to restart the 2220 * channel here to flush them out. This only seems to 2221 * be required with the PCIe devices. 2222 */ 2223 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2224 (sc->rl_flags & RL_FLAG_PCIE)) 2225 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2226 if (status & ( 2227 #ifdef RE_TX_MODERATION 2228 RL_ISR_TIMEOUT_EXPIRED| 2229 #else 2230 RL_ISR_TX_OK| 2231 #endif 2232 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2233 re_txeof(sc); 2234 2235 if (status & RL_ISR_SYSTEM_ERR) { 2236 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2237 re_init_locked(sc); 2238 } 2239 2240 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2241 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2242 2243 RL_UNLOCK(sc); 2244 2245 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2246 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2247 return; 2248 } 2249 2250 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2251 } 2252 2253 static int 2254 re_encap(struct rl_softc *sc, struct mbuf **m_head) 2255 { 2256 struct rl_txdesc *txd, *txd_last; 2257 bus_dma_segment_t segs[RL_NTXSEGS]; 2258 bus_dmamap_t map; 2259 struct mbuf *m_new; 2260 struct rl_desc *desc; 2261 int nsegs, prod; 2262 int i, error, ei, si; 2263 int padlen; 2264 uint32_t cmdstat, csum_flags, vlanctl; 2265 2266 RL_LOCK_ASSERT(sc); 2267 M_ASSERTPKTHDR((*m_head)); 2268 2269 /* 2270 * With some of the RealTek chips, using the checksum offload 2271 * support in conjunction with the autopadding feature results 2272 * in the transmission of corrupt frames. For example, if we 2273 * need to send a really small IP fragment that's less than 60 2274 * bytes in size, and IP header checksumming is enabled, the 2275 * resulting ethernet frame that appears on the wire will 2276 * have garbled payload. To work around this, if TX IP checksum 2277 * offload is enabled, we always manually pad short frames out 2278 * to the minimum ethernet frame size. 2279 */ 2280 if ((sc->rl_flags & RL_FLAG_AUTOPAD) == 0 && 2281 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN && 2282 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) { 2283 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2284 if (M_WRITABLE(*m_head) == 0) { 2285 /* Get a writable copy. */ 2286 m_new = m_dup(*m_head, M_DONTWAIT); 2287 m_freem(*m_head); 2288 if (m_new == NULL) { 2289 *m_head = NULL; 2290 return (ENOBUFS); 2291 } 2292 *m_head = m_new; 2293 } 2294 if ((*m_head)->m_next != NULL || 2295 M_TRAILINGSPACE(*m_head) < padlen) { 2296 m_new = m_defrag(*m_head, M_DONTWAIT); 2297 if (m_new == NULL) { 2298 m_freem(*m_head); 2299 *m_head = NULL; 2300 return (ENOBUFS); 2301 } 2302 } else 2303 m_new = *m_head; 2304 2305 /* 2306 * Manually pad short frames, and zero the pad space 2307 * to avoid leaking data. 2308 */ 2309 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2310 m_new->m_pkthdr.len += padlen; 2311 m_new->m_len = m_new->m_pkthdr.len; 2312 *m_head = m_new; 2313 } 2314 2315 prod = sc->rl_ldata.rl_tx_prodidx; 2316 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2317 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2318 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2319 if (error == EFBIG) { 2320 m_new = m_collapse(*m_head, M_DONTWAIT, RL_NTXSEGS); 2321 if (m_new == NULL) { 2322 m_freem(*m_head); 2323 *m_head = NULL; 2324 return (ENOBUFS); 2325 } 2326 *m_head = m_new; 2327 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2328 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2329 if (error != 0) { 2330 m_freem(*m_head); 2331 *m_head = NULL; 2332 return (error); 2333 } 2334 } else if (error != 0) 2335 return (error); 2336 if (nsegs == 0) { 2337 m_freem(*m_head); 2338 *m_head = NULL; 2339 return (EIO); 2340 } 2341 2342 /* Check for number of available descriptors. */ 2343 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2344 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2345 return (ENOBUFS); 2346 } 2347 2348 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2349 BUS_DMASYNC_PREWRITE); 2350 2351 /* 2352 * Set up checksum offload. Note: checksum offload bits must 2353 * appear in all descriptors of a multi-descriptor transmit 2354 * attempt. This is according to testing done with an 8169 2355 * chip. This is a requirement. 2356 */ 2357 vlanctl = 0; 2358 csum_flags = 0; 2359 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) 2360 csum_flags = RL_TDESC_CMD_LGSEND | 2361 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2362 RL_TDESC_CMD_MSSVAL_SHIFT); 2363 else { 2364 /* 2365 * Unconditionally enable IP checksum if TCP or UDP 2366 * checksum is required. Otherwise, TCP/UDP checksum 2367 * does't make effects. 2368 */ 2369 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) { 2370 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2371 csum_flags |= RL_TDESC_CMD_IPCSUM; 2372 if (((*m_head)->m_pkthdr.csum_flags & 2373 CSUM_TCP) != 0) 2374 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2375 if (((*m_head)->m_pkthdr.csum_flags & 2376 CSUM_UDP) != 0) 2377 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2378 } else { 2379 vlanctl |= RL_TDESC_CMD_IPCSUMV2; 2380 if (((*m_head)->m_pkthdr.csum_flags & 2381 CSUM_TCP) != 0) 2382 vlanctl |= RL_TDESC_CMD_TCPCSUMV2; 2383 if (((*m_head)->m_pkthdr.csum_flags & 2384 CSUM_UDP) != 0) 2385 vlanctl |= RL_TDESC_CMD_UDPCSUMV2; 2386 } 2387 } 2388 } 2389 2390 /* 2391 * Set up hardware VLAN tagging. Note: vlan tag info must 2392 * appear in all descriptors of a multi-descriptor 2393 * transmission attempt. 2394 */ 2395 if ((*m_head)->m_flags & M_VLANTAG) 2396 vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) | 2397 RL_TDESC_VLANCTL_TAG; 2398 2399 si = prod; 2400 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2401 desc = &sc->rl_ldata.rl_tx_list[prod]; 2402 desc->rl_vlanctl = htole32(vlanctl); 2403 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2404 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2405 cmdstat = segs[i].ds_len; 2406 if (i != 0) 2407 cmdstat |= RL_TDESC_CMD_OWN; 2408 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2409 cmdstat |= RL_TDESC_CMD_EOR; 2410 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2411 sc->rl_ldata.rl_tx_free--; 2412 } 2413 /* Update producer index. */ 2414 sc->rl_ldata.rl_tx_prodidx = prod; 2415 2416 /* Set EOF on the last descriptor. */ 2417 ei = RL_TX_DESC_PRV(sc, prod); 2418 desc = &sc->rl_ldata.rl_tx_list[ei]; 2419 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2420 2421 desc = &sc->rl_ldata.rl_tx_list[si]; 2422 /* Set SOF and transfer ownership of packet to the chip. */ 2423 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2424 2425 /* 2426 * Insure that the map for this transmission 2427 * is placed at the array index of the last descriptor 2428 * in this chain. (Swap last and first dmamaps.) 2429 */ 2430 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2431 map = txd->tx_dmamap; 2432 txd->tx_dmamap = txd_last->tx_dmamap; 2433 txd_last->tx_dmamap = map; 2434 txd_last->tx_m = *m_head; 2435 2436 return (0); 2437 } 2438 2439 static void 2440 re_tx_task(void *arg, int npending) 2441 { 2442 struct ifnet *ifp; 2443 2444 ifp = arg; 2445 re_start(ifp); 2446 } 2447 2448 /* 2449 * Main transmit routine for C+ and gigE NICs. 2450 */ 2451 static void 2452 re_start(struct ifnet *ifp) 2453 { 2454 struct rl_softc *sc; 2455 struct mbuf *m_head; 2456 int queued; 2457 2458 sc = ifp->if_softc; 2459 2460 RL_LOCK(sc); 2461 2462 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2463 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) { 2464 RL_UNLOCK(sc); 2465 return; 2466 } 2467 2468 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2469 sc->rl_ldata.rl_tx_free > 1;) { 2470 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2471 if (m_head == NULL) 2472 break; 2473 2474 if (re_encap(sc, &m_head) != 0) { 2475 if (m_head == NULL) 2476 break; 2477 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2478 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2479 break; 2480 } 2481 2482 /* 2483 * If there's a BPF listener, bounce a copy of this frame 2484 * to him. 2485 */ 2486 ETHER_BPF_MTAP(ifp, m_head); 2487 2488 queued++; 2489 } 2490 2491 if (queued == 0) { 2492 #ifdef RE_TX_MODERATION 2493 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2494 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2495 #endif 2496 RL_UNLOCK(sc); 2497 return; 2498 } 2499 2500 /* Flush the TX descriptors */ 2501 2502 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2503 sc->rl_ldata.rl_tx_list_map, 2504 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2505 2506 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2507 2508 #ifdef RE_TX_MODERATION 2509 /* 2510 * Use the countdown timer for interrupt moderation. 2511 * 'TX done' interrupts are disabled. Instead, we reset the 2512 * countdown timer, which will begin counting until it hits 2513 * the value in the TIMERINT register, and then trigger an 2514 * interrupt. Each time we write to the TIMERCNT register, 2515 * the timer count is reset to 0. 2516 */ 2517 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2518 #endif 2519 2520 /* 2521 * Set a timeout in case the chip goes out to lunch. 2522 */ 2523 sc->rl_watchdog_timer = 5; 2524 2525 RL_UNLOCK(sc); 2526 } 2527 2528 static void 2529 re_init(void *xsc) 2530 { 2531 struct rl_softc *sc = xsc; 2532 2533 RL_LOCK(sc); 2534 re_init_locked(sc); 2535 RL_UNLOCK(sc); 2536 } 2537 2538 static void 2539 re_init_locked(struct rl_softc *sc) 2540 { 2541 struct ifnet *ifp = sc->rl_ifp; 2542 struct mii_data *mii; 2543 uint32_t reg; 2544 uint16_t cfg; 2545 union { 2546 uint32_t align_dummy; 2547 u_char eaddr[ETHER_ADDR_LEN]; 2548 } eaddr; 2549 2550 RL_LOCK_ASSERT(sc); 2551 2552 mii = device_get_softc(sc->rl_miibus); 2553 2554 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2555 return; 2556 2557 /* 2558 * Cancel pending I/O and free all RX/TX buffers. 2559 */ 2560 re_stop(sc); 2561 2562 /* Put controller into known state. */ 2563 re_reset(sc); 2564 2565 /* 2566 * Enable C+ RX and TX mode, as well as VLAN stripping and 2567 * RX checksum offload. We must configure the C+ register 2568 * before all others. 2569 */ 2570 cfg = RL_CPLUSCMD_PCI_MRW; 2571 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2572 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 2573 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2574 cfg |= RL_CPLUSCMD_VLANSTRIP; 2575 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) { 2576 cfg |= RL_CPLUSCMD_MACSTAT_DIS; 2577 /* XXX magic. */ 2578 cfg |= 0x0001; 2579 } else 2580 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB; 2581 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg); 2582 if (sc->rl_hwrev == RL_HWREV_8169_8110SC || 2583 sc->rl_hwrev == RL_HWREV_8169_8110SCE) { 2584 reg = 0x000fff00; 2585 if ((CSR_READ_1(sc, RL_CFG2) & RL_CFG2_PCI66MHZ) != 0) 2586 reg |= 0x000000ff; 2587 if (sc->rl_hwrev == RL_HWREV_8169_8110SCE) 2588 reg |= 0x00f00000; 2589 CSR_WRITE_4(sc, 0x7c, reg); 2590 /* Disable interrupt mitigation. */ 2591 CSR_WRITE_2(sc, 0xe2, 0); 2592 } 2593 /* 2594 * Disable TSO if interface MTU size is greater than MSS 2595 * allowed in controller. 2596 */ 2597 if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) { 2598 ifp->if_capenable &= ~IFCAP_TSO4; 2599 ifp->if_hwassist &= ~CSUM_TSO; 2600 } 2601 2602 /* 2603 * Init our MAC address. Even though the chipset 2604 * documentation doesn't mention it, we need to enter "Config 2605 * register write enable" mode to modify the ID registers. 2606 */ 2607 /* Copy MAC address on stack to align. */ 2608 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 2609 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2610 CSR_WRITE_4(sc, RL_IDR0, 2611 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 2612 CSR_WRITE_4(sc, RL_IDR4, 2613 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 2614 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2615 2616 /* 2617 * For C+ mode, initialize the RX descriptors and mbufs. 2618 */ 2619 re_rx_list_init(sc); 2620 re_tx_list_init(sc); 2621 2622 /* 2623 * Load the addresses of the RX and TX lists into the chip. 2624 */ 2625 2626 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2627 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2628 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2629 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2630 2631 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2632 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2633 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2634 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2635 2636 /* 2637 * Enable transmit and receive. 2638 */ 2639 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2640 2641 /* 2642 * Set the initial TX configuration. 2643 */ 2644 if (sc->rl_testmode) { 2645 if (sc->rl_type == RL_8169) 2646 CSR_WRITE_4(sc, RL_TXCFG, 2647 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2648 else 2649 CSR_WRITE_4(sc, RL_TXCFG, 2650 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2651 } else 2652 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2653 2654 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2655 2656 /* 2657 * Set the initial RX configuration. 2658 */ 2659 re_set_rxmode(sc); 2660 2661 #ifdef DEVICE_POLLING 2662 /* 2663 * Disable interrupts if we are polling. 2664 */ 2665 if (ifp->if_capenable & IFCAP_POLLING) 2666 CSR_WRITE_2(sc, RL_IMR, 0); 2667 else /* otherwise ... */ 2668 #endif 2669 2670 /* 2671 * Enable interrupts. 2672 */ 2673 if (sc->rl_testmode) 2674 CSR_WRITE_2(sc, RL_IMR, 0); 2675 else 2676 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2677 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 2678 2679 /* Set initial TX threshold */ 2680 sc->rl_txthresh = RL_TX_THRESH_INIT; 2681 2682 /* Start RX/TX process. */ 2683 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2684 #ifdef notdef 2685 /* Enable receiver and transmitter. */ 2686 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2687 #endif 2688 2689 #ifdef RE_TX_MODERATION 2690 /* 2691 * Initialize the timer interrupt register so that 2692 * a timer interrupt will be generated once the timer 2693 * reaches a certain number of ticks. The timer is 2694 * reloaded on each transmit. This gives us TX interrupt 2695 * moderation, which dramatically improves TX frame rate. 2696 */ 2697 if (sc->rl_type == RL_8169) 2698 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2699 else 2700 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2701 #endif 2702 2703 /* 2704 * For 8169 gigE NICs, set the max allowed RX packet 2705 * size so we can receive jumbo frames. 2706 */ 2707 if (sc->rl_type == RL_8169) 2708 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2709 2710 if (sc->rl_testmode) 2711 return; 2712 2713 mii_mediachg(mii); 2714 2715 CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD); 2716 2717 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2718 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2719 2720 sc->rl_flags &= ~RL_FLAG_LINK; 2721 sc->rl_watchdog_timer = 0; 2722 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2723 } 2724 2725 /* 2726 * Set media options. 2727 */ 2728 static int 2729 re_ifmedia_upd(struct ifnet *ifp) 2730 { 2731 struct rl_softc *sc; 2732 struct mii_data *mii; 2733 int error; 2734 2735 sc = ifp->if_softc; 2736 mii = device_get_softc(sc->rl_miibus); 2737 RL_LOCK(sc); 2738 error = mii_mediachg(mii); 2739 RL_UNLOCK(sc); 2740 2741 return (error); 2742 } 2743 2744 /* 2745 * Report current media status. 2746 */ 2747 static void 2748 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2749 { 2750 struct rl_softc *sc; 2751 struct mii_data *mii; 2752 2753 sc = ifp->if_softc; 2754 mii = device_get_softc(sc->rl_miibus); 2755 2756 RL_LOCK(sc); 2757 mii_pollstat(mii); 2758 RL_UNLOCK(sc); 2759 ifmr->ifm_active = mii->mii_media_active; 2760 ifmr->ifm_status = mii->mii_media_status; 2761 } 2762 2763 static int 2764 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2765 { 2766 struct rl_softc *sc = ifp->if_softc; 2767 struct ifreq *ifr = (struct ifreq *) data; 2768 struct mii_data *mii; 2769 int error = 0; 2770 2771 switch (command) { 2772 case SIOCSIFMTU: 2773 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > RL_JUMBO_MTU) { 2774 error = EINVAL; 2775 break; 2776 } 2777 if ((sc->rl_flags & RL_FLAG_NOJUMBO) != 0 && 2778 ifr->ifr_mtu > RL_MAX_FRAMELEN) { 2779 error = EINVAL; 2780 break; 2781 } 2782 RL_LOCK(sc); 2783 if (ifp->if_mtu != ifr->ifr_mtu) 2784 ifp->if_mtu = ifr->ifr_mtu; 2785 if (ifp->if_mtu > RL_TSO_MTU && 2786 (ifp->if_capenable & IFCAP_TSO4) != 0) { 2787 ifp->if_capenable &= ~IFCAP_TSO4; 2788 ifp->if_hwassist &= ~CSUM_TSO; 2789 } 2790 RL_UNLOCK(sc); 2791 break; 2792 case SIOCSIFFLAGS: 2793 RL_LOCK(sc); 2794 if ((ifp->if_flags & IFF_UP) != 0) { 2795 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2796 if (((ifp->if_flags ^ sc->rl_if_flags) 2797 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2798 re_set_rxmode(sc); 2799 } else 2800 re_init_locked(sc); 2801 } else { 2802 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2803 re_stop(sc); 2804 } 2805 sc->rl_if_flags = ifp->if_flags; 2806 RL_UNLOCK(sc); 2807 break; 2808 case SIOCADDMULTI: 2809 case SIOCDELMULTI: 2810 RL_LOCK(sc); 2811 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2812 re_set_rxmode(sc); 2813 RL_UNLOCK(sc); 2814 break; 2815 case SIOCGIFMEDIA: 2816 case SIOCSIFMEDIA: 2817 mii = device_get_softc(sc->rl_miibus); 2818 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2819 break; 2820 case SIOCSIFCAP: 2821 { 2822 int mask, reinit; 2823 2824 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2825 reinit = 0; 2826 #ifdef DEVICE_POLLING 2827 if (mask & IFCAP_POLLING) { 2828 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2829 error = ether_poll_register(re_poll, ifp); 2830 if (error) 2831 return(error); 2832 RL_LOCK(sc); 2833 /* Disable interrupts */ 2834 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2835 ifp->if_capenable |= IFCAP_POLLING; 2836 RL_UNLOCK(sc); 2837 } else { 2838 error = ether_poll_deregister(ifp); 2839 /* Enable interrupts. */ 2840 RL_LOCK(sc); 2841 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2842 ifp->if_capenable &= ~IFCAP_POLLING; 2843 RL_UNLOCK(sc); 2844 } 2845 } 2846 #endif /* DEVICE_POLLING */ 2847 if (mask & IFCAP_HWCSUM) { 2848 ifp->if_capenable ^= IFCAP_HWCSUM; 2849 if (ifp->if_capenable & IFCAP_TXCSUM) 2850 ifp->if_hwassist |= RE_CSUM_FEATURES; 2851 else 2852 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 2853 reinit = 1; 2854 } 2855 if (mask & IFCAP_VLAN_HWTAGGING) { 2856 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2857 reinit = 1; 2858 } 2859 if (mask & IFCAP_TSO4) { 2860 ifp->if_capenable ^= IFCAP_TSO4; 2861 if ((IFCAP_TSO4 & ifp->if_capenable) && 2862 (IFCAP_TSO4 & ifp->if_capabilities)) 2863 ifp->if_hwassist |= CSUM_TSO; 2864 else 2865 ifp->if_hwassist &= ~CSUM_TSO; 2866 if (ifp->if_mtu > RL_TSO_MTU && 2867 (ifp->if_capenable & IFCAP_TSO4) != 0) { 2868 ifp->if_capenable &= ~IFCAP_TSO4; 2869 ifp->if_hwassist &= ~CSUM_TSO; 2870 } 2871 } 2872 if ((mask & IFCAP_WOL) != 0 && 2873 (ifp->if_capabilities & IFCAP_WOL) != 0) { 2874 if ((mask & IFCAP_WOL_UCAST) != 0) 2875 ifp->if_capenable ^= IFCAP_WOL_UCAST; 2876 if ((mask & IFCAP_WOL_MCAST) != 0) 2877 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2878 if ((mask & IFCAP_WOL_MAGIC) != 0) 2879 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2880 } 2881 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) { 2882 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2883 re_init(sc); 2884 } 2885 VLAN_CAPABILITIES(ifp); 2886 } 2887 break; 2888 default: 2889 error = ether_ioctl(ifp, command, data); 2890 break; 2891 } 2892 2893 return (error); 2894 } 2895 2896 static void 2897 re_watchdog(struct rl_softc *sc) 2898 { 2899 struct ifnet *ifp; 2900 2901 RL_LOCK_ASSERT(sc); 2902 2903 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 2904 return; 2905 2906 ifp = sc->rl_ifp; 2907 re_txeof(sc); 2908 if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) { 2909 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 2910 "-- recovering\n"); 2911 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2912 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2913 return; 2914 } 2915 2916 if_printf(ifp, "watchdog timeout\n"); 2917 ifp->if_oerrors++; 2918 2919 re_rxeof(sc, NULL); 2920 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2921 re_init_locked(sc); 2922 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2923 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2924 } 2925 2926 /* 2927 * Stop the adapter and free any mbufs allocated to the 2928 * RX and TX lists. 2929 */ 2930 static void 2931 re_stop(struct rl_softc *sc) 2932 { 2933 int i; 2934 struct ifnet *ifp; 2935 struct rl_txdesc *txd; 2936 struct rl_rxdesc *rxd; 2937 2938 RL_LOCK_ASSERT(sc); 2939 2940 ifp = sc->rl_ifp; 2941 2942 sc->rl_watchdog_timer = 0; 2943 callout_stop(&sc->rl_stat_callout); 2944 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2945 2946 if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0) 2947 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB | 2948 RL_CMD_RX_ENB); 2949 else 2950 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2951 DELAY(1000); 2952 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2953 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 2954 2955 if (sc->rl_head != NULL) { 2956 m_freem(sc->rl_head); 2957 sc->rl_head = sc->rl_tail = NULL; 2958 } 2959 2960 /* Free the TX list buffers. */ 2961 2962 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 2963 txd = &sc->rl_ldata.rl_tx_desc[i]; 2964 if (txd->tx_m != NULL) { 2965 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2966 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2967 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2968 txd->tx_dmamap); 2969 m_freem(txd->tx_m); 2970 txd->tx_m = NULL; 2971 } 2972 } 2973 2974 /* Free the RX list buffers. */ 2975 2976 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2977 rxd = &sc->rl_ldata.rl_rx_desc[i]; 2978 if (rxd->rx_m != NULL) { 2979 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2980 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2981 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 2982 rxd->rx_dmamap); 2983 m_freem(rxd->rx_m); 2984 rxd->rx_m = NULL; 2985 } 2986 } 2987 } 2988 2989 /* 2990 * Device suspend routine. Stop the interface and save some PCI 2991 * settings in case the BIOS doesn't restore them properly on 2992 * resume. 2993 */ 2994 static int 2995 re_suspend(device_t dev) 2996 { 2997 struct rl_softc *sc; 2998 2999 sc = device_get_softc(dev); 3000 3001 RL_LOCK(sc); 3002 re_stop(sc); 3003 re_setwol(sc); 3004 sc->suspended = 1; 3005 RL_UNLOCK(sc); 3006 3007 return (0); 3008 } 3009 3010 /* 3011 * Device resume routine. Restore some PCI settings in case the BIOS 3012 * doesn't, re-enable busmastering, and restart the interface if 3013 * appropriate. 3014 */ 3015 static int 3016 re_resume(device_t dev) 3017 { 3018 struct rl_softc *sc; 3019 struct ifnet *ifp; 3020 3021 sc = device_get_softc(dev); 3022 3023 RL_LOCK(sc); 3024 3025 ifp = sc->rl_ifp; 3026 /* Take controller out of sleep mode. */ 3027 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3028 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3029 CSR_WRITE_1(sc, RL_GPIO, 3030 CSR_READ_1(sc, RL_GPIO) | 0x01); 3031 } 3032 3033 /* 3034 * Clear WOL matching such that normal Rx filtering 3035 * wouldn't interfere with WOL patterns. 3036 */ 3037 re_clrwol(sc); 3038 3039 /* reinitialize interface if necessary */ 3040 if (ifp->if_flags & IFF_UP) 3041 re_init_locked(sc); 3042 3043 sc->suspended = 0; 3044 RL_UNLOCK(sc); 3045 3046 return (0); 3047 } 3048 3049 /* 3050 * Stop all chip I/O so that the kernel's probe routines don't 3051 * get confused by errant DMAs when rebooting. 3052 */ 3053 static int 3054 re_shutdown(device_t dev) 3055 { 3056 struct rl_softc *sc; 3057 3058 sc = device_get_softc(dev); 3059 3060 RL_LOCK(sc); 3061 re_stop(sc); 3062 /* 3063 * Mark interface as down since otherwise we will panic if 3064 * interrupt comes in later on, which can happen in some 3065 * cases. 3066 */ 3067 sc->rl_ifp->if_flags &= ~IFF_UP; 3068 re_setwol(sc); 3069 RL_UNLOCK(sc); 3070 3071 return (0); 3072 } 3073 3074 static void 3075 re_setwol(struct rl_softc *sc) 3076 { 3077 struct ifnet *ifp; 3078 int pmc; 3079 uint16_t pmstat; 3080 uint8_t v; 3081 3082 RL_LOCK_ASSERT(sc); 3083 3084 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3085 return; 3086 3087 ifp = sc->rl_ifp; 3088 /* Put controller into sleep mode. */ 3089 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3090 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3091 CSR_WRITE_1(sc, RL_GPIO, 3092 CSR_READ_1(sc, RL_GPIO) & ~0x01); 3093 } 3094 if ((ifp->if_capenable & IFCAP_WOL) != 0 && 3095 (sc->rl_flags & RL_FLAG_WOLRXENB) != 0) 3096 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB); 3097 /* Enable config register write. */ 3098 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3099 3100 /* Enable PME. */ 3101 v = CSR_READ_1(sc, RL_CFG1); 3102 v &= ~RL_CFG1_PME; 3103 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3104 v |= RL_CFG1_PME; 3105 CSR_WRITE_1(sc, RL_CFG1, v); 3106 3107 v = CSR_READ_1(sc, RL_CFG3); 3108 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3109 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3110 v |= RL_CFG3_WOL_MAGIC; 3111 CSR_WRITE_1(sc, RL_CFG3, v); 3112 3113 /* Config register write done. */ 3114 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3115 3116 v = CSR_READ_1(sc, RL_CFG5); 3117 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3118 v &= ~RL_CFG5_WOL_LANWAKE; 3119 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 3120 v |= RL_CFG5_WOL_UCAST; 3121 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 3122 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 3123 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3124 v |= RL_CFG5_WOL_LANWAKE; 3125 CSR_WRITE_1(sc, RL_CFG5, v); 3126 3127 /* 3128 * It seems that hardware resets its link speed to 100Mbps in 3129 * power down mode so switching to 100Mbps in driver is not 3130 * needed. 3131 */ 3132 3133 /* Request PME if WOL is requested. */ 3134 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 3135 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3136 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3137 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3138 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 3139 } 3140 3141 static void 3142 re_clrwol(struct rl_softc *sc) 3143 { 3144 int pmc; 3145 uint8_t v; 3146 3147 RL_LOCK_ASSERT(sc); 3148 3149 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3150 return; 3151 3152 /* Enable config register write. */ 3153 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3154 3155 v = CSR_READ_1(sc, RL_CFG3); 3156 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3157 CSR_WRITE_1(sc, RL_CFG3, v); 3158 3159 /* Config register write done. */ 3160 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3161 3162 v = CSR_READ_1(sc, RL_CFG5); 3163 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3164 v &= ~RL_CFG5_WOL_LANWAKE; 3165 CSR_WRITE_1(sc, RL_CFG5, v); 3166 } 3167