1 /*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44 /* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111 #ifdef HAVE_KERNEL_OPTION_HEADERS 112 #include "opt_device_polling.h" 113 #endif 114 115 #include <sys/param.h> 116 #include <sys/endian.h> 117 #include <sys/systm.h> 118 #include <sys/sockio.h> 119 #include <sys/mbuf.h> 120 #include <sys/malloc.h> 121 #include <sys/module.h> 122 #include <sys/kernel.h> 123 #include <sys/socket.h> 124 #include <sys/lock.h> 125 #include <sys/mutex.h> 126 #include <sys/taskqueue.h> 127 128 #include <net/if.h> 129 #include <net/if_arp.h> 130 #include <net/ethernet.h> 131 #include <net/if_dl.h> 132 #include <net/if_media.h> 133 #include <net/if_types.h> 134 #include <net/if_vlan_var.h> 135 136 #include <net/bpf.h> 137 138 #include <machine/bus.h> 139 #include <machine/resource.h> 140 #include <sys/bus.h> 141 #include <sys/rman.h> 142 143 #include <dev/mii/mii.h> 144 #include <dev/mii/miivar.h> 145 146 #include <dev/pci/pcireg.h> 147 #include <dev/pci/pcivar.h> 148 149 #include <pci/if_rlreg.h> 150 151 MODULE_DEPEND(re, pci, 1, 1, 1); 152 MODULE_DEPEND(re, ether, 1, 1, 1); 153 MODULE_DEPEND(re, miibus, 1, 1, 1); 154 155 /* "device miibus" required. See GENERIC if you get errors here. */ 156 #include "miibus_if.h" 157 158 /* Tunables. */ 159 static int msi_disable = 1; 160 TUNABLE_INT("hw.re.msi_disable", &msi_disable); 161 162 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 163 164 /* 165 * Various supported device vendors/types and their names. 166 */ 167 static struct rl_type re_devs[] = { 168 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0, 169 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 170 { RT_VENDORID, RT_DEVICEID_8139, 0, 171 "RealTek 8139C+ 10/100BaseTX" }, 172 { RT_VENDORID, RT_DEVICEID_8101E, 0, 173 "RealTek 8101E/8102E/8102EL PCIe 10/100baseTX" }, 174 { RT_VENDORID, RT_DEVICEID_8168, 0, 175 "RealTek 8168/8168B/8168C/8168CP/8168D/8111B/8111C/8111CP PCIe " 176 "Gigabit Ethernet" }, 177 { RT_VENDORID, RT_DEVICEID_8169, 0, 178 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" }, 179 { RT_VENDORID, RT_DEVICEID_8169SC, 0, 180 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 181 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0, 182 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 183 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0, 184 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 185 { USR_VENDORID, USR_DEVICEID_997902, 0, 186 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 187 }; 188 189 static struct rl_hwrev re_hwrevs[] = { 190 { RL_HWREV_8139, RL_8139, "" }, 191 { RL_HWREV_8139A, RL_8139, "A" }, 192 { RL_HWREV_8139AG, RL_8139, "A-G" }, 193 { RL_HWREV_8139B, RL_8139, "B" }, 194 { RL_HWREV_8130, RL_8139, "8130" }, 195 { RL_HWREV_8139C, RL_8139, "C" }, 196 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 197 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 198 { RL_HWREV_8168_SPIN1, RL_8169, "8168"}, 199 { RL_HWREV_8169, RL_8169, "8169"}, 200 { RL_HWREV_8169S, RL_8169, "8169S"}, 201 { RL_HWREV_8110S, RL_8169, "8110S"}, 202 { RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB"}, 203 { RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC"}, 204 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL"}, 205 { RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC"}, 206 { RL_HWREV_8100, RL_8139, "8100"}, 207 { RL_HWREV_8101, RL_8139, "8101"}, 208 { RL_HWREV_8100E, RL_8169, "8100E"}, 209 { RL_HWREV_8101E, RL_8169, "8101E"}, 210 { RL_HWREV_8102E, RL_8169, "8102E"}, 211 { RL_HWREV_8102EL, RL_8169, "8102EL"}, 212 { RL_HWREV_8168_SPIN2, RL_8169, "8168"}, 213 { RL_HWREV_8168_SPIN3, RL_8169, "8168"}, 214 { RL_HWREV_8168C, RL_8169, "8168C/8111C"}, 215 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C"}, 216 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP"}, 217 { RL_HWREV_8168D, RL_8169, "8168D"}, 218 { 0, 0, NULL } 219 }; 220 221 static int re_probe (device_t); 222 static int re_attach (device_t); 223 static int re_detach (device_t); 224 225 static int re_encap (struct rl_softc *, struct mbuf **); 226 227 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 228 static int re_allocmem (device_t, struct rl_softc *); 229 static __inline void re_discard_rxbuf 230 (struct rl_softc *, int); 231 static int re_newbuf (struct rl_softc *, int); 232 static int re_rx_list_init (struct rl_softc *); 233 static int re_tx_list_init (struct rl_softc *); 234 #ifdef RE_FIXUP_RX 235 static __inline void re_fixup_rx 236 (struct mbuf *); 237 #endif 238 static int re_rxeof (struct rl_softc *); 239 static void re_txeof (struct rl_softc *); 240 #ifdef DEVICE_POLLING 241 static void re_poll (struct ifnet *, enum poll_cmd, int); 242 static void re_poll_locked (struct ifnet *, enum poll_cmd, int); 243 #endif 244 static int re_intr (void *); 245 static void re_tick (void *); 246 static void re_tx_task (void *, int); 247 static void re_int_task (void *, int); 248 static void re_start (struct ifnet *); 249 static int re_ioctl (struct ifnet *, u_long, caddr_t); 250 static void re_init (void *); 251 static void re_init_locked (struct rl_softc *); 252 static void re_stop (struct rl_softc *); 253 static void re_watchdog (struct rl_softc *); 254 static int re_suspend (device_t); 255 static int re_resume (device_t); 256 static int re_shutdown (device_t); 257 static int re_ifmedia_upd (struct ifnet *); 258 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 259 260 static void re_eeprom_putbyte (struct rl_softc *, int); 261 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 262 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 263 static int re_gmii_readreg (device_t, int, int); 264 static int re_gmii_writereg (device_t, int, int, int); 265 266 static int re_miibus_readreg (device_t, int, int); 267 static int re_miibus_writereg (device_t, int, int, int); 268 static void re_miibus_statchg (device_t); 269 270 static void re_set_rxmode (struct rl_softc *); 271 static void re_reset (struct rl_softc *); 272 static void re_setwol (struct rl_softc *); 273 static void re_clrwol (struct rl_softc *); 274 275 #ifdef RE_DIAG 276 static int re_diag (struct rl_softc *); 277 #endif 278 279 static device_method_t re_methods[] = { 280 /* Device interface */ 281 DEVMETHOD(device_probe, re_probe), 282 DEVMETHOD(device_attach, re_attach), 283 DEVMETHOD(device_detach, re_detach), 284 DEVMETHOD(device_suspend, re_suspend), 285 DEVMETHOD(device_resume, re_resume), 286 DEVMETHOD(device_shutdown, re_shutdown), 287 288 /* bus interface */ 289 DEVMETHOD(bus_print_child, bus_generic_print_child), 290 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 291 292 /* MII interface */ 293 DEVMETHOD(miibus_readreg, re_miibus_readreg), 294 DEVMETHOD(miibus_writereg, re_miibus_writereg), 295 DEVMETHOD(miibus_statchg, re_miibus_statchg), 296 297 { 0, 0 } 298 }; 299 300 static driver_t re_driver = { 301 "re", 302 re_methods, 303 sizeof(struct rl_softc) 304 }; 305 306 static devclass_t re_devclass; 307 308 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 309 DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0); 310 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 311 312 #define EE_SET(x) \ 313 CSR_WRITE_1(sc, RL_EECMD, \ 314 CSR_READ_1(sc, RL_EECMD) | x) 315 316 #define EE_CLR(x) \ 317 CSR_WRITE_1(sc, RL_EECMD, \ 318 CSR_READ_1(sc, RL_EECMD) & ~x) 319 320 /* 321 * Send a read command and address to the EEPROM, check for ACK. 322 */ 323 static void 324 re_eeprom_putbyte(struct rl_softc *sc, int addr) 325 { 326 int d, i; 327 328 d = addr | (RL_9346_READ << sc->rl_eewidth); 329 330 /* 331 * Feed in each bit and strobe the clock. 332 */ 333 334 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 335 if (d & i) { 336 EE_SET(RL_EE_DATAIN); 337 } else { 338 EE_CLR(RL_EE_DATAIN); 339 } 340 DELAY(100); 341 EE_SET(RL_EE_CLK); 342 DELAY(150); 343 EE_CLR(RL_EE_CLK); 344 DELAY(100); 345 } 346 } 347 348 /* 349 * Read a word of data stored in the EEPROM at address 'addr.' 350 */ 351 static void 352 re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest) 353 { 354 int i; 355 u_int16_t word = 0; 356 357 /* 358 * Send address of word we want to read. 359 */ 360 re_eeprom_putbyte(sc, addr); 361 362 /* 363 * Start reading bits from EEPROM. 364 */ 365 for (i = 0x8000; i; i >>= 1) { 366 EE_SET(RL_EE_CLK); 367 DELAY(100); 368 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 369 word |= i; 370 EE_CLR(RL_EE_CLK); 371 DELAY(100); 372 } 373 374 *dest = word; 375 } 376 377 /* 378 * Read a sequence of words from the EEPROM. 379 */ 380 static void 381 re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt) 382 { 383 int i; 384 u_int16_t word = 0, *ptr; 385 386 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 387 388 DELAY(100); 389 390 for (i = 0; i < cnt; i++) { 391 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 392 re_eeprom_getword(sc, off + i, &word); 393 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 394 ptr = (u_int16_t *)(dest + (i * 2)); 395 *ptr = word; 396 } 397 398 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 399 } 400 401 static int 402 re_gmii_readreg(device_t dev, int phy, int reg) 403 { 404 struct rl_softc *sc; 405 u_int32_t rval; 406 int i; 407 408 if (phy != 1) 409 return (0); 410 411 sc = device_get_softc(dev); 412 413 /* Let the rgephy driver read the GMEDIASTAT register */ 414 415 if (reg == RL_GMEDIASTAT) { 416 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 417 return (rval); 418 } 419 420 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 421 422 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 423 rval = CSR_READ_4(sc, RL_PHYAR); 424 if (rval & RL_PHYAR_BUSY) 425 break; 426 DELAY(100); 427 } 428 429 if (i == RL_PHY_TIMEOUT) { 430 device_printf(sc->rl_dev, "PHY read failed\n"); 431 return (0); 432 } 433 434 return (rval & RL_PHYAR_PHYDATA); 435 } 436 437 static int 438 re_gmii_writereg(device_t dev, int phy, int reg, int data) 439 { 440 struct rl_softc *sc; 441 u_int32_t rval; 442 int i; 443 444 sc = device_get_softc(dev); 445 446 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 447 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 448 449 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 450 rval = CSR_READ_4(sc, RL_PHYAR); 451 if (!(rval & RL_PHYAR_BUSY)) 452 break; 453 DELAY(100); 454 } 455 456 if (i == RL_PHY_TIMEOUT) { 457 device_printf(sc->rl_dev, "PHY write failed\n"); 458 return (0); 459 } 460 461 return (0); 462 } 463 464 static int 465 re_miibus_readreg(device_t dev, int phy, int reg) 466 { 467 struct rl_softc *sc; 468 u_int16_t rval = 0; 469 u_int16_t re8139_reg = 0; 470 471 sc = device_get_softc(dev); 472 473 if (sc->rl_type == RL_8169) { 474 rval = re_gmii_readreg(dev, phy, reg); 475 return (rval); 476 } 477 478 /* Pretend the internal PHY is only at address 0 */ 479 if (phy) { 480 return (0); 481 } 482 switch (reg) { 483 case MII_BMCR: 484 re8139_reg = RL_BMCR; 485 break; 486 case MII_BMSR: 487 re8139_reg = RL_BMSR; 488 break; 489 case MII_ANAR: 490 re8139_reg = RL_ANAR; 491 break; 492 case MII_ANER: 493 re8139_reg = RL_ANER; 494 break; 495 case MII_ANLPAR: 496 re8139_reg = RL_LPAR; 497 break; 498 case MII_PHYIDR1: 499 case MII_PHYIDR2: 500 return (0); 501 /* 502 * Allow the rlphy driver to read the media status 503 * register. If we have a link partner which does not 504 * support NWAY, this is the register which will tell 505 * us the results of parallel detection. 506 */ 507 case RL_MEDIASTAT: 508 rval = CSR_READ_1(sc, RL_MEDIASTAT); 509 return (rval); 510 default: 511 device_printf(sc->rl_dev, "bad phy register\n"); 512 return (0); 513 } 514 rval = CSR_READ_2(sc, re8139_reg); 515 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 516 /* 8139C+ has different bit layout. */ 517 rval &= ~(BMCR_LOOP | BMCR_ISO); 518 } 519 return (rval); 520 } 521 522 static int 523 re_miibus_writereg(device_t dev, int phy, int reg, int data) 524 { 525 struct rl_softc *sc; 526 u_int16_t re8139_reg = 0; 527 int rval = 0; 528 529 sc = device_get_softc(dev); 530 531 if (sc->rl_type == RL_8169) { 532 rval = re_gmii_writereg(dev, phy, reg, data); 533 return (rval); 534 } 535 536 /* Pretend the internal PHY is only at address 0 */ 537 if (phy) 538 return (0); 539 540 switch (reg) { 541 case MII_BMCR: 542 re8139_reg = RL_BMCR; 543 if (sc->rl_type == RL_8139CPLUS) { 544 /* 8139C+ has different bit layout. */ 545 data &= ~(BMCR_LOOP | BMCR_ISO); 546 } 547 break; 548 case MII_BMSR: 549 re8139_reg = RL_BMSR; 550 break; 551 case MII_ANAR: 552 re8139_reg = RL_ANAR; 553 break; 554 case MII_ANER: 555 re8139_reg = RL_ANER; 556 break; 557 case MII_ANLPAR: 558 re8139_reg = RL_LPAR; 559 break; 560 case MII_PHYIDR1: 561 case MII_PHYIDR2: 562 return (0); 563 break; 564 default: 565 device_printf(sc->rl_dev, "bad phy register\n"); 566 return (0); 567 } 568 CSR_WRITE_2(sc, re8139_reg, data); 569 return (0); 570 } 571 572 static void 573 re_miibus_statchg(device_t dev) 574 { 575 struct rl_softc *sc; 576 struct ifnet *ifp; 577 struct mii_data *mii; 578 579 sc = device_get_softc(dev); 580 mii = device_get_softc(sc->rl_miibus); 581 ifp = sc->rl_ifp; 582 if (mii == NULL || ifp == NULL || 583 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 584 return; 585 586 sc->rl_flags &= ~RL_FLAG_LINK; 587 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 588 (IFM_ACTIVE | IFM_AVALID)) { 589 switch (IFM_SUBTYPE(mii->mii_media_active)) { 590 case IFM_10_T: 591 case IFM_100_TX: 592 sc->rl_flags |= RL_FLAG_LINK; 593 break; 594 case IFM_1000_T: 595 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0) 596 break; 597 sc->rl_flags |= RL_FLAG_LINK; 598 break; 599 default: 600 break; 601 } 602 } 603 /* 604 * RealTek controllers does not provide any interface to 605 * Tx/Rx MACs for resolved speed, duplex and flow-control 606 * parameters. 607 */ 608 } 609 610 /* 611 * Set the RX configuration and 64-bit multicast hash filter. 612 */ 613 static void 614 re_set_rxmode(struct rl_softc *sc) 615 { 616 struct ifnet *ifp; 617 struct ifmultiaddr *ifma; 618 uint32_t hashes[2] = { 0, 0 }; 619 uint32_t h, rxfilt; 620 621 RL_LOCK_ASSERT(sc); 622 623 ifp = sc->rl_ifp; 624 625 rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD; 626 627 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 628 if (ifp->if_flags & IFF_PROMISC) 629 rxfilt |= RL_RXCFG_RX_ALLPHYS; 630 /* 631 * Unlike other hardwares, we have to explicitly set 632 * RL_RXCFG_RX_MULTI to receive multicast frames in 633 * promiscuous mode. 634 */ 635 rxfilt |= RL_RXCFG_RX_MULTI; 636 hashes[0] = hashes[1] = 0xffffffff; 637 goto done; 638 } 639 640 IF_ADDR_LOCK(ifp); 641 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 642 if (ifma->ifma_addr->sa_family != AF_LINK) 643 continue; 644 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 645 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 646 if (h < 32) 647 hashes[0] |= (1 << h); 648 else 649 hashes[1] |= (1 << (h - 32)); 650 } 651 IF_ADDR_UNLOCK(ifp); 652 653 if (hashes[0] != 0 || hashes[1] != 0) { 654 /* 655 * For some unfathomable reason, RealTek decided to 656 * reverse the order of the multicast hash registers 657 * in the PCI Express parts. This means we have to 658 * write the hash pattern in reverse order for those 659 * devices. 660 */ 661 if ((sc->rl_flags & RL_FLAG_PCIE) != 0) { 662 h = bswap32(hashes[0]); 663 hashes[0] = bswap32(hashes[1]); 664 hashes[1] = h; 665 } 666 rxfilt |= RL_RXCFG_RX_MULTI; 667 } 668 669 done: 670 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 671 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 672 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 673 } 674 675 static void 676 re_reset(struct rl_softc *sc) 677 { 678 int i; 679 680 RL_LOCK_ASSERT(sc); 681 682 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 683 684 for (i = 0; i < RL_TIMEOUT; i++) { 685 DELAY(10); 686 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 687 break; 688 } 689 if (i == RL_TIMEOUT) 690 device_printf(sc->rl_dev, "reset never completed!\n"); 691 692 if ((sc->rl_flags & RL_FLAG_MACRESET) != 0) 693 CSR_WRITE_1(sc, 0x82, 1); 694 if (sc->rl_hwrev == RL_HWREV_8169S) 695 re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0); 696 } 697 698 #ifdef RE_DIAG 699 700 /* 701 * The following routine is designed to test for a defect on some 702 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 703 * lines connected to the bus, however for a 32-bit only card, they 704 * should be pulled high. The result of this defect is that the 705 * NIC will not work right if you plug it into a 64-bit slot: DMA 706 * operations will be done with 64-bit transfers, which will fail 707 * because the 64-bit data lines aren't connected. 708 * 709 * There's no way to work around this (short of talking a soldering 710 * iron to the board), however we can detect it. The method we use 711 * here is to put the NIC into digital loopback mode, set the receiver 712 * to promiscuous mode, and then try to send a frame. We then compare 713 * the frame data we sent to what was received. If the data matches, 714 * then the NIC is working correctly, otherwise we know the user has 715 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 716 * slot. In the latter case, there's no way the NIC can work correctly, 717 * so we print out a message on the console and abort the device attach. 718 */ 719 720 static int 721 re_diag(struct rl_softc *sc) 722 { 723 struct ifnet *ifp = sc->rl_ifp; 724 struct mbuf *m0; 725 struct ether_header *eh; 726 struct rl_desc *cur_rx; 727 u_int16_t status; 728 u_int32_t rxstat; 729 int total_len, i, error = 0, phyaddr; 730 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 731 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 732 733 /* Allocate a single mbuf */ 734 MGETHDR(m0, M_DONTWAIT, MT_DATA); 735 if (m0 == NULL) 736 return (ENOBUFS); 737 738 RL_LOCK(sc); 739 740 /* 741 * Initialize the NIC in test mode. This sets the chip up 742 * so that it can send and receive frames, but performs the 743 * following special functions: 744 * - Puts receiver in promiscuous mode 745 * - Enables digital loopback mode 746 * - Leaves interrupts turned off 747 */ 748 749 ifp->if_flags |= IFF_PROMISC; 750 sc->rl_testmode = 1; 751 re_init_locked(sc); 752 sc->rl_flags |= RL_FLAG_LINK; 753 if (sc->rl_type == RL_8169) 754 phyaddr = 1; 755 else 756 phyaddr = 0; 757 758 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 759 for (i = 0; i < RL_TIMEOUT; i++) { 760 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 761 if (!(status & BMCR_RESET)) 762 break; 763 } 764 765 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 766 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 767 768 DELAY(100000); 769 770 /* Put some data in the mbuf */ 771 772 eh = mtod(m0, struct ether_header *); 773 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 774 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 775 eh->ether_type = htons(ETHERTYPE_IP); 776 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 777 778 /* 779 * Queue the packet, start transmission. 780 * Note: IF_HANDOFF() ultimately calls re_start() for us. 781 */ 782 783 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 784 RL_UNLOCK(sc); 785 /* XXX: re_diag must not be called when in ALTQ mode */ 786 IF_HANDOFF(&ifp->if_snd, m0, ifp); 787 RL_LOCK(sc); 788 m0 = NULL; 789 790 /* Wait for it to propagate through the chip */ 791 792 DELAY(100000); 793 for (i = 0; i < RL_TIMEOUT; i++) { 794 status = CSR_READ_2(sc, RL_ISR); 795 CSR_WRITE_2(sc, RL_ISR, status); 796 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 797 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 798 break; 799 DELAY(10); 800 } 801 802 if (i == RL_TIMEOUT) { 803 device_printf(sc->rl_dev, 804 "diagnostic failed, failed to receive packet in" 805 " loopback mode\n"); 806 error = EIO; 807 goto done; 808 } 809 810 /* 811 * The packet should have been dumped into the first 812 * entry in the RX DMA ring. Grab it from there. 813 */ 814 815 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 816 sc->rl_ldata.rl_rx_list_map, 817 BUS_DMASYNC_POSTREAD); 818 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 819 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 820 BUS_DMASYNC_POSTREAD); 821 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 822 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 823 824 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 825 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 826 eh = mtod(m0, struct ether_header *); 827 828 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 829 total_len = RL_RXBYTES(cur_rx); 830 rxstat = le32toh(cur_rx->rl_cmdstat); 831 832 if (total_len != ETHER_MIN_LEN) { 833 device_printf(sc->rl_dev, 834 "diagnostic failed, received short packet\n"); 835 error = EIO; 836 goto done; 837 } 838 839 /* Test that the received packet data matches what we sent. */ 840 841 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 842 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 843 ntohs(eh->ether_type) != ETHERTYPE_IP) { 844 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 845 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 846 dst, ":", src, ":", ETHERTYPE_IP); 847 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 848 eh->ether_dhost, ":", eh->ether_shost, ":", 849 ntohs(eh->ether_type)); 850 device_printf(sc->rl_dev, "You may have a defective 32-bit " 851 "NIC plugged into a 64-bit PCI slot.\n"); 852 device_printf(sc->rl_dev, "Please re-install the NIC in a " 853 "32-bit slot for proper operation.\n"); 854 device_printf(sc->rl_dev, "Read the re(4) man page for more " 855 "details.\n"); 856 error = EIO; 857 } 858 859 done: 860 /* Turn interface off, release resources */ 861 862 sc->rl_testmode = 0; 863 sc->rl_flags &= ~RL_FLAG_LINK; 864 ifp->if_flags &= ~IFF_PROMISC; 865 re_stop(sc); 866 if (m0 != NULL) 867 m_freem(m0); 868 869 RL_UNLOCK(sc); 870 871 return (error); 872 } 873 874 #endif 875 876 /* 877 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 878 * IDs against our list and return a device name if we find a match. 879 */ 880 static int 881 re_probe(device_t dev) 882 { 883 struct rl_type *t; 884 uint16_t devid, vendor; 885 uint16_t revid, sdevid; 886 int i; 887 888 vendor = pci_get_vendor(dev); 889 devid = pci_get_device(dev); 890 revid = pci_get_revid(dev); 891 sdevid = pci_get_subdevice(dev); 892 893 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 894 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 895 /* 896 * Only attach to rev. 3 of the Linksys EG1032 adapter. 897 * Rev. 2 is supported by sk(4). 898 */ 899 return (ENXIO); 900 } 901 } 902 903 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 904 if (revid != 0x20) { 905 /* 8139, let rl(4) take care of this device. */ 906 return (ENXIO); 907 } 908 } 909 910 t = re_devs; 911 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) { 912 if (vendor == t->rl_vid && devid == t->rl_did) { 913 device_set_desc(dev, t->rl_name); 914 return (BUS_PROBE_DEFAULT); 915 } 916 } 917 918 return (ENXIO); 919 } 920 921 /* 922 * Map a single buffer address. 923 */ 924 925 static void 926 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 927 { 928 bus_addr_t *addr; 929 930 if (error) 931 return; 932 933 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 934 addr = arg; 935 *addr = segs->ds_addr; 936 } 937 938 static int 939 re_allocmem(device_t dev, struct rl_softc *sc) 940 { 941 bus_size_t rx_list_size, tx_list_size; 942 int error; 943 int i; 944 945 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 946 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 947 948 /* 949 * Allocate the parent bus DMA tag appropriate for PCI. 950 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD 951 * register should be set. However some RealTek chips are known 952 * to be buggy on DAC handling, therefore disable DAC by limiting 953 * DMA address space to 32bit. PCIe variants of RealTek chips 954 * may not have the limitation but I took safer path. 955 */ 956 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 957 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 958 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 959 NULL, NULL, &sc->rl_parent_tag); 960 if (error) { 961 device_printf(dev, "could not allocate parent DMA tag\n"); 962 return (error); 963 } 964 965 /* 966 * Allocate map for TX mbufs. 967 */ 968 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 969 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 970 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 971 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 972 if (error) { 973 device_printf(dev, "could not allocate TX DMA tag\n"); 974 return (error); 975 } 976 977 /* 978 * Allocate map for RX mbufs. 979 */ 980 981 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 982 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 983 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 984 if (error) { 985 device_printf(dev, "could not allocate RX DMA tag\n"); 986 return (error); 987 } 988 989 /* 990 * Allocate map for TX descriptor list. 991 */ 992 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 993 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 994 NULL, tx_list_size, 1, tx_list_size, 0, 995 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 996 if (error) { 997 device_printf(dev, "could not allocate TX DMA ring tag\n"); 998 return (error); 999 } 1000 1001 /* Allocate DMA'able memory for the TX ring */ 1002 1003 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1004 (void **)&sc->rl_ldata.rl_tx_list, 1005 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1006 &sc->rl_ldata.rl_tx_list_map); 1007 if (error) { 1008 device_printf(dev, "could not allocate TX DMA ring\n"); 1009 return (error); 1010 } 1011 1012 /* Load the map for the TX ring. */ 1013 1014 sc->rl_ldata.rl_tx_list_addr = 0; 1015 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1016 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1017 tx_list_size, re_dma_map_addr, 1018 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1019 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 1020 device_printf(dev, "could not load TX DMA ring\n"); 1021 return (ENOMEM); 1022 } 1023 1024 /* Create DMA maps for TX buffers */ 1025 1026 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1027 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1028 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1029 if (error) { 1030 device_printf(dev, "could not create DMA map for TX\n"); 1031 return (error); 1032 } 1033 } 1034 1035 /* 1036 * Allocate map for RX descriptor list. 1037 */ 1038 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1039 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1040 NULL, rx_list_size, 1, rx_list_size, 0, 1041 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1042 if (error) { 1043 device_printf(dev, "could not create RX DMA ring tag\n"); 1044 return (error); 1045 } 1046 1047 /* Allocate DMA'able memory for the RX ring */ 1048 1049 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1050 (void **)&sc->rl_ldata.rl_rx_list, 1051 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1052 &sc->rl_ldata.rl_rx_list_map); 1053 if (error) { 1054 device_printf(dev, "could not allocate RX DMA ring\n"); 1055 return (error); 1056 } 1057 1058 /* Load the map for the RX ring. */ 1059 1060 sc->rl_ldata.rl_rx_list_addr = 0; 1061 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1062 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1063 rx_list_size, re_dma_map_addr, 1064 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1065 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1066 device_printf(dev, "could not load RX DMA ring\n"); 1067 return (ENOMEM); 1068 } 1069 1070 /* Create DMA maps for RX buffers */ 1071 1072 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1073 &sc->rl_ldata.rl_rx_sparemap); 1074 if (error) { 1075 device_printf(dev, "could not create spare DMA map for RX\n"); 1076 return (error); 1077 } 1078 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1079 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1080 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1081 if (error) { 1082 device_printf(dev, "could not create DMA map for RX\n"); 1083 return (error); 1084 } 1085 } 1086 1087 return (0); 1088 } 1089 1090 /* 1091 * Attach the interface. Allocate softc structures, do ifmedia 1092 * setup and ethernet/BPF attach. 1093 */ 1094 static int 1095 re_attach(device_t dev) 1096 { 1097 u_char eaddr[ETHER_ADDR_LEN]; 1098 u_int16_t as[ETHER_ADDR_LEN / 2]; 1099 struct rl_softc *sc; 1100 struct ifnet *ifp; 1101 struct rl_hwrev *hw_rev; 1102 int hwrev; 1103 u_int16_t devid, re_did = 0; 1104 int error = 0, rid, i; 1105 int msic, reg; 1106 uint8_t cfg; 1107 1108 sc = device_get_softc(dev); 1109 sc->rl_dev = dev; 1110 1111 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1112 MTX_DEF); 1113 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1114 1115 /* 1116 * Map control/status registers. 1117 */ 1118 pci_enable_busmaster(dev); 1119 1120 devid = pci_get_device(dev); 1121 /* Prefer memory space register mapping over IO space. */ 1122 sc->rl_res_id = PCIR_BAR(1); 1123 sc->rl_res_type = SYS_RES_MEMORY; 1124 /* RTL8168/8101E seems to use different BARs. */ 1125 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E) 1126 sc->rl_res_id = PCIR_BAR(2); 1127 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1128 &sc->rl_res_id, RF_ACTIVE); 1129 1130 if (sc->rl_res == NULL) { 1131 sc->rl_res_id = PCIR_BAR(0); 1132 sc->rl_res_type = SYS_RES_IOPORT; 1133 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1134 &sc->rl_res_id, RF_ACTIVE); 1135 if (sc->rl_res == NULL) { 1136 device_printf(dev, "couldn't map ports/memory\n"); 1137 error = ENXIO; 1138 goto fail; 1139 } 1140 } 1141 1142 sc->rl_btag = rman_get_bustag(sc->rl_res); 1143 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1144 1145 msic = 0; 1146 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 1147 sc->rl_flags |= RL_FLAG_PCIE; 1148 msic = pci_msi_count(dev); 1149 if (bootverbose) 1150 device_printf(dev, "MSI count : %d\n", msic); 1151 } 1152 if (msic == RL_MSI_MESSAGES && msi_disable == 0) { 1153 if (pci_alloc_msi(dev, &msic) == 0) { 1154 if (msic == RL_MSI_MESSAGES) { 1155 device_printf(dev, "Using %d MSI messages\n", 1156 msic); 1157 sc->rl_flags |= RL_FLAG_MSI; 1158 /* Explicitly set MSI enable bit. */ 1159 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1160 cfg = CSR_READ_1(sc, RL_CFG2); 1161 cfg |= RL_CFG2_MSI; 1162 CSR_WRITE_1(sc, RL_CFG2, cfg); 1163 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1164 } else 1165 pci_release_msi(dev); 1166 } 1167 } 1168 1169 /* Allocate interrupt */ 1170 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1171 rid = 0; 1172 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1173 RF_SHAREABLE | RF_ACTIVE); 1174 if (sc->rl_irq[0] == NULL) { 1175 device_printf(dev, "couldn't allocate IRQ resources\n"); 1176 error = ENXIO; 1177 goto fail; 1178 } 1179 } else { 1180 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1181 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1182 SYS_RES_IRQ, &rid, RF_ACTIVE); 1183 if (sc->rl_irq[i] == NULL) { 1184 device_printf(dev, 1185 "couldn't llocate IRQ resources for " 1186 "message %d\n", rid); 1187 error = ENXIO; 1188 goto fail; 1189 } 1190 } 1191 } 1192 1193 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1194 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1195 cfg = CSR_READ_1(sc, RL_CFG2); 1196 if ((cfg & RL_CFG2_MSI) != 0) { 1197 device_printf(dev, "turning off MSI enable bit.\n"); 1198 cfg &= ~RL_CFG2_MSI; 1199 CSR_WRITE_1(sc, RL_CFG2, cfg); 1200 } 1201 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1202 } 1203 1204 /* Reset the adapter. */ 1205 RL_LOCK(sc); 1206 re_reset(sc); 1207 RL_UNLOCK(sc); 1208 1209 hw_rev = re_hwrevs; 1210 hwrev = CSR_READ_4(sc, RL_TXCFG); 1211 switch (hwrev & 0x70000000) { 1212 case 0x00000000: 1213 case 0x10000000: 1214 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000); 1215 hwrev &= (RL_TXCFG_HWREV | 0x80000000); 1216 break; 1217 default: 1218 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000); 1219 hwrev &= RL_TXCFG_HWREV; 1220 break; 1221 } 1222 device_printf(dev, "MAC rev. 0x%08x\n", hwrev & 0x00700000); 1223 while (hw_rev->rl_desc != NULL) { 1224 if (hw_rev->rl_rev == hwrev) { 1225 sc->rl_type = hw_rev->rl_type; 1226 sc->rl_hwrev = hw_rev->rl_rev; 1227 break; 1228 } 1229 hw_rev++; 1230 } 1231 if (hw_rev->rl_desc == NULL) { 1232 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev); 1233 error = ENXIO; 1234 goto fail; 1235 } 1236 1237 switch (hw_rev->rl_rev) { 1238 case RL_HWREV_8139CPLUS: 1239 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_FASTETHER; 1240 break; 1241 case RL_HWREV_8100E: 1242 case RL_HWREV_8101E: 1243 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_PHYWAKE | 1244 RL_FLAG_FASTETHER; 1245 break; 1246 case RL_HWREV_8102E: 1247 case RL_HWREV_8102EL: 1248 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_PHYWAKE | 1249 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1250 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP; 1251 break; 1252 case RL_HWREV_8168_SPIN1: 1253 case RL_HWREV_8168_SPIN2: 1254 sc->rl_flags |= RL_FLAG_WOLRXENB; 1255 /* FALLTHROUGH */ 1256 case RL_HWREV_8168_SPIN3: 1257 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT; 1258 break; 1259 case RL_HWREV_8168C_SPIN2: 1260 sc->rl_flags |= RL_FLAG_MACSLEEP; 1261 /* FALLTHROUGH */ 1262 case RL_HWREV_8168C: 1263 if ((hwrev & 0x00700000) == 0x00200000) 1264 sc->rl_flags |= RL_FLAG_MACSLEEP; 1265 /* FALLTHROUGH */ 1266 case RL_HWREV_8168CP: 1267 case RL_HWREV_8168D: 1268 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1269 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP; 1270 /* 1271 * These controllers support jumbo frame but it seems 1272 * that enabling it requires touching additional magic 1273 * registers. Depending on MAC revisions some 1274 * controllers need to disable checksum offload. So 1275 * disable jumbo frame until I have better idea what 1276 * it really requires to make it support. 1277 * RTL8168C/CP : supports up to 6KB jumbo frame. 1278 * RTL8111C/CP : supports up to 9KB jumbo frame. 1279 */ 1280 sc->rl_flags |= RL_FLAG_NOJUMBO; 1281 break; 1282 case RL_HWREV_8169_8110SB: 1283 case RL_HWREV_8169_8110SBL: 1284 case RL_HWREV_8169_8110SC: 1285 case RL_HWREV_8169_8110SCE: 1286 sc->rl_flags |= RL_FLAG_PHYWAKE; 1287 /* FALLTHROUGH */ 1288 case RL_HWREV_8169: 1289 case RL_HWREV_8169S: 1290 case RL_HWREV_8110S: 1291 sc->rl_flags |= RL_FLAG_MACRESET; 1292 break; 1293 default: 1294 break; 1295 } 1296 1297 /* Enable PME. */ 1298 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1299 cfg = CSR_READ_1(sc, RL_CFG1); 1300 cfg |= RL_CFG1_PME; 1301 CSR_WRITE_1(sc, RL_CFG1, cfg); 1302 cfg = CSR_READ_1(sc, RL_CFG5); 1303 cfg &= RL_CFG5_PME_STS; 1304 CSR_WRITE_1(sc, RL_CFG5, cfg); 1305 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1306 1307 if ((sc->rl_flags & RL_FLAG_PAR) != 0) { 1308 /* 1309 * XXX Should have a better way to extract station 1310 * address from EEPROM. 1311 */ 1312 for (i = 0; i < ETHER_ADDR_LEN; i++) 1313 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1314 } else { 1315 sc->rl_eewidth = RL_9356_ADDR_LEN; 1316 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1317 if (re_did != 0x8129) 1318 sc->rl_eewidth = RL_9346_ADDR_LEN; 1319 1320 /* 1321 * Get station address from the EEPROM. 1322 */ 1323 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1324 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1325 as[i] = le16toh(as[i]); 1326 bcopy(as, eaddr, sizeof(eaddr)); 1327 } 1328 1329 if (sc->rl_type == RL_8169) { 1330 /* Set RX length mask and number of descriptors. */ 1331 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1332 sc->rl_txstart = RL_GTXSTART; 1333 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1334 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1335 } else { 1336 /* Set RX length mask and number of descriptors. */ 1337 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1338 sc->rl_txstart = RL_TXSTART; 1339 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1340 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1341 } 1342 1343 error = re_allocmem(dev, sc); 1344 if (error) 1345 goto fail; 1346 1347 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1348 if (ifp == NULL) { 1349 device_printf(dev, "can not if_alloc()\n"); 1350 error = ENOSPC; 1351 goto fail; 1352 } 1353 1354 /* Take controller out of deep sleep mode. */ 1355 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 1356 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 1357 CSR_WRITE_1(sc, RL_GPIO, 1358 CSR_READ_1(sc, RL_GPIO) | 0x01); 1359 else 1360 CSR_WRITE_1(sc, RL_GPIO, 1361 CSR_READ_1(sc, RL_GPIO) & ~0x01); 1362 } 1363 1364 /* Take PHY out of power down mode. */ 1365 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) { 1366 re_gmii_writereg(dev, 1, 0x1f, 0); 1367 re_gmii_writereg(dev, 1, 0x0e, 0); 1368 } 1369 1370 /* Do MII setup */ 1371 if (mii_phy_probe(dev, &sc->rl_miibus, 1372 re_ifmedia_upd, re_ifmedia_sts)) { 1373 device_printf(dev, "MII without any phy!\n"); 1374 error = ENXIO; 1375 goto fail; 1376 } 1377 1378 ifp->if_softc = sc; 1379 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1380 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1381 ifp->if_ioctl = re_ioctl; 1382 ifp->if_start = re_start; 1383 ifp->if_hwassist = RE_CSUM_FEATURES; 1384 ifp->if_capabilities = IFCAP_HWCSUM; 1385 ifp->if_capenable = ifp->if_capabilities; 1386 ifp->if_init = re_init; 1387 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1388 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1389 IFQ_SET_READY(&ifp->if_snd); 1390 1391 TASK_INIT(&sc->rl_txtask, 1, re_tx_task, ifp); 1392 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1393 1394 /* 1395 * XXX 1396 * Still have no idea how to make TSO work on 8168C, 8168CP, 1397 * 8111C and 8111CP. 1398 */ 1399 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 1400 ifp->if_hwassist |= CSUM_TSO; 1401 ifp->if_capabilities |= IFCAP_TSO4; 1402 } 1403 1404 /* 1405 * Call MI attach routine. 1406 */ 1407 ether_ifattach(ifp, eaddr); 1408 1409 /* VLAN capability setup */ 1410 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1411 if (ifp->if_capabilities & IFCAP_HWCSUM) 1412 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1413 /* Enable WOL if PM is supported. */ 1414 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, ®) == 0) 1415 ifp->if_capabilities |= IFCAP_WOL; 1416 ifp->if_capenable = ifp->if_capabilities; 1417 /* 1418 * Don't enable TSO by default. Under certain 1419 * circumtances the controller generated corrupted 1420 * packets in TSO size. 1421 */ 1422 ifp->if_hwassist &= ~CSUM_TSO; 1423 ifp->if_capenable &= ~IFCAP_TSO4; 1424 #ifdef DEVICE_POLLING 1425 ifp->if_capabilities |= IFCAP_POLLING; 1426 #endif 1427 /* 1428 * Tell the upper layer(s) we support long frames. 1429 * Must appear after the call to ether_ifattach() because 1430 * ether_ifattach() sets ifi_hdrlen to the default value. 1431 */ 1432 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1433 1434 #ifdef RE_DIAG 1435 /* 1436 * Perform hardware diagnostic on the original RTL8169. 1437 * Some 32-bit cards were incorrectly wired and would 1438 * malfunction if plugged into a 64-bit slot. 1439 */ 1440 1441 if (hwrev == RL_HWREV_8169) { 1442 error = re_diag(sc); 1443 if (error) { 1444 device_printf(dev, 1445 "attach aborted due to hardware diag failure\n"); 1446 ether_ifdetach(ifp); 1447 goto fail; 1448 } 1449 } 1450 #endif 1451 1452 /* Hook interrupt last to avoid having to lock softc */ 1453 if ((sc->rl_flags & RL_FLAG_MSI) == 0) 1454 error = bus_setup_intr(dev, sc->rl_irq[0], 1455 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1456 &sc->rl_intrhand[0]); 1457 else { 1458 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1459 error = bus_setup_intr(dev, sc->rl_irq[i], 1460 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1461 &sc->rl_intrhand[i]); 1462 if (error != 0) 1463 break; 1464 } 1465 } 1466 if (error) { 1467 device_printf(dev, "couldn't set up irq\n"); 1468 ether_ifdetach(ifp); 1469 } 1470 1471 fail: 1472 1473 if (error) 1474 re_detach(dev); 1475 1476 return (error); 1477 } 1478 1479 /* 1480 * Shutdown hardware and free up resources. This can be called any 1481 * time after the mutex has been initialized. It is called in both 1482 * the error case in attach and the normal detach case so it needs 1483 * to be careful about only freeing resources that have actually been 1484 * allocated. 1485 */ 1486 static int 1487 re_detach(device_t dev) 1488 { 1489 struct rl_softc *sc; 1490 struct ifnet *ifp; 1491 int i, rid; 1492 1493 sc = device_get_softc(dev); 1494 ifp = sc->rl_ifp; 1495 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1496 1497 /* These should only be active if attach succeeded */ 1498 if (device_is_attached(dev)) { 1499 #ifdef DEVICE_POLLING 1500 if (ifp->if_capenable & IFCAP_POLLING) 1501 ether_poll_deregister(ifp); 1502 #endif 1503 RL_LOCK(sc); 1504 #if 0 1505 sc->suspended = 1; 1506 #endif 1507 re_stop(sc); 1508 RL_UNLOCK(sc); 1509 callout_drain(&sc->rl_stat_callout); 1510 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1511 taskqueue_drain(taskqueue_fast, &sc->rl_txtask); 1512 /* 1513 * Force off the IFF_UP flag here, in case someone 1514 * still had a BPF descriptor attached to this 1515 * interface. If they do, ether_ifdetach() will cause 1516 * the BPF code to try and clear the promisc mode 1517 * flag, which will bubble down to re_ioctl(), 1518 * which will try to call re_init() again. This will 1519 * turn the NIC back on and restart the MII ticker, 1520 * which will panic the system when the kernel tries 1521 * to invoke the re_tick() function that isn't there 1522 * anymore. 1523 */ 1524 ifp->if_flags &= ~IFF_UP; 1525 ether_ifdetach(ifp); 1526 } 1527 if (sc->rl_miibus) 1528 device_delete_child(dev, sc->rl_miibus); 1529 bus_generic_detach(dev); 1530 1531 /* 1532 * The rest is resource deallocation, so we should already be 1533 * stopped here. 1534 */ 1535 1536 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1537 if (sc->rl_intrhand[i] != NULL) { 1538 bus_teardown_intr(dev, sc->rl_irq[i], 1539 sc->rl_intrhand[i]); 1540 sc->rl_intrhand[i] = NULL; 1541 } 1542 } 1543 if (ifp != NULL) 1544 if_free(ifp); 1545 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1546 if (sc->rl_irq[0] != NULL) { 1547 bus_release_resource(dev, SYS_RES_IRQ, 0, 1548 sc->rl_irq[0]); 1549 sc->rl_irq[0] = NULL; 1550 } 1551 } else { 1552 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1553 if (sc->rl_irq[i] != NULL) { 1554 bus_release_resource(dev, SYS_RES_IRQ, rid, 1555 sc->rl_irq[i]); 1556 sc->rl_irq[i] = NULL; 1557 } 1558 } 1559 pci_release_msi(dev); 1560 } 1561 if (sc->rl_res) 1562 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, 1563 sc->rl_res); 1564 1565 /* Unload and free the RX DMA ring memory and map */ 1566 1567 if (sc->rl_ldata.rl_rx_list_tag) { 1568 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1569 sc->rl_ldata.rl_rx_list_map); 1570 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1571 sc->rl_ldata.rl_rx_list, 1572 sc->rl_ldata.rl_rx_list_map); 1573 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1574 } 1575 1576 /* Unload and free the TX DMA ring memory and map */ 1577 1578 if (sc->rl_ldata.rl_tx_list_tag) { 1579 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1580 sc->rl_ldata.rl_tx_list_map); 1581 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1582 sc->rl_ldata.rl_tx_list, 1583 sc->rl_ldata.rl_tx_list_map); 1584 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1585 } 1586 1587 /* Destroy all the RX and TX buffer maps */ 1588 1589 if (sc->rl_ldata.rl_tx_mtag) { 1590 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1591 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1592 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1593 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1594 } 1595 if (sc->rl_ldata.rl_rx_mtag) { 1596 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) 1597 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1598 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1599 if (sc->rl_ldata.rl_rx_sparemap) 1600 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1601 sc->rl_ldata.rl_rx_sparemap); 1602 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1603 } 1604 1605 /* Unload and free the stats buffer and map */ 1606 1607 if (sc->rl_ldata.rl_stag) { 1608 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1609 sc->rl_ldata.rl_rx_list_map); 1610 bus_dmamem_free(sc->rl_ldata.rl_stag, 1611 sc->rl_ldata.rl_stats, 1612 sc->rl_ldata.rl_smap); 1613 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1614 } 1615 1616 if (sc->rl_parent_tag) 1617 bus_dma_tag_destroy(sc->rl_parent_tag); 1618 1619 mtx_destroy(&sc->rl_mtx); 1620 1621 return (0); 1622 } 1623 1624 static __inline void 1625 re_discard_rxbuf(struct rl_softc *sc, int idx) 1626 { 1627 struct rl_desc *desc; 1628 struct rl_rxdesc *rxd; 1629 uint32_t cmdstat; 1630 1631 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1632 desc = &sc->rl_ldata.rl_rx_list[idx]; 1633 desc->rl_vlanctl = 0; 1634 cmdstat = rxd->rx_size; 1635 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1636 cmdstat |= RL_RDESC_CMD_EOR; 1637 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1638 } 1639 1640 static int 1641 re_newbuf(struct rl_softc *sc, int idx) 1642 { 1643 struct mbuf *m; 1644 struct rl_rxdesc *rxd; 1645 bus_dma_segment_t segs[1]; 1646 bus_dmamap_t map; 1647 struct rl_desc *desc; 1648 uint32_t cmdstat; 1649 int error, nsegs; 1650 1651 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1652 if (m == NULL) 1653 return (ENOBUFS); 1654 1655 m->m_len = m->m_pkthdr.len = MCLBYTES; 1656 #ifdef RE_FIXUP_RX 1657 /* 1658 * This is part of an evil trick to deal with non-x86 platforms. 1659 * The RealTek chip requires RX buffers to be aligned on 64-bit 1660 * boundaries, but that will hose non-x86 machines. To get around 1661 * this, we leave some empty space at the start of each buffer 1662 * and for non-x86 hosts, we copy the buffer back six bytes 1663 * to achieve word alignment. This is slightly more efficient 1664 * than allocating a new buffer, copying the contents, and 1665 * discarding the old buffer. 1666 */ 1667 m_adj(m, RE_ETHER_ALIGN); 1668 #endif 1669 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1670 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1671 if (error != 0) { 1672 m_freem(m); 1673 return (ENOBUFS); 1674 } 1675 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1676 1677 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1678 if (rxd->rx_m != NULL) { 1679 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1680 BUS_DMASYNC_POSTREAD); 1681 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1682 } 1683 1684 rxd->rx_m = m; 1685 map = rxd->rx_dmamap; 1686 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1687 rxd->rx_size = segs[0].ds_len; 1688 sc->rl_ldata.rl_rx_sparemap = map; 1689 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1690 BUS_DMASYNC_PREREAD); 1691 1692 desc = &sc->rl_ldata.rl_rx_list[idx]; 1693 desc->rl_vlanctl = 0; 1694 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1695 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1696 cmdstat = segs[0].ds_len; 1697 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1698 cmdstat |= RL_RDESC_CMD_EOR; 1699 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1700 1701 return (0); 1702 } 1703 1704 #ifdef RE_FIXUP_RX 1705 static __inline void 1706 re_fixup_rx(struct mbuf *m) 1707 { 1708 int i; 1709 uint16_t *src, *dst; 1710 1711 src = mtod(m, uint16_t *); 1712 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1713 1714 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1715 *dst++ = *src++; 1716 1717 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1718 } 1719 #endif 1720 1721 static int 1722 re_tx_list_init(struct rl_softc *sc) 1723 { 1724 struct rl_desc *desc; 1725 int i; 1726 1727 RL_LOCK_ASSERT(sc); 1728 1729 bzero(sc->rl_ldata.rl_tx_list, 1730 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 1731 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1732 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 1733 /* Set EOR. */ 1734 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 1735 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 1736 1737 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1738 sc->rl_ldata.rl_tx_list_map, 1739 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1740 1741 sc->rl_ldata.rl_tx_prodidx = 0; 1742 sc->rl_ldata.rl_tx_considx = 0; 1743 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 1744 1745 return (0); 1746 } 1747 1748 static int 1749 re_rx_list_init(struct rl_softc *sc) 1750 { 1751 int error, i; 1752 1753 bzero(sc->rl_ldata.rl_rx_list, 1754 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 1755 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1756 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 1757 if ((error = re_newbuf(sc, i)) != 0) 1758 return (error); 1759 } 1760 1761 /* Flush the RX descriptors */ 1762 1763 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1764 sc->rl_ldata.rl_rx_list_map, 1765 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1766 1767 sc->rl_ldata.rl_rx_prodidx = 0; 1768 sc->rl_head = sc->rl_tail = NULL; 1769 1770 return (0); 1771 } 1772 1773 /* 1774 * RX handler for C+ and 8169. For the gigE chips, we support 1775 * the reception of jumbo frames that have been fragmented 1776 * across multiple 2K mbuf cluster buffers. 1777 */ 1778 static int 1779 re_rxeof(struct rl_softc *sc) 1780 { 1781 struct mbuf *m; 1782 struct ifnet *ifp; 1783 int i, total_len; 1784 struct rl_desc *cur_rx; 1785 u_int32_t rxstat, rxvlan; 1786 int maxpkt = 16; 1787 1788 RL_LOCK_ASSERT(sc); 1789 1790 ifp = sc->rl_ifp; 1791 1792 /* Invalidate the descriptor memory */ 1793 1794 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1795 sc->rl_ldata.rl_rx_list_map, 1796 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1797 1798 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 1799 i = RL_RX_DESC_NXT(sc, i)) { 1800 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1801 rxstat = le32toh(cur_rx->rl_cmdstat); 1802 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 1803 break; 1804 total_len = rxstat & sc->rl_rxlenmask; 1805 rxvlan = le32toh(cur_rx->rl_vlanctl); 1806 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 1807 1808 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1809 if (re_newbuf(sc, i) != 0) { 1810 /* 1811 * If this is part of a multi-fragment packet, 1812 * discard all the pieces. 1813 */ 1814 if (sc->rl_head != NULL) { 1815 m_freem(sc->rl_head); 1816 sc->rl_head = sc->rl_tail = NULL; 1817 } 1818 re_discard_rxbuf(sc, i); 1819 continue; 1820 } 1821 m->m_len = RE_RX_DESC_BUFLEN; 1822 if (sc->rl_head == NULL) 1823 sc->rl_head = sc->rl_tail = m; 1824 else { 1825 m->m_flags &= ~M_PKTHDR; 1826 sc->rl_tail->m_next = m; 1827 sc->rl_tail = m; 1828 } 1829 continue; 1830 } 1831 1832 /* 1833 * NOTE: for the 8139C+, the frame length field 1834 * is always 12 bits in size, but for the gigE chips, 1835 * it is 13 bits (since the max RX frame length is 16K). 1836 * Unfortunately, all 32 bits in the status word 1837 * were already used, so to make room for the extra 1838 * length bit, RealTek took out the 'frame alignment 1839 * error' bit and shifted the other status bits 1840 * over one slot. The OWN, EOR, FS and LS bits are 1841 * still in the same places. We have already extracted 1842 * the frame length and checked the OWN bit, so rather 1843 * than using an alternate bit mapping, we shift the 1844 * status bits one space to the right so we can evaluate 1845 * them using the 8169 status as though it was in the 1846 * same format as that of the 8139C+. 1847 */ 1848 if (sc->rl_type == RL_8169) 1849 rxstat >>= 1; 1850 1851 /* 1852 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 1853 * set, but if CRC is clear, it will still be a valid frame. 1854 */ 1855 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 && 1856 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) { 1857 ifp->if_ierrors++; 1858 /* 1859 * If this is part of a multi-fragment packet, 1860 * discard all the pieces. 1861 */ 1862 if (sc->rl_head != NULL) { 1863 m_freem(sc->rl_head); 1864 sc->rl_head = sc->rl_tail = NULL; 1865 } 1866 re_discard_rxbuf(sc, i); 1867 continue; 1868 } 1869 1870 /* 1871 * If allocating a replacement mbuf fails, 1872 * reload the current one. 1873 */ 1874 1875 if (re_newbuf(sc, i) != 0) { 1876 ifp->if_iqdrops++; 1877 if (sc->rl_head != NULL) { 1878 m_freem(sc->rl_head); 1879 sc->rl_head = sc->rl_tail = NULL; 1880 } 1881 re_discard_rxbuf(sc, i); 1882 continue; 1883 } 1884 1885 if (sc->rl_head != NULL) { 1886 m->m_len = total_len % RE_RX_DESC_BUFLEN; 1887 if (m->m_len == 0) 1888 m->m_len = RE_RX_DESC_BUFLEN; 1889 /* 1890 * Special case: if there's 4 bytes or less 1891 * in this buffer, the mbuf can be discarded: 1892 * the last 4 bytes is the CRC, which we don't 1893 * care about anyway. 1894 */ 1895 if (m->m_len <= ETHER_CRC_LEN) { 1896 sc->rl_tail->m_len -= 1897 (ETHER_CRC_LEN - m->m_len); 1898 m_freem(m); 1899 } else { 1900 m->m_len -= ETHER_CRC_LEN; 1901 m->m_flags &= ~M_PKTHDR; 1902 sc->rl_tail->m_next = m; 1903 } 1904 m = sc->rl_head; 1905 sc->rl_head = sc->rl_tail = NULL; 1906 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1907 } else 1908 m->m_pkthdr.len = m->m_len = 1909 (total_len - ETHER_CRC_LEN); 1910 1911 #ifdef RE_FIXUP_RX 1912 re_fixup_rx(m); 1913 #endif 1914 ifp->if_ipackets++; 1915 m->m_pkthdr.rcvif = ifp; 1916 1917 /* Do RX checksumming if enabled */ 1918 1919 if (ifp->if_capenable & IFCAP_RXCSUM) { 1920 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 1921 /* Check IP header checksum */ 1922 if (rxstat & RL_RDESC_STAT_PROTOID) 1923 m->m_pkthdr.csum_flags |= 1924 CSUM_IP_CHECKED; 1925 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1926 m->m_pkthdr.csum_flags |= 1927 CSUM_IP_VALID; 1928 1929 /* Check TCP/UDP checksum */ 1930 if ((RL_TCPPKT(rxstat) && 1931 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1932 (RL_UDPPKT(rxstat) && 1933 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1934 m->m_pkthdr.csum_flags |= 1935 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1936 m->m_pkthdr.csum_data = 0xffff; 1937 } 1938 } else { 1939 /* 1940 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP 1941 */ 1942 if ((rxstat & RL_RDESC_STAT_PROTOID) && 1943 (rxvlan & RL_RDESC_IPV4)) 1944 m->m_pkthdr.csum_flags |= 1945 CSUM_IP_CHECKED; 1946 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) && 1947 (rxvlan & RL_RDESC_IPV4)) 1948 m->m_pkthdr.csum_flags |= 1949 CSUM_IP_VALID; 1950 if (((rxstat & RL_RDESC_STAT_TCP) && 1951 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1952 ((rxstat & RL_RDESC_STAT_UDP) && 1953 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1954 m->m_pkthdr.csum_flags |= 1955 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1956 m->m_pkthdr.csum_data = 0xffff; 1957 } 1958 } 1959 } 1960 maxpkt--; 1961 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 1962 m->m_pkthdr.ether_vtag = 1963 bswap16((rxvlan & RL_RDESC_VLANCTL_DATA)); 1964 m->m_flags |= M_VLANTAG; 1965 } 1966 RL_UNLOCK(sc); 1967 (*ifp->if_input)(ifp, m); 1968 RL_LOCK(sc); 1969 } 1970 1971 /* Flush the RX DMA ring */ 1972 1973 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1974 sc->rl_ldata.rl_rx_list_map, 1975 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1976 1977 sc->rl_ldata.rl_rx_prodidx = i; 1978 1979 if (maxpkt) 1980 return(EAGAIN); 1981 1982 return(0); 1983 } 1984 1985 static void 1986 re_txeof(struct rl_softc *sc) 1987 { 1988 struct ifnet *ifp; 1989 struct rl_txdesc *txd; 1990 u_int32_t txstat; 1991 int cons; 1992 1993 cons = sc->rl_ldata.rl_tx_considx; 1994 if (cons == sc->rl_ldata.rl_tx_prodidx) 1995 return; 1996 1997 ifp = sc->rl_ifp; 1998 /* Invalidate the TX descriptor list */ 1999 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2000 sc->rl_ldata.rl_tx_list_map, 2001 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2002 2003 for (; cons != sc->rl_ldata.rl_tx_prodidx; 2004 cons = RL_TX_DESC_NXT(sc, cons)) { 2005 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 2006 if (txstat & RL_TDESC_STAT_OWN) 2007 break; 2008 /* 2009 * We only stash mbufs in the last descriptor 2010 * in a fragment chain, which also happens to 2011 * be the only place where the TX status bits 2012 * are valid. 2013 */ 2014 if (txstat & RL_TDESC_CMD_EOF) { 2015 txd = &sc->rl_ldata.rl_tx_desc[cons]; 2016 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2017 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2018 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2019 txd->tx_dmamap); 2020 KASSERT(txd->tx_m != NULL, 2021 ("%s: freeing NULL mbufs!", __func__)); 2022 m_freem(txd->tx_m); 2023 txd->tx_m = NULL; 2024 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 2025 RL_TDESC_STAT_COLCNT)) 2026 ifp->if_collisions++; 2027 if (txstat & RL_TDESC_STAT_TXERRSUM) 2028 ifp->if_oerrors++; 2029 else 2030 ifp->if_opackets++; 2031 } 2032 sc->rl_ldata.rl_tx_free++; 2033 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2034 } 2035 sc->rl_ldata.rl_tx_considx = cons; 2036 2037 /* No changes made to the TX ring, so no flush needed */ 2038 2039 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 2040 #ifdef RE_TX_MODERATION 2041 /* 2042 * If not all descriptors have been reaped yet, reload 2043 * the timer so that we will eventually get another 2044 * interrupt that will cause us to re-enter this routine. 2045 * This is done in case the transmitter has gone idle. 2046 */ 2047 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2048 #endif 2049 } else 2050 sc->rl_watchdog_timer = 0; 2051 } 2052 2053 static void 2054 re_tick(void *xsc) 2055 { 2056 struct rl_softc *sc; 2057 struct mii_data *mii; 2058 2059 sc = xsc; 2060 2061 RL_LOCK_ASSERT(sc); 2062 2063 mii = device_get_softc(sc->rl_miibus); 2064 mii_tick(mii); 2065 if ((sc->rl_flags & RL_FLAG_LINK) == 0) 2066 re_miibus_statchg(sc->rl_dev); 2067 re_watchdog(sc); 2068 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2069 } 2070 2071 #ifdef DEVICE_POLLING 2072 static void 2073 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2074 { 2075 struct rl_softc *sc = ifp->if_softc; 2076 2077 RL_LOCK(sc); 2078 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2079 re_poll_locked(ifp, cmd, count); 2080 RL_UNLOCK(sc); 2081 } 2082 2083 static void 2084 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2085 { 2086 struct rl_softc *sc = ifp->if_softc; 2087 2088 RL_LOCK_ASSERT(sc); 2089 2090 sc->rxcycles = count; 2091 re_rxeof(sc); 2092 re_txeof(sc); 2093 2094 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2095 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2096 2097 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2098 u_int16_t status; 2099 2100 status = CSR_READ_2(sc, RL_ISR); 2101 if (status == 0xffff) 2102 return; 2103 if (status) 2104 CSR_WRITE_2(sc, RL_ISR, status); 2105 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2106 (sc->rl_flags & RL_FLAG_PCIE)) 2107 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2108 2109 /* 2110 * XXX check behaviour on receiver stalls. 2111 */ 2112 2113 if (status & RL_ISR_SYSTEM_ERR) 2114 re_init_locked(sc); 2115 } 2116 } 2117 #endif /* DEVICE_POLLING */ 2118 2119 static int 2120 re_intr(void *arg) 2121 { 2122 struct rl_softc *sc; 2123 uint16_t status; 2124 2125 sc = arg; 2126 2127 status = CSR_READ_2(sc, RL_ISR); 2128 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2129 return (FILTER_STRAY); 2130 CSR_WRITE_2(sc, RL_IMR, 0); 2131 2132 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2133 2134 return (FILTER_HANDLED); 2135 } 2136 2137 static void 2138 re_int_task(void *arg, int npending) 2139 { 2140 struct rl_softc *sc; 2141 struct ifnet *ifp; 2142 u_int16_t status; 2143 int rval = 0; 2144 2145 sc = arg; 2146 ifp = sc->rl_ifp; 2147 2148 RL_LOCK(sc); 2149 2150 status = CSR_READ_2(sc, RL_ISR); 2151 CSR_WRITE_2(sc, RL_ISR, status); 2152 2153 if (sc->suspended || 2154 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2155 RL_UNLOCK(sc); 2156 return; 2157 } 2158 2159 #ifdef DEVICE_POLLING 2160 if (ifp->if_capenable & IFCAP_POLLING) { 2161 RL_UNLOCK(sc); 2162 return; 2163 } 2164 #endif 2165 2166 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2167 rval = re_rxeof(sc); 2168 2169 /* 2170 * Some chips will ignore a second TX request issued 2171 * while an existing transmission is in progress. If 2172 * the transmitter goes idle but there are still 2173 * packets waiting to be sent, we need to restart the 2174 * channel here to flush them out. This only seems to 2175 * be required with the PCIe devices. 2176 */ 2177 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2178 (sc->rl_flags & RL_FLAG_PCIE)) 2179 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2180 if (status & ( 2181 #ifdef RE_TX_MODERATION 2182 RL_ISR_TIMEOUT_EXPIRED| 2183 #else 2184 RL_ISR_TX_OK| 2185 #endif 2186 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2187 re_txeof(sc); 2188 2189 if (status & RL_ISR_SYSTEM_ERR) 2190 re_init_locked(sc); 2191 2192 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2193 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2194 2195 RL_UNLOCK(sc); 2196 2197 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2198 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2199 return; 2200 } 2201 2202 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2203 } 2204 2205 static int 2206 re_encap(struct rl_softc *sc, struct mbuf **m_head) 2207 { 2208 struct rl_txdesc *txd, *txd_last; 2209 bus_dma_segment_t segs[RL_NTXSEGS]; 2210 bus_dmamap_t map; 2211 struct mbuf *m_new; 2212 struct rl_desc *desc; 2213 int nsegs, prod; 2214 int i, error, ei, si; 2215 int padlen; 2216 uint32_t cmdstat, csum_flags, vlanctl; 2217 2218 RL_LOCK_ASSERT(sc); 2219 M_ASSERTPKTHDR((*m_head)); 2220 2221 /* 2222 * With some of the RealTek chips, using the checksum offload 2223 * support in conjunction with the autopadding feature results 2224 * in the transmission of corrupt frames. For example, if we 2225 * need to send a really small IP fragment that's less than 60 2226 * bytes in size, and IP header checksumming is enabled, the 2227 * resulting ethernet frame that appears on the wire will 2228 * have garbled payload. To work around this, if TX IP checksum 2229 * offload is enabled, we always manually pad short frames out 2230 * to the minimum ethernet frame size. 2231 */ 2232 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0 && 2233 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN && 2234 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) { 2235 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2236 if (M_WRITABLE(*m_head) == 0) { 2237 /* Get a writable copy. */ 2238 m_new = m_dup(*m_head, M_DONTWAIT); 2239 m_freem(*m_head); 2240 if (m_new == NULL) { 2241 *m_head = NULL; 2242 return (ENOBUFS); 2243 } 2244 *m_head = m_new; 2245 } 2246 if ((*m_head)->m_next != NULL || 2247 M_TRAILINGSPACE(*m_head) < padlen) { 2248 m_new = m_defrag(*m_head, M_DONTWAIT); 2249 if (m_new == NULL) { 2250 m_freem(*m_head); 2251 *m_head = NULL; 2252 return (ENOBUFS); 2253 } 2254 } else 2255 m_new = *m_head; 2256 2257 /* 2258 * Manually pad short frames, and zero the pad space 2259 * to avoid leaking data. 2260 */ 2261 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2262 m_new->m_pkthdr.len += padlen; 2263 m_new->m_len = m_new->m_pkthdr.len; 2264 *m_head = m_new; 2265 } 2266 2267 prod = sc->rl_ldata.rl_tx_prodidx; 2268 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2269 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2270 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2271 if (error == EFBIG) { 2272 m_new = m_collapse(*m_head, M_DONTWAIT, RL_NTXSEGS); 2273 if (m_new == NULL) { 2274 m_freem(*m_head); 2275 *m_head = NULL; 2276 return (ENOBUFS); 2277 } 2278 *m_head = m_new; 2279 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2280 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2281 if (error != 0) { 2282 m_freem(*m_head); 2283 *m_head = NULL; 2284 return (error); 2285 } 2286 } else if (error != 0) 2287 return (error); 2288 if (nsegs == 0) { 2289 m_freem(*m_head); 2290 *m_head = NULL; 2291 return (EIO); 2292 } 2293 2294 /* Check for number of available descriptors. */ 2295 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2296 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2297 return (ENOBUFS); 2298 } 2299 2300 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2301 BUS_DMASYNC_PREWRITE); 2302 2303 /* 2304 * Set up checksum offload. Note: checksum offload bits must 2305 * appear in all descriptors of a multi-descriptor transmit 2306 * attempt. This is according to testing done with an 8169 2307 * chip. This is a requirement. 2308 */ 2309 vlanctl = 0; 2310 csum_flags = 0; 2311 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) 2312 csum_flags = RL_TDESC_CMD_LGSEND | 2313 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2314 RL_TDESC_CMD_MSSVAL_SHIFT); 2315 else { 2316 /* 2317 * Unconditionally enable IP checksum if TCP or UDP 2318 * checksum is required. Otherwise, TCP/UDP checksum 2319 * does't make effects. 2320 */ 2321 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) { 2322 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2323 csum_flags |= RL_TDESC_CMD_IPCSUM; 2324 if (((*m_head)->m_pkthdr.csum_flags & 2325 CSUM_TCP) != 0) 2326 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2327 if (((*m_head)->m_pkthdr.csum_flags & 2328 CSUM_UDP) != 0) 2329 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2330 } else { 2331 vlanctl |= RL_TDESC_CMD_IPCSUMV2; 2332 if (((*m_head)->m_pkthdr.csum_flags & 2333 CSUM_TCP) != 0) 2334 vlanctl |= RL_TDESC_CMD_TCPCSUMV2; 2335 if (((*m_head)->m_pkthdr.csum_flags & 2336 CSUM_UDP) != 0) 2337 vlanctl |= RL_TDESC_CMD_UDPCSUMV2; 2338 } 2339 } 2340 } 2341 2342 /* 2343 * Set up hardware VLAN tagging. Note: vlan tag info must 2344 * appear in all descriptors of a multi-descriptor 2345 * transmission attempt. 2346 */ 2347 if ((*m_head)->m_flags & M_VLANTAG) 2348 vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) | 2349 RL_TDESC_VLANCTL_TAG; 2350 2351 si = prod; 2352 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2353 desc = &sc->rl_ldata.rl_tx_list[prod]; 2354 desc->rl_vlanctl = htole32(vlanctl); 2355 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2356 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2357 cmdstat = segs[i].ds_len; 2358 if (i != 0) 2359 cmdstat |= RL_TDESC_CMD_OWN; 2360 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2361 cmdstat |= RL_TDESC_CMD_EOR; 2362 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2363 sc->rl_ldata.rl_tx_free--; 2364 } 2365 /* Update producer index. */ 2366 sc->rl_ldata.rl_tx_prodidx = prod; 2367 2368 /* Set EOF on the last descriptor. */ 2369 ei = RL_TX_DESC_PRV(sc, prod); 2370 desc = &sc->rl_ldata.rl_tx_list[ei]; 2371 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2372 2373 desc = &sc->rl_ldata.rl_tx_list[si]; 2374 /* Set SOF and transfer ownership of packet to the chip. */ 2375 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2376 2377 /* 2378 * Insure that the map for this transmission 2379 * is placed at the array index of the last descriptor 2380 * in this chain. (Swap last and first dmamaps.) 2381 */ 2382 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2383 map = txd->tx_dmamap; 2384 txd->tx_dmamap = txd_last->tx_dmamap; 2385 txd_last->tx_dmamap = map; 2386 txd_last->tx_m = *m_head; 2387 2388 return (0); 2389 } 2390 2391 static void 2392 re_tx_task(void *arg, int npending) 2393 { 2394 struct ifnet *ifp; 2395 2396 ifp = arg; 2397 re_start(ifp); 2398 } 2399 2400 /* 2401 * Main transmit routine for C+ and gigE NICs. 2402 */ 2403 static void 2404 re_start(struct ifnet *ifp) 2405 { 2406 struct rl_softc *sc; 2407 struct mbuf *m_head; 2408 int queued; 2409 2410 sc = ifp->if_softc; 2411 2412 RL_LOCK(sc); 2413 2414 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2415 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) { 2416 RL_UNLOCK(sc); 2417 return; 2418 } 2419 2420 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2421 sc->rl_ldata.rl_tx_free > 1;) { 2422 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2423 if (m_head == NULL) 2424 break; 2425 2426 if (re_encap(sc, &m_head) != 0) { 2427 if (m_head == NULL) 2428 break; 2429 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2430 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2431 break; 2432 } 2433 2434 /* 2435 * If there's a BPF listener, bounce a copy of this frame 2436 * to him. 2437 */ 2438 ETHER_BPF_MTAP(ifp, m_head); 2439 2440 queued++; 2441 } 2442 2443 if (queued == 0) { 2444 #ifdef RE_TX_MODERATION 2445 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2446 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2447 #endif 2448 RL_UNLOCK(sc); 2449 return; 2450 } 2451 2452 /* Flush the TX descriptors */ 2453 2454 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2455 sc->rl_ldata.rl_tx_list_map, 2456 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2457 2458 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2459 2460 #ifdef RE_TX_MODERATION 2461 /* 2462 * Use the countdown timer for interrupt moderation. 2463 * 'TX done' interrupts are disabled. Instead, we reset the 2464 * countdown timer, which will begin counting until it hits 2465 * the value in the TIMERINT register, and then trigger an 2466 * interrupt. Each time we write to the TIMERCNT register, 2467 * the timer count is reset to 0. 2468 */ 2469 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2470 #endif 2471 2472 /* 2473 * Set a timeout in case the chip goes out to lunch. 2474 */ 2475 sc->rl_watchdog_timer = 5; 2476 2477 RL_UNLOCK(sc); 2478 } 2479 2480 static void 2481 re_init(void *xsc) 2482 { 2483 struct rl_softc *sc = xsc; 2484 2485 RL_LOCK(sc); 2486 re_init_locked(sc); 2487 RL_UNLOCK(sc); 2488 } 2489 2490 static void 2491 re_init_locked(struct rl_softc *sc) 2492 { 2493 struct ifnet *ifp = sc->rl_ifp; 2494 struct mii_data *mii; 2495 uint32_t reg; 2496 uint16_t cfg; 2497 union { 2498 uint32_t align_dummy; 2499 u_char eaddr[ETHER_ADDR_LEN]; 2500 } eaddr; 2501 2502 RL_LOCK_ASSERT(sc); 2503 2504 mii = device_get_softc(sc->rl_miibus); 2505 2506 /* 2507 * Cancel pending I/O and free all RX/TX buffers. 2508 */ 2509 re_stop(sc); 2510 2511 /* Put controller into known state. */ 2512 re_reset(sc); 2513 2514 /* 2515 * Enable C+ RX and TX mode, as well as VLAN stripping and 2516 * RX checksum offload. We must configure the C+ register 2517 * before all others. 2518 */ 2519 cfg = RL_CPLUSCMD_PCI_MRW; 2520 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2521 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 2522 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2523 cfg |= RL_CPLUSCMD_VLANSTRIP; 2524 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) { 2525 cfg |= RL_CPLUSCMD_MACSTAT_DIS; 2526 /* XXX magic. */ 2527 cfg |= 0x0001; 2528 } else 2529 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB; 2530 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg); 2531 if (sc->rl_hwrev == RL_HWREV_8169_8110SC || 2532 sc->rl_hwrev == RL_HWREV_8169_8110SCE) { 2533 reg = 0x000fff00; 2534 if ((CSR_READ_1(sc, RL_CFG2) & RL_CFG2_PCI66MHZ) != 0) 2535 reg |= 0x000000ff; 2536 if (sc->rl_hwrev == RL_HWREV_8169_8110SCE) 2537 reg |= 0x00f00000; 2538 CSR_WRITE_4(sc, 0x7c, reg); 2539 /* Disable interrupt mitigation. */ 2540 CSR_WRITE_2(sc, 0xe2, 0); 2541 } 2542 /* 2543 * Disable TSO if interface MTU size is greater than MSS 2544 * allowed in controller. 2545 */ 2546 if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) { 2547 ifp->if_capenable &= ~IFCAP_TSO4; 2548 ifp->if_hwassist &= ~CSUM_TSO; 2549 } 2550 2551 /* 2552 * Init our MAC address. Even though the chipset 2553 * documentation doesn't mention it, we need to enter "Config 2554 * register write enable" mode to modify the ID registers. 2555 */ 2556 /* Copy MAC address on stack to align. */ 2557 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 2558 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2559 CSR_WRITE_4(sc, RL_IDR0, 2560 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 2561 CSR_WRITE_4(sc, RL_IDR4, 2562 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 2563 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2564 2565 /* 2566 * For C+ mode, initialize the RX descriptors and mbufs. 2567 */ 2568 re_rx_list_init(sc); 2569 re_tx_list_init(sc); 2570 2571 /* 2572 * Load the addresses of the RX and TX lists into the chip. 2573 */ 2574 2575 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2576 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2577 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2578 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2579 2580 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2581 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2582 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2583 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2584 2585 /* 2586 * Enable transmit and receive. 2587 */ 2588 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2589 2590 /* 2591 * Set the initial TX configuration. 2592 */ 2593 if (sc->rl_testmode) { 2594 if (sc->rl_type == RL_8169) 2595 CSR_WRITE_4(sc, RL_TXCFG, 2596 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2597 else 2598 CSR_WRITE_4(sc, RL_TXCFG, 2599 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2600 } else 2601 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2602 2603 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2604 2605 /* 2606 * Set the initial RX configuration. 2607 */ 2608 re_set_rxmode(sc); 2609 2610 #ifdef DEVICE_POLLING 2611 /* 2612 * Disable interrupts if we are polling. 2613 */ 2614 if (ifp->if_capenable & IFCAP_POLLING) 2615 CSR_WRITE_2(sc, RL_IMR, 0); 2616 else /* otherwise ... */ 2617 #endif 2618 2619 /* 2620 * Enable interrupts. 2621 */ 2622 if (sc->rl_testmode) 2623 CSR_WRITE_2(sc, RL_IMR, 0); 2624 else 2625 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2626 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 2627 2628 /* Set initial TX threshold */ 2629 sc->rl_txthresh = RL_TX_THRESH_INIT; 2630 2631 /* Start RX/TX process. */ 2632 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2633 #ifdef notdef 2634 /* Enable receiver and transmitter. */ 2635 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2636 #endif 2637 2638 #ifdef RE_TX_MODERATION 2639 /* 2640 * Initialize the timer interrupt register so that 2641 * a timer interrupt will be generated once the timer 2642 * reaches a certain number of ticks. The timer is 2643 * reloaded on each transmit. This gives us TX interrupt 2644 * moderation, which dramatically improves TX frame rate. 2645 */ 2646 if (sc->rl_type == RL_8169) 2647 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2648 else 2649 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2650 #endif 2651 2652 /* 2653 * For 8169 gigE NICs, set the max allowed RX packet 2654 * size so we can receive jumbo frames. 2655 */ 2656 if (sc->rl_type == RL_8169) 2657 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2658 2659 if (sc->rl_testmode) 2660 return; 2661 2662 mii_mediachg(mii); 2663 2664 CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD); 2665 2666 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2667 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2668 2669 sc->rl_flags &= ~RL_FLAG_LINK; 2670 sc->rl_watchdog_timer = 0; 2671 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2672 } 2673 2674 /* 2675 * Set media options. 2676 */ 2677 static int 2678 re_ifmedia_upd(struct ifnet *ifp) 2679 { 2680 struct rl_softc *sc; 2681 struct mii_data *mii; 2682 int error; 2683 2684 sc = ifp->if_softc; 2685 mii = device_get_softc(sc->rl_miibus); 2686 RL_LOCK(sc); 2687 error = mii_mediachg(mii); 2688 RL_UNLOCK(sc); 2689 2690 return (error); 2691 } 2692 2693 /* 2694 * Report current media status. 2695 */ 2696 static void 2697 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2698 { 2699 struct rl_softc *sc; 2700 struct mii_data *mii; 2701 2702 sc = ifp->if_softc; 2703 mii = device_get_softc(sc->rl_miibus); 2704 2705 RL_LOCK(sc); 2706 mii_pollstat(mii); 2707 RL_UNLOCK(sc); 2708 ifmr->ifm_active = mii->mii_media_active; 2709 ifmr->ifm_status = mii->mii_media_status; 2710 } 2711 2712 static int 2713 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2714 { 2715 struct rl_softc *sc = ifp->if_softc; 2716 struct ifreq *ifr = (struct ifreq *) data; 2717 struct mii_data *mii; 2718 int error = 0; 2719 2720 switch (command) { 2721 case SIOCSIFMTU: 2722 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > RL_JUMBO_MTU) { 2723 error = EINVAL; 2724 break; 2725 } 2726 if ((sc->rl_flags & RL_FLAG_NOJUMBO) != 0 && 2727 ifr->ifr_mtu > RL_MAX_FRAMELEN) { 2728 error = EINVAL; 2729 break; 2730 } 2731 RL_LOCK(sc); 2732 if (ifp->if_mtu != ifr->ifr_mtu) 2733 ifp->if_mtu = ifr->ifr_mtu; 2734 if (ifp->if_mtu > RL_TSO_MTU && 2735 (ifp->if_capenable & IFCAP_TSO4) != 0) { 2736 ifp->if_capenable &= ~IFCAP_TSO4; 2737 ifp->if_hwassist &= ~CSUM_TSO; 2738 } 2739 RL_UNLOCK(sc); 2740 break; 2741 case SIOCSIFFLAGS: 2742 RL_LOCK(sc); 2743 if ((ifp->if_flags & IFF_UP) != 0) { 2744 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2745 if (((ifp->if_flags ^ sc->rl_if_flags) 2746 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2747 re_set_rxmode(sc); 2748 } else 2749 re_init_locked(sc); 2750 } else { 2751 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2752 re_stop(sc); 2753 } 2754 sc->rl_if_flags = ifp->if_flags; 2755 RL_UNLOCK(sc); 2756 break; 2757 case SIOCADDMULTI: 2758 case SIOCDELMULTI: 2759 RL_LOCK(sc); 2760 re_set_rxmode(sc); 2761 RL_UNLOCK(sc); 2762 break; 2763 case SIOCGIFMEDIA: 2764 case SIOCSIFMEDIA: 2765 mii = device_get_softc(sc->rl_miibus); 2766 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2767 break; 2768 case SIOCSIFCAP: 2769 { 2770 int mask, reinit; 2771 2772 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2773 reinit = 0; 2774 #ifdef DEVICE_POLLING 2775 if (mask & IFCAP_POLLING) { 2776 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2777 error = ether_poll_register(re_poll, ifp); 2778 if (error) 2779 return(error); 2780 RL_LOCK(sc); 2781 /* Disable interrupts */ 2782 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2783 ifp->if_capenable |= IFCAP_POLLING; 2784 RL_UNLOCK(sc); 2785 } else { 2786 error = ether_poll_deregister(ifp); 2787 /* Enable interrupts. */ 2788 RL_LOCK(sc); 2789 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2790 ifp->if_capenable &= ~IFCAP_POLLING; 2791 RL_UNLOCK(sc); 2792 } 2793 } 2794 #endif /* DEVICE_POLLING */ 2795 if (mask & IFCAP_HWCSUM) { 2796 ifp->if_capenable ^= IFCAP_HWCSUM; 2797 if (ifp->if_capenable & IFCAP_TXCSUM) 2798 ifp->if_hwassist |= RE_CSUM_FEATURES; 2799 else 2800 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 2801 reinit = 1; 2802 } 2803 if (mask & IFCAP_VLAN_HWTAGGING) { 2804 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2805 reinit = 1; 2806 } 2807 if (mask & IFCAP_TSO4) { 2808 ifp->if_capenable ^= IFCAP_TSO4; 2809 if ((IFCAP_TSO4 & ifp->if_capenable) && 2810 (IFCAP_TSO4 & ifp->if_capabilities)) 2811 ifp->if_hwassist |= CSUM_TSO; 2812 else 2813 ifp->if_hwassist &= ~CSUM_TSO; 2814 if (ifp->if_mtu > RL_TSO_MTU && 2815 (ifp->if_capenable & IFCAP_TSO4) != 0) { 2816 ifp->if_capenable &= ~IFCAP_TSO4; 2817 ifp->if_hwassist &= ~CSUM_TSO; 2818 } 2819 } 2820 if ((mask & IFCAP_WOL) != 0 && 2821 (ifp->if_capabilities & IFCAP_WOL) != 0) { 2822 if ((mask & IFCAP_WOL_UCAST) != 0) 2823 ifp->if_capenable ^= IFCAP_WOL_UCAST; 2824 if ((mask & IFCAP_WOL_MCAST) != 0) 2825 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2826 if ((mask & IFCAP_WOL_MAGIC) != 0) 2827 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2828 } 2829 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) 2830 re_init(sc); 2831 VLAN_CAPABILITIES(ifp); 2832 } 2833 break; 2834 default: 2835 error = ether_ioctl(ifp, command, data); 2836 break; 2837 } 2838 2839 return (error); 2840 } 2841 2842 static void 2843 re_watchdog(struct rl_softc *sc) 2844 { 2845 struct ifnet *ifp; 2846 2847 RL_LOCK_ASSERT(sc); 2848 2849 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 2850 return; 2851 2852 ifp = sc->rl_ifp; 2853 re_txeof(sc); 2854 if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) { 2855 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 2856 "-- recovering\n"); 2857 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2858 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2859 return; 2860 } 2861 2862 if_printf(ifp, "watchdog timeout\n"); 2863 ifp->if_oerrors++; 2864 2865 re_rxeof(sc); 2866 re_init_locked(sc); 2867 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2868 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2869 } 2870 2871 /* 2872 * Stop the adapter and free any mbufs allocated to the 2873 * RX and TX lists. 2874 */ 2875 static void 2876 re_stop(struct rl_softc *sc) 2877 { 2878 int i; 2879 struct ifnet *ifp; 2880 struct rl_txdesc *txd; 2881 struct rl_rxdesc *rxd; 2882 2883 RL_LOCK_ASSERT(sc); 2884 2885 ifp = sc->rl_ifp; 2886 2887 sc->rl_watchdog_timer = 0; 2888 callout_stop(&sc->rl_stat_callout); 2889 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2890 2891 if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0) 2892 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB | 2893 RL_CMD_RX_ENB); 2894 else 2895 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2896 DELAY(1000); 2897 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2898 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 2899 2900 if (sc->rl_head != NULL) { 2901 m_freem(sc->rl_head); 2902 sc->rl_head = sc->rl_tail = NULL; 2903 } 2904 2905 /* Free the TX list buffers. */ 2906 2907 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 2908 txd = &sc->rl_ldata.rl_tx_desc[i]; 2909 if (txd->tx_m != NULL) { 2910 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2911 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2912 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2913 txd->tx_dmamap); 2914 m_freem(txd->tx_m); 2915 txd->tx_m = NULL; 2916 } 2917 } 2918 2919 /* Free the RX list buffers. */ 2920 2921 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2922 rxd = &sc->rl_ldata.rl_rx_desc[i]; 2923 if (rxd->rx_m != NULL) { 2924 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2925 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2926 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 2927 rxd->rx_dmamap); 2928 m_freem(rxd->rx_m); 2929 rxd->rx_m = NULL; 2930 } 2931 } 2932 } 2933 2934 /* 2935 * Device suspend routine. Stop the interface and save some PCI 2936 * settings in case the BIOS doesn't restore them properly on 2937 * resume. 2938 */ 2939 static int 2940 re_suspend(device_t dev) 2941 { 2942 struct rl_softc *sc; 2943 2944 sc = device_get_softc(dev); 2945 2946 RL_LOCK(sc); 2947 re_stop(sc); 2948 re_setwol(sc); 2949 sc->suspended = 1; 2950 RL_UNLOCK(sc); 2951 2952 return (0); 2953 } 2954 2955 /* 2956 * Device resume routine. Restore some PCI settings in case the BIOS 2957 * doesn't, re-enable busmastering, and restart the interface if 2958 * appropriate. 2959 */ 2960 static int 2961 re_resume(device_t dev) 2962 { 2963 struct rl_softc *sc; 2964 struct ifnet *ifp; 2965 2966 sc = device_get_softc(dev); 2967 2968 RL_LOCK(sc); 2969 2970 ifp = sc->rl_ifp; 2971 /* Take controller out of sleep mode. */ 2972 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 2973 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 2974 CSR_WRITE_1(sc, RL_GPIO, 2975 CSR_READ_1(sc, RL_GPIO) | 0x01); 2976 } 2977 2978 /* reinitialize interface if necessary */ 2979 if (ifp->if_flags & IFF_UP) 2980 re_init_locked(sc); 2981 2982 /* 2983 * Clear WOL matching such that normal Rx filtering 2984 * wouldn't interfere with WOL patterns. 2985 */ 2986 re_clrwol(sc); 2987 sc->suspended = 0; 2988 RL_UNLOCK(sc); 2989 2990 return (0); 2991 } 2992 2993 /* 2994 * Stop all chip I/O so that the kernel's probe routines don't 2995 * get confused by errant DMAs when rebooting. 2996 */ 2997 static int 2998 re_shutdown(device_t dev) 2999 { 3000 struct rl_softc *sc; 3001 3002 sc = device_get_softc(dev); 3003 3004 RL_LOCK(sc); 3005 re_stop(sc); 3006 /* 3007 * Mark interface as down since otherwise we will panic if 3008 * interrupt comes in later on, which can happen in some 3009 * cases. 3010 */ 3011 sc->rl_ifp->if_flags &= ~IFF_UP; 3012 re_setwol(sc); 3013 RL_UNLOCK(sc); 3014 3015 return (0); 3016 } 3017 3018 static void 3019 re_setwol(struct rl_softc *sc) 3020 { 3021 struct ifnet *ifp; 3022 int pmc; 3023 uint16_t pmstat; 3024 uint8_t v; 3025 3026 RL_LOCK_ASSERT(sc); 3027 3028 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3029 return; 3030 3031 ifp = sc->rl_ifp; 3032 /* Put controller into sleep mode. */ 3033 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3034 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3035 CSR_WRITE_1(sc, RL_GPIO, 3036 CSR_READ_1(sc, RL_GPIO) & ~0x01); 3037 } 3038 if ((ifp->if_capenable & IFCAP_WOL) != 0 && 3039 (sc->rl_flags & RL_FLAG_WOLRXENB) != 0) 3040 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB); 3041 /* Enable config register write. */ 3042 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3043 3044 /* Enable PME. */ 3045 v = CSR_READ_1(sc, RL_CFG1); 3046 v &= ~RL_CFG1_PME; 3047 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3048 v |= RL_CFG1_PME; 3049 CSR_WRITE_1(sc, RL_CFG1, v); 3050 3051 v = CSR_READ_1(sc, RL_CFG3); 3052 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3053 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3054 v |= RL_CFG3_WOL_MAGIC; 3055 CSR_WRITE_1(sc, RL_CFG3, v); 3056 3057 /* Config register write done. */ 3058 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3059 3060 v = CSR_READ_1(sc, RL_CFG5); 3061 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3062 v &= ~RL_CFG5_WOL_LANWAKE; 3063 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 3064 v |= RL_CFG5_WOL_UCAST; 3065 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 3066 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 3067 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3068 v |= RL_CFG5_WOL_LANWAKE; 3069 CSR_WRITE_1(sc, RL_CFG5, v); 3070 3071 /* 3072 * It seems that hardware resets its link speed to 100Mbps in 3073 * power down mode so switching to 100Mbps in driver is not 3074 * needed. 3075 */ 3076 3077 /* Request PME if WOL is requested. */ 3078 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 3079 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3080 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3081 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3082 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 3083 } 3084 3085 static void 3086 re_clrwol(struct rl_softc *sc) 3087 { 3088 int pmc; 3089 uint8_t v; 3090 3091 RL_LOCK_ASSERT(sc); 3092 3093 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3094 return; 3095 3096 /* Enable config register write. */ 3097 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3098 3099 v = CSR_READ_1(sc, RL_CFG3); 3100 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3101 CSR_WRITE_1(sc, RL_CFG3, v); 3102 3103 /* Config register write done. */ 3104 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3105 3106 v = CSR_READ_1(sc, RL_CFG5); 3107 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3108 v &= ~RL_CFG5_WOL_LANWAKE; 3109 CSR_WRITE_1(sc, RL_CFG5, v); 3110 } 3111