xref: /freebsd/sys/dev/re/if_re.c (revision 3b8f08459569bf0faa21473e5cec2491e95c9349)
1 /*-
2  * Copyright (c) 1997, 1998-2003
3  *	Bill Paul <wpaul@windriver.com>.  All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  * 3. All advertising materials mentioning features or use of this software
14  *    must display the following acknowledgement:
15  *	This product includes software developed by Bill Paul.
16  * 4. Neither the name of the author nor the names of any co-contributors
17  *    may be used to endorse or promote products derived from this software
18  *    without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30  * THE POSSIBILITY OF SUCH DAMAGE.
31  */
32 
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
35 
36 /*
37  * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver
38  *
39  * Written by Bill Paul <wpaul@windriver.com>
40  * Senior Networking Software Engineer
41  * Wind River Systems
42  */
43 
44 /*
45  * This driver is designed to support RealTek's next generation of
46  * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
47  * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S,
48  * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E.
49  *
50  * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
51  * with the older 8139 family, however it also supports a special
52  * C+ mode of operation that provides several new performance enhancing
53  * features. These include:
54  *
55  *	o Descriptor based DMA mechanism. Each descriptor represents
56  *	  a single packet fragment. Data buffers may be aligned on
57  *	  any byte boundary.
58  *
59  *	o 64-bit DMA
60  *
61  *	o TCP/IP checksum offload for both RX and TX
62  *
63  *	o High and normal priority transmit DMA rings
64  *
65  *	o VLAN tag insertion and extraction
66  *
67  *	o TCP large send (segmentation offload)
68  *
69  * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
70  * programming API is fairly straightforward. The RX filtering, EEPROM
71  * access and PHY access is the same as it is on the older 8139 series
72  * chips.
73  *
74  * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
75  * same programming API and feature set as the 8139C+ with the following
76  * differences and additions:
77  *
78  *	o 1000Mbps mode
79  *
80  *	o Jumbo frames
81  *
82  *	o GMII and TBI ports/registers for interfacing with copper
83  *	  or fiber PHYs
84  *
85  *	o RX and TX DMA rings can have up to 1024 descriptors
86  *	  (the 8139C+ allows a maximum of 64)
87  *
88  *	o Slight differences in register layout from the 8139C+
89  *
90  * The TX start and timer interrupt registers are at different locations
91  * on the 8169 than they are on the 8139C+. Also, the status word in the
92  * RX descriptor has a slightly different bit layout. The 8169 does not
93  * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
94  * copper gigE PHY.
95  *
96  * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
97  * (the 'S' stands for 'single-chip'). These devices have the same
98  * programming API as the older 8169, but also have some vendor-specific
99  * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
100  * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
101  *
102  * This driver takes advantage of the RX and TX checksum offload and
103  * VLAN tag insertion/extraction features. It also implements TX
104  * interrupt moderation using the timer interrupt registers, which
105  * significantly reduces TX interrupt load. There is also support
106  * for jumbo frames, however the 8169/8169S/8110S can not transmit
107  * jumbo frames larger than 7440, so the max MTU possible with this
108  * driver is 7422 bytes.
109  */
110 
111 #ifdef HAVE_KERNEL_OPTION_HEADERS
112 #include "opt_device_polling.h"
113 #endif
114 
115 #include <sys/param.h>
116 #include <sys/endian.h>
117 #include <sys/systm.h>
118 #include <sys/sockio.h>
119 #include <sys/mbuf.h>
120 #include <sys/malloc.h>
121 #include <sys/module.h>
122 #include <sys/kernel.h>
123 #include <sys/socket.h>
124 #include <sys/lock.h>
125 #include <sys/mutex.h>
126 #include <sys/sysctl.h>
127 #include <sys/taskqueue.h>
128 
129 #include <net/if.h>
130 #include <net/if_var.h>
131 #include <net/if_arp.h>
132 #include <net/ethernet.h>
133 #include <net/if_dl.h>
134 #include <net/if_media.h>
135 #include <net/if_types.h>
136 #include <net/if_vlan_var.h>
137 
138 #include <net/bpf.h>
139 
140 #include <machine/bus.h>
141 #include <machine/resource.h>
142 #include <sys/bus.h>
143 #include <sys/rman.h>
144 
145 #include <dev/mii/mii.h>
146 #include <dev/mii/miivar.h>
147 
148 #include <dev/pci/pcireg.h>
149 #include <dev/pci/pcivar.h>
150 
151 #include <pci/if_rlreg.h>
152 
153 MODULE_DEPEND(re, pci, 1, 1, 1);
154 MODULE_DEPEND(re, ether, 1, 1, 1);
155 MODULE_DEPEND(re, miibus, 1, 1, 1);
156 
157 /* "device miibus" required.  See GENERIC if you get errors here. */
158 #include "miibus_if.h"
159 
160 /* Tunables. */
161 static int intr_filter = 0;
162 TUNABLE_INT("hw.re.intr_filter", &intr_filter);
163 static int msi_disable = 0;
164 TUNABLE_INT("hw.re.msi_disable", &msi_disable);
165 static int msix_disable = 0;
166 TUNABLE_INT("hw.re.msix_disable", &msix_disable);
167 static int prefer_iomap = 0;
168 TUNABLE_INT("hw.re.prefer_iomap", &prefer_iomap);
169 
170 #define RE_CSUM_FEATURES    (CSUM_IP | CSUM_TCP | CSUM_UDP)
171 
172 /*
173  * Various supported device vendors/types and their names.
174  */
175 static const struct rl_type re_devs[] = {
176 	{ DLINK_VENDORID, DLINK_DEVICEID_528T, 0,
177 	    "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
178 	{ DLINK_VENDORID, DLINK_DEVICEID_530T_REVC, 0,
179 	    "D-Link DGE-530(T) Gigabit Ethernet Adapter" },
180 	{ RT_VENDORID, RT_DEVICEID_8139, 0,
181 	    "RealTek 8139C+ 10/100BaseTX" },
182 	{ RT_VENDORID, RT_DEVICEID_8101E, 0,
183 	    "RealTek 810xE PCIe 10/100baseTX" },
184 	{ RT_VENDORID, RT_DEVICEID_8168, 0,
185 	    "RealTek 8168/8111 B/C/CP/D/DP/E/F/G PCIe Gigabit Ethernet" },
186 	{ RT_VENDORID, RT_DEVICEID_8169, 0,
187 	    "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" },
188 	{ RT_VENDORID, RT_DEVICEID_8169SC, 0,
189 	    "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
190 	{ COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0,
191 	    "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" },
192 	{ LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0,
193 	    "Linksys EG1032 (RTL8169S) Gigabit Ethernet" },
194 	{ USR_VENDORID, USR_DEVICEID_997902, 0,
195 	    "US Robotics 997902 (RTL8169S) Gigabit Ethernet" }
196 };
197 
198 static const struct rl_hwrev re_hwrevs[] = {
199 	{ RL_HWREV_8139, RL_8139, "", RL_MTU },
200 	{ RL_HWREV_8139A, RL_8139, "A", RL_MTU },
201 	{ RL_HWREV_8139AG, RL_8139, "A-G", RL_MTU },
202 	{ RL_HWREV_8139B, RL_8139, "B", RL_MTU },
203 	{ RL_HWREV_8130, RL_8139, "8130", RL_MTU },
204 	{ RL_HWREV_8139C, RL_8139, "C", RL_MTU },
205 	{ RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C", RL_MTU },
206 	{ RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+", RL_MTU },
207 	{ RL_HWREV_8168B_SPIN1, RL_8169, "8168", RL_JUMBO_MTU },
208 	{ RL_HWREV_8169, RL_8169, "8169", RL_JUMBO_MTU },
209 	{ RL_HWREV_8169S, RL_8169, "8169S", RL_JUMBO_MTU },
210 	{ RL_HWREV_8110S, RL_8169, "8110S", RL_JUMBO_MTU },
211 	{ RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB", RL_JUMBO_MTU },
212 	{ RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU },
213 	{ RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL", RL_JUMBO_MTU },
214 	{ RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU },
215 	{ RL_HWREV_8100, RL_8139, "8100", RL_MTU },
216 	{ RL_HWREV_8101, RL_8139, "8101", RL_MTU },
217 	{ RL_HWREV_8100E, RL_8169, "8100E", RL_MTU },
218 	{ RL_HWREV_8101E, RL_8169, "8101E", RL_MTU },
219 	{ RL_HWREV_8102E, RL_8169, "8102E", RL_MTU },
220 	{ RL_HWREV_8102EL, RL_8169, "8102EL", RL_MTU },
221 	{ RL_HWREV_8102EL_SPIN1, RL_8169, "8102EL", RL_MTU },
222 	{ RL_HWREV_8103E, RL_8169, "8103E", RL_MTU },
223 	{ RL_HWREV_8401E, RL_8169, "8401E", RL_MTU },
224 	{ RL_HWREV_8402, RL_8169, "8402", RL_MTU },
225 	{ RL_HWREV_8105E, RL_8169, "8105E", RL_MTU },
226 	{ RL_HWREV_8105E_SPIN1, RL_8169, "8105E", RL_MTU },
227 	{ RL_HWREV_8106E, RL_8169, "8106E", RL_MTU },
228 	{ RL_HWREV_8168B_SPIN2, RL_8169, "8168", RL_JUMBO_MTU },
229 	{ RL_HWREV_8168B_SPIN3, RL_8169, "8168", RL_JUMBO_MTU },
230 	{ RL_HWREV_8168C, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K },
231 	{ RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K },
232 	{ RL_HWREV_8168CP, RL_8169, "8168CP/8111CP", RL_JUMBO_MTU_6K },
233 	{ RL_HWREV_8168D, RL_8169, "8168D/8111D", RL_JUMBO_MTU_9K },
234 	{ RL_HWREV_8168DP, RL_8169, "8168DP/8111DP", RL_JUMBO_MTU_9K },
235 	{ RL_HWREV_8168E, RL_8169, "8168E/8111E", RL_JUMBO_MTU_9K},
236 	{ RL_HWREV_8168E_VL, RL_8169, "8168E/8111E-VL", RL_JUMBO_MTU_6K},
237 	{ RL_HWREV_8168EP, RL_8169, "8168EP/8111EP", RL_JUMBO_MTU_9K},
238 	{ RL_HWREV_8168F, RL_8169, "8168F/8111F", RL_JUMBO_MTU_9K},
239 	{ RL_HWREV_8168G, RL_8169, "8168G/8111G", RL_JUMBO_MTU_9K},
240 	{ RL_HWREV_8168GU, RL_8169, "8168GU/8111GU", RL_JUMBO_MTU_9K},
241 	{ RL_HWREV_8411, RL_8169, "8411", RL_JUMBO_MTU_9K},
242 	{ RL_HWREV_8411B, RL_8169, "8411B", RL_JUMBO_MTU_9K},
243 	{ 0, 0, NULL, 0 }
244 };
245 
246 static int re_probe		(device_t);
247 static int re_attach		(device_t);
248 static int re_detach		(device_t);
249 
250 static int re_encap		(struct rl_softc *, struct mbuf **);
251 
252 static void re_dma_map_addr	(void *, bus_dma_segment_t *, int, int);
253 static int re_allocmem		(device_t, struct rl_softc *);
254 static __inline void re_discard_rxbuf
255 				(struct rl_softc *, int);
256 static int re_newbuf		(struct rl_softc *, int);
257 static int re_jumbo_newbuf	(struct rl_softc *, int);
258 static int re_rx_list_init	(struct rl_softc *);
259 static int re_jrx_list_init	(struct rl_softc *);
260 static int re_tx_list_init	(struct rl_softc *);
261 #ifdef RE_FIXUP_RX
262 static __inline void re_fixup_rx
263 				(struct mbuf *);
264 #endif
265 static int re_rxeof		(struct rl_softc *, int *);
266 static void re_txeof		(struct rl_softc *);
267 #ifdef DEVICE_POLLING
268 static int re_poll		(struct ifnet *, enum poll_cmd, int);
269 static int re_poll_locked	(struct ifnet *, enum poll_cmd, int);
270 #endif
271 static int re_intr		(void *);
272 static void re_intr_msi		(void *);
273 static void re_tick		(void *);
274 static void re_int_task		(void *, int);
275 static void re_start		(struct ifnet *);
276 static void re_start_locked	(struct ifnet *);
277 static int re_ioctl		(struct ifnet *, u_long, caddr_t);
278 static void re_init		(void *);
279 static void re_init_locked	(struct rl_softc *);
280 static void re_stop		(struct rl_softc *);
281 static void re_watchdog		(struct rl_softc *);
282 static int re_suspend		(device_t);
283 static int re_resume		(device_t);
284 static int re_shutdown		(device_t);
285 static int re_ifmedia_upd	(struct ifnet *);
286 static void re_ifmedia_sts	(struct ifnet *, struct ifmediareq *);
287 
288 static void re_eeprom_putbyte	(struct rl_softc *, int);
289 static void re_eeprom_getword	(struct rl_softc *, int, u_int16_t *);
290 static void re_read_eeprom	(struct rl_softc *, caddr_t, int, int);
291 static int re_gmii_readreg	(device_t, int, int);
292 static int re_gmii_writereg	(device_t, int, int, int);
293 
294 static int re_miibus_readreg	(device_t, int, int);
295 static int re_miibus_writereg	(device_t, int, int, int);
296 static void re_miibus_statchg	(device_t);
297 
298 static void re_set_jumbo	(struct rl_softc *, int);
299 static void re_set_rxmode		(struct rl_softc *);
300 static void re_reset		(struct rl_softc *);
301 static void re_setwol		(struct rl_softc *);
302 static void re_clrwol		(struct rl_softc *);
303 static void re_set_linkspeed	(struct rl_softc *);
304 
305 #ifdef DEV_NETMAP	/* see ixgbe.c for details */
306 #include <dev/netmap/if_re_netmap.h>
307 #endif /* !DEV_NETMAP */
308 
309 #ifdef RE_DIAG
310 static int re_diag		(struct rl_softc *);
311 #endif
312 
313 static void re_add_sysctls	(struct rl_softc *);
314 static int re_sysctl_stats	(SYSCTL_HANDLER_ARGS);
315 static int sysctl_int_range	(SYSCTL_HANDLER_ARGS, int, int);
316 static int sysctl_hw_re_int_mod	(SYSCTL_HANDLER_ARGS);
317 
318 static device_method_t re_methods[] = {
319 	/* Device interface */
320 	DEVMETHOD(device_probe,		re_probe),
321 	DEVMETHOD(device_attach,	re_attach),
322 	DEVMETHOD(device_detach,	re_detach),
323 	DEVMETHOD(device_suspend,	re_suspend),
324 	DEVMETHOD(device_resume,	re_resume),
325 	DEVMETHOD(device_shutdown,	re_shutdown),
326 
327 	/* MII interface */
328 	DEVMETHOD(miibus_readreg,	re_miibus_readreg),
329 	DEVMETHOD(miibus_writereg,	re_miibus_writereg),
330 	DEVMETHOD(miibus_statchg,	re_miibus_statchg),
331 
332 	DEVMETHOD_END
333 };
334 
335 static driver_t re_driver = {
336 	"re",
337 	re_methods,
338 	sizeof(struct rl_softc)
339 };
340 
341 static devclass_t re_devclass;
342 
343 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0);
344 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0);
345 
346 #define EE_SET(x)					\
347 	CSR_WRITE_1(sc, RL_EECMD,			\
348 		CSR_READ_1(sc, RL_EECMD) | x)
349 
350 #define EE_CLR(x)					\
351 	CSR_WRITE_1(sc, RL_EECMD,			\
352 		CSR_READ_1(sc, RL_EECMD) & ~x)
353 
354 /*
355  * Send a read command and address to the EEPROM, check for ACK.
356  */
357 static void
358 re_eeprom_putbyte(struct rl_softc *sc, int addr)
359 {
360 	int			d, i;
361 
362 	d = addr | (RL_9346_READ << sc->rl_eewidth);
363 
364 	/*
365 	 * Feed in each bit and strobe the clock.
366 	 */
367 
368 	for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) {
369 		if (d & i) {
370 			EE_SET(RL_EE_DATAIN);
371 		} else {
372 			EE_CLR(RL_EE_DATAIN);
373 		}
374 		DELAY(100);
375 		EE_SET(RL_EE_CLK);
376 		DELAY(150);
377 		EE_CLR(RL_EE_CLK);
378 		DELAY(100);
379 	}
380 }
381 
382 /*
383  * Read a word of data stored in the EEPROM at address 'addr.'
384  */
385 static void
386 re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest)
387 {
388 	int			i;
389 	u_int16_t		word = 0;
390 
391 	/*
392 	 * Send address of word we want to read.
393 	 */
394 	re_eeprom_putbyte(sc, addr);
395 
396 	/*
397 	 * Start reading bits from EEPROM.
398 	 */
399 	for (i = 0x8000; i; i >>= 1) {
400 		EE_SET(RL_EE_CLK);
401 		DELAY(100);
402 		if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
403 			word |= i;
404 		EE_CLR(RL_EE_CLK);
405 		DELAY(100);
406 	}
407 
408 	*dest = word;
409 }
410 
411 /*
412  * Read a sequence of words from the EEPROM.
413  */
414 static void
415 re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt)
416 {
417 	int			i;
418 	u_int16_t		word = 0, *ptr;
419 
420 	CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM);
421 
422         DELAY(100);
423 
424 	for (i = 0; i < cnt; i++) {
425 		CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL);
426 		re_eeprom_getword(sc, off + i, &word);
427 		CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL);
428 		ptr = (u_int16_t *)(dest + (i * 2));
429                 *ptr = word;
430 	}
431 
432 	CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM);
433 }
434 
435 static int
436 re_gmii_readreg(device_t dev, int phy, int reg)
437 {
438 	struct rl_softc		*sc;
439 	u_int32_t		rval;
440 	int			i;
441 
442 	sc = device_get_softc(dev);
443 
444 	/* Let the rgephy driver read the GMEDIASTAT register */
445 
446 	if (reg == RL_GMEDIASTAT) {
447 		rval = CSR_READ_1(sc, RL_GMEDIASTAT);
448 		return (rval);
449 	}
450 
451 	CSR_WRITE_4(sc, RL_PHYAR, reg << 16);
452 
453 	for (i = 0; i < RL_PHY_TIMEOUT; i++) {
454 		rval = CSR_READ_4(sc, RL_PHYAR);
455 		if (rval & RL_PHYAR_BUSY)
456 			break;
457 		DELAY(25);
458 	}
459 
460 	if (i == RL_PHY_TIMEOUT) {
461 		device_printf(sc->rl_dev, "PHY read failed\n");
462 		return (0);
463 	}
464 
465 	/*
466 	 * Controller requires a 20us delay to process next MDIO request.
467 	 */
468 	DELAY(20);
469 
470 	return (rval & RL_PHYAR_PHYDATA);
471 }
472 
473 static int
474 re_gmii_writereg(device_t dev, int phy, int reg, int data)
475 {
476 	struct rl_softc		*sc;
477 	u_int32_t		rval;
478 	int			i;
479 
480 	sc = device_get_softc(dev);
481 
482 	CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) |
483 	    (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY);
484 
485 	for (i = 0; i < RL_PHY_TIMEOUT; i++) {
486 		rval = CSR_READ_4(sc, RL_PHYAR);
487 		if (!(rval & RL_PHYAR_BUSY))
488 			break;
489 		DELAY(25);
490 	}
491 
492 	if (i == RL_PHY_TIMEOUT) {
493 		device_printf(sc->rl_dev, "PHY write failed\n");
494 		return (0);
495 	}
496 
497 	/*
498 	 * Controller requires a 20us delay to process next MDIO request.
499 	 */
500 	DELAY(20);
501 
502 	return (0);
503 }
504 
505 static int
506 re_miibus_readreg(device_t dev, int phy, int reg)
507 {
508 	struct rl_softc		*sc;
509 	u_int16_t		rval = 0;
510 	u_int16_t		re8139_reg = 0;
511 
512 	sc = device_get_softc(dev);
513 
514 	if (sc->rl_type == RL_8169) {
515 		rval = re_gmii_readreg(dev, phy, reg);
516 		return (rval);
517 	}
518 
519 	switch (reg) {
520 	case MII_BMCR:
521 		re8139_reg = RL_BMCR;
522 		break;
523 	case MII_BMSR:
524 		re8139_reg = RL_BMSR;
525 		break;
526 	case MII_ANAR:
527 		re8139_reg = RL_ANAR;
528 		break;
529 	case MII_ANER:
530 		re8139_reg = RL_ANER;
531 		break;
532 	case MII_ANLPAR:
533 		re8139_reg = RL_LPAR;
534 		break;
535 	case MII_PHYIDR1:
536 	case MII_PHYIDR2:
537 		return (0);
538 	/*
539 	 * Allow the rlphy driver to read the media status
540 	 * register. If we have a link partner which does not
541 	 * support NWAY, this is the register which will tell
542 	 * us the results of parallel detection.
543 	 */
544 	case RL_MEDIASTAT:
545 		rval = CSR_READ_1(sc, RL_MEDIASTAT);
546 		return (rval);
547 	default:
548 		device_printf(sc->rl_dev, "bad phy register\n");
549 		return (0);
550 	}
551 	rval = CSR_READ_2(sc, re8139_reg);
552 	if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) {
553 		/* 8139C+ has different bit layout. */
554 		rval &= ~(BMCR_LOOP | BMCR_ISO);
555 	}
556 	return (rval);
557 }
558 
559 static int
560 re_miibus_writereg(device_t dev, int phy, int reg, int data)
561 {
562 	struct rl_softc		*sc;
563 	u_int16_t		re8139_reg = 0;
564 	int			rval = 0;
565 
566 	sc = device_get_softc(dev);
567 
568 	if (sc->rl_type == RL_8169) {
569 		rval = re_gmii_writereg(dev, phy, reg, data);
570 		return (rval);
571 	}
572 
573 	switch (reg) {
574 	case MII_BMCR:
575 		re8139_reg = RL_BMCR;
576 		if (sc->rl_type == RL_8139CPLUS) {
577 			/* 8139C+ has different bit layout. */
578 			data &= ~(BMCR_LOOP | BMCR_ISO);
579 		}
580 		break;
581 	case MII_BMSR:
582 		re8139_reg = RL_BMSR;
583 		break;
584 	case MII_ANAR:
585 		re8139_reg = RL_ANAR;
586 		break;
587 	case MII_ANER:
588 		re8139_reg = RL_ANER;
589 		break;
590 	case MII_ANLPAR:
591 		re8139_reg = RL_LPAR;
592 		break;
593 	case MII_PHYIDR1:
594 	case MII_PHYIDR2:
595 		return (0);
596 		break;
597 	default:
598 		device_printf(sc->rl_dev, "bad phy register\n");
599 		return (0);
600 	}
601 	CSR_WRITE_2(sc, re8139_reg, data);
602 	return (0);
603 }
604 
605 static void
606 re_miibus_statchg(device_t dev)
607 {
608 	struct rl_softc		*sc;
609 	struct ifnet		*ifp;
610 	struct mii_data		*mii;
611 
612 	sc = device_get_softc(dev);
613 	mii = device_get_softc(sc->rl_miibus);
614 	ifp = sc->rl_ifp;
615 	if (mii == NULL || ifp == NULL ||
616 	    (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
617 		return;
618 
619 	sc->rl_flags &= ~RL_FLAG_LINK;
620 	if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
621 	    (IFM_ACTIVE | IFM_AVALID)) {
622 		switch (IFM_SUBTYPE(mii->mii_media_active)) {
623 		case IFM_10_T:
624 		case IFM_100_TX:
625 			sc->rl_flags |= RL_FLAG_LINK;
626 			break;
627 		case IFM_1000_T:
628 			if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0)
629 				break;
630 			sc->rl_flags |= RL_FLAG_LINK;
631 			break;
632 		default:
633 			break;
634 		}
635 	}
636 	/*
637 	 * RealTek controllers does not provide any interface to
638 	 * Tx/Rx MACs for resolved speed, duplex and flow-control
639 	 * parameters.
640 	 */
641 }
642 
643 /*
644  * Set the RX configuration and 64-bit multicast hash filter.
645  */
646 static void
647 re_set_rxmode(struct rl_softc *sc)
648 {
649 	struct ifnet		*ifp;
650 	struct ifmultiaddr	*ifma;
651 	uint32_t		hashes[2] = { 0, 0 };
652 	uint32_t		h, rxfilt;
653 
654 	RL_LOCK_ASSERT(sc);
655 
656 	ifp = sc->rl_ifp;
657 
658 	rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD;
659 	if ((sc->rl_flags & RL_FLAG_EARLYOFF) != 0)
660 		rxfilt |= RL_RXCFG_EARLYOFF;
661 	else if ((sc->rl_flags & RL_FLAG_EARLYOFFV2) != 0)
662 		rxfilt |= RL_RXCFG_EARLYOFFV2;
663 
664 	if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
665 		if (ifp->if_flags & IFF_PROMISC)
666 			rxfilt |= RL_RXCFG_RX_ALLPHYS;
667 		/*
668 		 * Unlike other hardwares, we have to explicitly set
669 		 * RL_RXCFG_RX_MULTI to receive multicast frames in
670 		 * promiscuous mode.
671 		 */
672 		rxfilt |= RL_RXCFG_RX_MULTI;
673 		hashes[0] = hashes[1] = 0xffffffff;
674 		goto done;
675 	}
676 
677 	if_maddr_rlock(ifp);
678 	TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
679 		if (ifma->ifma_addr->sa_family != AF_LINK)
680 			continue;
681 		h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
682 		    ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
683 		if (h < 32)
684 			hashes[0] |= (1 << h);
685 		else
686 			hashes[1] |= (1 << (h - 32));
687 	}
688 	if_maddr_runlock(ifp);
689 
690 	if (hashes[0] != 0 || hashes[1] != 0) {
691 		/*
692 		 * For some unfathomable reason, RealTek decided to
693 		 * reverse the order of the multicast hash registers
694 		 * in the PCI Express parts.  This means we have to
695 		 * write the hash pattern in reverse order for those
696 		 * devices.
697 		 */
698 		if ((sc->rl_flags & RL_FLAG_PCIE) != 0) {
699 			h = bswap32(hashes[0]);
700 			hashes[0] = bswap32(hashes[1]);
701 			hashes[1] = h;
702 		}
703 		rxfilt |= RL_RXCFG_RX_MULTI;
704 	}
705 
706 done:
707 	CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
708 	CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
709 	CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
710 }
711 
712 static void
713 re_reset(struct rl_softc *sc)
714 {
715 	int			i;
716 
717 	RL_LOCK_ASSERT(sc);
718 
719 	CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
720 
721 	for (i = 0; i < RL_TIMEOUT; i++) {
722 		DELAY(10);
723 		if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
724 			break;
725 	}
726 	if (i == RL_TIMEOUT)
727 		device_printf(sc->rl_dev, "reset never completed!\n");
728 
729 	if ((sc->rl_flags & RL_FLAG_MACRESET) != 0)
730 		CSR_WRITE_1(sc, 0x82, 1);
731 	if (sc->rl_hwrev->rl_rev == RL_HWREV_8169S)
732 		re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0);
733 }
734 
735 #ifdef RE_DIAG
736 
737 /*
738  * The following routine is designed to test for a defect on some
739  * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
740  * lines connected to the bus, however for a 32-bit only card, they
741  * should be pulled high. The result of this defect is that the
742  * NIC will not work right if you plug it into a 64-bit slot: DMA
743  * operations will be done with 64-bit transfers, which will fail
744  * because the 64-bit data lines aren't connected.
745  *
746  * There's no way to work around this (short of talking a soldering
747  * iron to the board), however we can detect it. The method we use
748  * here is to put the NIC into digital loopback mode, set the receiver
749  * to promiscuous mode, and then try to send a frame. We then compare
750  * the frame data we sent to what was received. If the data matches,
751  * then the NIC is working correctly, otherwise we know the user has
752  * a defective NIC which has been mistakenly plugged into a 64-bit PCI
753  * slot. In the latter case, there's no way the NIC can work correctly,
754  * so we print out a message on the console and abort the device attach.
755  */
756 
757 static int
758 re_diag(struct rl_softc *sc)
759 {
760 	struct ifnet		*ifp = sc->rl_ifp;
761 	struct mbuf		*m0;
762 	struct ether_header	*eh;
763 	struct rl_desc		*cur_rx;
764 	u_int16_t		status;
765 	u_int32_t		rxstat;
766 	int			total_len, i, error = 0, phyaddr;
767 	u_int8_t		dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
768 	u_int8_t		src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
769 
770 	/* Allocate a single mbuf */
771 	MGETHDR(m0, M_NOWAIT, MT_DATA);
772 	if (m0 == NULL)
773 		return (ENOBUFS);
774 
775 	RL_LOCK(sc);
776 
777 	/*
778 	 * Initialize the NIC in test mode. This sets the chip up
779 	 * so that it can send and receive frames, but performs the
780 	 * following special functions:
781 	 * - Puts receiver in promiscuous mode
782 	 * - Enables digital loopback mode
783 	 * - Leaves interrupts turned off
784 	 */
785 
786 	ifp->if_flags |= IFF_PROMISC;
787 	sc->rl_testmode = 1;
788 	ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
789 	re_init_locked(sc);
790 	sc->rl_flags |= RL_FLAG_LINK;
791 	if (sc->rl_type == RL_8169)
792 		phyaddr = 1;
793 	else
794 		phyaddr = 0;
795 
796 	re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET);
797 	for (i = 0; i < RL_TIMEOUT; i++) {
798 		status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR);
799 		if (!(status & BMCR_RESET))
800 			break;
801 	}
802 
803 	re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP);
804 	CSR_WRITE_2(sc, RL_ISR, RL_INTRS);
805 
806 	DELAY(100000);
807 
808 	/* Put some data in the mbuf */
809 
810 	eh = mtod(m0, struct ether_header *);
811 	bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN);
812 	bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN);
813 	eh->ether_type = htons(ETHERTYPE_IP);
814 	m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
815 
816 	/*
817 	 * Queue the packet, start transmission.
818 	 * Note: IF_HANDOFF() ultimately calls re_start() for us.
819 	 */
820 
821 	CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
822 	RL_UNLOCK(sc);
823 	/* XXX: re_diag must not be called when in ALTQ mode */
824 	IF_HANDOFF(&ifp->if_snd, m0, ifp);
825 	RL_LOCK(sc);
826 	m0 = NULL;
827 
828 	/* Wait for it to propagate through the chip */
829 
830 	DELAY(100000);
831 	for (i = 0; i < RL_TIMEOUT; i++) {
832 		status = CSR_READ_2(sc, RL_ISR);
833 		CSR_WRITE_2(sc, RL_ISR, status);
834 		if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) ==
835 		    (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK))
836 			break;
837 		DELAY(10);
838 	}
839 
840 	if (i == RL_TIMEOUT) {
841 		device_printf(sc->rl_dev,
842 		    "diagnostic failed, failed to receive packet in"
843 		    " loopback mode\n");
844 		error = EIO;
845 		goto done;
846 	}
847 
848 	/*
849 	 * The packet should have been dumped into the first
850 	 * entry in the RX DMA ring. Grab it from there.
851 	 */
852 
853 	bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
854 	    sc->rl_ldata.rl_rx_list_map,
855 	    BUS_DMASYNC_POSTREAD);
856 	bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag,
857 	    sc->rl_ldata.rl_rx_desc[0].rx_dmamap,
858 	    BUS_DMASYNC_POSTREAD);
859 	bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag,
860 	    sc->rl_ldata.rl_rx_desc[0].rx_dmamap);
861 
862 	m0 = sc->rl_ldata.rl_rx_desc[0].rx_m;
863 	sc->rl_ldata.rl_rx_desc[0].rx_m = NULL;
864 	eh = mtod(m0, struct ether_header *);
865 
866 	cur_rx = &sc->rl_ldata.rl_rx_list[0];
867 	total_len = RL_RXBYTES(cur_rx);
868 	rxstat = le32toh(cur_rx->rl_cmdstat);
869 
870 	if (total_len != ETHER_MIN_LEN) {
871 		device_printf(sc->rl_dev,
872 		    "diagnostic failed, received short packet\n");
873 		error = EIO;
874 		goto done;
875 	}
876 
877 	/* Test that the received packet data matches what we sent. */
878 
879 	if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) ||
880 	    bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) ||
881 	    ntohs(eh->ether_type) != ETHERTYPE_IP) {
882 		device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n");
883 		device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n",
884 		    dst, ":", src, ":", ETHERTYPE_IP);
885 		device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n",
886 		    eh->ether_dhost, ":", eh->ether_shost, ":",
887 		    ntohs(eh->ether_type));
888 		device_printf(sc->rl_dev, "You may have a defective 32-bit "
889 		    "NIC plugged into a 64-bit PCI slot.\n");
890 		device_printf(sc->rl_dev, "Please re-install the NIC in a "
891 		    "32-bit slot for proper operation.\n");
892 		device_printf(sc->rl_dev, "Read the re(4) man page for more "
893 		    "details.\n");
894 		error = EIO;
895 	}
896 
897 done:
898 	/* Turn interface off, release resources */
899 
900 	sc->rl_testmode = 0;
901 	sc->rl_flags &= ~RL_FLAG_LINK;
902 	ifp->if_flags &= ~IFF_PROMISC;
903 	re_stop(sc);
904 	if (m0 != NULL)
905 		m_freem(m0);
906 
907 	RL_UNLOCK(sc);
908 
909 	return (error);
910 }
911 
912 #endif
913 
914 /*
915  * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
916  * IDs against our list and return a device name if we find a match.
917  */
918 static int
919 re_probe(device_t dev)
920 {
921 	const struct rl_type	*t;
922 	uint16_t		devid, vendor;
923 	uint16_t		revid, sdevid;
924 	int			i;
925 
926 	vendor = pci_get_vendor(dev);
927 	devid = pci_get_device(dev);
928 	revid = pci_get_revid(dev);
929 	sdevid = pci_get_subdevice(dev);
930 
931 	if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) {
932 		if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) {
933 			/*
934 			 * Only attach to rev. 3 of the Linksys EG1032 adapter.
935 			 * Rev. 2 is supported by sk(4).
936 			 */
937 			return (ENXIO);
938 		}
939 	}
940 
941 	if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) {
942 		if (revid != 0x20) {
943 			/* 8139, let rl(4) take care of this device. */
944 			return (ENXIO);
945 		}
946 	}
947 
948 	t = re_devs;
949 	for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) {
950 		if (vendor == t->rl_vid && devid == t->rl_did) {
951 			device_set_desc(dev, t->rl_name);
952 			return (BUS_PROBE_DEFAULT);
953 		}
954 	}
955 
956 	return (ENXIO);
957 }
958 
959 /*
960  * Map a single buffer address.
961  */
962 
963 static void
964 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
965 {
966 	bus_addr_t		*addr;
967 
968 	if (error)
969 		return;
970 
971 	KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
972 	addr = arg;
973 	*addr = segs->ds_addr;
974 }
975 
976 static int
977 re_allocmem(device_t dev, struct rl_softc *sc)
978 {
979 	bus_addr_t		lowaddr;
980 	bus_size_t		rx_list_size, tx_list_size;
981 	int			error;
982 	int			i;
983 
984 	rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc);
985 	tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc);
986 
987 	/*
988 	 * Allocate the parent bus DMA tag appropriate for PCI.
989 	 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD
990 	 * register should be set. However some RealTek chips are known
991 	 * to be buggy on DAC handling, therefore disable DAC by limiting
992 	 * DMA address space to 32bit. PCIe variants of RealTek chips
993 	 * may not have the limitation.
994 	 */
995 	lowaddr = BUS_SPACE_MAXADDR;
996 	if ((sc->rl_flags & RL_FLAG_PCIE) == 0)
997 		lowaddr = BUS_SPACE_MAXADDR_32BIT;
998 	error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
999 	    lowaddr, BUS_SPACE_MAXADDR, NULL, NULL,
1000 	    BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
1001 	    NULL, NULL, &sc->rl_parent_tag);
1002 	if (error) {
1003 		device_printf(dev, "could not allocate parent DMA tag\n");
1004 		return (error);
1005 	}
1006 
1007 	/*
1008 	 * Allocate map for TX mbufs.
1009 	 */
1010 	error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0,
1011 	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
1012 	    NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0,
1013 	    NULL, NULL, &sc->rl_ldata.rl_tx_mtag);
1014 	if (error) {
1015 		device_printf(dev, "could not allocate TX DMA tag\n");
1016 		return (error);
1017 	}
1018 
1019 	/*
1020 	 * Allocate map for RX mbufs.
1021 	 */
1022 
1023 	if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
1024 		error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t),
1025 		    0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1026 		    MJUM9BYTES, 1, MJUM9BYTES, 0, NULL, NULL,
1027 		    &sc->rl_ldata.rl_jrx_mtag);
1028 		if (error) {
1029 			device_printf(dev,
1030 			    "could not allocate jumbo RX DMA tag\n");
1031 			return (error);
1032 		}
1033 	}
1034 	error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0,
1035 	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1036 	    MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag);
1037 	if (error) {
1038 		device_printf(dev, "could not allocate RX DMA tag\n");
1039 		return (error);
1040 	}
1041 
1042 	/*
1043 	 * Allocate map for TX descriptor list.
1044 	 */
1045 	error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
1046 	    0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1047 	    NULL, tx_list_size, 1, tx_list_size, 0,
1048 	    NULL, NULL, &sc->rl_ldata.rl_tx_list_tag);
1049 	if (error) {
1050 		device_printf(dev, "could not allocate TX DMA ring tag\n");
1051 		return (error);
1052 	}
1053 
1054 	/* Allocate DMA'able memory for the TX ring */
1055 
1056 	error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag,
1057 	    (void **)&sc->rl_ldata.rl_tx_list,
1058 	    BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
1059 	    &sc->rl_ldata.rl_tx_list_map);
1060 	if (error) {
1061 		device_printf(dev, "could not allocate TX DMA ring\n");
1062 		return (error);
1063 	}
1064 
1065 	/* Load the map for the TX ring. */
1066 
1067 	sc->rl_ldata.rl_tx_list_addr = 0;
1068 	error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag,
1069 	     sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list,
1070 	     tx_list_size, re_dma_map_addr,
1071 	     &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT);
1072 	if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) {
1073 		device_printf(dev, "could not load TX DMA ring\n");
1074 		return (ENOMEM);
1075 	}
1076 
1077 	/* Create DMA maps for TX buffers */
1078 
1079 	for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) {
1080 		error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0,
1081 		    &sc->rl_ldata.rl_tx_desc[i].tx_dmamap);
1082 		if (error) {
1083 			device_printf(dev, "could not create DMA map for TX\n");
1084 			return (error);
1085 		}
1086 	}
1087 
1088 	/*
1089 	 * Allocate map for RX descriptor list.
1090 	 */
1091 	error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
1092 	    0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1093 	    NULL, rx_list_size, 1, rx_list_size, 0,
1094 	    NULL, NULL, &sc->rl_ldata.rl_rx_list_tag);
1095 	if (error) {
1096 		device_printf(dev, "could not create RX DMA ring tag\n");
1097 		return (error);
1098 	}
1099 
1100 	/* Allocate DMA'able memory for the RX ring */
1101 
1102 	error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag,
1103 	    (void **)&sc->rl_ldata.rl_rx_list,
1104 	    BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
1105 	    &sc->rl_ldata.rl_rx_list_map);
1106 	if (error) {
1107 		device_printf(dev, "could not allocate RX DMA ring\n");
1108 		return (error);
1109 	}
1110 
1111 	/* Load the map for the RX ring. */
1112 
1113 	sc->rl_ldata.rl_rx_list_addr = 0;
1114 	error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag,
1115 	     sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list,
1116 	     rx_list_size, re_dma_map_addr,
1117 	     &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT);
1118 	if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) {
1119 		device_printf(dev, "could not load RX DMA ring\n");
1120 		return (ENOMEM);
1121 	}
1122 
1123 	/* Create DMA maps for RX buffers */
1124 
1125 	if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
1126 		error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0,
1127 		    &sc->rl_ldata.rl_jrx_sparemap);
1128 		if (error) {
1129 			device_printf(dev,
1130 			    "could not create spare DMA map for jumbo RX\n");
1131 			return (error);
1132 		}
1133 		for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
1134 			error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0,
1135 			    &sc->rl_ldata.rl_jrx_desc[i].rx_dmamap);
1136 			if (error) {
1137 				device_printf(dev,
1138 				    "could not create DMA map for jumbo RX\n");
1139 				return (error);
1140 			}
1141 		}
1142 	}
1143 	error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0,
1144 	    &sc->rl_ldata.rl_rx_sparemap);
1145 	if (error) {
1146 		device_printf(dev, "could not create spare DMA map for RX\n");
1147 		return (error);
1148 	}
1149 	for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
1150 		error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0,
1151 		    &sc->rl_ldata.rl_rx_desc[i].rx_dmamap);
1152 		if (error) {
1153 			device_printf(dev, "could not create DMA map for RX\n");
1154 			return (error);
1155 		}
1156 	}
1157 
1158 	/* Create DMA map for statistics. */
1159 	error = bus_dma_tag_create(sc->rl_parent_tag, RL_DUMP_ALIGN, 0,
1160 	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1161 	    sizeof(struct rl_stats), 1, sizeof(struct rl_stats), 0, NULL, NULL,
1162 	    &sc->rl_ldata.rl_stag);
1163 	if (error) {
1164 		device_printf(dev, "could not create statistics DMA tag\n");
1165 		return (error);
1166 	}
1167 	/* Allocate DMA'able memory for statistics. */
1168 	error = bus_dmamem_alloc(sc->rl_ldata.rl_stag,
1169 	    (void **)&sc->rl_ldata.rl_stats,
1170 	    BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
1171 	    &sc->rl_ldata.rl_smap);
1172 	if (error) {
1173 		device_printf(dev,
1174 		    "could not allocate statistics DMA memory\n");
1175 		return (error);
1176 	}
1177 	/* Load the map for statistics. */
1178 	sc->rl_ldata.rl_stats_addr = 0;
1179 	error = bus_dmamap_load(sc->rl_ldata.rl_stag, sc->rl_ldata.rl_smap,
1180 	    sc->rl_ldata.rl_stats, sizeof(struct rl_stats), re_dma_map_addr,
1181 	     &sc->rl_ldata.rl_stats_addr, BUS_DMA_NOWAIT);
1182 	if (error != 0 || sc->rl_ldata.rl_stats_addr == 0) {
1183 		device_printf(dev, "could not load statistics DMA memory\n");
1184 		return (ENOMEM);
1185 	}
1186 
1187 	return (0);
1188 }
1189 
1190 /*
1191  * Attach the interface. Allocate softc structures, do ifmedia
1192  * setup and ethernet/BPF attach.
1193  */
1194 static int
1195 re_attach(device_t dev)
1196 {
1197 	u_char			eaddr[ETHER_ADDR_LEN];
1198 	u_int16_t		as[ETHER_ADDR_LEN / 2];
1199 	struct rl_softc		*sc;
1200 	struct ifnet		*ifp;
1201 	const struct rl_hwrev	*hw_rev;
1202 	u_int32_t		cap, ctl;
1203 	int			hwrev;
1204 	u_int16_t		devid, re_did = 0;
1205 	int			error = 0, i, phy, rid;
1206 	int			msic, msixc, reg;
1207 	uint8_t			cfg;
1208 
1209 	sc = device_get_softc(dev);
1210 	sc->rl_dev = dev;
1211 
1212 	mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1213 	    MTX_DEF);
1214 	callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
1215 
1216 	/*
1217 	 * Map control/status registers.
1218 	 */
1219 	pci_enable_busmaster(dev);
1220 
1221 	devid = pci_get_device(dev);
1222 	/*
1223 	 * Prefer memory space register mapping over IO space.
1224 	 * Because RTL8169SC does not seem to work when memory mapping
1225 	 * is used always activate io mapping.
1226 	 */
1227 	if (devid == RT_DEVICEID_8169SC)
1228 		prefer_iomap = 1;
1229 	if (prefer_iomap == 0) {
1230 		sc->rl_res_id = PCIR_BAR(1);
1231 		sc->rl_res_type = SYS_RES_MEMORY;
1232 		/* RTL8168/8101E seems to use different BARs. */
1233 		if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E)
1234 			sc->rl_res_id = PCIR_BAR(2);
1235 	} else {
1236 		sc->rl_res_id = PCIR_BAR(0);
1237 		sc->rl_res_type = SYS_RES_IOPORT;
1238 	}
1239 	sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
1240 	    &sc->rl_res_id, RF_ACTIVE);
1241 	if (sc->rl_res == NULL && prefer_iomap == 0) {
1242 		sc->rl_res_id = PCIR_BAR(0);
1243 		sc->rl_res_type = SYS_RES_IOPORT;
1244 		sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
1245 		    &sc->rl_res_id, RF_ACTIVE);
1246 	}
1247 	if (sc->rl_res == NULL) {
1248 		device_printf(dev, "couldn't map ports/memory\n");
1249 		error = ENXIO;
1250 		goto fail;
1251 	}
1252 
1253 	sc->rl_btag = rman_get_bustag(sc->rl_res);
1254 	sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
1255 
1256 	msic = pci_msi_count(dev);
1257 	msixc = pci_msix_count(dev);
1258 	if (pci_find_cap(dev, PCIY_EXPRESS, &reg) == 0) {
1259 		sc->rl_flags |= RL_FLAG_PCIE;
1260 		sc->rl_expcap = reg;
1261 	}
1262 	if (bootverbose) {
1263 		device_printf(dev, "MSI count : %d\n", msic);
1264 		device_printf(dev, "MSI-X count : %d\n", msixc);
1265 	}
1266 	if (msix_disable > 0)
1267 		msixc = 0;
1268 	if (msi_disable > 0)
1269 		msic = 0;
1270 	/* Prefer MSI-X to MSI. */
1271 	if (msixc > 0) {
1272 		msixc = RL_MSI_MESSAGES;
1273 		rid = PCIR_BAR(4);
1274 		sc->rl_res_pba = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1275 		    &rid, RF_ACTIVE);
1276 		if (sc->rl_res_pba == NULL) {
1277 			device_printf(sc->rl_dev,
1278 			    "could not allocate MSI-X PBA resource\n");
1279 		}
1280 		if (sc->rl_res_pba != NULL &&
1281 		    pci_alloc_msix(dev, &msixc) == 0) {
1282 			if (msixc == RL_MSI_MESSAGES) {
1283 				device_printf(dev, "Using %d MSI-X message\n",
1284 				    msixc);
1285 				sc->rl_flags |= RL_FLAG_MSIX;
1286 			} else
1287 				pci_release_msi(dev);
1288 		}
1289 		if ((sc->rl_flags & RL_FLAG_MSIX) == 0) {
1290 			if (sc->rl_res_pba != NULL)
1291 				bus_release_resource(dev, SYS_RES_MEMORY, rid,
1292 				    sc->rl_res_pba);
1293 			sc->rl_res_pba = NULL;
1294 			msixc = 0;
1295 		}
1296 	}
1297 	/* Prefer MSI to INTx. */
1298 	if (msixc == 0 && msic > 0) {
1299 		msic = RL_MSI_MESSAGES;
1300 		if (pci_alloc_msi(dev, &msic) == 0) {
1301 			if (msic == RL_MSI_MESSAGES) {
1302 				device_printf(dev, "Using %d MSI message\n",
1303 				    msic);
1304 				sc->rl_flags |= RL_FLAG_MSI;
1305 				/* Explicitly set MSI enable bit. */
1306 				CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
1307 				cfg = CSR_READ_1(sc, RL_CFG2);
1308 				cfg |= RL_CFG2_MSI;
1309 				CSR_WRITE_1(sc, RL_CFG2, cfg);
1310 				CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1311 			} else
1312 				pci_release_msi(dev);
1313 		}
1314 		if ((sc->rl_flags & RL_FLAG_MSI) == 0)
1315 			msic = 0;
1316 	}
1317 
1318 	/* Allocate interrupt */
1319 	if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) {
1320 		rid = 0;
1321 		sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1322 		    RF_SHAREABLE | RF_ACTIVE);
1323 		if (sc->rl_irq[0] == NULL) {
1324 			device_printf(dev, "couldn't allocate IRQ resources\n");
1325 			error = ENXIO;
1326 			goto fail;
1327 		}
1328 	} else {
1329 		for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) {
1330 			sc->rl_irq[i] = bus_alloc_resource_any(dev,
1331 			    SYS_RES_IRQ, &rid, RF_ACTIVE);
1332 			if (sc->rl_irq[i] == NULL) {
1333 				device_printf(dev,
1334 				    "couldn't allocate IRQ resources for "
1335 				    "message %d\n", rid);
1336 				error = ENXIO;
1337 				goto fail;
1338 			}
1339 		}
1340 	}
1341 
1342 	if ((sc->rl_flags & RL_FLAG_MSI) == 0) {
1343 		CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
1344 		cfg = CSR_READ_1(sc, RL_CFG2);
1345 		if ((cfg & RL_CFG2_MSI) != 0) {
1346 			device_printf(dev, "turning off MSI enable bit.\n");
1347 			cfg &= ~RL_CFG2_MSI;
1348 			CSR_WRITE_1(sc, RL_CFG2, cfg);
1349 		}
1350 		CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1351 	}
1352 
1353 	/* Disable ASPM L0S/L1. */
1354 	if (sc->rl_expcap != 0) {
1355 		cap = pci_read_config(dev, sc->rl_expcap +
1356 		    PCIER_LINK_CAP, 2);
1357 		if ((cap & PCIEM_LINK_CAP_ASPM) != 0) {
1358 			ctl = pci_read_config(dev, sc->rl_expcap +
1359 			    PCIER_LINK_CTL, 2);
1360 			if ((ctl & PCIEM_LINK_CTL_ASPMC) != 0) {
1361 				ctl &= ~PCIEM_LINK_CTL_ASPMC;
1362 				pci_write_config(dev, sc->rl_expcap +
1363 				    PCIER_LINK_CTL, ctl, 2);
1364 				device_printf(dev, "ASPM disabled\n");
1365 			}
1366 		} else
1367 			device_printf(dev, "no ASPM capability\n");
1368 	}
1369 
1370 	hw_rev = re_hwrevs;
1371 	hwrev = CSR_READ_4(sc, RL_TXCFG);
1372 	switch (hwrev & 0x70000000) {
1373 	case 0x00000000:
1374 	case 0x10000000:
1375 		device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000);
1376 		hwrev &= (RL_TXCFG_HWREV | 0x80000000);
1377 		break;
1378 	default:
1379 		device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000);
1380 		sc->rl_macrev = hwrev & 0x00700000;
1381 		hwrev &= RL_TXCFG_HWREV;
1382 		break;
1383 	}
1384 	device_printf(dev, "MAC rev. 0x%08x\n", sc->rl_macrev);
1385 	while (hw_rev->rl_desc != NULL) {
1386 		if (hw_rev->rl_rev == hwrev) {
1387 			sc->rl_type = hw_rev->rl_type;
1388 			sc->rl_hwrev = hw_rev;
1389 			break;
1390 		}
1391 		hw_rev++;
1392 	}
1393 	if (hw_rev->rl_desc == NULL) {
1394 		device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev);
1395 		error = ENXIO;
1396 		goto fail;
1397 	}
1398 
1399 	switch (hw_rev->rl_rev) {
1400 	case RL_HWREV_8139CPLUS:
1401 		sc->rl_flags |= RL_FLAG_FASTETHER | RL_FLAG_AUTOPAD;
1402 		break;
1403 	case RL_HWREV_8100E:
1404 	case RL_HWREV_8101E:
1405 		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_FASTETHER;
1406 		break;
1407 	case RL_HWREV_8102E:
1408 	case RL_HWREV_8102EL:
1409 	case RL_HWREV_8102EL_SPIN1:
1410 		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 |
1411 		    RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP |
1412 		    RL_FLAG_AUTOPAD;
1413 		break;
1414 	case RL_HWREV_8103E:
1415 		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 |
1416 		    RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP |
1417 		    RL_FLAG_AUTOPAD | RL_FLAG_MACSLEEP;
1418 		break;
1419 	case RL_HWREV_8401E:
1420 	case RL_HWREV_8105E:
1421 	case RL_HWREV_8105E_SPIN1:
1422 	case RL_HWREV_8106E:
1423 		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
1424 		    RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
1425 		    RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD;
1426 		break;
1427 	case RL_HWREV_8402:
1428 		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
1429 		    RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
1430 		    RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD |
1431 		    RL_FLAG_CMDSTOP_WAIT_TXQ;
1432 		break;
1433 	case RL_HWREV_8168B_SPIN1:
1434 	case RL_HWREV_8168B_SPIN2:
1435 		sc->rl_flags |= RL_FLAG_WOLRXENB;
1436 		/* FALLTHROUGH */
1437 	case RL_HWREV_8168B_SPIN3:
1438 		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT;
1439 		break;
1440 	case RL_HWREV_8168C_SPIN2:
1441 		sc->rl_flags |= RL_FLAG_MACSLEEP;
1442 		/* FALLTHROUGH */
1443 	case RL_HWREV_8168C:
1444 		if (sc->rl_macrev == 0x00200000)
1445 			sc->rl_flags |= RL_FLAG_MACSLEEP;
1446 		/* FALLTHROUGH */
1447 	case RL_HWREV_8168CP:
1448 		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
1449 		    RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP |
1450 		    RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK;
1451 		break;
1452 	case RL_HWREV_8168D:
1453 		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
1454 		    RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
1455 		    RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 |
1456 		    RL_FLAG_WOL_MANLINK;
1457 		break;
1458 	case RL_HWREV_8168DP:
1459 		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
1460 		    RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_AUTOPAD |
1461 		    RL_FLAG_JUMBOV2 | RL_FLAG_WAIT_TXPOLL | RL_FLAG_WOL_MANLINK;
1462 		break;
1463 	case RL_HWREV_8168E:
1464 		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
1465 		    RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
1466 		    RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 |
1467 		    RL_FLAG_WOL_MANLINK;
1468 		break;
1469 	case RL_HWREV_8168E_VL:
1470 	case RL_HWREV_8168F:
1471 		sc->rl_flags |= RL_FLAG_EARLYOFF;
1472 		/* FALLTHROUGH */
1473 	case RL_HWREV_8411:
1474 		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
1475 		    RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP |
1476 		    RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 |
1477 		    RL_FLAG_CMDSTOP_WAIT_TXQ | RL_FLAG_WOL_MANLINK;
1478 		break;
1479 	case RL_HWREV_8168EP:
1480 	case RL_HWREV_8168G:
1481 	case RL_HWREV_8411B:
1482 		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
1483 		    RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP |
1484 		    RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 |
1485 		    RL_FLAG_CMDSTOP_WAIT_TXQ | RL_FLAG_WOL_MANLINK |
1486 		    RL_FLAG_EARLYOFFV2 | RL_FLAG_RXDV_GATED;
1487 		break;
1488 	case RL_HWREV_8168GU:
1489 		if (pci_get_device(dev) == RT_DEVICEID_8101E) {
1490 			/* RTL8106EUS */
1491 			sc->rl_flags |= RL_FLAG_FASTETHER;
1492 		} else
1493 			sc->rl_flags |= RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK;
1494 
1495 		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
1496 		    RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP |
1497 		    RL_FLAG_AUTOPAD | RL_FLAG_CMDSTOP_WAIT_TXQ |
1498 		    RL_FLAG_EARLYOFFV2 | RL_FLAG_RXDV_GATED;
1499 		break;
1500 	case RL_HWREV_8169_8110SB:
1501 	case RL_HWREV_8169_8110SBL:
1502 	case RL_HWREV_8169_8110SC:
1503 	case RL_HWREV_8169_8110SCE:
1504 		sc->rl_flags |= RL_FLAG_PHYWAKE;
1505 		/* FALLTHROUGH */
1506 	case RL_HWREV_8169:
1507 	case RL_HWREV_8169S:
1508 	case RL_HWREV_8110S:
1509 		sc->rl_flags |= RL_FLAG_MACRESET;
1510 		break;
1511 	default:
1512 		break;
1513 	}
1514 
1515 	if (sc->rl_hwrev->rl_rev == RL_HWREV_8139CPLUS) {
1516 		sc->rl_cfg0 = RL_8139_CFG0;
1517 		sc->rl_cfg1 = RL_8139_CFG1;
1518 		sc->rl_cfg2 = 0;
1519 		sc->rl_cfg3 = RL_8139_CFG3;
1520 		sc->rl_cfg4 = RL_8139_CFG4;
1521 		sc->rl_cfg5 = RL_8139_CFG5;
1522 	} else {
1523 		sc->rl_cfg0 = RL_CFG0;
1524 		sc->rl_cfg1 = RL_CFG1;
1525 		sc->rl_cfg2 = RL_CFG2;
1526 		sc->rl_cfg3 = RL_CFG3;
1527 		sc->rl_cfg4 = RL_CFG4;
1528 		sc->rl_cfg5 = RL_CFG5;
1529 	}
1530 
1531 	/* Reset the adapter. */
1532 	RL_LOCK(sc);
1533 	re_reset(sc);
1534 	RL_UNLOCK(sc);
1535 
1536 	/* Enable PME. */
1537 	CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
1538 	cfg = CSR_READ_1(sc, sc->rl_cfg1);
1539 	cfg |= RL_CFG1_PME;
1540 	CSR_WRITE_1(sc, sc->rl_cfg1, cfg);
1541 	cfg = CSR_READ_1(sc, sc->rl_cfg5);
1542 	cfg &= RL_CFG5_PME_STS;
1543 	CSR_WRITE_1(sc, sc->rl_cfg5, cfg);
1544 	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1545 
1546 	if ((sc->rl_flags & RL_FLAG_PAR) != 0) {
1547 		/*
1548 		 * XXX Should have a better way to extract station
1549 		 * address from EEPROM.
1550 		 */
1551 		for (i = 0; i < ETHER_ADDR_LEN; i++)
1552 			eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i);
1553 	} else {
1554 		sc->rl_eewidth = RL_9356_ADDR_LEN;
1555 		re_read_eeprom(sc, (caddr_t)&re_did, 0, 1);
1556 		if (re_did != 0x8129)
1557 			sc->rl_eewidth = RL_9346_ADDR_LEN;
1558 
1559 		/*
1560 		 * Get station address from the EEPROM.
1561 		 */
1562 		re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3);
1563 		for (i = 0; i < ETHER_ADDR_LEN / 2; i++)
1564 			as[i] = le16toh(as[i]);
1565 		bcopy(as, eaddr, ETHER_ADDR_LEN);
1566 	}
1567 
1568 	if (sc->rl_type == RL_8169) {
1569 		/* Set RX length mask and number of descriptors. */
1570 		sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN;
1571 		sc->rl_txstart = RL_GTXSTART;
1572 		sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT;
1573 		sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT;
1574 	} else {
1575 		/* Set RX length mask and number of descriptors. */
1576 		sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN;
1577 		sc->rl_txstart = RL_TXSTART;
1578 		sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT;
1579 		sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT;
1580 	}
1581 
1582 	error = re_allocmem(dev, sc);
1583 	if (error)
1584 		goto fail;
1585 	re_add_sysctls(sc);
1586 
1587 	ifp = sc->rl_ifp = if_alloc(IFT_ETHER);
1588 	if (ifp == NULL) {
1589 		device_printf(dev, "can not if_alloc()\n");
1590 		error = ENOSPC;
1591 		goto fail;
1592 	}
1593 
1594 	/* Take controller out of deep sleep mode. */
1595 	if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) {
1596 		if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80)
1597 			CSR_WRITE_1(sc, RL_GPIO,
1598 			    CSR_READ_1(sc, RL_GPIO) | 0x01);
1599 		else
1600 			CSR_WRITE_1(sc, RL_GPIO,
1601 			    CSR_READ_1(sc, RL_GPIO) & ~0x01);
1602 	}
1603 
1604 	/* Take PHY out of power down mode. */
1605 	if ((sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) {
1606 		CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80);
1607 		if (hw_rev->rl_rev == RL_HWREV_8401E)
1608 			CSR_WRITE_1(sc, 0xD1, CSR_READ_1(sc, 0xD1) & ~0x08);
1609 	}
1610 	if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) {
1611 		re_gmii_writereg(dev, 1, 0x1f, 0);
1612 		re_gmii_writereg(dev, 1, 0x0e, 0);
1613 	}
1614 
1615 	ifp->if_softc = sc;
1616 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1617 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1618 	ifp->if_ioctl = re_ioctl;
1619 	ifp->if_start = re_start;
1620 	/*
1621 	 * RTL8168/8111C generates wrong IP checksummed frame if the
1622 	 * packet has IP options so disable TX IP checksum offloading.
1623 	 */
1624 	if (sc->rl_hwrev->rl_rev == RL_HWREV_8168C ||
1625 	    sc->rl_hwrev->rl_rev == RL_HWREV_8168C_SPIN2 ||
1626 	    sc->rl_hwrev->rl_rev == RL_HWREV_8168CP)
1627 		ifp->if_hwassist = CSUM_TCP | CSUM_UDP;
1628 	else
1629 		ifp->if_hwassist = CSUM_IP | CSUM_TCP | CSUM_UDP;
1630 	ifp->if_hwassist |= CSUM_TSO;
1631 	ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4;
1632 	ifp->if_capenable = ifp->if_capabilities;
1633 	ifp->if_init = re_init;
1634 	IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN);
1635 	ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN;
1636 	IFQ_SET_READY(&ifp->if_snd);
1637 
1638 	TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc);
1639 
1640 #define	RE_PHYAD_INTERNAL	 0
1641 
1642 	/* Do MII setup. */
1643 	phy = RE_PHYAD_INTERNAL;
1644 	if (sc->rl_type == RL_8169)
1645 		phy = 1;
1646 	error = mii_attach(dev, &sc->rl_miibus, ifp, re_ifmedia_upd,
1647 	    re_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, MIIF_DOPAUSE);
1648 	if (error != 0) {
1649 		device_printf(dev, "attaching PHYs failed\n");
1650 		goto fail;
1651 	}
1652 
1653 	/*
1654 	 * Call MI attach routine.
1655 	 */
1656 	ether_ifattach(ifp, eaddr);
1657 
1658 	/* VLAN capability setup */
1659 	ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
1660 	if (ifp->if_capabilities & IFCAP_HWCSUM)
1661 		ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
1662 	/* Enable WOL if PM is supported. */
1663 	if (pci_find_cap(sc->rl_dev, PCIY_PMG, &reg) == 0)
1664 		ifp->if_capabilities |= IFCAP_WOL;
1665 	ifp->if_capenable = ifp->if_capabilities;
1666 	ifp->if_capenable &= ~(IFCAP_WOL_UCAST | IFCAP_WOL_MCAST);
1667 	/*
1668 	 * Don't enable TSO by default.  It is known to generate
1669 	 * corrupted TCP segments(bad TCP options) under certain
1670 	 * circumstances.
1671 	 */
1672 	ifp->if_hwassist &= ~CSUM_TSO;
1673 	ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO);
1674 #ifdef DEVICE_POLLING
1675 	ifp->if_capabilities |= IFCAP_POLLING;
1676 #endif
1677 	/*
1678 	 * Tell the upper layer(s) we support long frames.
1679 	 * Must appear after the call to ether_ifattach() because
1680 	 * ether_ifattach() sets ifi_hdrlen to the default value.
1681 	 */
1682 	ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1683 
1684 #ifdef DEV_NETMAP
1685 	re_netmap_attach(sc);
1686 #endif /* DEV_NETMAP */
1687 #ifdef RE_DIAG
1688 	/*
1689 	 * Perform hardware diagnostic on the original RTL8169.
1690 	 * Some 32-bit cards were incorrectly wired and would
1691 	 * malfunction if plugged into a 64-bit slot.
1692 	 */
1693 
1694 	if (hwrev == RL_HWREV_8169) {
1695 		error = re_diag(sc);
1696 		if (error) {
1697 			device_printf(dev,
1698 		    	"attach aborted due to hardware diag failure\n");
1699 			ether_ifdetach(ifp);
1700 			goto fail;
1701 		}
1702 	}
1703 #endif
1704 
1705 #ifdef RE_TX_MODERATION
1706 	intr_filter = 1;
1707 #endif
1708 	/* Hook interrupt last to avoid having to lock softc */
1709 	if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 &&
1710 	    intr_filter == 0) {
1711 		error = bus_setup_intr(dev, sc->rl_irq[0],
1712 		    INTR_TYPE_NET | INTR_MPSAFE, NULL, re_intr_msi, sc,
1713 		    &sc->rl_intrhand[0]);
1714 	} else {
1715 		error = bus_setup_intr(dev, sc->rl_irq[0],
1716 		    INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc,
1717 		    &sc->rl_intrhand[0]);
1718 	}
1719 	if (error) {
1720 		device_printf(dev, "couldn't set up irq\n");
1721 		ether_ifdetach(ifp);
1722 	}
1723 
1724 fail:
1725 
1726 	if (error)
1727 		re_detach(dev);
1728 
1729 	return (error);
1730 }
1731 
1732 /*
1733  * Shutdown hardware and free up resources. This can be called any
1734  * time after the mutex has been initialized. It is called in both
1735  * the error case in attach and the normal detach case so it needs
1736  * to be careful about only freeing resources that have actually been
1737  * allocated.
1738  */
1739 static int
1740 re_detach(device_t dev)
1741 {
1742 	struct rl_softc		*sc;
1743 	struct ifnet		*ifp;
1744 	int			i, rid;
1745 
1746 	sc = device_get_softc(dev);
1747 	ifp = sc->rl_ifp;
1748 	KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized"));
1749 
1750 	/* These should only be active if attach succeeded */
1751 	if (device_is_attached(dev)) {
1752 #ifdef DEVICE_POLLING
1753 		if (ifp->if_capenable & IFCAP_POLLING)
1754 			ether_poll_deregister(ifp);
1755 #endif
1756 		RL_LOCK(sc);
1757 #if 0
1758 		sc->suspended = 1;
1759 #endif
1760 		re_stop(sc);
1761 		RL_UNLOCK(sc);
1762 		callout_drain(&sc->rl_stat_callout);
1763 		taskqueue_drain(taskqueue_fast, &sc->rl_inttask);
1764 		/*
1765 		 * Force off the IFF_UP flag here, in case someone
1766 		 * still had a BPF descriptor attached to this
1767 		 * interface. If they do, ether_ifdetach() will cause
1768 		 * the BPF code to try and clear the promisc mode
1769 		 * flag, which will bubble down to re_ioctl(),
1770 		 * which will try to call re_init() again. This will
1771 		 * turn the NIC back on and restart the MII ticker,
1772 		 * which will panic the system when the kernel tries
1773 		 * to invoke the re_tick() function that isn't there
1774 		 * anymore.
1775 		 */
1776 		ifp->if_flags &= ~IFF_UP;
1777 		ether_ifdetach(ifp);
1778 	}
1779 	if (sc->rl_miibus)
1780 		device_delete_child(dev, sc->rl_miibus);
1781 	bus_generic_detach(dev);
1782 
1783 	/*
1784 	 * The rest is resource deallocation, so we should already be
1785 	 * stopped here.
1786 	 */
1787 
1788 	if (sc->rl_intrhand[0] != NULL) {
1789 		bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]);
1790 		sc->rl_intrhand[0] = NULL;
1791 	}
1792 	if (ifp != NULL) {
1793 #ifdef DEV_NETMAP
1794 		netmap_detach(ifp);
1795 #endif /* DEV_NETMAP */
1796 		if_free(ifp);
1797 	}
1798 	if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0)
1799 		rid = 0;
1800 	else
1801 		rid = 1;
1802 	if (sc->rl_irq[0] != NULL) {
1803 		bus_release_resource(dev, SYS_RES_IRQ, rid, sc->rl_irq[0]);
1804 		sc->rl_irq[0] = NULL;
1805 	}
1806 	if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0)
1807 		pci_release_msi(dev);
1808 	if (sc->rl_res_pba) {
1809 		rid = PCIR_BAR(4);
1810 		bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->rl_res_pba);
1811 	}
1812 	if (sc->rl_res)
1813 		bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id,
1814 		    sc->rl_res);
1815 
1816 	/* Unload and free the RX DMA ring memory and map */
1817 
1818 	if (sc->rl_ldata.rl_rx_list_tag) {
1819 		if (sc->rl_ldata.rl_rx_list_map)
1820 			bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag,
1821 			    sc->rl_ldata.rl_rx_list_map);
1822 		if (sc->rl_ldata.rl_rx_list_map && sc->rl_ldata.rl_rx_list)
1823 			bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag,
1824 			    sc->rl_ldata.rl_rx_list,
1825 			    sc->rl_ldata.rl_rx_list_map);
1826 		bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag);
1827 	}
1828 
1829 	/* Unload and free the TX DMA ring memory and map */
1830 
1831 	if (sc->rl_ldata.rl_tx_list_tag) {
1832 		if (sc->rl_ldata.rl_tx_list_map)
1833 			bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag,
1834 			    sc->rl_ldata.rl_tx_list_map);
1835 		if (sc->rl_ldata.rl_tx_list_map && sc->rl_ldata.rl_tx_list)
1836 			bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag,
1837 			    sc->rl_ldata.rl_tx_list,
1838 			    sc->rl_ldata.rl_tx_list_map);
1839 		bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag);
1840 	}
1841 
1842 	/* Destroy all the RX and TX buffer maps */
1843 
1844 	if (sc->rl_ldata.rl_tx_mtag) {
1845 		for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) {
1846 			if (sc->rl_ldata.rl_tx_desc[i].tx_dmamap)
1847 				bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag,
1848 				    sc->rl_ldata.rl_tx_desc[i].tx_dmamap);
1849 		}
1850 		bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag);
1851 	}
1852 	if (sc->rl_ldata.rl_rx_mtag) {
1853 		for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
1854 			if (sc->rl_ldata.rl_rx_desc[i].rx_dmamap)
1855 				bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag,
1856 				    sc->rl_ldata.rl_rx_desc[i].rx_dmamap);
1857 		}
1858 		if (sc->rl_ldata.rl_rx_sparemap)
1859 			bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag,
1860 			    sc->rl_ldata.rl_rx_sparemap);
1861 		bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag);
1862 	}
1863 	if (sc->rl_ldata.rl_jrx_mtag) {
1864 		for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
1865 			if (sc->rl_ldata.rl_jrx_desc[i].rx_dmamap)
1866 				bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag,
1867 				    sc->rl_ldata.rl_jrx_desc[i].rx_dmamap);
1868 		}
1869 		if (sc->rl_ldata.rl_jrx_sparemap)
1870 			bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag,
1871 			    sc->rl_ldata.rl_jrx_sparemap);
1872 		bus_dma_tag_destroy(sc->rl_ldata.rl_jrx_mtag);
1873 	}
1874 	/* Unload and free the stats buffer and map */
1875 
1876 	if (sc->rl_ldata.rl_stag) {
1877 		if (sc->rl_ldata.rl_smap)
1878 			bus_dmamap_unload(sc->rl_ldata.rl_stag,
1879 			    sc->rl_ldata.rl_smap);
1880 		if (sc->rl_ldata.rl_smap && sc->rl_ldata.rl_stats)
1881 			bus_dmamem_free(sc->rl_ldata.rl_stag,
1882 			    sc->rl_ldata.rl_stats, sc->rl_ldata.rl_smap);
1883 		bus_dma_tag_destroy(sc->rl_ldata.rl_stag);
1884 	}
1885 
1886 	if (sc->rl_parent_tag)
1887 		bus_dma_tag_destroy(sc->rl_parent_tag);
1888 
1889 	mtx_destroy(&sc->rl_mtx);
1890 
1891 	return (0);
1892 }
1893 
1894 static __inline void
1895 re_discard_rxbuf(struct rl_softc *sc, int idx)
1896 {
1897 	struct rl_desc		*desc;
1898 	struct rl_rxdesc	*rxd;
1899 	uint32_t		cmdstat;
1900 
1901 	if (sc->rl_ifp->if_mtu > RL_MTU &&
1902 	    (sc->rl_flags & RL_FLAG_JUMBOV2) != 0)
1903 		rxd = &sc->rl_ldata.rl_jrx_desc[idx];
1904 	else
1905 		rxd = &sc->rl_ldata.rl_rx_desc[idx];
1906 	desc = &sc->rl_ldata.rl_rx_list[idx];
1907 	desc->rl_vlanctl = 0;
1908 	cmdstat = rxd->rx_size;
1909 	if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1)
1910 		cmdstat |= RL_RDESC_CMD_EOR;
1911 	desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN);
1912 }
1913 
1914 static int
1915 re_newbuf(struct rl_softc *sc, int idx)
1916 {
1917 	struct mbuf		*m;
1918 	struct rl_rxdesc	*rxd;
1919 	bus_dma_segment_t	segs[1];
1920 	bus_dmamap_t		map;
1921 	struct rl_desc		*desc;
1922 	uint32_t		cmdstat;
1923 	int			error, nsegs;
1924 
1925 	m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1926 	if (m == NULL)
1927 		return (ENOBUFS);
1928 
1929 	m->m_len = m->m_pkthdr.len = MCLBYTES;
1930 #ifdef RE_FIXUP_RX
1931 	/*
1932 	 * This is part of an evil trick to deal with non-x86 platforms.
1933 	 * The RealTek chip requires RX buffers to be aligned on 64-bit
1934 	 * boundaries, but that will hose non-x86 machines. To get around
1935 	 * this, we leave some empty space at the start of each buffer
1936 	 * and for non-x86 hosts, we copy the buffer back six bytes
1937 	 * to achieve word alignment. This is slightly more efficient
1938 	 * than allocating a new buffer, copying the contents, and
1939 	 * discarding the old buffer.
1940 	 */
1941 	m_adj(m, RE_ETHER_ALIGN);
1942 #endif
1943 	error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag,
1944 	    sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT);
1945 	if (error != 0) {
1946 		m_freem(m);
1947 		return (ENOBUFS);
1948 	}
1949 	KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs));
1950 
1951 	rxd = &sc->rl_ldata.rl_rx_desc[idx];
1952 	if (rxd->rx_m != NULL) {
1953 		bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap,
1954 		    BUS_DMASYNC_POSTREAD);
1955 		bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap);
1956 	}
1957 
1958 	rxd->rx_m = m;
1959 	map = rxd->rx_dmamap;
1960 	rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap;
1961 	rxd->rx_size = segs[0].ds_len;
1962 	sc->rl_ldata.rl_rx_sparemap = map;
1963 	bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap,
1964 	    BUS_DMASYNC_PREREAD);
1965 
1966 	desc = &sc->rl_ldata.rl_rx_list[idx];
1967 	desc->rl_vlanctl = 0;
1968 	desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr));
1969 	desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr));
1970 	cmdstat = segs[0].ds_len;
1971 	if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1)
1972 		cmdstat |= RL_RDESC_CMD_EOR;
1973 	desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN);
1974 
1975 	return (0);
1976 }
1977 
1978 static int
1979 re_jumbo_newbuf(struct rl_softc *sc, int idx)
1980 {
1981 	struct mbuf		*m;
1982 	struct rl_rxdesc	*rxd;
1983 	bus_dma_segment_t	segs[1];
1984 	bus_dmamap_t		map;
1985 	struct rl_desc		*desc;
1986 	uint32_t		cmdstat;
1987 	int			error, nsegs;
1988 
1989 	m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
1990 	if (m == NULL)
1991 		return (ENOBUFS);
1992 	m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1993 #ifdef RE_FIXUP_RX
1994 	m_adj(m, RE_ETHER_ALIGN);
1995 #endif
1996 	error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_jrx_mtag,
1997 	    sc->rl_ldata.rl_jrx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT);
1998 	if (error != 0) {
1999 		m_freem(m);
2000 		return (ENOBUFS);
2001 	}
2002 	KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs));
2003 
2004 	rxd = &sc->rl_ldata.rl_jrx_desc[idx];
2005 	if (rxd->rx_m != NULL) {
2006 		bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap,
2007 		    BUS_DMASYNC_POSTREAD);
2008 		bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap);
2009 	}
2010 
2011 	rxd->rx_m = m;
2012 	map = rxd->rx_dmamap;
2013 	rxd->rx_dmamap = sc->rl_ldata.rl_jrx_sparemap;
2014 	rxd->rx_size = segs[0].ds_len;
2015 	sc->rl_ldata.rl_jrx_sparemap = map;
2016 	bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap,
2017 	    BUS_DMASYNC_PREREAD);
2018 
2019 	desc = &sc->rl_ldata.rl_rx_list[idx];
2020 	desc->rl_vlanctl = 0;
2021 	desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr));
2022 	desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr));
2023 	cmdstat = segs[0].ds_len;
2024 	if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1)
2025 		cmdstat |= RL_RDESC_CMD_EOR;
2026 	desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN);
2027 
2028 	return (0);
2029 }
2030 
2031 #ifdef RE_FIXUP_RX
2032 static __inline void
2033 re_fixup_rx(struct mbuf *m)
2034 {
2035 	int                     i;
2036 	uint16_t                *src, *dst;
2037 
2038 	src = mtod(m, uint16_t *);
2039 	dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src;
2040 
2041 	for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
2042 		*dst++ = *src++;
2043 
2044 	m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN;
2045 }
2046 #endif
2047 
2048 static int
2049 re_tx_list_init(struct rl_softc *sc)
2050 {
2051 	struct rl_desc		*desc;
2052 	int			i;
2053 
2054 	RL_LOCK_ASSERT(sc);
2055 
2056 	bzero(sc->rl_ldata.rl_tx_list,
2057 	    sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc));
2058 	for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++)
2059 		sc->rl_ldata.rl_tx_desc[i].tx_m = NULL;
2060 #ifdef DEV_NETMAP
2061 	re_netmap_tx_init(sc);
2062 #endif /* DEV_NETMAP */
2063 	/* Set EOR. */
2064 	desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1];
2065 	desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR);
2066 
2067 	bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
2068 	    sc->rl_ldata.rl_tx_list_map,
2069 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2070 
2071 	sc->rl_ldata.rl_tx_prodidx = 0;
2072 	sc->rl_ldata.rl_tx_considx = 0;
2073 	sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt;
2074 
2075 	return (0);
2076 }
2077 
2078 static int
2079 re_rx_list_init(struct rl_softc *sc)
2080 {
2081 	int			error, i;
2082 
2083 	bzero(sc->rl_ldata.rl_rx_list,
2084 	    sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc));
2085 	for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
2086 		sc->rl_ldata.rl_rx_desc[i].rx_m = NULL;
2087 		if ((error = re_newbuf(sc, i)) != 0)
2088 			return (error);
2089 	}
2090 #ifdef DEV_NETMAP
2091 	re_netmap_rx_init(sc);
2092 #endif /* DEV_NETMAP */
2093 
2094 	/* Flush the RX descriptors */
2095 
2096 	bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
2097 	    sc->rl_ldata.rl_rx_list_map,
2098 	    BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
2099 
2100 	sc->rl_ldata.rl_rx_prodidx = 0;
2101 	sc->rl_head = sc->rl_tail = NULL;
2102 	sc->rl_int_rx_act = 0;
2103 
2104 	return (0);
2105 }
2106 
2107 static int
2108 re_jrx_list_init(struct rl_softc *sc)
2109 {
2110 	int			error, i;
2111 
2112 	bzero(sc->rl_ldata.rl_rx_list,
2113 	    sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc));
2114 	for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
2115 		sc->rl_ldata.rl_jrx_desc[i].rx_m = NULL;
2116 		if ((error = re_jumbo_newbuf(sc, i)) != 0)
2117 			return (error);
2118 	}
2119 
2120 	bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
2121 	    sc->rl_ldata.rl_rx_list_map,
2122 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2123 
2124 	sc->rl_ldata.rl_rx_prodidx = 0;
2125 	sc->rl_head = sc->rl_tail = NULL;
2126 	sc->rl_int_rx_act = 0;
2127 
2128 	return (0);
2129 }
2130 
2131 /*
2132  * RX handler for C+ and 8169. For the gigE chips, we support
2133  * the reception of jumbo frames that have been fragmented
2134  * across multiple 2K mbuf cluster buffers.
2135  */
2136 static int
2137 re_rxeof(struct rl_softc *sc, int *rx_npktsp)
2138 {
2139 	struct mbuf		*m;
2140 	struct ifnet		*ifp;
2141 	int			i, rxerr, total_len;
2142 	struct rl_desc		*cur_rx;
2143 	u_int32_t		rxstat, rxvlan;
2144 	int			jumbo, maxpkt = 16, rx_npkts = 0;
2145 
2146 	RL_LOCK_ASSERT(sc);
2147 
2148 	ifp = sc->rl_ifp;
2149 #ifdef DEV_NETMAP
2150 	if (netmap_rx_irq(ifp, 0, &rx_npkts))
2151 		return 0;
2152 #endif /* DEV_NETMAP */
2153 	if (ifp->if_mtu > RL_MTU && (sc->rl_flags & RL_FLAG_JUMBOV2) != 0)
2154 		jumbo = 1;
2155 	else
2156 		jumbo = 0;
2157 
2158 	/* Invalidate the descriptor memory */
2159 
2160 	bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
2161 	    sc->rl_ldata.rl_rx_list_map,
2162 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2163 
2164 	for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0;
2165 	    i = RL_RX_DESC_NXT(sc, i)) {
2166 		if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
2167 			break;
2168 		cur_rx = &sc->rl_ldata.rl_rx_list[i];
2169 		rxstat = le32toh(cur_rx->rl_cmdstat);
2170 		if ((rxstat & RL_RDESC_STAT_OWN) != 0)
2171 			break;
2172 		total_len = rxstat & sc->rl_rxlenmask;
2173 		rxvlan = le32toh(cur_rx->rl_vlanctl);
2174 		if (jumbo != 0)
2175 			m = sc->rl_ldata.rl_jrx_desc[i].rx_m;
2176 		else
2177 			m = sc->rl_ldata.rl_rx_desc[i].rx_m;
2178 
2179 		if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 &&
2180 		    (rxstat & (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) !=
2181 		    (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) {
2182 			/*
2183 			 * RTL8168C or later controllers do not
2184 			 * support multi-fragment packet.
2185 			 */
2186 			re_discard_rxbuf(sc, i);
2187 			continue;
2188 		} else if ((rxstat & RL_RDESC_STAT_EOF) == 0) {
2189 			if (re_newbuf(sc, i) != 0) {
2190 				/*
2191 				 * If this is part of a multi-fragment packet,
2192 				 * discard all the pieces.
2193 				 */
2194 				if (sc->rl_head != NULL) {
2195 					m_freem(sc->rl_head);
2196 					sc->rl_head = sc->rl_tail = NULL;
2197 				}
2198 				re_discard_rxbuf(sc, i);
2199 				continue;
2200 			}
2201 			m->m_len = RE_RX_DESC_BUFLEN;
2202 			if (sc->rl_head == NULL)
2203 				sc->rl_head = sc->rl_tail = m;
2204 			else {
2205 				m->m_flags &= ~M_PKTHDR;
2206 				sc->rl_tail->m_next = m;
2207 				sc->rl_tail = m;
2208 			}
2209 			continue;
2210 		}
2211 
2212 		/*
2213 		 * NOTE: for the 8139C+, the frame length field
2214 		 * is always 12 bits in size, but for the gigE chips,
2215 		 * it is 13 bits (since the max RX frame length is 16K).
2216 		 * Unfortunately, all 32 bits in the status word
2217 		 * were already used, so to make room for the extra
2218 		 * length bit, RealTek took out the 'frame alignment
2219 		 * error' bit and shifted the other status bits
2220 		 * over one slot. The OWN, EOR, FS and LS bits are
2221 		 * still in the same places. We have already extracted
2222 		 * the frame length and checked the OWN bit, so rather
2223 		 * than using an alternate bit mapping, we shift the
2224 		 * status bits one space to the right so we can evaluate
2225 		 * them using the 8169 status as though it was in the
2226 		 * same format as that of the 8139C+.
2227 		 */
2228 		if (sc->rl_type == RL_8169)
2229 			rxstat >>= 1;
2230 
2231 		/*
2232 		 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be
2233 		 * set, but if CRC is clear, it will still be a valid frame.
2234 		 */
2235 		if ((rxstat & RL_RDESC_STAT_RXERRSUM) != 0) {
2236 			rxerr = 1;
2237 			if ((sc->rl_flags & RL_FLAG_JUMBOV2) == 0 &&
2238 			    total_len > 8191 &&
2239 			    (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)
2240 				rxerr = 0;
2241 			if (rxerr != 0) {
2242 				ifp->if_ierrors++;
2243 				/*
2244 				 * If this is part of a multi-fragment packet,
2245 				 * discard all the pieces.
2246 				 */
2247 				if (sc->rl_head != NULL) {
2248 					m_freem(sc->rl_head);
2249 					sc->rl_head = sc->rl_tail = NULL;
2250 				}
2251 				re_discard_rxbuf(sc, i);
2252 				continue;
2253 			}
2254 		}
2255 
2256 		/*
2257 		 * If allocating a replacement mbuf fails,
2258 		 * reload the current one.
2259 		 */
2260 		if (jumbo != 0)
2261 			rxerr = re_jumbo_newbuf(sc, i);
2262 		else
2263 			rxerr = re_newbuf(sc, i);
2264 		if (rxerr != 0) {
2265 			ifp->if_iqdrops++;
2266 			if (sc->rl_head != NULL) {
2267 				m_freem(sc->rl_head);
2268 				sc->rl_head = sc->rl_tail = NULL;
2269 			}
2270 			re_discard_rxbuf(sc, i);
2271 			continue;
2272 		}
2273 
2274 		if (sc->rl_head != NULL) {
2275 			if (jumbo != 0)
2276 				m->m_len = total_len;
2277 			else {
2278 				m->m_len = total_len % RE_RX_DESC_BUFLEN;
2279 				if (m->m_len == 0)
2280 					m->m_len = RE_RX_DESC_BUFLEN;
2281 			}
2282 			/*
2283 			 * Special case: if there's 4 bytes or less
2284 			 * in this buffer, the mbuf can be discarded:
2285 			 * the last 4 bytes is the CRC, which we don't
2286 			 * care about anyway.
2287 			 */
2288 			if (m->m_len <= ETHER_CRC_LEN) {
2289 				sc->rl_tail->m_len -=
2290 				    (ETHER_CRC_LEN - m->m_len);
2291 				m_freem(m);
2292 			} else {
2293 				m->m_len -= ETHER_CRC_LEN;
2294 				m->m_flags &= ~M_PKTHDR;
2295 				sc->rl_tail->m_next = m;
2296 			}
2297 			m = sc->rl_head;
2298 			sc->rl_head = sc->rl_tail = NULL;
2299 			m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
2300 		} else
2301 			m->m_pkthdr.len = m->m_len =
2302 			    (total_len - ETHER_CRC_LEN);
2303 
2304 #ifdef RE_FIXUP_RX
2305 		re_fixup_rx(m);
2306 #endif
2307 		ifp->if_ipackets++;
2308 		m->m_pkthdr.rcvif = ifp;
2309 
2310 		/* Do RX checksumming if enabled */
2311 
2312 		if (ifp->if_capenable & IFCAP_RXCSUM) {
2313 			if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) {
2314 				/* Check IP header checksum */
2315 				if (rxstat & RL_RDESC_STAT_PROTOID)
2316 					m->m_pkthdr.csum_flags |=
2317 					    CSUM_IP_CHECKED;
2318 				if (!(rxstat & RL_RDESC_STAT_IPSUMBAD))
2319 					m->m_pkthdr.csum_flags |=
2320 					    CSUM_IP_VALID;
2321 
2322 				/* Check TCP/UDP checksum */
2323 				if ((RL_TCPPKT(rxstat) &&
2324 				    !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) ||
2325 				    (RL_UDPPKT(rxstat) &&
2326 				     !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) {
2327 					m->m_pkthdr.csum_flags |=
2328 						CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
2329 					m->m_pkthdr.csum_data = 0xffff;
2330 				}
2331 			} else {
2332 				/*
2333 				 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP
2334 				 */
2335 				if ((rxstat & RL_RDESC_STAT_PROTOID) &&
2336 				    (rxvlan & RL_RDESC_IPV4))
2337 					m->m_pkthdr.csum_flags |=
2338 					    CSUM_IP_CHECKED;
2339 				if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) &&
2340 				    (rxvlan & RL_RDESC_IPV4))
2341 					m->m_pkthdr.csum_flags |=
2342 					    CSUM_IP_VALID;
2343 				if (((rxstat & RL_RDESC_STAT_TCP) &&
2344 				    !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) ||
2345 				    ((rxstat & RL_RDESC_STAT_UDP) &&
2346 				    !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) {
2347 					m->m_pkthdr.csum_flags |=
2348 						CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
2349 					m->m_pkthdr.csum_data = 0xffff;
2350 				}
2351 			}
2352 		}
2353 		maxpkt--;
2354 		if (rxvlan & RL_RDESC_VLANCTL_TAG) {
2355 			m->m_pkthdr.ether_vtag =
2356 			    bswap16((rxvlan & RL_RDESC_VLANCTL_DATA));
2357 			m->m_flags |= M_VLANTAG;
2358 		}
2359 		RL_UNLOCK(sc);
2360 		(*ifp->if_input)(ifp, m);
2361 		RL_LOCK(sc);
2362 		rx_npkts++;
2363 	}
2364 
2365 	/* Flush the RX DMA ring */
2366 
2367 	bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
2368 	    sc->rl_ldata.rl_rx_list_map,
2369 	    BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
2370 
2371 	sc->rl_ldata.rl_rx_prodidx = i;
2372 
2373 	if (rx_npktsp != NULL)
2374 		*rx_npktsp = rx_npkts;
2375 	if (maxpkt)
2376 		return (EAGAIN);
2377 
2378 	return (0);
2379 }
2380 
2381 static void
2382 re_txeof(struct rl_softc *sc)
2383 {
2384 	struct ifnet		*ifp;
2385 	struct rl_txdesc	*txd;
2386 	u_int32_t		txstat;
2387 	int			cons;
2388 
2389 	cons = sc->rl_ldata.rl_tx_considx;
2390 	if (cons == sc->rl_ldata.rl_tx_prodidx)
2391 		return;
2392 
2393 	ifp = sc->rl_ifp;
2394 #ifdef DEV_NETMAP
2395 	if (netmap_tx_irq(ifp, 0))
2396 		return;
2397 #endif /* DEV_NETMAP */
2398 	/* Invalidate the TX descriptor list */
2399 	bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
2400 	    sc->rl_ldata.rl_tx_list_map,
2401 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2402 
2403 	for (; cons != sc->rl_ldata.rl_tx_prodidx;
2404 	    cons = RL_TX_DESC_NXT(sc, cons)) {
2405 		txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat);
2406 		if (txstat & RL_TDESC_STAT_OWN)
2407 			break;
2408 		/*
2409 		 * We only stash mbufs in the last descriptor
2410 		 * in a fragment chain, which also happens to
2411 		 * be the only place where the TX status bits
2412 		 * are valid.
2413 		 */
2414 		if (txstat & RL_TDESC_CMD_EOF) {
2415 			txd = &sc->rl_ldata.rl_tx_desc[cons];
2416 			bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag,
2417 			    txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2418 			bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag,
2419 			    txd->tx_dmamap);
2420 			KASSERT(txd->tx_m != NULL,
2421 			    ("%s: freeing NULL mbufs!", __func__));
2422 			m_freem(txd->tx_m);
2423 			txd->tx_m = NULL;
2424 			if (txstat & (RL_TDESC_STAT_EXCESSCOL|
2425 			    RL_TDESC_STAT_COLCNT))
2426 				ifp->if_collisions++;
2427 			if (txstat & RL_TDESC_STAT_TXERRSUM)
2428 				ifp->if_oerrors++;
2429 			else
2430 				ifp->if_opackets++;
2431 		}
2432 		sc->rl_ldata.rl_tx_free++;
2433 		ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2434 	}
2435 	sc->rl_ldata.rl_tx_considx = cons;
2436 
2437 	/* No changes made to the TX ring, so no flush needed */
2438 
2439 	if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) {
2440 #ifdef RE_TX_MODERATION
2441 		/*
2442 		 * If not all descriptors have been reaped yet, reload
2443 		 * the timer so that we will eventually get another
2444 		 * interrupt that will cause us to re-enter this routine.
2445 		 * This is done in case the transmitter has gone idle.
2446 		 */
2447 		CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2448 #endif
2449 	} else
2450 		sc->rl_watchdog_timer = 0;
2451 }
2452 
2453 static void
2454 re_tick(void *xsc)
2455 {
2456 	struct rl_softc		*sc;
2457 	struct mii_data		*mii;
2458 
2459 	sc = xsc;
2460 
2461 	RL_LOCK_ASSERT(sc);
2462 
2463 	mii = device_get_softc(sc->rl_miibus);
2464 	mii_tick(mii);
2465 	if ((sc->rl_flags & RL_FLAG_LINK) == 0)
2466 		re_miibus_statchg(sc->rl_dev);
2467 	/*
2468 	 * Reclaim transmitted frames here. Technically it is not
2469 	 * necessary to do here but it ensures periodic reclamation
2470 	 * regardless of Tx completion interrupt which seems to be
2471 	 * lost on PCIe based controllers under certain situations.
2472 	 */
2473 	re_txeof(sc);
2474 	re_watchdog(sc);
2475 	callout_reset(&sc->rl_stat_callout, hz, re_tick, sc);
2476 }
2477 
2478 #ifdef DEVICE_POLLING
2479 static int
2480 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2481 {
2482 	struct rl_softc *sc = ifp->if_softc;
2483 	int rx_npkts = 0;
2484 
2485 	RL_LOCK(sc);
2486 	if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2487 		rx_npkts = re_poll_locked(ifp, cmd, count);
2488 	RL_UNLOCK(sc);
2489 	return (rx_npkts);
2490 }
2491 
2492 static int
2493 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
2494 {
2495 	struct rl_softc *sc = ifp->if_softc;
2496 	int rx_npkts;
2497 
2498 	RL_LOCK_ASSERT(sc);
2499 
2500 	sc->rxcycles = count;
2501 	re_rxeof(sc, &rx_npkts);
2502 	re_txeof(sc);
2503 
2504 	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2505 		re_start_locked(ifp);
2506 
2507 	if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
2508 		u_int16_t       status;
2509 
2510 		status = CSR_READ_2(sc, RL_ISR);
2511 		if (status == 0xffff)
2512 			return (rx_npkts);
2513 		if (status)
2514 			CSR_WRITE_2(sc, RL_ISR, status);
2515 		if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) &&
2516 		    (sc->rl_flags & RL_FLAG_PCIE))
2517 			CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2518 
2519 		/*
2520 		 * XXX check behaviour on receiver stalls.
2521 		 */
2522 
2523 		if (status & RL_ISR_SYSTEM_ERR) {
2524 			ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2525 			re_init_locked(sc);
2526 		}
2527 	}
2528 	return (rx_npkts);
2529 }
2530 #endif /* DEVICE_POLLING */
2531 
2532 static int
2533 re_intr(void *arg)
2534 {
2535 	struct rl_softc		*sc;
2536 	uint16_t		status;
2537 
2538 	sc = arg;
2539 
2540 	status = CSR_READ_2(sc, RL_ISR);
2541 	if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0)
2542                 return (FILTER_STRAY);
2543 	CSR_WRITE_2(sc, RL_IMR, 0);
2544 
2545 	taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask);
2546 
2547 	return (FILTER_HANDLED);
2548 }
2549 
2550 static void
2551 re_int_task(void *arg, int npending)
2552 {
2553 	struct rl_softc		*sc;
2554 	struct ifnet		*ifp;
2555 	u_int16_t		status;
2556 	int			rval = 0;
2557 
2558 	sc = arg;
2559 	ifp = sc->rl_ifp;
2560 
2561 	RL_LOCK(sc);
2562 
2563 	status = CSR_READ_2(sc, RL_ISR);
2564         CSR_WRITE_2(sc, RL_ISR, status);
2565 
2566 	if (sc->suspended ||
2567 	    (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2568 		RL_UNLOCK(sc);
2569 		return;
2570 	}
2571 
2572 #ifdef DEVICE_POLLING
2573 	if  (ifp->if_capenable & IFCAP_POLLING) {
2574 		RL_UNLOCK(sc);
2575 		return;
2576 	}
2577 #endif
2578 
2579 	if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW))
2580 		rval = re_rxeof(sc, NULL);
2581 
2582 	/*
2583 	 * Some chips will ignore a second TX request issued
2584 	 * while an existing transmission is in progress. If
2585 	 * the transmitter goes idle but there are still
2586 	 * packets waiting to be sent, we need to restart the
2587 	 * channel here to flush them out. This only seems to
2588 	 * be required with the PCIe devices.
2589 	 */
2590 	if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) &&
2591 	    (sc->rl_flags & RL_FLAG_PCIE))
2592 		CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2593 	if (status & (
2594 #ifdef RE_TX_MODERATION
2595 	    RL_ISR_TIMEOUT_EXPIRED|
2596 #else
2597 	    RL_ISR_TX_OK|
2598 #endif
2599 	    RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL))
2600 		re_txeof(sc);
2601 
2602 	if (status & RL_ISR_SYSTEM_ERR) {
2603 		ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2604 		re_init_locked(sc);
2605 	}
2606 
2607 	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2608 		re_start_locked(ifp);
2609 
2610 	RL_UNLOCK(sc);
2611 
2612         if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) {
2613 		taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask);
2614 		return;
2615 	}
2616 
2617 	CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
2618 }
2619 
2620 static void
2621 re_intr_msi(void *xsc)
2622 {
2623 	struct rl_softc		*sc;
2624 	struct ifnet		*ifp;
2625 	uint16_t		intrs, status;
2626 
2627 	sc = xsc;
2628 	RL_LOCK(sc);
2629 
2630 	ifp = sc->rl_ifp;
2631 #ifdef DEVICE_POLLING
2632 	if (ifp->if_capenable & IFCAP_POLLING) {
2633 		RL_UNLOCK(sc);
2634 		return;
2635 	}
2636 #endif
2637 	/* Disable interrupts. */
2638 	CSR_WRITE_2(sc, RL_IMR, 0);
2639 	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2640 		RL_UNLOCK(sc);
2641 		return;
2642 	}
2643 
2644 	intrs = RL_INTRS_CPLUS;
2645 	status = CSR_READ_2(sc, RL_ISR);
2646         CSR_WRITE_2(sc, RL_ISR, status);
2647 	if (sc->rl_int_rx_act > 0) {
2648 		intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW |
2649 		    RL_ISR_RX_OVERRUN);
2650 		status &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW |
2651 		    RL_ISR_RX_OVERRUN);
2652 	}
2653 
2654 	if (status & (RL_ISR_TIMEOUT_EXPIRED | RL_ISR_RX_OK | RL_ISR_RX_ERR |
2655 	    RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) {
2656 		re_rxeof(sc, NULL);
2657 		if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2658 			if (sc->rl_int_rx_mod != 0 &&
2659 			    (status & (RL_ISR_RX_OK | RL_ISR_RX_ERR |
2660 			    RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) != 0) {
2661 				/* Rearm one-shot timer. */
2662 				CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2663 				intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR |
2664 				    RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN);
2665 				sc->rl_int_rx_act = 1;
2666 			} else {
2667 				intrs |= RL_ISR_RX_OK | RL_ISR_RX_ERR |
2668 				    RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN;
2669 				sc->rl_int_rx_act = 0;
2670 			}
2671 		}
2672 	}
2673 
2674 	/*
2675 	 * Some chips will ignore a second TX request issued
2676 	 * while an existing transmission is in progress. If
2677 	 * the transmitter goes idle but there are still
2678 	 * packets waiting to be sent, we need to restart the
2679 	 * channel here to flush them out. This only seems to
2680 	 * be required with the PCIe devices.
2681 	 */
2682 	if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) &&
2683 	    (sc->rl_flags & RL_FLAG_PCIE))
2684 		CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2685 	if (status & (RL_ISR_TX_OK | RL_ISR_TX_ERR | RL_ISR_TX_DESC_UNAVAIL))
2686 		re_txeof(sc);
2687 
2688 	if (status & RL_ISR_SYSTEM_ERR) {
2689 		ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2690 		re_init_locked(sc);
2691 	}
2692 
2693 	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2694 		if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2695 			re_start_locked(ifp);
2696 		CSR_WRITE_2(sc, RL_IMR, intrs);
2697 	}
2698 	RL_UNLOCK(sc);
2699 }
2700 
2701 static int
2702 re_encap(struct rl_softc *sc, struct mbuf **m_head)
2703 {
2704 	struct rl_txdesc	*txd, *txd_last;
2705 	bus_dma_segment_t	segs[RL_NTXSEGS];
2706 	bus_dmamap_t		map;
2707 	struct mbuf		*m_new;
2708 	struct rl_desc		*desc;
2709 	int			nsegs, prod;
2710 	int			i, error, ei, si;
2711 	int			padlen;
2712 	uint32_t		cmdstat, csum_flags, vlanctl;
2713 
2714 	RL_LOCK_ASSERT(sc);
2715 	M_ASSERTPKTHDR((*m_head));
2716 
2717 	/*
2718 	 * With some of the RealTek chips, using the checksum offload
2719 	 * support in conjunction with the autopadding feature results
2720 	 * in the transmission of corrupt frames. For example, if we
2721 	 * need to send a really small IP fragment that's less than 60
2722 	 * bytes in size, and IP header checksumming is enabled, the
2723 	 * resulting ethernet frame that appears on the wire will
2724 	 * have garbled payload. To work around this, if TX IP checksum
2725 	 * offload is enabled, we always manually pad short frames out
2726 	 * to the minimum ethernet frame size.
2727 	 */
2728 	if ((sc->rl_flags & RL_FLAG_AUTOPAD) == 0 &&
2729 	    (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN &&
2730 	    ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) {
2731 		padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len;
2732 		if (M_WRITABLE(*m_head) == 0) {
2733 			/* Get a writable copy. */
2734 			m_new = m_dup(*m_head, M_NOWAIT);
2735 			m_freem(*m_head);
2736 			if (m_new == NULL) {
2737 				*m_head = NULL;
2738 				return (ENOBUFS);
2739 			}
2740 			*m_head = m_new;
2741 		}
2742 		if ((*m_head)->m_next != NULL ||
2743 		    M_TRAILINGSPACE(*m_head) < padlen) {
2744 			m_new = m_defrag(*m_head, M_NOWAIT);
2745 			if (m_new == NULL) {
2746 				m_freem(*m_head);
2747 				*m_head = NULL;
2748 				return (ENOBUFS);
2749 			}
2750 		} else
2751 			m_new = *m_head;
2752 
2753 		/*
2754 		 * Manually pad short frames, and zero the pad space
2755 		 * to avoid leaking data.
2756 		 */
2757 		bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen);
2758 		m_new->m_pkthdr.len += padlen;
2759 		m_new->m_len = m_new->m_pkthdr.len;
2760 		*m_head = m_new;
2761 	}
2762 
2763 	prod = sc->rl_ldata.rl_tx_prodidx;
2764 	txd = &sc->rl_ldata.rl_tx_desc[prod];
2765 	error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap,
2766 	    *m_head, segs, &nsegs, BUS_DMA_NOWAIT);
2767 	if (error == EFBIG) {
2768 		m_new = m_collapse(*m_head, M_NOWAIT, RL_NTXSEGS);
2769 		if (m_new == NULL) {
2770 			m_freem(*m_head);
2771 			*m_head = NULL;
2772 			return (ENOBUFS);
2773 		}
2774 		*m_head = m_new;
2775 		error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag,
2776 		    txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT);
2777 		if (error != 0) {
2778 			m_freem(*m_head);
2779 			*m_head = NULL;
2780 			return (error);
2781 		}
2782 	} else if (error != 0)
2783 		return (error);
2784 	if (nsegs == 0) {
2785 		m_freem(*m_head);
2786 		*m_head = NULL;
2787 		return (EIO);
2788 	}
2789 
2790 	/* Check for number of available descriptors. */
2791 	if (sc->rl_ldata.rl_tx_free - nsegs <= 1) {
2792 		bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap);
2793 		return (ENOBUFS);
2794 	}
2795 
2796 	bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap,
2797 	    BUS_DMASYNC_PREWRITE);
2798 
2799 	/*
2800 	 * Set up checksum offload. Note: checksum offload bits must
2801 	 * appear in all descriptors of a multi-descriptor transmit
2802 	 * attempt. This is according to testing done with an 8169
2803 	 * chip. This is a requirement.
2804 	 */
2805 	vlanctl = 0;
2806 	csum_flags = 0;
2807 	if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
2808 		if ((sc->rl_flags & RL_FLAG_DESCV2) != 0) {
2809 			csum_flags |= RL_TDESC_CMD_LGSEND;
2810 			vlanctl |= ((uint32_t)(*m_head)->m_pkthdr.tso_segsz <<
2811 			    RL_TDESC_CMD_MSSVALV2_SHIFT);
2812 		} else {
2813 			csum_flags |= RL_TDESC_CMD_LGSEND |
2814 			    ((uint32_t)(*m_head)->m_pkthdr.tso_segsz <<
2815 			    RL_TDESC_CMD_MSSVAL_SHIFT);
2816 		}
2817 	} else {
2818 		/*
2819 		 * Unconditionally enable IP checksum if TCP or UDP
2820 		 * checksum is required. Otherwise, TCP/UDP checksum
2821 		 * doesn't make effects.
2822 		 */
2823 		if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) {
2824 			if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) {
2825 				csum_flags |= RL_TDESC_CMD_IPCSUM;
2826 				if (((*m_head)->m_pkthdr.csum_flags &
2827 				    CSUM_TCP) != 0)
2828 					csum_flags |= RL_TDESC_CMD_TCPCSUM;
2829 				if (((*m_head)->m_pkthdr.csum_flags &
2830 				    CSUM_UDP) != 0)
2831 					csum_flags |= RL_TDESC_CMD_UDPCSUM;
2832 			} else {
2833 				vlanctl |= RL_TDESC_CMD_IPCSUMV2;
2834 				if (((*m_head)->m_pkthdr.csum_flags &
2835 				    CSUM_TCP) != 0)
2836 					vlanctl |= RL_TDESC_CMD_TCPCSUMV2;
2837 				if (((*m_head)->m_pkthdr.csum_flags &
2838 				    CSUM_UDP) != 0)
2839 					vlanctl |= RL_TDESC_CMD_UDPCSUMV2;
2840 			}
2841 		}
2842 	}
2843 
2844 	/*
2845 	 * Set up hardware VLAN tagging. Note: vlan tag info must
2846 	 * appear in all descriptors of a multi-descriptor
2847 	 * transmission attempt.
2848 	 */
2849 	if ((*m_head)->m_flags & M_VLANTAG)
2850 		vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) |
2851 		    RL_TDESC_VLANCTL_TAG;
2852 
2853 	si = prod;
2854 	for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) {
2855 		desc = &sc->rl_ldata.rl_tx_list[prod];
2856 		desc->rl_vlanctl = htole32(vlanctl);
2857 		desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr));
2858 		desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr));
2859 		cmdstat = segs[i].ds_len;
2860 		if (i != 0)
2861 			cmdstat |= RL_TDESC_CMD_OWN;
2862 		if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1)
2863 			cmdstat |= RL_TDESC_CMD_EOR;
2864 		desc->rl_cmdstat = htole32(cmdstat | csum_flags);
2865 		sc->rl_ldata.rl_tx_free--;
2866 	}
2867 	/* Update producer index. */
2868 	sc->rl_ldata.rl_tx_prodidx = prod;
2869 
2870 	/* Set EOF on the last descriptor. */
2871 	ei = RL_TX_DESC_PRV(sc, prod);
2872 	desc = &sc->rl_ldata.rl_tx_list[ei];
2873 	desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF);
2874 
2875 	desc = &sc->rl_ldata.rl_tx_list[si];
2876 	/* Set SOF and transfer ownership of packet to the chip. */
2877 	desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF);
2878 
2879 	/*
2880 	 * Insure that the map for this transmission
2881 	 * is placed at the array index of the last descriptor
2882 	 * in this chain.  (Swap last and first dmamaps.)
2883 	 */
2884 	txd_last = &sc->rl_ldata.rl_tx_desc[ei];
2885 	map = txd->tx_dmamap;
2886 	txd->tx_dmamap = txd_last->tx_dmamap;
2887 	txd_last->tx_dmamap = map;
2888 	txd_last->tx_m = *m_head;
2889 
2890 	return (0);
2891 }
2892 
2893 static void
2894 re_start(struct ifnet *ifp)
2895 {
2896 	struct rl_softc		*sc;
2897 
2898 	sc = ifp->if_softc;
2899 	RL_LOCK(sc);
2900 	re_start_locked(ifp);
2901 	RL_UNLOCK(sc);
2902 }
2903 
2904 /*
2905  * Main transmit routine for C+ and gigE NICs.
2906  */
2907 static void
2908 re_start_locked(struct ifnet *ifp)
2909 {
2910 	struct rl_softc		*sc;
2911 	struct mbuf		*m_head;
2912 	int			queued;
2913 
2914 	sc = ifp->if_softc;
2915 
2916 #ifdef DEV_NETMAP
2917 	/* XXX is this necessary ? */
2918 	if (ifp->if_capenable & IFCAP_NETMAP) {
2919 		struct netmap_kring *kring = &NA(ifp)->tx_rings[0];
2920 		if (sc->rl_ldata.rl_tx_prodidx != kring->nr_hwcur) {
2921 			/* kick the tx unit */
2922 			CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2923 #ifdef RE_TX_MODERATION
2924 			CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2925 #endif
2926 			sc->rl_watchdog_timer = 5;
2927 		}
2928 		return;
2929 	}
2930 #endif /* DEV_NETMAP */
2931 	if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2932 	    IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0)
2933 		return;
2934 
2935 	for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2936 	    sc->rl_ldata.rl_tx_free > 1;) {
2937 		IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2938 		if (m_head == NULL)
2939 			break;
2940 
2941 		if (re_encap(sc, &m_head) != 0) {
2942 			if (m_head == NULL)
2943 				break;
2944 			IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2945 			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2946 			break;
2947 		}
2948 
2949 		/*
2950 		 * If there's a BPF listener, bounce a copy of this frame
2951 		 * to him.
2952 		 */
2953 		ETHER_BPF_MTAP(ifp, m_head);
2954 
2955 		queued++;
2956 	}
2957 
2958 	if (queued == 0) {
2959 #ifdef RE_TX_MODERATION
2960 		if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt)
2961 			CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2962 #endif
2963 		return;
2964 	}
2965 
2966 	/* Flush the TX descriptors */
2967 
2968 	bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
2969 	    sc->rl_ldata.rl_tx_list_map,
2970 	    BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
2971 
2972 	CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2973 
2974 #ifdef RE_TX_MODERATION
2975 	/*
2976 	 * Use the countdown timer for interrupt moderation.
2977 	 * 'TX done' interrupts are disabled. Instead, we reset the
2978 	 * countdown timer, which will begin counting until it hits
2979 	 * the value in the TIMERINT register, and then trigger an
2980 	 * interrupt. Each time we write to the TIMERCNT register,
2981 	 * the timer count is reset to 0.
2982 	 */
2983 	CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2984 #endif
2985 
2986 	/*
2987 	 * Set a timeout in case the chip goes out to lunch.
2988 	 */
2989 	sc->rl_watchdog_timer = 5;
2990 }
2991 
2992 static void
2993 re_set_jumbo(struct rl_softc *sc, int jumbo)
2994 {
2995 
2996 	if (sc->rl_hwrev->rl_rev == RL_HWREV_8168E_VL) {
2997 		pci_set_max_read_req(sc->rl_dev, 4096);
2998 		return;
2999 	}
3000 
3001 	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
3002 	if (jumbo != 0) {
3003 		CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) |
3004 		    RL_CFG3_JUMBO_EN0);
3005 		switch (sc->rl_hwrev->rl_rev) {
3006 		case RL_HWREV_8168DP:
3007 			break;
3008 		case RL_HWREV_8168E:
3009 			CSR_WRITE_1(sc, sc->rl_cfg4,
3010 			    CSR_READ_1(sc, sc->rl_cfg4) | 0x01);
3011 			break;
3012 		default:
3013 			CSR_WRITE_1(sc, sc->rl_cfg4,
3014 			    CSR_READ_1(sc, sc->rl_cfg4) | RL_CFG4_JUMBO_EN1);
3015 		}
3016 	} else {
3017 		CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) &
3018 		    ~RL_CFG3_JUMBO_EN0);
3019 		switch (sc->rl_hwrev->rl_rev) {
3020 		case RL_HWREV_8168DP:
3021 			break;
3022 		case RL_HWREV_8168E:
3023 			CSR_WRITE_1(sc, sc->rl_cfg4,
3024 			    CSR_READ_1(sc, sc->rl_cfg4) & ~0x01);
3025 			break;
3026 		default:
3027 			CSR_WRITE_1(sc, sc->rl_cfg4,
3028 			    CSR_READ_1(sc, sc->rl_cfg4) & ~RL_CFG4_JUMBO_EN1);
3029 		}
3030 	}
3031 	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
3032 
3033 	switch (sc->rl_hwrev->rl_rev) {
3034 	case RL_HWREV_8168DP:
3035 		pci_set_max_read_req(sc->rl_dev, 4096);
3036 		break;
3037 	default:
3038 		if (jumbo != 0)
3039 			pci_set_max_read_req(sc->rl_dev, 512);
3040 		else
3041 			pci_set_max_read_req(sc->rl_dev, 4096);
3042 	}
3043 }
3044 
3045 static void
3046 re_init(void *xsc)
3047 {
3048 	struct rl_softc		*sc = xsc;
3049 
3050 	RL_LOCK(sc);
3051 	re_init_locked(sc);
3052 	RL_UNLOCK(sc);
3053 }
3054 
3055 static void
3056 re_init_locked(struct rl_softc *sc)
3057 {
3058 	struct ifnet		*ifp = sc->rl_ifp;
3059 	struct mii_data		*mii;
3060 	uint32_t		reg;
3061 	uint16_t		cfg;
3062 	union {
3063 		uint32_t align_dummy;
3064 		u_char eaddr[ETHER_ADDR_LEN];
3065         } eaddr;
3066 
3067 	RL_LOCK_ASSERT(sc);
3068 
3069 	mii = device_get_softc(sc->rl_miibus);
3070 
3071 	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
3072 		return;
3073 
3074 	/*
3075 	 * Cancel pending I/O and free all RX/TX buffers.
3076 	 */
3077 	re_stop(sc);
3078 
3079 	/* Put controller into known state. */
3080 	re_reset(sc);
3081 
3082 	/*
3083 	 * For C+ mode, initialize the RX descriptors and mbufs.
3084 	 */
3085 	if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
3086 		if (ifp->if_mtu > RL_MTU) {
3087 			if (re_jrx_list_init(sc) != 0) {
3088 				device_printf(sc->rl_dev,
3089 				    "no memory for jumbo RX buffers\n");
3090 				re_stop(sc);
3091 				return;
3092 			}
3093 			/* Disable checksum offloading for jumbo frames. */
3094 			ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_TSO4);
3095 			ifp->if_hwassist &= ~(RE_CSUM_FEATURES | CSUM_TSO);
3096 		} else {
3097 			if (re_rx_list_init(sc) != 0) {
3098 				device_printf(sc->rl_dev,
3099 				    "no memory for RX buffers\n");
3100 				re_stop(sc);
3101 				return;
3102 			}
3103 		}
3104 		re_set_jumbo(sc, ifp->if_mtu > RL_MTU);
3105 	} else {
3106 		if (re_rx_list_init(sc) != 0) {
3107 			device_printf(sc->rl_dev, "no memory for RX buffers\n");
3108 			re_stop(sc);
3109 			return;
3110 		}
3111 		if ((sc->rl_flags & RL_FLAG_PCIE) != 0 &&
3112 		    pci_get_device(sc->rl_dev) != RT_DEVICEID_8101E) {
3113 			if (ifp->if_mtu > RL_MTU)
3114 				pci_set_max_read_req(sc->rl_dev, 512);
3115 			else
3116 				pci_set_max_read_req(sc->rl_dev, 4096);
3117 		}
3118 	}
3119 	re_tx_list_init(sc);
3120 
3121 	/*
3122 	 * Enable C+ RX and TX mode, as well as VLAN stripping and
3123 	 * RX checksum offload. We must configure the C+ register
3124 	 * before all others.
3125 	 */
3126 	cfg = RL_CPLUSCMD_PCI_MRW;
3127 	if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
3128 		cfg |= RL_CPLUSCMD_RXCSUM_ENB;
3129 	if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
3130 		cfg |= RL_CPLUSCMD_VLANSTRIP;
3131 	if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) {
3132 		cfg |= RL_CPLUSCMD_MACSTAT_DIS;
3133 		/* XXX magic. */
3134 		cfg |= 0x0001;
3135 	} else
3136 		cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB;
3137 	CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg);
3138 	if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SC ||
3139 	    sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) {
3140 		reg = 0x000fff00;
3141 		if ((CSR_READ_1(sc, sc->rl_cfg2) & RL_CFG2_PCI66MHZ) != 0)
3142 			reg |= 0x000000ff;
3143 		if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE)
3144 			reg |= 0x00f00000;
3145 		CSR_WRITE_4(sc, 0x7c, reg);
3146 		/* Disable interrupt mitigation. */
3147 		CSR_WRITE_2(sc, 0xe2, 0);
3148 	}
3149 	/*
3150 	 * Disable TSO if interface MTU size is greater than MSS
3151 	 * allowed in controller.
3152 	 */
3153 	if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) {
3154 		ifp->if_capenable &= ~IFCAP_TSO4;
3155 		ifp->if_hwassist &= ~CSUM_TSO;
3156 	}
3157 
3158 	/*
3159 	 * Init our MAC address.  Even though the chipset
3160 	 * documentation doesn't mention it, we need to enter "Config
3161 	 * register write enable" mode to modify the ID registers.
3162 	 */
3163 	/* Copy MAC address on stack to align. */
3164 	bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN);
3165 	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
3166 	CSR_WRITE_4(sc, RL_IDR0,
3167 	    htole32(*(u_int32_t *)(&eaddr.eaddr[0])));
3168 	CSR_WRITE_4(sc, RL_IDR4,
3169 	    htole32(*(u_int32_t *)(&eaddr.eaddr[4])));
3170 	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
3171 
3172 	/*
3173 	 * Load the addresses of the RX and TX lists into the chip.
3174 	 */
3175 
3176 	CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI,
3177 	    RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr));
3178 	CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO,
3179 	    RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr));
3180 
3181 	CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI,
3182 	    RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr));
3183 	CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO,
3184 	    RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr));
3185 
3186 	if ((sc->rl_flags & RL_FLAG_RXDV_GATED) != 0)
3187 		CSR_WRITE_4(sc, RL_MISC, CSR_READ_4(sc, RL_MISC) &
3188 		    ~0x00080000);
3189 
3190 	/*
3191 	 * Enable transmit and receive.
3192 	 */
3193 	CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
3194 
3195 	/*
3196 	 * Set the initial TX configuration.
3197 	 */
3198 	if (sc->rl_testmode) {
3199 		if (sc->rl_type == RL_8169)
3200 			CSR_WRITE_4(sc, RL_TXCFG,
3201 			    RL_TXCFG_CONFIG|RL_LOOPTEST_ON);
3202 		else
3203 			CSR_WRITE_4(sc, RL_TXCFG,
3204 			    RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS);
3205 	} else
3206 		CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
3207 
3208 	CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16);
3209 
3210 	/*
3211 	 * Set the initial RX configuration.
3212 	 */
3213 	re_set_rxmode(sc);
3214 
3215 	/* Configure interrupt moderation. */
3216 	if (sc->rl_type == RL_8169) {
3217 		/* Magic from vendor. */
3218 		CSR_WRITE_2(sc, RL_INTRMOD, 0x5100);
3219 	}
3220 
3221 #ifdef DEVICE_POLLING
3222 	/*
3223 	 * Disable interrupts if we are polling.
3224 	 */
3225 	if (ifp->if_capenable & IFCAP_POLLING)
3226 		CSR_WRITE_2(sc, RL_IMR, 0);
3227 	else	/* otherwise ... */
3228 #endif
3229 
3230 	/*
3231 	 * Enable interrupts.
3232 	 */
3233 	if (sc->rl_testmode)
3234 		CSR_WRITE_2(sc, RL_IMR, 0);
3235 	else
3236 		CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
3237 	CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS);
3238 
3239 	/* Set initial TX threshold */
3240 	sc->rl_txthresh = RL_TX_THRESH_INIT;
3241 
3242 	/* Start RX/TX process. */
3243 	CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
3244 #ifdef notdef
3245 	/* Enable receiver and transmitter. */
3246 	CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
3247 #endif
3248 
3249 	/*
3250 	 * Initialize the timer interrupt register so that
3251 	 * a timer interrupt will be generated once the timer
3252 	 * reaches a certain number of ticks. The timer is
3253 	 * reloaded on each transmit.
3254 	 */
3255 #ifdef RE_TX_MODERATION
3256 	/*
3257 	 * Use timer interrupt register to moderate TX interrupt
3258 	 * moderation, which dramatically improves TX frame rate.
3259 	 */
3260 	if (sc->rl_type == RL_8169)
3261 		CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800);
3262 	else
3263 		CSR_WRITE_4(sc, RL_TIMERINT, 0x400);
3264 #else
3265 	/*
3266 	 * Use timer interrupt register to moderate RX interrupt
3267 	 * moderation.
3268 	 */
3269 	if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 &&
3270 	    intr_filter == 0) {
3271 		if (sc->rl_type == RL_8169)
3272 			CSR_WRITE_4(sc, RL_TIMERINT_8169,
3273 			    RL_USECS(sc->rl_int_rx_mod));
3274 	} else {
3275 		if (sc->rl_type == RL_8169)
3276 			CSR_WRITE_4(sc, RL_TIMERINT_8169, RL_USECS(0));
3277 	}
3278 #endif
3279 
3280 	/*
3281 	 * For 8169 gigE NICs, set the max allowed RX packet
3282 	 * size so we can receive jumbo frames.
3283 	 */
3284 	if (sc->rl_type == RL_8169) {
3285 		if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
3286 			/*
3287 			 * For controllers that use new jumbo frame scheme,
3288 			 * set maximum size of jumbo frame depending on
3289 			 * controller revisions.
3290 			 */
3291 			if (ifp->if_mtu > RL_MTU)
3292 				CSR_WRITE_2(sc, RL_MAXRXPKTLEN,
3293 				    sc->rl_hwrev->rl_max_mtu +
3294 				    ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN +
3295 				    ETHER_CRC_LEN);
3296 			else
3297 				CSR_WRITE_2(sc, RL_MAXRXPKTLEN,
3298 				    RE_RX_DESC_BUFLEN);
3299 		} else if ((sc->rl_flags & RL_FLAG_PCIE) != 0 &&
3300 		    sc->rl_hwrev->rl_max_mtu == RL_MTU) {
3301 			/* RTL810x has no jumbo frame support. */
3302 			CSR_WRITE_2(sc, RL_MAXRXPKTLEN, RE_RX_DESC_BUFLEN);
3303 		} else
3304 			CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383);
3305 	}
3306 
3307 	if (sc->rl_testmode)
3308 		return;
3309 
3310 	CSR_WRITE_1(sc, sc->rl_cfg1, CSR_READ_1(sc, sc->rl_cfg1) |
3311 	    RL_CFG1_DRVLOAD);
3312 
3313 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
3314 	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3315 
3316 	sc->rl_flags &= ~RL_FLAG_LINK;
3317 	mii_mediachg(mii);
3318 
3319 	sc->rl_watchdog_timer = 0;
3320 	callout_reset(&sc->rl_stat_callout, hz, re_tick, sc);
3321 }
3322 
3323 /*
3324  * Set media options.
3325  */
3326 static int
3327 re_ifmedia_upd(struct ifnet *ifp)
3328 {
3329 	struct rl_softc		*sc;
3330 	struct mii_data		*mii;
3331 	int			error;
3332 
3333 	sc = ifp->if_softc;
3334 	mii = device_get_softc(sc->rl_miibus);
3335 	RL_LOCK(sc);
3336 	error = mii_mediachg(mii);
3337 	RL_UNLOCK(sc);
3338 
3339 	return (error);
3340 }
3341 
3342 /*
3343  * Report current media status.
3344  */
3345 static void
3346 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3347 {
3348 	struct rl_softc		*sc;
3349 	struct mii_data		*mii;
3350 
3351 	sc = ifp->if_softc;
3352 	mii = device_get_softc(sc->rl_miibus);
3353 
3354 	RL_LOCK(sc);
3355 	mii_pollstat(mii);
3356 	ifmr->ifm_active = mii->mii_media_active;
3357 	ifmr->ifm_status = mii->mii_media_status;
3358 	RL_UNLOCK(sc);
3359 }
3360 
3361 static int
3362 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3363 {
3364 	struct rl_softc		*sc = ifp->if_softc;
3365 	struct ifreq		*ifr = (struct ifreq *) data;
3366 	struct mii_data		*mii;
3367 	uint32_t		rev;
3368 	int			error = 0;
3369 
3370 	switch (command) {
3371 	case SIOCSIFMTU:
3372 		if (ifr->ifr_mtu < ETHERMIN ||
3373 		    ifr->ifr_mtu > sc->rl_hwrev->rl_max_mtu ||
3374 		    ((sc->rl_flags & RL_FLAG_FASTETHER) != 0 &&
3375 		    ifr->ifr_mtu > RL_MTU)) {
3376 			error = EINVAL;
3377 			break;
3378 		}
3379 		RL_LOCK(sc);
3380 		if (ifp->if_mtu != ifr->ifr_mtu) {
3381 			ifp->if_mtu = ifr->ifr_mtu;
3382 			if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 &&
3383 			    (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
3384 				ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3385 				re_init_locked(sc);
3386 			}
3387 			if (ifp->if_mtu > RL_TSO_MTU &&
3388 			    (ifp->if_capenable & IFCAP_TSO4) != 0) {
3389 				ifp->if_capenable &= ~(IFCAP_TSO4 |
3390 				    IFCAP_VLAN_HWTSO);
3391 				ifp->if_hwassist &= ~CSUM_TSO;
3392 			}
3393 			VLAN_CAPABILITIES(ifp);
3394 		}
3395 		RL_UNLOCK(sc);
3396 		break;
3397 	case SIOCSIFFLAGS:
3398 		RL_LOCK(sc);
3399 		if ((ifp->if_flags & IFF_UP) != 0) {
3400 			if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
3401 				if (((ifp->if_flags ^ sc->rl_if_flags)
3402 				    & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
3403 					re_set_rxmode(sc);
3404 			} else
3405 				re_init_locked(sc);
3406 		} else {
3407 			if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
3408 				re_stop(sc);
3409 		}
3410 		sc->rl_if_flags = ifp->if_flags;
3411 		RL_UNLOCK(sc);
3412 		break;
3413 	case SIOCADDMULTI:
3414 	case SIOCDELMULTI:
3415 		RL_LOCK(sc);
3416 		if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
3417 			re_set_rxmode(sc);
3418 		RL_UNLOCK(sc);
3419 		break;
3420 	case SIOCGIFMEDIA:
3421 	case SIOCSIFMEDIA:
3422 		mii = device_get_softc(sc->rl_miibus);
3423 		error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
3424 		break;
3425 	case SIOCSIFCAP:
3426 	    {
3427 		int mask, reinit;
3428 
3429 		mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3430 		reinit = 0;
3431 #ifdef DEVICE_POLLING
3432 		if (mask & IFCAP_POLLING) {
3433 			if (ifr->ifr_reqcap & IFCAP_POLLING) {
3434 				error = ether_poll_register(re_poll, ifp);
3435 				if (error)
3436 					return (error);
3437 				RL_LOCK(sc);
3438 				/* Disable interrupts */
3439 				CSR_WRITE_2(sc, RL_IMR, 0x0000);
3440 				ifp->if_capenable |= IFCAP_POLLING;
3441 				RL_UNLOCK(sc);
3442 			} else {
3443 				error = ether_poll_deregister(ifp);
3444 				/* Enable interrupts. */
3445 				RL_LOCK(sc);
3446 				CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
3447 				ifp->if_capenable &= ~IFCAP_POLLING;
3448 				RL_UNLOCK(sc);
3449 			}
3450 		}
3451 #endif /* DEVICE_POLLING */
3452 		RL_LOCK(sc);
3453 		if ((mask & IFCAP_TXCSUM) != 0 &&
3454 		    (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
3455 			ifp->if_capenable ^= IFCAP_TXCSUM;
3456 			if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) {
3457 				rev = sc->rl_hwrev->rl_rev;
3458 				if (rev == RL_HWREV_8168C ||
3459 				    rev == RL_HWREV_8168C_SPIN2 ||
3460 				    rev == RL_HWREV_8168CP)
3461 					ifp->if_hwassist |= CSUM_TCP | CSUM_UDP;
3462 				else
3463 					ifp->if_hwassist |= RE_CSUM_FEATURES;
3464 			} else
3465 				ifp->if_hwassist &= ~RE_CSUM_FEATURES;
3466 			reinit = 1;
3467 		}
3468 		if ((mask & IFCAP_RXCSUM) != 0 &&
3469 		    (ifp->if_capabilities & IFCAP_RXCSUM) != 0) {
3470 			ifp->if_capenable ^= IFCAP_RXCSUM;
3471 			reinit = 1;
3472 		}
3473 		if ((mask & IFCAP_TSO4) != 0 &&
3474 		    (ifp->if_capabilities & IFCAP_TSO4) != 0) {
3475 			ifp->if_capenable ^= IFCAP_TSO4;
3476 			if ((IFCAP_TSO4 & ifp->if_capenable) != 0)
3477 				ifp->if_hwassist |= CSUM_TSO;
3478 			else
3479 				ifp->if_hwassist &= ~CSUM_TSO;
3480 			if (ifp->if_mtu > RL_TSO_MTU &&
3481 			    (ifp->if_capenable & IFCAP_TSO4) != 0) {
3482 				ifp->if_capenable &= ~IFCAP_TSO4;
3483 				ifp->if_hwassist &= ~CSUM_TSO;
3484 			}
3485 		}
3486 		if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
3487 		    (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
3488 			ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
3489 		if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
3490 		    (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
3491 			ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
3492 			/* TSO over VLAN requires VLAN hardware tagging. */
3493 			if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
3494 				ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
3495 			reinit = 1;
3496 		}
3497 		if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 &&
3498 		    (mask & (IFCAP_HWCSUM | IFCAP_TSO4 |
3499 		    IFCAP_VLAN_HWTSO)) != 0)
3500 				reinit = 1;
3501 		if ((mask & IFCAP_WOL) != 0 &&
3502 		    (ifp->if_capabilities & IFCAP_WOL) != 0) {
3503 			if ((mask & IFCAP_WOL_UCAST) != 0)
3504 				ifp->if_capenable ^= IFCAP_WOL_UCAST;
3505 			if ((mask & IFCAP_WOL_MCAST) != 0)
3506 				ifp->if_capenable ^= IFCAP_WOL_MCAST;
3507 			if ((mask & IFCAP_WOL_MAGIC) != 0)
3508 				ifp->if_capenable ^= IFCAP_WOL_MAGIC;
3509 		}
3510 		if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) {
3511 			ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3512 			re_init_locked(sc);
3513 		}
3514 		RL_UNLOCK(sc);
3515 		VLAN_CAPABILITIES(ifp);
3516 	    }
3517 		break;
3518 	default:
3519 		error = ether_ioctl(ifp, command, data);
3520 		break;
3521 	}
3522 
3523 	return (error);
3524 }
3525 
3526 static void
3527 re_watchdog(struct rl_softc *sc)
3528 {
3529 	struct ifnet		*ifp;
3530 
3531 	RL_LOCK_ASSERT(sc);
3532 
3533 	if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0)
3534 		return;
3535 
3536 	ifp = sc->rl_ifp;
3537 	re_txeof(sc);
3538 	if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) {
3539 		if_printf(ifp, "watchdog timeout (missed Tx interrupts) "
3540 		    "-- recovering\n");
3541 		if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3542 			re_start_locked(ifp);
3543 		return;
3544 	}
3545 
3546 	if_printf(ifp, "watchdog timeout\n");
3547 	ifp->if_oerrors++;
3548 
3549 	re_rxeof(sc, NULL);
3550 	ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3551 	re_init_locked(sc);
3552 	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3553 		re_start_locked(ifp);
3554 }
3555 
3556 /*
3557  * Stop the adapter and free any mbufs allocated to the
3558  * RX and TX lists.
3559  */
3560 static void
3561 re_stop(struct rl_softc *sc)
3562 {
3563 	int			i;
3564 	struct ifnet		*ifp;
3565 	struct rl_txdesc	*txd;
3566 	struct rl_rxdesc	*rxd;
3567 
3568 	RL_LOCK_ASSERT(sc);
3569 
3570 	ifp = sc->rl_ifp;
3571 
3572 	sc->rl_watchdog_timer = 0;
3573 	callout_stop(&sc->rl_stat_callout);
3574 	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3575 
3576 	/*
3577 	 * Disable accepting frames to put RX MAC into idle state.
3578 	 * Otherwise it's possible to get frames while stop command
3579 	 * execution is in progress and controller can DMA the frame
3580 	 * to already freed RX buffer during that period.
3581 	 */
3582 	CSR_WRITE_4(sc, RL_RXCFG, CSR_READ_4(sc, RL_RXCFG) &
3583 	    ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_MULTI |
3584 	    RL_RXCFG_RX_BROAD));
3585 
3586 	if ((sc->rl_flags & RL_FLAG_WAIT_TXPOLL) != 0) {
3587 		for (i = RL_TIMEOUT; i > 0; i--) {
3588 			if ((CSR_READ_1(sc, sc->rl_txstart) &
3589 			    RL_TXSTART_START) == 0)
3590 				break;
3591 			DELAY(20);
3592 		}
3593 		if (i == 0)
3594 			device_printf(sc->rl_dev,
3595 			    "stopping TX poll timed out!\n");
3596 		CSR_WRITE_1(sc, RL_COMMAND, 0x00);
3597 	} else if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0) {
3598 		CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB |
3599 		    RL_CMD_RX_ENB);
3600 		if ((sc->rl_flags & RL_FLAG_CMDSTOP_WAIT_TXQ) != 0) {
3601 			for (i = RL_TIMEOUT; i > 0; i--) {
3602 				if ((CSR_READ_4(sc, RL_TXCFG) &
3603 				    RL_TXCFG_QUEUE_EMPTY) != 0)
3604 					break;
3605 				DELAY(100);
3606 			}
3607 			if (i == 0)
3608 				device_printf(sc->rl_dev,
3609 				   "stopping TXQ timed out!\n");
3610 		}
3611 	} else
3612 		CSR_WRITE_1(sc, RL_COMMAND, 0x00);
3613 	DELAY(1000);
3614 	CSR_WRITE_2(sc, RL_IMR, 0x0000);
3615 	CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
3616 
3617 	if (sc->rl_head != NULL) {
3618 		m_freem(sc->rl_head);
3619 		sc->rl_head = sc->rl_tail = NULL;
3620 	}
3621 
3622 	/* Free the TX list buffers. */
3623 	for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) {
3624 		txd = &sc->rl_ldata.rl_tx_desc[i];
3625 		if (txd->tx_m != NULL) {
3626 			bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag,
3627 			    txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
3628 			bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag,
3629 			    txd->tx_dmamap);
3630 			m_freem(txd->tx_m);
3631 			txd->tx_m = NULL;
3632 		}
3633 	}
3634 
3635 	/* Free the RX list buffers. */
3636 	for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
3637 		rxd = &sc->rl_ldata.rl_rx_desc[i];
3638 		if (rxd->rx_m != NULL) {
3639 			bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag,
3640 			    rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3641 			bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag,
3642 			    rxd->rx_dmamap);
3643 			m_freem(rxd->rx_m);
3644 			rxd->rx_m = NULL;
3645 		}
3646 	}
3647 
3648 	if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
3649 		for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
3650 			rxd = &sc->rl_ldata.rl_jrx_desc[i];
3651 			if (rxd->rx_m != NULL) {
3652 				bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag,
3653 				    rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3654 				bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag,
3655 				    rxd->rx_dmamap);
3656 				m_freem(rxd->rx_m);
3657 				rxd->rx_m = NULL;
3658 			}
3659 		}
3660 	}
3661 }
3662 
3663 /*
3664  * Device suspend routine.  Stop the interface and save some PCI
3665  * settings in case the BIOS doesn't restore them properly on
3666  * resume.
3667  */
3668 static int
3669 re_suspend(device_t dev)
3670 {
3671 	struct rl_softc		*sc;
3672 
3673 	sc = device_get_softc(dev);
3674 
3675 	RL_LOCK(sc);
3676 	re_stop(sc);
3677 	re_setwol(sc);
3678 	sc->suspended = 1;
3679 	RL_UNLOCK(sc);
3680 
3681 	return (0);
3682 }
3683 
3684 /*
3685  * Device resume routine.  Restore some PCI settings in case the BIOS
3686  * doesn't, re-enable busmastering, and restart the interface if
3687  * appropriate.
3688  */
3689 static int
3690 re_resume(device_t dev)
3691 {
3692 	struct rl_softc		*sc;
3693 	struct ifnet		*ifp;
3694 
3695 	sc = device_get_softc(dev);
3696 
3697 	RL_LOCK(sc);
3698 
3699 	ifp = sc->rl_ifp;
3700 	/* Take controller out of sleep mode. */
3701 	if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) {
3702 		if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80)
3703 			CSR_WRITE_1(sc, RL_GPIO,
3704 			    CSR_READ_1(sc, RL_GPIO) | 0x01);
3705 	}
3706 
3707 	/*
3708 	 * Clear WOL matching such that normal Rx filtering
3709 	 * wouldn't interfere with WOL patterns.
3710 	 */
3711 	re_clrwol(sc);
3712 
3713 	/* reinitialize interface if necessary */
3714 	if (ifp->if_flags & IFF_UP)
3715 		re_init_locked(sc);
3716 
3717 	sc->suspended = 0;
3718 	RL_UNLOCK(sc);
3719 
3720 	return (0);
3721 }
3722 
3723 /*
3724  * Stop all chip I/O so that the kernel's probe routines don't
3725  * get confused by errant DMAs when rebooting.
3726  */
3727 static int
3728 re_shutdown(device_t dev)
3729 {
3730 	struct rl_softc		*sc;
3731 
3732 	sc = device_get_softc(dev);
3733 
3734 	RL_LOCK(sc);
3735 	re_stop(sc);
3736 	/*
3737 	 * Mark interface as down since otherwise we will panic if
3738 	 * interrupt comes in later on, which can happen in some
3739 	 * cases.
3740 	 */
3741 	sc->rl_ifp->if_flags &= ~IFF_UP;
3742 	re_setwol(sc);
3743 	RL_UNLOCK(sc);
3744 
3745 	return (0);
3746 }
3747 
3748 static void
3749 re_set_linkspeed(struct rl_softc *sc)
3750 {
3751 	struct mii_softc *miisc;
3752 	struct mii_data *mii;
3753 	int aneg, i, phyno;
3754 
3755 	RL_LOCK_ASSERT(sc);
3756 
3757 	mii = device_get_softc(sc->rl_miibus);
3758 	mii_pollstat(mii);
3759 	aneg = 0;
3760 	if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
3761 	    (IFM_ACTIVE | IFM_AVALID)) {
3762 		switch IFM_SUBTYPE(mii->mii_media_active) {
3763 		case IFM_10_T:
3764 		case IFM_100_TX:
3765 			return;
3766 		case IFM_1000_T:
3767 			aneg++;
3768 			break;
3769 		default:
3770 			break;
3771 		}
3772 	}
3773 	miisc = LIST_FIRST(&mii->mii_phys);
3774 	phyno = miisc->mii_phy;
3775 	LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3776 		PHY_RESET(miisc);
3777 	re_miibus_writereg(sc->rl_dev, phyno, MII_100T2CR, 0);
3778 	re_miibus_writereg(sc->rl_dev, phyno,
3779 	    MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
3780 	re_miibus_writereg(sc->rl_dev, phyno,
3781 	    MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG);
3782 	DELAY(1000);
3783 	if (aneg != 0) {
3784 		/*
3785 		 * Poll link state until re(4) get a 10/100Mbps link.
3786 		 */
3787 		for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
3788 			mii_pollstat(mii);
3789 			if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID))
3790 			    == (IFM_ACTIVE | IFM_AVALID)) {
3791 				switch (IFM_SUBTYPE(mii->mii_media_active)) {
3792 				case IFM_10_T:
3793 				case IFM_100_TX:
3794 					return;
3795 				default:
3796 					break;
3797 				}
3798 			}
3799 			RL_UNLOCK(sc);
3800 			pause("relnk", hz);
3801 			RL_LOCK(sc);
3802 		}
3803 		if (i == MII_ANEGTICKS_GIGE)
3804 			device_printf(sc->rl_dev,
3805 			    "establishing a link failed, WOL may not work!");
3806 	}
3807 	/*
3808 	 * No link, force MAC to have 100Mbps, full-duplex link.
3809 	 * MAC does not require reprogramming on resolved speed/duplex,
3810 	 * so this is just for completeness.
3811 	 */
3812 	mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
3813 	mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
3814 }
3815 
3816 static void
3817 re_setwol(struct rl_softc *sc)
3818 {
3819 	struct ifnet		*ifp;
3820 	int			pmc;
3821 	uint16_t		pmstat;
3822 	uint8_t			v;
3823 
3824 	RL_LOCK_ASSERT(sc);
3825 
3826 	if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
3827 		return;
3828 
3829 	ifp = sc->rl_ifp;
3830 	/* Put controller into sleep mode. */
3831 	if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) {
3832 		if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80)
3833 			CSR_WRITE_1(sc, RL_GPIO,
3834 			    CSR_READ_1(sc, RL_GPIO) & ~0x01);
3835 	}
3836 	if ((ifp->if_capenable & IFCAP_WOL) != 0) {
3837 		re_set_rxmode(sc);
3838 		if ((sc->rl_flags & RL_FLAG_WOL_MANLINK) != 0)
3839 			re_set_linkspeed(sc);
3840 		if ((sc->rl_flags & RL_FLAG_WOLRXENB) != 0)
3841 			CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB);
3842 	}
3843 	/* Enable config register write. */
3844 	CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
3845 
3846 	/* Enable PME. */
3847 	v = CSR_READ_1(sc, sc->rl_cfg1);
3848 	v &= ~RL_CFG1_PME;
3849 	if ((ifp->if_capenable & IFCAP_WOL) != 0)
3850 		v |= RL_CFG1_PME;
3851 	CSR_WRITE_1(sc, sc->rl_cfg1, v);
3852 
3853 	v = CSR_READ_1(sc, sc->rl_cfg3);
3854 	v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
3855 	if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
3856 		v |= RL_CFG3_WOL_MAGIC;
3857 	CSR_WRITE_1(sc, sc->rl_cfg3, v);
3858 
3859 	v = CSR_READ_1(sc, sc->rl_cfg5);
3860 	v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST |
3861 	    RL_CFG5_WOL_LANWAKE);
3862 	if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0)
3863 		v |= RL_CFG5_WOL_UCAST;
3864 	if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
3865 		v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST;
3866 	if ((ifp->if_capenable & IFCAP_WOL) != 0)
3867 		v |= RL_CFG5_WOL_LANWAKE;
3868 	CSR_WRITE_1(sc, sc->rl_cfg5, v);
3869 
3870 	/* Config register write done. */
3871 	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
3872 
3873 	if ((ifp->if_capenable & IFCAP_WOL) == 0 &&
3874 	    (sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0)
3875 		CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) & ~0x80);
3876 	/*
3877 	 * It seems that hardware resets its link speed to 100Mbps in
3878 	 * power down mode so switching to 100Mbps in driver is not
3879 	 * needed.
3880 	 */
3881 
3882 	/* Request PME if WOL is requested. */
3883 	pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2);
3884 	pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
3885 	if ((ifp->if_capenable & IFCAP_WOL) != 0)
3886 		pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3887 	pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
3888 }
3889 
3890 static void
3891 re_clrwol(struct rl_softc *sc)
3892 {
3893 	int			pmc;
3894 	uint8_t			v;
3895 
3896 	RL_LOCK_ASSERT(sc);
3897 
3898 	if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
3899 		return;
3900 
3901 	/* Enable config register write. */
3902 	CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
3903 
3904 	v = CSR_READ_1(sc, sc->rl_cfg3);
3905 	v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
3906 	CSR_WRITE_1(sc, sc->rl_cfg3, v);
3907 
3908 	/* Config register write done. */
3909 	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
3910 
3911 	v = CSR_READ_1(sc, sc->rl_cfg5);
3912 	v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST);
3913 	v &= ~RL_CFG5_WOL_LANWAKE;
3914 	CSR_WRITE_1(sc, sc->rl_cfg5, v);
3915 }
3916 
3917 static void
3918 re_add_sysctls(struct rl_softc *sc)
3919 {
3920 	struct sysctl_ctx_list	*ctx;
3921 	struct sysctl_oid_list	*children;
3922 	int			error;
3923 
3924 	ctx = device_get_sysctl_ctx(sc->rl_dev);
3925 	children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev));
3926 
3927 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "stats",
3928 	    CTLTYPE_INT | CTLFLAG_RW, sc, 0, re_sysctl_stats, "I",
3929 	    "Statistics Information");
3930 	if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0)
3931 		return;
3932 
3933 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "int_rx_mod",
3934 	    CTLTYPE_INT | CTLFLAG_RW, &sc->rl_int_rx_mod, 0,
3935 	    sysctl_hw_re_int_mod, "I", "re RX interrupt moderation");
3936 	/* Pull in device tunables. */
3937 	sc->rl_int_rx_mod = RL_TIMER_DEFAULT;
3938 	error = resource_int_value(device_get_name(sc->rl_dev),
3939 	    device_get_unit(sc->rl_dev), "int_rx_mod", &sc->rl_int_rx_mod);
3940 	if (error == 0) {
3941 		if (sc->rl_int_rx_mod < RL_TIMER_MIN ||
3942 		    sc->rl_int_rx_mod > RL_TIMER_MAX) {
3943 			device_printf(sc->rl_dev, "int_rx_mod value out of "
3944 			    "range; using default: %d\n",
3945 			    RL_TIMER_DEFAULT);
3946 			sc->rl_int_rx_mod = RL_TIMER_DEFAULT;
3947 		}
3948 	}
3949 
3950 }
3951 
3952 static int
3953 re_sysctl_stats(SYSCTL_HANDLER_ARGS)
3954 {
3955 	struct rl_softc		*sc;
3956 	struct rl_stats		*stats;
3957 	int			error, i, result;
3958 
3959 	result = -1;
3960 	error = sysctl_handle_int(oidp, &result, 0, req);
3961 	if (error || req->newptr == NULL)
3962 		return (error);
3963 
3964 	if (result == 1) {
3965 		sc = (struct rl_softc *)arg1;
3966 		RL_LOCK(sc);
3967 		if ((sc->rl_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
3968 			RL_UNLOCK(sc);
3969 			goto done;
3970 		}
3971 		bus_dmamap_sync(sc->rl_ldata.rl_stag,
3972 		    sc->rl_ldata.rl_smap, BUS_DMASYNC_PREREAD);
3973 		CSR_WRITE_4(sc, RL_DUMPSTATS_HI,
3974 		    RL_ADDR_HI(sc->rl_ldata.rl_stats_addr));
3975 		CSR_WRITE_4(sc, RL_DUMPSTATS_LO,
3976 		    RL_ADDR_LO(sc->rl_ldata.rl_stats_addr));
3977 		CSR_WRITE_4(sc, RL_DUMPSTATS_LO,
3978 		    RL_ADDR_LO(sc->rl_ldata.rl_stats_addr |
3979 		    RL_DUMPSTATS_START));
3980 		for (i = RL_TIMEOUT; i > 0; i--) {
3981 			if ((CSR_READ_4(sc, RL_DUMPSTATS_LO) &
3982 			    RL_DUMPSTATS_START) == 0)
3983 				break;
3984 			DELAY(1000);
3985 		}
3986 		bus_dmamap_sync(sc->rl_ldata.rl_stag,
3987 		    sc->rl_ldata.rl_smap, BUS_DMASYNC_POSTREAD);
3988 		RL_UNLOCK(sc);
3989 		if (i == 0) {
3990 			device_printf(sc->rl_dev,
3991 			    "DUMP statistics request timed out\n");
3992 			return (ETIMEDOUT);
3993 		}
3994 done:
3995 		stats = sc->rl_ldata.rl_stats;
3996 		printf("%s statistics:\n", device_get_nameunit(sc->rl_dev));
3997 		printf("Tx frames : %ju\n",
3998 		    (uintmax_t)le64toh(stats->rl_tx_pkts));
3999 		printf("Rx frames : %ju\n",
4000 		    (uintmax_t)le64toh(stats->rl_rx_pkts));
4001 		printf("Tx errors : %ju\n",
4002 		    (uintmax_t)le64toh(stats->rl_tx_errs));
4003 		printf("Rx errors : %u\n",
4004 		    le32toh(stats->rl_rx_errs));
4005 		printf("Rx missed frames : %u\n",
4006 		    (uint32_t)le16toh(stats->rl_missed_pkts));
4007 		printf("Rx frame alignment errs : %u\n",
4008 		    (uint32_t)le16toh(stats->rl_rx_framealign_errs));
4009 		printf("Tx single collisions : %u\n",
4010 		    le32toh(stats->rl_tx_onecoll));
4011 		printf("Tx multiple collisions : %u\n",
4012 		    le32toh(stats->rl_tx_multicolls));
4013 		printf("Rx unicast frames : %ju\n",
4014 		    (uintmax_t)le64toh(stats->rl_rx_ucasts));
4015 		printf("Rx broadcast frames : %ju\n",
4016 		    (uintmax_t)le64toh(stats->rl_rx_bcasts));
4017 		printf("Rx multicast frames : %u\n",
4018 		    le32toh(stats->rl_rx_mcasts));
4019 		printf("Tx aborts : %u\n",
4020 		    (uint32_t)le16toh(stats->rl_tx_aborts));
4021 		printf("Tx underruns : %u\n",
4022 		    (uint32_t)le16toh(stats->rl_rx_underruns));
4023 	}
4024 
4025 	return (error);
4026 }
4027 
4028 static int
4029 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
4030 {
4031 	int error, value;
4032 
4033 	if (arg1 == NULL)
4034 		return (EINVAL);
4035 	value = *(int *)arg1;
4036 	error = sysctl_handle_int(oidp, &value, 0, req);
4037 	if (error || req->newptr == NULL)
4038 		return (error);
4039 	if (value < low || value > high)
4040 		return (EINVAL);
4041 	*(int *)arg1 = value;
4042 
4043 	return (0);
4044 }
4045 
4046 static int
4047 sysctl_hw_re_int_mod(SYSCTL_HANDLER_ARGS)
4048 {
4049 
4050 	return (sysctl_int_range(oidp, arg1, arg2, req, RL_TIMER_MIN,
4051 	    RL_TIMER_MAX));
4052 }
4053