1 /*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44 /* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S 48 * and the RTL8110S. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111 #include <sys/param.h> 112 #include <sys/endian.h> 113 #include <sys/systm.h> 114 #include <sys/sockio.h> 115 #include <sys/mbuf.h> 116 #include <sys/malloc.h> 117 #include <sys/module.h> 118 #include <sys/kernel.h> 119 #include <sys/socket.h> 120 121 #include <net/if.h> 122 #include <net/if_arp.h> 123 #include <net/ethernet.h> 124 #include <net/if_dl.h> 125 #include <net/if_media.h> 126 #include <net/if_types.h> 127 #include <net/if_vlan_var.h> 128 129 #include <net/bpf.h> 130 131 #include <machine/bus.h> 132 #include <machine/resource.h> 133 #include <sys/bus.h> 134 #include <sys/rman.h> 135 136 #include <dev/mii/mii.h> 137 #include <dev/mii/miivar.h> 138 139 #include <dev/pci/pcireg.h> 140 #include <dev/pci/pcivar.h> 141 142 MODULE_DEPEND(re, pci, 1, 1, 1); 143 MODULE_DEPEND(re, ether, 1, 1, 1); 144 MODULE_DEPEND(re, miibus, 1, 1, 1); 145 146 /* "controller miibus0" required. See GENERIC if you get errors here. */ 147 #include "miibus_if.h" 148 149 /* 150 * Default to using PIO access for this driver. 151 */ 152 #define RE_USEIOSPACE 153 154 #include <pci/if_rlreg.h> 155 156 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 157 158 /* 159 * Various supported device vendors/types and their names. 160 */ 161 static struct rl_type re_devs[] = { 162 { DLINK_VENDORID, DLINK_DEVICEID_528T, RL_HWREV_8169S, 163 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 164 { RT_VENDORID, RT_DEVICEID_8139, RL_HWREV_8139CPLUS, 165 "RealTek 8139C+ 10/100BaseTX" }, 166 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169, 167 "RealTek 8169 Gigabit Ethernet" }, 168 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169S, 169 "RealTek 8169S Single-chip Gigabit Ethernet" }, 170 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169SB, 171 "RealTek 8169SB Single-chip Gigabit Ethernet" }, 172 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8110S, 173 "RealTek 8110S Single-chip Gigabit Ethernet" }, 174 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, RL_HWREV_8169S, 175 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 176 { 0, 0, 0, NULL } 177 }; 178 179 static struct rl_hwrev re_hwrevs[] = { 180 { RL_HWREV_8139, RL_8139, "" }, 181 { RL_HWREV_8139A, RL_8139, "A" }, 182 { RL_HWREV_8139AG, RL_8139, "A-G" }, 183 { RL_HWREV_8139B, RL_8139, "B" }, 184 { RL_HWREV_8130, RL_8139, "8130" }, 185 { RL_HWREV_8139C, RL_8139, "C" }, 186 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 187 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 188 { RL_HWREV_8169, RL_8169, "8169"}, 189 { RL_HWREV_8169S, RL_8169, "8169S"}, 190 { RL_HWREV_8169SB, RL_8169, "8169SB"}, 191 { RL_HWREV_8110S, RL_8169, "8110S"}, 192 { RL_HWREV_8100, RL_8139, "8100"}, 193 { RL_HWREV_8101, RL_8139, "8101"}, 194 { 0, 0, NULL } 195 }; 196 197 static int re_probe (device_t); 198 static int re_attach (device_t); 199 static int re_detach (device_t); 200 201 static int re_encap (struct rl_softc *, struct mbuf **, int *); 202 203 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 204 static void re_dma_map_desc (void *, bus_dma_segment_t *, int, 205 bus_size_t, int); 206 static int re_allocmem (device_t, struct rl_softc *); 207 static int re_newbuf (struct rl_softc *, int, struct mbuf *); 208 static int re_rx_list_init (struct rl_softc *); 209 static int re_tx_list_init (struct rl_softc *); 210 #ifdef RE_FIXUP_RX 211 static __inline void re_fixup_rx 212 (struct mbuf *); 213 #endif 214 static void re_rxeof (struct rl_softc *); 215 static void re_txeof (struct rl_softc *); 216 #ifdef DEVICE_POLLING 217 static void re_poll (struct ifnet *, enum poll_cmd, int); 218 static void re_poll_locked (struct ifnet *, enum poll_cmd, int); 219 #endif 220 static void re_intr (void *); 221 static void re_tick (void *); 222 static void re_tick_locked (struct rl_softc *); 223 static void re_start (struct ifnet *); 224 static void re_start_locked (struct ifnet *); 225 static int re_ioctl (struct ifnet *, u_long, caddr_t); 226 static void re_init (void *); 227 static void re_init_locked (struct rl_softc *); 228 static void re_stop (struct rl_softc *); 229 static void re_watchdog (struct ifnet *); 230 static int re_suspend (device_t); 231 static int re_resume (device_t); 232 static void re_shutdown (device_t); 233 static int re_ifmedia_upd (struct ifnet *); 234 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 235 236 static void re_eeprom_putbyte (struct rl_softc *, int); 237 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 238 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int, int); 239 static int re_gmii_readreg (device_t, int, int); 240 static int re_gmii_writereg (device_t, int, int, int); 241 242 static int re_miibus_readreg (device_t, int, int); 243 static int re_miibus_writereg (device_t, int, int, int); 244 static void re_miibus_statchg (device_t); 245 246 static void re_setmulti (struct rl_softc *); 247 static void re_reset (struct rl_softc *); 248 249 static int re_diag (struct rl_softc *); 250 251 #ifdef RE_USEIOSPACE 252 #define RL_RES SYS_RES_IOPORT 253 #define RL_RID RL_PCI_LOIO 254 #else 255 #define RL_RES SYS_RES_MEMORY 256 #define RL_RID RL_PCI_LOMEM 257 #endif 258 259 static device_method_t re_methods[] = { 260 /* Device interface */ 261 DEVMETHOD(device_probe, re_probe), 262 DEVMETHOD(device_attach, re_attach), 263 DEVMETHOD(device_detach, re_detach), 264 DEVMETHOD(device_suspend, re_suspend), 265 DEVMETHOD(device_resume, re_resume), 266 DEVMETHOD(device_shutdown, re_shutdown), 267 268 /* bus interface */ 269 DEVMETHOD(bus_print_child, bus_generic_print_child), 270 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 271 272 /* MII interface */ 273 DEVMETHOD(miibus_readreg, re_miibus_readreg), 274 DEVMETHOD(miibus_writereg, re_miibus_writereg), 275 DEVMETHOD(miibus_statchg, re_miibus_statchg), 276 277 { 0, 0 } 278 }; 279 280 static driver_t re_driver = { 281 "re", 282 re_methods, 283 sizeof(struct rl_softc) 284 }; 285 286 static devclass_t re_devclass; 287 288 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 289 DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0); 290 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 291 292 #define EE_SET(x) \ 293 CSR_WRITE_1(sc, RL_EECMD, \ 294 CSR_READ_1(sc, RL_EECMD) | x) 295 296 #define EE_CLR(x) \ 297 CSR_WRITE_1(sc, RL_EECMD, \ 298 CSR_READ_1(sc, RL_EECMD) & ~x) 299 300 /* 301 * Send a read command and address to the EEPROM, check for ACK. 302 */ 303 static void 304 re_eeprom_putbyte(sc, addr) 305 struct rl_softc *sc; 306 int addr; 307 { 308 register int d, i; 309 310 d = addr | sc->rl_eecmd_read; 311 312 /* 313 * Feed in each bit and strobe the clock. 314 */ 315 for (i = 0x400; i; i >>= 1) { 316 if (d & i) { 317 EE_SET(RL_EE_DATAIN); 318 } else { 319 EE_CLR(RL_EE_DATAIN); 320 } 321 DELAY(100); 322 EE_SET(RL_EE_CLK); 323 DELAY(150); 324 EE_CLR(RL_EE_CLK); 325 DELAY(100); 326 } 327 } 328 329 /* 330 * Read a word of data stored in the EEPROM at address 'addr.' 331 */ 332 static void 333 re_eeprom_getword(sc, addr, dest) 334 struct rl_softc *sc; 335 int addr; 336 u_int16_t *dest; 337 { 338 register int i; 339 u_int16_t word = 0; 340 341 /* Enter EEPROM access mode. */ 342 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 343 344 /* 345 * Send address of word we want to read. 346 */ 347 re_eeprom_putbyte(sc, addr); 348 349 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); 350 351 /* 352 * Start reading bits from EEPROM. 353 */ 354 for (i = 0x8000; i; i >>= 1) { 355 EE_SET(RL_EE_CLK); 356 DELAY(100); 357 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 358 word |= i; 359 EE_CLR(RL_EE_CLK); 360 DELAY(100); 361 } 362 363 /* Turn off EEPROM access mode. */ 364 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 365 366 *dest = word; 367 } 368 369 /* 370 * Read a sequence of words from the EEPROM. 371 */ 372 static void 373 re_read_eeprom(sc, dest, off, cnt, swap) 374 struct rl_softc *sc; 375 caddr_t dest; 376 int off; 377 int cnt; 378 int swap; 379 { 380 int i; 381 u_int16_t word = 0, *ptr; 382 383 for (i = 0; i < cnt; i++) { 384 re_eeprom_getword(sc, off + i, &word); 385 ptr = (u_int16_t *)(dest + (i * 2)); 386 if (swap) 387 *ptr = ntohs(word); 388 else 389 *ptr = word; 390 } 391 } 392 393 static int 394 re_gmii_readreg(dev, phy, reg) 395 device_t dev; 396 int phy, reg; 397 { 398 struct rl_softc *sc; 399 u_int32_t rval; 400 int i; 401 402 if (phy != 1) 403 return (0); 404 405 sc = device_get_softc(dev); 406 407 /* Let the rgephy driver read the GMEDIASTAT register */ 408 409 if (reg == RL_GMEDIASTAT) { 410 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 411 return (rval); 412 } 413 414 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 415 DELAY(1000); 416 417 for (i = 0; i < RL_TIMEOUT; i++) { 418 rval = CSR_READ_4(sc, RL_PHYAR); 419 if (rval & RL_PHYAR_BUSY) 420 break; 421 DELAY(100); 422 } 423 424 if (i == RL_TIMEOUT) { 425 printf ("re%d: PHY read failed\n", sc->rl_unit); 426 return (0); 427 } 428 429 return (rval & RL_PHYAR_PHYDATA); 430 } 431 432 static int 433 re_gmii_writereg(dev, phy, reg, data) 434 device_t dev; 435 int phy, reg, data; 436 { 437 struct rl_softc *sc; 438 u_int32_t rval; 439 int i; 440 441 sc = device_get_softc(dev); 442 443 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 444 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 445 DELAY(1000); 446 447 for (i = 0; i < RL_TIMEOUT; i++) { 448 rval = CSR_READ_4(sc, RL_PHYAR); 449 if (!(rval & RL_PHYAR_BUSY)) 450 break; 451 DELAY(100); 452 } 453 454 if (i == RL_TIMEOUT) { 455 printf ("re%d: PHY write failed\n", sc->rl_unit); 456 return (0); 457 } 458 459 return (0); 460 } 461 462 static int 463 re_miibus_readreg(dev, phy, reg) 464 device_t dev; 465 int phy, reg; 466 { 467 struct rl_softc *sc; 468 u_int16_t rval = 0; 469 u_int16_t re8139_reg = 0; 470 471 sc = device_get_softc(dev); 472 473 if (sc->rl_type == RL_8169) { 474 rval = re_gmii_readreg(dev, phy, reg); 475 return (rval); 476 } 477 478 /* Pretend the internal PHY is only at address 0 */ 479 if (phy) { 480 return (0); 481 } 482 switch (reg) { 483 case MII_BMCR: 484 re8139_reg = RL_BMCR; 485 break; 486 case MII_BMSR: 487 re8139_reg = RL_BMSR; 488 break; 489 case MII_ANAR: 490 re8139_reg = RL_ANAR; 491 break; 492 case MII_ANER: 493 re8139_reg = RL_ANER; 494 break; 495 case MII_ANLPAR: 496 re8139_reg = RL_LPAR; 497 break; 498 case MII_PHYIDR1: 499 case MII_PHYIDR2: 500 return (0); 501 /* 502 * Allow the rlphy driver to read the media status 503 * register. If we have a link partner which does not 504 * support NWAY, this is the register which will tell 505 * us the results of parallel detection. 506 */ 507 case RL_MEDIASTAT: 508 rval = CSR_READ_1(sc, RL_MEDIASTAT); 509 return (rval); 510 default: 511 printf("re%d: bad phy register\n", sc->rl_unit); 512 return (0); 513 } 514 rval = CSR_READ_2(sc, re8139_reg); 515 return (rval); 516 } 517 518 static int 519 re_miibus_writereg(dev, phy, reg, data) 520 device_t dev; 521 int phy, reg, data; 522 { 523 struct rl_softc *sc; 524 u_int16_t re8139_reg = 0; 525 int rval = 0; 526 527 sc = device_get_softc(dev); 528 529 if (sc->rl_type == RL_8169) { 530 rval = re_gmii_writereg(dev, phy, reg, data); 531 return (rval); 532 } 533 534 /* Pretend the internal PHY is only at address 0 */ 535 if (phy) 536 return (0); 537 538 switch (reg) { 539 case MII_BMCR: 540 re8139_reg = RL_BMCR; 541 break; 542 case MII_BMSR: 543 re8139_reg = RL_BMSR; 544 break; 545 case MII_ANAR: 546 re8139_reg = RL_ANAR; 547 break; 548 case MII_ANER: 549 re8139_reg = RL_ANER; 550 break; 551 case MII_ANLPAR: 552 re8139_reg = RL_LPAR; 553 break; 554 case MII_PHYIDR1: 555 case MII_PHYIDR2: 556 return (0); 557 break; 558 default: 559 printf("re%d: bad phy register\n", sc->rl_unit); 560 return (0); 561 } 562 CSR_WRITE_2(sc, re8139_reg, data); 563 return (0); 564 } 565 566 static void 567 re_miibus_statchg(dev) 568 device_t dev; 569 { 570 571 } 572 573 /* 574 * Program the 64-bit multicast hash filter. 575 */ 576 static void 577 re_setmulti(sc) 578 struct rl_softc *sc; 579 { 580 struct ifnet *ifp; 581 int h = 0; 582 u_int32_t hashes[2] = { 0, 0 }; 583 struct ifmultiaddr *ifma; 584 u_int32_t rxfilt; 585 int mcnt = 0; 586 587 RL_LOCK_ASSERT(sc); 588 589 ifp = sc->rl_ifp; 590 591 rxfilt = CSR_READ_4(sc, RL_RXCFG); 592 593 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 594 rxfilt |= RL_RXCFG_RX_MULTI; 595 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 596 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 597 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 598 return; 599 } 600 601 /* first, zot all the existing hash bits */ 602 CSR_WRITE_4(sc, RL_MAR0, 0); 603 CSR_WRITE_4(sc, RL_MAR4, 0); 604 605 /* now program new ones */ 606 IF_ADDR_LOCK(ifp); 607 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 608 if (ifma->ifma_addr->sa_family != AF_LINK) 609 continue; 610 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 611 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 612 if (h < 32) 613 hashes[0] |= (1 << h); 614 else 615 hashes[1] |= (1 << (h - 32)); 616 mcnt++; 617 } 618 IF_ADDR_UNLOCK(ifp); 619 620 if (mcnt) 621 rxfilt |= RL_RXCFG_RX_MULTI; 622 else 623 rxfilt &= ~RL_RXCFG_RX_MULTI; 624 625 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 626 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 627 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 628 } 629 630 static void 631 re_reset(sc) 632 struct rl_softc *sc; 633 { 634 register int i; 635 636 RL_LOCK_ASSERT(sc); 637 638 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 639 640 for (i = 0; i < RL_TIMEOUT; i++) { 641 DELAY(10); 642 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 643 break; 644 } 645 if (i == RL_TIMEOUT) 646 printf("re%d: reset never completed!\n", sc->rl_unit); 647 648 CSR_WRITE_1(sc, 0x82, 1); 649 } 650 651 /* 652 * The following routine is designed to test for a defect on some 653 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 654 * lines connected to the bus, however for a 32-bit only card, they 655 * should be pulled high. The result of this defect is that the 656 * NIC will not work right if you plug it into a 64-bit slot: DMA 657 * operations will be done with 64-bit transfers, which will fail 658 * because the 64-bit data lines aren't connected. 659 * 660 * There's no way to work around this (short of talking a soldering 661 * iron to the board), however we can detect it. The method we use 662 * here is to put the NIC into digital loopback mode, set the receiver 663 * to promiscuous mode, and then try to send a frame. We then compare 664 * the frame data we sent to what was received. If the data matches, 665 * then the NIC is working correctly, otherwise we know the user has 666 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 667 * slot. In the latter case, there's no way the NIC can work correctly, 668 * so we print out a message on the console and abort the device attach. 669 */ 670 671 static int 672 re_diag(sc) 673 struct rl_softc *sc; 674 { 675 struct ifnet *ifp = sc->rl_ifp; 676 struct mbuf *m0; 677 struct ether_header *eh; 678 struct rl_desc *cur_rx; 679 u_int16_t status; 680 u_int32_t rxstat; 681 int total_len, i, error = 0; 682 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 683 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 684 685 /* Allocate a single mbuf */ 686 MGETHDR(m0, M_DONTWAIT, MT_DATA); 687 if (m0 == NULL) 688 return (ENOBUFS); 689 690 RL_LOCK(sc); 691 692 /* 693 * Initialize the NIC in test mode. This sets the chip up 694 * so that it can send and receive frames, but performs the 695 * following special functions: 696 * - Puts receiver in promiscuous mode 697 * - Enables digital loopback mode 698 * - Leaves interrupts turned off 699 */ 700 701 ifp->if_flags |= IFF_PROMISC; 702 sc->rl_testmode = 1; 703 re_init_locked(sc); 704 re_stop(sc); 705 DELAY(100000); 706 re_init_locked(sc); 707 708 /* Put some data in the mbuf */ 709 710 eh = mtod(m0, struct ether_header *); 711 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 712 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 713 eh->ether_type = htons(ETHERTYPE_IP); 714 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 715 716 /* 717 * Queue the packet, start transmission. 718 * Note: IF_HANDOFF() ultimately calls re_start() for us. 719 */ 720 721 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 722 RL_UNLOCK(sc); 723 /* XXX: re_diag must not be called when in ALTQ mode */ 724 IF_HANDOFF(&ifp->if_snd, m0, ifp); 725 RL_LOCK(sc); 726 m0 = NULL; 727 728 /* Wait for it to propagate through the chip */ 729 730 DELAY(100000); 731 for (i = 0; i < RL_TIMEOUT; i++) { 732 status = CSR_READ_2(sc, RL_ISR); 733 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 734 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 735 break; 736 DELAY(10); 737 } 738 739 if (i == RL_TIMEOUT) { 740 printf("re%d: diagnostic failed, failed to receive packet " 741 "in loopback mode\n", sc->rl_unit); 742 error = EIO; 743 goto done; 744 } 745 746 /* 747 * The packet should have been dumped into the first 748 * entry in the RX DMA ring. Grab it from there. 749 */ 750 751 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 752 sc->rl_ldata.rl_rx_list_map, 753 BUS_DMASYNC_POSTREAD); 754 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 755 sc->rl_ldata.rl_rx_dmamap[0], 756 BUS_DMASYNC_POSTWRITE); 757 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 758 sc->rl_ldata.rl_rx_dmamap[0]); 759 760 m0 = sc->rl_ldata.rl_rx_mbuf[0]; 761 sc->rl_ldata.rl_rx_mbuf[0] = NULL; 762 eh = mtod(m0, struct ether_header *); 763 764 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 765 total_len = RL_RXBYTES(cur_rx); 766 rxstat = le32toh(cur_rx->rl_cmdstat); 767 768 if (total_len != ETHER_MIN_LEN) { 769 printf("re%d: diagnostic failed, received short packet\n", 770 sc->rl_unit); 771 error = EIO; 772 goto done; 773 } 774 775 /* Test that the received packet data matches what we sent. */ 776 777 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 778 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 779 ntohs(eh->ether_type) != ETHERTYPE_IP) { 780 printf("re%d: WARNING, DMA FAILURE!\n", sc->rl_unit); 781 printf("re%d: expected TX data: %6D/%6D/0x%x\n", sc->rl_unit, 782 dst, ":", src, ":", ETHERTYPE_IP); 783 printf("re%d: received RX data: %6D/%6D/0x%x\n", sc->rl_unit, 784 eh->ether_dhost, ":", eh->ether_shost, ":", 785 ntohs(eh->ether_type)); 786 printf("re%d: You may have a defective 32-bit NIC plugged " 787 "into a 64-bit PCI slot.\n", sc->rl_unit); 788 printf("re%d: Please re-install the NIC in a 32-bit slot " 789 "for proper operation.\n", sc->rl_unit); 790 printf("re%d: Read the re(4) man page for more details.\n", 791 sc->rl_unit); 792 error = EIO; 793 } 794 795 done: 796 /* Turn interface off, release resources */ 797 798 sc->rl_testmode = 0; 799 ifp->if_flags &= ~IFF_PROMISC; 800 re_stop(sc); 801 if (m0 != NULL) 802 m_freem(m0); 803 804 RL_UNLOCK(sc); 805 806 return (error); 807 } 808 809 /* 810 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 811 * IDs against our list and return a device name if we find a match. 812 */ 813 static int 814 re_probe(dev) 815 device_t dev; 816 { 817 struct rl_type *t; 818 struct rl_softc *sc; 819 int rid; 820 u_int32_t hwrev; 821 822 t = re_devs; 823 sc = device_get_softc(dev); 824 825 while (t->rl_name != NULL) { 826 if ((pci_get_vendor(dev) == t->rl_vid) && 827 (pci_get_device(dev) == t->rl_did)) { 828 829 /* 830 * Temporarily map the I/O space 831 * so we can read the chip ID register. 832 */ 833 rid = RL_RID; 834 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 835 RF_ACTIVE); 836 if (sc->rl_res == NULL) { 837 device_printf(dev, 838 "couldn't map ports/memory\n"); 839 return (ENXIO); 840 } 841 sc->rl_btag = rman_get_bustag(sc->rl_res); 842 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 843 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 844 bus_release_resource(dev, RL_RES, 845 RL_RID, sc->rl_res); 846 if (t->rl_basetype == hwrev) { 847 device_set_desc(dev, t->rl_name); 848 return (BUS_PROBE_DEFAULT); 849 } 850 } 851 t++; 852 } 853 854 return (ENXIO); 855 } 856 857 /* 858 * This routine takes the segment list provided as the result of 859 * a bus_dma_map_load() operation and assigns the addresses/lengths 860 * to RealTek DMA descriptors. This can be called either by the RX 861 * code or the TX code. In the RX case, we'll probably wind up mapping 862 * at most one segment. For the TX case, there could be any number of 863 * segments since TX packets may span multiple mbufs. In either case, 864 * if the number of segments is larger than the rl_maxsegs limit 865 * specified by the caller, we abort the mapping operation. Sadly, 866 * whoever designed the buffer mapping API did not provide a way to 867 * return an error from here, so we have to fake it a bit. 868 */ 869 870 static void 871 re_dma_map_desc(arg, segs, nseg, mapsize, error) 872 void *arg; 873 bus_dma_segment_t *segs; 874 int nseg; 875 bus_size_t mapsize; 876 int error; 877 { 878 struct rl_dmaload_arg *ctx; 879 struct rl_desc *d = NULL; 880 int i = 0, idx; 881 882 if (error) 883 return; 884 885 ctx = arg; 886 887 /* Signal error to caller if there's too many segments */ 888 if (nseg > ctx->rl_maxsegs) { 889 ctx->rl_maxsegs = 0; 890 return; 891 } 892 893 /* 894 * Map the segment array into descriptors. Note that we set the 895 * start-of-frame and end-of-frame markers for either TX or RX, but 896 * they really only have meaning in the TX case. (In the RX case, 897 * it's the chip that tells us where packets begin and end.) 898 * We also keep track of the end of the ring and set the 899 * end-of-ring bits as needed, and we set the ownership bits 900 * in all except the very first descriptor. (The caller will 901 * set this descriptor later when it start transmission or 902 * reception.) 903 */ 904 idx = ctx->rl_idx; 905 for (;;) { 906 u_int32_t cmdstat; 907 d = &ctx->rl_ring[idx]; 908 if (le32toh(d->rl_cmdstat) & RL_RDESC_STAT_OWN) { 909 ctx->rl_maxsegs = 0; 910 return; 911 } 912 cmdstat = segs[i].ds_len; 913 d->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 914 d->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 915 if (i == 0) 916 cmdstat |= RL_TDESC_CMD_SOF; 917 else 918 cmdstat |= RL_TDESC_CMD_OWN; 919 if (idx == (RL_RX_DESC_CNT - 1)) 920 cmdstat |= RL_TDESC_CMD_EOR; 921 d->rl_cmdstat = htole32(cmdstat | ctx->rl_flags); 922 i++; 923 if (i == nseg) 924 break; 925 RL_DESC_INC(idx); 926 } 927 928 d->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 929 ctx->rl_maxsegs = nseg; 930 ctx->rl_idx = idx; 931 } 932 933 /* 934 * Map a single buffer address. 935 */ 936 937 static void 938 re_dma_map_addr(arg, segs, nseg, error) 939 void *arg; 940 bus_dma_segment_t *segs; 941 int nseg; 942 int error; 943 { 944 bus_addr_t *addr; 945 946 if (error) 947 return; 948 949 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 950 addr = arg; 951 *addr = segs->ds_addr; 952 } 953 954 static int 955 re_allocmem(dev, sc) 956 device_t dev; 957 struct rl_softc *sc; 958 { 959 int error; 960 int nseg; 961 int i; 962 963 /* 964 * Allocate map for RX mbufs. 965 */ 966 nseg = 32; 967 error = bus_dma_tag_create(sc->rl_parent_tag, ETHER_ALIGN, 0, 968 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 969 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 970 NULL, NULL, &sc->rl_ldata.rl_mtag); 971 if (error) { 972 device_printf(dev, "could not allocate dma tag\n"); 973 return (ENOMEM); 974 } 975 976 /* 977 * Allocate map for TX descriptor list. 978 */ 979 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 980 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 981 NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 982 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 983 if (error) { 984 device_printf(dev, "could not allocate dma tag\n"); 985 return (ENOMEM); 986 } 987 988 /* Allocate DMA'able memory for the TX ring */ 989 990 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 991 (void **)&sc->rl_ldata.rl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 992 &sc->rl_ldata.rl_tx_list_map); 993 if (error) 994 return (ENOMEM); 995 996 /* Load the map for the TX ring. */ 997 998 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 999 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1000 RL_TX_LIST_SZ, re_dma_map_addr, 1001 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1002 1003 /* Create DMA maps for TX buffers */ 1004 1005 for (i = 0; i < RL_TX_DESC_CNT; i++) { 1006 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1007 &sc->rl_ldata.rl_tx_dmamap[i]); 1008 if (error) { 1009 device_printf(dev, "can't create DMA map for TX\n"); 1010 return (ENOMEM); 1011 } 1012 } 1013 1014 /* 1015 * Allocate map for RX descriptor list. 1016 */ 1017 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1018 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1019 NULL, RL_RX_LIST_SZ, 1, RL_RX_LIST_SZ, BUS_DMA_ALLOCNOW, 1020 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1021 if (error) { 1022 device_printf(dev, "could not allocate dma tag\n"); 1023 return (ENOMEM); 1024 } 1025 1026 /* Allocate DMA'able memory for the RX ring */ 1027 1028 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1029 (void **)&sc->rl_ldata.rl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1030 &sc->rl_ldata.rl_rx_list_map); 1031 if (error) 1032 return (ENOMEM); 1033 1034 /* Load the map for the RX ring. */ 1035 1036 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1037 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1038 RL_RX_LIST_SZ, re_dma_map_addr, 1039 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1040 1041 /* Create DMA maps for RX buffers */ 1042 1043 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1044 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1045 &sc->rl_ldata.rl_rx_dmamap[i]); 1046 if (error) { 1047 device_printf(dev, "can't create DMA map for RX\n"); 1048 return (ENOMEM); 1049 } 1050 } 1051 1052 return (0); 1053 } 1054 1055 /* 1056 * Attach the interface. Allocate softc structures, do ifmedia 1057 * setup and ethernet/BPF attach. 1058 */ 1059 static int 1060 re_attach(dev) 1061 device_t dev; 1062 { 1063 u_char eaddr[ETHER_ADDR_LEN]; 1064 u_int16_t as[3]; 1065 struct rl_softc *sc; 1066 struct ifnet *ifp; 1067 struct rl_hwrev *hw_rev; 1068 int hwrev; 1069 u_int16_t re_did = 0; 1070 int unit, error = 0, rid, i; 1071 1072 sc = device_get_softc(dev); 1073 unit = device_get_unit(dev); 1074 1075 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1076 MTX_DEF); 1077 /* 1078 * Map control/status registers. 1079 */ 1080 pci_enable_busmaster(dev); 1081 1082 rid = RL_RID; 1083 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 1084 RF_ACTIVE); 1085 1086 if (sc->rl_res == NULL) { 1087 printf ("re%d: couldn't map ports/memory\n", unit); 1088 error = ENXIO; 1089 goto fail; 1090 } 1091 1092 sc->rl_btag = rman_get_bustag(sc->rl_res); 1093 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1094 1095 /* Allocate interrupt */ 1096 rid = 0; 1097 sc->rl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1098 RF_SHAREABLE | RF_ACTIVE); 1099 1100 if (sc->rl_irq == NULL) { 1101 printf("re%d: couldn't map interrupt\n", unit); 1102 error = ENXIO; 1103 goto fail; 1104 } 1105 1106 /* Reset the adapter. */ 1107 RL_LOCK(sc); 1108 re_reset(sc); 1109 RL_UNLOCK(sc); 1110 1111 hw_rev = re_hwrevs; 1112 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 1113 while (hw_rev->rl_desc != NULL) { 1114 if (hw_rev->rl_rev == hwrev) { 1115 sc->rl_type = hw_rev->rl_type; 1116 break; 1117 } 1118 hw_rev++; 1119 } 1120 1121 if (sc->rl_type == RL_8169) { 1122 1123 /* Set RX length mask */ 1124 1125 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1126 1127 /* Force station address autoload from the EEPROM */ 1128 1129 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_AUTOLOAD); 1130 for (i = 0; i < RL_TIMEOUT; i++) { 1131 if (!(CSR_READ_1(sc, RL_EECMD) & RL_EEMODE_AUTOLOAD)) 1132 break; 1133 DELAY(100); 1134 } 1135 if (i == RL_TIMEOUT) 1136 printf ("re%d: eeprom autoload timed out\n", unit); 1137 1138 for (i = 0; i < ETHER_ADDR_LEN; i++) 1139 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1140 } else { 1141 1142 /* Set RX length mask */ 1143 1144 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1145 1146 sc->rl_eecmd_read = RL_EECMD_READ_6BIT; 1147 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1, 0); 1148 if (re_did != 0x8129) 1149 sc->rl_eecmd_read = RL_EECMD_READ_8BIT; 1150 1151 /* 1152 * Get station address from the EEPROM. 1153 */ 1154 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0); 1155 for (i = 0; i < 3; i++) { 1156 eaddr[(i * 2) + 0] = as[i] & 0xff; 1157 eaddr[(i * 2) + 1] = as[i] >> 8; 1158 } 1159 } 1160 1161 sc->rl_unit = unit; 1162 1163 /* 1164 * Allocate the parent bus DMA tag appropriate for PCI. 1165 */ 1166 #define RL_NSEG_NEW 32 1167 error = bus_dma_tag_create(NULL, /* parent */ 1168 1, 0, /* alignment, boundary */ 1169 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1170 BUS_SPACE_MAXADDR, /* highaddr */ 1171 NULL, NULL, /* filter, filterarg */ 1172 MAXBSIZE, RL_NSEG_NEW, /* maxsize, nsegments */ 1173 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1174 BUS_DMA_ALLOCNOW, /* flags */ 1175 NULL, NULL, /* lockfunc, lockarg */ 1176 &sc->rl_parent_tag); 1177 if (error) 1178 goto fail; 1179 1180 error = re_allocmem(dev, sc); 1181 1182 if (error) 1183 goto fail; 1184 1185 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1186 if (ifp == NULL) { 1187 printf("re%d: can not if_alloc()\n", sc->rl_unit); 1188 error = ENOSPC; 1189 goto fail; 1190 } 1191 1192 /* Do MII setup */ 1193 if (mii_phy_probe(dev, &sc->rl_miibus, 1194 re_ifmedia_upd, re_ifmedia_sts)) { 1195 printf("re%d: MII without any phy!\n", sc->rl_unit); 1196 error = ENXIO; 1197 goto fail; 1198 } 1199 1200 ifp->if_softc = sc; 1201 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1202 ifp->if_mtu = ETHERMTU; 1203 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1204 ifp->if_ioctl = re_ioctl; 1205 ifp->if_capabilities = IFCAP_VLAN_MTU; 1206 ifp->if_start = re_start; 1207 ifp->if_hwassist = /*RE_CSUM_FEATURES*/0; 1208 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1209 #ifdef DEVICE_POLLING 1210 ifp->if_capabilities |= IFCAP_POLLING; 1211 #endif 1212 ifp->if_watchdog = re_watchdog; 1213 ifp->if_init = re_init; 1214 if (sc->rl_type == RL_8169) 1215 ifp->if_baudrate = 1000000000; 1216 else 1217 ifp->if_baudrate = 100000000; 1218 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1219 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1220 IFQ_SET_READY(&ifp->if_snd); 1221 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM; 1222 1223 callout_handle_init(&sc->rl_stat_ch); 1224 1225 /* 1226 * Call MI attach routine. 1227 */ 1228 ether_ifattach(ifp, eaddr); 1229 1230 /* Perform hardware diagnostic. */ 1231 error = re_diag(sc); 1232 1233 if (error) { 1234 printf("re%d: attach aborted due to hardware diag failure\n", 1235 unit); 1236 ether_ifdetach(ifp); 1237 goto fail; 1238 } 1239 1240 /* Hook interrupt last to avoid having to lock softc */ 1241 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET | INTR_MPSAFE, 1242 re_intr, sc, &sc->rl_intrhand); 1243 if (error) { 1244 printf("re%d: couldn't set up irq\n", unit); 1245 ether_ifdetach(ifp); 1246 } 1247 1248 fail: 1249 if (error) 1250 re_detach(dev); 1251 1252 return (error); 1253 } 1254 1255 /* 1256 * Shutdown hardware and free up resources. This can be called any 1257 * time after the mutex has been initialized. It is called in both 1258 * the error case in attach and the normal detach case so it needs 1259 * to be careful about only freeing resources that have actually been 1260 * allocated. 1261 */ 1262 static int 1263 re_detach(dev) 1264 device_t dev; 1265 { 1266 struct rl_softc *sc; 1267 struct ifnet *ifp; 1268 int i; 1269 1270 sc = device_get_softc(dev); 1271 ifp = sc->rl_ifp; 1272 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1273 1274 /* These should only be active if attach succeeded */ 1275 if (device_is_attached(dev)) { 1276 RL_LOCK(sc); 1277 #if 0 1278 sc->suspended = 1; 1279 #endif 1280 re_stop(sc); 1281 RL_UNLOCK(sc); 1282 /* 1283 * Force off the IFF_UP flag here, in case someone 1284 * still had a BPF descriptor attached to this 1285 * interface. If they do, ether_ifdetach() will cause 1286 * the BPF code to try and clear the promisc mode 1287 * flag, which will bubble down to re_ioctl(), 1288 * which will try to call re_init() again. This will 1289 * turn the NIC back on and restart the MII ticker, 1290 * which will panic the system when the kernel tries 1291 * to invoke the re_tick() function that isn't there 1292 * anymore. 1293 */ 1294 ifp->if_flags &= ~IFF_UP; 1295 ether_ifdetach(ifp); 1296 } 1297 if (sc->rl_miibus) 1298 device_delete_child(dev, sc->rl_miibus); 1299 bus_generic_detach(dev); 1300 1301 /* 1302 * The rest is resource deallocation, so we should already be 1303 * stopped here. 1304 */ 1305 1306 if (sc->rl_intrhand) 1307 bus_teardown_intr(dev, sc->rl_irq, sc->rl_intrhand); 1308 if (ifp != NULL) 1309 if_free(ifp); 1310 if (sc->rl_irq) 1311 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->rl_irq); 1312 if (sc->rl_res) 1313 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1314 1315 1316 /* Unload and free the RX DMA ring memory and map */ 1317 1318 if (sc->rl_ldata.rl_rx_list_tag) { 1319 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1320 sc->rl_ldata.rl_rx_list_map); 1321 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1322 sc->rl_ldata.rl_rx_list, 1323 sc->rl_ldata.rl_rx_list_map); 1324 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1325 } 1326 1327 /* Unload and free the TX DMA ring memory and map */ 1328 1329 if (sc->rl_ldata.rl_tx_list_tag) { 1330 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1331 sc->rl_ldata.rl_tx_list_map); 1332 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1333 sc->rl_ldata.rl_tx_list, 1334 sc->rl_ldata.rl_tx_list_map); 1335 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1336 } 1337 1338 /* Destroy all the RX and TX buffer maps */ 1339 1340 if (sc->rl_ldata.rl_mtag) { 1341 for (i = 0; i < RL_TX_DESC_CNT; i++) 1342 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1343 sc->rl_ldata.rl_tx_dmamap[i]); 1344 for (i = 0; i < RL_RX_DESC_CNT; i++) 1345 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1346 sc->rl_ldata.rl_rx_dmamap[i]); 1347 bus_dma_tag_destroy(sc->rl_ldata.rl_mtag); 1348 } 1349 1350 /* Unload and free the stats buffer and map */ 1351 1352 if (sc->rl_ldata.rl_stag) { 1353 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1354 sc->rl_ldata.rl_rx_list_map); 1355 bus_dmamem_free(sc->rl_ldata.rl_stag, 1356 sc->rl_ldata.rl_stats, 1357 sc->rl_ldata.rl_smap); 1358 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1359 } 1360 1361 if (sc->rl_parent_tag) 1362 bus_dma_tag_destroy(sc->rl_parent_tag); 1363 1364 mtx_destroy(&sc->rl_mtx); 1365 1366 return (0); 1367 } 1368 1369 static int 1370 re_newbuf(sc, idx, m) 1371 struct rl_softc *sc; 1372 int idx; 1373 struct mbuf *m; 1374 { 1375 struct rl_dmaload_arg arg; 1376 struct mbuf *n = NULL; 1377 int error; 1378 1379 if (m == NULL) { 1380 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1381 if (n == NULL) 1382 return (ENOBUFS); 1383 m = n; 1384 } else 1385 m->m_data = m->m_ext.ext_buf; 1386 1387 m->m_len = m->m_pkthdr.len = MCLBYTES; 1388 #ifdef RE_FIXUP_RX 1389 /* 1390 * This is part of an evil trick to deal with non-x86 platforms. 1391 * The RealTek chip requires RX buffers to be aligned on 64-bit 1392 * boundaries, but that will hose non-x86 machines. To get around 1393 * this, we leave some empty space at the start of each buffer 1394 * and for non-x86 hosts, we copy the buffer back six bytes 1395 * to achieve word alignment. This is slightly more efficient 1396 * than allocating a new buffer, copying the contents, and 1397 * discarding the old buffer. 1398 */ 1399 m_adj(m, RE_ETHER_ALIGN); 1400 #endif 1401 arg.sc = sc; 1402 arg.rl_idx = idx; 1403 arg.rl_maxsegs = 1; 1404 arg.rl_flags = 0; 1405 arg.rl_ring = sc->rl_ldata.rl_rx_list; 1406 1407 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, 1408 sc->rl_ldata.rl_rx_dmamap[idx], m, re_dma_map_desc, 1409 &arg, BUS_DMA_NOWAIT); 1410 if (error || arg.rl_maxsegs != 1) { 1411 if (n != NULL) 1412 m_freem(n); 1413 return (ENOMEM); 1414 } 1415 1416 sc->rl_ldata.rl_rx_list[idx].rl_cmdstat |= htole32(RL_RDESC_CMD_OWN); 1417 sc->rl_ldata.rl_rx_mbuf[idx] = m; 1418 1419 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1420 sc->rl_ldata.rl_rx_dmamap[idx], 1421 BUS_DMASYNC_PREREAD); 1422 1423 return (0); 1424 } 1425 1426 #ifdef RE_FIXUP_RX 1427 static __inline void 1428 re_fixup_rx(m) 1429 struct mbuf *m; 1430 { 1431 int i; 1432 uint16_t *src, *dst; 1433 1434 src = mtod(m, uint16_t *); 1435 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1436 1437 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1438 *dst++ = *src++; 1439 1440 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1441 1442 return; 1443 } 1444 #endif 1445 1446 static int 1447 re_tx_list_init(sc) 1448 struct rl_softc *sc; 1449 { 1450 1451 RL_LOCK_ASSERT(sc); 1452 1453 bzero ((char *)sc->rl_ldata.rl_tx_list, RL_TX_LIST_SZ); 1454 bzero ((char *)&sc->rl_ldata.rl_tx_mbuf, 1455 (RL_TX_DESC_CNT * sizeof(struct mbuf *))); 1456 1457 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1458 sc->rl_ldata.rl_tx_list_map, BUS_DMASYNC_PREWRITE); 1459 sc->rl_ldata.rl_tx_prodidx = 0; 1460 sc->rl_ldata.rl_tx_considx = 0; 1461 sc->rl_ldata.rl_tx_free = RL_TX_DESC_CNT; 1462 1463 return (0); 1464 } 1465 1466 static int 1467 re_rx_list_init(sc) 1468 struct rl_softc *sc; 1469 { 1470 int i; 1471 1472 bzero ((char *)sc->rl_ldata.rl_rx_list, RL_RX_LIST_SZ); 1473 bzero ((char *)&sc->rl_ldata.rl_rx_mbuf, 1474 (RL_RX_DESC_CNT * sizeof(struct mbuf *))); 1475 1476 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1477 if (re_newbuf(sc, i, NULL) == ENOBUFS) 1478 return (ENOBUFS); 1479 } 1480 1481 /* Flush the RX descriptors */ 1482 1483 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1484 sc->rl_ldata.rl_rx_list_map, 1485 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1486 1487 sc->rl_ldata.rl_rx_prodidx = 0; 1488 sc->rl_head = sc->rl_tail = NULL; 1489 1490 return (0); 1491 } 1492 1493 /* 1494 * RX handler for C+ and 8169. For the gigE chips, we support 1495 * the reception of jumbo frames that have been fragmented 1496 * across multiple 2K mbuf cluster buffers. 1497 */ 1498 static void 1499 re_rxeof(sc) 1500 struct rl_softc *sc; 1501 { 1502 struct mbuf *m; 1503 struct ifnet *ifp; 1504 int i, total_len; 1505 struct rl_desc *cur_rx; 1506 u_int32_t rxstat, rxvlan; 1507 1508 RL_LOCK_ASSERT(sc); 1509 1510 ifp = sc->rl_ifp; 1511 i = sc->rl_ldata.rl_rx_prodidx; 1512 1513 /* Invalidate the descriptor memory */ 1514 1515 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1516 sc->rl_ldata.rl_rx_list_map, 1517 BUS_DMASYNC_POSTREAD); 1518 1519 while (!RL_OWN(&sc->rl_ldata.rl_rx_list[i])) { 1520 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1521 m = sc->rl_ldata.rl_rx_mbuf[i]; 1522 total_len = RL_RXBYTES(cur_rx); 1523 rxstat = le32toh(cur_rx->rl_cmdstat); 1524 rxvlan = le32toh(cur_rx->rl_vlanctl); 1525 1526 /* Invalidate the RX mbuf and unload its map */ 1527 1528 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1529 sc->rl_ldata.rl_rx_dmamap[i], 1530 BUS_DMASYNC_POSTWRITE); 1531 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1532 sc->rl_ldata.rl_rx_dmamap[i]); 1533 1534 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1535 m->m_len = RE_RX_DESC_BUFLEN; 1536 if (sc->rl_head == NULL) 1537 sc->rl_head = sc->rl_tail = m; 1538 else { 1539 m->m_flags &= ~M_PKTHDR; 1540 sc->rl_tail->m_next = m; 1541 sc->rl_tail = m; 1542 } 1543 re_newbuf(sc, i, NULL); 1544 RL_DESC_INC(i); 1545 continue; 1546 } 1547 1548 /* 1549 * NOTE: for the 8139C+, the frame length field 1550 * is always 12 bits in size, but for the gigE chips, 1551 * it is 13 bits (since the max RX frame length is 16K). 1552 * Unfortunately, all 32 bits in the status word 1553 * were already used, so to make room for the extra 1554 * length bit, RealTek took out the 'frame alignment 1555 * error' bit and shifted the other status bits 1556 * over one slot. The OWN, EOR, FS and LS bits are 1557 * still in the same places. We have already extracted 1558 * the frame length and checked the OWN bit, so rather 1559 * than using an alternate bit mapping, we shift the 1560 * status bits one space to the right so we can evaluate 1561 * them using the 8169 status as though it was in the 1562 * same format as that of the 8139C+. 1563 */ 1564 if (sc->rl_type == RL_8169) 1565 rxstat >>= 1; 1566 1567 /* 1568 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 1569 * set, but if CRC is clear, it will still be a valid frame. 1570 */ 1571 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 && 1572 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) { 1573 ifp->if_ierrors++; 1574 /* 1575 * If this is part of a multi-fragment packet, 1576 * discard all the pieces. 1577 */ 1578 if (sc->rl_head != NULL) { 1579 m_freem(sc->rl_head); 1580 sc->rl_head = sc->rl_tail = NULL; 1581 } 1582 re_newbuf(sc, i, m); 1583 RL_DESC_INC(i); 1584 continue; 1585 } 1586 1587 /* 1588 * If allocating a replacement mbuf fails, 1589 * reload the current one. 1590 */ 1591 1592 if (re_newbuf(sc, i, NULL)) { 1593 ifp->if_ierrors++; 1594 if (sc->rl_head != NULL) { 1595 m_freem(sc->rl_head); 1596 sc->rl_head = sc->rl_tail = NULL; 1597 } 1598 re_newbuf(sc, i, m); 1599 RL_DESC_INC(i); 1600 continue; 1601 } 1602 1603 RL_DESC_INC(i); 1604 1605 if (sc->rl_head != NULL) { 1606 m->m_len = total_len % RE_RX_DESC_BUFLEN; 1607 if (m->m_len == 0) 1608 m->m_len = RE_RX_DESC_BUFLEN; 1609 /* 1610 * Special case: if there's 4 bytes or less 1611 * in this buffer, the mbuf can be discarded: 1612 * the last 4 bytes is the CRC, which we don't 1613 * care about anyway. 1614 */ 1615 if (m->m_len <= ETHER_CRC_LEN) { 1616 sc->rl_tail->m_len -= 1617 (ETHER_CRC_LEN - m->m_len); 1618 m_freem(m); 1619 } else { 1620 m->m_len -= ETHER_CRC_LEN; 1621 m->m_flags &= ~M_PKTHDR; 1622 sc->rl_tail->m_next = m; 1623 } 1624 m = sc->rl_head; 1625 sc->rl_head = sc->rl_tail = NULL; 1626 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1627 } else 1628 m->m_pkthdr.len = m->m_len = 1629 (total_len - ETHER_CRC_LEN); 1630 1631 #ifdef RE_FIXUP_RX 1632 re_fixup_rx(m); 1633 #endif 1634 ifp->if_ipackets++; 1635 m->m_pkthdr.rcvif = ifp; 1636 1637 /* Do RX checksumming if enabled */ 1638 1639 if (ifp->if_capenable & IFCAP_RXCSUM) { 1640 1641 /* Check IP header checksum */ 1642 if (rxstat & RL_RDESC_STAT_PROTOID) 1643 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1644 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1645 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1646 1647 /* Check TCP/UDP checksum */ 1648 if ((RL_TCPPKT(rxstat) && 1649 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1650 (RL_UDPPKT(rxstat) && 1651 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1652 m->m_pkthdr.csum_flags |= 1653 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1654 m->m_pkthdr.csum_data = 0xffff; 1655 } 1656 } 1657 1658 if (rxvlan & RL_RDESC_VLANCTL_TAG) 1659 VLAN_INPUT_TAG(ifp, m, 1660 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)), continue); 1661 RL_UNLOCK(sc); 1662 (*ifp->if_input)(ifp, m); 1663 RL_LOCK(sc); 1664 } 1665 1666 /* Flush the RX DMA ring */ 1667 1668 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1669 sc->rl_ldata.rl_rx_list_map, 1670 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1671 1672 sc->rl_ldata.rl_rx_prodidx = i; 1673 } 1674 1675 static void 1676 re_txeof(sc) 1677 struct rl_softc *sc; 1678 { 1679 struct ifnet *ifp; 1680 u_int32_t txstat; 1681 int idx; 1682 1683 ifp = sc->rl_ifp; 1684 idx = sc->rl_ldata.rl_tx_considx; 1685 1686 /* Invalidate the TX descriptor list */ 1687 1688 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1689 sc->rl_ldata.rl_tx_list_map, 1690 BUS_DMASYNC_POSTREAD); 1691 1692 while (idx != sc->rl_ldata.rl_tx_prodidx) { 1693 1694 txstat = le32toh(sc->rl_ldata.rl_tx_list[idx].rl_cmdstat); 1695 if (txstat & RL_TDESC_CMD_OWN) 1696 break; 1697 1698 /* 1699 * We only stash mbufs in the last descriptor 1700 * in a fragment chain, which also happens to 1701 * be the only place where the TX status bits 1702 * are valid. 1703 */ 1704 1705 if (txstat & RL_TDESC_CMD_EOF) { 1706 m_freem(sc->rl_ldata.rl_tx_mbuf[idx]); 1707 sc->rl_ldata.rl_tx_mbuf[idx] = NULL; 1708 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1709 sc->rl_ldata.rl_tx_dmamap[idx]); 1710 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 1711 RL_TDESC_STAT_COLCNT)) 1712 ifp->if_collisions++; 1713 if (txstat & RL_TDESC_STAT_TXERRSUM) 1714 ifp->if_oerrors++; 1715 else 1716 ifp->if_opackets++; 1717 } 1718 sc->rl_ldata.rl_tx_free++; 1719 RL_DESC_INC(idx); 1720 } 1721 1722 /* No changes made to the TX ring, so no flush needed */ 1723 1724 if (idx != sc->rl_ldata.rl_tx_considx) { 1725 sc->rl_ldata.rl_tx_considx = idx; 1726 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1727 ifp->if_timer = 0; 1728 } 1729 1730 /* 1731 * If not all descriptors have been released reaped yet, 1732 * reload the timer so that we will eventually get another 1733 * interrupt that will cause us to re-enter this routine. 1734 * This is done in case the transmitter has gone idle. 1735 */ 1736 if (sc->rl_ldata.rl_tx_free != RL_TX_DESC_CNT) 1737 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 1738 } 1739 1740 static void 1741 re_tick(xsc) 1742 void *xsc; 1743 { 1744 struct rl_softc *sc; 1745 1746 sc = xsc; 1747 RL_LOCK(sc); 1748 re_tick_locked(sc); 1749 RL_UNLOCK(sc); 1750 } 1751 1752 static void 1753 re_tick_locked(sc) 1754 struct rl_softc *sc; 1755 { 1756 struct mii_data *mii; 1757 1758 RL_LOCK_ASSERT(sc); 1759 1760 mii = device_get_softc(sc->rl_miibus); 1761 1762 mii_tick(mii); 1763 1764 sc->rl_stat_ch = timeout(re_tick, sc, hz); 1765 } 1766 1767 #ifdef DEVICE_POLLING 1768 static void 1769 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1770 { 1771 struct rl_softc *sc = ifp->if_softc; 1772 1773 RL_LOCK(sc); 1774 re_poll_locked(ifp, cmd, count); 1775 RL_UNLOCK(sc); 1776 } 1777 1778 static void 1779 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1780 { 1781 struct rl_softc *sc = ifp->if_softc; 1782 1783 RL_LOCK_ASSERT(sc); 1784 1785 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1786 ether_poll_deregister(ifp); 1787 cmd = POLL_DEREGISTER; 1788 } 1789 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1790 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 1791 return; 1792 } 1793 1794 sc->rxcycles = count; 1795 re_rxeof(sc); 1796 re_txeof(sc); 1797 1798 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1799 re_start_locked(ifp); 1800 1801 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1802 u_int16_t status; 1803 1804 status = CSR_READ_2(sc, RL_ISR); 1805 if (status == 0xffff) 1806 return; 1807 if (status) 1808 CSR_WRITE_2(sc, RL_ISR, status); 1809 1810 /* 1811 * XXX check behaviour on receiver stalls. 1812 */ 1813 1814 if (status & RL_ISR_SYSTEM_ERR) { 1815 re_reset(sc); 1816 re_init_locked(sc); 1817 } 1818 } 1819 } 1820 #endif /* DEVICE_POLLING */ 1821 1822 static void 1823 re_intr(arg) 1824 void *arg; 1825 { 1826 struct rl_softc *sc; 1827 struct ifnet *ifp; 1828 u_int16_t status; 1829 1830 sc = arg; 1831 1832 RL_LOCK(sc); 1833 1834 ifp = sc->rl_ifp; 1835 1836 if (sc->suspended || !(ifp->if_flags & IFF_UP)) 1837 goto done_locked; 1838 1839 #ifdef DEVICE_POLLING 1840 if (ifp->if_flags & IFF_POLLING) 1841 goto done_locked; 1842 if ((ifp->if_capenable & IFCAP_POLLING) && 1843 ether_poll_register(re_poll, ifp)) { /* ok, disable interrupts */ 1844 CSR_WRITE_2(sc, RL_IMR, 0x0000); 1845 re_poll_locked(ifp, 0, 1); 1846 goto done_locked; 1847 } 1848 #endif /* DEVICE_POLLING */ 1849 1850 for (;;) { 1851 1852 status = CSR_READ_2(sc, RL_ISR); 1853 /* If the card has gone away the read returns 0xffff. */ 1854 if (status == 0xffff) 1855 break; 1856 if (status) 1857 CSR_WRITE_2(sc, RL_ISR, status); 1858 1859 if ((status & RL_INTRS_CPLUS) == 0) 1860 break; 1861 1862 if ((status & RL_ISR_RX_OK) || 1863 (status & RL_ISR_RX_ERR)) 1864 re_rxeof(sc); 1865 1866 if ((status & RL_ISR_TIMEOUT_EXPIRED) || 1867 (status & RL_ISR_TX_ERR) || 1868 (status & RL_ISR_TX_DESC_UNAVAIL)) 1869 re_txeof(sc); 1870 1871 if (status & RL_ISR_SYSTEM_ERR) { 1872 re_reset(sc); 1873 re_init_locked(sc); 1874 } 1875 1876 if (status & RL_ISR_LINKCHG) { 1877 untimeout(re_tick, sc, sc->rl_stat_ch); 1878 re_tick_locked(sc); 1879 } 1880 } 1881 1882 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1883 re_start_locked(ifp); 1884 1885 done_locked: 1886 RL_UNLOCK(sc); 1887 } 1888 1889 static int 1890 re_encap(sc, m_head, idx) 1891 struct rl_softc *sc; 1892 struct mbuf **m_head; 1893 int *idx; 1894 { 1895 struct mbuf *m_new = NULL; 1896 struct rl_dmaload_arg arg; 1897 bus_dmamap_t map; 1898 int error; 1899 struct m_tag *mtag; 1900 1901 RL_LOCK_ASSERT(sc); 1902 1903 if (sc->rl_ldata.rl_tx_free <= 4) 1904 return (EFBIG); 1905 1906 /* 1907 * Set up checksum offload. Note: checksum offload bits must 1908 * appear in all descriptors of a multi-descriptor transmit 1909 * attempt. This is according to testing done with an 8169 1910 * chip. This is a requirement. 1911 */ 1912 1913 arg.rl_flags = 0; 1914 1915 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) 1916 arg.rl_flags |= RL_TDESC_CMD_IPCSUM; 1917 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) 1918 arg.rl_flags |= RL_TDESC_CMD_TCPCSUM; 1919 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) 1920 arg.rl_flags |= RL_TDESC_CMD_UDPCSUM; 1921 1922 arg.sc = sc; 1923 arg.rl_idx = *idx; 1924 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 1925 if (arg.rl_maxsegs > 4) 1926 arg.rl_maxsegs -= 4; 1927 arg.rl_ring = sc->rl_ldata.rl_tx_list; 1928 1929 map = sc->rl_ldata.rl_tx_dmamap[*idx]; 1930 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 1931 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1932 1933 if (error && error != EFBIG) { 1934 printf("re%d: can't map mbuf (error %d)\n", sc->rl_unit, error); 1935 return (ENOBUFS); 1936 } 1937 1938 /* Too many segments to map, coalesce into a single mbuf */ 1939 1940 if (error || arg.rl_maxsegs == 0) { 1941 m_new = m_defrag(*m_head, M_DONTWAIT); 1942 if (m_new == NULL) 1943 return (ENOBUFS); 1944 else 1945 *m_head = m_new; 1946 1947 arg.sc = sc; 1948 arg.rl_idx = *idx; 1949 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 1950 arg.rl_ring = sc->rl_ldata.rl_tx_list; 1951 1952 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 1953 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 1954 if (error) { 1955 printf("re%d: can't map mbuf (error %d)\n", 1956 sc->rl_unit, error); 1957 return (EFBIG); 1958 } 1959 } 1960 1961 /* 1962 * Insure that the map for this transmission 1963 * is placed at the array index of the last descriptor 1964 * in this chain. (Swap last and first dmamaps.) 1965 */ 1966 sc->rl_ldata.rl_tx_dmamap[*idx] = 1967 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx]; 1968 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx] = map; 1969 1970 sc->rl_ldata.rl_tx_mbuf[arg.rl_idx] = *m_head; 1971 sc->rl_ldata.rl_tx_free -= arg.rl_maxsegs; 1972 1973 /* 1974 * Set up hardware VLAN tagging. Note: vlan tag info must 1975 * appear in the first descriptor of a multi-descriptor 1976 * transmission attempt. 1977 */ 1978 1979 mtag = VLAN_OUTPUT_TAG(sc->rl_ifp, *m_head); 1980 if (mtag != NULL) 1981 sc->rl_ldata.rl_tx_list[*idx].rl_vlanctl = 1982 htole32(htons(VLAN_TAG_VALUE(mtag)) | RL_TDESC_VLANCTL_TAG); 1983 1984 /* Transfer ownership of packet to the chip. */ 1985 1986 sc->rl_ldata.rl_tx_list[arg.rl_idx].rl_cmdstat |= 1987 htole32(RL_TDESC_CMD_OWN); 1988 if (*idx != arg.rl_idx) 1989 sc->rl_ldata.rl_tx_list[*idx].rl_cmdstat |= 1990 htole32(RL_TDESC_CMD_OWN); 1991 1992 RL_DESC_INC(arg.rl_idx); 1993 *idx = arg.rl_idx; 1994 1995 return (0); 1996 } 1997 1998 static void 1999 re_start(ifp) 2000 struct ifnet *ifp; 2001 { 2002 struct rl_softc *sc; 2003 2004 sc = ifp->if_softc; 2005 RL_LOCK(sc); 2006 re_start_locked(ifp); 2007 RL_UNLOCK(sc); 2008 } 2009 2010 /* 2011 * Main transmit routine for C+ and gigE NICs. 2012 */ 2013 static void 2014 re_start_locked(ifp) 2015 struct ifnet *ifp; 2016 { 2017 struct rl_softc *sc; 2018 struct mbuf *m_head = NULL; 2019 int idx, queued = 0; 2020 2021 sc = ifp->if_softc; 2022 2023 RL_LOCK_ASSERT(sc); 2024 2025 idx = sc->rl_ldata.rl_tx_prodidx; 2026 2027 while (sc->rl_ldata.rl_tx_mbuf[idx] == NULL) { 2028 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2029 if (m_head == NULL) 2030 break; 2031 2032 if (re_encap(sc, &m_head, &idx)) { 2033 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2034 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2035 break; 2036 } 2037 2038 /* 2039 * If there's a BPF listener, bounce a copy of this frame 2040 * to him. 2041 */ 2042 BPF_MTAP(ifp, m_head); 2043 2044 queued++; 2045 } 2046 2047 if (queued == 0) 2048 return; 2049 2050 /* Flush the TX descriptors */ 2051 2052 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2053 sc->rl_ldata.rl_tx_list_map, 2054 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2055 2056 sc->rl_ldata.rl_tx_prodidx = idx; 2057 2058 /* 2059 * RealTek put the TX poll request register in a different 2060 * location on the 8169 gigE chip. I don't know why. 2061 */ 2062 2063 if (sc->rl_type == RL_8169) 2064 CSR_WRITE_2(sc, RL_GTXSTART, RL_TXSTART_START); 2065 else 2066 CSR_WRITE_2(sc, RL_TXSTART, RL_TXSTART_START); 2067 2068 /* 2069 * Use the countdown timer for interrupt moderation. 2070 * 'TX done' interrupts are disabled. Instead, we reset the 2071 * countdown timer, which will begin counting until it hits 2072 * the value in the TIMERINT register, and then trigger an 2073 * interrupt. Each time we write to the TIMERCNT register, 2074 * the timer count is reset to 0. 2075 */ 2076 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2077 2078 /* 2079 * Set a timeout in case the chip goes out to lunch. 2080 */ 2081 ifp->if_timer = 5; 2082 } 2083 2084 static void 2085 re_init(xsc) 2086 void *xsc; 2087 { 2088 struct rl_softc *sc = xsc; 2089 2090 RL_LOCK(sc); 2091 re_init_locked(sc); 2092 RL_UNLOCK(sc); 2093 } 2094 2095 static void 2096 re_init_locked(sc) 2097 struct rl_softc *sc; 2098 { 2099 struct ifnet *ifp = sc->rl_ifp; 2100 struct mii_data *mii; 2101 u_int32_t rxcfg = 0; 2102 2103 RL_LOCK_ASSERT(sc); 2104 2105 mii = device_get_softc(sc->rl_miibus); 2106 2107 /* 2108 * Cancel pending I/O and free all RX/TX buffers. 2109 */ 2110 re_stop(sc); 2111 2112 /* 2113 * Enable C+ RX and TX mode, as well as VLAN stripping and 2114 * RX checksum offload. We must configure the C+ register 2115 * before all others. 2116 */ 2117 CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB| 2118 RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW| 2119 RL_CPLUSCMD_VLANSTRIP| 2120 (ifp->if_capenable & IFCAP_RXCSUM ? 2121 RL_CPLUSCMD_RXCSUM_ENB : 0)); 2122 2123 /* 2124 * Init our MAC address. Even though the chipset 2125 * documentation doesn't mention it, we need to enter "Config 2126 * register write enable" mode to modify the ID registers. 2127 */ 2128 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2129 CSR_WRITE_STREAM_4(sc, RL_IDR0, 2130 *(u_int32_t *)(&IFP2ENADDR(sc->rl_ifp)[0])); 2131 CSR_WRITE_STREAM_4(sc, RL_IDR4, 2132 *(u_int32_t *)(&IFP2ENADDR(sc->rl_ifp)[4])); 2133 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2134 2135 /* 2136 * For C+ mode, initialize the RX descriptors and mbufs. 2137 */ 2138 re_rx_list_init(sc); 2139 re_tx_list_init(sc); 2140 2141 /* 2142 * Enable transmit and receive. 2143 */ 2144 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2145 2146 /* 2147 * Set the initial TX and RX configuration. 2148 */ 2149 if (sc->rl_testmode) { 2150 if (sc->rl_type == RL_8169) 2151 CSR_WRITE_4(sc, RL_TXCFG, 2152 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2153 else 2154 CSR_WRITE_4(sc, RL_TXCFG, 2155 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2156 } else 2157 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2158 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 2159 2160 /* Set the individual bit to receive frames for this host only. */ 2161 rxcfg = CSR_READ_4(sc, RL_RXCFG); 2162 rxcfg |= RL_RXCFG_RX_INDIV; 2163 2164 /* If we want promiscuous mode, set the allframes bit. */ 2165 if (ifp->if_flags & IFF_PROMISC) 2166 rxcfg |= RL_RXCFG_RX_ALLPHYS; 2167 else 2168 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 2169 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2170 2171 /* 2172 * Set capture broadcast bit to capture broadcast frames. 2173 */ 2174 if (ifp->if_flags & IFF_BROADCAST) 2175 rxcfg |= RL_RXCFG_RX_BROAD; 2176 else 2177 rxcfg &= ~RL_RXCFG_RX_BROAD; 2178 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2179 2180 /* 2181 * Program the multicast filter, if necessary. 2182 */ 2183 re_setmulti(sc); 2184 2185 #ifdef DEVICE_POLLING 2186 /* 2187 * Disable interrupts if we are polling. 2188 */ 2189 if (ifp->if_flags & IFF_POLLING) 2190 CSR_WRITE_2(sc, RL_IMR, 0); 2191 else /* otherwise ... */ 2192 #endif /* DEVICE_POLLING */ 2193 /* 2194 * Enable interrupts. 2195 */ 2196 if (sc->rl_testmode) 2197 CSR_WRITE_2(sc, RL_IMR, 0); 2198 else 2199 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2200 2201 /* Set initial TX threshold */ 2202 sc->rl_txthresh = RL_TX_THRESH_INIT; 2203 2204 /* Start RX/TX process. */ 2205 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2206 #ifdef notdef 2207 /* Enable receiver and transmitter. */ 2208 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2209 #endif 2210 /* 2211 * Load the addresses of the RX and TX lists into the chip. 2212 */ 2213 2214 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2215 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2216 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2217 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2218 2219 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2220 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2221 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2222 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2223 2224 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2225 2226 /* 2227 * Initialize the timer interrupt register so that 2228 * a timer interrupt will be generated once the timer 2229 * reaches a certain number of ticks. The timer is 2230 * reloaded on each transmit. This gives us TX interrupt 2231 * moderation, which dramatically improves TX frame rate. 2232 */ 2233 if (sc->rl_type == RL_8169) 2234 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2235 else 2236 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2237 2238 /* 2239 * For 8169 gigE NICs, set the max allowed RX packet 2240 * size so we can receive jumbo frames. 2241 */ 2242 if (sc->rl_type == RL_8169) 2243 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2244 2245 if (sc->rl_testmode) 2246 return; 2247 2248 mii_mediachg(mii); 2249 2250 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX); 2251 2252 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2253 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2254 2255 sc->rl_stat_ch = timeout(re_tick, sc, hz); 2256 } 2257 2258 /* 2259 * Set media options. 2260 */ 2261 static int 2262 re_ifmedia_upd(ifp) 2263 struct ifnet *ifp; 2264 { 2265 struct rl_softc *sc; 2266 struct mii_data *mii; 2267 2268 sc = ifp->if_softc; 2269 mii = device_get_softc(sc->rl_miibus); 2270 mii_mediachg(mii); 2271 2272 return (0); 2273 } 2274 2275 /* 2276 * Report current media status. 2277 */ 2278 static void 2279 re_ifmedia_sts(ifp, ifmr) 2280 struct ifnet *ifp; 2281 struct ifmediareq *ifmr; 2282 { 2283 struct rl_softc *sc; 2284 struct mii_data *mii; 2285 2286 sc = ifp->if_softc; 2287 mii = device_get_softc(sc->rl_miibus); 2288 2289 mii_pollstat(mii); 2290 ifmr->ifm_active = mii->mii_media_active; 2291 ifmr->ifm_status = mii->mii_media_status; 2292 } 2293 2294 static int 2295 re_ioctl(ifp, command, data) 2296 struct ifnet *ifp; 2297 u_long command; 2298 caddr_t data; 2299 { 2300 struct rl_softc *sc = ifp->if_softc; 2301 struct ifreq *ifr = (struct ifreq *) data; 2302 struct mii_data *mii; 2303 int error = 0; 2304 2305 switch (command) { 2306 case SIOCSIFMTU: 2307 if (ifr->ifr_mtu > RL_JUMBO_MTU) 2308 error = EINVAL; 2309 ifp->if_mtu = ifr->ifr_mtu; 2310 break; 2311 case SIOCSIFFLAGS: 2312 RL_LOCK(sc); 2313 if (ifp->if_flags & IFF_UP) 2314 re_init_locked(sc); 2315 else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2316 re_stop(sc); 2317 RL_UNLOCK(sc); 2318 error = 0; 2319 break; 2320 case SIOCADDMULTI: 2321 case SIOCDELMULTI: 2322 RL_LOCK(sc); 2323 re_setmulti(sc); 2324 RL_UNLOCK(sc); 2325 error = 0; 2326 break; 2327 case SIOCGIFMEDIA: 2328 case SIOCSIFMEDIA: 2329 mii = device_get_softc(sc->rl_miibus); 2330 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2331 break; 2332 case SIOCSIFCAP: 2333 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_POLLING); 2334 ifp->if_capenable |= 2335 ifr->ifr_reqcap & (IFCAP_HWCSUM | IFCAP_POLLING); 2336 if (ifp->if_capenable & IFCAP_TXCSUM) 2337 ifp->if_hwassist = RE_CSUM_FEATURES; 2338 else 2339 ifp->if_hwassist = 0; 2340 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2341 re_init(sc); 2342 break; 2343 default: 2344 error = ether_ioctl(ifp, command, data); 2345 break; 2346 } 2347 2348 return (error); 2349 } 2350 2351 static void 2352 re_watchdog(ifp) 2353 struct ifnet *ifp; 2354 { 2355 struct rl_softc *sc; 2356 2357 sc = ifp->if_softc; 2358 RL_LOCK(sc); 2359 printf("re%d: watchdog timeout\n", sc->rl_unit); 2360 ifp->if_oerrors++; 2361 2362 re_txeof(sc); 2363 re_rxeof(sc); 2364 re_init_locked(sc); 2365 2366 RL_UNLOCK(sc); 2367 } 2368 2369 /* 2370 * Stop the adapter and free any mbufs allocated to the 2371 * RX and TX lists. 2372 */ 2373 static void 2374 re_stop(sc) 2375 struct rl_softc *sc; 2376 { 2377 register int i; 2378 struct ifnet *ifp; 2379 2380 RL_LOCK_ASSERT(sc); 2381 2382 ifp = sc->rl_ifp; 2383 ifp->if_timer = 0; 2384 2385 untimeout(re_tick, sc, sc->rl_stat_ch); 2386 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2387 #ifdef DEVICE_POLLING 2388 ether_poll_deregister(ifp); 2389 #endif /* DEVICE_POLLING */ 2390 2391 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2392 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2393 2394 if (sc->rl_head != NULL) { 2395 m_freem(sc->rl_head); 2396 sc->rl_head = sc->rl_tail = NULL; 2397 } 2398 2399 /* Free the TX list buffers. */ 2400 2401 for (i = 0; i < RL_TX_DESC_CNT; i++) { 2402 if (sc->rl_ldata.rl_tx_mbuf[i] != NULL) { 2403 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2404 sc->rl_ldata.rl_tx_dmamap[i]); 2405 m_freem(sc->rl_ldata.rl_tx_mbuf[i]); 2406 sc->rl_ldata.rl_tx_mbuf[i] = NULL; 2407 } 2408 } 2409 2410 /* Free the RX list buffers. */ 2411 2412 for (i = 0; i < RL_RX_DESC_CNT; i++) { 2413 if (sc->rl_ldata.rl_rx_mbuf[i] != NULL) { 2414 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2415 sc->rl_ldata.rl_rx_dmamap[i]); 2416 m_freem(sc->rl_ldata.rl_rx_mbuf[i]); 2417 sc->rl_ldata.rl_rx_mbuf[i] = NULL; 2418 } 2419 } 2420 } 2421 2422 /* 2423 * Device suspend routine. Stop the interface and save some PCI 2424 * settings in case the BIOS doesn't restore them properly on 2425 * resume. 2426 */ 2427 static int 2428 re_suspend(dev) 2429 device_t dev; 2430 { 2431 struct rl_softc *sc; 2432 2433 sc = device_get_softc(dev); 2434 2435 RL_LOCK(sc); 2436 re_stop(sc); 2437 sc->suspended = 1; 2438 RL_UNLOCK(sc); 2439 2440 return (0); 2441 } 2442 2443 /* 2444 * Device resume routine. Restore some PCI settings in case the BIOS 2445 * doesn't, re-enable busmastering, and restart the interface if 2446 * appropriate. 2447 */ 2448 static int 2449 re_resume(dev) 2450 device_t dev; 2451 { 2452 struct rl_softc *sc; 2453 struct ifnet *ifp; 2454 2455 sc = device_get_softc(dev); 2456 2457 RL_LOCK(sc); 2458 2459 ifp = sc->rl_ifp; 2460 2461 /* reinitialize interface if necessary */ 2462 if (ifp->if_flags & IFF_UP) 2463 re_init_locked(sc); 2464 2465 sc->suspended = 0; 2466 RL_UNLOCK(sc); 2467 2468 return (0); 2469 } 2470 2471 /* 2472 * Stop all chip I/O so that the kernel's probe routines don't 2473 * get confused by errant DMAs when rebooting. 2474 */ 2475 static void 2476 re_shutdown(dev) 2477 device_t dev; 2478 { 2479 struct rl_softc *sc; 2480 2481 sc = device_get_softc(dev); 2482 2483 RL_LOCK(sc); 2484 re_stop(sc); 2485 /* 2486 * Mark interface as down since otherwise we will panic if 2487 * interrupt comes in later on, which can happen in some 2488 * cases. 2489 */ 2490 sc->rl_ifp->if_flags &= ~IFF_UP; 2491 RL_UNLOCK(sc); 2492 } 2493