1 /*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44 /* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111 #ifdef HAVE_KERNEL_OPTION_HEADERS 112 #include "opt_device_polling.h" 113 #endif 114 115 #include <sys/param.h> 116 #include <sys/endian.h> 117 #include <sys/systm.h> 118 #include <sys/sockio.h> 119 #include <sys/mbuf.h> 120 #include <sys/malloc.h> 121 #include <sys/module.h> 122 #include <sys/kernel.h> 123 #include <sys/socket.h> 124 #include <sys/lock.h> 125 #include <sys/mutex.h> 126 #include <sys/taskqueue.h> 127 128 #include <net/if.h> 129 #include <net/if_arp.h> 130 #include <net/ethernet.h> 131 #include <net/if_dl.h> 132 #include <net/if_media.h> 133 #include <net/if_types.h> 134 #include <net/if_vlan_var.h> 135 136 #include <net/bpf.h> 137 138 #include <machine/bus.h> 139 #include <machine/resource.h> 140 #include <sys/bus.h> 141 #include <sys/rman.h> 142 143 #include <dev/mii/mii.h> 144 #include <dev/mii/miivar.h> 145 146 #include <dev/pci/pcireg.h> 147 #include <dev/pci/pcivar.h> 148 149 MODULE_DEPEND(re, pci, 1, 1, 1); 150 MODULE_DEPEND(re, ether, 1, 1, 1); 151 MODULE_DEPEND(re, miibus, 1, 1, 1); 152 153 /* "device miibus" required. See GENERIC if you get errors here. */ 154 #include "miibus_if.h" 155 156 /* 157 * Default to using PIO access for this driver. 158 */ 159 #define RE_USEIOSPACE 160 161 #include <pci/if_rlreg.h> 162 163 /* Tunables. */ 164 static int msi_disable = 0; 165 TUNABLE_INT("hw.re.msi_disable", &msi_disable); 166 167 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 168 169 /* 170 * Various supported device vendors/types and their names. 171 */ 172 static struct rl_type re_devs[] = { 173 { DLINK_VENDORID, DLINK_DEVICEID_528T, RL_HWREV_8169S, 174 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 175 { RT_VENDORID, RT_DEVICEID_8139, RL_HWREV_8139CPLUS, 176 "RealTek 8139C+ 10/100BaseTX" }, 177 { RT_VENDORID, RT_DEVICEID_8101E, RL_HWREV_8101E, 178 "RealTek 8101E PCIe 10/100baseTX" }, 179 { RT_VENDORID, RT_DEVICEID_8168, RL_HWREV_8168_SPIN1, 180 "RealTek 8168/8111B PCIe Gigabit Ethernet" }, 181 { RT_VENDORID, RT_DEVICEID_8168, RL_HWREV_8168_SPIN2, 182 "RealTek 8168/8111B PCIe Gigabit Ethernet" }, 183 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169, 184 "RealTek 8169 Gigabit Ethernet" }, 185 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169S, 186 "RealTek 8169S Single-chip Gigabit Ethernet" }, 187 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169_8110SB, 188 "RealTek 8169SB/8110SB Single-chip Gigabit Ethernet" }, 189 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169_8110SC, 190 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 191 { RT_VENDORID, RT_DEVICEID_8169SC, RL_HWREV_8169_8110SC, 192 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 193 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8110S, 194 "RealTek 8110S Single-chip Gigabit Ethernet" }, 195 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, RL_HWREV_8169S, 196 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 197 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, RL_HWREV_8169S, 198 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 199 { USR_VENDORID, USR_DEVICEID_997902, RL_HWREV_8169S, 200 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" }, 201 { 0, 0, 0, NULL } 202 }; 203 204 static struct rl_hwrev re_hwrevs[] = { 205 { RL_HWREV_8139, RL_8139, "" }, 206 { RL_HWREV_8139A, RL_8139, "A" }, 207 { RL_HWREV_8139AG, RL_8139, "A-G" }, 208 { RL_HWREV_8139B, RL_8139, "B" }, 209 { RL_HWREV_8130, RL_8139, "8130" }, 210 { RL_HWREV_8139C, RL_8139, "C" }, 211 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 212 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 213 { RL_HWREV_8168_SPIN1, RL_8169, "8168"}, 214 { RL_HWREV_8169, RL_8169, "8169"}, 215 { RL_HWREV_8169S, RL_8169, "8169S"}, 216 { RL_HWREV_8110S, RL_8169, "8110S"}, 217 { RL_HWREV_8169_8110SB, RL_8169, "8169SB"}, 218 { RL_HWREV_8169_8110SC, RL_8169, "8169SC"}, 219 { RL_HWREV_8100, RL_8139, "8100"}, 220 { RL_HWREV_8101, RL_8139, "8101"}, 221 { RL_HWREV_8100E, RL_8169, "8100E"}, 222 { RL_HWREV_8101E, RL_8169, "8101E"}, 223 { RL_HWREV_8168_SPIN2, RL_8169, "8168"}, 224 { 0, 0, NULL } 225 }; 226 227 static int re_probe (device_t); 228 static int re_attach (device_t); 229 static int re_detach (device_t); 230 231 static int re_encap (struct rl_softc *, struct mbuf **, int *); 232 233 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 234 static void re_dma_map_desc (void *, bus_dma_segment_t *, int, 235 bus_size_t, int); 236 static int re_allocmem (device_t, struct rl_softc *); 237 static int re_newbuf (struct rl_softc *, int, struct mbuf *); 238 static int re_rx_list_init (struct rl_softc *); 239 static int re_tx_list_init (struct rl_softc *); 240 #ifdef RE_FIXUP_RX 241 static __inline void re_fixup_rx 242 (struct mbuf *); 243 #endif 244 static int re_rxeof (struct rl_softc *); 245 static void re_txeof (struct rl_softc *); 246 #ifdef DEVICE_POLLING 247 static void re_poll (struct ifnet *, enum poll_cmd, int); 248 static void re_poll_locked (struct ifnet *, enum poll_cmd, int); 249 #endif 250 static int re_intr (void *); 251 static void re_tick (void *); 252 static void re_tx_task (void *, int); 253 static void re_int_task (void *, int); 254 static void re_start (struct ifnet *); 255 static int re_ioctl (struct ifnet *, u_long, caddr_t); 256 static void re_init (void *); 257 static void re_init_locked (struct rl_softc *); 258 static void re_stop (struct rl_softc *); 259 static void re_watchdog (struct rl_softc *); 260 static int re_suspend (device_t); 261 static int re_resume (device_t); 262 static void re_shutdown (device_t); 263 static int re_ifmedia_upd (struct ifnet *); 264 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 265 266 static void re_eeprom_putbyte (struct rl_softc *, int); 267 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 268 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 269 static int re_gmii_readreg (device_t, int, int); 270 static int re_gmii_writereg (device_t, int, int, int); 271 272 static int re_miibus_readreg (device_t, int, int); 273 static int re_miibus_writereg (device_t, int, int, int); 274 static void re_miibus_statchg (device_t); 275 276 static void re_setmulti (struct rl_softc *); 277 static void re_reset (struct rl_softc *); 278 279 #ifdef RE_DIAG 280 static int re_diag (struct rl_softc *); 281 #endif 282 283 #ifdef RE_USEIOSPACE 284 #define RL_RES SYS_RES_IOPORT 285 #define RL_RID RL_PCI_LOIO 286 #else 287 #define RL_RES SYS_RES_MEMORY 288 #define RL_RID RL_PCI_LOMEM 289 #endif 290 291 static device_method_t re_methods[] = { 292 /* Device interface */ 293 DEVMETHOD(device_probe, re_probe), 294 DEVMETHOD(device_attach, re_attach), 295 DEVMETHOD(device_detach, re_detach), 296 DEVMETHOD(device_suspend, re_suspend), 297 DEVMETHOD(device_resume, re_resume), 298 DEVMETHOD(device_shutdown, re_shutdown), 299 300 /* bus interface */ 301 DEVMETHOD(bus_print_child, bus_generic_print_child), 302 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 303 304 /* MII interface */ 305 DEVMETHOD(miibus_readreg, re_miibus_readreg), 306 DEVMETHOD(miibus_writereg, re_miibus_writereg), 307 DEVMETHOD(miibus_statchg, re_miibus_statchg), 308 309 { 0, 0 } 310 }; 311 312 static driver_t re_driver = { 313 "re", 314 re_methods, 315 sizeof(struct rl_softc) 316 }; 317 318 static devclass_t re_devclass; 319 320 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 321 DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0); 322 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 323 324 #define EE_SET(x) \ 325 CSR_WRITE_1(sc, RL_EECMD, \ 326 CSR_READ_1(sc, RL_EECMD) | x) 327 328 #define EE_CLR(x) \ 329 CSR_WRITE_1(sc, RL_EECMD, \ 330 CSR_READ_1(sc, RL_EECMD) & ~x) 331 332 /* 333 * Send a read command and address to the EEPROM, check for ACK. 334 */ 335 static void 336 re_eeprom_putbyte(sc, addr) 337 struct rl_softc *sc; 338 int addr; 339 { 340 register int d, i; 341 342 d = addr | (RL_9346_READ << sc->rl_eewidth); 343 344 /* 345 * Feed in each bit and strobe the clock. 346 */ 347 348 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 349 if (d & i) { 350 EE_SET(RL_EE_DATAIN); 351 } else { 352 EE_CLR(RL_EE_DATAIN); 353 } 354 DELAY(100); 355 EE_SET(RL_EE_CLK); 356 DELAY(150); 357 EE_CLR(RL_EE_CLK); 358 DELAY(100); 359 } 360 361 return; 362 } 363 364 /* 365 * Read a word of data stored in the EEPROM at address 'addr.' 366 */ 367 static void 368 re_eeprom_getword(sc, addr, dest) 369 struct rl_softc *sc; 370 int addr; 371 u_int16_t *dest; 372 { 373 register int i; 374 u_int16_t word = 0; 375 376 /* 377 * Send address of word we want to read. 378 */ 379 re_eeprom_putbyte(sc, addr); 380 381 /* 382 * Start reading bits from EEPROM. 383 */ 384 for (i = 0x8000; i; i >>= 1) { 385 EE_SET(RL_EE_CLK); 386 DELAY(100); 387 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 388 word |= i; 389 EE_CLR(RL_EE_CLK); 390 DELAY(100); 391 } 392 393 *dest = word; 394 395 return; 396 } 397 398 /* 399 * Read a sequence of words from the EEPROM. 400 */ 401 static void 402 re_read_eeprom(sc, dest, off, cnt) 403 struct rl_softc *sc; 404 caddr_t dest; 405 int off; 406 int cnt; 407 { 408 int i; 409 u_int16_t word = 0, *ptr; 410 411 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 412 413 DELAY(100); 414 415 for (i = 0; i < cnt; i++) { 416 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 417 re_eeprom_getword(sc, off + i, &word); 418 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 419 ptr = (u_int16_t *)(dest + (i * 2)); 420 *ptr = word; 421 } 422 423 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 424 425 return; 426 } 427 428 static int 429 re_gmii_readreg(dev, phy, reg) 430 device_t dev; 431 int phy, reg; 432 { 433 struct rl_softc *sc; 434 u_int32_t rval; 435 int i; 436 437 if (phy != 1) 438 return (0); 439 440 sc = device_get_softc(dev); 441 442 /* Let the rgephy driver read the GMEDIASTAT register */ 443 444 if (reg == RL_GMEDIASTAT) { 445 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 446 return (rval); 447 } 448 449 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 450 DELAY(1000); 451 452 for (i = 0; i < RL_TIMEOUT; i++) { 453 rval = CSR_READ_4(sc, RL_PHYAR); 454 if (rval & RL_PHYAR_BUSY) 455 break; 456 DELAY(100); 457 } 458 459 if (i == RL_TIMEOUT) { 460 device_printf(sc->rl_dev, "PHY read failed\n"); 461 return (0); 462 } 463 464 return (rval & RL_PHYAR_PHYDATA); 465 } 466 467 static int 468 re_gmii_writereg(dev, phy, reg, data) 469 device_t dev; 470 int phy, reg, data; 471 { 472 struct rl_softc *sc; 473 u_int32_t rval; 474 int i; 475 476 sc = device_get_softc(dev); 477 478 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 479 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 480 DELAY(1000); 481 482 for (i = 0; i < RL_TIMEOUT; i++) { 483 rval = CSR_READ_4(sc, RL_PHYAR); 484 if (!(rval & RL_PHYAR_BUSY)) 485 break; 486 DELAY(100); 487 } 488 489 if (i == RL_TIMEOUT) { 490 device_printf(sc->rl_dev, "PHY write failed\n"); 491 return (0); 492 } 493 494 return (0); 495 } 496 497 static int 498 re_miibus_readreg(dev, phy, reg) 499 device_t dev; 500 int phy, reg; 501 { 502 struct rl_softc *sc; 503 u_int16_t rval = 0; 504 u_int16_t re8139_reg = 0; 505 506 sc = device_get_softc(dev); 507 508 if (sc->rl_type == RL_8169) { 509 rval = re_gmii_readreg(dev, phy, reg); 510 return (rval); 511 } 512 513 /* Pretend the internal PHY is only at address 0 */ 514 if (phy) { 515 return (0); 516 } 517 switch (reg) { 518 case MII_BMCR: 519 re8139_reg = RL_BMCR; 520 break; 521 case MII_BMSR: 522 re8139_reg = RL_BMSR; 523 break; 524 case MII_ANAR: 525 re8139_reg = RL_ANAR; 526 break; 527 case MII_ANER: 528 re8139_reg = RL_ANER; 529 break; 530 case MII_ANLPAR: 531 re8139_reg = RL_LPAR; 532 break; 533 case MII_PHYIDR1: 534 case MII_PHYIDR2: 535 return (0); 536 /* 537 * Allow the rlphy driver to read the media status 538 * register. If we have a link partner which does not 539 * support NWAY, this is the register which will tell 540 * us the results of parallel detection. 541 */ 542 case RL_MEDIASTAT: 543 rval = CSR_READ_1(sc, RL_MEDIASTAT); 544 return (rval); 545 default: 546 device_printf(sc->rl_dev, "bad phy register\n"); 547 return (0); 548 } 549 rval = CSR_READ_2(sc, re8139_reg); 550 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 551 /* 8139C+ has different bit layout. */ 552 rval &= ~(BMCR_LOOP | BMCR_ISO); 553 } 554 return (rval); 555 } 556 557 static int 558 re_miibus_writereg(dev, phy, reg, data) 559 device_t dev; 560 int phy, reg, data; 561 { 562 struct rl_softc *sc; 563 u_int16_t re8139_reg = 0; 564 int rval = 0; 565 566 sc = device_get_softc(dev); 567 568 if (sc->rl_type == RL_8169) { 569 rval = re_gmii_writereg(dev, phy, reg, data); 570 return (rval); 571 } 572 573 /* Pretend the internal PHY is only at address 0 */ 574 if (phy) 575 return (0); 576 577 switch (reg) { 578 case MII_BMCR: 579 re8139_reg = RL_BMCR; 580 if (sc->rl_type == RL_8139CPLUS) { 581 /* 8139C+ has different bit layout. */ 582 data &= ~(BMCR_LOOP | BMCR_ISO); 583 } 584 break; 585 case MII_BMSR: 586 re8139_reg = RL_BMSR; 587 break; 588 case MII_ANAR: 589 re8139_reg = RL_ANAR; 590 break; 591 case MII_ANER: 592 re8139_reg = RL_ANER; 593 break; 594 case MII_ANLPAR: 595 re8139_reg = RL_LPAR; 596 break; 597 case MII_PHYIDR1: 598 case MII_PHYIDR2: 599 return (0); 600 break; 601 default: 602 device_printf(sc->rl_dev, "bad phy register\n"); 603 return (0); 604 } 605 CSR_WRITE_2(sc, re8139_reg, data); 606 return (0); 607 } 608 609 static void 610 re_miibus_statchg(dev) 611 device_t dev; 612 { 613 614 } 615 616 /* 617 * Program the 64-bit multicast hash filter. 618 */ 619 static void 620 re_setmulti(sc) 621 struct rl_softc *sc; 622 { 623 struct ifnet *ifp; 624 int h = 0; 625 u_int32_t hashes[2] = { 0, 0 }; 626 struct ifmultiaddr *ifma; 627 u_int32_t rxfilt; 628 int mcnt = 0; 629 u_int32_t hwrev; 630 631 RL_LOCK_ASSERT(sc); 632 633 ifp = sc->rl_ifp; 634 635 rxfilt = CSR_READ_4(sc, RL_RXCFG); 636 637 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 638 rxfilt |= RL_RXCFG_RX_MULTI; 639 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 640 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 641 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 642 return; 643 } 644 645 /* first, zot all the existing hash bits */ 646 CSR_WRITE_4(sc, RL_MAR0, 0); 647 CSR_WRITE_4(sc, RL_MAR4, 0); 648 649 /* now program new ones */ 650 IF_ADDR_LOCK(ifp); 651 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 652 if (ifma->ifma_addr->sa_family != AF_LINK) 653 continue; 654 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 655 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 656 if (h < 32) 657 hashes[0] |= (1 << h); 658 else 659 hashes[1] |= (1 << (h - 32)); 660 mcnt++; 661 } 662 IF_ADDR_UNLOCK(ifp); 663 664 if (mcnt) 665 rxfilt |= RL_RXCFG_RX_MULTI; 666 else 667 rxfilt &= ~RL_RXCFG_RX_MULTI; 668 669 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 670 671 /* 672 * For some unfathomable reason, RealTek decided to reverse 673 * the order of the multicast hash registers in the PCI Express 674 * parts. This means we have to write the hash pattern in reverse 675 * order for those devices. 676 */ 677 678 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 679 680 if (hwrev == RL_HWREV_8100E || hwrev == RL_HWREV_8101E || 681 hwrev == RL_HWREV_8168_SPIN1 || hwrev == RL_HWREV_8168_SPIN2) { 682 CSR_WRITE_4(sc, RL_MAR0, bswap32(hashes[1])); 683 CSR_WRITE_4(sc, RL_MAR4, bswap32(hashes[0])); 684 } else { 685 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 686 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 687 } 688 } 689 690 static void 691 re_reset(sc) 692 struct rl_softc *sc; 693 { 694 register int i; 695 696 RL_LOCK_ASSERT(sc); 697 698 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 699 700 for (i = 0; i < RL_TIMEOUT; i++) { 701 DELAY(10); 702 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 703 break; 704 } 705 if (i == RL_TIMEOUT) 706 device_printf(sc->rl_dev, "reset never completed!\n"); 707 708 CSR_WRITE_1(sc, 0x82, 1); 709 } 710 711 #ifdef RE_DIAG 712 713 /* 714 * The following routine is designed to test for a defect on some 715 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 716 * lines connected to the bus, however for a 32-bit only card, they 717 * should be pulled high. The result of this defect is that the 718 * NIC will not work right if you plug it into a 64-bit slot: DMA 719 * operations will be done with 64-bit transfers, which will fail 720 * because the 64-bit data lines aren't connected. 721 * 722 * There's no way to work around this (short of talking a soldering 723 * iron to the board), however we can detect it. The method we use 724 * here is to put the NIC into digital loopback mode, set the receiver 725 * to promiscuous mode, and then try to send a frame. We then compare 726 * the frame data we sent to what was received. If the data matches, 727 * then the NIC is working correctly, otherwise we know the user has 728 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 729 * slot. In the latter case, there's no way the NIC can work correctly, 730 * so we print out a message on the console and abort the device attach. 731 */ 732 733 static int 734 re_diag(sc) 735 struct rl_softc *sc; 736 { 737 struct ifnet *ifp = sc->rl_ifp; 738 struct mbuf *m0; 739 struct ether_header *eh; 740 struct rl_desc *cur_rx; 741 u_int16_t status; 742 u_int32_t rxstat; 743 int total_len, i, error = 0, phyaddr; 744 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 745 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 746 747 /* Allocate a single mbuf */ 748 MGETHDR(m0, M_DONTWAIT, MT_DATA); 749 if (m0 == NULL) 750 return (ENOBUFS); 751 752 RL_LOCK(sc); 753 754 /* 755 * Initialize the NIC in test mode. This sets the chip up 756 * so that it can send and receive frames, but performs the 757 * following special functions: 758 * - Puts receiver in promiscuous mode 759 * - Enables digital loopback mode 760 * - Leaves interrupts turned off 761 */ 762 763 ifp->if_flags |= IFF_PROMISC; 764 sc->rl_testmode = 1; 765 re_reset(sc); 766 re_init_locked(sc); 767 sc->rl_link = 1; 768 if (sc->rl_type == RL_8169) 769 phyaddr = 1; 770 else 771 phyaddr = 0; 772 773 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 774 for (i = 0; i < RL_TIMEOUT; i++) { 775 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 776 if (!(status & BMCR_RESET)) 777 break; 778 } 779 780 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 781 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 782 783 DELAY(100000); 784 785 /* Put some data in the mbuf */ 786 787 eh = mtod(m0, struct ether_header *); 788 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 789 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 790 eh->ether_type = htons(ETHERTYPE_IP); 791 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 792 793 /* 794 * Queue the packet, start transmission. 795 * Note: IF_HANDOFF() ultimately calls re_start() for us. 796 */ 797 798 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 799 RL_UNLOCK(sc); 800 /* XXX: re_diag must not be called when in ALTQ mode */ 801 IF_HANDOFF(&ifp->if_snd, m0, ifp); 802 RL_LOCK(sc); 803 m0 = NULL; 804 805 /* Wait for it to propagate through the chip */ 806 807 DELAY(100000); 808 for (i = 0; i < RL_TIMEOUT; i++) { 809 status = CSR_READ_2(sc, RL_ISR); 810 CSR_WRITE_2(sc, RL_ISR, status); 811 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 812 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 813 break; 814 DELAY(10); 815 } 816 817 if (i == RL_TIMEOUT) { 818 device_printf(sc->rl_dev, 819 "diagnostic failed, failed to receive packet in" 820 " loopback mode\n"); 821 error = EIO; 822 goto done; 823 } 824 825 /* 826 * The packet should have been dumped into the first 827 * entry in the RX DMA ring. Grab it from there. 828 */ 829 830 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 831 sc->rl_ldata.rl_rx_list_map, 832 BUS_DMASYNC_POSTREAD); 833 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 834 sc->rl_ldata.rl_rx_dmamap[0], 835 BUS_DMASYNC_POSTWRITE); 836 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 837 sc->rl_ldata.rl_rx_dmamap[0]); 838 839 m0 = sc->rl_ldata.rl_rx_mbuf[0]; 840 sc->rl_ldata.rl_rx_mbuf[0] = NULL; 841 eh = mtod(m0, struct ether_header *); 842 843 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 844 total_len = RL_RXBYTES(cur_rx); 845 rxstat = le32toh(cur_rx->rl_cmdstat); 846 847 if (total_len != ETHER_MIN_LEN) { 848 device_printf(sc->rl_dev, 849 "diagnostic failed, received short packet\n"); 850 error = EIO; 851 goto done; 852 } 853 854 /* Test that the received packet data matches what we sent. */ 855 856 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 857 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 858 ntohs(eh->ether_type) != ETHERTYPE_IP) { 859 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 860 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 861 dst, ":", src, ":", ETHERTYPE_IP); 862 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 863 eh->ether_dhost, ":", eh->ether_shost, ":", 864 ntohs(eh->ether_type)); 865 device_printf(sc->rl_dev, "You may have a defective 32-bit " 866 "NIC plugged into a 64-bit PCI slot.\n"); 867 device_printf(sc->rl_dev, "Please re-install the NIC in a " 868 "32-bit slot for proper operation.\n"); 869 device_printf(sc->rl_dev, "Read the re(4) man page for more " 870 "details.\n"); 871 error = EIO; 872 } 873 874 done: 875 /* Turn interface off, release resources */ 876 877 sc->rl_testmode = 0; 878 sc->rl_link = 0; 879 ifp->if_flags &= ~IFF_PROMISC; 880 re_stop(sc); 881 if (m0 != NULL) 882 m_freem(m0); 883 884 RL_UNLOCK(sc); 885 886 return (error); 887 } 888 889 #endif 890 891 /* 892 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 893 * IDs against our list and return a device name if we find a match. 894 */ 895 static int 896 re_probe(dev) 897 device_t dev; 898 { 899 struct rl_type *t; 900 struct rl_softc *sc; 901 int rid; 902 u_int32_t hwrev; 903 904 t = re_devs; 905 sc = device_get_softc(dev); 906 907 while (t->rl_name != NULL) { 908 if ((pci_get_vendor(dev) == t->rl_vid) && 909 (pci_get_device(dev) == t->rl_did)) { 910 /* 911 * Only attach to rev. 3 of the Linksys EG1032 adapter. 912 * Rev. 2 i supported by sk(4). 913 */ 914 if ((t->rl_vid == LINKSYS_VENDORID) && 915 (t->rl_did == LINKSYS_DEVICEID_EG1032) && 916 (pci_get_subdevice(dev) != 917 LINKSYS_SUBDEVICE_EG1032_REV3)) { 918 t++; 919 continue; 920 } 921 922 /* 923 * Temporarily map the I/O space 924 * so we can read the chip ID register. 925 */ 926 rid = RL_RID; 927 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 928 RF_ACTIVE); 929 if (sc->rl_res == NULL) { 930 device_printf(dev, 931 "couldn't map ports/memory\n"); 932 return (ENXIO); 933 } 934 sc->rl_btag = rman_get_bustag(sc->rl_res); 935 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 936 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 937 bus_release_resource(dev, RL_RES, 938 RL_RID, sc->rl_res); 939 if (t->rl_basetype == hwrev) { 940 device_set_desc(dev, t->rl_name); 941 return (BUS_PROBE_DEFAULT); 942 } 943 } 944 t++; 945 } 946 947 return (ENXIO); 948 } 949 950 /* 951 * This routine takes the segment list provided as the result of 952 * a bus_dma_map_load() operation and assigns the addresses/lengths 953 * to RealTek DMA descriptors. This can be called either by the RX 954 * code or the TX code. In the RX case, we'll probably wind up mapping 955 * at most one segment. For the TX case, there could be any number of 956 * segments since TX packets may span multiple mbufs. In either case, 957 * if the number of segments is larger than the rl_maxsegs limit 958 * specified by the caller, we abort the mapping operation. Sadly, 959 * whoever designed the buffer mapping API did not provide a way to 960 * return an error from here, so we have to fake it a bit. 961 */ 962 963 static void 964 re_dma_map_desc(arg, segs, nseg, mapsize, error) 965 void *arg; 966 bus_dma_segment_t *segs; 967 int nseg; 968 bus_size_t mapsize; 969 int error; 970 { 971 struct rl_dmaload_arg *ctx; 972 struct rl_desc *d = NULL; 973 int i = 0, idx; 974 u_int32_t cmdstat; 975 int totlen = 0; 976 977 if (error) 978 return; 979 980 ctx = arg; 981 982 /* Signal error to caller if there's too many segments */ 983 if (nseg > ctx->rl_maxsegs) { 984 ctx->rl_maxsegs = 0; 985 return; 986 } 987 988 /* 989 * Map the segment array into descriptors. Note that we set the 990 * start-of-frame and end-of-frame markers for either TX or RX, but 991 * they really only have meaning in the TX case. (In the RX case, 992 * it's the chip that tells us where packets begin and end.) 993 * We also keep track of the end of the ring and set the 994 * end-of-ring bits as needed, and we set the ownership bits 995 * in all except the very first descriptor. (The caller will 996 * set this descriptor later when it start transmission or 997 * reception.) 998 */ 999 idx = ctx->rl_idx; 1000 for (;;) { 1001 d = &ctx->rl_ring[idx]; 1002 if (le32toh(d->rl_cmdstat) & RL_RDESC_STAT_OWN) { 1003 ctx->rl_maxsegs = 0; 1004 return; 1005 } 1006 cmdstat = segs[i].ds_len; 1007 totlen += segs[i].ds_len; 1008 d->rl_vlanctl = 0; 1009 d->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 1010 d->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 1011 if (i == 0) 1012 cmdstat |= RL_TDESC_CMD_SOF; 1013 else 1014 cmdstat |= RL_TDESC_CMD_OWN; 1015 if (idx == (RL_RX_DESC_CNT - 1)) 1016 cmdstat |= RL_TDESC_CMD_EOR; 1017 d->rl_cmdstat = htole32(cmdstat | ctx->rl_flags); 1018 i++; 1019 if (i == nseg) 1020 break; 1021 RL_DESC_INC(idx); 1022 } 1023 1024 d->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 1025 ctx->rl_maxsegs = nseg; 1026 ctx->rl_idx = idx; 1027 } 1028 1029 /* 1030 * Map a single buffer address. 1031 */ 1032 1033 static void 1034 re_dma_map_addr(arg, segs, nseg, error) 1035 void *arg; 1036 bus_dma_segment_t *segs; 1037 int nseg; 1038 int error; 1039 { 1040 bus_addr_t *addr; 1041 1042 if (error) 1043 return; 1044 1045 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 1046 addr = arg; 1047 *addr = segs->ds_addr; 1048 } 1049 1050 static int 1051 re_allocmem(dev, sc) 1052 device_t dev; 1053 struct rl_softc *sc; 1054 { 1055 int error; 1056 int nseg; 1057 int i; 1058 1059 /* 1060 * Allocate map for RX mbufs. 1061 */ 1062 nseg = 32; 1063 error = bus_dma_tag_create(sc->rl_parent_tag, ETHER_ALIGN, 0, 1064 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1065 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 1066 NULL, NULL, &sc->rl_ldata.rl_mtag); 1067 if (error) { 1068 device_printf(dev, "could not allocate dma tag\n"); 1069 return (ENOMEM); 1070 } 1071 1072 /* 1073 * Allocate map for TX descriptor list. 1074 */ 1075 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1076 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1077 NULL, RL_TX_LIST_SZ, 1, RL_TX_LIST_SZ, 0, 1078 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1079 if (error) { 1080 device_printf(dev, "could not allocate dma tag\n"); 1081 return (ENOMEM); 1082 } 1083 1084 /* Allocate DMA'able memory for the TX ring */ 1085 1086 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1087 (void **)&sc->rl_ldata.rl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1088 &sc->rl_ldata.rl_tx_list_map); 1089 if (error) 1090 return (ENOMEM); 1091 1092 /* Load the map for the TX ring. */ 1093 1094 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1095 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1096 RL_TX_LIST_SZ, re_dma_map_addr, 1097 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1098 1099 /* Create DMA maps for TX buffers */ 1100 1101 for (i = 0; i < RL_TX_DESC_CNT; i++) { 1102 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1103 &sc->rl_ldata.rl_tx_dmamap[i]); 1104 if (error) { 1105 device_printf(dev, "can't create DMA map for TX\n"); 1106 return (ENOMEM); 1107 } 1108 } 1109 1110 /* 1111 * Allocate map for RX descriptor list. 1112 */ 1113 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1114 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1115 NULL, RL_RX_LIST_SZ, 1, RL_RX_LIST_SZ, 0, 1116 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1117 if (error) { 1118 device_printf(dev, "could not allocate dma tag\n"); 1119 return (ENOMEM); 1120 } 1121 1122 /* Allocate DMA'able memory for the RX ring */ 1123 1124 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1125 (void **)&sc->rl_ldata.rl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1126 &sc->rl_ldata.rl_rx_list_map); 1127 if (error) 1128 return (ENOMEM); 1129 1130 /* Load the map for the RX ring. */ 1131 1132 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1133 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1134 RL_RX_LIST_SZ, re_dma_map_addr, 1135 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1136 1137 /* Create DMA maps for RX buffers */ 1138 1139 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1140 error = bus_dmamap_create(sc->rl_ldata.rl_mtag, 0, 1141 &sc->rl_ldata.rl_rx_dmamap[i]); 1142 if (error) { 1143 device_printf(dev, "can't create DMA map for RX\n"); 1144 return (ENOMEM); 1145 } 1146 } 1147 1148 return (0); 1149 } 1150 1151 /* 1152 * Attach the interface. Allocate softc structures, do ifmedia 1153 * setup and ethernet/BPF attach. 1154 */ 1155 static int 1156 re_attach(dev) 1157 device_t dev; 1158 { 1159 u_char eaddr[ETHER_ADDR_LEN]; 1160 u_int16_t as[ETHER_ADDR_LEN / 2]; 1161 struct rl_softc *sc; 1162 struct ifnet *ifp; 1163 struct rl_hwrev *hw_rev; 1164 int hwrev; 1165 u_int16_t re_did = 0; 1166 int error = 0, rid, i; 1167 int msic, reg; 1168 1169 sc = device_get_softc(dev); 1170 sc->rl_dev = dev; 1171 1172 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1173 MTX_DEF); 1174 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1175 1176 /* 1177 * Map control/status registers. 1178 */ 1179 pci_enable_busmaster(dev); 1180 1181 rid = RL_RID; 1182 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 1183 RF_ACTIVE); 1184 1185 if (sc->rl_res == NULL) { 1186 device_printf(dev, "couldn't map ports/memory\n"); 1187 error = ENXIO; 1188 goto fail; 1189 } 1190 1191 sc->rl_btag = rman_get_bustag(sc->rl_res); 1192 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1193 1194 msic = 0; 1195 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 1196 msic = pci_msi_count(dev); 1197 if (bootverbose) 1198 device_printf(dev, "MSI count : %d\n", msic); 1199 } 1200 if (msic == RL_MSI_MESSAGES && msi_disable == 0) { 1201 if (pci_alloc_msi(dev, &msic) == 0) { 1202 if (msic == RL_MSI_MESSAGES) { 1203 device_printf(dev, "Using %d MSI messages\n", 1204 msic); 1205 sc->rl_msi = 1; 1206 } else 1207 pci_release_msi(dev); 1208 } 1209 } 1210 1211 /* Allocate interrupt */ 1212 if (sc->rl_msi == 0) { 1213 rid = 0; 1214 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1215 RF_SHAREABLE | RF_ACTIVE); 1216 if (sc->rl_irq[0] == NULL) { 1217 device_printf(dev, "couldn't allocate IRQ resources\n"); 1218 error = ENXIO; 1219 goto fail; 1220 } 1221 } else { 1222 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1223 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1224 SYS_RES_IRQ, &rid, RF_ACTIVE); 1225 if (sc->rl_irq[i] == NULL) { 1226 device_printf(dev, 1227 "couldn't llocate IRQ resources for " 1228 "message %d\n", rid); 1229 error = ENXIO; 1230 goto fail; 1231 } 1232 } 1233 } 1234 1235 /* Reset the adapter. */ 1236 RL_LOCK(sc); 1237 re_reset(sc); 1238 RL_UNLOCK(sc); 1239 1240 hw_rev = re_hwrevs; 1241 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 1242 while (hw_rev->rl_desc != NULL) { 1243 if (hw_rev->rl_rev == hwrev) { 1244 sc->rl_type = hw_rev->rl_type; 1245 break; 1246 } 1247 hw_rev++; 1248 } 1249 1250 sc->rl_eewidth = RL_9356_ADDR_LEN; 1251 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1252 if (re_did != 0x8129) 1253 sc->rl_eewidth = RL_9346_ADDR_LEN; 1254 1255 /* 1256 * Get station address from the EEPROM. 1257 */ 1258 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1259 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1260 as[i] = le16toh(as[i]); 1261 bcopy(as, eaddr, sizeof(eaddr)); 1262 1263 if (sc->rl_type == RL_8169) { 1264 /* Set RX length mask */ 1265 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1266 sc->rl_txstart = RL_GTXSTART; 1267 } else { 1268 /* Set RX length mask */ 1269 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1270 sc->rl_txstart = RL_TXSTART; 1271 } 1272 1273 /* 1274 * Allocate the parent bus DMA tag appropriate for PCI. 1275 */ 1276 #define RL_NSEG_NEW 32 1277 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 1278 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1279 MAXBSIZE, RL_NSEG_NEW, BUS_SPACE_MAXSIZE_32BIT, 0, 1280 NULL, NULL, &sc->rl_parent_tag); 1281 if (error) 1282 goto fail; 1283 1284 error = re_allocmem(dev, sc); 1285 1286 if (error) 1287 goto fail; 1288 1289 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1290 if (ifp == NULL) { 1291 device_printf(dev, "can not if_alloc()\n"); 1292 error = ENOSPC; 1293 goto fail; 1294 } 1295 1296 /* Do MII setup */ 1297 if (mii_phy_probe(dev, &sc->rl_miibus, 1298 re_ifmedia_upd, re_ifmedia_sts)) { 1299 device_printf(dev, "MII without any phy!\n"); 1300 error = ENXIO; 1301 goto fail; 1302 } 1303 1304 /* Take PHY out of power down mode. */ 1305 if (sc->rl_type == RL_8169) { 1306 uint32_t rev; 1307 1308 rev = CSR_READ_4(sc, RL_TXCFG); 1309 /* HWVERID 0, 1 and 2 : bit26-30, bit23 */ 1310 rev &= 0x7c800000; 1311 if (rev != 0) { 1312 /* RTL8169S single chip */ 1313 switch (rev) { 1314 case RL_HWREV_8169_8110SB: 1315 case RL_HWREV_8169_8110SC: 1316 case RL_HWREV_8168_SPIN2: 1317 re_gmii_writereg(dev, 1, 0x1f, 0); 1318 re_gmii_writereg(dev, 1, 0x0e, 0); 1319 break; 1320 default: 1321 break; 1322 } 1323 } 1324 } 1325 1326 ifp->if_softc = sc; 1327 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1328 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1329 ifp->if_ioctl = re_ioctl; 1330 ifp->if_start = re_start; 1331 ifp->if_hwassist = RE_CSUM_FEATURES; 1332 ifp->if_capabilities = IFCAP_HWCSUM; 1333 ifp->if_capenable = ifp->if_capabilities; 1334 ifp->if_init = re_init; 1335 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1336 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1337 IFQ_SET_READY(&ifp->if_snd); 1338 1339 TASK_INIT(&sc->rl_txtask, 1, re_tx_task, ifp); 1340 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1341 1342 /* 1343 * Call MI attach routine. 1344 */ 1345 ether_ifattach(ifp, eaddr); 1346 1347 /* VLAN capability setup */ 1348 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1349 if (ifp->if_capabilities & IFCAP_HWCSUM) 1350 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1351 ifp->if_capenable = ifp->if_capabilities; 1352 #ifdef DEVICE_POLLING 1353 ifp->if_capabilities |= IFCAP_POLLING; 1354 #endif 1355 /* 1356 * Tell the upper layer(s) we support long frames. 1357 * Must appear after the call to ether_ifattach() because 1358 * ether_ifattach() sets ifi_hdrlen to the default value. 1359 */ 1360 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1361 1362 #ifdef RE_DIAG 1363 /* 1364 * Perform hardware diagnostic on the original RTL8169. 1365 * Some 32-bit cards were incorrectly wired and would 1366 * malfunction if plugged into a 64-bit slot. 1367 */ 1368 1369 if (hwrev == RL_HWREV_8169) { 1370 error = re_diag(sc); 1371 if (error) { 1372 device_printf(dev, 1373 "attach aborted due to hardware diag failure\n"); 1374 ether_ifdetach(ifp); 1375 goto fail; 1376 } 1377 } 1378 #endif 1379 1380 /* Hook interrupt last to avoid having to lock softc */ 1381 if (sc->rl_msi == 0) 1382 error = bus_setup_intr(dev, sc->rl_irq[0], 1383 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1384 &sc->rl_intrhand[0]); 1385 else { 1386 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1387 error = bus_setup_intr(dev, sc->rl_irq[i], 1388 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1389 &sc->rl_intrhand[i]); 1390 if (error != 0) 1391 break; 1392 } 1393 } 1394 if (error) { 1395 device_printf(dev, "couldn't set up irq\n"); 1396 ether_ifdetach(ifp); 1397 } 1398 1399 fail: 1400 1401 if (error) 1402 re_detach(dev); 1403 1404 return (error); 1405 } 1406 1407 /* 1408 * Shutdown hardware and free up resources. This can be called any 1409 * time after the mutex has been initialized. It is called in both 1410 * the error case in attach and the normal detach case so it needs 1411 * to be careful about only freeing resources that have actually been 1412 * allocated. 1413 */ 1414 static int 1415 re_detach(dev) 1416 device_t dev; 1417 { 1418 struct rl_softc *sc; 1419 struct ifnet *ifp; 1420 int i, rid; 1421 1422 sc = device_get_softc(dev); 1423 ifp = sc->rl_ifp; 1424 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1425 1426 #ifdef DEVICE_POLLING 1427 if (ifp->if_capenable & IFCAP_POLLING) 1428 ether_poll_deregister(ifp); 1429 #endif 1430 /* These should only be active if attach succeeded */ 1431 if (device_is_attached(dev)) { 1432 RL_LOCK(sc); 1433 #if 0 1434 sc->suspended = 1; 1435 #endif 1436 re_stop(sc); 1437 RL_UNLOCK(sc); 1438 callout_drain(&sc->rl_stat_callout); 1439 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1440 taskqueue_drain(taskqueue_fast, &sc->rl_txtask); 1441 /* 1442 * Force off the IFF_UP flag here, in case someone 1443 * still had a BPF descriptor attached to this 1444 * interface. If they do, ether_ifdetach() will cause 1445 * the BPF code to try and clear the promisc mode 1446 * flag, which will bubble down to re_ioctl(), 1447 * which will try to call re_init() again. This will 1448 * turn the NIC back on and restart the MII ticker, 1449 * which will panic the system when the kernel tries 1450 * to invoke the re_tick() function that isn't there 1451 * anymore. 1452 */ 1453 ifp->if_flags &= ~IFF_UP; 1454 ether_ifdetach(ifp); 1455 } 1456 if (sc->rl_miibus) 1457 device_delete_child(dev, sc->rl_miibus); 1458 bus_generic_detach(dev); 1459 1460 /* 1461 * The rest is resource deallocation, so we should already be 1462 * stopped here. 1463 */ 1464 1465 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1466 if (sc->rl_intrhand[i] != NULL) { 1467 bus_teardown_intr(dev, sc->rl_irq[i], 1468 sc->rl_intrhand[i]); 1469 sc->rl_intrhand[i] = NULL; 1470 } 1471 } 1472 if (ifp != NULL) 1473 if_free(ifp); 1474 if (sc->rl_msi == 0) { 1475 if (sc->rl_irq[0] != NULL) { 1476 bus_release_resource(dev, SYS_RES_IRQ, 0, 1477 sc->rl_irq[0]); 1478 sc->rl_irq[0] = NULL; 1479 } 1480 } else { 1481 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1482 if (sc->rl_irq[i] != NULL) { 1483 bus_release_resource(dev, SYS_RES_IRQ, rid, 1484 sc->rl_irq[i]); 1485 sc->rl_irq[i] = NULL; 1486 } 1487 } 1488 pci_release_msi(dev); 1489 } 1490 if (sc->rl_res) 1491 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1492 1493 /* Unload and free the RX DMA ring memory and map */ 1494 1495 if (sc->rl_ldata.rl_rx_list_tag) { 1496 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1497 sc->rl_ldata.rl_rx_list_map); 1498 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1499 sc->rl_ldata.rl_rx_list, 1500 sc->rl_ldata.rl_rx_list_map); 1501 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1502 } 1503 1504 /* Unload and free the TX DMA ring memory and map */ 1505 1506 if (sc->rl_ldata.rl_tx_list_tag) { 1507 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1508 sc->rl_ldata.rl_tx_list_map); 1509 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1510 sc->rl_ldata.rl_tx_list, 1511 sc->rl_ldata.rl_tx_list_map); 1512 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1513 } 1514 1515 /* Destroy all the RX and TX buffer maps */ 1516 1517 if (sc->rl_ldata.rl_mtag) { 1518 for (i = 0; i < RL_TX_DESC_CNT; i++) 1519 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1520 sc->rl_ldata.rl_tx_dmamap[i]); 1521 for (i = 0; i < RL_RX_DESC_CNT; i++) 1522 bus_dmamap_destroy(sc->rl_ldata.rl_mtag, 1523 sc->rl_ldata.rl_rx_dmamap[i]); 1524 bus_dma_tag_destroy(sc->rl_ldata.rl_mtag); 1525 } 1526 1527 /* Unload and free the stats buffer and map */ 1528 1529 if (sc->rl_ldata.rl_stag) { 1530 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1531 sc->rl_ldata.rl_rx_list_map); 1532 bus_dmamem_free(sc->rl_ldata.rl_stag, 1533 sc->rl_ldata.rl_stats, 1534 sc->rl_ldata.rl_smap); 1535 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1536 } 1537 1538 if (sc->rl_parent_tag) 1539 bus_dma_tag_destroy(sc->rl_parent_tag); 1540 1541 mtx_destroy(&sc->rl_mtx); 1542 1543 return (0); 1544 } 1545 1546 static int 1547 re_newbuf(sc, idx, m) 1548 struct rl_softc *sc; 1549 int idx; 1550 struct mbuf *m; 1551 { 1552 struct rl_dmaload_arg arg; 1553 struct mbuf *n = NULL; 1554 int error; 1555 1556 if (m == NULL) { 1557 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1558 if (n == NULL) 1559 return (ENOBUFS); 1560 m = n; 1561 } else 1562 m->m_data = m->m_ext.ext_buf; 1563 1564 m->m_len = m->m_pkthdr.len = MCLBYTES; 1565 #ifdef RE_FIXUP_RX 1566 /* 1567 * This is part of an evil trick to deal with non-x86 platforms. 1568 * The RealTek chip requires RX buffers to be aligned on 64-bit 1569 * boundaries, but that will hose non-x86 machines. To get around 1570 * this, we leave some empty space at the start of each buffer 1571 * and for non-x86 hosts, we copy the buffer back six bytes 1572 * to achieve word alignment. This is slightly more efficient 1573 * than allocating a new buffer, copying the contents, and 1574 * discarding the old buffer. 1575 */ 1576 m_adj(m, RE_ETHER_ALIGN); 1577 #endif 1578 arg.rl_idx = idx; 1579 arg.rl_maxsegs = 1; 1580 arg.rl_flags = 0; 1581 arg.rl_ring = sc->rl_ldata.rl_rx_list; 1582 1583 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, 1584 sc->rl_ldata.rl_rx_dmamap[idx], m, re_dma_map_desc, 1585 &arg, BUS_DMA_NOWAIT); 1586 if (error || arg.rl_maxsegs != 1) { 1587 if (n != NULL) 1588 m_freem(n); 1589 if (arg.rl_maxsegs == 0) 1590 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1591 sc->rl_ldata.rl_rx_dmamap[idx]); 1592 return (ENOMEM); 1593 } 1594 1595 sc->rl_ldata.rl_rx_list[idx].rl_cmdstat |= htole32(RL_RDESC_CMD_OWN); 1596 sc->rl_ldata.rl_rx_mbuf[idx] = m; 1597 1598 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1599 sc->rl_ldata.rl_rx_dmamap[idx], 1600 BUS_DMASYNC_PREREAD); 1601 1602 return (0); 1603 } 1604 1605 #ifdef RE_FIXUP_RX 1606 static __inline void 1607 re_fixup_rx(m) 1608 struct mbuf *m; 1609 { 1610 int i; 1611 uint16_t *src, *dst; 1612 1613 src = mtod(m, uint16_t *); 1614 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1615 1616 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1617 *dst++ = *src++; 1618 1619 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1620 1621 return; 1622 } 1623 #endif 1624 1625 static int 1626 re_tx_list_init(sc) 1627 struct rl_softc *sc; 1628 { 1629 1630 RL_LOCK_ASSERT(sc); 1631 1632 bzero ((char *)sc->rl_ldata.rl_tx_list, RL_TX_LIST_SZ); 1633 bzero ((char *)&sc->rl_ldata.rl_tx_mbuf, 1634 (RL_TX_DESC_CNT * sizeof(struct mbuf *))); 1635 1636 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1637 sc->rl_ldata.rl_tx_list_map, BUS_DMASYNC_PREWRITE); 1638 sc->rl_ldata.rl_tx_prodidx = 0; 1639 sc->rl_ldata.rl_tx_considx = 0; 1640 sc->rl_ldata.rl_tx_free = RL_TX_DESC_CNT; 1641 1642 return (0); 1643 } 1644 1645 static int 1646 re_rx_list_init(sc) 1647 struct rl_softc *sc; 1648 { 1649 int i; 1650 1651 bzero ((char *)sc->rl_ldata.rl_rx_list, RL_RX_LIST_SZ); 1652 bzero ((char *)&sc->rl_ldata.rl_rx_mbuf, 1653 (RL_RX_DESC_CNT * sizeof(struct mbuf *))); 1654 1655 for (i = 0; i < RL_RX_DESC_CNT; i++) { 1656 if (re_newbuf(sc, i, NULL) == ENOBUFS) 1657 return (ENOBUFS); 1658 } 1659 1660 /* Flush the RX descriptors */ 1661 1662 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1663 sc->rl_ldata.rl_rx_list_map, 1664 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1665 1666 sc->rl_ldata.rl_rx_prodidx = 0; 1667 sc->rl_head = sc->rl_tail = NULL; 1668 1669 return (0); 1670 } 1671 1672 /* 1673 * RX handler for C+ and 8169. For the gigE chips, we support 1674 * the reception of jumbo frames that have been fragmented 1675 * across multiple 2K mbuf cluster buffers. 1676 */ 1677 static int 1678 re_rxeof(sc) 1679 struct rl_softc *sc; 1680 { 1681 struct mbuf *m; 1682 struct ifnet *ifp; 1683 int i, total_len; 1684 struct rl_desc *cur_rx; 1685 u_int32_t rxstat, rxvlan; 1686 int maxpkt = 16; 1687 1688 RL_LOCK_ASSERT(sc); 1689 1690 ifp = sc->rl_ifp; 1691 i = sc->rl_ldata.rl_rx_prodidx; 1692 1693 /* Invalidate the descriptor memory */ 1694 1695 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1696 sc->rl_ldata.rl_rx_list_map, 1697 BUS_DMASYNC_POSTREAD); 1698 1699 while (!RL_OWN(&sc->rl_ldata.rl_rx_list[i]) && maxpkt) { 1700 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1701 m = sc->rl_ldata.rl_rx_mbuf[i]; 1702 total_len = RL_RXBYTES(cur_rx); 1703 rxstat = le32toh(cur_rx->rl_cmdstat); 1704 rxvlan = le32toh(cur_rx->rl_vlanctl); 1705 1706 /* Invalidate the RX mbuf and unload its map */ 1707 1708 bus_dmamap_sync(sc->rl_ldata.rl_mtag, 1709 sc->rl_ldata.rl_rx_dmamap[i], 1710 BUS_DMASYNC_POSTWRITE); 1711 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1712 sc->rl_ldata.rl_rx_dmamap[i]); 1713 1714 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1715 m->m_len = RE_RX_DESC_BUFLEN; 1716 if (sc->rl_head == NULL) 1717 sc->rl_head = sc->rl_tail = m; 1718 else { 1719 m->m_flags &= ~M_PKTHDR; 1720 sc->rl_tail->m_next = m; 1721 sc->rl_tail = m; 1722 } 1723 re_newbuf(sc, i, NULL); 1724 RL_DESC_INC(i); 1725 continue; 1726 } 1727 1728 /* 1729 * NOTE: for the 8139C+, the frame length field 1730 * is always 12 bits in size, but for the gigE chips, 1731 * it is 13 bits (since the max RX frame length is 16K). 1732 * Unfortunately, all 32 bits in the status word 1733 * were already used, so to make room for the extra 1734 * length bit, RealTek took out the 'frame alignment 1735 * error' bit and shifted the other status bits 1736 * over one slot. The OWN, EOR, FS and LS bits are 1737 * still in the same places. We have already extracted 1738 * the frame length and checked the OWN bit, so rather 1739 * than using an alternate bit mapping, we shift the 1740 * status bits one space to the right so we can evaluate 1741 * them using the 8169 status as though it was in the 1742 * same format as that of the 8139C+. 1743 */ 1744 if (sc->rl_type == RL_8169) 1745 rxstat >>= 1; 1746 1747 /* 1748 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 1749 * set, but if CRC is clear, it will still be a valid frame. 1750 */ 1751 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 && 1752 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) { 1753 ifp->if_ierrors++; 1754 /* 1755 * If this is part of a multi-fragment packet, 1756 * discard all the pieces. 1757 */ 1758 if (sc->rl_head != NULL) { 1759 m_freem(sc->rl_head); 1760 sc->rl_head = sc->rl_tail = NULL; 1761 } 1762 re_newbuf(sc, i, m); 1763 RL_DESC_INC(i); 1764 continue; 1765 } 1766 1767 /* 1768 * If allocating a replacement mbuf fails, 1769 * reload the current one. 1770 */ 1771 1772 if (re_newbuf(sc, i, NULL)) { 1773 ifp->if_ierrors++; 1774 if (sc->rl_head != NULL) { 1775 m_freem(sc->rl_head); 1776 sc->rl_head = sc->rl_tail = NULL; 1777 } 1778 re_newbuf(sc, i, m); 1779 RL_DESC_INC(i); 1780 continue; 1781 } 1782 1783 RL_DESC_INC(i); 1784 1785 if (sc->rl_head != NULL) { 1786 m->m_len = total_len % RE_RX_DESC_BUFLEN; 1787 if (m->m_len == 0) 1788 m->m_len = RE_RX_DESC_BUFLEN; 1789 /* 1790 * Special case: if there's 4 bytes or less 1791 * in this buffer, the mbuf can be discarded: 1792 * the last 4 bytes is the CRC, which we don't 1793 * care about anyway. 1794 */ 1795 if (m->m_len <= ETHER_CRC_LEN) { 1796 sc->rl_tail->m_len -= 1797 (ETHER_CRC_LEN - m->m_len); 1798 m_freem(m); 1799 } else { 1800 m->m_len -= ETHER_CRC_LEN; 1801 m->m_flags &= ~M_PKTHDR; 1802 sc->rl_tail->m_next = m; 1803 } 1804 m = sc->rl_head; 1805 sc->rl_head = sc->rl_tail = NULL; 1806 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1807 } else 1808 m->m_pkthdr.len = m->m_len = 1809 (total_len - ETHER_CRC_LEN); 1810 1811 #ifdef RE_FIXUP_RX 1812 re_fixup_rx(m); 1813 #endif 1814 ifp->if_ipackets++; 1815 m->m_pkthdr.rcvif = ifp; 1816 1817 /* Do RX checksumming if enabled */ 1818 1819 if (ifp->if_capenable & IFCAP_RXCSUM) { 1820 1821 /* Check IP header checksum */ 1822 if (rxstat & RL_RDESC_STAT_PROTOID) 1823 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1824 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1825 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1826 1827 /* Check TCP/UDP checksum */ 1828 if ((RL_TCPPKT(rxstat) && 1829 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1830 (RL_UDPPKT(rxstat) && 1831 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1832 m->m_pkthdr.csum_flags |= 1833 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1834 m->m_pkthdr.csum_data = 0xffff; 1835 } 1836 } 1837 maxpkt--; 1838 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 1839 m->m_pkthdr.ether_vtag = 1840 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)); 1841 m->m_flags |= M_VLANTAG; 1842 } 1843 RL_UNLOCK(sc); 1844 (*ifp->if_input)(ifp, m); 1845 RL_LOCK(sc); 1846 } 1847 1848 /* Flush the RX DMA ring */ 1849 1850 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1851 sc->rl_ldata.rl_rx_list_map, 1852 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1853 1854 sc->rl_ldata.rl_rx_prodidx = i; 1855 1856 if (maxpkt) 1857 return(EAGAIN); 1858 1859 return(0); 1860 } 1861 1862 static void 1863 re_txeof(sc) 1864 struct rl_softc *sc; 1865 { 1866 struct ifnet *ifp; 1867 u_int32_t txstat; 1868 int idx; 1869 1870 ifp = sc->rl_ifp; 1871 idx = sc->rl_ldata.rl_tx_considx; 1872 1873 /* Invalidate the TX descriptor list */ 1874 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1875 sc->rl_ldata.rl_tx_list_map, 1876 BUS_DMASYNC_POSTREAD); 1877 1878 while (sc->rl_ldata.rl_tx_free < RL_TX_DESC_CNT) { 1879 txstat = le32toh(sc->rl_ldata.rl_tx_list[idx].rl_cmdstat); 1880 if (txstat & RL_TDESC_CMD_OWN) 1881 break; 1882 1883 sc->rl_ldata.rl_tx_list[idx].rl_bufaddr_lo = 0; 1884 1885 /* 1886 * We only stash mbufs in the last descriptor 1887 * in a fragment chain, which also happens to 1888 * be the only place where the TX status bits 1889 * are valid. 1890 */ 1891 if (txstat & RL_TDESC_CMD_EOF) { 1892 m_freem(sc->rl_ldata.rl_tx_mbuf[idx]); 1893 sc->rl_ldata.rl_tx_mbuf[idx] = NULL; 1894 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 1895 sc->rl_ldata.rl_tx_dmamap[idx]); 1896 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 1897 RL_TDESC_STAT_COLCNT)) 1898 ifp->if_collisions++; 1899 if (txstat & RL_TDESC_STAT_TXERRSUM) 1900 ifp->if_oerrors++; 1901 else 1902 ifp->if_opackets++; 1903 } 1904 sc->rl_ldata.rl_tx_free++; 1905 RL_DESC_INC(idx); 1906 } 1907 sc->rl_ldata.rl_tx_considx = idx; 1908 1909 /* No changes made to the TX ring, so no flush needed */ 1910 1911 if (sc->rl_ldata.rl_tx_free > RL_TX_DESC_THLD) 1912 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1913 1914 if (sc->rl_ldata.rl_tx_free < RL_TX_DESC_CNT) { 1915 /* 1916 * Some chips will ignore a second TX request issued 1917 * while an existing transmission is in progress. If 1918 * the transmitter goes idle but there are still 1919 * packets waiting to be sent, we need to restart the 1920 * channel here to flush them out. This only seems to 1921 * be required with the PCIe devices. 1922 */ 1923 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 1924 1925 #ifdef RE_TX_MODERATION 1926 /* 1927 * If not all descriptors have been reaped yet, reload 1928 * the timer so that we will eventually get another 1929 * interrupt that will cause us to re-enter this routine. 1930 * This is done in case the transmitter has gone idle. 1931 */ 1932 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 1933 #endif 1934 } else 1935 sc->rl_watchdog_timer = 0; 1936 } 1937 1938 static void 1939 re_tick(xsc) 1940 void *xsc; 1941 { 1942 struct rl_softc *sc; 1943 struct mii_data *mii; 1944 struct ifnet *ifp; 1945 1946 sc = xsc; 1947 ifp = sc->rl_ifp; 1948 1949 RL_LOCK_ASSERT(sc); 1950 1951 re_watchdog(sc); 1952 1953 mii = device_get_softc(sc->rl_miibus); 1954 mii_tick(mii); 1955 if (sc->rl_link) { 1956 if (!(mii->mii_media_status & IFM_ACTIVE)) 1957 sc->rl_link = 0; 1958 } else { 1959 if (mii->mii_media_status & IFM_ACTIVE && 1960 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1961 sc->rl_link = 1; 1962 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1963 taskqueue_enqueue_fast(taskqueue_fast, 1964 &sc->rl_txtask); 1965 } 1966 } 1967 1968 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 1969 } 1970 1971 #ifdef DEVICE_POLLING 1972 static void 1973 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1974 { 1975 struct rl_softc *sc = ifp->if_softc; 1976 1977 RL_LOCK(sc); 1978 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1979 re_poll_locked(ifp, cmd, count); 1980 RL_UNLOCK(sc); 1981 } 1982 1983 static void 1984 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1985 { 1986 struct rl_softc *sc = ifp->if_softc; 1987 1988 RL_LOCK_ASSERT(sc); 1989 1990 sc->rxcycles = count; 1991 re_rxeof(sc); 1992 re_txeof(sc); 1993 1994 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1995 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 1996 1997 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1998 u_int16_t status; 1999 2000 status = CSR_READ_2(sc, RL_ISR); 2001 if (status == 0xffff) 2002 return; 2003 if (status) 2004 CSR_WRITE_2(sc, RL_ISR, status); 2005 2006 /* 2007 * XXX check behaviour on receiver stalls. 2008 */ 2009 2010 if (status & RL_ISR_SYSTEM_ERR) { 2011 re_reset(sc); 2012 re_init_locked(sc); 2013 } 2014 } 2015 } 2016 #endif /* DEVICE_POLLING */ 2017 2018 static int 2019 re_intr(arg) 2020 void *arg; 2021 { 2022 struct rl_softc *sc; 2023 uint16_t status; 2024 2025 sc = arg; 2026 2027 status = CSR_READ_2(sc, RL_ISR); 2028 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2029 return (FILTER_STRAY); 2030 CSR_WRITE_2(sc, RL_IMR, 0); 2031 2032 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2033 2034 return (FILTER_HANDLED); 2035 } 2036 2037 static void 2038 re_int_task(arg, npending) 2039 void *arg; 2040 int npending; 2041 { 2042 struct rl_softc *sc; 2043 struct ifnet *ifp; 2044 u_int16_t status; 2045 int rval = 0; 2046 2047 sc = arg; 2048 ifp = sc->rl_ifp; 2049 2050 RL_LOCK(sc); 2051 2052 status = CSR_READ_2(sc, RL_ISR); 2053 CSR_WRITE_2(sc, RL_ISR, status); 2054 2055 if (sc->suspended || !(ifp->if_flags & IFF_UP)) { 2056 RL_UNLOCK(sc); 2057 return; 2058 } 2059 2060 #ifdef DEVICE_POLLING 2061 if (ifp->if_capenable & IFCAP_POLLING) { 2062 RL_UNLOCK(sc); 2063 return; 2064 } 2065 #endif 2066 2067 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2068 rval = re_rxeof(sc); 2069 2070 #ifdef RE_TX_MODERATION 2071 if (status & (RL_ISR_TIMEOUT_EXPIRED| 2072 #else 2073 if (status & (RL_ISR_TX_OK| 2074 #endif 2075 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2076 re_txeof(sc); 2077 2078 if (status & RL_ISR_SYSTEM_ERR) { 2079 re_reset(sc); 2080 re_init_locked(sc); 2081 } 2082 2083 if (status & RL_ISR_LINKCHG) { 2084 callout_stop(&sc->rl_stat_callout); 2085 re_tick(sc); 2086 } 2087 2088 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2089 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2090 2091 RL_UNLOCK(sc); 2092 2093 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2094 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2095 return; 2096 } 2097 2098 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2099 2100 return; 2101 } 2102 2103 static int 2104 re_encap(sc, m_head, idx) 2105 struct rl_softc *sc; 2106 struct mbuf **m_head; 2107 int *idx; 2108 { 2109 struct mbuf *m_new = NULL; 2110 struct rl_dmaload_arg arg; 2111 bus_dmamap_t map; 2112 int error; 2113 2114 RL_LOCK_ASSERT(sc); 2115 2116 if (sc->rl_ldata.rl_tx_free <= RL_TX_DESC_THLD) 2117 return (EFBIG); 2118 2119 /* 2120 * Set up checksum offload. Note: checksum offload bits must 2121 * appear in all descriptors of a multi-descriptor transmit 2122 * attempt. This is according to testing done with an 8169 2123 * chip. This is a requirement. 2124 */ 2125 2126 arg.rl_flags = 0; 2127 2128 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) 2129 arg.rl_flags = RL_TDESC_CMD_LGSEND | 2130 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2131 RL_TDESC_CMD_MSSVAL_SHIFT); 2132 else { 2133 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) 2134 arg.rl_flags |= RL_TDESC_CMD_IPCSUM; 2135 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) 2136 arg.rl_flags |= RL_TDESC_CMD_TCPCSUM; 2137 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) 2138 arg.rl_flags |= RL_TDESC_CMD_UDPCSUM; 2139 } 2140 2141 arg.rl_idx = *idx; 2142 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 2143 if (arg.rl_maxsegs > RL_TX_DESC_THLD) 2144 arg.rl_maxsegs -= RL_TX_DESC_THLD; 2145 arg.rl_ring = sc->rl_ldata.rl_tx_list; 2146 2147 map = sc->rl_ldata.rl_tx_dmamap[*idx]; 2148 2149 /* 2150 * With some of the RealTek chips, using the checksum offload 2151 * support in conjunction with the autopadding feature results 2152 * in the transmission of corrupt frames. For example, if we 2153 * need to send a really small IP fragment that's less than 60 2154 * bytes in size, and IP header checksumming is enabled, the 2155 * resulting ethernet frame that appears on the wire will 2156 * have garbled payload. To work around this, if TX checksum 2157 * offload is enabled, we always manually pad short frames out 2158 * to the minimum ethernet frame size. We do this by pretending 2159 * the mbuf chain has too many fragments so the coalescing code 2160 * below can assemble the packet into a single buffer that's 2161 * padded out to the mininum frame size. 2162 * 2163 * Note: this appears unnecessary for TCP, and doing it for TCP 2164 * with PCIe adapters seems to result in bad checksums. 2165 */ 2166 2167 if (arg.rl_flags && !(arg.rl_flags & RL_TDESC_CMD_TCPCSUM) && 2168 (*m_head)->m_pkthdr.len < RL_MIN_FRAMELEN) 2169 error = EFBIG; 2170 else 2171 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 2172 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 2173 2174 if (error && error != EFBIG) { 2175 device_printf(sc->rl_dev, "can't map mbuf (error %d)\n", error); 2176 return (ENOBUFS); 2177 } 2178 2179 /* Too many segments to map, coalesce into a single mbuf */ 2180 2181 if (error || arg.rl_maxsegs == 0) { 2182 if (arg.rl_maxsegs == 0) 2183 bus_dmamap_unload(sc->rl_ldata.rl_mtag, map); 2184 m_new = m_defrag(*m_head, M_DONTWAIT); 2185 if (m_new == NULL) { 2186 m_freem(*m_head); 2187 *m_head = NULL; 2188 return (ENOBUFS); 2189 } 2190 *m_head = m_new; 2191 2192 /* 2193 * Manually pad short frames, and zero the pad space 2194 * to avoid leaking data. 2195 */ 2196 if (m_new->m_pkthdr.len < RL_MIN_FRAMELEN) { 2197 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, 2198 RL_MIN_FRAMELEN - m_new->m_pkthdr.len); 2199 m_new->m_pkthdr.len += RL_MIN_FRAMELEN - 2200 m_new->m_pkthdr.len; 2201 m_new->m_len = m_new->m_pkthdr.len; 2202 } 2203 2204 /* Note that we'll run over RL_TX_DESC_THLD here. */ 2205 arg.rl_maxsegs = sc->rl_ldata.rl_tx_free; 2206 error = bus_dmamap_load_mbuf(sc->rl_ldata.rl_mtag, map, 2207 *m_head, re_dma_map_desc, &arg, BUS_DMA_NOWAIT); 2208 if (error || arg.rl_maxsegs == 0) { 2209 device_printf(sc->rl_dev, 2210 "can't map defragmented mbuf (error %d)\n", error); 2211 m_freem(m_new); 2212 *m_head = NULL; 2213 if (arg.rl_maxsegs == 0) 2214 bus_dmamap_unload(sc->rl_ldata.rl_mtag, map); 2215 return (EFBIG); 2216 } 2217 } 2218 2219 /* 2220 * Insure that the map for this transmission 2221 * is placed at the array index of the last descriptor 2222 * in this chain. (Swap last and first dmamaps.) 2223 */ 2224 sc->rl_ldata.rl_tx_dmamap[*idx] = 2225 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx]; 2226 sc->rl_ldata.rl_tx_dmamap[arg.rl_idx] = map; 2227 2228 sc->rl_ldata.rl_tx_mbuf[arg.rl_idx] = *m_head; 2229 sc->rl_ldata.rl_tx_free -= arg.rl_maxsegs; 2230 2231 /* 2232 * Set up hardware VLAN tagging. Note: vlan tag info must 2233 * appear in the first descriptor of a multi-descriptor 2234 * transmission attempt. 2235 */ 2236 if ((*m_head)->m_flags & M_VLANTAG) 2237 sc->rl_ldata.rl_tx_list[*idx].rl_vlanctl = 2238 htole32(htons((*m_head)->m_pkthdr.ether_vtag) | 2239 RL_TDESC_VLANCTL_TAG); 2240 2241 /* Transfer ownership of packet to the chip. */ 2242 2243 sc->rl_ldata.rl_tx_list[arg.rl_idx].rl_cmdstat |= 2244 htole32(RL_TDESC_CMD_OWN); 2245 if (*idx != arg.rl_idx) 2246 sc->rl_ldata.rl_tx_list[*idx].rl_cmdstat |= 2247 htole32(RL_TDESC_CMD_OWN); 2248 2249 RL_DESC_INC(arg.rl_idx); 2250 *idx = arg.rl_idx; 2251 2252 return (0); 2253 } 2254 2255 static void 2256 re_tx_task(arg, npending) 2257 void *arg; 2258 int npending; 2259 { 2260 struct ifnet *ifp; 2261 2262 ifp = arg; 2263 re_start(ifp); 2264 2265 return; 2266 } 2267 2268 /* 2269 * Main transmit routine for C+ and gigE NICs. 2270 */ 2271 static void 2272 re_start(ifp) 2273 struct ifnet *ifp; 2274 { 2275 struct rl_softc *sc; 2276 struct mbuf *m_head = NULL; 2277 int idx, queued = 0; 2278 2279 sc = ifp->if_softc; 2280 2281 RL_LOCK(sc); 2282 2283 if (!sc->rl_link || ifp->if_drv_flags & IFF_DRV_OACTIVE) { 2284 RL_UNLOCK(sc); 2285 return; 2286 } 2287 2288 idx = sc->rl_ldata.rl_tx_prodidx; 2289 2290 while (sc->rl_ldata.rl_tx_mbuf[idx] == NULL) { 2291 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2292 if (m_head == NULL) 2293 break; 2294 2295 if (re_encap(sc, &m_head, &idx)) { 2296 if (m_head == NULL) 2297 break; 2298 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2299 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2300 break; 2301 } 2302 2303 /* 2304 * If there's a BPF listener, bounce a copy of this frame 2305 * to him. 2306 */ 2307 ETHER_BPF_MTAP(ifp, m_head); 2308 2309 queued++; 2310 } 2311 2312 if (queued == 0) { 2313 #ifdef RE_TX_MODERATION 2314 if (sc->rl_ldata.rl_tx_free != RL_TX_DESC_CNT) 2315 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2316 #endif 2317 RL_UNLOCK(sc); 2318 return; 2319 } 2320 2321 /* Flush the TX descriptors */ 2322 2323 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2324 sc->rl_ldata.rl_tx_list_map, 2325 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2326 2327 sc->rl_ldata.rl_tx_prodidx = idx; 2328 2329 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2330 2331 #ifdef RE_TX_MODERATION 2332 /* 2333 * Use the countdown timer for interrupt moderation. 2334 * 'TX done' interrupts are disabled. Instead, we reset the 2335 * countdown timer, which will begin counting until it hits 2336 * the value in the TIMERINT register, and then trigger an 2337 * interrupt. Each time we write to the TIMERCNT register, 2338 * the timer count is reset to 0. 2339 */ 2340 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2341 #endif 2342 2343 /* 2344 * Set a timeout in case the chip goes out to lunch. 2345 */ 2346 sc->rl_watchdog_timer = 5; 2347 2348 RL_UNLOCK(sc); 2349 2350 return; 2351 } 2352 2353 static void 2354 re_init(xsc) 2355 void *xsc; 2356 { 2357 struct rl_softc *sc = xsc; 2358 2359 RL_LOCK(sc); 2360 re_init_locked(sc); 2361 RL_UNLOCK(sc); 2362 } 2363 2364 static void 2365 re_init_locked(sc) 2366 struct rl_softc *sc; 2367 { 2368 struct ifnet *ifp = sc->rl_ifp; 2369 struct mii_data *mii; 2370 u_int32_t rxcfg = 0; 2371 union { 2372 uint32_t align_dummy; 2373 u_char eaddr[ETHER_ADDR_LEN]; 2374 } eaddr; 2375 2376 RL_LOCK_ASSERT(sc); 2377 2378 mii = device_get_softc(sc->rl_miibus); 2379 2380 /* 2381 * Cancel pending I/O and free all RX/TX buffers. 2382 */ 2383 re_stop(sc); 2384 2385 /* 2386 * Enable C+ RX and TX mode, as well as VLAN stripping and 2387 * RX checksum offload. We must configure the C+ register 2388 * before all others. 2389 */ 2390 CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB| 2391 RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW| 2392 RL_CPLUSCMD_VLANSTRIP|RL_CPLUSCMD_RXCSUM_ENB); 2393 2394 /* 2395 * Init our MAC address. Even though the chipset 2396 * documentation doesn't mention it, we need to enter "Config 2397 * register write enable" mode to modify the ID registers. 2398 */ 2399 /* Copy MAC address on stack to align. */ 2400 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 2401 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2402 CSR_WRITE_4(sc, RL_IDR0, 2403 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 2404 CSR_WRITE_4(sc, RL_IDR4, 2405 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 2406 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2407 2408 /* 2409 * For C+ mode, initialize the RX descriptors and mbufs. 2410 */ 2411 re_rx_list_init(sc); 2412 re_tx_list_init(sc); 2413 2414 /* 2415 * Load the addresses of the RX and TX lists into the chip. 2416 */ 2417 2418 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2419 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2420 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2421 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2422 2423 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2424 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2425 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2426 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2427 2428 /* 2429 * Enable transmit and receive. 2430 */ 2431 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2432 2433 /* 2434 * Set the initial TX and RX configuration. 2435 */ 2436 if (sc->rl_testmode) { 2437 if (sc->rl_type == RL_8169) 2438 CSR_WRITE_4(sc, RL_TXCFG, 2439 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2440 else 2441 CSR_WRITE_4(sc, RL_TXCFG, 2442 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2443 } else 2444 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2445 2446 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2447 2448 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 2449 2450 /* Set the individual bit to receive frames for this host only. */ 2451 rxcfg = CSR_READ_4(sc, RL_RXCFG); 2452 rxcfg |= RL_RXCFG_RX_INDIV; 2453 2454 /* If we want promiscuous mode, set the allframes bit. */ 2455 if (ifp->if_flags & IFF_PROMISC) 2456 rxcfg |= RL_RXCFG_RX_ALLPHYS; 2457 else 2458 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 2459 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2460 2461 /* 2462 * Set capture broadcast bit to capture broadcast frames. 2463 */ 2464 if (ifp->if_flags & IFF_BROADCAST) 2465 rxcfg |= RL_RXCFG_RX_BROAD; 2466 else 2467 rxcfg &= ~RL_RXCFG_RX_BROAD; 2468 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2469 2470 /* 2471 * Program the multicast filter, if necessary. 2472 */ 2473 re_setmulti(sc); 2474 2475 #ifdef DEVICE_POLLING 2476 /* 2477 * Disable interrupts if we are polling. 2478 */ 2479 if (ifp->if_capenable & IFCAP_POLLING) 2480 CSR_WRITE_2(sc, RL_IMR, 0); 2481 else /* otherwise ... */ 2482 #endif 2483 2484 /* 2485 * Enable interrupts. 2486 */ 2487 if (sc->rl_testmode) 2488 CSR_WRITE_2(sc, RL_IMR, 0); 2489 else 2490 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2491 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 2492 2493 /* Set initial TX threshold */ 2494 sc->rl_txthresh = RL_TX_THRESH_INIT; 2495 2496 /* Start RX/TX process. */ 2497 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2498 #ifdef notdef 2499 /* Enable receiver and transmitter. */ 2500 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2501 #endif 2502 2503 #ifdef RE_TX_MODERATION 2504 /* 2505 * Initialize the timer interrupt register so that 2506 * a timer interrupt will be generated once the timer 2507 * reaches a certain number of ticks. The timer is 2508 * reloaded on each transmit. This gives us TX interrupt 2509 * moderation, which dramatically improves TX frame rate. 2510 */ 2511 if (sc->rl_type == RL_8169) 2512 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2513 else 2514 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2515 #endif 2516 2517 /* 2518 * For 8169 gigE NICs, set the max allowed RX packet 2519 * size so we can receive jumbo frames. 2520 */ 2521 if (sc->rl_type == RL_8169) 2522 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2523 2524 if (sc->rl_testmode) 2525 return; 2526 2527 mii_mediachg(mii); 2528 2529 CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD); 2530 2531 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2532 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2533 2534 sc->rl_link = 0; 2535 sc->rl_watchdog_timer = 0; 2536 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2537 } 2538 2539 /* 2540 * Set media options. 2541 */ 2542 static int 2543 re_ifmedia_upd(ifp) 2544 struct ifnet *ifp; 2545 { 2546 struct rl_softc *sc; 2547 struct mii_data *mii; 2548 2549 sc = ifp->if_softc; 2550 mii = device_get_softc(sc->rl_miibus); 2551 RL_LOCK(sc); 2552 mii_mediachg(mii); 2553 RL_UNLOCK(sc); 2554 2555 return (0); 2556 } 2557 2558 /* 2559 * Report current media status. 2560 */ 2561 static void 2562 re_ifmedia_sts(ifp, ifmr) 2563 struct ifnet *ifp; 2564 struct ifmediareq *ifmr; 2565 { 2566 struct rl_softc *sc; 2567 struct mii_data *mii; 2568 2569 sc = ifp->if_softc; 2570 mii = device_get_softc(sc->rl_miibus); 2571 2572 RL_LOCK(sc); 2573 mii_pollstat(mii); 2574 RL_UNLOCK(sc); 2575 ifmr->ifm_active = mii->mii_media_active; 2576 ifmr->ifm_status = mii->mii_media_status; 2577 } 2578 2579 static int 2580 re_ioctl(ifp, command, data) 2581 struct ifnet *ifp; 2582 u_long command; 2583 caddr_t data; 2584 { 2585 struct rl_softc *sc = ifp->if_softc; 2586 struct ifreq *ifr = (struct ifreq *) data; 2587 struct mii_data *mii; 2588 int error = 0; 2589 2590 switch (command) { 2591 case SIOCSIFMTU: 2592 RL_LOCK(sc); 2593 if (ifr->ifr_mtu > RL_JUMBO_MTU) 2594 error = EINVAL; 2595 ifp->if_mtu = ifr->ifr_mtu; 2596 RL_UNLOCK(sc); 2597 break; 2598 case SIOCSIFFLAGS: 2599 RL_LOCK(sc); 2600 if ((ifp->if_flags & IFF_UP) != 0) { 2601 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2602 if (((ifp->if_flags ^ sc->rl_if_flags) 2603 & IFF_PROMISC) != 0) 2604 re_setmulti(sc); 2605 } else 2606 re_init_locked(sc); 2607 } else { 2608 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2609 re_stop(sc); 2610 } 2611 sc->rl_if_flags = ifp->if_flags; 2612 RL_UNLOCK(sc); 2613 break; 2614 case SIOCADDMULTI: 2615 case SIOCDELMULTI: 2616 RL_LOCK(sc); 2617 re_setmulti(sc); 2618 RL_UNLOCK(sc); 2619 break; 2620 case SIOCGIFMEDIA: 2621 case SIOCSIFMEDIA: 2622 mii = device_get_softc(sc->rl_miibus); 2623 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2624 break; 2625 case SIOCSIFCAP: 2626 { 2627 int mask, reinit; 2628 2629 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2630 reinit = 0; 2631 #ifdef DEVICE_POLLING 2632 if (mask & IFCAP_POLLING) { 2633 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2634 error = ether_poll_register(re_poll, ifp); 2635 if (error) 2636 return(error); 2637 RL_LOCK(sc); 2638 /* Disable interrupts */ 2639 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2640 ifp->if_capenable |= IFCAP_POLLING; 2641 RL_UNLOCK(sc); 2642 } else { 2643 error = ether_poll_deregister(ifp); 2644 /* Enable interrupts. */ 2645 RL_LOCK(sc); 2646 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2647 ifp->if_capenable &= ~IFCAP_POLLING; 2648 RL_UNLOCK(sc); 2649 } 2650 } 2651 #endif /* DEVICE_POLLING */ 2652 if (mask & IFCAP_HWCSUM) { 2653 ifp->if_capenable ^= IFCAP_HWCSUM; 2654 if (ifp->if_capenable & IFCAP_TXCSUM) 2655 ifp->if_hwassist |= RE_CSUM_FEATURES; 2656 else 2657 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 2658 reinit = 1; 2659 } 2660 if (mask & IFCAP_VLAN_HWTAGGING) { 2661 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2662 reinit = 1; 2663 } 2664 if (mask & IFCAP_TSO4) { 2665 ifp->if_capenable ^= IFCAP_TSO4; 2666 if ((IFCAP_TSO4 & ifp->if_capenable) && 2667 (IFCAP_TSO4 & ifp->if_capabilities)) 2668 ifp->if_hwassist |= CSUM_TSO; 2669 else 2670 ifp->if_hwassist &= ~CSUM_TSO; 2671 } 2672 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) 2673 re_init(sc); 2674 VLAN_CAPABILITIES(ifp); 2675 } 2676 break; 2677 default: 2678 error = ether_ioctl(ifp, command, data); 2679 break; 2680 } 2681 2682 return (error); 2683 } 2684 2685 static void 2686 re_watchdog(sc) 2687 struct rl_softc *sc; 2688 { 2689 2690 RL_LOCK_ASSERT(sc); 2691 2692 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 2693 return; 2694 2695 device_printf(sc->rl_dev, "watchdog timeout\n"); 2696 sc->rl_ifp->if_oerrors++; 2697 2698 re_txeof(sc); 2699 re_rxeof(sc); 2700 re_init_locked(sc); 2701 } 2702 2703 /* 2704 * Stop the adapter and free any mbufs allocated to the 2705 * RX and TX lists. 2706 */ 2707 static void 2708 re_stop(sc) 2709 struct rl_softc *sc; 2710 { 2711 register int i; 2712 struct ifnet *ifp; 2713 2714 RL_LOCK_ASSERT(sc); 2715 2716 ifp = sc->rl_ifp; 2717 2718 sc->rl_watchdog_timer = 0; 2719 callout_stop(&sc->rl_stat_callout); 2720 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2721 2722 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2723 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2724 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 2725 2726 if (sc->rl_head != NULL) { 2727 m_freem(sc->rl_head); 2728 sc->rl_head = sc->rl_tail = NULL; 2729 } 2730 2731 /* Free the TX list buffers. */ 2732 2733 for (i = 0; i < RL_TX_DESC_CNT; i++) { 2734 if (sc->rl_ldata.rl_tx_mbuf[i] != NULL) { 2735 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2736 sc->rl_ldata.rl_tx_dmamap[i]); 2737 m_freem(sc->rl_ldata.rl_tx_mbuf[i]); 2738 sc->rl_ldata.rl_tx_mbuf[i] = NULL; 2739 } 2740 } 2741 2742 /* Free the RX list buffers. */ 2743 2744 for (i = 0; i < RL_RX_DESC_CNT; i++) { 2745 if (sc->rl_ldata.rl_rx_mbuf[i] != NULL) { 2746 bus_dmamap_unload(sc->rl_ldata.rl_mtag, 2747 sc->rl_ldata.rl_rx_dmamap[i]); 2748 m_freem(sc->rl_ldata.rl_rx_mbuf[i]); 2749 sc->rl_ldata.rl_rx_mbuf[i] = NULL; 2750 } 2751 } 2752 } 2753 2754 /* 2755 * Device suspend routine. Stop the interface and save some PCI 2756 * settings in case the BIOS doesn't restore them properly on 2757 * resume. 2758 */ 2759 static int 2760 re_suspend(dev) 2761 device_t dev; 2762 { 2763 struct rl_softc *sc; 2764 2765 sc = device_get_softc(dev); 2766 2767 RL_LOCK(sc); 2768 re_stop(sc); 2769 sc->suspended = 1; 2770 RL_UNLOCK(sc); 2771 2772 return (0); 2773 } 2774 2775 /* 2776 * Device resume routine. Restore some PCI settings in case the BIOS 2777 * doesn't, re-enable busmastering, and restart the interface if 2778 * appropriate. 2779 */ 2780 static int 2781 re_resume(dev) 2782 device_t dev; 2783 { 2784 struct rl_softc *sc; 2785 struct ifnet *ifp; 2786 2787 sc = device_get_softc(dev); 2788 2789 RL_LOCK(sc); 2790 2791 ifp = sc->rl_ifp; 2792 2793 /* reinitialize interface if necessary */ 2794 if (ifp->if_flags & IFF_UP) 2795 re_init_locked(sc); 2796 2797 sc->suspended = 0; 2798 RL_UNLOCK(sc); 2799 2800 return (0); 2801 } 2802 2803 /* 2804 * Stop all chip I/O so that the kernel's probe routines don't 2805 * get confused by errant DMAs when rebooting. 2806 */ 2807 static void 2808 re_shutdown(dev) 2809 device_t dev; 2810 { 2811 struct rl_softc *sc; 2812 2813 sc = device_get_softc(dev); 2814 2815 RL_LOCK(sc); 2816 re_stop(sc); 2817 /* 2818 * Mark interface as down since otherwise we will panic if 2819 * interrupt comes in later on, which can happen in some 2820 * cases. 2821 */ 2822 sc->rl_ifp->if_flags &= ~IFF_UP; 2823 RL_UNLOCK(sc); 2824 } 2825