1 /*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44 /* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111 #ifdef HAVE_KERNEL_OPTION_HEADERS 112 #include "opt_device_polling.h" 113 #endif 114 115 #include <sys/param.h> 116 #include <sys/endian.h> 117 #include <sys/systm.h> 118 #include <sys/sockio.h> 119 #include <sys/mbuf.h> 120 #include <sys/malloc.h> 121 #include <sys/module.h> 122 #include <sys/kernel.h> 123 #include <sys/socket.h> 124 #include <sys/lock.h> 125 #include <sys/mutex.h> 126 #include <sys/taskqueue.h> 127 128 #include <net/if.h> 129 #include <net/if_arp.h> 130 #include <net/ethernet.h> 131 #include <net/if_dl.h> 132 #include <net/if_media.h> 133 #include <net/if_types.h> 134 #include <net/if_vlan_var.h> 135 136 #include <net/bpf.h> 137 138 #include <machine/bus.h> 139 #include <machine/resource.h> 140 #include <sys/bus.h> 141 #include <sys/rman.h> 142 143 #include <dev/mii/mii.h> 144 #include <dev/mii/miivar.h> 145 146 #include <dev/pci/pcireg.h> 147 #include <dev/pci/pcivar.h> 148 149 #include <pci/if_rlreg.h> 150 151 MODULE_DEPEND(re, pci, 1, 1, 1); 152 MODULE_DEPEND(re, ether, 1, 1, 1); 153 MODULE_DEPEND(re, miibus, 1, 1, 1); 154 155 /* "device miibus" required. See GENERIC if you get errors here. */ 156 #include "miibus_if.h" 157 158 /* Tunables. */ 159 static int msi_disable = 0; 160 TUNABLE_INT("hw.re.msi_disable", &msi_disable); 161 static int prefer_iomap = 0; 162 TUNABLE_INT("hw.re.prefer_iomap", &prefer_iomap); 163 164 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 165 166 /* 167 * Various supported device vendors/types and their names. 168 */ 169 static struct rl_type re_devs[] = { 170 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0, 171 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 172 { RT_VENDORID, RT_DEVICEID_8139, 0, 173 "RealTek 8139C+ 10/100BaseTX" }, 174 { RT_VENDORID, RT_DEVICEID_8101E, 0, 175 "RealTek 8101E/8102E/8102EL/8103E PCIe 10/100baseTX" }, 176 { RT_VENDORID, RT_DEVICEID_8168, 0, 177 "RealTek 8168/8168B/8168C/8168CP/8168D/8168DP/" 178 "8111B/8111C/8111CP/8111DP PCIe Gigabit Ethernet" }, 179 { RT_VENDORID, RT_DEVICEID_8169, 0, 180 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" }, 181 { RT_VENDORID, RT_DEVICEID_8169SC, 0, 182 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 183 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0, 184 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 185 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0, 186 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 187 { USR_VENDORID, USR_DEVICEID_997902, 0, 188 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 189 }; 190 191 static struct rl_hwrev re_hwrevs[] = { 192 { RL_HWREV_8139, RL_8139, "" }, 193 { RL_HWREV_8139A, RL_8139, "A" }, 194 { RL_HWREV_8139AG, RL_8139, "A-G" }, 195 { RL_HWREV_8139B, RL_8139, "B" }, 196 { RL_HWREV_8130, RL_8139, "8130" }, 197 { RL_HWREV_8139C, RL_8139, "C" }, 198 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 199 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 200 { RL_HWREV_8168_SPIN1, RL_8169, "8168"}, 201 { RL_HWREV_8169, RL_8169, "8169"}, 202 { RL_HWREV_8169S, RL_8169, "8169S"}, 203 { RL_HWREV_8110S, RL_8169, "8110S"}, 204 { RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB"}, 205 { RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC"}, 206 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL"}, 207 { RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC"}, 208 { RL_HWREV_8100, RL_8139, "8100"}, 209 { RL_HWREV_8101, RL_8139, "8101"}, 210 { RL_HWREV_8100E, RL_8169, "8100E"}, 211 { RL_HWREV_8101E, RL_8169, "8101E"}, 212 { RL_HWREV_8102E, RL_8169, "8102E"}, 213 { RL_HWREV_8102EL, RL_8169, "8102EL"}, 214 { RL_HWREV_8102EL_SPIN1, RL_8169, "8102EL"}, 215 { RL_HWREV_8103E, RL_8169, "8103E"}, 216 { RL_HWREV_8168_SPIN2, RL_8169, "8168"}, 217 { RL_HWREV_8168_SPIN3, RL_8169, "8168"}, 218 { RL_HWREV_8168C, RL_8169, "8168C/8111C"}, 219 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C"}, 220 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP"}, 221 { RL_HWREV_8168D, RL_8169, "8168D/8111D"}, 222 { RL_HWREV_8168DP, RL_8169, "8168DP/8111DP"}, 223 { 0, 0, NULL } 224 }; 225 226 static int re_probe (device_t); 227 static int re_attach (device_t); 228 static int re_detach (device_t); 229 230 static int re_encap (struct rl_softc *, struct mbuf **); 231 232 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 233 static int re_allocmem (device_t, struct rl_softc *); 234 static __inline void re_discard_rxbuf 235 (struct rl_softc *, int); 236 static int re_newbuf (struct rl_softc *, int); 237 static int re_rx_list_init (struct rl_softc *); 238 static int re_tx_list_init (struct rl_softc *); 239 #ifdef RE_FIXUP_RX 240 static __inline void re_fixup_rx 241 (struct mbuf *); 242 #endif 243 static int re_rxeof (struct rl_softc *, int *); 244 static void re_txeof (struct rl_softc *); 245 #ifdef DEVICE_POLLING 246 static int re_poll (struct ifnet *, enum poll_cmd, int); 247 static int re_poll_locked (struct ifnet *, enum poll_cmd, int); 248 #endif 249 static int re_intr (void *); 250 static void re_tick (void *); 251 static void re_tx_task (void *, int); 252 static void re_int_task (void *, int); 253 static void re_start (struct ifnet *); 254 static int re_ioctl (struct ifnet *, u_long, caddr_t); 255 static void re_init (void *); 256 static void re_init_locked (struct rl_softc *); 257 static void re_stop (struct rl_softc *); 258 static void re_watchdog (struct rl_softc *); 259 static int re_suspend (device_t); 260 static int re_resume (device_t); 261 static int re_shutdown (device_t); 262 static int re_ifmedia_upd (struct ifnet *); 263 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 264 265 static void re_eeprom_putbyte (struct rl_softc *, int); 266 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 267 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 268 static int re_gmii_readreg (device_t, int, int); 269 static int re_gmii_writereg (device_t, int, int, int); 270 271 static int re_miibus_readreg (device_t, int, int); 272 static int re_miibus_writereg (device_t, int, int, int); 273 static void re_miibus_statchg (device_t); 274 275 static void re_set_rxmode (struct rl_softc *); 276 static void re_reset (struct rl_softc *); 277 static void re_setwol (struct rl_softc *); 278 static void re_clrwol (struct rl_softc *); 279 280 #ifdef RE_DIAG 281 static int re_diag (struct rl_softc *); 282 #endif 283 284 static device_method_t re_methods[] = { 285 /* Device interface */ 286 DEVMETHOD(device_probe, re_probe), 287 DEVMETHOD(device_attach, re_attach), 288 DEVMETHOD(device_detach, re_detach), 289 DEVMETHOD(device_suspend, re_suspend), 290 DEVMETHOD(device_resume, re_resume), 291 DEVMETHOD(device_shutdown, re_shutdown), 292 293 /* bus interface */ 294 DEVMETHOD(bus_print_child, bus_generic_print_child), 295 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 296 297 /* MII interface */ 298 DEVMETHOD(miibus_readreg, re_miibus_readreg), 299 DEVMETHOD(miibus_writereg, re_miibus_writereg), 300 DEVMETHOD(miibus_statchg, re_miibus_statchg), 301 302 { 0, 0 } 303 }; 304 305 static driver_t re_driver = { 306 "re", 307 re_methods, 308 sizeof(struct rl_softc) 309 }; 310 311 static devclass_t re_devclass; 312 313 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 314 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 315 316 #define EE_SET(x) \ 317 CSR_WRITE_1(sc, RL_EECMD, \ 318 CSR_READ_1(sc, RL_EECMD) | x) 319 320 #define EE_CLR(x) \ 321 CSR_WRITE_1(sc, RL_EECMD, \ 322 CSR_READ_1(sc, RL_EECMD) & ~x) 323 324 /* 325 * Send a read command and address to the EEPROM, check for ACK. 326 */ 327 static void 328 re_eeprom_putbyte(struct rl_softc *sc, int addr) 329 { 330 int d, i; 331 332 d = addr | (RL_9346_READ << sc->rl_eewidth); 333 334 /* 335 * Feed in each bit and strobe the clock. 336 */ 337 338 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 339 if (d & i) { 340 EE_SET(RL_EE_DATAIN); 341 } else { 342 EE_CLR(RL_EE_DATAIN); 343 } 344 DELAY(100); 345 EE_SET(RL_EE_CLK); 346 DELAY(150); 347 EE_CLR(RL_EE_CLK); 348 DELAY(100); 349 } 350 } 351 352 /* 353 * Read a word of data stored in the EEPROM at address 'addr.' 354 */ 355 static void 356 re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest) 357 { 358 int i; 359 u_int16_t word = 0; 360 361 /* 362 * Send address of word we want to read. 363 */ 364 re_eeprom_putbyte(sc, addr); 365 366 /* 367 * Start reading bits from EEPROM. 368 */ 369 for (i = 0x8000; i; i >>= 1) { 370 EE_SET(RL_EE_CLK); 371 DELAY(100); 372 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 373 word |= i; 374 EE_CLR(RL_EE_CLK); 375 DELAY(100); 376 } 377 378 *dest = word; 379 } 380 381 /* 382 * Read a sequence of words from the EEPROM. 383 */ 384 static void 385 re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt) 386 { 387 int i; 388 u_int16_t word = 0, *ptr; 389 390 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 391 392 DELAY(100); 393 394 for (i = 0; i < cnt; i++) { 395 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 396 re_eeprom_getword(sc, off + i, &word); 397 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 398 ptr = (u_int16_t *)(dest + (i * 2)); 399 *ptr = word; 400 } 401 402 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 403 } 404 405 static int 406 re_gmii_readreg(device_t dev, int phy, int reg) 407 { 408 struct rl_softc *sc; 409 u_int32_t rval; 410 int i; 411 412 if (phy != 1) 413 return (0); 414 415 sc = device_get_softc(dev); 416 417 /* Let the rgephy driver read the GMEDIASTAT register */ 418 419 if (reg == RL_GMEDIASTAT) { 420 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 421 return (rval); 422 } 423 424 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 425 DELAY(1000); 426 427 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 428 rval = CSR_READ_4(sc, RL_PHYAR); 429 if (rval & RL_PHYAR_BUSY) 430 break; 431 DELAY(100); 432 } 433 434 if (i == RL_PHY_TIMEOUT) { 435 device_printf(sc->rl_dev, "PHY read failed\n"); 436 return (0); 437 } 438 439 return (rval & RL_PHYAR_PHYDATA); 440 } 441 442 static int 443 re_gmii_writereg(device_t dev, int phy, int reg, int data) 444 { 445 struct rl_softc *sc; 446 u_int32_t rval; 447 int i; 448 449 sc = device_get_softc(dev); 450 451 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 452 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 453 DELAY(1000); 454 455 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 456 rval = CSR_READ_4(sc, RL_PHYAR); 457 if (!(rval & RL_PHYAR_BUSY)) 458 break; 459 DELAY(100); 460 } 461 462 if (i == RL_PHY_TIMEOUT) { 463 device_printf(sc->rl_dev, "PHY write failed\n"); 464 return (0); 465 } 466 467 return (0); 468 } 469 470 static int 471 re_miibus_readreg(device_t dev, int phy, int reg) 472 { 473 struct rl_softc *sc; 474 u_int16_t rval = 0; 475 u_int16_t re8139_reg = 0; 476 477 sc = device_get_softc(dev); 478 479 if (sc->rl_type == RL_8169) { 480 rval = re_gmii_readreg(dev, phy, reg); 481 return (rval); 482 } 483 484 /* Pretend the internal PHY is only at address 0 */ 485 if (phy) { 486 return (0); 487 } 488 switch (reg) { 489 case MII_BMCR: 490 re8139_reg = RL_BMCR; 491 break; 492 case MII_BMSR: 493 re8139_reg = RL_BMSR; 494 break; 495 case MII_ANAR: 496 re8139_reg = RL_ANAR; 497 break; 498 case MII_ANER: 499 re8139_reg = RL_ANER; 500 break; 501 case MII_ANLPAR: 502 re8139_reg = RL_LPAR; 503 break; 504 case MII_PHYIDR1: 505 case MII_PHYIDR2: 506 return (0); 507 /* 508 * Allow the rlphy driver to read the media status 509 * register. If we have a link partner which does not 510 * support NWAY, this is the register which will tell 511 * us the results of parallel detection. 512 */ 513 case RL_MEDIASTAT: 514 rval = CSR_READ_1(sc, RL_MEDIASTAT); 515 return (rval); 516 default: 517 device_printf(sc->rl_dev, "bad phy register\n"); 518 return (0); 519 } 520 rval = CSR_READ_2(sc, re8139_reg); 521 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 522 /* 8139C+ has different bit layout. */ 523 rval &= ~(BMCR_LOOP | BMCR_ISO); 524 } 525 return (rval); 526 } 527 528 static int 529 re_miibus_writereg(device_t dev, int phy, int reg, int data) 530 { 531 struct rl_softc *sc; 532 u_int16_t re8139_reg = 0; 533 int rval = 0; 534 535 sc = device_get_softc(dev); 536 537 if (sc->rl_type == RL_8169) { 538 rval = re_gmii_writereg(dev, phy, reg, data); 539 return (rval); 540 } 541 542 /* Pretend the internal PHY is only at address 0 */ 543 if (phy) 544 return (0); 545 546 switch (reg) { 547 case MII_BMCR: 548 re8139_reg = RL_BMCR; 549 if (sc->rl_type == RL_8139CPLUS) { 550 /* 8139C+ has different bit layout. */ 551 data &= ~(BMCR_LOOP | BMCR_ISO); 552 } 553 break; 554 case MII_BMSR: 555 re8139_reg = RL_BMSR; 556 break; 557 case MII_ANAR: 558 re8139_reg = RL_ANAR; 559 break; 560 case MII_ANER: 561 re8139_reg = RL_ANER; 562 break; 563 case MII_ANLPAR: 564 re8139_reg = RL_LPAR; 565 break; 566 case MII_PHYIDR1: 567 case MII_PHYIDR2: 568 return (0); 569 break; 570 default: 571 device_printf(sc->rl_dev, "bad phy register\n"); 572 return (0); 573 } 574 CSR_WRITE_2(sc, re8139_reg, data); 575 return (0); 576 } 577 578 static void 579 re_miibus_statchg(device_t dev) 580 { 581 struct rl_softc *sc; 582 struct ifnet *ifp; 583 struct mii_data *mii; 584 585 sc = device_get_softc(dev); 586 mii = device_get_softc(sc->rl_miibus); 587 ifp = sc->rl_ifp; 588 if (mii == NULL || ifp == NULL || 589 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 590 return; 591 592 sc->rl_flags &= ~RL_FLAG_LINK; 593 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 594 (IFM_ACTIVE | IFM_AVALID)) { 595 switch (IFM_SUBTYPE(mii->mii_media_active)) { 596 case IFM_10_T: 597 case IFM_100_TX: 598 sc->rl_flags |= RL_FLAG_LINK; 599 break; 600 case IFM_1000_T: 601 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0) 602 break; 603 sc->rl_flags |= RL_FLAG_LINK; 604 break; 605 default: 606 break; 607 } 608 } 609 /* 610 * RealTek controllers does not provide any interface to 611 * Tx/Rx MACs for resolved speed, duplex and flow-control 612 * parameters. 613 */ 614 } 615 616 /* 617 * Set the RX configuration and 64-bit multicast hash filter. 618 */ 619 static void 620 re_set_rxmode(struct rl_softc *sc) 621 { 622 struct ifnet *ifp; 623 struct ifmultiaddr *ifma; 624 uint32_t hashes[2] = { 0, 0 }; 625 uint32_t h, rxfilt; 626 627 RL_LOCK_ASSERT(sc); 628 629 ifp = sc->rl_ifp; 630 631 rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD; 632 633 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 634 if (ifp->if_flags & IFF_PROMISC) 635 rxfilt |= RL_RXCFG_RX_ALLPHYS; 636 /* 637 * Unlike other hardwares, we have to explicitly set 638 * RL_RXCFG_RX_MULTI to receive multicast frames in 639 * promiscuous mode. 640 */ 641 rxfilt |= RL_RXCFG_RX_MULTI; 642 hashes[0] = hashes[1] = 0xffffffff; 643 goto done; 644 } 645 646 if_maddr_rlock(ifp); 647 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 648 if (ifma->ifma_addr->sa_family != AF_LINK) 649 continue; 650 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 651 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 652 if (h < 32) 653 hashes[0] |= (1 << h); 654 else 655 hashes[1] |= (1 << (h - 32)); 656 } 657 if_maddr_runlock(ifp); 658 659 if (hashes[0] != 0 || hashes[1] != 0) { 660 /* 661 * For some unfathomable reason, RealTek decided to 662 * reverse the order of the multicast hash registers 663 * in the PCI Express parts. This means we have to 664 * write the hash pattern in reverse order for those 665 * devices. 666 */ 667 if ((sc->rl_flags & RL_FLAG_PCIE) != 0) { 668 h = bswap32(hashes[0]); 669 hashes[0] = bswap32(hashes[1]); 670 hashes[1] = h; 671 } 672 rxfilt |= RL_RXCFG_RX_MULTI; 673 } 674 675 done: 676 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 677 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 678 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 679 } 680 681 static void 682 re_reset(struct rl_softc *sc) 683 { 684 int i; 685 686 RL_LOCK_ASSERT(sc); 687 688 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 689 690 for (i = 0; i < RL_TIMEOUT; i++) { 691 DELAY(10); 692 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 693 break; 694 } 695 if (i == RL_TIMEOUT) 696 device_printf(sc->rl_dev, "reset never completed!\n"); 697 698 if ((sc->rl_flags & RL_FLAG_MACRESET) != 0) 699 CSR_WRITE_1(sc, 0x82, 1); 700 if (sc->rl_hwrev == RL_HWREV_8169S) 701 re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0); 702 } 703 704 #ifdef RE_DIAG 705 706 /* 707 * The following routine is designed to test for a defect on some 708 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 709 * lines connected to the bus, however for a 32-bit only card, they 710 * should be pulled high. The result of this defect is that the 711 * NIC will not work right if you plug it into a 64-bit slot: DMA 712 * operations will be done with 64-bit transfers, which will fail 713 * because the 64-bit data lines aren't connected. 714 * 715 * There's no way to work around this (short of talking a soldering 716 * iron to the board), however we can detect it. The method we use 717 * here is to put the NIC into digital loopback mode, set the receiver 718 * to promiscuous mode, and then try to send a frame. We then compare 719 * the frame data we sent to what was received. If the data matches, 720 * then the NIC is working correctly, otherwise we know the user has 721 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 722 * slot. In the latter case, there's no way the NIC can work correctly, 723 * so we print out a message on the console and abort the device attach. 724 */ 725 726 static int 727 re_diag(struct rl_softc *sc) 728 { 729 struct ifnet *ifp = sc->rl_ifp; 730 struct mbuf *m0; 731 struct ether_header *eh; 732 struct rl_desc *cur_rx; 733 u_int16_t status; 734 u_int32_t rxstat; 735 int total_len, i, error = 0, phyaddr; 736 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 737 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 738 739 /* Allocate a single mbuf */ 740 MGETHDR(m0, M_DONTWAIT, MT_DATA); 741 if (m0 == NULL) 742 return (ENOBUFS); 743 744 RL_LOCK(sc); 745 746 /* 747 * Initialize the NIC in test mode. This sets the chip up 748 * so that it can send and receive frames, but performs the 749 * following special functions: 750 * - Puts receiver in promiscuous mode 751 * - Enables digital loopback mode 752 * - Leaves interrupts turned off 753 */ 754 755 ifp->if_flags |= IFF_PROMISC; 756 sc->rl_testmode = 1; 757 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 758 re_init_locked(sc); 759 sc->rl_flags |= RL_FLAG_LINK; 760 if (sc->rl_type == RL_8169) 761 phyaddr = 1; 762 else 763 phyaddr = 0; 764 765 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 766 for (i = 0; i < RL_TIMEOUT; i++) { 767 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 768 if (!(status & BMCR_RESET)) 769 break; 770 } 771 772 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 773 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 774 775 DELAY(100000); 776 777 /* Put some data in the mbuf */ 778 779 eh = mtod(m0, struct ether_header *); 780 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 781 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 782 eh->ether_type = htons(ETHERTYPE_IP); 783 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 784 785 /* 786 * Queue the packet, start transmission. 787 * Note: IF_HANDOFF() ultimately calls re_start() for us. 788 */ 789 790 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 791 RL_UNLOCK(sc); 792 /* XXX: re_diag must not be called when in ALTQ mode */ 793 IF_HANDOFF(&ifp->if_snd, m0, ifp); 794 RL_LOCK(sc); 795 m0 = NULL; 796 797 /* Wait for it to propagate through the chip */ 798 799 DELAY(100000); 800 for (i = 0; i < RL_TIMEOUT; i++) { 801 status = CSR_READ_2(sc, RL_ISR); 802 CSR_WRITE_2(sc, RL_ISR, status); 803 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 804 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 805 break; 806 DELAY(10); 807 } 808 809 if (i == RL_TIMEOUT) { 810 device_printf(sc->rl_dev, 811 "diagnostic failed, failed to receive packet in" 812 " loopback mode\n"); 813 error = EIO; 814 goto done; 815 } 816 817 /* 818 * The packet should have been dumped into the first 819 * entry in the RX DMA ring. Grab it from there. 820 */ 821 822 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 823 sc->rl_ldata.rl_rx_list_map, 824 BUS_DMASYNC_POSTREAD); 825 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 826 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 827 BUS_DMASYNC_POSTREAD); 828 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 829 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 830 831 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 832 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 833 eh = mtod(m0, struct ether_header *); 834 835 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 836 total_len = RL_RXBYTES(cur_rx); 837 rxstat = le32toh(cur_rx->rl_cmdstat); 838 839 if (total_len != ETHER_MIN_LEN) { 840 device_printf(sc->rl_dev, 841 "diagnostic failed, received short packet\n"); 842 error = EIO; 843 goto done; 844 } 845 846 /* Test that the received packet data matches what we sent. */ 847 848 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 849 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 850 ntohs(eh->ether_type) != ETHERTYPE_IP) { 851 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 852 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 853 dst, ":", src, ":", ETHERTYPE_IP); 854 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 855 eh->ether_dhost, ":", eh->ether_shost, ":", 856 ntohs(eh->ether_type)); 857 device_printf(sc->rl_dev, "You may have a defective 32-bit " 858 "NIC plugged into a 64-bit PCI slot.\n"); 859 device_printf(sc->rl_dev, "Please re-install the NIC in a " 860 "32-bit slot for proper operation.\n"); 861 device_printf(sc->rl_dev, "Read the re(4) man page for more " 862 "details.\n"); 863 error = EIO; 864 } 865 866 done: 867 /* Turn interface off, release resources */ 868 869 sc->rl_testmode = 0; 870 sc->rl_flags &= ~RL_FLAG_LINK; 871 ifp->if_flags &= ~IFF_PROMISC; 872 re_stop(sc); 873 if (m0 != NULL) 874 m_freem(m0); 875 876 RL_UNLOCK(sc); 877 878 return (error); 879 } 880 881 #endif 882 883 /* 884 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 885 * IDs against our list and return a device name if we find a match. 886 */ 887 static int 888 re_probe(device_t dev) 889 { 890 struct rl_type *t; 891 uint16_t devid, vendor; 892 uint16_t revid, sdevid; 893 int i; 894 895 vendor = pci_get_vendor(dev); 896 devid = pci_get_device(dev); 897 revid = pci_get_revid(dev); 898 sdevid = pci_get_subdevice(dev); 899 900 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 901 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 902 /* 903 * Only attach to rev. 3 of the Linksys EG1032 adapter. 904 * Rev. 2 is supported by sk(4). 905 */ 906 return (ENXIO); 907 } 908 } 909 910 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 911 if (revid != 0x20) { 912 /* 8139, let rl(4) take care of this device. */ 913 return (ENXIO); 914 } 915 } 916 917 t = re_devs; 918 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) { 919 if (vendor == t->rl_vid && devid == t->rl_did) { 920 device_set_desc(dev, t->rl_name); 921 return (BUS_PROBE_DEFAULT); 922 } 923 } 924 925 return (ENXIO); 926 } 927 928 /* 929 * Map a single buffer address. 930 */ 931 932 static void 933 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 934 { 935 bus_addr_t *addr; 936 937 if (error) 938 return; 939 940 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 941 addr = arg; 942 *addr = segs->ds_addr; 943 } 944 945 static int 946 re_allocmem(device_t dev, struct rl_softc *sc) 947 { 948 bus_size_t rx_list_size, tx_list_size; 949 int error; 950 int i; 951 952 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 953 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 954 955 /* 956 * Allocate the parent bus DMA tag appropriate for PCI. 957 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD 958 * register should be set. However some RealTek chips are known 959 * to be buggy on DAC handling, therefore disable DAC by limiting 960 * DMA address space to 32bit. PCIe variants of RealTek chips 961 * may not have the limitation but I took safer path. 962 */ 963 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 964 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 965 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 966 NULL, NULL, &sc->rl_parent_tag); 967 if (error) { 968 device_printf(dev, "could not allocate parent DMA tag\n"); 969 return (error); 970 } 971 972 /* 973 * Allocate map for TX mbufs. 974 */ 975 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 976 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 977 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 978 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 979 if (error) { 980 device_printf(dev, "could not allocate TX DMA tag\n"); 981 return (error); 982 } 983 984 /* 985 * Allocate map for RX mbufs. 986 */ 987 988 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 989 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 990 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 991 if (error) { 992 device_printf(dev, "could not allocate RX DMA tag\n"); 993 return (error); 994 } 995 996 /* 997 * Allocate map for TX descriptor list. 998 */ 999 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1000 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1001 NULL, tx_list_size, 1, tx_list_size, 0, 1002 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1003 if (error) { 1004 device_printf(dev, "could not allocate TX DMA ring tag\n"); 1005 return (error); 1006 } 1007 1008 /* Allocate DMA'able memory for the TX ring */ 1009 1010 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1011 (void **)&sc->rl_ldata.rl_tx_list, 1012 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1013 &sc->rl_ldata.rl_tx_list_map); 1014 if (error) { 1015 device_printf(dev, "could not allocate TX DMA ring\n"); 1016 return (error); 1017 } 1018 1019 /* Load the map for the TX ring. */ 1020 1021 sc->rl_ldata.rl_tx_list_addr = 0; 1022 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1023 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1024 tx_list_size, re_dma_map_addr, 1025 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1026 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 1027 device_printf(dev, "could not load TX DMA ring\n"); 1028 return (ENOMEM); 1029 } 1030 1031 /* Create DMA maps for TX buffers */ 1032 1033 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1034 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1035 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1036 if (error) { 1037 device_printf(dev, "could not create DMA map for TX\n"); 1038 return (error); 1039 } 1040 } 1041 1042 /* 1043 * Allocate map for RX descriptor list. 1044 */ 1045 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1046 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1047 NULL, rx_list_size, 1, rx_list_size, 0, 1048 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1049 if (error) { 1050 device_printf(dev, "could not create RX DMA ring tag\n"); 1051 return (error); 1052 } 1053 1054 /* Allocate DMA'able memory for the RX ring */ 1055 1056 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1057 (void **)&sc->rl_ldata.rl_rx_list, 1058 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1059 &sc->rl_ldata.rl_rx_list_map); 1060 if (error) { 1061 device_printf(dev, "could not allocate RX DMA ring\n"); 1062 return (error); 1063 } 1064 1065 /* Load the map for the RX ring. */ 1066 1067 sc->rl_ldata.rl_rx_list_addr = 0; 1068 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1069 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1070 rx_list_size, re_dma_map_addr, 1071 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1072 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1073 device_printf(dev, "could not load RX DMA ring\n"); 1074 return (ENOMEM); 1075 } 1076 1077 /* Create DMA maps for RX buffers */ 1078 1079 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1080 &sc->rl_ldata.rl_rx_sparemap); 1081 if (error) { 1082 device_printf(dev, "could not create spare DMA map for RX\n"); 1083 return (error); 1084 } 1085 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1086 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1087 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1088 if (error) { 1089 device_printf(dev, "could not create DMA map for RX\n"); 1090 return (error); 1091 } 1092 } 1093 1094 return (0); 1095 } 1096 1097 /* 1098 * Attach the interface. Allocate softc structures, do ifmedia 1099 * setup and ethernet/BPF attach. 1100 */ 1101 static int 1102 re_attach(device_t dev) 1103 { 1104 u_char eaddr[ETHER_ADDR_LEN]; 1105 u_int16_t as[ETHER_ADDR_LEN / 2]; 1106 struct rl_softc *sc; 1107 struct ifnet *ifp; 1108 struct rl_hwrev *hw_rev; 1109 int hwrev; 1110 u_int16_t devid, re_did = 0; 1111 int error = 0, rid, i; 1112 int msic, reg; 1113 uint8_t cfg; 1114 1115 sc = device_get_softc(dev); 1116 sc->rl_dev = dev; 1117 1118 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1119 MTX_DEF); 1120 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1121 1122 /* 1123 * Map control/status registers. 1124 */ 1125 pci_enable_busmaster(dev); 1126 1127 devid = pci_get_device(dev); 1128 /* 1129 * Prefer memory space register mapping over IO space. 1130 * Because RTL8169SC does not seem to work when memory mapping 1131 * is used always activate io mapping. 1132 */ 1133 if (devid == RT_DEVICEID_8169SC) 1134 prefer_iomap = 1; 1135 if (prefer_iomap == 0) { 1136 sc->rl_res_id = PCIR_BAR(1); 1137 sc->rl_res_type = SYS_RES_MEMORY; 1138 /* RTL8168/8101E seems to use different BARs. */ 1139 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E) 1140 sc->rl_res_id = PCIR_BAR(2); 1141 } else { 1142 sc->rl_res_id = PCIR_BAR(0); 1143 sc->rl_res_type = SYS_RES_IOPORT; 1144 } 1145 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1146 &sc->rl_res_id, RF_ACTIVE); 1147 if (sc->rl_res == NULL && prefer_iomap == 0) { 1148 sc->rl_res_id = PCIR_BAR(0); 1149 sc->rl_res_type = SYS_RES_IOPORT; 1150 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1151 &sc->rl_res_id, RF_ACTIVE); 1152 } 1153 if (sc->rl_res == NULL) { 1154 device_printf(dev, "couldn't map ports/memory\n"); 1155 error = ENXIO; 1156 goto fail; 1157 } 1158 1159 sc->rl_btag = rman_get_bustag(sc->rl_res); 1160 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1161 1162 msic = 0; 1163 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 1164 sc->rl_flags |= RL_FLAG_PCIE; 1165 /* Set PCIe maximum read request size to 2048. */ 1166 if (pci_get_max_read_req(dev) < 2048) 1167 pci_set_max_read_req(dev, 2048); 1168 msic = pci_msi_count(dev); 1169 if (bootverbose) 1170 device_printf(dev, "MSI count : %d\n", msic); 1171 } 1172 if (msic > 0 && msi_disable == 0) { 1173 msic = 1; 1174 if (pci_alloc_msi(dev, &msic) == 0) { 1175 if (msic == RL_MSI_MESSAGES) { 1176 device_printf(dev, "Using %d MSI messages\n", 1177 msic); 1178 sc->rl_flags |= RL_FLAG_MSI; 1179 /* Explicitly set MSI enable bit. */ 1180 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1181 cfg = CSR_READ_1(sc, RL_CFG2); 1182 cfg |= RL_CFG2_MSI; 1183 CSR_WRITE_1(sc, RL_CFG2, cfg); 1184 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1185 } else 1186 pci_release_msi(dev); 1187 } 1188 } 1189 1190 /* Allocate interrupt */ 1191 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1192 rid = 0; 1193 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1194 RF_SHAREABLE | RF_ACTIVE); 1195 if (sc->rl_irq[0] == NULL) { 1196 device_printf(dev, "couldn't allocate IRQ resources\n"); 1197 error = ENXIO; 1198 goto fail; 1199 } 1200 } else { 1201 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1202 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1203 SYS_RES_IRQ, &rid, RF_ACTIVE); 1204 if (sc->rl_irq[i] == NULL) { 1205 device_printf(dev, 1206 "couldn't llocate IRQ resources for " 1207 "message %d\n", rid); 1208 error = ENXIO; 1209 goto fail; 1210 } 1211 } 1212 } 1213 1214 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1215 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1216 cfg = CSR_READ_1(sc, RL_CFG2); 1217 if ((cfg & RL_CFG2_MSI) != 0) { 1218 device_printf(dev, "turning off MSI enable bit.\n"); 1219 cfg &= ~RL_CFG2_MSI; 1220 CSR_WRITE_1(sc, RL_CFG2, cfg); 1221 } 1222 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1223 } 1224 1225 /* Reset the adapter. */ 1226 RL_LOCK(sc); 1227 re_reset(sc); 1228 RL_UNLOCK(sc); 1229 1230 hw_rev = re_hwrevs; 1231 hwrev = CSR_READ_4(sc, RL_TXCFG); 1232 switch (hwrev & 0x70000000) { 1233 case 0x00000000: 1234 case 0x10000000: 1235 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000); 1236 hwrev &= (RL_TXCFG_HWREV | 0x80000000); 1237 break; 1238 default: 1239 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000); 1240 hwrev &= RL_TXCFG_HWREV; 1241 break; 1242 } 1243 device_printf(dev, "MAC rev. 0x%08x\n", hwrev & 0x00700000); 1244 while (hw_rev->rl_desc != NULL) { 1245 if (hw_rev->rl_rev == hwrev) { 1246 sc->rl_type = hw_rev->rl_type; 1247 sc->rl_hwrev = hw_rev->rl_rev; 1248 break; 1249 } 1250 hw_rev++; 1251 } 1252 if (hw_rev->rl_desc == NULL) { 1253 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev); 1254 error = ENXIO; 1255 goto fail; 1256 } 1257 1258 switch (hw_rev->rl_rev) { 1259 case RL_HWREV_8139CPLUS: 1260 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_FASTETHER | 1261 RL_FLAG_AUTOPAD; 1262 break; 1263 case RL_HWREV_8100E: 1264 case RL_HWREV_8101E: 1265 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_PHYWAKE | 1266 RL_FLAG_FASTETHER; 1267 break; 1268 case RL_HWREV_8102E: 1269 case RL_HWREV_8102EL: 1270 case RL_HWREV_8102EL_SPIN1: 1271 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_PHYWAKE | 1272 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1273 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD; 1274 break; 1275 case RL_HWREV_8103E: 1276 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_PHYWAKE | 1277 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1278 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | 1279 RL_FLAG_MACSLEEP; 1280 break; 1281 case RL_HWREV_8168_SPIN1: 1282 case RL_HWREV_8168_SPIN2: 1283 sc->rl_flags |= RL_FLAG_WOLRXENB; 1284 /* FALLTHROUGH */ 1285 case RL_HWREV_8168_SPIN3: 1286 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT; 1287 break; 1288 case RL_HWREV_8168C_SPIN2: 1289 sc->rl_flags |= RL_FLAG_MACSLEEP; 1290 /* FALLTHROUGH */ 1291 case RL_HWREV_8168C: 1292 if ((hwrev & 0x00700000) == 0x00200000) 1293 sc->rl_flags |= RL_FLAG_MACSLEEP; 1294 /* FALLTHROUGH */ 1295 case RL_HWREV_8168CP: 1296 case RL_HWREV_8168D: 1297 case RL_HWREV_8168DP: 1298 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1299 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1300 RL_FLAG_AUTOPAD; 1301 /* 1302 * These controllers support jumbo frame but it seems 1303 * that enabling it requires touching additional magic 1304 * registers. Depending on MAC revisions some 1305 * controllers need to disable checksum offload. So 1306 * disable jumbo frame until I have better idea what 1307 * it really requires to make it support. 1308 * RTL8168C/CP : supports up to 6KB jumbo frame. 1309 * RTL8111C/CP : supports up to 9KB jumbo frame. 1310 */ 1311 sc->rl_flags |= RL_FLAG_NOJUMBO; 1312 break; 1313 case RL_HWREV_8169_8110SB: 1314 case RL_HWREV_8169_8110SBL: 1315 case RL_HWREV_8169_8110SC: 1316 case RL_HWREV_8169_8110SCE: 1317 sc->rl_flags |= RL_FLAG_PHYWAKE; 1318 /* FALLTHROUGH */ 1319 case RL_HWREV_8169: 1320 case RL_HWREV_8169S: 1321 case RL_HWREV_8110S: 1322 sc->rl_flags |= RL_FLAG_MACRESET; 1323 break; 1324 default: 1325 break; 1326 } 1327 1328 /* Enable PME. */ 1329 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1330 cfg = CSR_READ_1(sc, RL_CFG1); 1331 cfg |= RL_CFG1_PME; 1332 CSR_WRITE_1(sc, RL_CFG1, cfg); 1333 cfg = CSR_READ_1(sc, RL_CFG5); 1334 cfg &= RL_CFG5_PME_STS; 1335 CSR_WRITE_1(sc, RL_CFG5, cfg); 1336 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1337 1338 if ((sc->rl_flags & RL_FLAG_PAR) != 0) { 1339 /* 1340 * XXX Should have a better way to extract station 1341 * address from EEPROM. 1342 */ 1343 for (i = 0; i < ETHER_ADDR_LEN; i++) 1344 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1345 } else { 1346 sc->rl_eewidth = RL_9356_ADDR_LEN; 1347 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1348 if (re_did != 0x8129) 1349 sc->rl_eewidth = RL_9346_ADDR_LEN; 1350 1351 /* 1352 * Get station address from the EEPROM. 1353 */ 1354 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1355 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1356 as[i] = le16toh(as[i]); 1357 bcopy(as, eaddr, sizeof(eaddr)); 1358 } 1359 1360 if (sc->rl_type == RL_8169) { 1361 /* Set RX length mask and number of descriptors. */ 1362 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1363 sc->rl_txstart = RL_GTXSTART; 1364 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1365 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1366 } else { 1367 /* Set RX length mask and number of descriptors. */ 1368 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1369 sc->rl_txstart = RL_TXSTART; 1370 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1371 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1372 } 1373 1374 error = re_allocmem(dev, sc); 1375 if (error) 1376 goto fail; 1377 1378 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1379 if (ifp == NULL) { 1380 device_printf(dev, "can not if_alloc()\n"); 1381 error = ENOSPC; 1382 goto fail; 1383 } 1384 1385 /* Take controller out of deep sleep mode. */ 1386 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 1387 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 1388 CSR_WRITE_1(sc, RL_GPIO, 1389 CSR_READ_1(sc, RL_GPIO) | 0x01); 1390 else 1391 CSR_WRITE_1(sc, RL_GPIO, 1392 CSR_READ_1(sc, RL_GPIO) & ~0x01); 1393 } 1394 1395 /* Take PHY out of power down mode. */ 1396 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) { 1397 re_gmii_writereg(dev, 1, 0x1f, 0); 1398 re_gmii_writereg(dev, 1, 0x0e, 0); 1399 } 1400 1401 /* Do MII setup */ 1402 if (mii_phy_probe(dev, &sc->rl_miibus, 1403 re_ifmedia_upd, re_ifmedia_sts)) { 1404 device_printf(dev, "MII without any phy!\n"); 1405 error = ENXIO; 1406 goto fail; 1407 } 1408 1409 ifp->if_softc = sc; 1410 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1411 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1412 ifp->if_ioctl = re_ioctl; 1413 ifp->if_start = re_start; 1414 ifp->if_hwassist = RE_CSUM_FEATURES; 1415 ifp->if_capabilities = IFCAP_HWCSUM; 1416 ifp->if_capenable = ifp->if_capabilities; 1417 ifp->if_init = re_init; 1418 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1419 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1420 IFQ_SET_READY(&ifp->if_snd); 1421 1422 TASK_INIT(&sc->rl_txtask, 1, re_tx_task, ifp); 1423 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1424 1425 /* 1426 * XXX 1427 * Still have no idea how to make TSO work on 8168C, 8168CP, 1428 * 8111C and 8111CP. 1429 */ 1430 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 1431 ifp->if_hwassist |= CSUM_TSO; 1432 ifp->if_capabilities |= IFCAP_TSO4 | IFCAP_VLAN_HWTSO; 1433 } 1434 1435 /* 1436 * Call MI attach routine. 1437 */ 1438 ether_ifattach(ifp, eaddr); 1439 1440 /* VLAN capability setup */ 1441 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1442 if (ifp->if_capabilities & IFCAP_HWCSUM) 1443 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1444 /* Enable WOL if PM is supported. */ 1445 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, ®) == 0) 1446 ifp->if_capabilities |= IFCAP_WOL; 1447 ifp->if_capenable = ifp->if_capabilities; 1448 /* 1449 * Don't enable TSO by default. Under certain 1450 * circumtances the controller generated corrupted 1451 * packets in TSO size. 1452 */ 1453 ifp->if_hwassist &= ~CSUM_TSO; 1454 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO); 1455 #ifdef DEVICE_POLLING 1456 ifp->if_capabilities |= IFCAP_POLLING; 1457 #endif 1458 /* 1459 * Tell the upper layer(s) we support long frames. 1460 * Must appear after the call to ether_ifattach() because 1461 * ether_ifattach() sets ifi_hdrlen to the default value. 1462 */ 1463 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1464 1465 #ifdef RE_DIAG 1466 /* 1467 * Perform hardware diagnostic on the original RTL8169. 1468 * Some 32-bit cards were incorrectly wired and would 1469 * malfunction if plugged into a 64-bit slot. 1470 */ 1471 1472 if (hwrev == RL_HWREV_8169) { 1473 error = re_diag(sc); 1474 if (error) { 1475 device_printf(dev, 1476 "attach aborted due to hardware diag failure\n"); 1477 ether_ifdetach(ifp); 1478 goto fail; 1479 } 1480 } 1481 #endif 1482 1483 /* Hook interrupt last to avoid having to lock softc */ 1484 if ((sc->rl_flags & RL_FLAG_MSI) == 0) 1485 error = bus_setup_intr(dev, sc->rl_irq[0], 1486 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1487 &sc->rl_intrhand[0]); 1488 else { 1489 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1490 error = bus_setup_intr(dev, sc->rl_irq[i], 1491 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1492 &sc->rl_intrhand[i]); 1493 if (error != 0) 1494 break; 1495 } 1496 } 1497 if (error) { 1498 device_printf(dev, "couldn't set up irq\n"); 1499 ether_ifdetach(ifp); 1500 } 1501 1502 fail: 1503 1504 if (error) 1505 re_detach(dev); 1506 1507 return (error); 1508 } 1509 1510 /* 1511 * Shutdown hardware and free up resources. This can be called any 1512 * time after the mutex has been initialized. It is called in both 1513 * the error case in attach and the normal detach case so it needs 1514 * to be careful about only freeing resources that have actually been 1515 * allocated. 1516 */ 1517 static int 1518 re_detach(device_t dev) 1519 { 1520 struct rl_softc *sc; 1521 struct ifnet *ifp; 1522 int i, rid; 1523 1524 sc = device_get_softc(dev); 1525 ifp = sc->rl_ifp; 1526 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1527 1528 /* These should only be active if attach succeeded */ 1529 if (device_is_attached(dev)) { 1530 #ifdef DEVICE_POLLING 1531 if (ifp->if_capenable & IFCAP_POLLING) 1532 ether_poll_deregister(ifp); 1533 #endif 1534 RL_LOCK(sc); 1535 #if 0 1536 sc->suspended = 1; 1537 #endif 1538 re_stop(sc); 1539 RL_UNLOCK(sc); 1540 callout_drain(&sc->rl_stat_callout); 1541 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1542 taskqueue_drain(taskqueue_fast, &sc->rl_txtask); 1543 /* 1544 * Force off the IFF_UP flag here, in case someone 1545 * still had a BPF descriptor attached to this 1546 * interface. If they do, ether_ifdetach() will cause 1547 * the BPF code to try and clear the promisc mode 1548 * flag, which will bubble down to re_ioctl(), 1549 * which will try to call re_init() again. This will 1550 * turn the NIC back on and restart the MII ticker, 1551 * which will panic the system when the kernel tries 1552 * to invoke the re_tick() function that isn't there 1553 * anymore. 1554 */ 1555 ifp->if_flags &= ~IFF_UP; 1556 ether_ifdetach(ifp); 1557 } 1558 if (sc->rl_miibus) 1559 device_delete_child(dev, sc->rl_miibus); 1560 bus_generic_detach(dev); 1561 1562 /* 1563 * The rest is resource deallocation, so we should already be 1564 * stopped here. 1565 */ 1566 1567 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1568 if (sc->rl_intrhand[i] != NULL) { 1569 bus_teardown_intr(dev, sc->rl_irq[i], 1570 sc->rl_intrhand[i]); 1571 sc->rl_intrhand[i] = NULL; 1572 } 1573 } 1574 if (ifp != NULL) 1575 if_free(ifp); 1576 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1577 if (sc->rl_irq[0] != NULL) { 1578 bus_release_resource(dev, SYS_RES_IRQ, 0, 1579 sc->rl_irq[0]); 1580 sc->rl_irq[0] = NULL; 1581 } 1582 } else { 1583 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1584 if (sc->rl_irq[i] != NULL) { 1585 bus_release_resource(dev, SYS_RES_IRQ, rid, 1586 sc->rl_irq[i]); 1587 sc->rl_irq[i] = NULL; 1588 } 1589 } 1590 pci_release_msi(dev); 1591 } 1592 if (sc->rl_res) 1593 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, 1594 sc->rl_res); 1595 1596 /* Unload and free the RX DMA ring memory and map */ 1597 1598 if (sc->rl_ldata.rl_rx_list_tag) { 1599 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1600 sc->rl_ldata.rl_rx_list_map); 1601 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1602 sc->rl_ldata.rl_rx_list, 1603 sc->rl_ldata.rl_rx_list_map); 1604 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1605 } 1606 1607 /* Unload and free the TX DMA ring memory and map */ 1608 1609 if (sc->rl_ldata.rl_tx_list_tag) { 1610 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1611 sc->rl_ldata.rl_tx_list_map); 1612 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1613 sc->rl_ldata.rl_tx_list, 1614 sc->rl_ldata.rl_tx_list_map); 1615 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1616 } 1617 1618 /* Destroy all the RX and TX buffer maps */ 1619 1620 if (sc->rl_ldata.rl_tx_mtag) { 1621 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1622 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1623 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1624 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1625 } 1626 if (sc->rl_ldata.rl_rx_mtag) { 1627 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) 1628 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1629 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1630 if (sc->rl_ldata.rl_rx_sparemap) 1631 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1632 sc->rl_ldata.rl_rx_sparemap); 1633 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1634 } 1635 1636 /* Unload and free the stats buffer and map */ 1637 1638 if (sc->rl_ldata.rl_stag) { 1639 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1640 sc->rl_ldata.rl_rx_list_map); 1641 bus_dmamem_free(sc->rl_ldata.rl_stag, 1642 sc->rl_ldata.rl_stats, 1643 sc->rl_ldata.rl_smap); 1644 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1645 } 1646 1647 if (sc->rl_parent_tag) 1648 bus_dma_tag_destroy(sc->rl_parent_tag); 1649 1650 mtx_destroy(&sc->rl_mtx); 1651 1652 return (0); 1653 } 1654 1655 static __inline void 1656 re_discard_rxbuf(struct rl_softc *sc, int idx) 1657 { 1658 struct rl_desc *desc; 1659 struct rl_rxdesc *rxd; 1660 uint32_t cmdstat; 1661 1662 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1663 desc = &sc->rl_ldata.rl_rx_list[idx]; 1664 desc->rl_vlanctl = 0; 1665 cmdstat = rxd->rx_size; 1666 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1667 cmdstat |= RL_RDESC_CMD_EOR; 1668 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1669 } 1670 1671 static int 1672 re_newbuf(struct rl_softc *sc, int idx) 1673 { 1674 struct mbuf *m; 1675 struct rl_rxdesc *rxd; 1676 bus_dma_segment_t segs[1]; 1677 bus_dmamap_t map; 1678 struct rl_desc *desc; 1679 uint32_t cmdstat; 1680 int error, nsegs; 1681 1682 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1683 if (m == NULL) 1684 return (ENOBUFS); 1685 1686 m->m_len = m->m_pkthdr.len = MCLBYTES; 1687 #ifdef RE_FIXUP_RX 1688 /* 1689 * This is part of an evil trick to deal with non-x86 platforms. 1690 * The RealTek chip requires RX buffers to be aligned on 64-bit 1691 * boundaries, but that will hose non-x86 machines. To get around 1692 * this, we leave some empty space at the start of each buffer 1693 * and for non-x86 hosts, we copy the buffer back six bytes 1694 * to achieve word alignment. This is slightly more efficient 1695 * than allocating a new buffer, copying the contents, and 1696 * discarding the old buffer. 1697 */ 1698 m_adj(m, RE_ETHER_ALIGN); 1699 #endif 1700 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1701 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1702 if (error != 0) { 1703 m_freem(m); 1704 return (ENOBUFS); 1705 } 1706 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1707 1708 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1709 if (rxd->rx_m != NULL) { 1710 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1711 BUS_DMASYNC_POSTREAD); 1712 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1713 } 1714 1715 rxd->rx_m = m; 1716 map = rxd->rx_dmamap; 1717 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1718 rxd->rx_size = segs[0].ds_len; 1719 sc->rl_ldata.rl_rx_sparemap = map; 1720 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1721 BUS_DMASYNC_PREREAD); 1722 1723 desc = &sc->rl_ldata.rl_rx_list[idx]; 1724 desc->rl_vlanctl = 0; 1725 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1726 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1727 cmdstat = segs[0].ds_len; 1728 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1729 cmdstat |= RL_RDESC_CMD_EOR; 1730 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1731 1732 return (0); 1733 } 1734 1735 #ifdef RE_FIXUP_RX 1736 static __inline void 1737 re_fixup_rx(struct mbuf *m) 1738 { 1739 int i; 1740 uint16_t *src, *dst; 1741 1742 src = mtod(m, uint16_t *); 1743 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1744 1745 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1746 *dst++ = *src++; 1747 1748 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1749 } 1750 #endif 1751 1752 static int 1753 re_tx_list_init(struct rl_softc *sc) 1754 { 1755 struct rl_desc *desc; 1756 int i; 1757 1758 RL_LOCK_ASSERT(sc); 1759 1760 bzero(sc->rl_ldata.rl_tx_list, 1761 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 1762 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1763 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 1764 /* Set EOR. */ 1765 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 1766 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 1767 1768 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1769 sc->rl_ldata.rl_tx_list_map, 1770 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1771 1772 sc->rl_ldata.rl_tx_prodidx = 0; 1773 sc->rl_ldata.rl_tx_considx = 0; 1774 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 1775 1776 return (0); 1777 } 1778 1779 static int 1780 re_rx_list_init(struct rl_softc *sc) 1781 { 1782 int error, i; 1783 1784 bzero(sc->rl_ldata.rl_rx_list, 1785 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 1786 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1787 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 1788 if ((error = re_newbuf(sc, i)) != 0) 1789 return (error); 1790 } 1791 1792 /* Flush the RX descriptors */ 1793 1794 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1795 sc->rl_ldata.rl_rx_list_map, 1796 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1797 1798 sc->rl_ldata.rl_rx_prodidx = 0; 1799 sc->rl_head = sc->rl_tail = NULL; 1800 1801 return (0); 1802 } 1803 1804 /* 1805 * RX handler for C+ and 8169. For the gigE chips, we support 1806 * the reception of jumbo frames that have been fragmented 1807 * across multiple 2K mbuf cluster buffers. 1808 */ 1809 static int 1810 re_rxeof(struct rl_softc *sc, int *rx_npktsp) 1811 { 1812 struct mbuf *m; 1813 struct ifnet *ifp; 1814 int i, total_len; 1815 struct rl_desc *cur_rx; 1816 u_int32_t rxstat, rxvlan; 1817 int maxpkt = 16, rx_npkts = 0; 1818 1819 RL_LOCK_ASSERT(sc); 1820 1821 ifp = sc->rl_ifp; 1822 1823 /* Invalidate the descriptor memory */ 1824 1825 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1826 sc->rl_ldata.rl_rx_list_map, 1827 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1828 1829 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 1830 i = RL_RX_DESC_NXT(sc, i)) { 1831 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1832 break; 1833 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1834 rxstat = le32toh(cur_rx->rl_cmdstat); 1835 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 1836 break; 1837 total_len = rxstat & sc->rl_rxlenmask; 1838 rxvlan = le32toh(cur_rx->rl_vlanctl); 1839 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 1840 1841 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1842 if (re_newbuf(sc, i) != 0) { 1843 /* 1844 * If this is part of a multi-fragment packet, 1845 * discard all the pieces. 1846 */ 1847 if (sc->rl_head != NULL) { 1848 m_freem(sc->rl_head); 1849 sc->rl_head = sc->rl_tail = NULL; 1850 } 1851 re_discard_rxbuf(sc, i); 1852 continue; 1853 } 1854 m->m_len = RE_RX_DESC_BUFLEN; 1855 if (sc->rl_head == NULL) 1856 sc->rl_head = sc->rl_tail = m; 1857 else { 1858 m->m_flags &= ~M_PKTHDR; 1859 sc->rl_tail->m_next = m; 1860 sc->rl_tail = m; 1861 } 1862 continue; 1863 } 1864 1865 /* 1866 * NOTE: for the 8139C+, the frame length field 1867 * is always 12 bits in size, but for the gigE chips, 1868 * it is 13 bits (since the max RX frame length is 16K). 1869 * Unfortunately, all 32 bits in the status word 1870 * were already used, so to make room for the extra 1871 * length bit, RealTek took out the 'frame alignment 1872 * error' bit and shifted the other status bits 1873 * over one slot. The OWN, EOR, FS and LS bits are 1874 * still in the same places. We have already extracted 1875 * the frame length and checked the OWN bit, so rather 1876 * than using an alternate bit mapping, we shift the 1877 * status bits one space to the right so we can evaluate 1878 * them using the 8169 status as though it was in the 1879 * same format as that of the 8139C+. 1880 */ 1881 if (sc->rl_type == RL_8169) 1882 rxstat >>= 1; 1883 1884 /* 1885 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 1886 * set, but if CRC is clear, it will still be a valid frame. 1887 */ 1888 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 && 1889 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) { 1890 ifp->if_ierrors++; 1891 /* 1892 * If this is part of a multi-fragment packet, 1893 * discard all the pieces. 1894 */ 1895 if (sc->rl_head != NULL) { 1896 m_freem(sc->rl_head); 1897 sc->rl_head = sc->rl_tail = NULL; 1898 } 1899 re_discard_rxbuf(sc, i); 1900 continue; 1901 } 1902 1903 /* 1904 * If allocating a replacement mbuf fails, 1905 * reload the current one. 1906 */ 1907 1908 if (re_newbuf(sc, i) != 0) { 1909 ifp->if_iqdrops++; 1910 if (sc->rl_head != NULL) { 1911 m_freem(sc->rl_head); 1912 sc->rl_head = sc->rl_tail = NULL; 1913 } 1914 re_discard_rxbuf(sc, i); 1915 continue; 1916 } 1917 1918 if (sc->rl_head != NULL) { 1919 m->m_len = total_len % RE_RX_DESC_BUFLEN; 1920 if (m->m_len == 0) 1921 m->m_len = RE_RX_DESC_BUFLEN; 1922 /* 1923 * Special case: if there's 4 bytes or less 1924 * in this buffer, the mbuf can be discarded: 1925 * the last 4 bytes is the CRC, which we don't 1926 * care about anyway. 1927 */ 1928 if (m->m_len <= ETHER_CRC_LEN) { 1929 sc->rl_tail->m_len -= 1930 (ETHER_CRC_LEN - m->m_len); 1931 m_freem(m); 1932 } else { 1933 m->m_len -= ETHER_CRC_LEN; 1934 m->m_flags &= ~M_PKTHDR; 1935 sc->rl_tail->m_next = m; 1936 } 1937 m = sc->rl_head; 1938 sc->rl_head = sc->rl_tail = NULL; 1939 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1940 } else 1941 m->m_pkthdr.len = m->m_len = 1942 (total_len - ETHER_CRC_LEN); 1943 1944 #ifdef RE_FIXUP_RX 1945 re_fixup_rx(m); 1946 #endif 1947 ifp->if_ipackets++; 1948 m->m_pkthdr.rcvif = ifp; 1949 1950 /* Do RX checksumming if enabled */ 1951 1952 if (ifp->if_capenable & IFCAP_RXCSUM) { 1953 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 1954 /* Check IP header checksum */ 1955 if (rxstat & RL_RDESC_STAT_PROTOID) 1956 m->m_pkthdr.csum_flags |= 1957 CSUM_IP_CHECKED; 1958 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1959 m->m_pkthdr.csum_flags |= 1960 CSUM_IP_VALID; 1961 1962 /* Check TCP/UDP checksum */ 1963 if ((RL_TCPPKT(rxstat) && 1964 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1965 (RL_UDPPKT(rxstat) && 1966 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1967 m->m_pkthdr.csum_flags |= 1968 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1969 m->m_pkthdr.csum_data = 0xffff; 1970 } 1971 } else { 1972 /* 1973 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP 1974 */ 1975 if ((rxstat & RL_RDESC_STAT_PROTOID) && 1976 (rxvlan & RL_RDESC_IPV4)) 1977 m->m_pkthdr.csum_flags |= 1978 CSUM_IP_CHECKED; 1979 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) && 1980 (rxvlan & RL_RDESC_IPV4)) 1981 m->m_pkthdr.csum_flags |= 1982 CSUM_IP_VALID; 1983 if (((rxstat & RL_RDESC_STAT_TCP) && 1984 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1985 ((rxstat & RL_RDESC_STAT_UDP) && 1986 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1987 m->m_pkthdr.csum_flags |= 1988 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1989 m->m_pkthdr.csum_data = 0xffff; 1990 } 1991 } 1992 } 1993 maxpkt--; 1994 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 1995 m->m_pkthdr.ether_vtag = 1996 bswap16((rxvlan & RL_RDESC_VLANCTL_DATA)); 1997 m->m_flags |= M_VLANTAG; 1998 } 1999 RL_UNLOCK(sc); 2000 (*ifp->if_input)(ifp, m); 2001 RL_LOCK(sc); 2002 rx_npkts++; 2003 } 2004 2005 /* Flush the RX DMA ring */ 2006 2007 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2008 sc->rl_ldata.rl_rx_list_map, 2009 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2010 2011 sc->rl_ldata.rl_rx_prodidx = i; 2012 2013 if (rx_npktsp != NULL) 2014 *rx_npktsp = rx_npkts; 2015 if (maxpkt) 2016 return(EAGAIN); 2017 2018 return(0); 2019 } 2020 2021 static void 2022 re_txeof(struct rl_softc *sc) 2023 { 2024 struct ifnet *ifp; 2025 struct rl_txdesc *txd; 2026 u_int32_t txstat; 2027 int cons; 2028 2029 cons = sc->rl_ldata.rl_tx_considx; 2030 if (cons == sc->rl_ldata.rl_tx_prodidx) 2031 return; 2032 2033 ifp = sc->rl_ifp; 2034 /* Invalidate the TX descriptor list */ 2035 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2036 sc->rl_ldata.rl_tx_list_map, 2037 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2038 2039 for (; cons != sc->rl_ldata.rl_tx_prodidx; 2040 cons = RL_TX_DESC_NXT(sc, cons)) { 2041 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 2042 if (txstat & RL_TDESC_STAT_OWN) 2043 break; 2044 /* 2045 * We only stash mbufs in the last descriptor 2046 * in a fragment chain, which also happens to 2047 * be the only place where the TX status bits 2048 * are valid. 2049 */ 2050 if (txstat & RL_TDESC_CMD_EOF) { 2051 txd = &sc->rl_ldata.rl_tx_desc[cons]; 2052 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2053 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2054 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2055 txd->tx_dmamap); 2056 KASSERT(txd->tx_m != NULL, 2057 ("%s: freeing NULL mbufs!", __func__)); 2058 m_freem(txd->tx_m); 2059 txd->tx_m = NULL; 2060 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 2061 RL_TDESC_STAT_COLCNT)) 2062 ifp->if_collisions++; 2063 if (txstat & RL_TDESC_STAT_TXERRSUM) 2064 ifp->if_oerrors++; 2065 else 2066 ifp->if_opackets++; 2067 } 2068 sc->rl_ldata.rl_tx_free++; 2069 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2070 } 2071 sc->rl_ldata.rl_tx_considx = cons; 2072 2073 /* No changes made to the TX ring, so no flush needed */ 2074 2075 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 2076 #ifdef RE_TX_MODERATION 2077 /* 2078 * If not all descriptors have been reaped yet, reload 2079 * the timer so that we will eventually get another 2080 * interrupt that will cause us to re-enter this routine. 2081 * This is done in case the transmitter has gone idle. 2082 */ 2083 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2084 #endif 2085 } else 2086 sc->rl_watchdog_timer = 0; 2087 } 2088 2089 static void 2090 re_tick(void *xsc) 2091 { 2092 struct rl_softc *sc; 2093 struct mii_data *mii; 2094 2095 sc = xsc; 2096 2097 RL_LOCK_ASSERT(sc); 2098 2099 mii = device_get_softc(sc->rl_miibus); 2100 mii_tick(mii); 2101 if ((sc->rl_flags & RL_FLAG_LINK) == 0) 2102 re_miibus_statchg(sc->rl_dev); 2103 /* 2104 * Reclaim transmitted frames here. Technically it is not 2105 * necessary to do here but it ensures periodic reclamation 2106 * regardless of Tx completion interrupt which seems to be 2107 * lost on PCIe based controllers under certain situations. 2108 */ 2109 re_txeof(sc); 2110 re_watchdog(sc); 2111 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2112 } 2113 2114 #ifdef DEVICE_POLLING 2115 static int 2116 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2117 { 2118 struct rl_softc *sc = ifp->if_softc; 2119 int rx_npkts = 0; 2120 2121 RL_LOCK(sc); 2122 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2123 rx_npkts = re_poll_locked(ifp, cmd, count); 2124 RL_UNLOCK(sc); 2125 return (rx_npkts); 2126 } 2127 2128 static int 2129 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2130 { 2131 struct rl_softc *sc = ifp->if_softc; 2132 int rx_npkts; 2133 2134 RL_LOCK_ASSERT(sc); 2135 2136 sc->rxcycles = count; 2137 re_rxeof(sc, &rx_npkts); 2138 re_txeof(sc); 2139 2140 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2141 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2142 2143 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2144 u_int16_t status; 2145 2146 status = CSR_READ_2(sc, RL_ISR); 2147 if (status == 0xffff) 2148 return (rx_npkts); 2149 if (status) 2150 CSR_WRITE_2(sc, RL_ISR, status); 2151 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2152 (sc->rl_flags & RL_FLAG_PCIE)) 2153 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2154 2155 /* 2156 * XXX check behaviour on receiver stalls. 2157 */ 2158 2159 if (status & RL_ISR_SYSTEM_ERR) { 2160 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2161 re_init_locked(sc); 2162 } 2163 } 2164 return (rx_npkts); 2165 } 2166 #endif /* DEVICE_POLLING */ 2167 2168 static int 2169 re_intr(void *arg) 2170 { 2171 struct rl_softc *sc; 2172 uint16_t status; 2173 2174 sc = arg; 2175 2176 status = CSR_READ_2(sc, RL_ISR); 2177 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2178 return (FILTER_STRAY); 2179 CSR_WRITE_2(sc, RL_IMR, 0); 2180 2181 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2182 2183 return (FILTER_HANDLED); 2184 } 2185 2186 static void 2187 re_int_task(void *arg, int npending) 2188 { 2189 struct rl_softc *sc; 2190 struct ifnet *ifp; 2191 u_int16_t status; 2192 int rval = 0; 2193 2194 sc = arg; 2195 ifp = sc->rl_ifp; 2196 2197 RL_LOCK(sc); 2198 2199 status = CSR_READ_2(sc, RL_ISR); 2200 CSR_WRITE_2(sc, RL_ISR, status); 2201 2202 if (sc->suspended || 2203 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2204 RL_UNLOCK(sc); 2205 return; 2206 } 2207 2208 #ifdef DEVICE_POLLING 2209 if (ifp->if_capenable & IFCAP_POLLING) { 2210 RL_UNLOCK(sc); 2211 return; 2212 } 2213 #endif 2214 2215 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2216 rval = re_rxeof(sc, NULL); 2217 2218 /* 2219 * Some chips will ignore a second TX request issued 2220 * while an existing transmission is in progress. If 2221 * the transmitter goes idle but there are still 2222 * packets waiting to be sent, we need to restart the 2223 * channel here to flush them out. This only seems to 2224 * be required with the PCIe devices. 2225 */ 2226 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2227 (sc->rl_flags & RL_FLAG_PCIE)) 2228 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2229 if (status & ( 2230 #ifdef RE_TX_MODERATION 2231 RL_ISR_TIMEOUT_EXPIRED| 2232 #else 2233 RL_ISR_TX_OK| 2234 #endif 2235 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2236 re_txeof(sc); 2237 2238 if (status & RL_ISR_SYSTEM_ERR) { 2239 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2240 re_init_locked(sc); 2241 } 2242 2243 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2244 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2245 2246 RL_UNLOCK(sc); 2247 2248 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2249 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2250 return; 2251 } 2252 2253 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2254 } 2255 2256 static int 2257 re_encap(struct rl_softc *sc, struct mbuf **m_head) 2258 { 2259 struct rl_txdesc *txd, *txd_last; 2260 bus_dma_segment_t segs[RL_NTXSEGS]; 2261 bus_dmamap_t map; 2262 struct mbuf *m_new; 2263 struct rl_desc *desc; 2264 int nsegs, prod; 2265 int i, error, ei, si; 2266 int padlen; 2267 uint32_t cmdstat, csum_flags, vlanctl; 2268 2269 RL_LOCK_ASSERT(sc); 2270 M_ASSERTPKTHDR((*m_head)); 2271 2272 /* 2273 * With some of the RealTek chips, using the checksum offload 2274 * support in conjunction with the autopadding feature results 2275 * in the transmission of corrupt frames. For example, if we 2276 * need to send a really small IP fragment that's less than 60 2277 * bytes in size, and IP header checksumming is enabled, the 2278 * resulting ethernet frame that appears on the wire will 2279 * have garbled payload. To work around this, if TX IP checksum 2280 * offload is enabled, we always manually pad short frames out 2281 * to the minimum ethernet frame size. 2282 */ 2283 if ((sc->rl_flags & RL_FLAG_AUTOPAD) == 0 && 2284 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN && 2285 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) { 2286 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2287 if (M_WRITABLE(*m_head) == 0) { 2288 /* Get a writable copy. */ 2289 m_new = m_dup(*m_head, M_DONTWAIT); 2290 m_freem(*m_head); 2291 if (m_new == NULL) { 2292 *m_head = NULL; 2293 return (ENOBUFS); 2294 } 2295 *m_head = m_new; 2296 } 2297 if ((*m_head)->m_next != NULL || 2298 M_TRAILINGSPACE(*m_head) < padlen) { 2299 m_new = m_defrag(*m_head, M_DONTWAIT); 2300 if (m_new == NULL) { 2301 m_freem(*m_head); 2302 *m_head = NULL; 2303 return (ENOBUFS); 2304 } 2305 } else 2306 m_new = *m_head; 2307 2308 /* 2309 * Manually pad short frames, and zero the pad space 2310 * to avoid leaking data. 2311 */ 2312 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2313 m_new->m_pkthdr.len += padlen; 2314 m_new->m_len = m_new->m_pkthdr.len; 2315 *m_head = m_new; 2316 } 2317 2318 prod = sc->rl_ldata.rl_tx_prodidx; 2319 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2320 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2321 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2322 if (error == EFBIG) { 2323 m_new = m_collapse(*m_head, M_DONTWAIT, RL_NTXSEGS); 2324 if (m_new == NULL) { 2325 m_freem(*m_head); 2326 *m_head = NULL; 2327 return (ENOBUFS); 2328 } 2329 *m_head = m_new; 2330 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2331 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2332 if (error != 0) { 2333 m_freem(*m_head); 2334 *m_head = NULL; 2335 return (error); 2336 } 2337 } else if (error != 0) 2338 return (error); 2339 if (nsegs == 0) { 2340 m_freem(*m_head); 2341 *m_head = NULL; 2342 return (EIO); 2343 } 2344 2345 /* Check for number of available descriptors. */ 2346 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2347 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2348 return (ENOBUFS); 2349 } 2350 2351 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2352 BUS_DMASYNC_PREWRITE); 2353 2354 /* 2355 * Set up checksum offload. Note: checksum offload bits must 2356 * appear in all descriptors of a multi-descriptor transmit 2357 * attempt. This is according to testing done with an 8169 2358 * chip. This is a requirement. 2359 */ 2360 vlanctl = 0; 2361 csum_flags = 0; 2362 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) 2363 csum_flags = RL_TDESC_CMD_LGSEND | 2364 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2365 RL_TDESC_CMD_MSSVAL_SHIFT); 2366 else { 2367 /* 2368 * Unconditionally enable IP checksum if TCP or UDP 2369 * checksum is required. Otherwise, TCP/UDP checksum 2370 * does't make effects. 2371 */ 2372 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) { 2373 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2374 csum_flags |= RL_TDESC_CMD_IPCSUM; 2375 if (((*m_head)->m_pkthdr.csum_flags & 2376 CSUM_TCP) != 0) 2377 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2378 if (((*m_head)->m_pkthdr.csum_flags & 2379 CSUM_UDP) != 0) 2380 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2381 } else { 2382 vlanctl |= RL_TDESC_CMD_IPCSUMV2; 2383 if (((*m_head)->m_pkthdr.csum_flags & 2384 CSUM_TCP) != 0) 2385 vlanctl |= RL_TDESC_CMD_TCPCSUMV2; 2386 if (((*m_head)->m_pkthdr.csum_flags & 2387 CSUM_UDP) != 0) 2388 vlanctl |= RL_TDESC_CMD_UDPCSUMV2; 2389 } 2390 } 2391 } 2392 2393 /* 2394 * Set up hardware VLAN tagging. Note: vlan tag info must 2395 * appear in all descriptors of a multi-descriptor 2396 * transmission attempt. 2397 */ 2398 if ((*m_head)->m_flags & M_VLANTAG) 2399 vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) | 2400 RL_TDESC_VLANCTL_TAG; 2401 2402 si = prod; 2403 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2404 desc = &sc->rl_ldata.rl_tx_list[prod]; 2405 desc->rl_vlanctl = htole32(vlanctl); 2406 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2407 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2408 cmdstat = segs[i].ds_len; 2409 if (i != 0) 2410 cmdstat |= RL_TDESC_CMD_OWN; 2411 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2412 cmdstat |= RL_TDESC_CMD_EOR; 2413 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2414 sc->rl_ldata.rl_tx_free--; 2415 } 2416 /* Update producer index. */ 2417 sc->rl_ldata.rl_tx_prodidx = prod; 2418 2419 /* Set EOF on the last descriptor. */ 2420 ei = RL_TX_DESC_PRV(sc, prod); 2421 desc = &sc->rl_ldata.rl_tx_list[ei]; 2422 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2423 2424 desc = &sc->rl_ldata.rl_tx_list[si]; 2425 /* Set SOF and transfer ownership of packet to the chip. */ 2426 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2427 2428 /* 2429 * Insure that the map for this transmission 2430 * is placed at the array index of the last descriptor 2431 * in this chain. (Swap last and first dmamaps.) 2432 */ 2433 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2434 map = txd->tx_dmamap; 2435 txd->tx_dmamap = txd_last->tx_dmamap; 2436 txd_last->tx_dmamap = map; 2437 txd_last->tx_m = *m_head; 2438 2439 return (0); 2440 } 2441 2442 static void 2443 re_tx_task(void *arg, int npending) 2444 { 2445 struct ifnet *ifp; 2446 2447 ifp = arg; 2448 re_start(ifp); 2449 } 2450 2451 /* 2452 * Main transmit routine for C+ and gigE NICs. 2453 */ 2454 static void 2455 re_start(struct ifnet *ifp) 2456 { 2457 struct rl_softc *sc; 2458 struct mbuf *m_head; 2459 int queued; 2460 2461 sc = ifp->if_softc; 2462 2463 RL_LOCK(sc); 2464 2465 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2466 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) { 2467 RL_UNLOCK(sc); 2468 return; 2469 } 2470 2471 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2472 sc->rl_ldata.rl_tx_free > 1;) { 2473 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2474 if (m_head == NULL) 2475 break; 2476 2477 if (re_encap(sc, &m_head) != 0) { 2478 if (m_head == NULL) 2479 break; 2480 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2481 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2482 break; 2483 } 2484 2485 /* 2486 * If there's a BPF listener, bounce a copy of this frame 2487 * to him. 2488 */ 2489 ETHER_BPF_MTAP(ifp, m_head); 2490 2491 queued++; 2492 } 2493 2494 if (queued == 0) { 2495 #ifdef RE_TX_MODERATION 2496 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2497 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2498 #endif 2499 RL_UNLOCK(sc); 2500 return; 2501 } 2502 2503 /* Flush the TX descriptors */ 2504 2505 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2506 sc->rl_ldata.rl_tx_list_map, 2507 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2508 2509 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2510 2511 #ifdef RE_TX_MODERATION 2512 /* 2513 * Use the countdown timer for interrupt moderation. 2514 * 'TX done' interrupts are disabled. Instead, we reset the 2515 * countdown timer, which will begin counting until it hits 2516 * the value in the TIMERINT register, and then trigger an 2517 * interrupt. Each time we write to the TIMERCNT register, 2518 * the timer count is reset to 0. 2519 */ 2520 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2521 #endif 2522 2523 /* 2524 * Set a timeout in case the chip goes out to lunch. 2525 */ 2526 sc->rl_watchdog_timer = 5; 2527 2528 RL_UNLOCK(sc); 2529 } 2530 2531 static void 2532 re_init(void *xsc) 2533 { 2534 struct rl_softc *sc = xsc; 2535 2536 RL_LOCK(sc); 2537 re_init_locked(sc); 2538 RL_UNLOCK(sc); 2539 } 2540 2541 static void 2542 re_init_locked(struct rl_softc *sc) 2543 { 2544 struct ifnet *ifp = sc->rl_ifp; 2545 struct mii_data *mii; 2546 uint32_t reg; 2547 uint16_t cfg; 2548 union { 2549 uint32_t align_dummy; 2550 u_char eaddr[ETHER_ADDR_LEN]; 2551 } eaddr; 2552 2553 RL_LOCK_ASSERT(sc); 2554 2555 mii = device_get_softc(sc->rl_miibus); 2556 2557 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2558 return; 2559 2560 /* 2561 * Cancel pending I/O and free all RX/TX buffers. 2562 */ 2563 re_stop(sc); 2564 2565 /* Put controller into known state. */ 2566 re_reset(sc); 2567 2568 /* 2569 * Enable C+ RX and TX mode, as well as VLAN stripping and 2570 * RX checksum offload. We must configure the C+ register 2571 * before all others. 2572 */ 2573 cfg = RL_CPLUSCMD_PCI_MRW; 2574 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2575 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 2576 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2577 cfg |= RL_CPLUSCMD_VLANSTRIP; 2578 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) { 2579 cfg |= RL_CPLUSCMD_MACSTAT_DIS; 2580 /* XXX magic. */ 2581 cfg |= 0x0001; 2582 } else 2583 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB; 2584 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg); 2585 if (sc->rl_hwrev == RL_HWREV_8169_8110SC || 2586 sc->rl_hwrev == RL_HWREV_8169_8110SCE) { 2587 reg = 0x000fff00; 2588 if ((CSR_READ_1(sc, RL_CFG2) & RL_CFG2_PCI66MHZ) != 0) 2589 reg |= 0x000000ff; 2590 if (sc->rl_hwrev == RL_HWREV_8169_8110SCE) 2591 reg |= 0x00f00000; 2592 CSR_WRITE_4(sc, 0x7c, reg); 2593 /* Disable interrupt mitigation. */ 2594 CSR_WRITE_2(sc, 0xe2, 0); 2595 } 2596 /* 2597 * Disable TSO if interface MTU size is greater than MSS 2598 * allowed in controller. 2599 */ 2600 if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) { 2601 ifp->if_capenable &= ~IFCAP_TSO4; 2602 ifp->if_hwassist &= ~CSUM_TSO; 2603 } 2604 2605 /* 2606 * Init our MAC address. Even though the chipset 2607 * documentation doesn't mention it, we need to enter "Config 2608 * register write enable" mode to modify the ID registers. 2609 */ 2610 /* Copy MAC address on stack to align. */ 2611 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 2612 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2613 CSR_WRITE_4(sc, RL_IDR0, 2614 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 2615 CSR_WRITE_4(sc, RL_IDR4, 2616 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 2617 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2618 2619 /* 2620 * For C+ mode, initialize the RX descriptors and mbufs. 2621 */ 2622 re_rx_list_init(sc); 2623 re_tx_list_init(sc); 2624 2625 /* 2626 * Load the addresses of the RX and TX lists into the chip. 2627 */ 2628 2629 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2630 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2631 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2632 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2633 2634 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2635 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2636 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2637 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2638 2639 /* 2640 * Enable transmit and receive. 2641 */ 2642 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2643 2644 /* 2645 * Set the initial TX configuration. 2646 */ 2647 if (sc->rl_testmode) { 2648 if (sc->rl_type == RL_8169) 2649 CSR_WRITE_4(sc, RL_TXCFG, 2650 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2651 else 2652 CSR_WRITE_4(sc, RL_TXCFG, 2653 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2654 } else 2655 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2656 2657 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2658 2659 /* 2660 * Set the initial RX configuration. 2661 */ 2662 re_set_rxmode(sc); 2663 2664 #ifdef DEVICE_POLLING 2665 /* 2666 * Disable interrupts if we are polling. 2667 */ 2668 if (ifp->if_capenable & IFCAP_POLLING) 2669 CSR_WRITE_2(sc, RL_IMR, 0); 2670 else /* otherwise ... */ 2671 #endif 2672 2673 /* 2674 * Enable interrupts. 2675 */ 2676 if (sc->rl_testmode) 2677 CSR_WRITE_2(sc, RL_IMR, 0); 2678 else 2679 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2680 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 2681 2682 /* Set initial TX threshold */ 2683 sc->rl_txthresh = RL_TX_THRESH_INIT; 2684 2685 /* Start RX/TX process. */ 2686 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2687 #ifdef notdef 2688 /* Enable receiver and transmitter. */ 2689 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2690 #endif 2691 2692 #ifdef RE_TX_MODERATION 2693 /* 2694 * Initialize the timer interrupt register so that 2695 * a timer interrupt will be generated once the timer 2696 * reaches a certain number of ticks. The timer is 2697 * reloaded on each transmit. This gives us TX interrupt 2698 * moderation, which dramatically improves TX frame rate. 2699 */ 2700 if (sc->rl_type == RL_8169) 2701 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2702 else 2703 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2704 #endif 2705 2706 /* 2707 * For 8169 gigE NICs, set the max allowed RX packet 2708 * size so we can receive jumbo frames. 2709 */ 2710 if (sc->rl_type == RL_8169) 2711 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2712 2713 if (sc->rl_testmode) 2714 return; 2715 2716 mii_mediachg(mii); 2717 2718 CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD); 2719 2720 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2721 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2722 2723 sc->rl_flags &= ~RL_FLAG_LINK; 2724 sc->rl_watchdog_timer = 0; 2725 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2726 } 2727 2728 /* 2729 * Set media options. 2730 */ 2731 static int 2732 re_ifmedia_upd(struct ifnet *ifp) 2733 { 2734 struct rl_softc *sc; 2735 struct mii_data *mii; 2736 int error; 2737 2738 sc = ifp->if_softc; 2739 mii = device_get_softc(sc->rl_miibus); 2740 RL_LOCK(sc); 2741 error = mii_mediachg(mii); 2742 RL_UNLOCK(sc); 2743 2744 return (error); 2745 } 2746 2747 /* 2748 * Report current media status. 2749 */ 2750 static void 2751 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2752 { 2753 struct rl_softc *sc; 2754 struct mii_data *mii; 2755 2756 sc = ifp->if_softc; 2757 mii = device_get_softc(sc->rl_miibus); 2758 2759 RL_LOCK(sc); 2760 mii_pollstat(mii); 2761 RL_UNLOCK(sc); 2762 ifmr->ifm_active = mii->mii_media_active; 2763 ifmr->ifm_status = mii->mii_media_status; 2764 } 2765 2766 static int 2767 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2768 { 2769 struct rl_softc *sc = ifp->if_softc; 2770 struct ifreq *ifr = (struct ifreq *) data; 2771 struct mii_data *mii; 2772 int error = 0; 2773 2774 switch (command) { 2775 case SIOCSIFMTU: 2776 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > RL_JUMBO_MTU) { 2777 error = EINVAL; 2778 break; 2779 } 2780 if ((sc->rl_flags & RL_FLAG_NOJUMBO) != 0 && 2781 ifr->ifr_mtu > RL_MAX_FRAMELEN) { 2782 error = EINVAL; 2783 break; 2784 } 2785 RL_LOCK(sc); 2786 if (ifp->if_mtu != ifr->ifr_mtu) 2787 ifp->if_mtu = ifr->ifr_mtu; 2788 if (ifp->if_mtu > RL_TSO_MTU && 2789 (ifp->if_capenable & IFCAP_TSO4) != 0) { 2790 ifp->if_capenable &= ~IFCAP_TSO4; 2791 ifp->if_hwassist &= ~CSUM_TSO; 2792 VLAN_CAPABILITIES(ifp); 2793 } 2794 RL_UNLOCK(sc); 2795 break; 2796 case SIOCSIFFLAGS: 2797 RL_LOCK(sc); 2798 if ((ifp->if_flags & IFF_UP) != 0) { 2799 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2800 if (((ifp->if_flags ^ sc->rl_if_flags) 2801 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2802 re_set_rxmode(sc); 2803 } else 2804 re_init_locked(sc); 2805 } else { 2806 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2807 re_stop(sc); 2808 } 2809 sc->rl_if_flags = ifp->if_flags; 2810 RL_UNLOCK(sc); 2811 break; 2812 case SIOCADDMULTI: 2813 case SIOCDELMULTI: 2814 RL_LOCK(sc); 2815 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2816 re_set_rxmode(sc); 2817 RL_UNLOCK(sc); 2818 break; 2819 case SIOCGIFMEDIA: 2820 case SIOCSIFMEDIA: 2821 mii = device_get_softc(sc->rl_miibus); 2822 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2823 break; 2824 case SIOCSIFCAP: 2825 { 2826 int mask, reinit; 2827 2828 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2829 reinit = 0; 2830 #ifdef DEVICE_POLLING 2831 if (mask & IFCAP_POLLING) { 2832 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2833 error = ether_poll_register(re_poll, ifp); 2834 if (error) 2835 return(error); 2836 RL_LOCK(sc); 2837 /* Disable interrupts */ 2838 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2839 ifp->if_capenable |= IFCAP_POLLING; 2840 RL_UNLOCK(sc); 2841 } else { 2842 error = ether_poll_deregister(ifp); 2843 /* Enable interrupts. */ 2844 RL_LOCK(sc); 2845 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2846 ifp->if_capenable &= ~IFCAP_POLLING; 2847 RL_UNLOCK(sc); 2848 } 2849 } 2850 #endif /* DEVICE_POLLING */ 2851 if (mask & IFCAP_HWCSUM) { 2852 ifp->if_capenable ^= IFCAP_HWCSUM; 2853 if (ifp->if_capenable & IFCAP_TXCSUM) 2854 ifp->if_hwassist |= RE_CSUM_FEATURES; 2855 else 2856 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 2857 reinit = 1; 2858 } 2859 if ((mask & IFCAP_TSO4) != 0 && 2860 (ifp->if_capabilities & IFCAP_TSO) != 0) { 2861 ifp->if_capenable ^= IFCAP_TSO4; 2862 if ((IFCAP_TSO4 & ifp->if_capenable) != 0) 2863 ifp->if_hwassist |= CSUM_TSO; 2864 else 2865 ifp->if_hwassist &= ~CSUM_TSO; 2866 if (ifp->if_mtu > RL_TSO_MTU && 2867 (ifp->if_capenable & IFCAP_TSO4) != 0) { 2868 ifp->if_capenable &= ~IFCAP_TSO4; 2869 ifp->if_hwassist &= ~CSUM_TSO; 2870 } 2871 } 2872 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2873 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 2874 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 2875 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2876 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2877 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2878 /* TSO over VLAN requires VLAN hardware tagging. */ 2879 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 2880 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 2881 reinit = 1; 2882 } 2883 if ((mask & IFCAP_WOL) != 0 && 2884 (ifp->if_capabilities & IFCAP_WOL) != 0) { 2885 if ((mask & IFCAP_WOL_UCAST) != 0) 2886 ifp->if_capenable ^= IFCAP_WOL_UCAST; 2887 if ((mask & IFCAP_WOL_MCAST) != 0) 2888 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2889 if ((mask & IFCAP_WOL_MAGIC) != 0) 2890 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2891 } 2892 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) { 2893 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2894 re_init(sc); 2895 } 2896 VLAN_CAPABILITIES(ifp); 2897 } 2898 break; 2899 default: 2900 error = ether_ioctl(ifp, command, data); 2901 break; 2902 } 2903 2904 return (error); 2905 } 2906 2907 static void 2908 re_watchdog(struct rl_softc *sc) 2909 { 2910 struct ifnet *ifp; 2911 2912 RL_LOCK_ASSERT(sc); 2913 2914 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 2915 return; 2916 2917 ifp = sc->rl_ifp; 2918 re_txeof(sc); 2919 if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) { 2920 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 2921 "-- recovering\n"); 2922 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2923 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2924 return; 2925 } 2926 2927 if_printf(ifp, "watchdog timeout\n"); 2928 ifp->if_oerrors++; 2929 2930 re_rxeof(sc, NULL); 2931 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2932 re_init_locked(sc); 2933 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2934 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2935 } 2936 2937 /* 2938 * Stop the adapter and free any mbufs allocated to the 2939 * RX and TX lists. 2940 */ 2941 static void 2942 re_stop(struct rl_softc *sc) 2943 { 2944 int i; 2945 struct ifnet *ifp; 2946 struct rl_txdesc *txd; 2947 struct rl_rxdesc *rxd; 2948 2949 RL_LOCK_ASSERT(sc); 2950 2951 ifp = sc->rl_ifp; 2952 2953 sc->rl_watchdog_timer = 0; 2954 callout_stop(&sc->rl_stat_callout); 2955 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2956 2957 if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0) 2958 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB | 2959 RL_CMD_RX_ENB); 2960 else 2961 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2962 DELAY(1000); 2963 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2964 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 2965 2966 if (sc->rl_head != NULL) { 2967 m_freem(sc->rl_head); 2968 sc->rl_head = sc->rl_tail = NULL; 2969 } 2970 2971 /* Free the TX list buffers. */ 2972 2973 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 2974 txd = &sc->rl_ldata.rl_tx_desc[i]; 2975 if (txd->tx_m != NULL) { 2976 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2977 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2978 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2979 txd->tx_dmamap); 2980 m_freem(txd->tx_m); 2981 txd->tx_m = NULL; 2982 } 2983 } 2984 2985 /* Free the RX list buffers. */ 2986 2987 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2988 rxd = &sc->rl_ldata.rl_rx_desc[i]; 2989 if (rxd->rx_m != NULL) { 2990 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2991 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2992 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 2993 rxd->rx_dmamap); 2994 m_freem(rxd->rx_m); 2995 rxd->rx_m = NULL; 2996 } 2997 } 2998 } 2999 3000 /* 3001 * Device suspend routine. Stop the interface and save some PCI 3002 * settings in case the BIOS doesn't restore them properly on 3003 * resume. 3004 */ 3005 static int 3006 re_suspend(device_t dev) 3007 { 3008 struct rl_softc *sc; 3009 3010 sc = device_get_softc(dev); 3011 3012 RL_LOCK(sc); 3013 re_stop(sc); 3014 re_setwol(sc); 3015 sc->suspended = 1; 3016 RL_UNLOCK(sc); 3017 3018 return (0); 3019 } 3020 3021 /* 3022 * Device resume routine. Restore some PCI settings in case the BIOS 3023 * doesn't, re-enable busmastering, and restart the interface if 3024 * appropriate. 3025 */ 3026 static int 3027 re_resume(device_t dev) 3028 { 3029 struct rl_softc *sc; 3030 struct ifnet *ifp; 3031 3032 sc = device_get_softc(dev); 3033 3034 RL_LOCK(sc); 3035 3036 ifp = sc->rl_ifp; 3037 /* Take controller out of sleep mode. */ 3038 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3039 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3040 CSR_WRITE_1(sc, RL_GPIO, 3041 CSR_READ_1(sc, RL_GPIO) | 0x01); 3042 } 3043 3044 /* 3045 * Clear WOL matching such that normal Rx filtering 3046 * wouldn't interfere with WOL patterns. 3047 */ 3048 re_clrwol(sc); 3049 3050 /* reinitialize interface if necessary */ 3051 if (ifp->if_flags & IFF_UP) 3052 re_init_locked(sc); 3053 3054 sc->suspended = 0; 3055 RL_UNLOCK(sc); 3056 3057 return (0); 3058 } 3059 3060 /* 3061 * Stop all chip I/O so that the kernel's probe routines don't 3062 * get confused by errant DMAs when rebooting. 3063 */ 3064 static int 3065 re_shutdown(device_t dev) 3066 { 3067 struct rl_softc *sc; 3068 3069 sc = device_get_softc(dev); 3070 3071 RL_LOCK(sc); 3072 re_stop(sc); 3073 /* 3074 * Mark interface as down since otherwise we will panic if 3075 * interrupt comes in later on, which can happen in some 3076 * cases. 3077 */ 3078 sc->rl_ifp->if_flags &= ~IFF_UP; 3079 re_setwol(sc); 3080 RL_UNLOCK(sc); 3081 3082 return (0); 3083 } 3084 3085 static void 3086 re_setwol(struct rl_softc *sc) 3087 { 3088 struct ifnet *ifp; 3089 int pmc; 3090 uint16_t pmstat; 3091 uint8_t v; 3092 3093 RL_LOCK_ASSERT(sc); 3094 3095 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3096 return; 3097 3098 ifp = sc->rl_ifp; 3099 /* Put controller into sleep mode. */ 3100 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3101 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3102 CSR_WRITE_1(sc, RL_GPIO, 3103 CSR_READ_1(sc, RL_GPIO) & ~0x01); 3104 } 3105 if ((ifp->if_capenable & IFCAP_WOL) != 0 && 3106 (sc->rl_flags & RL_FLAG_WOLRXENB) != 0) 3107 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB); 3108 /* Enable config register write. */ 3109 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3110 3111 /* Enable PME. */ 3112 v = CSR_READ_1(sc, RL_CFG1); 3113 v &= ~RL_CFG1_PME; 3114 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3115 v |= RL_CFG1_PME; 3116 CSR_WRITE_1(sc, RL_CFG1, v); 3117 3118 v = CSR_READ_1(sc, RL_CFG3); 3119 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3120 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3121 v |= RL_CFG3_WOL_MAGIC; 3122 CSR_WRITE_1(sc, RL_CFG3, v); 3123 3124 /* Config register write done. */ 3125 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3126 3127 v = CSR_READ_1(sc, RL_CFG5); 3128 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3129 v &= ~RL_CFG5_WOL_LANWAKE; 3130 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 3131 v |= RL_CFG5_WOL_UCAST; 3132 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 3133 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 3134 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3135 v |= RL_CFG5_WOL_LANWAKE; 3136 CSR_WRITE_1(sc, RL_CFG5, v); 3137 3138 /* 3139 * It seems that hardware resets its link speed to 100Mbps in 3140 * power down mode so switching to 100Mbps in driver is not 3141 * needed. 3142 */ 3143 3144 /* Request PME if WOL is requested. */ 3145 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 3146 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3147 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3148 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3149 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 3150 } 3151 3152 static void 3153 re_clrwol(struct rl_softc *sc) 3154 { 3155 int pmc; 3156 uint8_t v; 3157 3158 RL_LOCK_ASSERT(sc); 3159 3160 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3161 return; 3162 3163 /* Enable config register write. */ 3164 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3165 3166 v = CSR_READ_1(sc, RL_CFG3); 3167 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3168 CSR_WRITE_1(sc, RL_CFG3, v); 3169 3170 /* Config register write done. */ 3171 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3172 3173 v = CSR_READ_1(sc, RL_CFG5); 3174 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3175 v &= ~RL_CFG5_WOL_LANWAKE; 3176 CSR_WRITE_1(sc, RL_CFG5, v); 3177 } 3178