1 /*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44 /* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111 #ifdef HAVE_KERNEL_OPTION_HEADERS 112 #include "opt_device_polling.h" 113 #endif 114 115 #include <sys/param.h> 116 #include <sys/endian.h> 117 #include <sys/systm.h> 118 #include <sys/sockio.h> 119 #include <sys/mbuf.h> 120 #include <sys/malloc.h> 121 #include <sys/module.h> 122 #include <sys/kernel.h> 123 #include <sys/socket.h> 124 #include <sys/lock.h> 125 #include <sys/mutex.h> 126 #include <sys/taskqueue.h> 127 128 #include <net/if.h> 129 #include <net/if_arp.h> 130 #include <net/ethernet.h> 131 #include <net/if_dl.h> 132 #include <net/if_media.h> 133 #include <net/if_types.h> 134 #include <net/if_vlan_var.h> 135 136 #include <net/bpf.h> 137 138 #include <machine/bus.h> 139 #include <machine/resource.h> 140 #include <sys/bus.h> 141 #include <sys/rman.h> 142 143 #include <dev/mii/mii.h> 144 #include <dev/mii/miivar.h> 145 146 #include <dev/pci/pcireg.h> 147 #include <dev/pci/pcivar.h> 148 149 #include <pci/if_rlreg.h> 150 151 MODULE_DEPEND(re, pci, 1, 1, 1); 152 MODULE_DEPEND(re, ether, 1, 1, 1); 153 MODULE_DEPEND(re, miibus, 1, 1, 1); 154 155 /* "device miibus" required. See GENERIC if you get errors here. */ 156 #include "miibus_if.h" 157 158 /* 159 * Default to using PIO access for this driver. 160 */ 161 #define RE_USEIOSPACE 162 163 /* Tunables. */ 164 static int msi_disable = 0; 165 TUNABLE_INT("hw.re.msi_disable", &msi_disable); 166 167 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 168 169 /* 170 * Various supported device vendors/types and their names. 171 */ 172 static struct rl_type re_devs[] = { 173 { DLINK_VENDORID, DLINK_DEVICEID_528T, RL_HWREV_8169S, 174 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 175 { DLINK_VENDORID, DLINK_DEVICEID_528T, RL_HWREV_8169_8110SB, 176 "D-Link DGE-528(T) Rev.B1 Gigabit Ethernet Adapter" }, 177 { RT_VENDORID, RT_DEVICEID_8139, RL_HWREV_8139CPLUS, 178 "RealTek 8139C+ 10/100BaseTX" }, 179 { RT_VENDORID, RT_DEVICEID_8101E, RL_HWREV_8101E, 180 "RealTek 8101E PCIe 10/100baseTX" }, 181 { RT_VENDORID, RT_DEVICEID_8168, RL_HWREV_8168_SPIN1, 182 "RealTek 8168/8111B PCIe Gigabit Ethernet" }, 183 { RT_VENDORID, RT_DEVICEID_8168, RL_HWREV_8168_SPIN2, 184 "RealTek 8168/8111B PCIe Gigabit Ethernet" }, 185 { RT_VENDORID, RT_DEVICEID_8168, RL_HWREV_8168_SPIN3, 186 "RealTek 8168/8111B PCIe Gigabit Ethernet" }, 187 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169, 188 "RealTek 8169 Gigabit Ethernet" }, 189 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169S, 190 "RealTek 8169S Single-chip Gigabit Ethernet" }, 191 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169_8110SB, 192 "RealTek 8169SB/8110SB Single-chip Gigabit Ethernet" }, 193 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169_8110SC, 194 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 195 { RT_VENDORID, RT_DEVICEID_8169SC, RL_HWREV_8169_8110SC, 196 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 197 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8110S, 198 "RealTek 8110S Single-chip Gigabit Ethernet" }, 199 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, RL_HWREV_8169S, 200 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 201 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, RL_HWREV_8169S, 202 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 203 { USR_VENDORID, USR_DEVICEID_997902, RL_HWREV_8169S, 204 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" }, 205 { 0, 0, 0, NULL } 206 }; 207 208 static struct rl_hwrev re_hwrevs[] = { 209 { RL_HWREV_8139, RL_8139, "" }, 210 { RL_HWREV_8139A, RL_8139, "A" }, 211 { RL_HWREV_8139AG, RL_8139, "A-G" }, 212 { RL_HWREV_8139B, RL_8139, "B" }, 213 { RL_HWREV_8130, RL_8139, "8130" }, 214 { RL_HWREV_8139C, RL_8139, "C" }, 215 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 216 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 217 { RL_HWREV_8168_SPIN1, RL_8169, "8168"}, 218 { RL_HWREV_8169, RL_8169, "8169"}, 219 { RL_HWREV_8169S, RL_8169, "8169S"}, 220 { RL_HWREV_8110S, RL_8169, "8110S"}, 221 { RL_HWREV_8169_8110SB, RL_8169, "8169SB"}, 222 { RL_HWREV_8169_8110SC, RL_8169, "8169SC"}, 223 { RL_HWREV_8100, RL_8139, "8100"}, 224 { RL_HWREV_8101, RL_8139, "8101"}, 225 { RL_HWREV_8100E, RL_8169, "8100E"}, 226 { RL_HWREV_8101E, RL_8169, "8101E"}, 227 { RL_HWREV_8168_SPIN2, RL_8169, "8168"}, 228 { RL_HWREV_8168_SPIN3, RL_8169, "8168"}, 229 { 0, 0, NULL } 230 }; 231 232 static int re_probe (device_t); 233 static int re_attach (device_t); 234 static int re_detach (device_t); 235 236 static struct mbuf *re_defrag (struct mbuf *, int, int); 237 static int re_encap (struct rl_softc *, struct mbuf **); 238 239 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 240 static int re_allocmem (device_t, struct rl_softc *); 241 static __inline void re_discard_rxbuf 242 (struct rl_softc *, int); 243 static int re_newbuf (struct rl_softc *, int); 244 static int re_rx_list_init (struct rl_softc *); 245 static int re_tx_list_init (struct rl_softc *); 246 #ifdef RE_FIXUP_RX 247 static __inline void re_fixup_rx 248 (struct mbuf *); 249 #endif 250 static int re_rxeof (struct rl_softc *); 251 static void re_txeof (struct rl_softc *); 252 #ifdef DEVICE_POLLING 253 static void re_poll (struct ifnet *, enum poll_cmd, int); 254 static void re_poll_locked (struct ifnet *, enum poll_cmd, int); 255 #endif 256 static int re_intr (void *); 257 static void re_tick (void *); 258 static void re_tx_task (void *, int); 259 static void re_int_task (void *, int); 260 static void re_start (struct ifnet *); 261 static int re_ioctl (struct ifnet *, u_long, caddr_t); 262 static void re_init (void *); 263 static void re_init_locked (struct rl_softc *); 264 static void re_stop (struct rl_softc *); 265 static void re_watchdog (struct rl_softc *); 266 static int re_suspend (device_t); 267 static int re_resume (device_t); 268 static int re_shutdown (device_t); 269 static int re_ifmedia_upd (struct ifnet *); 270 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 271 272 static void re_eeprom_putbyte (struct rl_softc *, int); 273 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 274 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 275 static int re_gmii_readreg (device_t, int, int); 276 static int re_gmii_writereg (device_t, int, int, int); 277 278 static int re_miibus_readreg (device_t, int, int); 279 static int re_miibus_writereg (device_t, int, int, int); 280 static void re_miibus_statchg (device_t); 281 282 static void re_setmulti (struct rl_softc *); 283 static void re_reset (struct rl_softc *); 284 285 #ifdef RE_DIAG 286 static int re_diag (struct rl_softc *); 287 #endif 288 289 #ifdef RE_USEIOSPACE 290 #define RL_RES SYS_RES_IOPORT 291 #define RL_RID RL_PCI_LOIO 292 #else 293 #define RL_RES SYS_RES_MEMORY 294 #define RL_RID RL_PCI_LOMEM 295 #endif 296 297 static device_method_t re_methods[] = { 298 /* Device interface */ 299 DEVMETHOD(device_probe, re_probe), 300 DEVMETHOD(device_attach, re_attach), 301 DEVMETHOD(device_detach, re_detach), 302 DEVMETHOD(device_suspend, re_suspend), 303 DEVMETHOD(device_resume, re_resume), 304 DEVMETHOD(device_shutdown, re_shutdown), 305 306 /* bus interface */ 307 DEVMETHOD(bus_print_child, bus_generic_print_child), 308 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 309 310 /* MII interface */ 311 DEVMETHOD(miibus_readreg, re_miibus_readreg), 312 DEVMETHOD(miibus_writereg, re_miibus_writereg), 313 DEVMETHOD(miibus_statchg, re_miibus_statchg), 314 315 { 0, 0 } 316 }; 317 318 static driver_t re_driver = { 319 "re", 320 re_methods, 321 sizeof(struct rl_softc) 322 }; 323 324 static devclass_t re_devclass; 325 326 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 327 DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0); 328 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 329 330 #define EE_SET(x) \ 331 CSR_WRITE_1(sc, RL_EECMD, \ 332 CSR_READ_1(sc, RL_EECMD) | x) 333 334 #define EE_CLR(x) \ 335 CSR_WRITE_1(sc, RL_EECMD, \ 336 CSR_READ_1(sc, RL_EECMD) & ~x) 337 338 /* 339 * Send a read command and address to the EEPROM, check for ACK. 340 */ 341 static void 342 re_eeprom_putbyte(sc, addr) 343 struct rl_softc *sc; 344 int addr; 345 { 346 register int d, i; 347 348 d = addr | (RL_9346_READ << sc->rl_eewidth); 349 350 /* 351 * Feed in each bit and strobe the clock. 352 */ 353 354 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 355 if (d & i) { 356 EE_SET(RL_EE_DATAIN); 357 } else { 358 EE_CLR(RL_EE_DATAIN); 359 } 360 DELAY(100); 361 EE_SET(RL_EE_CLK); 362 DELAY(150); 363 EE_CLR(RL_EE_CLK); 364 DELAY(100); 365 } 366 367 return; 368 } 369 370 /* 371 * Read a word of data stored in the EEPROM at address 'addr.' 372 */ 373 static void 374 re_eeprom_getword(sc, addr, dest) 375 struct rl_softc *sc; 376 int addr; 377 u_int16_t *dest; 378 { 379 register int i; 380 u_int16_t word = 0; 381 382 /* 383 * Send address of word we want to read. 384 */ 385 re_eeprom_putbyte(sc, addr); 386 387 /* 388 * Start reading bits from EEPROM. 389 */ 390 for (i = 0x8000; i; i >>= 1) { 391 EE_SET(RL_EE_CLK); 392 DELAY(100); 393 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 394 word |= i; 395 EE_CLR(RL_EE_CLK); 396 DELAY(100); 397 } 398 399 *dest = word; 400 401 return; 402 } 403 404 /* 405 * Read a sequence of words from the EEPROM. 406 */ 407 static void 408 re_read_eeprom(sc, dest, off, cnt) 409 struct rl_softc *sc; 410 caddr_t dest; 411 int off; 412 int cnt; 413 { 414 int i; 415 u_int16_t word = 0, *ptr; 416 417 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 418 419 DELAY(100); 420 421 for (i = 0; i < cnt; i++) { 422 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 423 re_eeprom_getword(sc, off + i, &word); 424 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 425 ptr = (u_int16_t *)(dest + (i * 2)); 426 *ptr = word; 427 } 428 429 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 430 431 return; 432 } 433 434 static int 435 re_gmii_readreg(dev, phy, reg) 436 device_t dev; 437 int phy, reg; 438 { 439 struct rl_softc *sc; 440 u_int32_t rval; 441 int i; 442 443 if (phy != 1) 444 return (0); 445 446 sc = device_get_softc(dev); 447 448 /* Let the rgephy driver read the GMEDIASTAT register */ 449 450 if (reg == RL_GMEDIASTAT) { 451 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 452 return (rval); 453 } 454 455 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 456 DELAY(1000); 457 458 for (i = 0; i < RL_TIMEOUT; i++) { 459 rval = CSR_READ_4(sc, RL_PHYAR); 460 if (rval & RL_PHYAR_BUSY) 461 break; 462 DELAY(100); 463 } 464 465 if (i == RL_TIMEOUT) { 466 device_printf(sc->rl_dev, "PHY read failed\n"); 467 return (0); 468 } 469 470 return (rval & RL_PHYAR_PHYDATA); 471 } 472 473 static int 474 re_gmii_writereg(dev, phy, reg, data) 475 device_t dev; 476 int phy, reg, data; 477 { 478 struct rl_softc *sc; 479 u_int32_t rval; 480 int i; 481 482 sc = device_get_softc(dev); 483 484 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 485 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 486 DELAY(1000); 487 488 for (i = 0; i < RL_TIMEOUT; i++) { 489 rval = CSR_READ_4(sc, RL_PHYAR); 490 if (!(rval & RL_PHYAR_BUSY)) 491 break; 492 DELAY(100); 493 } 494 495 if (i == RL_TIMEOUT) { 496 device_printf(sc->rl_dev, "PHY write failed\n"); 497 return (0); 498 } 499 500 return (0); 501 } 502 503 static int 504 re_miibus_readreg(dev, phy, reg) 505 device_t dev; 506 int phy, reg; 507 { 508 struct rl_softc *sc; 509 u_int16_t rval = 0; 510 u_int16_t re8139_reg = 0; 511 512 sc = device_get_softc(dev); 513 514 if (sc->rl_type == RL_8169) { 515 rval = re_gmii_readreg(dev, phy, reg); 516 return (rval); 517 } 518 519 /* Pretend the internal PHY is only at address 0 */ 520 if (phy) { 521 return (0); 522 } 523 switch (reg) { 524 case MII_BMCR: 525 re8139_reg = RL_BMCR; 526 break; 527 case MII_BMSR: 528 re8139_reg = RL_BMSR; 529 break; 530 case MII_ANAR: 531 re8139_reg = RL_ANAR; 532 break; 533 case MII_ANER: 534 re8139_reg = RL_ANER; 535 break; 536 case MII_ANLPAR: 537 re8139_reg = RL_LPAR; 538 break; 539 case MII_PHYIDR1: 540 case MII_PHYIDR2: 541 return (0); 542 /* 543 * Allow the rlphy driver to read the media status 544 * register. If we have a link partner which does not 545 * support NWAY, this is the register which will tell 546 * us the results of parallel detection. 547 */ 548 case RL_MEDIASTAT: 549 rval = CSR_READ_1(sc, RL_MEDIASTAT); 550 return (rval); 551 default: 552 device_printf(sc->rl_dev, "bad phy register\n"); 553 return (0); 554 } 555 rval = CSR_READ_2(sc, re8139_reg); 556 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 557 /* 8139C+ has different bit layout. */ 558 rval &= ~(BMCR_LOOP | BMCR_ISO); 559 } 560 return (rval); 561 } 562 563 static int 564 re_miibus_writereg(dev, phy, reg, data) 565 device_t dev; 566 int phy, reg, data; 567 { 568 struct rl_softc *sc; 569 u_int16_t re8139_reg = 0; 570 int rval = 0; 571 572 sc = device_get_softc(dev); 573 574 if (sc->rl_type == RL_8169) { 575 rval = re_gmii_writereg(dev, phy, reg, data); 576 return (rval); 577 } 578 579 /* Pretend the internal PHY is only at address 0 */ 580 if (phy) 581 return (0); 582 583 switch (reg) { 584 case MII_BMCR: 585 re8139_reg = RL_BMCR; 586 if (sc->rl_type == RL_8139CPLUS) { 587 /* 8139C+ has different bit layout. */ 588 data &= ~(BMCR_LOOP | BMCR_ISO); 589 } 590 break; 591 case MII_BMSR: 592 re8139_reg = RL_BMSR; 593 break; 594 case MII_ANAR: 595 re8139_reg = RL_ANAR; 596 break; 597 case MII_ANER: 598 re8139_reg = RL_ANER; 599 break; 600 case MII_ANLPAR: 601 re8139_reg = RL_LPAR; 602 break; 603 case MII_PHYIDR1: 604 case MII_PHYIDR2: 605 return (0); 606 break; 607 default: 608 device_printf(sc->rl_dev, "bad phy register\n"); 609 return (0); 610 } 611 CSR_WRITE_2(sc, re8139_reg, data); 612 return (0); 613 } 614 615 static void 616 re_miibus_statchg(dev) 617 device_t dev; 618 { 619 620 } 621 622 /* 623 * Program the 64-bit multicast hash filter. 624 */ 625 static void 626 re_setmulti(sc) 627 struct rl_softc *sc; 628 { 629 struct ifnet *ifp; 630 int h = 0; 631 u_int32_t hashes[2] = { 0, 0 }; 632 struct ifmultiaddr *ifma; 633 u_int32_t rxfilt; 634 int mcnt = 0; 635 u_int32_t hwrev; 636 637 RL_LOCK_ASSERT(sc); 638 639 ifp = sc->rl_ifp; 640 641 642 rxfilt = CSR_READ_4(sc, RL_RXCFG); 643 rxfilt &= ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_MULTI); 644 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 645 if (ifp->if_flags & IFF_PROMISC) 646 rxfilt |= RL_RXCFG_RX_ALLPHYS; 647 /* 648 * Unlike other hardwares, we have to explicitly set 649 * RL_RXCFG_RX_MULTI to receive multicast frames in 650 * promiscuous mode. 651 */ 652 rxfilt |= RL_RXCFG_RX_MULTI; 653 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 654 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 655 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 656 return; 657 } 658 659 /* first, zot all the existing hash bits */ 660 CSR_WRITE_4(sc, RL_MAR0, 0); 661 CSR_WRITE_4(sc, RL_MAR4, 0); 662 663 /* now program new ones */ 664 IF_ADDR_LOCK(ifp); 665 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 666 if (ifma->ifma_addr->sa_family != AF_LINK) 667 continue; 668 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 669 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 670 if (h < 32) 671 hashes[0] |= (1 << h); 672 else 673 hashes[1] |= (1 << (h - 32)); 674 mcnt++; 675 } 676 IF_ADDR_UNLOCK(ifp); 677 678 if (mcnt) 679 rxfilt |= RL_RXCFG_RX_MULTI; 680 else 681 rxfilt &= ~RL_RXCFG_RX_MULTI; 682 683 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 684 685 /* 686 * For some unfathomable reason, RealTek decided to reverse 687 * the order of the multicast hash registers in the PCI Express 688 * parts. This means we have to write the hash pattern in reverse 689 * order for those devices. 690 */ 691 692 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 693 694 switch (hwrev) { 695 case RL_HWREV_8100E: 696 case RL_HWREV_8101E: 697 case RL_HWREV_8168_SPIN1: 698 case RL_HWREV_8168_SPIN2: 699 case RL_HWREV_8168_SPIN3: 700 CSR_WRITE_4(sc, RL_MAR0, bswap32(hashes[1])); 701 CSR_WRITE_4(sc, RL_MAR4, bswap32(hashes[0])); 702 break; 703 default: 704 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 705 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 706 break; 707 } 708 } 709 710 static void 711 re_reset(sc) 712 struct rl_softc *sc; 713 { 714 register int i; 715 716 RL_LOCK_ASSERT(sc); 717 718 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 719 720 for (i = 0; i < RL_TIMEOUT; i++) { 721 DELAY(10); 722 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 723 break; 724 } 725 if (i == RL_TIMEOUT) 726 device_printf(sc->rl_dev, "reset never completed!\n"); 727 728 CSR_WRITE_1(sc, 0x82, 1); 729 } 730 731 #ifdef RE_DIAG 732 733 /* 734 * The following routine is designed to test for a defect on some 735 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 736 * lines connected to the bus, however for a 32-bit only card, they 737 * should be pulled high. The result of this defect is that the 738 * NIC will not work right if you plug it into a 64-bit slot: DMA 739 * operations will be done with 64-bit transfers, which will fail 740 * because the 64-bit data lines aren't connected. 741 * 742 * There's no way to work around this (short of talking a soldering 743 * iron to the board), however we can detect it. The method we use 744 * here is to put the NIC into digital loopback mode, set the receiver 745 * to promiscuous mode, and then try to send a frame. We then compare 746 * the frame data we sent to what was received. If the data matches, 747 * then the NIC is working correctly, otherwise we know the user has 748 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 749 * slot. In the latter case, there's no way the NIC can work correctly, 750 * so we print out a message on the console and abort the device attach. 751 */ 752 753 static int 754 re_diag(sc) 755 struct rl_softc *sc; 756 { 757 struct ifnet *ifp = sc->rl_ifp; 758 struct mbuf *m0; 759 struct ether_header *eh; 760 struct rl_desc *cur_rx; 761 u_int16_t status; 762 u_int32_t rxstat; 763 int total_len, i, error = 0, phyaddr; 764 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 765 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 766 767 /* Allocate a single mbuf */ 768 MGETHDR(m0, M_DONTWAIT, MT_DATA); 769 if (m0 == NULL) 770 return (ENOBUFS); 771 772 RL_LOCK(sc); 773 774 /* 775 * Initialize the NIC in test mode. This sets the chip up 776 * so that it can send and receive frames, but performs the 777 * following special functions: 778 * - Puts receiver in promiscuous mode 779 * - Enables digital loopback mode 780 * - Leaves interrupts turned off 781 */ 782 783 ifp->if_flags |= IFF_PROMISC; 784 sc->rl_testmode = 1; 785 re_reset(sc); 786 re_init_locked(sc); 787 sc->rl_link = 1; 788 if (sc->rl_type == RL_8169) 789 phyaddr = 1; 790 else 791 phyaddr = 0; 792 793 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 794 for (i = 0; i < RL_TIMEOUT; i++) { 795 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 796 if (!(status & BMCR_RESET)) 797 break; 798 } 799 800 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 801 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 802 803 DELAY(100000); 804 805 /* Put some data in the mbuf */ 806 807 eh = mtod(m0, struct ether_header *); 808 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 809 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 810 eh->ether_type = htons(ETHERTYPE_IP); 811 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 812 813 /* 814 * Queue the packet, start transmission. 815 * Note: IF_HANDOFF() ultimately calls re_start() for us. 816 */ 817 818 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 819 RL_UNLOCK(sc); 820 /* XXX: re_diag must not be called when in ALTQ mode */ 821 IF_HANDOFF(&ifp->if_snd, m0, ifp); 822 RL_LOCK(sc); 823 m0 = NULL; 824 825 /* Wait for it to propagate through the chip */ 826 827 DELAY(100000); 828 for (i = 0; i < RL_TIMEOUT; i++) { 829 status = CSR_READ_2(sc, RL_ISR); 830 CSR_WRITE_2(sc, RL_ISR, status); 831 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 832 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 833 break; 834 DELAY(10); 835 } 836 837 if (i == RL_TIMEOUT) { 838 device_printf(sc->rl_dev, 839 "diagnostic failed, failed to receive packet in" 840 " loopback mode\n"); 841 error = EIO; 842 goto done; 843 } 844 845 /* 846 * The packet should have been dumped into the first 847 * entry in the RX DMA ring. Grab it from there. 848 */ 849 850 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 851 sc->rl_ldata.rl_rx_list_map, 852 BUS_DMASYNC_POSTREAD); 853 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 854 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 855 BUS_DMASYNC_POSTREAD); 856 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 857 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 858 859 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 860 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 861 eh = mtod(m0, struct ether_header *); 862 863 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 864 total_len = RL_RXBYTES(cur_rx); 865 rxstat = le32toh(cur_rx->rl_cmdstat); 866 867 if (total_len != ETHER_MIN_LEN) { 868 device_printf(sc->rl_dev, 869 "diagnostic failed, received short packet\n"); 870 error = EIO; 871 goto done; 872 } 873 874 /* Test that the received packet data matches what we sent. */ 875 876 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 877 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 878 ntohs(eh->ether_type) != ETHERTYPE_IP) { 879 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 880 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 881 dst, ":", src, ":", ETHERTYPE_IP); 882 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 883 eh->ether_dhost, ":", eh->ether_shost, ":", 884 ntohs(eh->ether_type)); 885 device_printf(sc->rl_dev, "You may have a defective 32-bit " 886 "NIC plugged into a 64-bit PCI slot.\n"); 887 device_printf(sc->rl_dev, "Please re-install the NIC in a " 888 "32-bit slot for proper operation.\n"); 889 device_printf(sc->rl_dev, "Read the re(4) man page for more " 890 "details.\n"); 891 error = EIO; 892 } 893 894 done: 895 /* Turn interface off, release resources */ 896 897 sc->rl_testmode = 0; 898 sc->rl_link = 0; 899 ifp->if_flags &= ~IFF_PROMISC; 900 re_stop(sc); 901 if (m0 != NULL) 902 m_freem(m0); 903 904 RL_UNLOCK(sc); 905 906 return (error); 907 } 908 909 #endif 910 911 /* 912 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 913 * IDs against our list and return a device name if we find a match. 914 */ 915 static int 916 re_probe(dev) 917 device_t dev; 918 { 919 struct rl_type *t; 920 struct rl_softc *sc; 921 int rid; 922 u_int32_t hwrev; 923 924 t = re_devs; 925 sc = device_get_softc(dev); 926 927 while (t->rl_name != NULL) { 928 if ((pci_get_vendor(dev) == t->rl_vid) && 929 (pci_get_device(dev) == t->rl_did)) { 930 /* 931 * Only attach to rev. 3 of the Linksys EG1032 adapter. 932 * Rev. 2 i supported by sk(4). 933 */ 934 if ((t->rl_vid == LINKSYS_VENDORID) && 935 (t->rl_did == LINKSYS_DEVICEID_EG1032) && 936 (pci_get_subdevice(dev) != 937 LINKSYS_SUBDEVICE_EG1032_REV3)) { 938 t++; 939 continue; 940 } 941 942 /* 943 * Temporarily map the I/O space 944 * so we can read the chip ID register. 945 */ 946 rid = RL_RID; 947 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 948 RF_ACTIVE); 949 if (sc->rl_res == NULL) { 950 device_printf(dev, 951 "couldn't map ports/memory\n"); 952 return (ENXIO); 953 } 954 sc->rl_btag = rman_get_bustag(sc->rl_res); 955 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 956 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 957 bus_release_resource(dev, RL_RES, 958 RL_RID, sc->rl_res); 959 if (t->rl_basetype == hwrev) { 960 device_set_desc(dev, t->rl_name); 961 return (BUS_PROBE_DEFAULT); 962 } 963 } 964 t++; 965 } 966 967 return (ENXIO); 968 } 969 970 /* 971 * Map a single buffer address. 972 */ 973 974 static void 975 re_dma_map_addr(arg, segs, nseg, error) 976 void *arg; 977 bus_dma_segment_t *segs; 978 int nseg; 979 int error; 980 { 981 bus_addr_t *addr; 982 983 if (error) 984 return; 985 986 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 987 addr = arg; 988 *addr = segs->ds_addr; 989 } 990 991 static int 992 re_allocmem(dev, sc) 993 device_t dev; 994 struct rl_softc *sc; 995 { 996 bus_size_t rx_list_size, tx_list_size; 997 int error; 998 int i; 999 1000 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 1001 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 1002 1003 /* 1004 * Allocate the parent bus DMA tag appropriate for PCI. 1005 */ 1006 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 1007 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1008 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 1009 NULL, NULL, &sc->rl_parent_tag); 1010 if (error) { 1011 device_printf(dev, "could not allocate parent DMA tag\n"); 1012 return (error); 1013 } 1014 1015 /* 1016 * Allocate map for TX mbufs. 1017 */ 1018 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 1019 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1020 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 1021 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 1022 if (error) { 1023 device_printf(dev, "could not allocate TX DMA tag\n"); 1024 return (error); 1025 } 1026 1027 /* 1028 * Allocate map for RX mbufs. 1029 */ 1030 1031 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 1032 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1033 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 1034 if (error) { 1035 device_printf(dev, "could not allocate RX DMA tag\n"); 1036 return (error); 1037 } 1038 1039 /* 1040 * Allocate map for TX descriptor list. 1041 */ 1042 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1043 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1044 NULL, tx_list_size, 1, tx_list_size, 0, 1045 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1046 if (error) { 1047 device_printf(dev, "could not allocate TX DMA ring tag\n"); 1048 return (error); 1049 } 1050 1051 /* Allocate DMA'able memory for the TX ring */ 1052 1053 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1054 (void **)&sc->rl_ldata.rl_tx_list, 1055 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1056 &sc->rl_ldata.rl_tx_list_map); 1057 if (error) { 1058 device_printf(dev, "could not allocate TX DMA ring\n"); 1059 return (error); 1060 } 1061 1062 /* Load the map for the TX ring. */ 1063 1064 sc->rl_ldata.rl_tx_list_addr = 0; 1065 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1066 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1067 tx_list_size, re_dma_map_addr, 1068 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1069 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 1070 device_printf(dev, "could not load TX DMA ring\n"); 1071 return (ENOMEM); 1072 } 1073 1074 /* Create DMA maps for TX buffers */ 1075 1076 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1077 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1078 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1079 if (error) { 1080 device_printf(dev, "could not create DMA map for TX\n"); 1081 return (error); 1082 } 1083 } 1084 1085 /* 1086 * Allocate map for RX descriptor list. 1087 */ 1088 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1089 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1090 NULL, rx_list_size, 1, rx_list_size, 0, 1091 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1092 if (error) { 1093 device_printf(dev, "could not create RX DMA ring tag\n"); 1094 return (error); 1095 } 1096 1097 /* Allocate DMA'able memory for the RX ring */ 1098 1099 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1100 (void **)&sc->rl_ldata.rl_rx_list, 1101 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1102 &sc->rl_ldata.rl_rx_list_map); 1103 if (error) { 1104 device_printf(dev, "could not allocate RX DMA ring\n"); 1105 return (error); 1106 } 1107 1108 /* Load the map for the RX ring. */ 1109 1110 sc->rl_ldata.rl_rx_list_addr = 0; 1111 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1112 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1113 rx_list_size, re_dma_map_addr, 1114 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1115 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1116 device_printf(dev, "could not load RX DMA ring\n"); 1117 return (ENOMEM); 1118 } 1119 1120 /* Create DMA maps for RX buffers */ 1121 1122 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1123 &sc->rl_ldata.rl_rx_sparemap); 1124 if (error) { 1125 device_printf(dev, "could not create spare DMA map for RX\n"); 1126 return (error); 1127 } 1128 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1129 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1130 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1131 if (error) { 1132 device_printf(dev, "could not create DMA map for RX\n"); 1133 return (error); 1134 } 1135 } 1136 1137 return (0); 1138 } 1139 1140 /* 1141 * Attach the interface. Allocate softc structures, do ifmedia 1142 * setup and ethernet/BPF attach. 1143 */ 1144 static int 1145 re_attach(dev) 1146 device_t dev; 1147 { 1148 u_char eaddr[ETHER_ADDR_LEN]; 1149 u_int16_t as[ETHER_ADDR_LEN / 2]; 1150 struct rl_softc *sc; 1151 struct ifnet *ifp; 1152 struct rl_hwrev *hw_rev; 1153 int hwrev; 1154 u_int16_t re_did = 0; 1155 int error = 0, rid, i; 1156 int msic, reg; 1157 1158 sc = device_get_softc(dev); 1159 sc->rl_dev = dev; 1160 1161 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1162 MTX_DEF); 1163 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1164 1165 /* 1166 * Map control/status registers. 1167 */ 1168 pci_enable_busmaster(dev); 1169 1170 rid = RL_RID; 1171 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 1172 RF_ACTIVE); 1173 1174 if (sc->rl_res == NULL) { 1175 device_printf(dev, "couldn't map ports/memory\n"); 1176 error = ENXIO; 1177 goto fail; 1178 } 1179 1180 sc->rl_btag = rman_get_bustag(sc->rl_res); 1181 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1182 1183 msic = 0; 1184 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 1185 msic = pci_msi_count(dev); 1186 if (bootverbose) 1187 device_printf(dev, "MSI count : %d\n", msic); 1188 } 1189 if (msic == RL_MSI_MESSAGES && msi_disable == 0) { 1190 if (pci_alloc_msi(dev, &msic) == 0) { 1191 if (msic == RL_MSI_MESSAGES) { 1192 device_printf(dev, "Using %d MSI messages\n", 1193 msic); 1194 sc->rl_msi = 1; 1195 } else 1196 pci_release_msi(dev); 1197 } 1198 } 1199 1200 /* Allocate interrupt */ 1201 if (sc->rl_msi == 0) { 1202 rid = 0; 1203 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1204 RF_SHAREABLE | RF_ACTIVE); 1205 if (sc->rl_irq[0] == NULL) { 1206 device_printf(dev, "couldn't allocate IRQ resources\n"); 1207 error = ENXIO; 1208 goto fail; 1209 } 1210 } else { 1211 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1212 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1213 SYS_RES_IRQ, &rid, RF_ACTIVE); 1214 if (sc->rl_irq[i] == NULL) { 1215 device_printf(dev, 1216 "couldn't llocate IRQ resources for " 1217 "message %d\n", rid); 1218 error = ENXIO; 1219 goto fail; 1220 } 1221 } 1222 } 1223 1224 /* Reset the adapter. */ 1225 RL_LOCK(sc); 1226 re_reset(sc); 1227 RL_UNLOCK(sc); 1228 1229 hw_rev = re_hwrevs; 1230 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 1231 while (hw_rev->rl_desc != NULL) { 1232 if (hw_rev->rl_rev == hwrev) { 1233 sc->rl_type = hw_rev->rl_type; 1234 break; 1235 } 1236 hw_rev++; 1237 } 1238 if (hw_rev->rl_desc == NULL) { 1239 device_printf(dev, "Unknown H/W revision: %08x\n", hwrev); 1240 error = ENXIO; 1241 goto fail; 1242 } 1243 1244 sc->rl_eewidth = RL_9356_ADDR_LEN; 1245 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1246 if (re_did != 0x8129) 1247 sc->rl_eewidth = RL_9346_ADDR_LEN; 1248 1249 /* 1250 * Get station address from the EEPROM. 1251 */ 1252 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1253 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1254 as[i] = le16toh(as[i]); 1255 bcopy(as, eaddr, sizeof(eaddr)); 1256 1257 if (sc->rl_type == RL_8169) { 1258 /* Set RX length mask and number of descriptors. */ 1259 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1260 sc->rl_txstart = RL_GTXSTART; 1261 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1262 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1263 } else { 1264 /* Set RX length mask and number of descriptors. */ 1265 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1266 sc->rl_txstart = RL_TXSTART; 1267 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1268 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1269 } 1270 1271 error = re_allocmem(dev, sc); 1272 if (error) 1273 goto fail; 1274 1275 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1276 if (ifp == NULL) { 1277 device_printf(dev, "can not if_alloc()\n"); 1278 error = ENOSPC; 1279 goto fail; 1280 } 1281 1282 /* Do MII setup */ 1283 if (mii_phy_probe(dev, &sc->rl_miibus, 1284 re_ifmedia_upd, re_ifmedia_sts)) { 1285 device_printf(dev, "MII without any phy!\n"); 1286 error = ENXIO; 1287 goto fail; 1288 } 1289 1290 /* Take PHY out of power down mode. */ 1291 if (sc->rl_type == RL_8169) { 1292 uint32_t rev; 1293 1294 rev = CSR_READ_4(sc, RL_TXCFG); 1295 /* HWVERID 0, 1 and 2 : bit26-30, bit23 */ 1296 rev &= 0x7c800000; 1297 if (rev != 0) { 1298 /* RTL8169S single chip */ 1299 switch (rev) { 1300 case RL_HWREV_8169_8110SB: 1301 case RL_HWREV_8169_8110SC: 1302 case RL_HWREV_8168_SPIN2: 1303 case RL_HWREV_8168_SPIN3: 1304 re_gmii_writereg(dev, 1, 0x1f, 0); 1305 re_gmii_writereg(dev, 1, 0x0e, 0); 1306 break; 1307 default: 1308 break; 1309 } 1310 } 1311 } 1312 1313 ifp->if_softc = sc; 1314 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1315 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1316 ifp->if_ioctl = re_ioctl; 1317 ifp->if_start = re_start; 1318 ifp->if_hwassist = RE_CSUM_FEATURES | CSUM_TSO; 1319 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 1320 ifp->if_capenable = ifp->if_capabilities; 1321 ifp->if_init = re_init; 1322 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1323 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1324 IFQ_SET_READY(&ifp->if_snd); 1325 1326 TASK_INIT(&sc->rl_txtask, 1, re_tx_task, ifp); 1327 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1328 1329 /* 1330 * Call MI attach routine. 1331 */ 1332 ether_ifattach(ifp, eaddr); 1333 1334 /* VLAN capability setup */ 1335 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1336 if (ifp->if_capabilities & IFCAP_HWCSUM) 1337 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1338 ifp->if_capenable = ifp->if_capabilities; 1339 #ifdef DEVICE_POLLING 1340 ifp->if_capabilities |= IFCAP_POLLING; 1341 #endif 1342 /* 1343 * Tell the upper layer(s) we support long frames. 1344 * Must appear after the call to ether_ifattach() because 1345 * ether_ifattach() sets ifi_hdrlen to the default value. 1346 */ 1347 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1348 1349 #ifdef RE_DIAG 1350 /* 1351 * Perform hardware diagnostic on the original RTL8169. 1352 * Some 32-bit cards were incorrectly wired and would 1353 * malfunction if plugged into a 64-bit slot. 1354 */ 1355 1356 if (hwrev == RL_HWREV_8169) { 1357 error = re_diag(sc); 1358 if (error) { 1359 device_printf(dev, 1360 "attach aborted due to hardware diag failure\n"); 1361 ether_ifdetach(ifp); 1362 goto fail; 1363 } 1364 } 1365 #endif 1366 1367 /* Hook interrupt last to avoid having to lock softc */ 1368 if (sc->rl_msi == 0) 1369 error = bus_setup_intr(dev, sc->rl_irq[0], 1370 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1371 &sc->rl_intrhand[0]); 1372 else { 1373 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1374 error = bus_setup_intr(dev, sc->rl_irq[i], 1375 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1376 &sc->rl_intrhand[i]); 1377 if (error != 0) 1378 break; 1379 } 1380 } 1381 if (error) { 1382 device_printf(dev, "couldn't set up irq\n"); 1383 ether_ifdetach(ifp); 1384 } 1385 1386 fail: 1387 1388 if (error) 1389 re_detach(dev); 1390 1391 return (error); 1392 } 1393 1394 /* 1395 * Shutdown hardware and free up resources. This can be called any 1396 * time after the mutex has been initialized. It is called in both 1397 * the error case in attach and the normal detach case so it needs 1398 * to be careful about only freeing resources that have actually been 1399 * allocated. 1400 */ 1401 static int 1402 re_detach(dev) 1403 device_t dev; 1404 { 1405 struct rl_softc *sc; 1406 struct ifnet *ifp; 1407 int i, rid; 1408 1409 sc = device_get_softc(dev); 1410 ifp = sc->rl_ifp; 1411 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1412 1413 #ifdef DEVICE_POLLING 1414 if (ifp->if_capenable & IFCAP_POLLING) 1415 ether_poll_deregister(ifp); 1416 #endif 1417 /* These should only be active if attach succeeded */ 1418 if (device_is_attached(dev)) { 1419 RL_LOCK(sc); 1420 #if 0 1421 sc->suspended = 1; 1422 #endif 1423 re_stop(sc); 1424 RL_UNLOCK(sc); 1425 callout_drain(&sc->rl_stat_callout); 1426 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1427 taskqueue_drain(taskqueue_fast, &sc->rl_txtask); 1428 /* 1429 * Force off the IFF_UP flag here, in case someone 1430 * still had a BPF descriptor attached to this 1431 * interface. If they do, ether_ifdetach() will cause 1432 * the BPF code to try and clear the promisc mode 1433 * flag, which will bubble down to re_ioctl(), 1434 * which will try to call re_init() again. This will 1435 * turn the NIC back on and restart the MII ticker, 1436 * which will panic the system when the kernel tries 1437 * to invoke the re_tick() function that isn't there 1438 * anymore. 1439 */ 1440 ifp->if_flags &= ~IFF_UP; 1441 ether_ifdetach(ifp); 1442 } 1443 if (sc->rl_miibus) 1444 device_delete_child(dev, sc->rl_miibus); 1445 bus_generic_detach(dev); 1446 1447 /* 1448 * The rest is resource deallocation, so we should already be 1449 * stopped here. 1450 */ 1451 1452 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1453 if (sc->rl_intrhand[i] != NULL) { 1454 bus_teardown_intr(dev, sc->rl_irq[i], 1455 sc->rl_intrhand[i]); 1456 sc->rl_intrhand[i] = NULL; 1457 } 1458 } 1459 if (ifp != NULL) 1460 if_free(ifp); 1461 if (sc->rl_msi == 0) { 1462 if (sc->rl_irq[0] != NULL) { 1463 bus_release_resource(dev, SYS_RES_IRQ, 0, 1464 sc->rl_irq[0]); 1465 sc->rl_irq[0] = NULL; 1466 } 1467 } else { 1468 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1469 if (sc->rl_irq[i] != NULL) { 1470 bus_release_resource(dev, SYS_RES_IRQ, rid, 1471 sc->rl_irq[i]); 1472 sc->rl_irq[i] = NULL; 1473 } 1474 } 1475 pci_release_msi(dev); 1476 } 1477 if (sc->rl_res) 1478 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1479 1480 /* Unload and free the RX DMA ring memory and map */ 1481 1482 if (sc->rl_ldata.rl_rx_list_tag) { 1483 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1484 sc->rl_ldata.rl_rx_list_map); 1485 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1486 sc->rl_ldata.rl_rx_list, 1487 sc->rl_ldata.rl_rx_list_map); 1488 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1489 } 1490 1491 /* Unload and free the TX DMA ring memory and map */ 1492 1493 if (sc->rl_ldata.rl_tx_list_tag) { 1494 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1495 sc->rl_ldata.rl_tx_list_map); 1496 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1497 sc->rl_ldata.rl_tx_list, 1498 sc->rl_ldata.rl_tx_list_map); 1499 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1500 } 1501 1502 /* Destroy all the RX and TX buffer maps */ 1503 1504 if (sc->rl_ldata.rl_tx_mtag) { 1505 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1506 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1507 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1508 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1509 } 1510 if (sc->rl_ldata.rl_rx_mtag) { 1511 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) 1512 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1513 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1514 if (sc->rl_ldata.rl_rx_sparemap) 1515 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1516 sc->rl_ldata.rl_rx_sparemap); 1517 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1518 } 1519 1520 /* Unload and free the stats buffer and map */ 1521 1522 if (sc->rl_ldata.rl_stag) { 1523 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1524 sc->rl_ldata.rl_rx_list_map); 1525 bus_dmamem_free(sc->rl_ldata.rl_stag, 1526 sc->rl_ldata.rl_stats, 1527 sc->rl_ldata.rl_smap); 1528 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1529 } 1530 1531 if (sc->rl_parent_tag) 1532 bus_dma_tag_destroy(sc->rl_parent_tag); 1533 1534 mtx_destroy(&sc->rl_mtx); 1535 1536 return (0); 1537 } 1538 1539 static __inline void 1540 re_discard_rxbuf(sc, idx) 1541 struct rl_softc *sc; 1542 int idx; 1543 { 1544 struct rl_desc *desc; 1545 struct rl_rxdesc *rxd; 1546 uint32_t cmdstat; 1547 1548 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1549 desc = &sc->rl_ldata.rl_rx_list[idx]; 1550 desc->rl_vlanctl = 0; 1551 cmdstat = rxd->rx_size; 1552 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1553 cmdstat |= RL_RDESC_CMD_EOR; 1554 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1555 } 1556 1557 static int 1558 re_newbuf(sc, idx) 1559 struct rl_softc *sc; 1560 int idx; 1561 { 1562 struct mbuf *m; 1563 struct rl_rxdesc *rxd; 1564 bus_dma_segment_t segs[1]; 1565 bus_dmamap_t map; 1566 struct rl_desc *desc; 1567 uint32_t cmdstat; 1568 int error, nsegs; 1569 1570 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1571 if (m == NULL) 1572 return (ENOBUFS); 1573 1574 m->m_len = m->m_pkthdr.len = MCLBYTES; 1575 #ifdef RE_FIXUP_RX 1576 /* 1577 * This is part of an evil trick to deal with non-x86 platforms. 1578 * The RealTek chip requires RX buffers to be aligned on 64-bit 1579 * boundaries, but that will hose non-x86 machines. To get around 1580 * this, we leave some empty space at the start of each buffer 1581 * and for non-x86 hosts, we copy the buffer back six bytes 1582 * to achieve word alignment. This is slightly more efficient 1583 * than allocating a new buffer, copying the contents, and 1584 * discarding the old buffer. 1585 */ 1586 m_adj(m, RE_ETHER_ALIGN); 1587 #endif 1588 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1589 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1590 if (error != 0) { 1591 m_freem(m); 1592 return (ENOBUFS); 1593 } 1594 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1595 1596 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1597 if (rxd->rx_m != NULL) { 1598 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1599 BUS_DMASYNC_POSTREAD); 1600 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1601 } 1602 1603 rxd->rx_m = m; 1604 map = rxd->rx_dmamap; 1605 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1606 rxd->rx_size = segs[0].ds_len; 1607 sc->rl_ldata.rl_rx_sparemap = map; 1608 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1609 BUS_DMASYNC_PREREAD); 1610 1611 desc = &sc->rl_ldata.rl_rx_list[idx]; 1612 desc->rl_vlanctl = 0; 1613 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1614 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1615 cmdstat = segs[0].ds_len; 1616 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1617 cmdstat |= RL_RDESC_CMD_EOR; 1618 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1619 1620 return (0); 1621 } 1622 1623 #ifdef RE_FIXUP_RX 1624 static __inline void 1625 re_fixup_rx(m) 1626 struct mbuf *m; 1627 { 1628 int i; 1629 uint16_t *src, *dst; 1630 1631 src = mtod(m, uint16_t *); 1632 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1633 1634 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1635 *dst++ = *src++; 1636 1637 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1638 1639 return; 1640 } 1641 #endif 1642 1643 static int 1644 re_tx_list_init(sc) 1645 struct rl_softc *sc; 1646 { 1647 struct rl_desc *desc; 1648 int i; 1649 1650 RL_LOCK_ASSERT(sc); 1651 1652 bzero(sc->rl_ldata.rl_tx_list, 1653 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 1654 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1655 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 1656 /* Set EOR. */ 1657 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 1658 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 1659 1660 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1661 sc->rl_ldata.rl_tx_list_map, 1662 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1663 1664 sc->rl_ldata.rl_tx_prodidx = 0; 1665 sc->rl_ldata.rl_tx_considx = 0; 1666 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 1667 1668 return (0); 1669 } 1670 1671 static int 1672 re_rx_list_init(sc) 1673 struct rl_softc *sc; 1674 { 1675 int error, i; 1676 1677 bzero(sc->rl_ldata.rl_rx_list, 1678 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 1679 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1680 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 1681 if ((error = re_newbuf(sc, i)) != 0) 1682 return (error); 1683 } 1684 1685 /* Flush the RX descriptors */ 1686 1687 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1688 sc->rl_ldata.rl_rx_list_map, 1689 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1690 1691 sc->rl_ldata.rl_rx_prodidx = 0; 1692 sc->rl_head = sc->rl_tail = NULL; 1693 1694 return (0); 1695 } 1696 1697 /* 1698 * RX handler for C+ and 8169. For the gigE chips, we support 1699 * the reception of jumbo frames that have been fragmented 1700 * across multiple 2K mbuf cluster buffers. 1701 */ 1702 static int 1703 re_rxeof(sc) 1704 struct rl_softc *sc; 1705 { 1706 struct mbuf *m; 1707 struct ifnet *ifp; 1708 int i, total_len; 1709 struct rl_desc *cur_rx; 1710 u_int32_t rxstat, rxvlan; 1711 int maxpkt = 16; 1712 1713 RL_LOCK_ASSERT(sc); 1714 1715 ifp = sc->rl_ifp; 1716 1717 /* Invalidate the descriptor memory */ 1718 1719 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1720 sc->rl_ldata.rl_rx_list_map, 1721 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1722 1723 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 1724 i = RL_RX_DESC_NXT(sc, i)) { 1725 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1726 rxstat = le32toh(cur_rx->rl_cmdstat); 1727 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 1728 break; 1729 total_len = rxstat & sc->rl_rxlenmask; 1730 rxvlan = le32toh(cur_rx->rl_vlanctl); 1731 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 1732 1733 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1734 if (re_newbuf(sc, i) != 0) { 1735 /* 1736 * If this is part of a multi-fragment packet, 1737 * discard all the pieces. 1738 */ 1739 if (sc->rl_head != NULL) { 1740 m_freem(sc->rl_head); 1741 sc->rl_head = sc->rl_tail = NULL; 1742 } 1743 re_discard_rxbuf(sc, i); 1744 continue; 1745 } 1746 m->m_len = RE_RX_DESC_BUFLEN; 1747 if (sc->rl_head == NULL) 1748 sc->rl_head = sc->rl_tail = m; 1749 else { 1750 m->m_flags &= ~M_PKTHDR; 1751 sc->rl_tail->m_next = m; 1752 sc->rl_tail = m; 1753 } 1754 continue; 1755 } 1756 1757 /* 1758 * NOTE: for the 8139C+, the frame length field 1759 * is always 12 bits in size, but for the gigE chips, 1760 * it is 13 bits (since the max RX frame length is 16K). 1761 * Unfortunately, all 32 bits in the status word 1762 * were already used, so to make room for the extra 1763 * length bit, RealTek took out the 'frame alignment 1764 * error' bit and shifted the other status bits 1765 * over one slot. The OWN, EOR, FS and LS bits are 1766 * still in the same places. We have already extracted 1767 * the frame length and checked the OWN bit, so rather 1768 * than using an alternate bit mapping, we shift the 1769 * status bits one space to the right so we can evaluate 1770 * them using the 8169 status as though it was in the 1771 * same format as that of the 8139C+. 1772 */ 1773 if (sc->rl_type == RL_8169) 1774 rxstat >>= 1; 1775 1776 /* 1777 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 1778 * set, but if CRC is clear, it will still be a valid frame. 1779 */ 1780 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 && 1781 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) { 1782 ifp->if_ierrors++; 1783 /* 1784 * If this is part of a multi-fragment packet, 1785 * discard all the pieces. 1786 */ 1787 if (sc->rl_head != NULL) { 1788 m_freem(sc->rl_head); 1789 sc->rl_head = sc->rl_tail = NULL; 1790 } 1791 re_discard_rxbuf(sc, i); 1792 continue; 1793 } 1794 1795 /* 1796 * If allocating a replacement mbuf fails, 1797 * reload the current one. 1798 */ 1799 1800 if (re_newbuf(sc, i) != 0) { 1801 ifp->if_iqdrops++; 1802 if (sc->rl_head != NULL) { 1803 m_freem(sc->rl_head); 1804 sc->rl_head = sc->rl_tail = NULL; 1805 } 1806 re_discard_rxbuf(sc, i); 1807 continue; 1808 } 1809 1810 if (sc->rl_head != NULL) { 1811 m->m_len = total_len % RE_RX_DESC_BUFLEN; 1812 if (m->m_len == 0) 1813 m->m_len = RE_RX_DESC_BUFLEN; 1814 /* 1815 * Special case: if there's 4 bytes or less 1816 * in this buffer, the mbuf can be discarded: 1817 * the last 4 bytes is the CRC, which we don't 1818 * care about anyway. 1819 */ 1820 if (m->m_len <= ETHER_CRC_LEN) { 1821 sc->rl_tail->m_len -= 1822 (ETHER_CRC_LEN - m->m_len); 1823 m_freem(m); 1824 } else { 1825 m->m_len -= ETHER_CRC_LEN; 1826 m->m_flags &= ~M_PKTHDR; 1827 sc->rl_tail->m_next = m; 1828 } 1829 m = sc->rl_head; 1830 sc->rl_head = sc->rl_tail = NULL; 1831 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1832 } else 1833 m->m_pkthdr.len = m->m_len = 1834 (total_len - ETHER_CRC_LEN); 1835 1836 #ifdef RE_FIXUP_RX 1837 re_fixup_rx(m); 1838 #endif 1839 ifp->if_ipackets++; 1840 m->m_pkthdr.rcvif = ifp; 1841 1842 /* Do RX checksumming if enabled */ 1843 1844 if (ifp->if_capenable & IFCAP_RXCSUM) { 1845 1846 /* Check IP header checksum */ 1847 if (rxstat & RL_RDESC_STAT_PROTOID) 1848 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1849 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1850 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1851 1852 /* Check TCP/UDP checksum */ 1853 if ((RL_TCPPKT(rxstat) && 1854 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1855 (RL_UDPPKT(rxstat) && 1856 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1857 m->m_pkthdr.csum_flags |= 1858 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1859 m->m_pkthdr.csum_data = 0xffff; 1860 } 1861 } 1862 maxpkt--; 1863 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 1864 m->m_pkthdr.ether_vtag = 1865 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)); 1866 m->m_flags |= M_VLANTAG; 1867 } 1868 RL_UNLOCK(sc); 1869 (*ifp->if_input)(ifp, m); 1870 RL_LOCK(sc); 1871 } 1872 1873 /* Flush the RX DMA ring */ 1874 1875 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1876 sc->rl_ldata.rl_rx_list_map, 1877 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1878 1879 sc->rl_ldata.rl_rx_prodidx = i; 1880 1881 if (maxpkt) 1882 return(EAGAIN); 1883 1884 return(0); 1885 } 1886 1887 static void 1888 re_txeof(sc) 1889 struct rl_softc *sc; 1890 { 1891 struct ifnet *ifp; 1892 struct rl_txdesc *txd; 1893 u_int32_t txstat; 1894 int cons; 1895 1896 cons = sc->rl_ldata.rl_tx_considx; 1897 if (cons == sc->rl_ldata.rl_tx_prodidx) 1898 return; 1899 1900 ifp = sc->rl_ifp; 1901 /* Invalidate the TX descriptor list */ 1902 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1903 sc->rl_ldata.rl_tx_list_map, 1904 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1905 1906 for (; cons != sc->rl_ldata.rl_tx_prodidx; 1907 cons = RL_TX_DESC_NXT(sc, cons)) { 1908 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 1909 if (txstat & RL_TDESC_STAT_OWN) 1910 break; 1911 /* 1912 * We only stash mbufs in the last descriptor 1913 * in a fragment chain, which also happens to 1914 * be the only place where the TX status bits 1915 * are valid. 1916 */ 1917 if (txstat & RL_TDESC_CMD_EOF) { 1918 txd = &sc->rl_ldata.rl_tx_desc[cons]; 1919 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 1920 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 1921 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 1922 txd->tx_dmamap); 1923 KASSERT(txd->tx_m != NULL, 1924 ("%s: freeing NULL mbufs!", __func__)); 1925 m_freem(txd->tx_m); 1926 txd->tx_m = NULL; 1927 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 1928 RL_TDESC_STAT_COLCNT)) 1929 ifp->if_collisions++; 1930 if (txstat & RL_TDESC_STAT_TXERRSUM) 1931 ifp->if_oerrors++; 1932 else 1933 ifp->if_opackets++; 1934 } 1935 sc->rl_ldata.rl_tx_free++; 1936 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1937 } 1938 sc->rl_ldata.rl_tx_considx = cons; 1939 1940 /* No changes made to the TX ring, so no flush needed */ 1941 1942 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 1943 /* 1944 * Some chips will ignore a second TX request issued 1945 * while an existing transmission is in progress. If 1946 * the transmitter goes idle but there are still 1947 * packets waiting to be sent, we need to restart the 1948 * channel here to flush them out. This only seems to 1949 * be required with the PCIe devices. 1950 */ 1951 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 1952 1953 #ifdef RE_TX_MODERATION 1954 /* 1955 * If not all descriptors have been reaped yet, reload 1956 * the timer so that we will eventually get another 1957 * interrupt that will cause us to re-enter this routine. 1958 * This is done in case the transmitter has gone idle. 1959 */ 1960 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 1961 #endif 1962 } else 1963 sc->rl_watchdog_timer = 0; 1964 } 1965 1966 static void 1967 re_tick(xsc) 1968 void *xsc; 1969 { 1970 struct rl_softc *sc; 1971 struct mii_data *mii; 1972 struct ifnet *ifp; 1973 1974 sc = xsc; 1975 ifp = sc->rl_ifp; 1976 1977 RL_LOCK_ASSERT(sc); 1978 1979 re_watchdog(sc); 1980 1981 mii = device_get_softc(sc->rl_miibus); 1982 mii_tick(mii); 1983 if (sc->rl_link) { 1984 if (!(mii->mii_media_status & IFM_ACTIVE)) 1985 sc->rl_link = 0; 1986 } else { 1987 if (mii->mii_media_status & IFM_ACTIVE && 1988 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1989 sc->rl_link = 1; 1990 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1991 taskqueue_enqueue_fast(taskqueue_fast, 1992 &sc->rl_txtask); 1993 } 1994 } 1995 1996 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 1997 } 1998 1999 #ifdef DEVICE_POLLING 2000 static void 2001 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2002 { 2003 struct rl_softc *sc = ifp->if_softc; 2004 2005 RL_LOCK(sc); 2006 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2007 re_poll_locked(ifp, cmd, count); 2008 RL_UNLOCK(sc); 2009 } 2010 2011 static void 2012 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2013 { 2014 struct rl_softc *sc = ifp->if_softc; 2015 2016 RL_LOCK_ASSERT(sc); 2017 2018 sc->rxcycles = count; 2019 re_rxeof(sc); 2020 re_txeof(sc); 2021 2022 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2023 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2024 2025 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2026 u_int16_t status; 2027 2028 status = CSR_READ_2(sc, RL_ISR); 2029 if (status == 0xffff) 2030 return; 2031 if (status) 2032 CSR_WRITE_2(sc, RL_ISR, status); 2033 2034 /* 2035 * XXX check behaviour on receiver stalls. 2036 */ 2037 2038 if (status & RL_ISR_SYSTEM_ERR) { 2039 re_reset(sc); 2040 re_init_locked(sc); 2041 } 2042 } 2043 } 2044 #endif /* DEVICE_POLLING */ 2045 2046 static int 2047 re_intr(arg) 2048 void *arg; 2049 { 2050 struct rl_softc *sc; 2051 uint16_t status; 2052 2053 sc = arg; 2054 2055 status = CSR_READ_2(sc, RL_ISR); 2056 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2057 return (FILTER_STRAY); 2058 CSR_WRITE_2(sc, RL_IMR, 0); 2059 2060 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2061 2062 return (FILTER_HANDLED); 2063 } 2064 2065 static void 2066 re_int_task(arg, npending) 2067 void *arg; 2068 int npending; 2069 { 2070 struct rl_softc *sc; 2071 struct ifnet *ifp; 2072 u_int16_t status; 2073 int rval = 0; 2074 2075 sc = arg; 2076 ifp = sc->rl_ifp; 2077 2078 RL_LOCK(sc); 2079 2080 status = CSR_READ_2(sc, RL_ISR); 2081 CSR_WRITE_2(sc, RL_ISR, status); 2082 2083 if (sc->suspended || 2084 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2085 RL_UNLOCK(sc); 2086 return; 2087 } 2088 2089 #ifdef DEVICE_POLLING 2090 if (ifp->if_capenable & IFCAP_POLLING) { 2091 RL_UNLOCK(sc); 2092 return; 2093 } 2094 #endif 2095 2096 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2097 rval = re_rxeof(sc); 2098 2099 #ifdef RE_TX_MODERATION 2100 if (status & (RL_ISR_TIMEOUT_EXPIRED| 2101 #else 2102 if (status & (RL_ISR_TX_OK| 2103 #endif 2104 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2105 re_txeof(sc); 2106 2107 if (status & RL_ISR_SYSTEM_ERR) { 2108 re_reset(sc); 2109 re_init_locked(sc); 2110 } 2111 2112 if (status & RL_ISR_LINKCHG) { 2113 callout_stop(&sc->rl_stat_callout); 2114 re_tick(sc); 2115 } 2116 2117 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2118 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2119 2120 RL_UNLOCK(sc); 2121 2122 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2123 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2124 return; 2125 } 2126 2127 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2128 2129 return; 2130 } 2131 2132 /* 2133 * It's copy of ath_defrag(ath(4)). 2134 * 2135 * Defragment an mbuf chain, returning at most maxfrags separate 2136 * mbufs+clusters. If this is not possible NULL is returned and 2137 * the original mbuf chain is left in it's present (potentially 2138 * modified) state. We use two techniques: collapsing consecutive 2139 * mbufs and replacing consecutive mbufs by a cluster. 2140 */ 2141 static struct mbuf * 2142 re_defrag(m0, how, maxfrags) 2143 struct mbuf *m0; 2144 int how; 2145 int maxfrags; 2146 { 2147 struct mbuf *m, *n, *n2, **prev; 2148 u_int curfrags; 2149 2150 /* 2151 * Calculate the current number of frags. 2152 */ 2153 curfrags = 0; 2154 for (m = m0; m != NULL; m = m->m_next) 2155 curfrags++; 2156 /* 2157 * First, try to collapse mbufs. Note that we always collapse 2158 * towards the front so we don't need to deal with moving the 2159 * pkthdr. This may be suboptimal if the first mbuf has much 2160 * less data than the following. 2161 */ 2162 m = m0; 2163 again: 2164 for (;;) { 2165 n = m->m_next; 2166 if (n == NULL) 2167 break; 2168 if ((m->m_flags & M_RDONLY) == 0 && 2169 n->m_len < M_TRAILINGSPACE(m)) { 2170 bcopy(mtod(n, void *), mtod(m, char *) + m->m_len, 2171 n->m_len); 2172 m->m_len += n->m_len; 2173 m->m_next = n->m_next; 2174 m_free(n); 2175 if (--curfrags <= maxfrags) 2176 return (m0); 2177 } else 2178 m = n; 2179 } 2180 KASSERT(maxfrags > 1, 2181 ("maxfrags %u, but normal collapse failed", maxfrags)); 2182 /* 2183 * Collapse consecutive mbufs to a cluster. 2184 */ 2185 prev = &m0->m_next; /* NB: not the first mbuf */ 2186 while ((n = *prev) != NULL) { 2187 if ((n2 = n->m_next) != NULL && 2188 n->m_len + n2->m_len < MCLBYTES) { 2189 m = m_getcl(how, MT_DATA, 0); 2190 if (m == NULL) 2191 goto bad; 2192 bcopy(mtod(n, void *), mtod(m, void *), n->m_len); 2193 bcopy(mtod(n2, void *), mtod(m, char *) + n->m_len, 2194 n2->m_len); 2195 m->m_len = n->m_len + n2->m_len; 2196 m->m_next = n2->m_next; 2197 *prev = m; 2198 m_free(n); 2199 m_free(n2); 2200 if (--curfrags <= maxfrags) /* +1 cl -2 mbufs */ 2201 return m0; 2202 /* 2203 * Still not there, try the normal collapse 2204 * again before we allocate another cluster. 2205 */ 2206 goto again; 2207 } 2208 prev = &n->m_next; 2209 } 2210 /* 2211 * No place where we can collapse to a cluster; punt. 2212 * This can occur if, for example, you request 2 frags 2213 * but the packet requires that both be clusters (we 2214 * never reallocate the first mbuf to avoid moving the 2215 * packet header). 2216 */ 2217 bad: 2218 return (NULL); 2219 } 2220 2221 static int 2222 re_encap(sc, m_head) 2223 struct rl_softc *sc; 2224 struct mbuf **m_head; 2225 { 2226 struct rl_txdesc *txd, *txd_last; 2227 bus_dma_segment_t segs[RL_NTXSEGS]; 2228 bus_dmamap_t map; 2229 struct mbuf *m_new; 2230 struct rl_desc *desc; 2231 int nsegs, prod; 2232 int i, error, ei, si; 2233 int padlen; 2234 uint32_t cmdstat, csum_flags; 2235 2236 RL_LOCK_ASSERT(sc); 2237 M_ASSERTPKTHDR((*m_head)); 2238 2239 /* 2240 * With some of the RealTek chips, using the checksum offload 2241 * support in conjunction with the autopadding feature results 2242 * in the transmission of corrupt frames. For example, if we 2243 * need to send a really small IP fragment that's less than 60 2244 * bytes in size, and IP header checksumming is enabled, the 2245 * resulting ethernet frame that appears on the wire will 2246 * have garbled payload. To work around this, if TX checksum 2247 * offload is enabled, we always manually pad short frames out 2248 * to the minimum ethernet frame size. 2249 * 2250 * Note: this appears unnecessary for TCP, and doing it for TCP 2251 * with PCIe adapters seems to result in bad checksums. 2252 */ 2253 if ((*m_head)->m_pkthdr.csum_flags & (CSUM_IP | CSUM_UDP) && 2254 ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) == 0 && 2255 (*m_head)->m_pkthdr.len < RL_MIN_FRAMELEN) { 2256 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2257 if (M_WRITABLE(*m_head) == 0) { 2258 /* Get a writable copy. */ 2259 m_new = m_dup(*m_head, M_DONTWAIT); 2260 m_freem(*m_head); 2261 if (m_new == NULL) { 2262 *m_head = NULL; 2263 return (ENOBUFS); 2264 } 2265 *m_head = m_new; 2266 } 2267 if ((*m_head)->m_next != NULL || 2268 M_TRAILINGSPACE(*m_head) < padlen) { 2269 m_new = m_defrag(*m_head, M_DONTWAIT); 2270 if (m_new == NULL) { 2271 m_freem(*m_head); 2272 *m_head = NULL; 2273 return (ENOBUFS); 2274 } 2275 } else 2276 m_new = *m_head; 2277 2278 /* 2279 * Manually pad short frames, and zero the pad space 2280 * to avoid leaking data. 2281 */ 2282 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2283 m_new->m_pkthdr.len += padlen; 2284 m_new->m_len = m_new->m_pkthdr.len; 2285 *m_head = m_new; 2286 } 2287 2288 prod = sc->rl_ldata.rl_tx_prodidx; 2289 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2290 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2291 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2292 if (error == EFBIG) { 2293 m_new = re_defrag(*m_head, M_DONTWAIT, RL_NTXSEGS); 2294 if (m_new == NULL) { 2295 m_freem(*m_head); 2296 *m_head = NULL; 2297 return (ENOBUFS); 2298 } 2299 *m_head = m_new; 2300 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2301 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2302 if (error != 0) { 2303 m_freem(*m_head); 2304 *m_head = NULL; 2305 return (error); 2306 } 2307 } else if (error != 0) 2308 return (error); 2309 if (nsegs == 0) { 2310 m_freem(*m_head); 2311 *m_head = NULL; 2312 return (EIO); 2313 } 2314 2315 /* Check for number of available descriptors. */ 2316 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2317 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2318 return (ENOBUFS); 2319 } 2320 2321 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2322 BUS_DMASYNC_PREWRITE); 2323 2324 /* 2325 * Set up checksum offload. Note: checksum offload bits must 2326 * appear in all descriptors of a multi-descriptor transmit 2327 * attempt. This is according to testing done with an 8169 2328 * chip. This is a requirement. 2329 */ 2330 csum_flags = 0; 2331 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) 2332 csum_flags = RL_TDESC_CMD_LGSEND | 2333 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2334 RL_TDESC_CMD_MSSVAL_SHIFT); 2335 else { 2336 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) 2337 csum_flags |= RL_TDESC_CMD_IPCSUM; 2338 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) 2339 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2340 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) 2341 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2342 } 2343 2344 si = prod; 2345 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2346 desc = &sc->rl_ldata.rl_tx_list[prod]; 2347 desc->rl_vlanctl = 0; 2348 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2349 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2350 cmdstat = segs[i].ds_len; 2351 if (i != 0) 2352 cmdstat |= RL_TDESC_CMD_OWN; 2353 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2354 cmdstat |= RL_TDESC_CMD_EOR; 2355 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2356 sc->rl_ldata.rl_tx_free--; 2357 } 2358 /* Update producer index. */ 2359 sc->rl_ldata.rl_tx_prodidx = prod; 2360 2361 /* Set EOF on the last descriptor. */ 2362 ei = RL_TX_DESC_PRV(sc, prod); 2363 desc = &sc->rl_ldata.rl_tx_list[ei]; 2364 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2365 2366 desc = &sc->rl_ldata.rl_tx_list[si]; 2367 /* 2368 * Set up hardware VLAN tagging. Note: vlan tag info must 2369 * appear in the first descriptor of a multi-descriptor 2370 * transmission attempt. 2371 */ 2372 if ((*m_head)->m_flags & M_VLANTAG) 2373 desc->rl_vlanctl = 2374 htole32(htons((*m_head)->m_pkthdr.ether_vtag) | 2375 RL_TDESC_VLANCTL_TAG); 2376 /* Set SOF and transfer ownership of packet to the chip. */ 2377 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2378 2379 /* 2380 * Insure that the map for this transmission 2381 * is placed at the array index of the last descriptor 2382 * in this chain. (Swap last and first dmamaps.) 2383 */ 2384 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2385 map = txd->tx_dmamap; 2386 txd->tx_dmamap = txd_last->tx_dmamap; 2387 txd_last->tx_dmamap = map; 2388 txd_last->tx_m = *m_head; 2389 2390 return (0); 2391 } 2392 2393 static void 2394 re_tx_task(arg, npending) 2395 void *arg; 2396 int npending; 2397 { 2398 struct ifnet *ifp; 2399 2400 ifp = arg; 2401 re_start(ifp); 2402 2403 return; 2404 } 2405 2406 /* 2407 * Main transmit routine for C+ and gigE NICs. 2408 */ 2409 static void 2410 re_start(ifp) 2411 struct ifnet *ifp; 2412 { 2413 struct rl_softc *sc; 2414 struct mbuf *m_head; 2415 int queued; 2416 2417 sc = ifp->if_softc; 2418 2419 RL_LOCK(sc); 2420 2421 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2422 IFF_DRV_RUNNING || sc->rl_link == 0) { 2423 RL_UNLOCK(sc); 2424 return; 2425 } 2426 2427 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2428 sc->rl_ldata.rl_tx_free > 1;) { 2429 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2430 if (m_head == NULL) 2431 break; 2432 2433 if (re_encap(sc, &m_head) != 0) { 2434 if (m_head == NULL) 2435 break; 2436 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2437 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2438 break; 2439 } 2440 2441 /* 2442 * If there's a BPF listener, bounce a copy of this frame 2443 * to him. 2444 */ 2445 ETHER_BPF_MTAP(ifp, m_head); 2446 2447 queued++; 2448 } 2449 2450 if (queued == 0) { 2451 #ifdef RE_TX_MODERATION 2452 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2453 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2454 #endif 2455 RL_UNLOCK(sc); 2456 return; 2457 } 2458 2459 /* Flush the TX descriptors */ 2460 2461 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2462 sc->rl_ldata.rl_tx_list_map, 2463 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2464 2465 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2466 2467 #ifdef RE_TX_MODERATION 2468 /* 2469 * Use the countdown timer for interrupt moderation. 2470 * 'TX done' interrupts are disabled. Instead, we reset the 2471 * countdown timer, which will begin counting until it hits 2472 * the value in the TIMERINT register, and then trigger an 2473 * interrupt. Each time we write to the TIMERCNT register, 2474 * the timer count is reset to 0. 2475 */ 2476 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2477 #endif 2478 2479 /* 2480 * Set a timeout in case the chip goes out to lunch. 2481 */ 2482 sc->rl_watchdog_timer = 5; 2483 2484 RL_UNLOCK(sc); 2485 2486 return; 2487 } 2488 2489 static void 2490 re_init(xsc) 2491 void *xsc; 2492 { 2493 struct rl_softc *sc = xsc; 2494 2495 RL_LOCK(sc); 2496 re_init_locked(sc); 2497 RL_UNLOCK(sc); 2498 } 2499 2500 static void 2501 re_init_locked(sc) 2502 struct rl_softc *sc; 2503 { 2504 struct ifnet *ifp = sc->rl_ifp; 2505 struct mii_data *mii; 2506 u_int32_t rxcfg = 0; 2507 union { 2508 uint32_t align_dummy; 2509 u_char eaddr[ETHER_ADDR_LEN]; 2510 } eaddr; 2511 2512 RL_LOCK_ASSERT(sc); 2513 2514 mii = device_get_softc(sc->rl_miibus); 2515 2516 /* 2517 * Cancel pending I/O and free all RX/TX buffers. 2518 */ 2519 re_stop(sc); 2520 2521 /* 2522 * Enable C+ RX and TX mode, as well as VLAN stripping and 2523 * RX checksum offload. We must configure the C+ register 2524 * before all others. 2525 */ 2526 CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB| 2527 RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW| 2528 RL_CPLUSCMD_VLANSTRIP|RL_CPLUSCMD_RXCSUM_ENB); 2529 2530 /* 2531 * Init our MAC address. Even though the chipset 2532 * documentation doesn't mention it, we need to enter "Config 2533 * register write enable" mode to modify the ID registers. 2534 */ 2535 /* Copy MAC address on stack to align. */ 2536 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 2537 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2538 CSR_WRITE_4(sc, RL_IDR0, 2539 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 2540 CSR_WRITE_4(sc, RL_IDR4, 2541 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 2542 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2543 2544 /* 2545 * For C+ mode, initialize the RX descriptors and mbufs. 2546 */ 2547 re_rx_list_init(sc); 2548 re_tx_list_init(sc); 2549 2550 /* 2551 * Load the addresses of the RX and TX lists into the chip. 2552 */ 2553 2554 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2555 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2556 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2557 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2558 2559 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2560 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2561 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2562 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2563 2564 /* 2565 * Enable transmit and receive. 2566 */ 2567 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2568 2569 /* 2570 * Set the initial TX and RX configuration. 2571 */ 2572 if (sc->rl_testmode) { 2573 if (sc->rl_type == RL_8169) 2574 CSR_WRITE_4(sc, RL_TXCFG, 2575 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2576 else 2577 CSR_WRITE_4(sc, RL_TXCFG, 2578 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2579 } else 2580 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2581 2582 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2583 2584 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 2585 2586 /* Set the individual bit to receive frames for this host only. */ 2587 rxcfg = CSR_READ_4(sc, RL_RXCFG); 2588 rxcfg |= RL_RXCFG_RX_INDIV; 2589 2590 /* If we want promiscuous mode, set the allframes bit. */ 2591 if (ifp->if_flags & IFF_PROMISC) 2592 rxcfg |= RL_RXCFG_RX_ALLPHYS; 2593 else 2594 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 2595 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2596 2597 /* 2598 * Set capture broadcast bit to capture broadcast frames. 2599 */ 2600 if (ifp->if_flags & IFF_BROADCAST) 2601 rxcfg |= RL_RXCFG_RX_BROAD; 2602 else 2603 rxcfg &= ~RL_RXCFG_RX_BROAD; 2604 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2605 2606 /* 2607 * Program the multicast filter, if necessary. 2608 */ 2609 re_setmulti(sc); 2610 2611 #ifdef DEVICE_POLLING 2612 /* 2613 * Disable interrupts if we are polling. 2614 */ 2615 if (ifp->if_capenable & IFCAP_POLLING) 2616 CSR_WRITE_2(sc, RL_IMR, 0); 2617 else /* otherwise ... */ 2618 #endif 2619 2620 /* 2621 * Enable interrupts. 2622 */ 2623 if (sc->rl_testmode) 2624 CSR_WRITE_2(sc, RL_IMR, 0); 2625 else 2626 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2627 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 2628 2629 /* Set initial TX threshold */ 2630 sc->rl_txthresh = RL_TX_THRESH_INIT; 2631 2632 /* Start RX/TX process. */ 2633 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2634 #ifdef notdef 2635 /* Enable receiver and transmitter. */ 2636 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2637 #endif 2638 2639 #ifdef RE_TX_MODERATION 2640 /* 2641 * Initialize the timer interrupt register so that 2642 * a timer interrupt will be generated once the timer 2643 * reaches a certain number of ticks. The timer is 2644 * reloaded on each transmit. This gives us TX interrupt 2645 * moderation, which dramatically improves TX frame rate. 2646 */ 2647 if (sc->rl_type == RL_8169) 2648 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2649 else 2650 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2651 #endif 2652 2653 /* 2654 * For 8169 gigE NICs, set the max allowed RX packet 2655 * size so we can receive jumbo frames. 2656 */ 2657 if (sc->rl_type == RL_8169) 2658 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2659 2660 if (sc->rl_testmode) 2661 return; 2662 2663 mii_mediachg(mii); 2664 2665 CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD); 2666 2667 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2668 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2669 2670 sc->rl_link = 0; 2671 sc->rl_watchdog_timer = 0; 2672 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2673 } 2674 2675 /* 2676 * Set media options. 2677 */ 2678 static int 2679 re_ifmedia_upd(ifp) 2680 struct ifnet *ifp; 2681 { 2682 struct rl_softc *sc; 2683 struct mii_data *mii; 2684 2685 sc = ifp->if_softc; 2686 mii = device_get_softc(sc->rl_miibus); 2687 RL_LOCK(sc); 2688 mii_mediachg(mii); 2689 RL_UNLOCK(sc); 2690 2691 return (0); 2692 } 2693 2694 /* 2695 * Report current media status. 2696 */ 2697 static void 2698 re_ifmedia_sts(ifp, ifmr) 2699 struct ifnet *ifp; 2700 struct ifmediareq *ifmr; 2701 { 2702 struct rl_softc *sc; 2703 struct mii_data *mii; 2704 2705 sc = ifp->if_softc; 2706 mii = device_get_softc(sc->rl_miibus); 2707 2708 RL_LOCK(sc); 2709 mii_pollstat(mii); 2710 RL_UNLOCK(sc); 2711 ifmr->ifm_active = mii->mii_media_active; 2712 ifmr->ifm_status = mii->mii_media_status; 2713 } 2714 2715 static int 2716 re_ioctl(ifp, command, data) 2717 struct ifnet *ifp; 2718 u_long command; 2719 caddr_t data; 2720 { 2721 struct rl_softc *sc = ifp->if_softc; 2722 struct ifreq *ifr = (struct ifreq *) data; 2723 struct mii_data *mii; 2724 int error = 0; 2725 2726 switch (command) { 2727 case SIOCSIFMTU: 2728 RL_LOCK(sc); 2729 if (ifr->ifr_mtu > RL_JUMBO_MTU) 2730 error = EINVAL; 2731 ifp->if_mtu = ifr->ifr_mtu; 2732 RL_UNLOCK(sc); 2733 break; 2734 case SIOCSIFFLAGS: 2735 RL_LOCK(sc); 2736 if ((ifp->if_flags & IFF_UP) != 0) { 2737 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2738 if (((ifp->if_flags ^ sc->rl_if_flags) 2739 & IFF_PROMISC) != 0) 2740 re_setmulti(sc); 2741 } else 2742 re_init_locked(sc); 2743 } else { 2744 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2745 re_stop(sc); 2746 } 2747 sc->rl_if_flags = ifp->if_flags; 2748 RL_UNLOCK(sc); 2749 break; 2750 case SIOCADDMULTI: 2751 case SIOCDELMULTI: 2752 RL_LOCK(sc); 2753 re_setmulti(sc); 2754 RL_UNLOCK(sc); 2755 break; 2756 case SIOCGIFMEDIA: 2757 case SIOCSIFMEDIA: 2758 mii = device_get_softc(sc->rl_miibus); 2759 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2760 break; 2761 case SIOCSIFCAP: 2762 { 2763 int mask, reinit; 2764 2765 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2766 reinit = 0; 2767 #ifdef DEVICE_POLLING 2768 if (mask & IFCAP_POLLING) { 2769 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2770 error = ether_poll_register(re_poll, ifp); 2771 if (error) 2772 return(error); 2773 RL_LOCK(sc); 2774 /* Disable interrupts */ 2775 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2776 ifp->if_capenable |= IFCAP_POLLING; 2777 RL_UNLOCK(sc); 2778 } else { 2779 error = ether_poll_deregister(ifp); 2780 /* Enable interrupts. */ 2781 RL_LOCK(sc); 2782 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2783 ifp->if_capenable &= ~IFCAP_POLLING; 2784 RL_UNLOCK(sc); 2785 } 2786 } 2787 #endif /* DEVICE_POLLING */ 2788 if (mask & IFCAP_HWCSUM) { 2789 ifp->if_capenable ^= IFCAP_HWCSUM; 2790 if (ifp->if_capenable & IFCAP_TXCSUM) 2791 ifp->if_hwassist |= RE_CSUM_FEATURES; 2792 else 2793 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 2794 reinit = 1; 2795 } 2796 if (mask & IFCAP_VLAN_HWTAGGING) { 2797 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2798 reinit = 1; 2799 } 2800 if (mask & IFCAP_TSO4) { 2801 ifp->if_capenable ^= IFCAP_TSO4; 2802 if ((IFCAP_TSO4 & ifp->if_capenable) && 2803 (IFCAP_TSO4 & ifp->if_capabilities)) 2804 ifp->if_hwassist |= CSUM_TSO; 2805 else 2806 ifp->if_hwassist &= ~CSUM_TSO; 2807 } 2808 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) 2809 re_init(sc); 2810 VLAN_CAPABILITIES(ifp); 2811 } 2812 break; 2813 default: 2814 error = ether_ioctl(ifp, command, data); 2815 break; 2816 } 2817 2818 return (error); 2819 } 2820 2821 static void 2822 re_watchdog(sc) 2823 struct rl_softc *sc; 2824 { 2825 2826 RL_LOCK_ASSERT(sc); 2827 2828 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 2829 return; 2830 2831 device_printf(sc->rl_dev, "watchdog timeout\n"); 2832 sc->rl_ifp->if_oerrors++; 2833 2834 re_txeof(sc); 2835 re_rxeof(sc); 2836 re_init_locked(sc); 2837 } 2838 2839 /* 2840 * Stop the adapter and free any mbufs allocated to the 2841 * RX and TX lists. 2842 */ 2843 static void 2844 re_stop(sc) 2845 struct rl_softc *sc; 2846 { 2847 register int i; 2848 struct ifnet *ifp; 2849 struct rl_txdesc *txd; 2850 struct rl_rxdesc *rxd; 2851 2852 RL_LOCK_ASSERT(sc); 2853 2854 ifp = sc->rl_ifp; 2855 2856 sc->rl_watchdog_timer = 0; 2857 callout_stop(&sc->rl_stat_callout); 2858 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2859 2860 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2861 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2862 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 2863 2864 if (sc->rl_head != NULL) { 2865 m_freem(sc->rl_head); 2866 sc->rl_head = sc->rl_tail = NULL; 2867 } 2868 2869 /* Free the TX list buffers. */ 2870 2871 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 2872 txd = &sc->rl_ldata.rl_tx_desc[i]; 2873 if (txd->tx_m != NULL) { 2874 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2875 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2876 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2877 txd->tx_dmamap); 2878 m_freem(txd->tx_m); 2879 txd->tx_m = NULL; 2880 } 2881 } 2882 2883 /* Free the RX list buffers. */ 2884 2885 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2886 rxd = &sc->rl_ldata.rl_rx_desc[i]; 2887 if (rxd->rx_m != NULL) { 2888 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2889 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2890 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 2891 rxd->rx_dmamap); 2892 m_freem(rxd->rx_m); 2893 rxd->rx_m = NULL; 2894 } 2895 } 2896 } 2897 2898 /* 2899 * Device suspend routine. Stop the interface and save some PCI 2900 * settings in case the BIOS doesn't restore them properly on 2901 * resume. 2902 */ 2903 static int 2904 re_suspend(dev) 2905 device_t dev; 2906 { 2907 struct rl_softc *sc; 2908 2909 sc = device_get_softc(dev); 2910 2911 RL_LOCK(sc); 2912 re_stop(sc); 2913 sc->suspended = 1; 2914 RL_UNLOCK(sc); 2915 2916 return (0); 2917 } 2918 2919 /* 2920 * Device resume routine. Restore some PCI settings in case the BIOS 2921 * doesn't, re-enable busmastering, and restart the interface if 2922 * appropriate. 2923 */ 2924 static int 2925 re_resume(dev) 2926 device_t dev; 2927 { 2928 struct rl_softc *sc; 2929 struct ifnet *ifp; 2930 2931 sc = device_get_softc(dev); 2932 2933 RL_LOCK(sc); 2934 2935 ifp = sc->rl_ifp; 2936 2937 /* reinitialize interface if necessary */ 2938 if (ifp->if_flags & IFF_UP) 2939 re_init_locked(sc); 2940 2941 sc->suspended = 0; 2942 RL_UNLOCK(sc); 2943 2944 return (0); 2945 } 2946 2947 /* 2948 * Stop all chip I/O so that the kernel's probe routines don't 2949 * get confused by errant DMAs when rebooting. 2950 */ 2951 static int 2952 re_shutdown(dev) 2953 device_t dev; 2954 { 2955 struct rl_softc *sc; 2956 2957 sc = device_get_softc(dev); 2958 2959 RL_LOCK(sc); 2960 re_stop(sc); 2961 /* 2962 * Mark interface as down since otherwise we will panic if 2963 * interrupt comes in later on, which can happen in some 2964 * cases. 2965 */ 2966 sc->rl_ifp->if_flags &= ~IFF_UP; 2967 RL_UNLOCK(sc); 2968 2969 return (0); 2970 } 2971