1 /*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44 /* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111 #ifdef HAVE_KERNEL_OPTION_HEADERS 112 #include "opt_device_polling.h" 113 #endif 114 115 #include <sys/param.h> 116 #include <sys/endian.h> 117 #include <sys/systm.h> 118 #include <sys/sockio.h> 119 #include <sys/mbuf.h> 120 #include <sys/malloc.h> 121 #include <sys/module.h> 122 #include <sys/kernel.h> 123 #include <sys/socket.h> 124 #include <sys/lock.h> 125 #include <sys/mutex.h> 126 #include <sys/taskqueue.h> 127 128 #include <net/if.h> 129 #include <net/if_arp.h> 130 #include <net/ethernet.h> 131 #include <net/if_dl.h> 132 #include <net/if_media.h> 133 #include <net/if_types.h> 134 #include <net/if_vlan_var.h> 135 136 #include <net/bpf.h> 137 138 #include <machine/bus.h> 139 #include <machine/resource.h> 140 #include <sys/bus.h> 141 #include <sys/rman.h> 142 143 #include <dev/mii/mii.h> 144 #include <dev/mii/miivar.h> 145 146 #include <dev/pci/pcireg.h> 147 #include <dev/pci/pcivar.h> 148 149 #include <pci/if_rlreg.h> 150 151 MODULE_DEPEND(re, pci, 1, 1, 1); 152 MODULE_DEPEND(re, ether, 1, 1, 1); 153 MODULE_DEPEND(re, miibus, 1, 1, 1); 154 155 /* "device miibus" required. See GENERIC if you get errors here. */ 156 #include "miibus_if.h" 157 158 /* Tunables. */ 159 static int msi_disable = 1; 160 TUNABLE_INT("hw.re.msi_disable", &msi_disable); 161 162 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 163 164 /* 165 * Various supported device vendors/types and their names. 166 */ 167 static struct rl_type re_devs[] = { 168 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0, 169 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 170 { RT_VENDORID, RT_DEVICEID_8139, 0, 171 "RealTek 8139C+ 10/100BaseTX" }, 172 { RT_VENDORID, RT_DEVICEID_8101E, 0, 173 "RealTek 8101E/8102E/8102EL PCIe 10/100baseTX" }, 174 { RT_VENDORID, RT_DEVICEID_8168, 0, 175 "RealTek 8168/8168B/8168C/8168CP/8111B/8111C/8111CP PCIe " 176 "Gigabit Ethernet" }, 177 { RT_VENDORID, RT_DEVICEID_8169, 0, 178 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" }, 179 { RT_VENDORID, RT_DEVICEID_8169SC, 0, 180 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 181 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0, 182 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 183 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0, 184 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 185 { USR_VENDORID, USR_DEVICEID_997902, 0, 186 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 187 }; 188 189 static struct rl_hwrev re_hwrevs[] = { 190 { RL_HWREV_8139, RL_8139, "" }, 191 { RL_HWREV_8139A, RL_8139, "A" }, 192 { RL_HWREV_8139AG, RL_8139, "A-G" }, 193 { RL_HWREV_8139B, RL_8139, "B" }, 194 { RL_HWREV_8130, RL_8139, "8130" }, 195 { RL_HWREV_8139C, RL_8139, "C" }, 196 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 197 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 198 { RL_HWREV_8168_SPIN1, RL_8169, "8168"}, 199 { RL_HWREV_8169, RL_8169, "8169"}, 200 { RL_HWREV_8169S, RL_8169, "8169S"}, 201 { RL_HWREV_8110S, RL_8169, "8110S"}, 202 { RL_HWREV_8169_8110SB, RL_8169, "8169SB"}, 203 { RL_HWREV_8169_8110SC, RL_8169, "8169SC"}, 204 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL"}, 205 { RL_HWREV_8100, RL_8139, "8100"}, 206 { RL_HWREV_8101, RL_8139, "8101"}, 207 { RL_HWREV_8100E, RL_8169, "8100E"}, 208 { RL_HWREV_8101E, RL_8169, "8101E"}, 209 { RL_HWREV_8102E, RL_8169, "8102E"}, 210 { RL_HWREV_8102EL, RL_8169, "8102EL"}, 211 { RL_HWREV_8168_SPIN2, RL_8169, "8168"}, 212 { RL_HWREV_8168_SPIN3, RL_8169, "8168"}, 213 { RL_HWREV_8168C, RL_8169, "8168C/8111C"}, 214 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C"}, 215 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP"}, 216 { 0, 0, NULL } 217 }; 218 219 static int re_probe (device_t); 220 static int re_attach (device_t); 221 static int re_detach (device_t); 222 223 static int re_encap (struct rl_softc *, struct mbuf **); 224 225 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 226 static int re_allocmem (device_t, struct rl_softc *); 227 static __inline void re_discard_rxbuf 228 (struct rl_softc *, int); 229 static int re_newbuf (struct rl_softc *, int); 230 static int re_rx_list_init (struct rl_softc *); 231 static int re_tx_list_init (struct rl_softc *); 232 #ifdef RE_FIXUP_RX 233 static __inline void re_fixup_rx 234 (struct mbuf *); 235 #endif 236 static int re_rxeof (struct rl_softc *); 237 static void re_txeof (struct rl_softc *); 238 #ifdef DEVICE_POLLING 239 static void re_poll (struct ifnet *, enum poll_cmd, int); 240 static void re_poll_locked (struct ifnet *, enum poll_cmd, int); 241 #endif 242 static int re_intr (void *); 243 static void re_tick (void *); 244 static void re_tx_task (void *, int); 245 static void re_int_task (void *, int); 246 static void re_start (struct ifnet *); 247 static int re_ioctl (struct ifnet *, u_long, caddr_t); 248 static void re_init (void *); 249 static void re_init_locked (struct rl_softc *); 250 static void re_stop (struct rl_softc *); 251 static void re_watchdog (struct rl_softc *); 252 static int re_suspend (device_t); 253 static int re_resume (device_t); 254 static int re_shutdown (device_t); 255 static int re_ifmedia_upd (struct ifnet *); 256 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 257 258 static void re_eeprom_putbyte (struct rl_softc *, int); 259 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 260 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 261 static int re_gmii_readreg (device_t, int, int); 262 static int re_gmii_writereg (device_t, int, int, int); 263 264 static int re_miibus_readreg (device_t, int, int); 265 static int re_miibus_writereg (device_t, int, int, int); 266 static void re_miibus_statchg (device_t); 267 268 static void re_setmulti (struct rl_softc *); 269 static void re_reset (struct rl_softc *); 270 static void re_setwol (struct rl_softc *); 271 static void re_clrwol (struct rl_softc *); 272 273 #ifdef RE_DIAG 274 static int re_diag (struct rl_softc *); 275 #endif 276 277 static device_method_t re_methods[] = { 278 /* Device interface */ 279 DEVMETHOD(device_probe, re_probe), 280 DEVMETHOD(device_attach, re_attach), 281 DEVMETHOD(device_detach, re_detach), 282 DEVMETHOD(device_suspend, re_suspend), 283 DEVMETHOD(device_resume, re_resume), 284 DEVMETHOD(device_shutdown, re_shutdown), 285 286 /* bus interface */ 287 DEVMETHOD(bus_print_child, bus_generic_print_child), 288 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 289 290 /* MII interface */ 291 DEVMETHOD(miibus_readreg, re_miibus_readreg), 292 DEVMETHOD(miibus_writereg, re_miibus_writereg), 293 DEVMETHOD(miibus_statchg, re_miibus_statchg), 294 295 { 0, 0 } 296 }; 297 298 static driver_t re_driver = { 299 "re", 300 re_methods, 301 sizeof(struct rl_softc) 302 }; 303 304 static devclass_t re_devclass; 305 306 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 307 DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0); 308 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 309 310 #define EE_SET(x) \ 311 CSR_WRITE_1(sc, RL_EECMD, \ 312 CSR_READ_1(sc, RL_EECMD) | x) 313 314 #define EE_CLR(x) \ 315 CSR_WRITE_1(sc, RL_EECMD, \ 316 CSR_READ_1(sc, RL_EECMD) & ~x) 317 318 /* 319 * Send a read command and address to the EEPROM, check for ACK. 320 */ 321 static void 322 re_eeprom_putbyte(struct rl_softc *sc, int addr) 323 { 324 int d, i; 325 326 d = addr | (RL_9346_READ << sc->rl_eewidth); 327 328 /* 329 * Feed in each bit and strobe the clock. 330 */ 331 332 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 333 if (d & i) { 334 EE_SET(RL_EE_DATAIN); 335 } else { 336 EE_CLR(RL_EE_DATAIN); 337 } 338 DELAY(100); 339 EE_SET(RL_EE_CLK); 340 DELAY(150); 341 EE_CLR(RL_EE_CLK); 342 DELAY(100); 343 } 344 } 345 346 /* 347 * Read a word of data stored in the EEPROM at address 'addr.' 348 */ 349 static void 350 re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest) 351 { 352 int i; 353 u_int16_t word = 0; 354 355 /* 356 * Send address of word we want to read. 357 */ 358 re_eeprom_putbyte(sc, addr); 359 360 /* 361 * Start reading bits from EEPROM. 362 */ 363 for (i = 0x8000; i; i >>= 1) { 364 EE_SET(RL_EE_CLK); 365 DELAY(100); 366 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 367 word |= i; 368 EE_CLR(RL_EE_CLK); 369 DELAY(100); 370 } 371 372 *dest = word; 373 } 374 375 /* 376 * Read a sequence of words from the EEPROM. 377 */ 378 static void 379 re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt) 380 { 381 int i; 382 u_int16_t word = 0, *ptr; 383 384 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 385 386 DELAY(100); 387 388 for (i = 0; i < cnt; i++) { 389 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 390 re_eeprom_getword(sc, off + i, &word); 391 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 392 ptr = (u_int16_t *)(dest + (i * 2)); 393 *ptr = word; 394 } 395 396 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 397 } 398 399 static int 400 re_gmii_readreg(device_t dev, int phy, int reg) 401 { 402 struct rl_softc *sc; 403 u_int32_t rval; 404 int i; 405 406 if (phy != 1) 407 return (0); 408 409 sc = device_get_softc(dev); 410 411 /* Let the rgephy driver read the GMEDIASTAT register */ 412 413 if (reg == RL_GMEDIASTAT) { 414 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 415 return (rval); 416 } 417 418 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 419 DELAY(1000); 420 421 for (i = 0; i < RL_TIMEOUT; i++) { 422 rval = CSR_READ_4(sc, RL_PHYAR); 423 if (rval & RL_PHYAR_BUSY) 424 break; 425 DELAY(100); 426 } 427 428 if (i == RL_TIMEOUT) { 429 device_printf(sc->rl_dev, "PHY read failed\n"); 430 return (0); 431 } 432 433 return (rval & RL_PHYAR_PHYDATA); 434 } 435 436 static int 437 re_gmii_writereg(device_t dev, int phy, int reg, int data) 438 { 439 struct rl_softc *sc; 440 u_int32_t rval; 441 int i; 442 443 sc = device_get_softc(dev); 444 445 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 446 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 447 DELAY(1000); 448 449 for (i = 0; i < RL_TIMEOUT; i++) { 450 rval = CSR_READ_4(sc, RL_PHYAR); 451 if (!(rval & RL_PHYAR_BUSY)) 452 break; 453 DELAY(100); 454 } 455 456 if (i == RL_TIMEOUT) { 457 device_printf(sc->rl_dev, "PHY write failed\n"); 458 return (0); 459 } 460 461 return (0); 462 } 463 464 static int 465 re_miibus_readreg(device_t dev, int phy, int reg) 466 { 467 struct rl_softc *sc; 468 u_int16_t rval = 0; 469 u_int16_t re8139_reg = 0; 470 471 sc = device_get_softc(dev); 472 473 if (sc->rl_type == RL_8169) { 474 rval = re_gmii_readreg(dev, phy, reg); 475 return (rval); 476 } 477 478 /* Pretend the internal PHY is only at address 0 */ 479 if (phy) { 480 return (0); 481 } 482 switch (reg) { 483 case MII_BMCR: 484 re8139_reg = RL_BMCR; 485 break; 486 case MII_BMSR: 487 re8139_reg = RL_BMSR; 488 break; 489 case MII_ANAR: 490 re8139_reg = RL_ANAR; 491 break; 492 case MII_ANER: 493 re8139_reg = RL_ANER; 494 break; 495 case MII_ANLPAR: 496 re8139_reg = RL_LPAR; 497 break; 498 case MII_PHYIDR1: 499 case MII_PHYIDR2: 500 return (0); 501 /* 502 * Allow the rlphy driver to read the media status 503 * register. If we have a link partner which does not 504 * support NWAY, this is the register which will tell 505 * us the results of parallel detection. 506 */ 507 case RL_MEDIASTAT: 508 rval = CSR_READ_1(sc, RL_MEDIASTAT); 509 return (rval); 510 default: 511 device_printf(sc->rl_dev, "bad phy register\n"); 512 return (0); 513 } 514 rval = CSR_READ_2(sc, re8139_reg); 515 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 516 /* 8139C+ has different bit layout. */ 517 rval &= ~(BMCR_LOOP | BMCR_ISO); 518 } 519 return (rval); 520 } 521 522 static int 523 re_miibus_writereg(device_t dev, int phy, int reg, int data) 524 { 525 struct rl_softc *sc; 526 u_int16_t re8139_reg = 0; 527 int rval = 0; 528 529 sc = device_get_softc(dev); 530 531 if (sc->rl_type == RL_8169) { 532 rval = re_gmii_writereg(dev, phy, reg, data); 533 return (rval); 534 } 535 536 /* Pretend the internal PHY is only at address 0 */ 537 if (phy) 538 return (0); 539 540 switch (reg) { 541 case MII_BMCR: 542 re8139_reg = RL_BMCR; 543 if (sc->rl_type == RL_8139CPLUS) { 544 /* 8139C+ has different bit layout. */ 545 data &= ~(BMCR_LOOP | BMCR_ISO); 546 } 547 break; 548 case MII_BMSR: 549 re8139_reg = RL_BMSR; 550 break; 551 case MII_ANAR: 552 re8139_reg = RL_ANAR; 553 break; 554 case MII_ANER: 555 re8139_reg = RL_ANER; 556 break; 557 case MII_ANLPAR: 558 re8139_reg = RL_LPAR; 559 break; 560 case MII_PHYIDR1: 561 case MII_PHYIDR2: 562 return (0); 563 break; 564 default: 565 device_printf(sc->rl_dev, "bad phy register\n"); 566 return (0); 567 } 568 CSR_WRITE_2(sc, re8139_reg, data); 569 return (0); 570 } 571 572 static void 573 re_miibus_statchg(device_t dev) 574 { 575 576 } 577 578 /* 579 * Program the 64-bit multicast hash filter. 580 */ 581 static void 582 re_setmulti(struct rl_softc *sc) 583 { 584 struct ifnet *ifp; 585 int h = 0; 586 u_int32_t hashes[2] = { 0, 0 }; 587 struct ifmultiaddr *ifma; 588 u_int32_t rxfilt; 589 int mcnt = 0; 590 591 RL_LOCK_ASSERT(sc); 592 593 ifp = sc->rl_ifp; 594 595 596 rxfilt = CSR_READ_4(sc, RL_RXCFG); 597 rxfilt &= ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_MULTI); 598 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 599 if (ifp->if_flags & IFF_PROMISC) 600 rxfilt |= RL_RXCFG_RX_ALLPHYS; 601 /* 602 * Unlike other hardwares, we have to explicitly set 603 * RL_RXCFG_RX_MULTI to receive multicast frames in 604 * promiscuous mode. 605 */ 606 rxfilt |= RL_RXCFG_RX_MULTI; 607 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 608 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 609 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 610 return; 611 } 612 613 /* first, zot all the existing hash bits */ 614 CSR_WRITE_4(sc, RL_MAR0, 0); 615 CSR_WRITE_4(sc, RL_MAR4, 0); 616 617 /* now program new ones */ 618 IF_ADDR_LOCK(ifp); 619 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 620 if (ifma->ifma_addr->sa_family != AF_LINK) 621 continue; 622 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 623 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 624 if (h < 32) 625 hashes[0] |= (1 << h); 626 else 627 hashes[1] |= (1 << (h - 32)); 628 mcnt++; 629 } 630 IF_ADDR_UNLOCK(ifp); 631 632 if (mcnt) 633 rxfilt |= RL_RXCFG_RX_MULTI; 634 else 635 rxfilt &= ~RL_RXCFG_RX_MULTI; 636 637 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 638 639 /* 640 * For some unfathomable reason, RealTek decided to reverse 641 * the order of the multicast hash registers in the PCI Express 642 * parts. This means we have to write the hash pattern in reverse 643 * order for those devices. 644 */ 645 646 if ((sc->rl_flags & RL_FLAG_INVMAR) != 0) { 647 CSR_WRITE_4(sc, RL_MAR0, bswap32(hashes[1])); 648 CSR_WRITE_4(sc, RL_MAR4, bswap32(hashes[0])); 649 } else { 650 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 651 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 652 } 653 } 654 655 static void 656 re_reset(struct rl_softc *sc) 657 { 658 int i; 659 660 RL_LOCK_ASSERT(sc); 661 662 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 663 664 for (i = 0; i < RL_TIMEOUT; i++) { 665 DELAY(10); 666 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 667 break; 668 } 669 if (i == RL_TIMEOUT) 670 device_printf(sc->rl_dev, "reset never completed!\n"); 671 672 CSR_WRITE_1(sc, 0x82, 1); 673 } 674 675 #ifdef RE_DIAG 676 677 /* 678 * The following routine is designed to test for a defect on some 679 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 680 * lines connected to the bus, however for a 32-bit only card, they 681 * should be pulled high. The result of this defect is that the 682 * NIC will not work right if you plug it into a 64-bit slot: DMA 683 * operations will be done with 64-bit transfers, which will fail 684 * because the 64-bit data lines aren't connected. 685 * 686 * There's no way to work around this (short of talking a soldering 687 * iron to the board), however we can detect it. The method we use 688 * here is to put the NIC into digital loopback mode, set the receiver 689 * to promiscuous mode, and then try to send a frame. We then compare 690 * the frame data we sent to what was received. If the data matches, 691 * then the NIC is working correctly, otherwise we know the user has 692 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 693 * slot. In the latter case, there's no way the NIC can work correctly, 694 * so we print out a message on the console and abort the device attach. 695 */ 696 697 static int 698 re_diag(struct rl_softc *sc) 699 { 700 struct ifnet *ifp = sc->rl_ifp; 701 struct mbuf *m0; 702 struct ether_header *eh; 703 struct rl_desc *cur_rx; 704 u_int16_t status; 705 u_int32_t rxstat; 706 int total_len, i, error = 0, phyaddr; 707 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 708 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 709 710 /* Allocate a single mbuf */ 711 MGETHDR(m0, M_DONTWAIT, MT_DATA); 712 if (m0 == NULL) 713 return (ENOBUFS); 714 715 RL_LOCK(sc); 716 717 /* 718 * Initialize the NIC in test mode. This sets the chip up 719 * so that it can send and receive frames, but performs the 720 * following special functions: 721 * - Puts receiver in promiscuous mode 722 * - Enables digital loopback mode 723 * - Leaves interrupts turned off 724 */ 725 726 ifp->if_flags |= IFF_PROMISC; 727 sc->rl_testmode = 1; 728 re_reset(sc); 729 re_init_locked(sc); 730 sc->rl_flags |= RL_FLAG_LINK; 731 if (sc->rl_type == RL_8169) 732 phyaddr = 1; 733 else 734 phyaddr = 0; 735 736 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 737 for (i = 0; i < RL_TIMEOUT; i++) { 738 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 739 if (!(status & BMCR_RESET)) 740 break; 741 } 742 743 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 744 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 745 746 DELAY(100000); 747 748 /* Put some data in the mbuf */ 749 750 eh = mtod(m0, struct ether_header *); 751 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 752 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 753 eh->ether_type = htons(ETHERTYPE_IP); 754 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 755 756 /* 757 * Queue the packet, start transmission. 758 * Note: IF_HANDOFF() ultimately calls re_start() for us. 759 */ 760 761 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 762 RL_UNLOCK(sc); 763 /* XXX: re_diag must not be called when in ALTQ mode */ 764 IF_HANDOFF(&ifp->if_snd, m0, ifp); 765 RL_LOCK(sc); 766 m0 = NULL; 767 768 /* Wait for it to propagate through the chip */ 769 770 DELAY(100000); 771 for (i = 0; i < RL_TIMEOUT; i++) { 772 status = CSR_READ_2(sc, RL_ISR); 773 CSR_WRITE_2(sc, RL_ISR, status); 774 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 775 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 776 break; 777 DELAY(10); 778 } 779 780 if (i == RL_TIMEOUT) { 781 device_printf(sc->rl_dev, 782 "diagnostic failed, failed to receive packet in" 783 " loopback mode\n"); 784 error = EIO; 785 goto done; 786 } 787 788 /* 789 * The packet should have been dumped into the first 790 * entry in the RX DMA ring. Grab it from there. 791 */ 792 793 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 794 sc->rl_ldata.rl_rx_list_map, 795 BUS_DMASYNC_POSTREAD); 796 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 797 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 798 BUS_DMASYNC_POSTREAD); 799 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 800 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 801 802 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 803 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 804 eh = mtod(m0, struct ether_header *); 805 806 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 807 total_len = RL_RXBYTES(cur_rx); 808 rxstat = le32toh(cur_rx->rl_cmdstat); 809 810 if (total_len != ETHER_MIN_LEN) { 811 device_printf(sc->rl_dev, 812 "diagnostic failed, received short packet\n"); 813 error = EIO; 814 goto done; 815 } 816 817 /* Test that the received packet data matches what we sent. */ 818 819 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 820 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 821 ntohs(eh->ether_type) != ETHERTYPE_IP) { 822 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 823 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 824 dst, ":", src, ":", ETHERTYPE_IP); 825 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 826 eh->ether_dhost, ":", eh->ether_shost, ":", 827 ntohs(eh->ether_type)); 828 device_printf(sc->rl_dev, "You may have a defective 32-bit " 829 "NIC plugged into a 64-bit PCI slot.\n"); 830 device_printf(sc->rl_dev, "Please re-install the NIC in a " 831 "32-bit slot for proper operation.\n"); 832 device_printf(sc->rl_dev, "Read the re(4) man page for more " 833 "details.\n"); 834 error = EIO; 835 } 836 837 done: 838 /* Turn interface off, release resources */ 839 840 sc->rl_testmode = 0; 841 sc->rl_flags &= ~RL_FLAG_LINK; 842 ifp->if_flags &= ~IFF_PROMISC; 843 re_stop(sc); 844 if (m0 != NULL) 845 m_freem(m0); 846 847 RL_UNLOCK(sc); 848 849 return (error); 850 } 851 852 #endif 853 854 /* 855 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 856 * IDs against our list and return a device name if we find a match. 857 */ 858 static int 859 re_probe(device_t dev) 860 { 861 struct rl_type *t; 862 uint16_t devid, vendor; 863 uint16_t revid, sdevid; 864 int i; 865 866 vendor = pci_get_vendor(dev); 867 devid = pci_get_device(dev); 868 revid = pci_get_revid(dev); 869 sdevid = pci_get_subdevice(dev); 870 871 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 872 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 873 /* 874 * Only attach to rev. 3 of the Linksys EG1032 adapter. 875 * Rev. 2 is supported by sk(4). 876 */ 877 return (ENXIO); 878 } 879 } 880 881 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 882 if (revid != 0x20) { 883 /* 8139, let rl(4) take care of this device. */ 884 return (ENXIO); 885 } 886 } 887 888 t = re_devs; 889 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) { 890 if (vendor == t->rl_vid && devid == t->rl_did) { 891 device_set_desc(dev, t->rl_name); 892 return (BUS_PROBE_DEFAULT); 893 } 894 } 895 896 return (ENXIO); 897 } 898 899 /* 900 * Map a single buffer address. 901 */ 902 903 static void 904 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 905 { 906 bus_addr_t *addr; 907 908 if (error) 909 return; 910 911 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 912 addr = arg; 913 *addr = segs->ds_addr; 914 } 915 916 static int 917 re_allocmem(device_t dev, struct rl_softc *sc) 918 { 919 bus_size_t rx_list_size, tx_list_size; 920 int error; 921 int i; 922 923 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 924 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 925 926 /* 927 * Allocate the parent bus DMA tag appropriate for PCI. 928 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD 929 * register should be set. However some RealTek chips are known 930 * to be buggy on DAC handling, therefore disable DAC by limiting 931 * DMA address space to 32bit. PCIe variants of RealTek chips 932 * may not have the limitation but I took safer path. 933 */ 934 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 935 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 936 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 937 NULL, NULL, &sc->rl_parent_tag); 938 if (error) { 939 device_printf(dev, "could not allocate parent DMA tag\n"); 940 return (error); 941 } 942 943 /* 944 * Allocate map for TX mbufs. 945 */ 946 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 947 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 948 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 949 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 950 if (error) { 951 device_printf(dev, "could not allocate TX DMA tag\n"); 952 return (error); 953 } 954 955 /* 956 * Allocate map for RX mbufs. 957 */ 958 959 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 960 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 961 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 962 if (error) { 963 device_printf(dev, "could not allocate RX DMA tag\n"); 964 return (error); 965 } 966 967 /* 968 * Allocate map for TX descriptor list. 969 */ 970 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 971 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 972 NULL, tx_list_size, 1, tx_list_size, 0, 973 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 974 if (error) { 975 device_printf(dev, "could not allocate TX DMA ring tag\n"); 976 return (error); 977 } 978 979 /* Allocate DMA'able memory for the TX ring */ 980 981 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 982 (void **)&sc->rl_ldata.rl_tx_list, 983 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 984 &sc->rl_ldata.rl_tx_list_map); 985 if (error) { 986 device_printf(dev, "could not allocate TX DMA ring\n"); 987 return (error); 988 } 989 990 /* Load the map for the TX ring. */ 991 992 sc->rl_ldata.rl_tx_list_addr = 0; 993 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 994 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 995 tx_list_size, re_dma_map_addr, 996 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 997 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 998 device_printf(dev, "could not load TX DMA ring\n"); 999 return (ENOMEM); 1000 } 1001 1002 /* Create DMA maps for TX buffers */ 1003 1004 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1005 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1006 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1007 if (error) { 1008 device_printf(dev, "could not create DMA map for TX\n"); 1009 return (error); 1010 } 1011 } 1012 1013 /* 1014 * Allocate map for RX descriptor list. 1015 */ 1016 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1017 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1018 NULL, rx_list_size, 1, rx_list_size, 0, 1019 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1020 if (error) { 1021 device_printf(dev, "could not create RX DMA ring tag\n"); 1022 return (error); 1023 } 1024 1025 /* Allocate DMA'able memory for the RX ring */ 1026 1027 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1028 (void **)&sc->rl_ldata.rl_rx_list, 1029 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1030 &sc->rl_ldata.rl_rx_list_map); 1031 if (error) { 1032 device_printf(dev, "could not allocate RX DMA ring\n"); 1033 return (error); 1034 } 1035 1036 /* Load the map for the RX ring. */ 1037 1038 sc->rl_ldata.rl_rx_list_addr = 0; 1039 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1040 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1041 rx_list_size, re_dma_map_addr, 1042 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1043 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1044 device_printf(dev, "could not load RX DMA ring\n"); 1045 return (ENOMEM); 1046 } 1047 1048 /* Create DMA maps for RX buffers */ 1049 1050 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1051 &sc->rl_ldata.rl_rx_sparemap); 1052 if (error) { 1053 device_printf(dev, "could not create spare DMA map for RX\n"); 1054 return (error); 1055 } 1056 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1057 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1058 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1059 if (error) { 1060 device_printf(dev, "could not create DMA map for RX\n"); 1061 return (error); 1062 } 1063 } 1064 1065 return (0); 1066 } 1067 1068 /* 1069 * Attach the interface. Allocate softc structures, do ifmedia 1070 * setup and ethernet/BPF attach. 1071 */ 1072 static int 1073 re_attach(device_t dev) 1074 { 1075 u_char eaddr[ETHER_ADDR_LEN]; 1076 u_int16_t as[ETHER_ADDR_LEN / 2]; 1077 struct rl_softc *sc; 1078 struct ifnet *ifp; 1079 struct rl_hwrev *hw_rev; 1080 int hwrev; 1081 u_int16_t devid, re_did = 0; 1082 int error = 0, rid, i; 1083 int msic, reg; 1084 uint8_t cfg; 1085 1086 sc = device_get_softc(dev); 1087 sc->rl_dev = dev; 1088 1089 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1090 MTX_DEF); 1091 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1092 1093 /* 1094 * Map control/status registers. 1095 */ 1096 pci_enable_busmaster(dev); 1097 1098 devid = pci_get_device(dev); 1099 /* Prefer memory space register mapping over IO space. */ 1100 sc->rl_res_id = PCIR_BAR(1); 1101 sc->rl_res_type = SYS_RES_MEMORY; 1102 /* RTL8168/8101E seems to use different BARs. */ 1103 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E) 1104 sc->rl_res_id = PCIR_BAR(2); 1105 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1106 &sc->rl_res_id, RF_ACTIVE); 1107 1108 if (sc->rl_res == NULL) { 1109 sc->rl_res_id = PCIR_BAR(0); 1110 sc->rl_res_type = SYS_RES_IOPORT; 1111 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1112 &sc->rl_res_id, RF_ACTIVE); 1113 if (sc->rl_res == NULL) { 1114 device_printf(dev, "couldn't map ports/memory\n"); 1115 error = ENXIO; 1116 goto fail; 1117 } 1118 } 1119 1120 sc->rl_btag = rman_get_bustag(sc->rl_res); 1121 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1122 1123 msic = 0; 1124 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 1125 msic = pci_msi_count(dev); 1126 if (bootverbose) 1127 device_printf(dev, "MSI count : %d\n", msic); 1128 } 1129 if (msic == RL_MSI_MESSAGES && msi_disable == 0) { 1130 if (pci_alloc_msi(dev, &msic) == 0) { 1131 if (msic == RL_MSI_MESSAGES) { 1132 device_printf(dev, "Using %d MSI messages\n", 1133 msic); 1134 sc->rl_flags |= RL_FLAG_MSI; 1135 /* Explicitly set MSI enable bit. */ 1136 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1137 cfg = CSR_READ_1(sc, RL_CFG2); 1138 cfg |= RL_CFG2_MSI; 1139 CSR_WRITE_1(sc, RL_CFG2, cfg); 1140 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1141 } else 1142 pci_release_msi(dev); 1143 } 1144 } 1145 1146 /* Allocate interrupt */ 1147 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1148 rid = 0; 1149 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1150 RF_SHAREABLE | RF_ACTIVE); 1151 if (sc->rl_irq[0] == NULL) { 1152 device_printf(dev, "couldn't allocate IRQ resources\n"); 1153 error = ENXIO; 1154 goto fail; 1155 } 1156 } else { 1157 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1158 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1159 SYS_RES_IRQ, &rid, RF_ACTIVE); 1160 if (sc->rl_irq[i] == NULL) { 1161 device_printf(dev, 1162 "couldn't llocate IRQ resources for " 1163 "message %d\n", rid); 1164 error = ENXIO; 1165 goto fail; 1166 } 1167 } 1168 } 1169 1170 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1171 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1172 cfg = CSR_READ_1(sc, RL_CFG2); 1173 if ((cfg & RL_CFG2_MSI) != 0) { 1174 device_printf(dev, "turning off MSI enable bit.\n"); 1175 cfg &= ~RL_CFG2_MSI; 1176 CSR_WRITE_1(sc, RL_CFG2, cfg); 1177 } 1178 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1179 } 1180 1181 /* Reset the adapter. */ 1182 RL_LOCK(sc); 1183 re_reset(sc); 1184 RL_UNLOCK(sc); 1185 1186 hw_rev = re_hwrevs; 1187 hwrev = CSR_READ_4(sc, RL_TXCFG); 1188 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000); 1189 device_printf(dev, "MAC rev. 0x%08x\n", hwrev & 0x00700000); 1190 hwrev &= RL_TXCFG_HWREV; 1191 while (hw_rev->rl_desc != NULL) { 1192 if (hw_rev->rl_rev == hwrev) { 1193 sc->rl_type = hw_rev->rl_type; 1194 break; 1195 } 1196 hw_rev++; 1197 } 1198 if (hw_rev->rl_desc == NULL) { 1199 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev); 1200 error = ENXIO; 1201 goto fail; 1202 } 1203 1204 switch (hw_rev->rl_rev) { 1205 case RL_HWREV_8139CPLUS: 1206 sc->rl_flags |= RL_FLAG_NOJUMBO; 1207 break; 1208 case RL_HWREV_8100E: 1209 case RL_HWREV_8101E: 1210 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_INVMAR | 1211 RL_FLAG_PHYWAKE; 1212 break; 1213 case RL_HWREV_8102E: 1214 case RL_HWREV_8102EL: 1215 sc->rl_flags |= RL_FLAG_NOJUMBO | RL_FLAG_INVMAR | 1216 RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1217 RL_FLAG_MACSTAT; 1218 break; 1219 case RL_HWREV_8168_SPIN1: 1220 case RL_HWREV_8168_SPIN2: 1221 case RL_HWREV_8168_SPIN3: 1222 sc->rl_flags |= RL_FLAG_INVMAR | RL_FLAG_PHYWAKE | 1223 RL_FLAG_MACSTAT; 1224 break; 1225 case RL_HWREV_8168C: 1226 case RL_HWREV_8168C_SPIN2: 1227 case RL_HWREV_8168CP: 1228 sc->rl_flags |= RL_FLAG_INVMAR | RL_FLAG_PHYWAKE | 1229 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT; 1230 /* 1231 * These controllers support jumbo frame but it seems 1232 * that enabling it requires touching additional magic 1233 * registers. Depending on MAC revisions some 1234 * controllers need to disable checksum offload. So 1235 * disable jumbo frame until I have better idea what 1236 * it really requires to make it support. 1237 * RTL8168C/CP : supports up to 6KB jumbo frame. 1238 * RTL8111C/CP : supports up to 9KB jumbo frame. 1239 */ 1240 sc->rl_flags |= RL_FLAG_NOJUMBO; 1241 break; 1242 case RL_HWREV_8169_8110SB: 1243 case RL_HWREV_8169_8110SC: 1244 case RL_HWREV_8169_8110SBL: 1245 sc->rl_flags |= RL_FLAG_PHYWAKE; 1246 break; 1247 default: 1248 break; 1249 } 1250 1251 /* Enable PME. */ 1252 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1253 cfg = CSR_READ_1(sc, RL_CFG1); 1254 cfg |= RL_CFG1_PME; 1255 CSR_WRITE_1(sc, RL_CFG1, cfg); 1256 cfg = CSR_READ_1(sc, RL_CFG5); 1257 cfg &= RL_CFG5_PME_STS; 1258 CSR_WRITE_1(sc, RL_CFG5, cfg); 1259 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1260 1261 if ((sc->rl_flags & RL_FLAG_PAR) != 0) { 1262 /* 1263 * XXX Should have a better way to extract station 1264 * address from EEPROM. 1265 */ 1266 for (i = 0; i < ETHER_ADDR_LEN; i++) 1267 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1268 } else { 1269 sc->rl_eewidth = RL_9356_ADDR_LEN; 1270 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1271 if (re_did != 0x8129) 1272 sc->rl_eewidth = RL_9346_ADDR_LEN; 1273 1274 /* 1275 * Get station address from the EEPROM. 1276 */ 1277 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1278 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1279 as[i] = le16toh(as[i]); 1280 bcopy(as, eaddr, sizeof(eaddr)); 1281 } 1282 1283 if (sc->rl_type == RL_8169) { 1284 /* Set RX length mask and number of descriptors. */ 1285 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1286 sc->rl_txstart = RL_GTXSTART; 1287 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1288 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1289 } else { 1290 /* Set RX length mask and number of descriptors. */ 1291 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1292 sc->rl_txstart = RL_TXSTART; 1293 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1294 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1295 } 1296 1297 error = re_allocmem(dev, sc); 1298 if (error) 1299 goto fail; 1300 1301 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1302 if (ifp == NULL) { 1303 device_printf(dev, "can not if_alloc()\n"); 1304 error = ENOSPC; 1305 goto fail; 1306 } 1307 1308 /* Take PHY out of power down mode. */ 1309 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) { 1310 re_gmii_writereg(dev, 1, 0x1f, 0); 1311 re_gmii_writereg(dev, 1, 0x0e, 0); 1312 } 1313 1314 /* Do MII setup */ 1315 if (mii_phy_probe(dev, &sc->rl_miibus, 1316 re_ifmedia_upd, re_ifmedia_sts)) { 1317 device_printf(dev, "MII without any phy!\n"); 1318 error = ENXIO; 1319 goto fail; 1320 } 1321 1322 ifp->if_softc = sc; 1323 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1324 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1325 ifp->if_ioctl = re_ioctl; 1326 ifp->if_start = re_start; 1327 ifp->if_hwassist = RE_CSUM_FEATURES; 1328 ifp->if_capabilities = IFCAP_HWCSUM; 1329 ifp->if_capenable = ifp->if_capabilities; 1330 ifp->if_init = re_init; 1331 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1332 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1333 IFQ_SET_READY(&ifp->if_snd); 1334 1335 TASK_INIT(&sc->rl_txtask, 1, re_tx_task, ifp); 1336 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1337 1338 /* 1339 * XXX 1340 * Still have no idea how to make TSO work on 8168C, 8168CP, 1341 * 8111C and 8111CP. 1342 */ 1343 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 1344 ifp->if_hwassist |= CSUM_TSO; 1345 ifp->if_capabilities |= IFCAP_TSO4; 1346 } 1347 1348 /* 1349 * Call MI attach routine. 1350 */ 1351 ether_ifattach(ifp, eaddr); 1352 1353 /* VLAN capability setup */ 1354 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1355 if (ifp->if_capabilities & IFCAP_HWCSUM) 1356 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1357 /* Enable WOL if PM is supported. */ 1358 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, ®) == 0) 1359 ifp->if_capabilities |= IFCAP_WOL; 1360 ifp->if_capenable = ifp->if_capabilities; 1361 /* 1362 * Don't enable TSO by default. Under certain 1363 * circumtances the controller generated corrupted 1364 * packets in TSO size. 1365 */ 1366 ifp->if_hwassist &= ~CSUM_TSO; 1367 ifp->if_capenable &= ~IFCAP_TSO4; 1368 #ifdef DEVICE_POLLING 1369 ifp->if_capabilities |= IFCAP_POLLING; 1370 #endif 1371 /* 1372 * Tell the upper layer(s) we support long frames. 1373 * Must appear after the call to ether_ifattach() because 1374 * ether_ifattach() sets ifi_hdrlen to the default value. 1375 */ 1376 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1377 1378 #ifdef RE_DIAG 1379 /* 1380 * Perform hardware diagnostic on the original RTL8169. 1381 * Some 32-bit cards were incorrectly wired and would 1382 * malfunction if plugged into a 64-bit slot. 1383 */ 1384 1385 if (hwrev == RL_HWREV_8169) { 1386 error = re_diag(sc); 1387 if (error) { 1388 device_printf(dev, 1389 "attach aborted due to hardware diag failure\n"); 1390 ether_ifdetach(ifp); 1391 goto fail; 1392 } 1393 } 1394 #endif 1395 1396 /* Hook interrupt last to avoid having to lock softc */ 1397 if ((sc->rl_flags & RL_FLAG_MSI) == 0) 1398 error = bus_setup_intr(dev, sc->rl_irq[0], 1399 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1400 &sc->rl_intrhand[0]); 1401 else { 1402 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1403 error = bus_setup_intr(dev, sc->rl_irq[i], 1404 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1405 &sc->rl_intrhand[i]); 1406 if (error != 0) 1407 break; 1408 } 1409 } 1410 if (error) { 1411 device_printf(dev, "couldn't set up irq\n"); 1412 ether_ifdetach(ifp); 1413 } 1414 1415 fail: 1416 1417 if (error) 1418 re_detach(dev); 1419 1420 return (error); 1421 } 1422 1423 /* 1424 * Shutdown hardware and free up resources. This can be called any 1425 * time after the mutex has been initialized. It is called in both 1426 * the error case in attach and the normal detach case so it needs 1427 * to be careful about only freeing resources that have actually been 1428 * allocated. 1429 */ 1430 static int 1431 re_detach(device_t dev) 1432 { 1433 struct rl_softc *sc; 1434 struct ifnet *ifp; 1435 int i, rid; 1436 1437 sc = device_get_softc(dev); 1438 ifp = sc->rl_ifp; 1439 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1440 1441 /* These should only be active if attach succeeded */ 1442 if (device_is_attached(dev)) { 1443 #ifdef DEVICE_POLLING 1444 if (ifp->if_capenable & IFCAP_POLLING) 1445 ether_poll_deregister(ifp); 1446 #endif 1447 RL_LOCK(sc); 1448 #if 0 1449 sc->suspended = 1; 1450 #endif 1451 re_stop(sc); 1452 RL_UNLOCK(sc); 1453 callout_drain(&sc->rl_stat_callout); 1454 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1455 taskqueue_drain(taskqueue_fast, &sc->rl_txtask); 1456 /* 1457 * Force off the IFF_UP flag here, in case someone 1458 * still had a BPF descriptor attached to this 1459 * interface. If they do, ether_ifdetach() will cause 1460 * the BPF code to try and clear the promisc mode 1461 * flag, which will bubble down to re_ioctl(), 1462 * which will try to call re_init() again. This will 1463 * turn the NIC back on and restart the MII ticker, 1464 * which will panic the system when the kernel tries 1465 * to invoke the re_tick() function that isn't there 1466 * anymore. 1467 */ 1468 ifp->if_flags &= ~IFF_UP; 1469 ether_ifdetach(ifp); 1470 } 1471 if (sc->rl_miibus) 1472 device_delete_child(dev, sc->rl_miibus); 1473 bus_generic_detach(dev); 1474 1475 /* 1476 * The rest is resource deallocation, so we should already be 1477 * stopped here. 1478 */ 1479 1480 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1481 if (sc->rl_intrhand[i] != NULL) { 1482 bus_teardown_intr(dev, sc->rl_irq[i], 1483 sc->rl_intrhand[i]); 1484 sc->rl_intrhand[i] = NULL; 1485 } 1486 } 1487 if (ifp != NULL) 1488 if_free(ifp); 1489 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1490 if (sc->rl_irq[0] != NULL) { 1491 bus_release_resource(dev, SYS_RES_IRQ, 0, 1492 sc->rl_irq[0]); 1493 sc->rl_irq[0] = NULL; 1494 } 1495 } else { 1496 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1497 if (sc->rl_irq[i] != NULL) { 1498 bus_release_resource(dev, SYS_RES_IRQ, rid, 1499 sc->rl_irq[i]); 1500 sc->rl_irq[i] = NULL; 1501 } 1502 } 1503 pci_release_msi(dev); 1504 } 1505 if (sc->rl_res) 1506 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, 1507 sc->rl_res); 1508 1509 /* Unload and free the RX DMA ring memory and map */ 1510 1511 if (sc->rl_ldata.rl_rx_list_tag) { 1512 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1513 sc->rl_ldata.rl_rx_list_map); 1514 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1515 sc->rl_ldata.rl_rx_list, 1516 sc->rl_ldata.rl_rx_list_map); 1517 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1518 } 1519 1520 /* Unload and free the TX DMA ring memory and map */ 1521 1522 if (sc->rl_ldata.rl_tx_list_tag) { 1523 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1524 sc->rl_ldata.rl_tx_list_map); 1525 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1526 sc->rl_ldata.rl_tx_list, 1527 sc->rl_ldata.rl_tx_list_map); 1528 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1529 } 1530 1531 /* Destroy all the RX and TX buffer maps */ 1532 1533 if (sc->rl_ldata.rl_tx_mtag) { 1534 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1535 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1536 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1537 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1538 } 1539 if (sc->rl_ldata.rl_rx_mtag) { 1540 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) 1541 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1542 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1543 if (sc->rl_ldata.rl_rx_sparemap) 1544 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1545 sc->rl_ldata.rl_rx_sparemap); 1546 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1547 } 1548 1549 /* Unload and free the stats buffer and map */ 1550 1551 if (sc->rl_ldata.rl_stag) { 1552 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1553 sc->rl_ldata.rl_rx_list_map); 1554 bus_dmamem_free(sc->rl_ldata.rl_stag, 1555 sc->rl_ldata.rl_stats, 1556 sc->rl_ldata.rl_smap); 1557 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1558 } 1559 1560 if (sc->rl_parent_tag) 1561 bus_dma_tag_destroy(sc->rl_parent_tag); 1562 1563 mtx_destroy(&sc->rl_mtx); 1564 1565 return (0); 1566 } 1567 1568 static __inline void 1569 re_discard_rxbuf(struct rl_softc *sc, int idx) 1570 { 1571 struct rl_desc *desc; 1572 struct rl_rxdesc *rxd; 1573 uint32_t cmdstat; 1574 1575 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1576 desc = &sc->rl_ldata.rl_rx_list[idx]; 1577 desc->rl_vlanctl = 0; 1578 cmdstat = rxd->rx_size; 1579 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1580 cmdstat |= RL_RDESC_CMD_EOR; 1581 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1582 } 1583 1584 static int 1585 re_newbuf(struct rl_softc *sc, int idx) 1586 { 1587 struct mbuf *m; 1588 struct rl_rxdesc *rxd; 1589 bus_dma_segment_t segs[1]; 1590 bus_dmamap_t map; 1591 struct rl_desc *desc; 1592 uint32_t cmdstat; 1593 int error, nsegs; 1594 1595 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1596 if (m == NULL) 1597 return (ENOBUFS); 1598 1599 m->m_len = m->m_pkthdr.len = MCLBYTES; 1600 #ifdef RE_FIXUP_RX 1601 /* 1602 * This is part of an evil trick to deal with non-x86 platforms. 1603 * The RealTek chip requires RX buffers to be aligned on 64-bit 1604 * boundaries, but that will hose non-x86 machines. To get around 1605 * this, we leave some empty space at the start of each buffer 1606 * and for non-x86 hosts, we copy the buffer back six bytes 1607 * to achieve word alignment. This is slightly more efficient 1608 * than allocating a new buffer, copying the contents, and 1609 * discarding the old buffer. 1610 */ 1611 m_adj(m, RE_ETHER_ALIGN); 1612 #endif 1613 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1614 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1615 if (error != 0) { 1616 m_freem(m); 1617 return (ENOBUFS); 1618 } 1619 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1620 1621 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1622 if (rxd->rx_m != NULL) { 1623 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1624 BUS_DMASYNC_POSTREAD); 1625 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1626 } 1627 1628 rxd->rx_m = m; 1629 map = rxd->rx_dmamap; 1630 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1631 rxd->rx_size = segs[0].ds_len; 1632 sc->rl_ldata.rl_rx_sparemap = map; 1633 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1634 BUS_DMASYNC_PREREAD); 1635 1636 desc = &sc->rl_ldata.rl_rx_list[idx]; 1637 desc->rl_vlanctl = 0; 1638 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1639 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1640 cmdstat = segs[0].ds_len; 1641 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1642 cmdstat |= RL_RDESC_CMD_EOR; 1643 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1644 1645 return (0); 1646 } 1647 1648 #ifdef RE_FIXUP_RX 1649 static __inline void 1650 re_fixup_rx(struct mbuf *m) 1651 { 1652 int i; 1653 uint16_t *src, *dst; 1654 1655 src = mtod(m, uint16_t *); 1656 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1657 1658 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1659 *dst++ = *src++; 1660 1661 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1662 } 1663 #endif 1664 1665 static int 1666 re_tx_list_init(struct rl_softc *sc) 1667 { 1668 struct rl_desc *desc; 1669 int i; 1670 1671 RL_LOCK_ASSERT(sc); 1672 1673 bzero(sc->rl_ldata.rl_tx_list, 1674 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 1675 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1676 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 1677 /* Set EOR. */ 1678 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 1679 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 1680 1681 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1682 sc->rl_ldata.rl_tx_list_map, 1683 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1684 1685 sc->rl_ldata.rl_tx_prodidx = 0; 1686 sc->rl_ldata.rl_tx_considx = 0; 1687 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 1688 1689 return (0); 1690 } 1691 1692 static int 1693 re_rx_list_init(struct rl_softc *sc) 1694 { 1695 int error, i; 1696 1697 bzero(sc->rl_ldata.rl_rx_list, 1698 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 1699 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1700 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 1701 if ((error = re_newbuf(sc, i)) != 0) 1702 return (error); 1703 } 1704 1705 /* Flush the RX descriptors */ 1706 1707 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1708 sc->rl_ldata.rl_rx_list_map, 1709 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1710 1711 sc->rl_ldata.rl_rx_prodidx = 0; 1712 sc->rl_head = sc->rl_tail = NULL; 1713 1714 return (0); 1715 } 1716 1717 /* 1718 * RX handler for C+ and 8169. For the gigE chips, we support 1719 * the reception of jumbo frames that have been fragmented 1720 * across multiple 2K mbuf cluster buffers. 1721 */ 1722 static int 1723 re_rxeof(struct rl_softc *sc) 1724 { 1725 struct mbuf *m; 1726 struct ifnet *ifp; 1727 int i, total_len; 1728 struct rl_desc *cur_rx; 1729 u_int32_t rxstat, rxvlan; 1730 int maxpkt = 16; 1731 1732 RL_LOCK_ASSERT(sc); 1733 1734 ifp = sc->rl_ifp; 1735 1736 /* Invalidate the descriptor memory */ 1737 1738 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1739 sc->rl_ldata.rl_rx_list_map, 1740 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1741 1742 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 1743 i = RL_RX_DESC_NXT(sc, i)) { 1744 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1745 rxstat = le32toh(cur_rx->rl_cmdstat); 1746 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 1747 break; 1748 total_len = rxstat & sc->rl_rxlenmask; 1749 rxvlan = le32toh(cur_rx->rl_vlanctl); 1750 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 1751 1752 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1753 if (re_newbuf(sc, i) != 0) { 1754 /* 1755 * If this is part of a multi-fragment packet, 1756 * discard all the pieces. 1757 */ 1758 if (sc->rl_head != NULL) { 1759 m_freem(sc->rl_head); 1760 sc->rl_head = sc->rl_tail = NULL; 1761 } 1762 re_discard_rxbuf(sc, i); 1763 continue; 1764 } 1765 m->m_len = RE_RX_DESC_BUFLEN; 1766 if (sc->rl_head == NULL) 1767 sc->rl_head = sc->rl_tail = m; 1768 else { 1769 m->m_flags &= ~M_PKTHDR; 1770 sc->rl_tail->m_next = m; 1771 sc->rl_tail = m; 1772 } 1773 continue; 1774 } 1775 1776 /* 1777 * NOTE: for the 8139C+, the frame length field 1778 * is always 12 bits in size, but for the gigE chips, 1779 * it is 13 bits (since the max RX frame length is 16K). 1780 * Unfortunately, all 32 bits in the status word 1781 * were already used, so to make room for the extra 1782 * length bit, RealTek took out the 'frame alignment 1783 * error' bit and shifted the other status bits 1784 * over one slot. The OWN, EOR, FS and LS bits are 1785 * still in the same places. We have already extracted 1786 * the frame length and checked the OWN bit, so rather 1787 * than using an alternate bit mapping, we shift the 1788 * status bits one space to the right so we can evaluate 1789 * them using the 8169 status as though it was in the 1790 * same format as that of the 8139C+. 1791 */ 1792 if (sc->rl_type == RL_8169) 1793 rxstat >>= 1; 1794 1795 /* 1796 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 1797 * set, but if CRC is clear, it will still be a valid frame. 1798 */ 1799 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 && 1800 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) { 1801 ifp->if_ierrors++; 1802 /* 1803 * If this is part of a multi-fragment packet, 1804 * discard all the pieces. 1805 */ 1806 if (sc->rl_head != NULL) { 1807 m_freem(sc->rl_head); 1808 sc->rl_head = sc->rl_tail = NULL; 1809 } 1810 re_discard_rxbuf(sc, i); 1811 continue; 1812 } 1813 1814 /* 1815 * If allocating a replacement mbuf fails, 1816 * reload the current one. 1817 */ 1818 1819 if (re_newbuf(sc, i) != 0) { 1820 ifp->if_iqdrops++; 1821 if (sc->rl_head != NULL) { 1822 m_freem(sc->rl_head); 1823 sc->rl_head = sc->rl_tail = NULL; 1824 } 1825 re_discard_rxbuf(sc, i); 1826 continue; 1827 } 1828 1829 if (sc->rl_head != NULL) { 1830 m->m_len = total_len % RE_RX_DESC_BUFLEN; 1831 if (m->m_len == 0) 1832 m->m_len = RE_RX_DESC_BUFLEN; 1833 /* 1834 * Special case: if there's 4 bytes or less 1835 * in this buffer, the mbuf can be discarded: 1836 * the last 4 bytes is the CRC, which we don't 1837 * care about anyway. 1838 */ 1839 if (m->m_len <= ETHER_CRC_LEN) { 1840 sc->rl_tail->m_len -= 1841 (ETHER_CRC_LEN - m->m_len); 1842 m_freem(m); 1843 } else { 1844 m->m_len -= ETHER_CRC_LEN; 1845 m->m_flags &= ~M_PKTHDR; 1846 sc->rl_tail->m_next = m; 1847 } 1848 m = sc->rl_head; 1849 sc->rl_head = sc->rl_tail = NULL; 1850 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1851 } else 1852 m->m_pkthdr.len = m->m_len = 1853 (total_len - ETHER_CRC_LEN); 1854 1855 #ifdef RE_FIXUP_RX 1856 re_fixup_rx(m); 1857 #endif 1858 ifp->if_ipackets++; 1859 m->m_pkthdr.rcvif = ifp; 1860 1861 /* Do RX checksumming if enabled */ 1862 1863 if (ifp->if_capenable & IFCAP_RXCSUM) { 1864 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 1865 /* Check IP header checksum */ 1866 if (rxstat & RL_RDESC_STAT_PROTOID) 1867 m->m_pkthdr.csum_flags |= 1868 CSUM_IP_CHECKED; 1869 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1870 m->m_pkthdr.csum_flags |= 1871 CSUM_IP_VALID; 1872 1873 /* Check TCP/UDP checksum */ 1874 if ((RL_TCPPKT(rxstat) && 1875 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1876 (RL_UDPPKT(rxstat) && 1877 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1878 m->m_pkthdr.csum_flags |= 1879 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1880 m->m_pkthdr.csum_data = 0xffff; 1881 } 1882 } else { 1883 /* 1884 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP 1885 */ 1886 if ((rxstat & RL_RDESC_STAT_PROTOID) && 1887 (rxvlan & RL_RDESC_IPV4)) 1888 m->m_pkthdr.csum_flags |= 1889 CSUM_IP_CHECKED; 1890 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) && 1891 (rxvlan & RL_RDESC_IPV4)) 1892 m->m_pkthdr.csum_flags |= 1893 CSUM_IP_VALID; 1894 if (((rxstat & RL_RDESC_STAT_TCP) && 1895 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1896 ((rxstat & RL_RDESC_STAT_UDP) && 1897 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1898 m->m_pkthdr.csum_flags |= 1899 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1900 m->m_pkthdr.csum_data = 0xffff; 1901 } 1902 } 1903 } 1904 maxpkt--; 1905 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 1906 m->m_pkthdr.ether_vtag = 1907 bswap16((rxvlan & RL_RDESC_VLANCTL_DATA)); 1908 m->m_flags |= M_VLANTAG; 1909 } 1910 RL_UNLOCK(sc); 1911 (*ifp->if_input)(ifp, m); 1912 RL_LOCK(sc); 1913 } 1914 1915 /* Flush the RX DMA ring */ 1916 1917 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1918 sc->rl_ldata.rl_rx_list_map, 1919 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1920 1921 sc->rl_ldata.rl_rx_prodidx = i; 1922 1923 if (maxpkt) 1924 return(EAGAIN); 1925 1926 return(0); 1927 } 1928 1929 static void 1930 re_txeof(struct rl_softc *sc) 1931 { 1932 struct ifnet *ifp; 1933 struct rl_txdesc *txd; 1934 u_int32_t txstat; 1935 int cons; 1936 1937 cons = sc->rl_ldata.rl_tx_considx; 1938 if (cons == sc->rl_ldata.rl_tx_prodidx) 1939 return; 1940 1941 ifp = sc->rl_ifp; 1942 /* Invalidate the TX descriptor list */ 1943 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1944 sc->rl_ldata.rl_tx_list_map, 1945 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1946 1947 for (; cons != sc->rl_ldata.rl_tx_prodidx; 1948 cons = RL_TX_DESC_NXT(sc, cons)) { 1949 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 1950 if (txstat & RL_TDESC_STAT_OWN) 1951 break; 1952 /* 1953 * We only stash mbufs in the last descriptor 1954 * in a fragment chain, which also happens to 1955 * be the only place where the TX status bits 1956 * are valid. 1957 */ 1958 if (txstat & RL_TDESC_CMD_EOF) { 1959 txd = &sc->rl_ldata.rl_tx_desc[cons]; 1960 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 1961 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 1962 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 1963 txd->tx_dmamap); 1964 KASSERT(txd->tx_m != NULL, 1965 ("%s: freeing NULL mbufs!", __func__)); 1966 m_freem(txd->tx_m); 1967 txd->tx_m = NULL; 1968 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 1969 RL_TDESC_STAT_COLCNT)) 1970 ifp->if_collisions++; 1971 if (txstat & RL_TDESC_STAT_TXERRSUM) 1972 ifp->if_oerrors++; 1973 else 1974 ifp->if_opackets++; 1975 } 1976 sc->rl_ldata.rl_tx_free++; 1977 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1978 } 1979 sc->rl_ldata.rl_tx_considx = cons; 1980 1981 /* No changes made to the TX ring, so no flush needed */ 1982 1983 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 1984 /* 1985 * Some chips will ignore a second TX request issued 1986 * while an existing transmission is in progress. If 1987 * the transmitter goes idle but there are still 1988 * packets waiting to be sent, we need to restart the 1989 * channel here to flush them out. This only seems to 1990 * be required with the PCIe devices. 1991 */ 1992 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 1993 1994 #ifdef RE_TX_MODERATION 1995 /* 1996 * If not all descriptors have been reaped yet, reload 1997 * the timer so that we will eventually get another 1998 * interrupt that will cause us to re-enter this routine. 1999 * This is done in case the transmitter has gone idle. 2000 */ 2001 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2002 #endif 2003 } else 2004 sc->rl_watchdog_timer = 0; 2005 } 2006 2007 static void 2008 re_tick(void *xsc) 2009 { 2010 struct rl_softc *sc; 2011 struct mii_data *mii; 2012 struct ifnet *ifp; 2013 2014 sc = xsc; 2015 ifp = sc->rl_ifp; 2016 2017 RL_LOCK_ASSERT(sc); 2018 2019 re_watchdog(sc); 2020 2021 mii = device_get_softc(sc->rl_miibus); 2022 mii_tick(mii); 2023 if ((sc->rl_flags & RL_FLAG_LINK) != 0) { 2024 if (!(mii->mii_media_status & IFM_ACTIVE)) 2025 sc->rl_flags &= ~RL_FLAG_LINK; 2026 } else { 2027 if (mii->mii_media_status & IFM_ACTIVE && 2028 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2029 sc->rl_flags |= RL_FLAG_LINK; 2030 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2031 taskqueue_enqueue_fast(taskqueue_fast, 2032 &sc->rl_txtask); 2033 } 2034 } 2035 2036 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2037 } 2038 2039 #ifdef DEVICE_POLLING 2040 static void 2041 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2042 { 2043 struct rl_softc *sc = ifp->if_softc; 2044 2045 RL_LOCK(sc); 2046 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2047 re_poll_locked(ifp, cmd, count); 2048 RL_UNLOCK(sc); 2049 } 2050 2051 static void 2052 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2053 { 2054 struct rl_softc *sc = ifp->if_softc; 2055 2056 RL_LOCK_ASSERT(sc); 2057 2058 sc->rxcycles = count; 2059 re_rxeof(sc); 2060 re_txeof(sc); 2061 2062 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2063 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2064 2065 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2066 u_int16_t status; 2067 2068 status = CSR_READ_2(sc, RL_ISR); 2069 if (status == 0xffff) 2070 return; 2071 if (status) 2072 CSR_WRITE_2(sc, RL_ISR, status); 2073 2074 /* 2075 * XXX check behaviour on receiver stalls. 2076 */ 2077 2078 if (status & RL_ISR_SYSTEM_ERR) { 2079 re_reset(sc); 2080 re_init_locked(sc); 2081 } 2082 } 2083 } 2084 #endif /* DEVICE_POLLING */ 2085 2086 static int 2087 re_intr(void *arg) 2088 { 2089 struct rl_softc *sc; 2090 uint16_t status; 2091 2092 sc = arg; 2093 2094 status = CSR_READ_2(sc, RL_ISR); 2095 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2096 return (FILTER_STRAY); 2097 CSR_WRITE_2(sc, RL_IMR, 0); 2098 2099 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2100 2101 return (FILTER_HANDLED); 2102 } 2103 2104 static void 2105 re_int_task(void *arg, int npending) 2106 { 2107 struct rl_softc *sc; 2108 struct ifnet *ifp; 2109 u_int16_t status; 2110 int rval = 0; 2111 2112 sc = arg; 2113 ifp = sc->rl_ifp; 2114 2115 RL_LOCK(sc); 2116 2117 status = CSR_READ_2(sc, RL_ISR); 2118 CSR_WRITE_2(sc, RL_ISR, status); 2119 2120 if (sc->suspended || 2121 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2122 RL_UNLOCK(sc); 2123 return; 2124 } 2125 2126 #ifdef DEVICE_POLLING 2127 if (ifp->if_capenable & IFCAP_POLLING) { 2128 RL_UNLOCK(sc); 2129 return; 2130 } 2131 #endif 2132 2133 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2134 rval = re_rxeof(sc); 2135 2136 if (status & ( 2137 #ifdef RE_TX_MODERATION 2138 RL_ISR_TIMEOUT_EXPIRED| 2139 #else 2140 RL_ISR_TX_OK| 2141 #endif 2142 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2143 re_txeof(sc); 2144 2145 if (status & RL_ISR_SYSTEM_ERR) { 2146 re_reset(sc); 2147 re_init_locked(sc); 2148 } 2149 2150 if (status & RL_ISR_LINKCHG) { 2151 callout_stop(&sc->rl_stat_callout); 2152 re_tick(sc); 2153 } 2154 2155 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2156 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2157 2158 RL_UNLOCK(sc); 2159 2160 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2161 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2162 return; 2163 } 2164 2165 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2166 } 2167 2168 static int 2169 re_encap(struct rl_softc *sc, struct mbuf **m_head) 2170 { 2171 struct rl_txdesc *txd, *txd_last; 2172 bus_dma_segment_t segs[RL_NTXSEGS]; 2173 bus_dmamap_t map; 2174 struct mbuf *m_new; 2175 struct rl_desc *desc; 2176 int nsegs, prod; 2177 int i, error, ei, si; 2178 int padlen; 2179 uint32_t cmdstat, csum_flags, vlanctl; 2180 2181 RL_LOCK_ASSERT(sc); 2182 M_ASSERTPKTHDR((*m_head)); 2183 2184 /* 2185 * With some of the RealTek chips, using the checksum offload 2186 * support in conjunction with the autopadding feature results 2187 * in the transmission of corrupt frames. For example, if we 2188 * need to send a really small IP fragment that's less than 60 2189 * bytes in size, and IP header checksumming is enabled, the 2190 * resulting ethernet frame that appears on the wire will 2191 * have garbled payload. To work around this, if TX IP checksum 2192 * offload is enabled, we always manually pad short frames out 2193 * to the minimum ethernet frame size. 2194 */ 2195 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0 && 2196 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN && 2197 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) { 2198 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2199 if (M_WRITABLE(*m_head) == 0) { 2200 /* Get a writable copy. */ 2201 m_new = m_dup(*m_head, M_DONTWAIT); 2202 m_freem(*m_head); 2203 if (m_new == NULL) { 2204 *m_head = NULL; 2205 return (ENOBUFS); 2206 } 2207 *m_head = m_new; 2208 } 2209 if ((*m_head)->m_next != NULL || 2210 M_TRAILINGSPACE(*m_head) < padlen) { 2211 m_new = m_defrag(*m_head, M_DONTWAIT); 2212 if (m_new == NULL) { 2213 m_freem(*m_head); 2214 *m_head = NULL; 2215 return (ENOBUFS); 2216 } 2217 } else 2218 m_new = *m_head; 2219 2220 /* 2221 * Manually pad short frames, and zero the pad space 2222 * to avoid leaking data. 2223 */ 2224 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2225 m_new->m_pkthdr.len += padlen; 2226 m_new->m_len = m_new->m_pkthdr.len; 2227 *m_head = m_new; 2228 } 2229 2230 prod = sc->rl_ldata.rl_tx_prodidx; 2231 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2232 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2233 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2234 if (error == EFBIG) { 2235 m_new = m_collapse(*m_head, M_DONTWAIT, RL_NTXSEGS); 2236 if (m_new == NULL) { 2237 m_freem(*m_head); 2238 *m_head = NULL; 2239 return (ENOBUFS); 2240 } 2241 *m_head = m_new; 2242 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2243 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2244 if (error != 0) { 2245 m_freem(*m_head); 2246 *m_head = NULL; 2247 return (error); 2248 } 2249 } else if (error != 0) 2250 return (error); 2251 if (nsegs == 0) { 2252 m_freem(*m_head); 2253 *m_head = NULL; 2254 return (EIO); 2255 } 2256 2257 /* Check for number of available descriptors. */ 2258 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2259 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2260 return (ENOBUFS); 2261 } 2262 2263 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2264 BUS_DMASYNC_PREWRITE); 2265 2266 /* 2267 * Set up checksum offload. Note: checksum offload bits must 2268 * appear in all descriptors of a multi-descriptor transmit 2269 * attempt. This is according to testing done with an 8169 2270 * chip. This is a requirement. 2271 */ 2272 vlanctl = 0; 2273 csum_flags = 0; 2274 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) 2275 csum_flags = RL_TDESC_CMD_LGSEND | 2276 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2277 RL_TDESC_CMD_MSSVAL_SHIFT); 2278 else { 2279 /* 2280 * Unconditionally enable IP checksum if TCP or UDP 2281 * checksum is required. Otherwise, TCP/UDP checksum 2282 * does't make effects. 2283 */ 2284 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) { 2285 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2286 csum_flags |= RL_TDESC_CMD_IPCSUM; 2287 if (((*m_head)->m_pkthdr.csum_flags & 2288 CSUM_TCP) != 0) 2289 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2290 if (((*m_head)->m_pkthdr.csum_flags & 2291 CSUM_UDP) != 0) 2292 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2293 } else { 2294 vlanctl |= RL_TDESC_CMD_IPCSUMV2; 2295 if (((*m_head)->m_pkthdr.csum_flags & 2296 CSUM_TCP) != 0) 2297 vlanctl |= RL_TDESC_CMD_TCPCSUMV2; 2298 if (((*m_head)->m_pkthdr.csum_flags & 2299 CSUM_UDP) != 0) 2300 vlanctl |= RL_TDESC_CMD_UDPCSUMV2; 2301 } 2302 } 2303 } 2304 2305 /* 2306 * Set up hardware VLAN tagging. Note: vlan tag info must 2307 * appear in all descriptors of a multi-descriptor 2308 * transmission attempt. 2309 */ 2310 if ((*m_head)->m_flags & M_VLANTAG) 2311 vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) | 2312 RL_TDESC_VLANCTL_TAG; 2313 2314 si = prod; 2315 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2316 desc = &sc->rl_ldata.rl_tx_list[prod]; 2317 desc->rl_vlanctl = htole32(vlanctl); 2318 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2319 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2320 cmdstat = segs[i].ds_len; 2321 if (i != 0) 2322 cmdstat |= RL_TDESC_CMD_OWN; 2323 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2324 cmdstat |= RL_TDESC_CMD_EOR; 2325 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2326 sc->rl_ldata.rl_tx_free--; 2327 } 2328 /* Update producer index. */ 2329 sc->rl_ldata.rl_tx_prodidx = prod; 2330 2331 /* Set EOF on the last descriptor. */ 2332 ei = RL_TX_DESC_PRV(sc, prod); 2333 desc = &sc->rl_ldata.rl_tx_list[ei]; 2334 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2335 2336 desc = &sc->rl_ldata.rl_tx_list[si]; 2337 /* Set SOF and transfer ownership of packet to the chip. */ 2338 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2339 2340 /* 2341 * Insure that the map for this transmission 2342 * is placed at the array index of the last descriptor 2343 * in this chain. (Swap last and first dmamaps.) 2344 */ 2345 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2346 map = txd->tx_dmamap; 2347 txd->tx_dmamap = txd_last->tx_dmamap; 2348 txd_last->tx_dmamap = map; 2349 txd_last->tx_m = *m_head; 2350 2351 return (0); 2352 } 2353 2354 static void 2355 re_tx_task(void *arg, int npending) 2356 { 2357 struct ifnet *ifp; 2358 2359 ifp = arg; 2360 re_start(ifp); 2361 } 2362 2363 /* 2364 * Main transmit routine for C+ and gigE NICs. 2365 */ 2366 static void 2367 re_start(struct ifnet *ifp) 2368 { 2369 struct rl_softc *sc; 2370 struct mbuf *m_head; 2371 int queued; 2372 2373 sc = ifp->if_softc; 2374 2375 RL_LOCK(sc); 2376 2377 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2378 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) { 2379 RL_UNLOCK(sc); 2380 return; 2381 } 2382 2383 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2384 sc->rl_ldata.rl_tx_free > 1;) { 2385 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2386 if (m_head == NULL) 2387 break; 2388 2389 if (re_encap(sc, &m_head) != 0) { 2390 if (m_head == NULL) 2391 break; 2392 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2393 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2394 break; 2395 } 2396 2397 /* 2398 * If there's a BPF listener, bounce a copy of this frame 2399 * to him. 2400 */ 2401 ETHER_BPF_MTAP(ifp, m_head); 2402 2403 queued++; 2404 } 2405 2406 if (queued == 0) { 2407 #ifdef RE_TX_MODERATION 2408 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2409 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2410 #endif 2411 RL_UNLOCK(sc); 2412 return; 2413 } 2414 2415 /* Flush the TX descriptors */ 2416 2417 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2418 sc->rl_ldata.rl_tx_list_map, 2419 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2420 2421 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2422 2423 #ifdef RE_TX_MODERATION 2424 /* 2425 * Use the countdown timer for interrupt moderation. 2426 * 'TX done' interrupts are disabled. Instead, we reset the 2427 * countdown timer, which will begin counting until it hits 2428 * the value in the TIMERINT register, and then trigger an 2429 * interrupt. Each time we write to the TIMERCNT register, 2430 * the timer count is reset to 0. 2431 */ 2432 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2433 #endif 2434 2435 /* 2436 * Set a timeout in case the chip goes out to lunch. 2437 */ 2438 sc->rl_watchdog_timer = 5; 2439 2440 RL_UNLOCK(sc); 2441 } 2442 2443 static void 2444 re_init(void *xsc) 2445 { 2446 struct rl_softc *sc = xsc; 2447 2448 RL_LOCK(sc); 2449 re_init_locked(sc); 2450 RL_UNLOCK(sc); 2451 } 2452 2453 static void 2454 re_init_locked(struct rl_softc *sc) 2455 { 2456 struct ifnet *ifp = sc->rl_ifp; 2457 struct mii_data *mii; 2458 u_int32_t rxcfg = 0; 2459 uint16_t cfg; 2460 union { 2461 uint32_t align_dummy; 2462 u_char eaddr[ETHER_ADDR_LEN]; 2463 } eaddr; 2464 2465 RL_LOCK_ASSERT(sc); 2466 2467 mii = device_get_softc(sc->rl_miibus); 2468 2469 /* 2470 * Cancel pending I/O and free all RX/TX buffers. 2471 */ 2472 re_stop(sc); 2473 2474 /* 2475 * Enable C+ RX and TX mode, as well as VLAN stripping and 2476 * RX checksum offload. We must configure the C+ register 2477 * before all others. 2478 */ 2479 cfg = RL_CPLUSCMD_PCI_MRW; 2480 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2481 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 2482 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2483 cfg |= RL_CPLUSCMD_VLANSTRIP; 2484 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) { 2485 cfg |= RL_CPLUSCMD_MACSTAT_DIS; 2486 /* XXX magic. */ 2487 cfg |= 0x0001; 2488 } else 2489 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB; 2490 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg); 2491 /* 2492 * Disable TSO if interface MTU size is greater than MSS 2493 * allowed in controller. 2494 */ 2495 if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) { 2496 ifp->if_capenable &= ~IFCAP_TSO4; 2497 ifp->if_hwassist &= ~CSUM_TSO; 2498 } 2499 2500 /* 2501 * Init our MAC address. Even though the chipset 2502 * documentation doesn't mention it, we need to enter "Config 2503 * register write enable" mode to modify the ID registers. 2504 */ 2505 /* Copy MAC address on stack to align. */ 2506 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 2507 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2508 CSR_WRITE_4(sc, RL_IDR0, 2509 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 2510 CSR_WRITE_4(sc, RL_IDR4, 2511 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 2512 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2513 2514 /* 2515 * For C+ mode, initialize the RX descriptors and mbufs. 2516 */ 2517 re_rx_list_init(sc); 2518 re_tx_list_init(sc); 2519 2520 /* 2521 * Load the addresses of the RX and TX lists into the chip. 2522 */ 2523 2524 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2525 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2526 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2527 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2528 2529 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2530 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2531 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2532 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2533 2534 /* 2535 * Enable transmit and receive. 2536 */ 2537 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2538 2539 /* 2540 * Set the initial TX and RX configuration. 2541 */ 2542 if (sc->rl_testmode) { 2543 if (sc->rl_type == RL_8169) 2544 CSR_WRITE_4(sc, RL_TXCFG, 2545 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2546 else 2547 CSR_WRITE_4(sc, RL_TXCFG, 2548 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2549 } else 2550 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2551 2552 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2553 2554 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 2555 2556 /* Set the individual bit to receive frames for this host only. */ 2557 rxcfg = CSR_READ_4(sc, RL_RXCFG); 2558 rxcfg |= RL_RXCFG_RX_INDIV; 2559 2560 /* If we want promiscuous mode, set the allframes bit. */ 2561 if (ifp->if_flags & IFF_PROMISC) 2562 rxcfg |= RL_RXCFG_RX_ALLPHYS; 2563 else 2564 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 2565 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2566 2567 /* 2568 * Set capture broadcast bit to capture broadcast frames. 2569 */ 2570 if (ifp->if_flags & IFF_BROADCAST) 2571 rxcfg |= RL_RXCFG_RX_BROAD; 2572 else 2573 rxcfg &= ~RL_RXCFG_RX_BROAD; 2574 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2575 2576 /* 2577 * Program the multicast filter, if necessary. 2578 */ 2579 re_setmulti(sc); 2580 2581 #ifdef DEVICE_POLLING 2582 /* 2583 * Disable interrupts if we are polling. 2584 */ 2585 if (ifp->if_capenable & IFCAP_POLLING) 2586 CSR_WRITE_2(sc, RL_IMR, 0); 2587 else /* otherwise ... */ 2588 #endif 2589 2590 /* 2591 * Enable interrupts. 2592 */ 2593 if (sc->rl_testmode) 2594 CSR_WRITE_2(sc, RL_IMR, 0); 2595 else 2596 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2597 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 2598 2599 /* Set initial TX threshold */ 2600 sc->rl_txthresh = RL_TX_THRESH_INIT; 2601 2602 /* Start RX/TX process. */ 2603 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2604 #ifdef notdef 2605 /* Enable receiver and transmitter. */ 2606 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2607 #endif 2608 2609 #ifdef RE_TX_MODERATION 2610 /* 2611 * Initialize the timer interrupt register so that 2612 * a timer interrupt will be generated once the timer 2613 * reaches a certain number of ticks. The timer is 2614 * reloaded on each transmit. This gives us TX interrupt 2615 * moderation, which dramatically improves TX frame rate. 2616 */ 2617 if (sc->rl_type == RL_8169) 2618 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2619 else 2620 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2621 #endif 2622 2623 /* 2624 * For 8169 gigE NICs, set the max allowed RX packet 2625 * size so we can receive jumbo frames. 2626 */ 2627 if (sc->rl_type == RL_8169) 2628 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2629 2630 if (sc->rl_testmode) 2631 return; 2632 2633 mii_mediachg(mii); 2634 2635 CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD); 2636 2637 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2638 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2639 2640 sc->rl_flags &= ~RL_FLAG_LINK; 2641 sc->rl_watchdog_timer = 0; 2642 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2643 } 2644 2645 /* 2646 * Set media options. 2647 */ 2648 static int 2649 re_ifmedia_upd(struct ifnet *ifp) 2650 { 2651 struct rl_softc *sc; 2652 struct mii_data *mii; 2653 2654 sc = ifp->if_softc; 2655 mii = device_get_softc(sc->rl_miibus); 2656 RL_LOCK(sc); 2657 mii_mediachg(mii); 2658 RL_UNLOCK(sc); 2659 2660 return (0); 2661 } 2662 2663 /* 2664 * Report current media status. 2665 */ 2666 static void 2667 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2668 { 2669 struct rl_softc *sc; 2670 struct mii_data *mii; 2671 2672 sc = ifp->if_softc; 2673 mii = device_get_softc(sc->rl_miibus); 2674 2675 RL_LOCK(sc); 2676 mii_pollstat(mii); 2677 RL_UNLOCK(sc); 2678 ifmr->ifm_active = mii->mii_media_active; 2679 ifmr->ifm_status = mii->mii_media_status; 2680 } 2681 2682 static int 2683 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2684 { 2685 struct rl_softc *sc = ifp->if_softc; 2686 struct ifreq *ifr = (struct ifreq *) data; 2687 struct mii_data *mii; 2688 int error = 0; 2689 2690 switch (command) { 2691 case SIOCSIFMTU: 2692 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > RL_JUMBO_MTU) { 2693 error = EINVAL; 2694 break; 2695 } 2696 if ((sc->rl_flags & RL_FLAG_NOJUMBO) != 0 && 2697 ifr->ifr_mtu > RL_MAX_FRAMELEN) { 2698 error = EINVAL; 2699 break; 2700 } 2701 RL_LOCK(sc); 2702 if (ifp->if_mtu != ifr->ifr_mtu) 2703 ifp->if_mtu = ifr->ifr_mtu; 2704 if (ifp->if_mtu > RL_TSO_MTU && 2705 (ifp->if_capenable & IFCAP_TSO4) != 0) { 2706 ifp->if_capenable &= ~IFCAP_TSO4; 2707 ifp->if_hwassist &= ~CSUM_TSO; 2708 } 2709 RL_UNLOCK(sc); 2710 break; 2711 case SIOCSIFFLAGS: 2712 RL_LOCK(sc); 2713 if ((ifp->if_flags & IFF_UP) != 0) { 2714 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2715 if (((ifp->if_flags ^ sc->rl_if_flags) 2716 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2717 re_setmulti(sc); 2718 } else 2719 re_init_locked(sc); 2720 } else { 2721 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2722 re_stop(sc); 2723 } 2724 sc->rl_if_flags = ifp->if_flags; 2725 RL_UNLOCK(sc); 2726 break; 2727 case SIOCADDMULTI: 2728 case SIOCDELMULTI: 2729 RL_LOCK(sc); 2730 re_setmulti(sc); 2731 RL_UNLOCK(sc); 2732 break; 2733 case SIOCGIFMEDIA: 2734 case SIOCSIFMEDIA: 2735 mii = device_get_softc(sc->rl_miibus); 2736 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2737 break; 2738 case SIOCSIFCAP: 2739 { 2740 int mask, reinit; 2741 2742 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2743 reinit = 0; 2744 #ifdef DEVICE_POLLING 2745 if (mask & IFCAP_POLLING) { 2746 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2747 error = ether_poll_register(re_poll, ifp); 2748 if (error) 2749 return(error); 2750 RL_LOCK(sc); 2751 /* Disable interrupts */ 2752 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2753 ifp->if_capenable |= IFCAP_POLLING; 2754 RL_UNLOCK(sc); 2755 } else { 2756 error = ether_poll_deregister(ifp); 2757 /* Enable interrupts. */ 2758 RL_LOCK(sc); 2759 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2760 ifp->if_capenable &= ~IFCAP_POLLING; 2761 RL_UNLOCK(sc); 2762 } 2763 } 2764 #endif /* DEVICE_POLLING */ 2765 if (mask & IFCAP_HWCSUM) { 2766 ifp->if_capenable ^= IFCAP_HWCSUM; 2767 if (ifp->if_capenable & IFCAP_TXCSUM) 2768 ifp->if_hwassist |= RE_CSUM_FEATURES; 2769 else 2770 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 2771 reinit = 1; 2772 } 2773 if (mask & IFCAP_VLAN_HWTAGGING) { 2774 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2775 reinit = 1; 2776 } 2777 if (mask & IFCAP_TSO4) { 2778 ifp->if_capenable ^= IFCAP_TSO4; 2779 if ((IFCAP_TSO4 & ifp->if_capenable) && 2780 (IFCAP_TSO4 & ifp->if_capabilities)) 2781 ifp->if_hwassist |= CSUM_TSO; 2782 else 2783 ifp->if_hwassist &= ~CSUM_TSO; 2784 if (ifp->if_mtu > RL_TSO_MTU && 2785 (ifp->if_capenable & IFCAP_TSO4) != 0) { 2786 ifp->if_capenable &= ~IFCAP_TSO4; 2787 ifp->if_hwassist &= ~CSUM_TSO; 2788 } 2789 } 2790 if ((mask & IFCAP_WOL) != 0 && 2791 (ifp->if_capabilities & IFCAP_WOL) != 0) { 2792 if ((mask & IFCAP_WOL_UCAST) != 0) 2793 ifp->if_capenable ^= IFCAP_WOL_UCAST; 2794 if ((mask & IFCAP_WOL_MCAST) != 0) 2795 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2796 if ((mask & IFCAP_WOL_MAGIC) != 0) 2797 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2798 } 2799 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) 2800 re_init(sc); 2801 VLAN_CAPABILITIES(ifp); 2802 } 2803 break; 2804 default: 2805 error = ether_ioctl(ifp, command, data); 2806 break; 2807 } 2808 2809 return (error); 2810 } 2811 2812 static void 2813 re_watchdog(struct rl_softc *sc) 2814 { 2815 2816 RL_LOCK_ASSERT(sc); 2817 2818 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 2819 return; 2820 2821 device_printf(sc->rl_dev, "watchdog timeout\n"); 2822 sc->rl_ifp->if_oerrors++; 2823 2824 re_txeof(sc); 2825 re_rxeof(sc); 2826 re_init_locked(sc); 2827 } 2828 2829 /* 2830 * Stop the adapter and free any mbufs allocated to the 2831 * RX and TX lists. 2832 */ 2833 static void 2834 re_stop(struct rl_softc *sc) 2835 { 2836 int i; 2837 struct ifnet *ifp; 2838 struct rl_txdesc *txd; 2839 struct rl_rxdesc *rxd; 2840 2841 RL_LOCK_ASSERT(sc); 2842 2843 ifp = sc->rl_ifp; 2844 2845 sc->rl_watchdog_timer = 0; 2846 callout_stop(&sc->rl_stat_callout); 2847 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2848 2849 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2850 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2851 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 2852 2853 if (sc->rl_head != NULL) { 2854 m_freem(sc->rl_head); 2855 sc->rl_head = sc->rl_tail = NULL; 2856 } 2857 2858 /* Free the TX list buffers. */ 2859 2860 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 2861 txd = &sc->rl_ldata.rl_tx_desc[i]; 2862 if (txd->tx_m != NULL) { 2863 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2864 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2865 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2866 txd->tx_dmamap); 2867 m_freem(txd->tx_m); 2868 txd->tx_m = NULL; 2869 } 2870 } 2871 2872 /* Free the RX list buffers. */ 2873 2874 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2875 rxd = &sc->rl_ldata.rl_rx_desc[i]; 2876 if (rxd->rx_m != NULL) { 2877 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2878 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2879 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 2880 rxd->rx_dmamap); 2881 m_freem(rxd->rx_m); 2882 rxd->rx_m = NULL; 2883 } 2884 } 2885 } 2886 2887 /* 2888 * Device suspend routine. Stop the interface and save some PCI 2889 * settings in case the BIOS doesn't restore them properly on 2890 * resume. 2891 */ 2892 static int 2893 re_suspend(device_t dev) 2894 { 2895 struct rl_softc *sc; 2896 2897 sc = device_get_softc(dev); 2898 2899 RL_LOCK(sc); 2900 re_stop(sc); 2901 re_setwol(sc); 2902 sc->suspended = 1; 2903 RL_UNLOCK(sc); 2904 2905 return (0); 2906 } 2907 2908 /* 2909 * Device resume routine. Restore some PCI settings in case the BIOS 2910 * doesn't, re-enable busmastering, and restart the interface if 2911 * appropriate. 2912 */ 2913 static int 2914 re_resume(device_t dev) 2915 { 2916 struct rl_softc *sc; 2917 struct ifnet *ifp; 2918 2919 sc = device_get_softc(dev); 2920 2921 RL_LOCK(sc); 2922 2923 ifp = sc->rl_ifp; 2924 2925 /* reinitialize interface if necessary */ 2926 if (ifp->if_flags & IFF_UP) 2927 re_init_locked(sc); 2928 2929 /* 2930 * Clear WOL matching such that normal Rx filtering 2931 * wouldn't interfere with WOL patterns. 2932 */ 2933 re_clrwol(sc); 2934 sc->suspended = 0; 2935 RL_UNLOCK(sc); 2936 2937 return (0); 2938 } 2939 2940 /* 2941 * Stop all chip I/O so that the kernel's probe routines don't 2942 * get confused by errant DMAs when rebooting. 2943 */ 2944 static int 2945 re_shutdown(device_t dev) 2946 { 2947 struct rl_softc *sc; 2948 2949 sc = device_get_softc(dev); 2950 2951 RL_LOCK(sc); 2952 re_stop(sc); 2953 /* 2954 * Mark interface as down since otherwise we will panic if 2955 * interrupt comes in later on, which can happen in some 2956 * cases. 2957 */ 2958 sc->rl_ifp->if_flags &= ~IFF_UP; 2959 re_setwol(sc); 2960 RL_UNLOCK(sc); 2961 2962 return (0); 2963 } 2964 2965 static void 2966 re_setwol(struct rl_softc *sc) 2967 { 2968 struct ifnet *ifp; 2969 int pmc; 2970 uint16_t pmstat; 2971 uint8_t v; 2972 2973 RL_LOCK_ASSERT(sc); 2974 2975 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 2976 return; 2977 2978 ifp = sc->rl_ifp; 2979 /* Enable config register write. */ 2980 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 2981 2982 /* Enable PME. */ 2983 v = CSR_READ_1(sc, RL_CFG1); 2984 v &= ~RL_CFG1_PME; 2985 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2986 v |= RL_CFG1_PME; 2987 CSR_WRITE_1(sc, RL_CFG1, v); 2988 2989 v = CSR_READ_1(sc, RL_CFG3); 2990 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 2991 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2992 v |= RL_CFG3_WOL_MAGIC; 2993 CSR_WRITE_1(sc, RL_CFG3, v); 2994 2995 /* Config register write done. */ 2996 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2997 2998 v = CSR_READ_1(sc, RL_CFG5); 2999 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3000 v &= ~RL_CFG5_WOL_LANWAKE; 3001 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 3002 v |= RL_CFG5_WOL_UCAST; 3003 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 3004 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 3005 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3006 v |= RL_CFG5_WOL_LANWAKE; 3007 CSR_WRITE_1(sc, RL_CFG5, v); 3008 3009 /* 3010 * It seems that hardware resets its link speed to 100Mbps in 3011 * power down mode so switching to 100Mbps in driver is not 3012 * needed. 3013 */ 3014 3015 /* Request PME if WOL is requested. */ 3016 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 3017 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3018 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3019 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3020 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 3021 } 3022 3023 static void 3024 re_clrwol(struct rl_softc *sc) 3025 { 3026 int pmc; 3027 uint8_t v; 3028 3029 RL_LOCK_ASSERT(sc); 3030 3031 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3032 return; 3033 3034 /* Enable config register write. */ 3035 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3036 3037 v = CSR_READ_1(sc, RL_CFG3); 3038 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3039 CSR_WRITE_1(sc, RL_CFG3, v); 3040 3041 /* Config register write done. */ 3042 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3043 3044 v = CSR_READ_1(sc, RL_CFG5); 3045 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3046 v &= ~RL_CFG5_WOL_LANWAKE; 3047 CSR_WRITE_1(sc, RL_CFG5, v); 3048 } 3049