1 /*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44 /* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111 #ifdef HAVE_KERNEL_OPTION_HEADERS 112 #include "opt_device_polling.h" 113 #endif 114 115 #include <sys/param.h> 116 #include <sys/endian.h> 117 #include <sys/systm.h> 118 #include <sys/sockio.h> 119 #include <sys/mbuf.h> 120 #include <sys/malloc.h> 121 #include <sys/module.h> 122 #include <sys/kernel.h> 123 #include <sys/socket.h> 124 #include <sys/lock.h> 125 #include <sys/mutex.h> 126 #include <sys/taskqueue.h> 127 128 #include <net/if.h> 129 #include <net/if_arp.h> 130 #include <net/ethernet.h> 131 #include <net/if_dl.h> 132 #include <net/if_media.h> 133 #include <net/if_types.h> 134 #include <net/if_vlan_var.h> 135 136 #include <net/bpf.h> 137 138 #include <machine/bus.h> 139 #include <machine/resource.h> 140 #include <sys/bus.h> 141 #include <sys/rman.h> 142 143 #include <dev/mii/mii.h> 144 #include <dev/mii/miivar.h> 145 146 #include <dev/pci/pcireg.h> 147 #include <dev/pci/pcivar.h> 148 149 #include <pci/if_rlreg.h> 150 151 MODULE_DEPEND(re, pci, 1, 1, 1); 152 MODULE_DEPEND(re, ether, 1, 1, 1); 153 MODULE_DEPEND(re, miibus, 1, 1, 1); 154 155 /* "device miibus" required. See GENERIC if you get errors here. */ 156 #include "miibus_if.h" 157 158 /* 159 * Default to using PIO access for this driver. 160 */ 161 #define RE_USEIOSPACE 162 163 /* Tunables. */ 164 static int msi_disable = 1; 165 TUNABLE_INT("hw.re.msi_disable", &msi_disable); 166 167 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 168 169 /* 170 * Various supported device vendors/types and their names. 171 */ 172 static struct rl_type re_devs[] = { 173 { DLINK_VENDORID, DLINK_DEVICEID_528T, RL_HWREV_8169S, 174 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 175 { DLINK_VENDORID, DLINK_DEVICEID_528T, RL_HWREV_8169_8110SB, 176 "D-Link DGE-528(T) Rev.B1 Gigabit Ethernet Adapter" }, 177 { RT_VENDORID, RT_DEVICEID_8139, RL_HWREV_8139CPLUS, 178 "RealTek 8139C+ 10/100BaseTX" }, 179 { RT_VENDORID, RT_DEVICEID_8101E, RL_HWREV_8101E, 180 "RealTek 8101E PCIe 10/100baseTX" }, 181 { RT_VENDORID, RT_DEVICEID_8168, RL_HWREV_8168_SPIN1, 182 "RealTek 8168/8111B PCIe Gigabit Ethernet" }, 183 { RT_VENDORID, RT_DEVICEID_8168, RL_HWREV_8168_SPIN2, 184 "RealTek 8168/8111B PCIe Gigabit Ethernet" }, 185 { RT_VENDORID, RT_DEVICEID_8168, RL_HWREV_8168_SPIN3, 186 "RealTek 8168/8111B PCIe Gigabit Ethernet" }, 187 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169, 188 "RealTek 8169 Gigabit Ethernet" }, 189 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169S, 190 "RealTek 8169S Single-chip Gigabit Ethernet" }, 191 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169_8110SB, 192 "RealTek 8169SB/8110SB Single-chip Gigabit Ethernet" }, 193 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169_8110SC, 194 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 195 { RT_VENDORID, RT_DEVICEID_8169SC, RL_HWREV_8169_8110SC, 196 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 197 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8110S, 198 "RealTek 8110S Single-chip Gigabit Ethernet" }, 199 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, RL_HWREV_8169S, 200 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 201 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, RL_HWREV_8169S, 202 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 203 { USR_VENDORID, USR_DEVICEID_997902, RL_HWREV_8169S, 204 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 205 }; 206 207 static struct rl_hwrev re_hwrevs[] = { 208 { RL_HWREV_8139, RL_8139, "" }, 209 { RL_HWREV_8139A, RL_8139, "A" }, 210 { RL_HWREV_8139AG, RL_8139, "A-G" }, 211 { RL_HWREV_8139B, RL_8139, "B" }, 212 { RL_HWREV_8130, RL_8139, "8130" }, 213 { RL_HWREV_8139C, RL_8139, "C" }, 214 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 215 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 216 { RL_HWREV_8168_SPIN1, RL_8169, "8168"}, 217 { RL_HWREV_8169, RL_8169, "8169"}, 218 { RL_HWREV_8169S, RL_8169, "8169S"}, 219 { RL_HWREV_8110S, RL_8169, "8110S"}, 220 { RL_HWREV_8169_8110SB, RL_8169, "8169SB"}, 221 { RL_HWREV_8169_8110SC, RL_8169, "8169SC"}, 222 { RL_HWREV_8100, RL_8139, "8100"}, 223 { RL_HWREV_8101, RL_8139, "8101"}, 224 { RL_HWREV_8100E, RL_8169, "8100E"}, 225 { RL_HWREV_8101E, RL_8169, "8101E"}, 226 { RL_HWREV_8168_SPIN2, RL_8169, "8168"}, 227 { RL_HWREV_8168_SPIN3, RL_8169, "8168"}, 228 { 0, 0, NULL } 229 }; 230 231 static int re_probe (device_t); 232 static int re_attach (device_t); 233 static int re_detach (device_t); 234 235 static int re_encap (struct rl_softc *, struct mbuf **); 236 237 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 238 static int re_allocmem (device_t, struct rl_softc *); 239 static __inline void re_discard_rxbuf 240 (struct rl_softc *, int); 241 static int re_newbuf (struct rl_softc *, int); 242 static int re_rx_list_init (struct rl_softc *); 243 static int re_tx_list_init (struct rl_softc *); 244 #ifdef RE_FIXUP_RX 245 static __inline void re_fixup_rx 246 (struct mbuf *); 247 #endif 248 static int re_rxeof (struct rl_softc *); 249 static void re_txeof (struct rl_softc *); 250 #ifdef DEVICE_POLLING 251 static void re_poll (struct ifnet *, enum poll_cmd, int); 252 static void re_poll_locked (struct ifnet *, enum poll_cmd, int); 253 #endif 254 static int re_intr (void *); 255 static void re_tick (void *); 256 static void re_tx_task (void *, int); 257 static void re_int_task (void *, int); 258 static void re_start (struct ifnet *); 259 static int re_ioctl (struct ifnet *, u_long, caddr_t); 260 static void re_init (void *); 261 static void re_init_locked (struct rl_softc *); 262 static void re_stop (struct rl_softc *); 263 static void re_watchdog (struct rl_softc *); 264 static int re_suspend (device_t); 265 static int re_resume (device_t); 266 static int re_shutdown (device_t); 267 static int re_ifmedia_upd (struct ifnet *); 268 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 269 270 static void re_eeprom_putbyte (struct rl_softc *, int); 271 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 272 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 273 static int re_gmii_readreg (device_t, int, int); 274 static int re_gmii_writereg (device_t, int, int, int); 275 276 static int re_miibus_readreg (device_t, int, int); 277 static int re_miibus_writereg (device_t, int, int, int); 278 static void re_miibus_statchg (device_t); 279 280 static void re_setmulti (struct rl_softc *); 281 static void re_reset (struct rl_softc *); 282 static void re_setwol (struct rl_softc *); 283 static void re_clrwol (struct rl_softc *); 284 285 #ifdef RE_DIAG 286 static int re_diag (struct rl_softc *); 287 #endif 288 289 #ifdef RE_USEIOSPACE 290 #define RL_RES SYS_RES_IOPORT 291 #define RL_RID RL_PCI_LOIO 292 #else 293 #define RL_RES SYS_RES_MEMORY 294 #define RL_RID RL_PCI_LOMEM 295 #endif 296 297 static device_method_t re_methods[] = { 298 /* Device interface */ 299 DEVMETHOD(device_probe, re_probe), 300 DEVMETHOD(device_attach, re_attach), 301 DEVMETHOD(device_detach, re_detach), 302 DEVMETHOD(device_suspend, re_suspend), 303 DEVMETHOD(device_resume, re_resume), 304 DEVMETHOD(device_shutdown, re_shutdown), 305 306 /* bus interface */ 307 DEVMETHOD(bus_print_child, bus_generic_print_child), 308 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 309 310 /* MII interface */ 311 DEVMETHOD(miibus_readreg, re_miibus_readreg), 312 DEVMETHOD(miibus_writereg, re_miibus_writereg), 313 DEVMETHOD(miibus_statchg, re_miibus_statchg), 314 315 { 0, 0 } 316 }; 317 318 static driver_t re_driver = { 319 "re", 320 re_methods, 321 sizeof(struct rl_softc) 322 }; 323 324 static devclass_t re_devclass; 325 326 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 327 DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0); 328 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 329 330 #define EE_SET(x) \ 331 CSR_WRITE_1(sc, RL_EECMD, \ 332 CSR_READ_1(sc, RL_EECMD) | x) 333 334 #define EE_CLR(x) \ 335 CSR_WRITE_1(sc, RL_EECMD, \ 336 CSR_READ_1(sc, RL_EECMD) & ~x) 337 338 /* 339 * Send a read command and address to the EEPROM, check for ACK. 340 */ 341 static void 342 re_eeprom_putbyte(sc, addr) 343 struct rl_softc *sc; 344 int addr; 345 { 346 register int d, i; 347 348 d = addr | (RL_9346_READ << sc->rl_eewidth); 349 350 /* 351 * Feed in each bit and strobe the clock. 352 */ 353 354 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 355 if (d & i) { 356 EE_SET(RL_EE_DATAIN); 357 } else { 358 EE_CLR(RL_EE_DATAIN); 359 } 360 DELAY(100); 361 EE_SET(RL_EE_CLK); 362 DELAY(150); 363 EE_CLR(RL_EE_CLK); 364 DELAY(100); 365 } 366 367 return; 368 } 369 370 /* 371 * Read a word of data stored in the EEPROM at address 'addr.' 372 */ 373 static void 374 re_eeprom_getword(sc, addr, dest) 375 struct rl_softc *sc; 376 int addr; 377 u_int16_t *dest; 378 { 379 register int i; 380 u_int16_t word = 0; 381 382 /* 383 * Send address of word we want to read. 384 */ 385 re_eeprom_putbyte(sc, addr); 386 387 /* 388 * Start reading bits from EEPROM. 389 */ 390 for (i = 0x8000; i; i >>= 1) { 391 EE_SET(RL_EE_CLK); 392 DELAY(100); 393 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 394 word |= i; 395 EE_CLR(RL_EE_CLK); 396 DELAY(100); 397 } 398 399 *dest = word; 400 401 return; 402 } 403 404 /* 405 * Read a sequence of words from the EEPROM. 406 */ 407 static void 408 re_read_eeprom(sc, dest, off, cnt) 409 struct rl_softc *sc; 410 caddr_t dest; 411 int off; 412 int cnt; 413 { 414 int i; 415 u_int16_t word = 0, *ptr; 416 417 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 418 419 DELAY(100); 420 421 for (i = 0; i < cnt; i++) { 422 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 423 re_eeprom_getword(sc, off + i, &word); 424 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 425 ptr = (u_int16_t *)(dest + (i * 2)); 426 *ptr = word; 427 } 428 429 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 430 431 return; 432 } 433 434 static int 435 re_gmii_readreg(dev, phy, reg) 436 device_t dev; 437 int phy, reg; 438 { 439 struct rl_softc *sc; 440 u_int32_t rval; 441 int i; 442 443 if (phy != 1) 444 return (0); 445 446 sc = device_get_softc(dev); 447 448 /* Let the rgephy driver read the GMEDIASTAT register */ 449 450 if (reg == RL_GMEDIASTAT) { 451 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 452 return (rval); 453 } 454 455 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 456 DELAY(1000); 457 458 for (i = 0; i < RL_TIMEOUT; i++) { 459 rval = CSR_READ_4(sc, RL_PHYAR); 460 if (rval & RL_PHYAR_BUSY) 461 break; 462 DELAY(100); 463 } 464 465 if (i == RL_TIMEOUT) { 466 device_printf(sc->rl_dev, "PHY read failed\n"); 467 return (0); 468 } 469 470 return (rval & RL_PHYAR_PHYDATA); 471 } 472 473 static int 474 re_gmii_writereg(dev, phy, reg, data) 475 device_t dev; 476 int phy, reg, data; 477 { 478 struct rl_softc *sc; 479 u_int32_t rval; 480 int i; 481 482 sc = device_get_softc(dev); 483 484 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 485 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 486 DELAY(1000); 487 488 for (i = 0; i < RL_TIMEOUT; i++) { 489 rval = CSR_READ_4(sc, RL_PHYAR); 490 if (!(rval & RL_PHYAR_BUSY)) 491 break; 492 DELAY(100); 493 } 494 495 if (i == RL_TIMEOUT) { 496 device_printf(sc->rl_dev, "PHY write failed\n"); 497 return (0); 498 } 499 500 return (0); 501 } 502 503 static int 504 re_miibus_readreg(dev, phy, reg) 505 device_t dev; 506 int phy, reg; 507 { 508 struct rl_softc *sc; 509 u_int16_t rval = 0; 510 u_int16_t re8139_reg = 0; 511 512 sc = device_get_softc(dev); 513 514 if (sc->rl_type == RL_8169) { 515 rval = re_gmii_readreg(dev, phy, reg); 516 return (rval); 517 } 518 519 /* Pretend the internal PHY is only at address 0 */ 520 if (phy) { 521 return (0); 522 } 523 switch (reg) { 524 case MII_BMCR: 525 re8139_reg = RL_BMCR; 526 break; 527 case MII_BMSR: 528 re8139_reg = RL_BMSR; 529 break; 530 case MII_ANAR: 531 re8139_reg = RL_ANAR; 532 break; 533 case MII_ANER: 534 re8139_reg = RL_ANER; 535 break; 536 case MII_ANLPAR: 537 re8139_reg = RL_LPAR; 538 break; 539 case MII_PHYIDR1: 540 case MII_PHYIDR2: 541 return (0); 542 /* 543 * Allow the rlphy driver to read the media status 544 * register. If we have a link partner which does not 545 * support NWAY, this is the register which will tell 546 * us the results of parallel detection. 547 */ 548 case RL_MEDIASTAT: 549 rval = CSR_READ_1(sc, RL_MEDIASTAT); 550 return (rval); 551 default: 552 device_printf(sc->rl_dev, "bad phy register\n"); 553 return (0); 554 } 555 rval = CSR_READ_2(sc, re8139_reg); 556 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 557 /* 8139C+ has different bit layout. */ 558 rval &= ~(BMCR_LOOP | BMCR_ISO); 559 } 560 return (rval); 561 } 562 563 static int 564 re_miibus_writereg(dev, phy, reg, data) 565 device_t dev; 566 int phy, reg, data; 567 { 568 struct rl_softc *sc; 569 u_int16_t re8139_reg = 0; 570 int rval = 0; 571 572 sc = device_get_softc(dev); 573 574 if (sc->rl_type == RL_8169) { 575 rval = re_gmii_writereg(dev, phy, reg, data); 576 return (rval); 577 } 578 579 /* Pretend the internal PHY is only at address 0 */ 580 if (phy) 581 return (0); 582 583 switch (reg) { 584 case MII_BMCR: 585 re8139_reg = RL_BMCR; 586 if (sc->rl_type == RL_8139CPLUS) { 587 /* 8139C+ has different bit layout. */ 588 data &= ~(BMCR_LOOP | BMCR_ISO); 589 } 590 break; 591 case MII_BMSR: 592 re8139_reg = RL_BMSR; 593 break; 594 case MII_ANAR: 595 re8139_reg = RL_ANAR; 596 break; 597 case MII_ANER: 598 re8139_reg = RL_ANER; 599 break; 600 case MII_ANLPAR: 601 re8139_reg = RL_LPAR; 602 break; 603 case MII_PHYIDR1: 604 case MII_PHYIDR2: 605 return (0); 606 break; 607 default: 608 device_printf(sc->rl_dev, "bad phy register\n"); 609 return (0); 610 } 611 CSR_WRITE_2(sc, re8139_reg, data); 612 return (0); 613 } 614 615 static void 616 re_miibus_statchg(dev) 617 device_t dev; 618 { 619 620 } 621 622 /* 623 * Program the 64-bit multicast hash filter. 624 */ 625 static void 626 re_setmulti(sc) 627 struct rl_softc *sc; 628 { 629 struct ifnet *ifp; 630 int h = 0; 631 u_int32_t hashes[2] = { 0, 0 }; 632 struct ifmultiaddr *ifma; 633 u_int32_t rxfilt; 634 int mcnt = 0; 635 u_int32_t hwrev; 636 637 RL_LOCK_ASSERT(sc); 638 639 ifp = sc->rl_ifp; 640 641 642 rxfilt = CSR_READ_4(sc, RL_RXCFG); 643 rxfilt &= ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_MULTI); 644 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 645 if (ifp->if_flags & IFF_PROMISC) 646 rxfilt |= RL_RXCFG_RX_ALLPHYS; 647 /* 648 * Unlike other hardwares, we have to explicitly set 649 * RL_RXCFG_RX_MULTI to receive multicast frames in 650 * promiscuous mode. 651 */ 652 rxfilt |= RL_RXCFG_RX_MULTI; 653 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 654 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 655 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 656 return; 657 } 658 659 /* first, zot all the existing hash bits */ 660 CSR_WRITE_4(sc, RL_MAR0, 0); 661 CSR_WRITE_4(sc, RL_MAR4, 0); 662 663 /* now program new ones */ 664 IF_ADDR_LOCK(ifp); 665 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 666 if (ifma->ifma_addr->sa_family != AF_LINK) 667 continue; 668 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 669 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 670 if (h < 32) 671 hashes[0] |= (1 << h); 672 else 673 hashes[1] |= (1 << (h - 32)); 674 mcnt++; 675 } 676 IF_ADDR_UNLOCK(ifp); 677 678 if (mcnt) 679 rxfilt |= RL_RXCFG_RX_MULTI; 680 else 681 rxfilt &= ~RL_RXCFG_RX_MULTI; 682 683 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 684 685 /* 686 * For some unfathomable reason, RealTek decided to reverse 687 * the order of the multicast hash registers in the PCI Express 688 * parts. This means we have to write the hash pattern in reverse 689 * order for those devices. 690 */ 691 692 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 693 694 switch (hwrev) { 695 case RL_HWREV_8100E: 696 case RL_HWREV_8101E: 697 case RL_HWREV_8168_SPIN1: 698 case RL_HWREV_8168_SPIN2: 699 case RL_HWREV_8168_SPIN3: 700 CSR_WRITE_4(sc, RL_MAR0, bswap32(hashes[1])); 701 CSR_WRITE_4(sc, RL_MAR4, bswap32(hashes[0])); 702 break; 703 default: 704 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 705 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 706 break; 707 } 708 } 709 710 static void 711 re_reset(sc) 712 struct rl_softc *sc; 713 { 714 register int i; 715 716 RL_LOCK_ASSERT(sc); 717 718 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 719 720 for (i = 0; i < RL_TIMEOUT; i++) { 721 DELAY(10); 722 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 723 break; 724 } 725 if (i == RL_TIMEOUT) 726 device_printf(sc->rl_dev, "reset never completed!\n"); 727 728 CSR_WRITE_1(sc, 0x82, 1); 729 } 730 731 #ifdef RE_DIAG 732 733 /* 734 * The following routine is designed to test for a defect on some 735 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 736 * lines connected to the bus, however for a 32-bit only card, they 737 * should be pulled high. The result of this defect is that the 738 * NIC will not work right if you plug it into a 64-bit slot: DMA 739 * operations will be done with 64-bit transfers, which will fail 740 * because the 64-bit data lines aren't connected. 741 * 742 * There's no way to work around this (short of talking a soldering 743 * iron to the board), however we can detect it. The method we use 744 * here is to put the NIC into digital loopback mode, set the receiver 745 * to promiscuous mode, and then try to send a frame. We then compare 746 * the frame data we sent to what was received. If the data matches, 747 * then the NIC is working correctly, otherwise we know the user has 748 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 749 * slot. In the latter case, there's no way the NIC can work correctly, 750 * so we print out a message on the console and abort the device attach. 751 */ 752 753 static int 754 re_diag(sc) 755 struct rl_softc *sc; 756 { 757 struct ifnet *ifp = sc->rl_ifp; 758 struct mbuf *m0; 759 struct ether_header *eh; 760 struct rl_desc *cur_rx; 761 u_int16_t status; 762 u_int32_t rxstat; 763 int total_len, i, error = 0, phyaddr; 764 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 765 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 766 767 /* Allocate a single mbuf */ 768 MGETHDR(m0, M_DONTWAIT, MT_DATA); 769 if (m0 == NULL) 770 return (ENOBUFS); 771 772 RL_LOCK(sc); 773 774 /* 775 * Initialize the NIC in test mode. This sets the chip up 776 * so that it can send and receive frames, but performs the 777 * following special functions: 778 * - Puts receiver in promiscuous mode 779 * - Enables digital loopback mode 780 * - Leaves interrupts turned off 781 */ 782 783 ifp->if_flags |= IFF_PROMISC; 784 sc->rl_testmode = 1; 785 re_reset(sc); 786 re_init_locked(sc); 787 sc->rl_link = 1; 788 if (sc->rl_type == RL_8169) 789 phyaddr = 1; 790 else 791 phyaddr = 0; 792 793 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 794 for (i = 0; i < RL_TIMEOUT; i++) { 795 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 796 if (!(status & BMCR_RESET)) 797 break; 798 } 799 800 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 801 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 802 803 DELAY(100000); 804 805 /* Put some data in the mbuf */ 806 807 eh = mtod(m0, struct ether_header *); 808 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 809 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 810 eh->ether_type = htons(ETHERTYPE_IP); 811 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 812 813 /* 814 * Queue the packet, start transmission. 815 * Note: IF_HANDOFF() ultimately calls re_start() for us. 816 */ 817 818 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 819 RL_UNLOCK(sc); 820 /* XXX: re_diag must not be called when in ALTQ mode */ 821 IF_HANDOFF(&ifp->if_snd, m0, ifp); 822 RL_LOCK(sc); 823 m0 = NULL; 824 825 /* Wait for it to propagate through the chip */ 826 827 DELAY(100000); 828 for (i = 0; i < RL_TIMEOUT; i++) { 829 status = CSR_READ_2(sc, RL_ISR); 830 CSR_WRITE_2(sc, RL_ISR, status); 831 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 832 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 833 break; 834 DELAY(10); 835 } 836 837 if (i == RL_TIMEOUT) { 838 device_printf(sc->rl_dev, 839 "diagnostic failed, failed to receive packet in" 840 " loopback mode\n"); 841 error = EIO; 842 goto done; 843 } 844 845 /* 846 * The packet should have been dumped into the first 847 * entry in the RX DMA ring. Grab it from there. 848 */ 849 850 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 851 sc->rl_ldata.rl_rx_list_map, 852 BUS_DMASYNC_POSTREAD); 853 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 854 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 855 BUS_DMASYNC_POSTREAD); 856 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 857 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 858 859 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 860 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 861 eh = mtod(m0, struct ether_header *); 862 863 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 864 total_len = RL_RXBYTES(cur_rx); 865 rxstat = le32toh(cur_rx->rl_cmdstat); 866 867 if (total_len != ETHER_MIN_LEN) { 868 device_printf(sc->rl_dev, 869 "diagnostic failed, received short packet\n"); 870 error = EIO; 871 goto done; 872 } 873 874 /* Test that the received packet data matches what we sent. */ 875 876 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 877 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 878 ntohs(eh->ether_type) != ETHERTYPE_IP) { 879 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 880 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 881 dst, ":", src, ":", ETHERTYPE_IP); 882 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 883 eh->ether_dhost, ":", eh->ether_shost, ":", 884 ntohs(eh->ether_type)); 885 device_printf(sc->rl_dev, "You may have a defective 32-bit " 886 "NIC plugged into a 64-bit PCI slot.\n"); 887 device_printf(sc->rl_dev, "Please re-install the NIC in a " 888 "32-bit slot for proper operation.\n"); 889 device_printf(sc->rl_dev, "Read the re(4) man page for more " 890 "details.\n"); 891 error = EIO; 892 } 893 894 done: 895 /* Turn interface off, release resources */ 896 897 sc->rl_testmode = 0; 898 sc->rl_link = 0; 899 ifp->if_flags &= ~IFF_PROMISC; 900 re_stop(sc); 901 if (m0 != NULL) 902 m_freem(m0); 903 904 RL_UNLOCK(sc); 905 906 return (error); 907 } 908 909 #endif 910 911 /* 912 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 913 * IDs against our list and return a device name if we find a match. 914 */ 915 static int 916 re_probe(dev) 917 device_t dev; 918 { 919 struct rl_type *t; 920 uint16_t devid, vendor; 921 uint16_t revid, sdevid; 922 int i; 923 924 vendor = pci_get_vendor(dev); 925 devid = pci_get_device(dev); 926 revid = pci_get_revid(dev); 927 sdevid = pci_get_subdevice(dev); 928 929 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 930 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 931 /* 932 * Only attach to rev. 3 of the Linksys EG1032 adapter. 933 * Rev. 2 is supported by sk(4). 934 */ 935 return (ENXIO); 936 } 937 } 938 939 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 940 if (revid != 0x20) { 941 /* 8139, let rl(4) take care of this device. */ 942 return (ENXIO); 943 } 944 } 945 946 t = re_devs; 947 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) { 948 if (vendor == t->rl_vid && devid == t->rl_did) { 949 device_set_desc(dev, t->rl_name); 950 return (BUS_PROBE_DEFAULT); 951 } 952 } 953 954 return (ENXIO); 955 } 956 957 /* 958 * Map a single buffer address. 959 */ 960 961 static void 962 re_dma_map_addr(arg, segs, nseg, error) 963 void *arg; 964 bus_dma_segment_t *segs; 965 int nseg; 966 int error; 967 { 968 bus_addr_t *addr; 969 970 if (error) 971 return; 972 973 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 974 addr = arg; 975 *addr = segs->ds_addr; 976 } 977 978 static int 979 re_allocmem(dev, sc) 980 device_t dev; 981 struct rl_softc *sc; 982 { 983 bus_size_t rx_list_size, tx_list_size; 984 int error; 985 int i; 986 987 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 988 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 989 990 /* 991 * Allocate the parent bus DMA tag appropriate for PCI. 992 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD 993 * register should be set. However some RealTek chips are known 994 * to be buggy on DAC handling, therefore disable DAC by limiting 995 * DMA address space to 32bit. PCIe variants of RealTek chips 996 * may not have the limitation but I took safer path. 997 */ 998 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 999 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1000 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 1001 NULL, NULL, &sc->rl_parent_tag); 1002 if (error) { 1003 device_printf(dev, "could not allocate parent DMA tag\n"); 1004 return (error); 1005 } 1006 1007 /* 1008 * Allocate map for TX mbufs. 1009 */ 1010 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 1011 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1012 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 1013 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 1014 if (error) { 1015 device_printf(dev, "could not allocate TX DMA tag\n"); 1016 return (error); 1017 } 1018 1019 /* 1020 * Allocate map for RX mbufs. 1021 */ 1022 1023 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 1024 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1025 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 1026 if (error) { 1027 device_printf(dev, "could not allocate RX DMA tag\n"); 1028 return (error); 1029 } 1030 1031 /* 1032 * Allocate map for TX descriptor list. 1033 */ 1034 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1035 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1036 NULL, tx_list_size, 1, tx_list_size, 0, 1037 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1038 if (error) { 1039 device_printf(dev, "could not allocate TX DMA ring tag\n"); 1040 return (error); 1041 } 1042 1043 /* Allocate DMA'able memory for the TX ring */ 1044 1045 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1046 (void **)&sc->rl_ldata.rl_tx_list, 1047 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1048 &sc->rl_ldata.rl_tx_list_map); 1049 if (error) { 1050 device_printf(dev, "could not allocate TX DMA ring\n"); 1051 return (error); 1052 } 1053 1054 /* Load the map for the TX ring. */ 1055 1056 sc->rl_ldata.rl_tx_list_addr = 0; 1057 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1058 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1059 tx_list_size, re_dma_map_addr, 1060 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1061 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 1062 device_printf(dev, "could not load TX DMA ring\n"); 1063 return (ENOMEM); 1064 } 1065 1066 /* Create DMA maps for TX buffers */ 1067 1068 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1069 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1070 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1071 if (error) { 1072 device_printf(dev, "could not create DMA map for TX\n"); 1073 return (error); 1074 } 1075 } 1076 1077 /* 1078 * Allocate map for RX descriptor list. 1079 */ 1080 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1081 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1082 NULL, rx_list_size, 1, rx_list_size, 0, 1083 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1084 if (error) { 1085 device_printf(dev, "could not create RX DMA ring tag\n"); 1086 return (error); 1087 } 1088 1089 /* Allocate DMA'able memory for the RX ring */ 1090 1091 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1092 (void **)&sc->rl_ldata.rl_rx_list, 1093 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1094 &sc->rl_ldata.rl_rx_list_map); 1095 if (error) { 1096 device_printf(dev, "could not allocate RX DMA ring\n"); 1097 return (error); 1098 } 1099 1100 /* Load the map for the RX ring. */ 1101 1102 sc->rl_ldata.rl_rx_list_addr = 0; 1103 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1104 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1105 rx_list_size, re_dma_map_addr, 1106 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1107 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1108 device_printf(dev, "could not load RX DMA ring\n"); 1109 return (ENOMEM); 1110 } 1111 1112 /* Create DMA maps for RX buffers */ 1113 1114 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1115 &sc->rl_ldata.rl_rx_sparemap); 1116 if (error) { 1117 device_printf(dev, "could not create spare DMA map for RX\n"); 1118 return (error); 1119 } 1120 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1121 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1122 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1123 if (error) { 1124 device_printf(dev, "could not create DMA map for RX\n"); 1125 return (error); 1126 } 1127 } 1128 1129 return (0); 1130 } 1131 1132 /* 1133 * Attach the interface. Allocate softc structures, do ifmedia 1134 * setup and ethernet/BPF attach. 1135 */ 1136 static int 1137 re_attach(dev) 1138 device_t dev; 1139 { 1140 u_char eaddr[ETHER_ADDR_LEN]; 1141 u_int16_t as[ETHER_ADDR_LEN / 2]; 1142 struct rl_softc *sc; 1143 struct ifnet *ifp; 1144 struct rl_hwrev *hw_rev; 1145 int hwrev; 1146 u_int16_t re_did = 0; 1147 int error = 0, rid, i; 1148 int msic, reg; 1149 uint8_t cfg; 1150 1151 sc = device_get_softc(dev); 1152 sc->rl_dev = dev; 1153 1154 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1155 MTX_DEF); 1156 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1157 1158 /* 1159 * Map control/status registers. 1160 */ 1161 pci_enable_busmaster(dev); 1162 1163 rid = RL_RID; 1164 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 1165 RF_ACTIVE); 1166 1167 if (sc->rl_res == NULL) { 1168 device_printf(dev, "couldn't map ports/memory\n"); 1169 error = ENXIO; 1170 goto fail; 1171 } 1172 1173 sc->rl_btag = rman_get_bustag(sc->rl_res); 1174 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1175 1176 msic = 0; 1177 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 1178 msic = pci_msi_count(dev); 1179 if (bootverbose) 1180 device_printf(dev, "MSI count : %d\n", msic); 1181 } 1182 if (msic == RL_MSI_MESSAGES && msi_disable == 0) { 1183 if (pci_alloc_msi(dev, &msic) == 0) { 1184 if (msic == RL_MSI_MESSAGES) { 1185 device_printf(dev, "Using %d MSI messages\n", 1186 msic); 1187 sc->rl_msi = 1; 1188 } else 1189 pci_release_msi(dev); 1190 } 1191 } 1192 1193 /* For MSI capable hardwares, explicitily set/clear MSI enable bit. */ 1194 if (msic != 0) { 1195 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1196 cfg = CSR_READ_1(sc, RL_CFG2); 1197 if (sc->rl_msi != 0) 1198 cfg |= RL_CFG2_MSI; 1199 else 1200 cfg &= ~RL_CFG2_MSI; 1201 CSR_WRITE_1(sc, RL_CFG2, cfg); 1202 CSR_WRITE_1(sc, RL_EECMD, 0); 1203 } 1204 1205 /* Allocate interrupt */ 1206 if (sc->rl_msi == 0) { 1207 rid = 0; 1208 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1209 RF_SHAREABLE | RF_ACTIVE); 1210 if (sc->rl_irq[0] == NULL) { 1211 device_printf(dev, "couldn't allocate IRQ resources\n"); 1212 error = ENXIO; 1213 goto fail; 1214 } 1215 } else { 1216 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1217 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1218 SYS_RES_IRQ, &rid, RF_ACTIVE); 1219 if (sc->rl_irq[i] == NULL) { 1220 device_printf(dev, 1221 "couldn't llocate IRQ resources for " 1222 "message %d\n", rid); 1223 error = ENXIO; 1224 goto fail; 1225 } 1226 } 1227 } 1228 1229 /* Reset the adapter. */ 1230 RL_LOCK(sc); 1231 re_reset(sc); 1232 RL_UNLOCK(sc); 1233 1234 hw_rev = re_hwrevs; 1235 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 1236 while (hw_rev->rl_desc != NULL) { 1237 if (hw_rev->rl_rev == hwrev) { 1238 sc->rl_type = hw_rev->rl_type; 1239 break; 1240 } 1241 hw_rev++; 1242 } 1243 if (hw_rev->rl_desc == NULL) { 1244 device_printf(dev, "Unknown H/W revision: %08x\n", hwrev); 1245 error = ENXIO; 1246 goto fail; 1247 } 1248 1249 sc->rl_eewidth = RL_9356_ADDR_LEN; 1250 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1251 if (re_did != 0x8129) 1252 sc->rl_eewidth = RL_9346_ADDR_LEN; 1253 1254 /* 1255 * Get station address from the EEPROM. 1256 */ 1257 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1258 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1259 as[i] = le16toh(as[i]); 1260 bcopy(as, eaddr, sizeof(eaddr)); 1261 1262 if (sc->rl_type == RL_8169) { 1263 /* Set RX length mask and number of descriptors. */ 1264 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1265 sc->rl_txstart = RL_GTXSTART; 1266 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1267 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1268 } else { 1269 /* Set RX length mask and number of descriptors. */ 1270 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1271 sc->rl_txstart = RL_TXSTART; 1272 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1273 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1274 } 1275 if (hw_rev->rl_desc == NULL) { 1276 device_printf(dev, "Unsupported revision : 0x%08x\n", hwrev); 1277 error = ENXIO; 1278 goto fail; 1279 } 1280 1281 error = re_allocmem(dev, sc); 1282 if (error) 1283 goto fail; 1284 1285 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1286 if (ifp == NULL) { 1287 device_printf(dev, "can not if_alloc()\n"); 1288 error = ENOSPC; 1289 goto fail; 1290 } 1291 1292 /* Do MII setup */ 1293 if (mii_phy_probe(dev, &sc->rl_miibus, 1294 re_ifmedia_upd, re_ifmedia_sts)) { 1295 device_printf(dev, "MII without any phy!\n"); 1296 error = ENXIO; 1297 goto fail; 1298 } 1299 1300 /* Take PHY out of power down mode. */ 1301 if (sc->rl_type == RL_8169) { 1302 uint32_t rev; 1303 1304 rev = CSR_READ_4(sc, RL_TXCFG); 1305 /* HWVERID 0, 1 and 2 : bit26-30, bit23 */ 1306 rev &= 0x7c800000; 1307 if (rev != 0) { 1308 /* RTL8169S single chip */ 1309 switch (rev) { 1310 case RL_HWREV_8169_8110SB: 1311 case RL_HWREV_8169_8110SC: 1312 case RL_HWREV_8168_SPIN2: 1313 case RL_HWREV_8168_SPIN3: 1314 re_gmii_writereg(dev, 1, 0x1f, 0); 1315 re_gmii_writereg(dev, 1, 0x0e, 0); 1316 break; 1317 default: 1318 break; 1319 } 1320 } 1321 } 1322 1323 ifp->if_softc = sc; 1324 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1325 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1326 ifp->if_ioctl = re_ioctl; 1327 ifp->if_start = re_start; 1328 ifp->if_hwassist = RE_CSUM_FEATURES | CSUM_TSO; 1329 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 1330 ifp->if_capenable = ifp->if_capabilities; 1331 ifp->if_init = re_init; 1332 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1333 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1334 IFQ_SET_READY(&ifp->if_snd); 1335 1336 TASK_INIT(&sc->rl_txtask, 1, re_tx_task, ifp); 1337 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1338 1339 /* 1340 * Call MI attach routine. 1341 */ 1342 ether_ifattach(ifp, eaddr); 1343 1344 /* VLAN capability setup */ 1345 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1346 if (ifp->if_capabilities & IFCAP_HWCSUM) 1347 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1348 /* Enable WOL if PM is supported. */ 1349 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, ®) == 0) 1350 ifp->if_capabilities |= IFCAP_WOL; 1351 ifp->if_capenable = ifp->if_capabilities; 1352 #ifdef DEVICE_POLLING 1353 ifp->if_capabilities |= IFCAP_POLLING; 1354 #endif 1355 /* 1356 * Tell the upper layer(s) we support long frames. 1357 * Must appear after the call to ether_ifattach() because 1358 * ether_ifattach() sets ifi_hdrlen to the default value. 1359 */ 1360 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1361 1362 #ifdef RE_DIAG 1363 /* 1364 * Perform hardware diagnostic on the original RTL8169. 1365 * Some 32-bit cards were incorrectly wired and would 1366 * malfunction if plugged into a 64-bit slot. 1367 */ 1368 1369 if (hwrev == RL_HWREV_8169) { 1370 error = re_diag(sc); 1371 if (error) { 1372 device_printf(dev, 1373 "attach aborted due to hardware diag failure\n"); 1374 ether_ifdetach(ifp); 1375 goto fail; 1376 } 1377 } 1378 #endif 1379 1380 /* Hook interrupt last to avoid having to lock softc */ 1381 if (sc->rl_msi == 0) 1382 error = bus_setup_intr(dev, sc->rl_irq[0], 1383 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1384 &sc->rl_intrhand[0]); 1385 else { 1386 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1387 error = bus_setup_intr(dev, sc->rl_irq[i], 1388 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1389 &sc->rl_intrhand[i]); 1390 if (error != 0) 1391 break; 1392 } 1393 } 1394 if (error) { 1395 device_printf(dev, "couldn't set up irq\n"); 1396 ether_ifdetach(ifp); 1397 } 1398 1399 fail: 1400 1401 if (error) 1402 re_detach(dev); 1403 1404 return (error); 1405 } 1406 1407 /* 1408 * Shutdown hardware and free up resources. This can be called any 1409 * time after the mutex has been initialized. It is called in both 1410 * the error case in attach and the normal detach case so it needs 1411 * to be careful about only freeing resources that have actually been 1412 * allocated. 1413 */ 1414 static int 1415 re_detach(dev) 1416 device_t dev; 1417 { 1418 struct rl_softc *sc; 1419 struct ifnet *ifp; 1420 int i, rid; 1421 1422 sc = device_get_softc(dev); 1423 ifp = sc->rl_ifp; 1424 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1425 1426 #ifdef DEVICE_POLLING 1427 if (ifp->if_capenable & IFCAP_POLLING) 1428 ether_poll_deregister(ifp); 1429 #endif 1430 /* These should only be active if attach succeeded */ 1431 if (device_is_attached(dev)) { 1432 RL_LOCK(sc); 1433 #if 0 1434 sc->suspended = 1; 1435 #endif 1436 re_stop(sc); 1437 RL_UNLOCK(sc); 1438 callout_drain(&sc->rl_stat_callout); 1439 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1440 taskqueue_drain(taskqueue_fast, &sc->rl_txtask); 1441 /* 1442 * Force off the IFF_UP flag here, in case someone 1443 * still had a BPF descriptor attached to this 1444 * interface. If they do, ether_ifdetach() will cause 1445 * the BPF code to try and clear the promisc mode 1446 * flag, which will bubble down to re_ioctl(), 1447 * which will try to call re_init() again. This will 1448 * turn the NIC back on and restart the MII ticker, 1449 * which will panic the system when the kernel tries 1450 * to invoke the re_tick() function that isn't there 1451 * anymore. 1452 */ 1453 ifp->if_flags &= ~IFF_UP; 1454 ether_ifdetach(ifp); 1455 } 1456 if (sc->rl_miibus) 1457 device_delete_child(dev, sc->rl_miibus); 1458 bus_generic_detach(dev); 1459 1460 /* 1461 * The rest is resource deallocation, so we should already be 1462 * stopped here. 1463 */ 1464 1465 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1466 if (sc->rl_intrhand[i] != NULL) { 1467 bus_teardown_intr(dev, sc->rl_irq[i], 1468 sc->rl_intrhand[i]); 1469 sc->rl_intrhand[i] = NULL; 1470 } 1471 } 1472 if (ifp != NULL) 1473 if_free(ifp); 1474 if (sc->rl_msi == 0) { 1475 if (sc->rl_irq[0] != NULL) { 1476 bus_release_resource(dev, SYS_RES_IRQ, 0, 1477 sc->rl_irq[0]); 1478 sc->rl_irq[0] = NULL; 1479 } 1480 } else { 1481 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1482 if (sc->rl_irq[i] != NULL) { 1483 bus_release_resource(dev, SYS_RES_IRQ, rid, 1484 sc->rl_irq[i]); 1485 sc->rl_irq[i] = NULL; 1486 } 1487 } 1488 pci_release_msi(dev); 1489 } 1490 if (sc->rl_res) 1491 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1492 1493 /* Unload and free the RX DMA ring memory and map */ 1494 1495 if (sc->rl_ldata.rl_rx_list_tag) { 1496 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1497 sc->rl_ldata.rl_rx_list_map); 1498 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1499 sc->rl_ldata.rl_rx_list, 1500 sc->rl_ldata.rl_rx_list_map); 1501 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1502 } 1503 1504 /* Unload and free the TX DMA ring memory and map */ 1505 1506 if (sc->rl_ldata.rl_tx_list_tag) { 1507 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1508 sc->rl_ldata.rl_tx_list_map); 1509 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1510 sc->rl_ldata.rl_tx_list, 1511 sc->rl_ldata.rl_tx_list_map); 1512 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1513 } 1514 1515 /* Destroy all the RX and TX buffer maps */ 1516 1517 if (sc->rl_ldata.rl_tx_mtag) { 1518 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1519 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1520 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1521 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1522 } 1523 if (sc->rl_ldata.rl_rx_mtag) { 1524 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) 1525 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1526 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1527 if (sc->rl_ldata.rl_rx_sparemap) 1528 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1529 sc->rl_ldata.rl_rx_sparemap); 1530 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1531 } 1532 1533 /* Unload and free the stats buffer and map */ 1534 1535 if (sc->rl_ldata.rl_stag) { 1536 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1537 sc->rl_ldata.rl_rx_list_map); 1538 bus_dmamem_free(sc->rl_ldata.rl_stag, 1539 sc->rl_ldata.rl_stats, 1540 sc->rl_ldata.rl_smap); 1541 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1542 } 1543 1544 if (sc->rl_parent_tag) 1545 bus_dma_tag_destroy(sc->rl_parent_tag); 1546 1547 mtx_destroy(&sc->rl_mtx); 1548 1549 return (0); 1550 } 1551 1552 static __inline void 1553 re_discard_rxbuf(sc, idx) 1554 struct rl_softc *sc; 1555 int idx; 1556 { 1557 struct rl_desc *desc; 1558 struct rl_rxdesc *rxd; 1559 uint32_t cmdstat; 1560 1561 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1562 desc = &sc->rl_ldata.rl_rx_list[idx]; 1563 desc->rl_vlanctl = 0; 1564 cmdstat = rxd->rx_size; 1565 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1566 cmdstat |= RL_RDESC_CMD_EOR; 1567 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1568 } 1569 1570 static int 1571 re_newbuf(sc, idx) 1572 struct rl_softc *sc; 1573 int idx; 1574 { 1575 struct mbuf *m; 1576 struct rl_rxdesc *rxd; 1577 bus_dma_segment_t segs[1]; 1578 bus_dmamap_t map; 1579 struct rl_desc *desc; 1580 uint32_t cmdstat; 1581 int error, nsegs; 1582 1583 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1584 if (m == NULL) 1585 return (ENOBUFS); 1586 1587 m->m_len = m->m_pkthdr.len = MCLBYTES; 1588 #ifdef RE_FIXUP_RX 1589 /* 1590 * This is part of an evil trick to deal with non-x86 platforms. 1591 * The RealTek chip requires RX buffers to be aligned on 64-bit 1592 * boundaries, but that will hose non-x86 machines. To get around 1593 * this, we leave some empty space at the start of each buffer 1594 * and for non-x86 hosts, we copy the buffer back six bytes 1595 * to achieve word alignment. This is slightly more efficient 1596 * than allocating a new buffer, copying the contents, and 1597 * discarding the old buffer. 1598 */ 1599 m_adj(m, RE_ETHER_ALIGN); 1600 #endif 1601 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1602 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1603 if (error != 0) { 1604 m_freem(m); 1605 return (ENOBUFS); 1606 } 1607 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1608 1609 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1610 if (rxd->rx_m != NULL) { 1611 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1612 BUS_DMASYNC_POSTREAD); 1613 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1614 } 1615 1616 rxd->rx_m = m; 1617 map = rxd->rx_dmamap; 1618 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1619 rxd->rx_size = segs[0].ds_len; 1620 sc->rl_ldata.rl_rx_sparemap = map; 1621 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1622 BUS_DMASYNC_PREREAD); 1623 1624 desc = &sc->rl_ldata.rl_rx_list[idx]; 1625 desc->rl_vlanctl = 0; 1626 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1627 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1628 cmdstat = segs[0].ds_len; 1629 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1630 cmdstat |= RL_RDESC_CMD_EOR; 1631 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1632 1633 return (0); 1634 } 1635 1636 #ifdef RE_FIXUP_RX 1637 static __inline void 1638 re_fixup_rx(m) 1639 struct mbuf *m; 1640 { 1641 int i; 1642 uint16_t *src, *dst; 1643 1644 src = mtod(m, uint16_t *); 1645 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1646 1647 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1648 *dst++ = *src++; 1649 1650 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1651 1652 return; 1653 } 1654 #endif 1655 1656 static int 1657 re_tx_list_init(sc) 1658 struct rl_softc *sc; 1659 { 1660 struct rl_desc *desc; 1661 int i; 1662 1663 RL_LOCK_ASSERT(sc); 1664 1665 bzero(sc->rl_ldata.rl_tx_list, 1666 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 1667 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1668 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 1669 /* Set EOR. */ 1670 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 1671 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 1672 1673 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1674 sc->rl_ldata.rl_tx_list_map, 1675 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1676 1677 sc->rl_ldata.rl_tx_prodidx = 0; 1678 sc->rl_ldata.rl_tx_considx = 0; 1679 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 1680 1681 return (0); 1682 } 1683 1684 static int 1685 re_rx_list_init(sc) 1686 struct rl_softc *sc; 1687 { 1688 int error, i; 1689 1690 bzero(sc->rl_ldata.rl_rx_list, 1691 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 1692 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1693 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 1694 if ((error = re_newbuf(sc, i)) != 0) 1695 return (error); 1696 } 1697 1698 /* Flush the RX descriptors */ 1699 1700 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1701 sc->rl_ldata.rl_rx_list_map, 1702 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1703 1704 sc->rl_ldata.rl_rx_prodidx = 0; 1705 sc->rl_head = sc->rl_tail = NULL; 1706 1707 return (0); 1708 } 1709 1710 /* 1711 * RX handler for C+ and 8169. For the gigE chips, we support 1712 * the reception of jumbo frames that have been fragmented 1713 * across multiple 2K mbuf cluster buffers. 1714 */ 1715 static int 1716 re_rxeof(sc) 1717 struct rl_softc *sc; 1718 { 1719 struct mbuf *m; 1720 struct ifnet *ifp; 1721 int i, total_len; 1722 struct rl_desc *cur_rx; 1723 u_int32_t rxstat, rxvlan; 1724 int maxpkt = 16; 1725 1726 RL_LOCK_ASSERT(sc); 1727 1728 ifp = sc->rl_ifp; 1729 1730 /* Invalidate the descriptor memory */ 1731 1732 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1733 sc->rl_ldata.rl_rx_list_map, 1734 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1735 1736 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 1737 i = RL_RX_DESC_NXT(sc, i)) { 1738 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1739 rxstat = le32toh(cur_rx->rl_cmdstat); 1740 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 1741 break; 1742 total_len = rxstat & sc->rl_rxlenmask; 1743 rxvlan = le32toh(cur_rx->rl_vlanctl); 1744 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 1745 1746 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1747 if (re_newbuf(sc, i) != 0) { 1748 /* 1749 * If this is part of a multi-fragment packet, 1750 * discard all the pieces. 1751 */ 1752 if (sc->rl_head != NULL) { 1753 m_freem(sc->rl_head); 1754 sc->rl_head = sc->rl_tail = NULL; 1755 } 1756 re_discard_rxbuf(sc, i); 1757 continue; 1758 } 1759 m->m_len = RE_RX_DESC_BUFLEN; 1760 if (sc->rl_head == NULL) 1761 sc->rl_head = sc->rl_tail = m; 1762 else { 1763 m->m_flags &= ~M_PKTHDR; 1764 sc->rl_tail->m_next = m; 1765 sc->rl_tail = m; 1766 } 1767 continue; 1768 } 1769 1770 /* 1771 * NOTE: for the 8139C+, the frame length field 1772 * is always 12 bits in size, but for the gigE chips, 1773 * it is 13 bits (since the max RX frame length is 16K). 1774 * Unfortunately, all 32 bits in the status word 1775 * were already used, so to make room for the extra 1776 * length bit, RealTek took out the 'frame alignment 1777 * error' bit and shifted the other status bits 1778 * over one slot. The OWN, EOR, FS and LS bits are 1779 * still in the same places. We have already extracted 1780 * the frame length and checked the OWN bit, so rather 1781 * than using an alternate bit mapping, we shift the 1782 * status bits one space to the right so we can evaluate 1783 * them using the 8169 status as though it was in the 1784 * same format as that of the 8139C+. 1785 */ 1786 if (sc->rl_type == RL_8169) 1787 rxstat >>= 1; 1788 1789 /* 1790 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 1791 * set, but if CRC is clear, it will still be a valid frame. 1792 */ 1793 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 && 1794 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) { 1795 ifp->if_ierrors++; 1796 /* 1797 * If this is part of a multi-fragment packet, 1798 * discard all the pieces. 1799 */ 1800 if (sc->rl_head != NULL) { 1801 m_freem(sc->rl_head); 1802 sc->rl_head = sc->rl_tail = NULL; 1803 } 1804 re_discard_rxbuf(sc, i); 1805 continue; 1806 } 1807 1808 /* 1809 * If allocating a replacement mbuf fails, 1810 * reload the current one. 1811 */ 1812 1813 if (re_newbuf(sc, i) != 0) { 1814 ifp->if_iqdrops++; 1815 if (sc->rl_head != NULL) { 1816 m_freem(sc->rl_head); 1817 sc->rl_head = sc->rl_tail = NULL; 1818 } 1819 re_discard_rxbuf(sc, i); 1820 continue; 1821 } 1822 1823 if (sc->rl_head != NULL) { 1824 m->m_len = total_len % RE_RX_DESC_BUFLEN; 1825 if (m->m_len == 0) 1826 m->m_len = RE_RX_DESC_BUFLEN; 1827 /* 1828 * Special case: if there's 4 bytes or less 1829 * in this buffer, the mbuf can be discarded: 1830 * the last 4 bytes is the CRC, which we don't 1831 * care about anyway. 1832 */ 1833 if (m->m_len <= ETHER_CRC_LEN) { 1834 sc->rl_tail->m_len -= 1835 (ETHER_CRC_LEN - m->m_len); 1836 m_freem(m); 1837 } else { 1838 m->m_len -= ETHER_CRC_LEN; 1839 m->m_flags &= ~M_PKTHDR; 1840 sc->rl_tail->m_next = m; 1841 } 1842 m = sc->rl_head; 1843 sc->rl_head = sc->rl_tail = NULL; 1844 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1845 } else 1846 m->m_pkthdr.len = m->m_len = 1847 (total_len - ETHER_CRC_LEN); 1848 1849 #ifdef RE_FIXUP_RX 1850 re_fixup_rx(m); 1851 #endif 1852 ifp->if_ipackets++; 1853 m->m_pkthdr.rcvif = ifp; 1854 1855 /* Do RX checksumming if enabled */ 1856 1857 if (ifp->if_capenable & IFCAP_RXCSUM) { 1858 1859 /* Check IP header checksum */ 1860 if (rxstat & RL_RDESC_STAT_PROTOID) 1861 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1862 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1863 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1864 1865 /* Check TCP/UDP checksum */ 1866 if ((RL_TCPPKT(rxstat) && 1867 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1868 (RL_UDPPKT(rxstat) && 1869 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1870 m->m_pkthdr.csum_flags |= 1871 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1872 m->m_pkthdr.csum_data = 0xffff; 1873 } 1874 } 1875 maxpkt--; 1876 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 1877 m->m_pkthdr.ether_vtag = 1878 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)); 1879 m->m_flags |= M_VLANTAG; 1880 } 1881 RL_UNLOCK(sc); 1882 (*ifp->if_input)(ifp, m); 1883 RL_LOCK(sc); 1884 } 1885 1886 /* Flush the RX DMA ring */ 1887 1888 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1889 sc->rl_ldata.rl_rx_list_map, 1890 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1891 1892 sc->rl_ldata.rl_rx_prodidx = i; 1893 1894 if (maxpkt) 1895 return(EAGAIN); 1896 1897 return(0); 1898 } 1899 1900 static void 1901 re_txeof(sc) 1902 struct rl_softc *sc; 1903 { 1904 struct ifnet *ifp; 1905 struct rl_txdesc *txd; 1906 u_int32_t txstat; 1907 int cons; 1908 1909 cons = sc->rl_ldata.rl_tx_considx; 1910 if (cons == sc->rl_ldata.rl_tx_prodidx) 1911 return; 1912 1913 ifp = sc->rl_ifp; 1914 /* Invalidate the TX descriptor list */ 1915 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1916 sc->rl_ldata.rl_tx_list_map, 1917 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1918 1919 for (; cons != sc->rl_ldata.rl_tx_prodidx; 1920 cons = RL_TX_DESC_NXT(sc, cons)) { 1921 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 1922 if (txstat & RL_TDESC_STAT_OWN) 1923 break; 1924 /* 1925 * We only stash mbufs in the last descriptor 1926 * in a fragment chain, which also happens to 1927 * be the only place where the TX status bits 1928 * are valid. 1929 */ 1930 if (txstat & RL_TDESC_CMD_EOF) { 1931 txd = &sc->rl_ldata.rl_tx_desc[cons]; 1932 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 1933 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 1934 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 1935 txd->tx_dmamap); 1936 KASSERT(txd->tx_m != NULL, 1937 ("%s: freeing NULL mbufs!", __func__)); 1938 m_freem(txd->tx_m); 1939 txd->tx_m = NULL; 1940 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 1941 RL_TDESC_STAT_COLCNT)) 1942 ifp->if_collisions++; 1943 if (txstat & RL_TDESC_STAT_TXERRSUM) 1944 ifp->if_oerrors++; 1945 else 1946 ifp->if_opackets++; 1947 } 1948 sc->rl_ldata.rl_tx_free++; 1949 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1950 } 1951 sc->rl_ldata.rl_tx_considx = cons; 1952 1953 /* No changes made to the TX ring, so no flush needed */ 1954 1955 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 1956 /* 1957 * Some chips will ignore a second TX request issued 1958 * while an existing transmission is in progress. If 1959 * the transmitter goes idle but there are still 1960 * packets waiting to be sent, we need to restart the 1961 * channel here to flush them out. This only seems to 1962 * be required with the PCIe devices. 1963 */ 1964 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 1965 1966 #ifdef RE_TX_MODERATION 1967 /* 1968 * If not all descriptors have been reaped yet, reload 1969 * the timer so that we will eventually get another 1970 * interrupt that will cause us to re-enter this routine. 1971 * This is done in case the transmitter has gone idle. 1972 */ 1973 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 1974 #endif 1975 } else 1976 sc->rl_watchdog_timer = 0; 1977 } 1978 1979 static void 1980 re_tick(xsc) 1981 void *xsc; 1982 { 1983 struct rl_softc *sc; 1984 struct mii_data *mii; 1985 struct ifnet *ifp; 1986 1987 sc = xsc; 1988 ifp = sc->rl_ifp; 1989 1990 RL_LOCK_ASSERT(sc); 1991 1992 re_watchdog(sc); 1993 1994 mii = device_get_softc(sc->rl_miibus); 1995 mii_tick(mii); 1996 if (sc->rl_link) { 1997 if (!(mii->mii_media_status & IFM_ACTIVE)) 1998 sc->rl_link = 0; 1999 } else { 2000 if (mii->mii_media_status & IFM_ACTIVE && 2001 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2002 sc->rl_link = 1; 2003 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2004 taskqueue_enqueue_fast(taskqueue_fast, 2005 &sc->rl_txtask); 2006 } 2007 } 2008 2009 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2010 } 2011 2012 #ifdef DEVICE_POLLING 2013 static void 2014 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2015 { 2016 struct rl_softc *sc = ifp->if_softc; 2017 2018 RL_LOCK(sc); 2019 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2020 re_poll_locked(ifp, cmd, count); 2021 RL_UNLOCK(sc); 2022 } 2023 2024 static void 2025 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2026 { 2027 struct rl_softc *sc = ifp->if_softc; 2028 2029 RL_LOCK_ASSERT(sc); 2030 2031 sc->rxcycles = count; 2032 re_rxeof(sc); 2033 re_txeof(sc); 2034 2035 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2036 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2037 2038 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2039 u_int16_t status; 2040 2041 status = CSR_READ_2(sc, RL_ISR); 2042 if (status == 0xffff) 2043 return; 2044 if (status) 2045 CSR_WRITE_2(sc, RL_ISR, status); 2046 2047 /* 2048 * XXX check behaviour on receiver stalls. 2049 */ 2050 2051 if (status & RL_ISR_SYSTEM_ERR) { 2052 re_reset(sc); 2053 re_init_locked(sc); 2054 } 2055 } 2056 } 2057 #endif /* DEVICE_POLLING */ 2058 2059 static int 2060 re_intr(arg) 2061 void *arg; 2062 { 2063 struct rl_softc *sc; 2064 uint16_t status; 2065 2066 sc = arg; 2067 2068 status = CSR_READ_2(sc, RL_ISR); 2069 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2070 return (FILTER_STRAY); 2071 CSR_WRITE_2(sc, RL_IMR, 0); 2072 2073 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2074 2075 return (FILTER_HANDLED); 2076 } 2077 2078 static void 2079 re_int_task(arg, npending) 2080 void *arg; 2081 int npending; 2082 { 2083 struct rl_softc *sc; 2084 struct ifnet *ifp; 2085 u_int16_t status; 2086 int rval = 0; 2087 2088 sc = arg; 2089 ifp = sc->rl_ifp; 2090 2091 RL_LOCK(sc); 2092 2093 status = CSR_READ_2(sc, RL_ISR); 2094 CSR_WRITE_2(sc, RL_ISR, status); 2095 2096 if (sc->suspended || 2097 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2098 RL_UNLOCK(sc); 2099 return; 2100 } 2101 2102 #ifdef DEVICE_POLLING 2103 if (ifp->if_capenable & IFCAP_POLLING) { 2104 RL_UNLOCK(sc); 2105 return; 2106 } 2107 #endif 2108 2109 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2110 rval = re_rxeof(sc); 2111 2112 #ifdef RE_TX_MODERATION 2113 if (status & (RL_ISR_TIMEOUT_EXPIRED| 2114 #else 2115 if (status & (RL_ISR_TX_OK| 2116 #endif 2117 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2118 re_txeof(sc); 2119 2120 if (status & RL_ISR_SYSTEM_ERR) { 2121 re_reset(sc); 2122 re_init_locked(sc); 2123 } 2124 2125 if (status & RL_ISR_LINKCHG) { 2126 callout_stop(&sc->rl_stat_callout); 2127 re_tick(sc); 2128 } 2129 2130 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2131 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2132 2133 RL_UNLOCK(sc); 2134 2135 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2136 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2137 return; 2138 } 2139 2140 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2141 2142 return; 2143 } 2144 2145 static int 2146 re_encap(sc, m_head) 2147 struct rl_softc *sc; 2148 struct mbuf **m_head; 2149 { 2150 struct rl_txdesc *txd, *txd_last; 2151 bus_dma_segment_t segs[RL_NTXSEGS]; 2152 bus_dmamap_t map; 2153 struct mbuf *m_new; 2154 struct rl_desc *desc; 2155 int nsegs, prod; 2156 int i, error, ei, si; 2157 int padlen; 2158 uint32_t cmdstat, csum_flags, vlanctl; 2159 2160 RL_LOCK_ASSERT(sc); 2161 M_ASSERTPKTHDR((*m_head)); 2162 2163 /* 2164 * With some of the RealTek chips, using the checksum offload 2165 * support in conjunction with the autopadding feature results 2166 * in the transmission of corrupt frames. For example, if we 2167 * need to send a really small IP fragment that's less than 60 2168 * bytes in size, and IP header checksumming is enabled, the 2169 * resulting ethernet frame that appears on the wire will 2170 * have garbled payload. To work around this, if TX checksum 2171 * offload is enabled, we always manually pad short frames out 2172 * to the minimum ethernet frame size. 2173 * 2174 * Note: this appears unnecessary for TCP, and doing it for TCP 2175 * with PCIe adapters seems to result in bad checksums. 2176 */ 2177 if ((*m_head)->m_pkthdr.csum_flags & (CSUM_IP | CSUM_UDP) && 2178 ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) == 0 && 2179 (*m_head)->m_pkthdr.len < RL_MIN_FRAMELEN) { 2180 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2181 if (M_WRITABLE(*m_head) == 0) { 2182 /* Get a writable copy. */ 2183 m_new = m_dup(*m_head, M_DONTWAIT); 2184 m_freem(*m_head); 2185 if (m_new == NULL) { 2186 *m_head = NULL; 2187 return (ENOBUFS); 2188 } 2189 *m_head = m_new; 2190 } 2191 if ((*m_head)->m_next != NULL || 2192 M_TRAILINGSPACE(*m_head) < padlen) { 2193 m_new = m_defrag(*m_head, M_DONTWAIT); 2194 if (m_new == NULL) { 2195 m_freem(*m_head); 2196 *m_head = NULL; 2197 return (ENOBUFS); 2198 } 2199 } else 2200 m_new = *m_head; 2201 2202 /* 2203 * Manually pad short frames, and zero the pad space 2204 * to avoid leaking data. 2205 */ 2206 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2207 m_new->m_pkthdr.len += padlen; 2208 m_new->m_len = m_new->m_pkthdr.len; 2209 *m_head = m_new; 2210 } 2211 2212 prod = sc->rl_ldata.rl_tx_prodidx; 2213 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2214 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2215 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2216 if (error == EFBIG) { 2217 m_new = m_collapse(*m_head, M_DONTWAIT, RL_NTXSEGS); 2218 if (m_new == NULL) { 2219 m_freem(*m_head); 2220 *m_head = NULL; 2221 return (ENOBUFS); 2222 } 2223 *m_head = m_new; 2224 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2225 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2226 if (error != 0) { 2227 m_freem(*m_head); 2228 *m_head = NULL; 2229 return (error); 2230 } 2231 } else if (error != 0) 2232 return (error); 2233 if (nsegs == 0) { 2234 m_freem(*m_head); 2235 *m_head = NULL; 2236 return (EIO); 2237 } 2238 2239 /* Check for number of available descriptors. */ 2240 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2241 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2242 return (ENOBUFS); 2243 } 2244 2245 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2246 BUS_DMASYNC_PREWRITE); 2247 2248 /* 2249 * Set up checksum offload. Note: checksum offload bits must 2250 * appear in all descriptors of a multi-descriptor transmit 2251 * attempt. This is according to testing done with an 8169 2252 * chip. This is a requirement. 2253 */ 2254 csum_flags = 0; 2255 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) 2256 csum_flags = RL_TDESC_CMD_LGSEND | 2257 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2258 RL_TDESC_CMD_MSSVAL_SHIFT); 2259 else { 2260 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) 2261 csum_flags |= RL_TDESC_CMD_IPCSUM; 2262 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) 2263 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2264 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) 2265 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2266 } 2267 2268 /* 2269 * Set up hardware VLAN tagging. Note: vlan tag info must 2270 * appear in all descriptors of a multi-descriptor 2271 * transmission attempt. 2272 */ 2273 vlanctl = 0; 2274 if ((*m_head)->m_flags & M_VLANTAG) 2275 vlanctl = 2276 htole32(htons((*m_head)->m_pkthdr.ether_vtag) | 2277 RL_TDESC_VLANCTL_TAG); 2278 2279 si = prod; 2280 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2281 desc = &sc->rl_ldata.rl_tx_list[prod]; 2282 desc->rl_vlanctl = vlanctl; 2283 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2284 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2285 cmdstat = segs[i].ds_len; 2286 if (i != 0) 2287 cmdstat |= RL_TDESC_CMD_OWN; 2288 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2289 cmdstat |= RL_TDESC_CMD_EOR; 2290 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2291 sc->rl_ldata.rl_tx_free--; 2292 } 2293 /* Update producer index. */ 2294 sc->rl_ldata.rl_tx_prodidx = prod; 2295 2296 /* Set EOF on the last descriptor. */ 2297 ei = RL_TX_DESC_PRV(sc, prod); 2298 desc = &sc->rl_ldata.rl_tx_list[ei]; 2299 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2300 2301 desc = &sc->rl_ldata.rl_tx_list[si]; 2302 /* Set SOF and transfer ownership of packet to the chip. */ 2303 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2304 2305 /* 2306 * Insure that the map for this transmission 2307 * is placed at the array index of the last descriptor 2308 * in this chain. (Swap last and first dmamaps.) 2309 */ 2310 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2311 map = txd->tx_dmamap; 2312 txd->tx_dmamap = txd_last->tx_dmamap; 2313 txd_last->tx_dmamap = map; 2314 txd_last->tx_m = *m_head; 2315 2316 return (0); 2317 } 2318 2319 static void 2320 re_tx_task(arg, npending) 2321 void *arg; 2322 int npending; 2323 { 2324 struct ifnet *ifp; 2325 2326 ifp = arg; 2327 re_start(ifp); 2328 2329 return; 2330 } 2331 2332 /* 2333 * Main transmit routine for C+ and gigE NICs. 2334 */ 2335 static void 2336 re_start(ifp) 2337 struct ifnet *ifp; 2338 { 2339 struct rl_softc *sc; 2340 struct mbuf *m_head; 2341 int queued; 2342 2343 sc = ifp->if_softc; 2344 2345 RL_LOCK(sc); 2346 2347 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2348 IFF_DRV_RUNNING || sc->rl_link == 0) { 2349 RL_UNLOCK(sc); 2350 return; 2351 } 2352 2353 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2354 sc->rl_ldata.rl_tx_free > 1;) { 2355 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2356 if (m_head == NULL) 2357 break; 2358 2359 if (re_encap(sc, &m_head) != 0) { 2360 if (m_head == NULL) 2361 break; 2362 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2363 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2364 break; 2365 } 2366 2367 /* 2368 * If there's a BPF listener, bounce a copy of this frame 2369 * to him. 2370 */ 2371 ETHER_BPF_MTAP(ifp, m_head); 2372 2373 queued++; 2374 } 2375 2376 if (queued == 0) { 2377 #ifdef RE_TX_MODERATION 2378 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2379 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2380 #endif 2381 RL_UNLOCK(sc); 2382 return; 2383 } 2384 2385 /* Flush the TX descriptors */ 2386 2387 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2388 sc->rl_ldata.rl_tx_list_map, 2389 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2390 2391 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2392 2393 #ifdef RE_TX_MODERATION 2394 /* 2395 * Use the countdown timer for interrupt moderation. 2396 * 'TX done' interrupts are disabled. Instead, we reset the 2397 * countdown timer, which will begin counting until it hits 2398 * the value in the TIMERINT register, and then trigger an 2399 * interrupt. Each time we write to the TIMERCNT register, 2400 * the timer count is reset to 0. 2401 */ 2402 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2403 #endif 2404 2405 /* 2406 * Set a timeout in case the chip goes out to lunch. 2407 */ 2408 sc->rl_watchdog_timer = 5; 2409 2410 RL_UNLOCK(sc); 2411 2412 return; 2413 } 2414 2415 static void 2416 re_init(xsc) 2417 void *xsc; 2418 { 2419 struct rl_softc *sc = xsc; 2420 2421 RL_LOCK(sc); 2422 re_init_locked(sc); 2423 RL_UNLOCK(sc); 2424 } 2425 2426 static void 2427 re_init_locked(sc) 2428 struct rl_softc *sc; 2429 { 2430 struct ifnet *ifp = sc->rl_ifp; 2431 struct mii_data *mii; 2432 u_int32_t rxcfg = 0; 2433 uint16_t cfg; 2434 union { 2435 uint32_t align_dummy; 2436 u_char eaddr[ETHER_ADDR_LEN]; 2437 } eaddr; 2438 2439 RL_LOCK_ASSERT(sc); 2440 2441 mii = device_get_softc(sc->rl_miibus); 2442 2443 /* 2444 * Cancel pending I/O and free all RX/TX buffers. 2445 */ 2446 re_stop(sc); 2447 2448 /* 2449 * Enable C+ RX and TX mode, as well as VLAN stripping and 2450 * RX checksum offload. We must configure the C+ register 2451 * before all others. 2452 */ 2453 cfg = RL_CPLUSCMD_PCI_MRW; 2454 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2455 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 2456 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2457 cfg |= RL_CPLUSCMD_VLANSTRIP; 2458 CSR_WRITE_2(sc, RL_CPLUS_CMD, 2459 cfg | RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB); 2460 2461 /* 2462 * Init our MAC address. Even though the chipset 2463 * documentation doesn't mention it, we need to enter "Config 2464 * register write enable" mode to modify the ID registers. 2465 */ 2466 /* Copy MAC address on stack to align. */ 2467 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 2468 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2469 CSR_WRITE_4(sc, RL_IDR0, 2470 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 2471 CSR_WRITE_4(sc, RL_IDR4, 2472 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 2473 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2474 2475 /* 2476 * For C+ mode, initialize the RX descriptors and mbufs. 2477 */ 2478 re_rx_list_init(sc); 2479 re_tx_list_init(sc); 2480 2481 /* 2482 * Load the addresses of the RX and TX lists into the chip. 2483 */ 2484 2485 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2486 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2487 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2488 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2489 2490 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2491 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2492 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2493 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2494 2495 /* 2496 * Enable transmit and receive. 2497 */ 2498 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2499 2500 /* 2501 * Set the initial TX and RX configuration. 2502 */ 2503 if (sc->rl_testmode) { 2504 if (sc->rl_type == RL_8169) 2505 CSR_WRITE_4(sc, RL_TXCFG, 2506 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2507 else 2508 CSR_WRITE_4(sc, RL_TXCFG, 2509 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2510 } else 2511 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2512 2513 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2514 2515 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 2516 2517 /* Set the individual bit to receive frames for this host only. */ 2518 rxcfg = CSR_READ_4(sc, RL_RXCFG); 2519 rxcfg |= RL_RXCFG_RX_INDIV; 2520 2521 /* If we want promiscuous mode, set the allframes bit. */ 2522 if (ifp->if_flags & IFF_PROMISC) 2523 rxcfg |= RL_RXCFG_RX_ALLPHYS; 2524 else 2525 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 2526 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2527 2528 /* 2529 * Set capture broadcast bit to capture broadcast frames. 2530 */ 2531 if (ifp->if_flags & IFF_BROADCAST) 2532 rxcfg |= RL_RXCFG_RX_BROAD; 2533 else 2534 rxcfg &= ~RL_RXCFG_RX_BROAD; 2535 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2536 2537 /* 2538 * Program the multicast filter, if necessary. 2539 */ 2540 re_setmulti(sc); 2541 2542 #ifdef DEVICE_POLLING 2543 /* 2544 * Disable interrupts if we are polling. 2545 */ 2546 if (ifp->if_capenable & IFCAP_POLLING) 2547 CSR_WRITE_2(sc, RL_IMR, 0); 2548 else /* otherwise ... */ 2549 #endif 2550 2551 /* 2552 * Enable interrupts. 2553 */ 2554 if (sc->rl_testmode) 2555 CSR_WRITE_2(sc, RL_IMR, 0); 2556 else 2557 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2558 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 2559 2560 /* Set initial TX threshold */ 2561 sc->rl_txthresh = RL_TX_THRESH_INIT; 2562 2563 /* Start RX/TX process. */ 2564 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2565 #ifdef notdef 2566 /* Enable receiver and transmitter. */ 2567 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2568 #endif 2569 2570 #ifdef RE_TX_MODERATION 2571 /* 2572 * Initialize the timer interrupt register so that 2573 * a timer interrupt will be generated once the timer 2574 * reaches a certain number of ticks. The timer is 2575 * reloaded on each transmit. This gives us TX interrupt 2576 * moderation, which dramatically improves TX frame rate. 2577 */ 2578 if (sc->rl_type == RL_8169) 2579 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2580 else 2581 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2582 #endif 2583 2584 /* 2585 * For 8169 gigE NICs, set the max allowed RX packet 2586 * size so we can receive jumbo frames. 2587 */ 2588 if (sc->rl_type == RL_8169) 2589 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2590 2591 if (sc->rl_testmode) 2592 return; 2593 2594 mii_mediachg(mii); 2595 2596 CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD); 2597 2598 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2599 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2600 2601 sc->rl_link = 0; 2602 sc->rl_watchdog_timer = 0; 2603 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2604 } 2605 2606 /* 2607 * Set media options. 2608 */ 2609 static int 2610 re_ifmedia_upd(ifp) 2611 struct ifnet *ifp; 2612 { 2613 struct rl_softc *sc; 2614 struct mii_data *mii; 2615 2616 sc = ifp->if_softc; 2617 mii = device_get_softc(sc->rl_miibus); 2618 RL_LOCK(sc); 2619 mii_mediachg(mii); 2620 RL_UNLOCK(sc); 2621 2622 return (0); 2623 } 2624 2625 /* 2626 * Report current media status. 2627 */ 2628 static void 2629 re_ifmedia_sts(ifp, ifmr) 2630 struct ifnet *ifp; 2631 struct ifmediareq *ifmr; 2632 { 2633 struct rl_softc *sc; 2634 struct mii_data *mii; 2635 2636 sc = ifp->if_softc; 2637 mii = device_get_softc(sc->rl_miibus); 2638 2639 RL_LOCK(sc); 2640 mii_pollstat(mii); 2641 RL_UNLOCK(sc); 2642 ifmr->ifm_active = mii->mii_media_active; 2643 ifmr->ifm_status = mii->mii_media_status; 2644 } 2645 2646 static int 2647 re_ioctl(ifp, command, data) 2648 struct ifnet *ifp; 2649 u_long command; 2650 caddr_t data; 2651 { 2652 struct rl_softc *sc = ifp->if_softc; 2653 struct ifreq *ifr = (struct ifreq *) data; 2654 struct mii_data *mii; 2655 int error = 0; 2656 2657 switch (command) { 2658 case SIOCSIFMTU: 2659 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > RL_JUMBO_MTU) { 2660 error = EINVAL; 2661 break; 2662 } 2663 if (sc->rl_type == RL_8139CPLUS && 2664 ifr->ifr_mtu > RL_MAX_FRAMELEN) { 2665 error = EINVAL; 2666 break; 2667 } 2668 RL_LOCK(sc); 2669 if (ifp->if_mtu != ifr->ifr_mtu) 2670 ifp->if_mtu = ifr->ifr_mtu; 2671 RL_UNLOCK(sc); 2672 break; 2673 case SIOCSIFFLAGS: 2674 RL_LOCK(sc); 2675 if ((ifp->if_flags & IFF_UP) != 0) { 2676 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2677 if (((ifp->if_flags ^ sc->rl_if_flags) 2678 & IFF_PROMISC) != 0) 2679 re_setmulti(sc); 2680 } else 2681 re_init_locked(sc); 2682 } else { 2683 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2684 re_stop(sc); 2685 } 2686 sc->rl_if_flags = ifp->if_flags; 2687 RL_UNLOCK(sc); 2688 break; 2689 case SIOCADDMULTI: 2690 case SIOCDELMULTI: 2691 RL_LOCK(sc); 2692 re_setmulti(sc); 2693 RL_UNLOCK(sc); 2694 break; 2695 case SIOCGIFMEDIA: 2696 case SIOCSIFMEDIA: 2697 mii = device_get_softc(sc->rl_miibus); 2698 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2699 break; 2700 case SIOCSIFCAP: 2701 { 2702 int mask, reinit; 2703 2704 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2705 reinit = 0; 2706 #ifdef DEVICE_POLLING 2707 if (mask & IFCAP_POLLING) { 2708 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2709 error = ether_poll_register(re_poll, ifp); 2710 if (error) 2711 return(error); 2712 RL_LOCK(sc); 2713 /* Disable interrupts */ 2714 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2715 ifp->if_capenable |= IFCAP_POLLING; 2716 RL_UNLOCK(sc); 2717 } else { 2718 error = ether_poll_deregister(ifp); 2719 /* Enable interrupts. */ 2720 RL_LOCK(sc); 2721 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2722 ifp->if_capenable &= ~IFCAP_POLLING; 2723 RL_UNLOCK(sc); 2724 } 2725 } 2726 #endif /* DEVICE_POLLING */ 2727 if (mask & IFCAP_HWCSUM) { 2728 ifp->if_capenable ^= IFCAP_HWCSUM; 2729 if (ifp->if_capenable & IFCAP_TXCSUM) 2730 ifp->if_hwassist |= RE_CSUM_FEATURES; 2731 else 2732 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 2733 reinit = 1; 2734 } 2735 if (mask & IFCAP_VLAN_HWTAGGING) { 2736 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2737 reinit = 1; 2738 } 2739 if (mask & IFCAP_TSO4) { 2740 ifp->if_capenable ^= IFCAP_TSO4; 2741 if ((IFCAP_TSO4 & ifp->if_capenable) && 2742 (IFCAP_TSO4 & ifp->if_capabilities)) 2743 ifp->if_hwassist |= CSUM_TSO; 2744 else 2745 ifp->if_hwassist &= ~CSUM_TSO; 2746 } 2747 if ((mask & IFCAP_WOL) != 0 && 2748 (ifp->if_capabilities & IFCAP_WOL) != 0) { 2749 if ((mask & IFCAP_WOL_UCAST) != 0) 2750 ifp->if_capenable ^= IFCAP_WOL_UCAST; 2751 if ((mask & IFCAP_WOL_MCAST) != 0) 2752 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2753 if ((mask & IFCAP_WOL_MAGIC) != 0) 2754 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2755 } 2756 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) 2757 re_init(sc); 2758 VLAN_CAPABILITIES(ifp); 2759 } 2760 break; 2761 default: 2762 error = ether_ioctl(ifp, command, data); 2763 break; 2764 } 2765 2766 return (error); 2767 } 2768 2769 static void 2770 re_watchdog(sc) 2771 struct rl_softc *sc; 2772 { 2773 2774 RL_LOCK_ASSERT(sc); 2775 2776 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 2777 return; 2778 2779 device_printf(sc->rl_dev, "watchdog timeout\n"); 2780 sc->rl_ifp->if_oerrors++; 2781 2782 re_txeof(sc); 2783 re_rxeof(sc); 2784 re_init_locked(sc); 2785 } 2786 2787 /* 2788 * Stop the adapter and free any mbufs allocated to the 2789 * RX and TX lists. 2790 */ 2791 static void 2792 re_stop(sc) 2793 struct rl_softc *sc; 2794 { 2795 register int i; 2796 struct ifnet *ifp; 2797 struct rl_txdesc *txd; 2798 struct rl_rxdesc *rxd; 2799 2800 RL_LOCK_ASSERT(sc); 2801 2802 ifp = sc->rl_ifp; 2803 2804 sc->rl_watchdog_timer = 0; 2805 callout_stop(&sc->rl_stat_callout); 2806 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2807 2808 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2809 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2810 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 2811 2812 if (sc->rl_head != NULL) { 2813 m_freem(sc->rl_head); 2814 sc->rl_head = sc->rl_tail = NULL; 2815 } 2816 2817 /* Free the TX list buffers. */ 2818 2819 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 2820 txd = &sc->rl_ldata.rl_tx_desc[i]; 2821 if (txd->tx_m != NULL) { 2822 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2823 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2824 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2825 txd->tx_dmamap); 2826 m_freem(txd->tx_m); 2827 txd->tx_m = NULL; 2828 } 2829 } 2830 2831 /* Free the RX list buffers. */ 2832 2833 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2834 rxd = &sc->rl_ldata.rl_rx_desc[i]; 2835 if (rxd->rx_m != NULL) { 2836 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2837 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2838 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 2839 rxd->rx_dmamap); 2840 m_freem(rxd->rx_m); 2841 rxd->rx_m = NULL; 2842 } 2843 } 2844 } 2845 2846 /* 2847 * Device suspend routine. Stop the interface and save some PCI 2848 * settings in case the BIOS doesn't restore them properly on 2849 * resume. 2850 */ 2851 static int 2852 re_suspend(dev) 2853 device_t dev; 2854 { 2855 struct rl_softc *sc; 2856 2857 sc = device_get_softc(dev); 2858 2859 RL_LOCK(sc); 2860 re_stop(sc); 2861 re_setwol(sc); 2862 sc->suspended = 1; 2863 RL_UNLOCK(sc); 2864 2865 return (0); 2866 } 2867 2868 /* 2869 * Device resume routine. Restore some PCI settings in case the BIOS 2870 * doesn't, re-enable busmastering, and restart the interface if 2871 * appropriate. 2872 */ 2873 static int 2874 re_resume(dev) 2875 device_t dev; 2876 { 2877 struct rl_softc *sc; 2878 struct ifnet *ifp; 2879 2880 sc = device_get_softc(dev); 2881 2882 RL_LOCK(sc); 2883 2884 ifp = sc->rl_ifp; 2885 2886 /* reinitialize interface if necessary */ 2887 if (ifp->if_flags & IFF_UP) 2888 re_init_locked(sc); 2889 2890 /* 2891 * Clear WOL matching such that normal Rx filtering 2892 * wouldn't interfere with WOL patterns. 2893 */ 2894 re_clrwol(sc); 2895 sc->suspended = 0; 2896 RL_UNLOCK(sc); 2897 2898 return (0); 2899 } 2900 2901 /* 2902 * Stop all chip I/O so that the kernel's probe routines don't 2903 * get confused by errant DMAs when rebooting. 2904 */ 2905 static int 2906 re_shutdown(dev) 2907 device_t dev; 2908 { 2909 struct rl_softc *sc; 2910 2911 sc = device_get_softc(dev); 2912 2913 RL_LOCK(sc); 2914 re_stop(sc); 2915 /* 2916 * Mark interface as down since otherwise we will panic if 2917 * interrupt comes in later on, which can happen in some 2918 * cases. 2919 */ 2920 sc->rl_ifp->if_flags &= ~IFF_UP; 2921 re_setwol(sc); 2922 RL_UNLOCK(sc); 2923 2924 return (0); 2925 } 2926 2927 static void 2928 re_setwol(sc) 2929 struct rl_softc *sc; 2930 { 2931 struct ifnet *ifp; 2932 int pmc; 2933 uint16_t pmstat; 2934 uint8_t v; 2935 2936 RL_LOCK_ASSERT(sc); 2937 2938 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 2939 return; 2940 2941 ifp = sc->rl_ifp; 2942 /* Enable config register write. */ 2943 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 2944 2945 /* Enable PME. */ 2946 v = CSR_READ_1(sc, RL_CFG1); 2947 v &= ~RL_CFG1_PME; 2948 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2949 v |= RL_CFG1_PME; 2950 CSR_WRITE_1(sc, RL_CFG1, v); 2951 2952 v = CSR_READ_1(sc, RL_CFG3); 2953 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 2954 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2955 v |= RL_CFG3_WOL_MAGIC; 2956 CSR_WRITE_1(sc, RL_CFG3, v); 2957 2958 /* Config register write done. */ 2959 CSR_WRITE_1(sc, RL_EECMD, 0); 2960 2961 v = CSR_READ_1(sc, RL_CFG5); 2962 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 2963 v &= ~RL_CFG5_WOL_LANWAKE; 2964 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 2965 v |= RL_CFG5_WOL_UCAST; 2966 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 2967 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 2968 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2969 v |= RL_CFG5_WOL_LANWAKE; 2970 CSR_WRITE_1(sc, RL_CFG5, v); 2971 2972 /* 2973 * It seems that hardware resets its link speed to 100Mbps in 2974 * power down mode so switching to 100Mbps in driver is not 2975 * needed. 2976 */ 2977 2978 /* Request PME if WOL is requested. */ 2979 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 2980 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2981 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2982 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2983 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 2984 } 2985 2986 static void 2987 re_clrwol(sc) 2988 struct rl_softc *sc; 2989 { 2990 int pmc; 2991 uint8_t v; 2992 2993 RL_LOCK_ASSERT(sc); 2994 2995 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 2996 return; 2997 2998 /* Enable config register write. */ 2999 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3000 3001 v = CSR_READ_1(sc, RL_CFG3); 3002 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3003 CSR_WRITE_1(sc, RL_CFG3, v); 3004 3005 /* Config register write done. */ 3006 CSR_WRITE_1(sc, RL_EECMD, 0); 3007 3008 v = CSR_READ_1(sc, RL_CFG5); 3009 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3010 v &= ~RL_CFG5_WOL_LANWAKE; 3011 CSR_WRITE_1(sc, RL_CFG5, v); 3012 } 3013