1 /*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44 /* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111 #ifdef HAVE_KERNEL_OPTION_HEADERS 112 #include "opt_device_polling.h" 113 #endif 114 115 #include <sys/param.h> 116 #include <sys/endian.h> 117 #include <sys/systm.h> 118 #include <sys/sockio.h> 119 #include <sys/mbuf.h> 120 #include <sys/malloc.h> 121 #include <sys/module.h> 122 #include <sys/kernel.h> 123 #include <sys/socket.h> 124 #include <sys/lock.h> 125 #include <sys/mutex.h> 126 #include <sys/sysctl.h> 127 #include <sys/taskqueue.h> 128 129 #include <net/if.h> 130 #include <net/if_arp.h> 131 #include <net/ethernet.h> 132 #include <net/if_dl.h> 133 #include <net/if_media.h> 134 #include <net/if_types.h> 135 #include <net/if_vlan_var.h> 136 137 #include <net/bpf.h> 138 139 #include <machine/bus.h> 140 #include <machine/resource.h> 141 #include <sys/bus.h> 142 #include <sys/rman.h> 143 144 #include <dev/mii/mii.h> 145 #include <dev/mii/miivar.h> 146 147 #include <dev/pci/pcireg.h> 148 #include <dev/pci/pcivar.h> 149 150 #include <pci/if_rlreg.h> 151 152 MODULE_DEPEND(re, pci, 1, 1, 1); 153 MODULE_DEPEND(re, ether, 1, 1, 1); 154 MODULE_DEPEND(re, miibus, 1, 1, 1); 155 156 /* "device miibus" required. See GENERIC if you get errors here. */ 157 #include "miibus_if.h" 158 159 /* Tunables. */ 160 static int intr_filter = 0; 161 TUNABLE_INT("hw.re.intr_filter", &intr_filter); 162 static int msi_disable = 0; 163 TUNABLE_INT("hw.re.msi_disable", &msi_disable); 164 static int msix_disable = 0; 165 TUNABLE_INT("hw.re.msix_disable", &msix_disable); 166 static int prefer_iomap = 0; 167 TUNABLE_INT("hw.re.prefer_iomap", &prefer_iomap); 168 169 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 170 171 /* 172 * Various supported device vendors/types and their names. 173 */ 174 static const struct rl_type const re_devs[] = { 175 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0, 176 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 177 { DLINK_VENDORID, DLINK_DEVICEID_530T_REVC, 0, 178 "D-Link DGE-530(T) Gigabit Ethernet Adapter" }, 179 { RT_VENDORID, RT_DEVICEID_8139, 0, 180 "RealTek 8139C+ 10/100BaseTX" }, 181 { RT_VENDORID, RT_DEVICEID_8101E, 0, 182 "RealTek 810xE PCIe 10/100baseTX" }, 183 { RT_VENDORID, RT_DEVICEID_8168, 0, 184 "RealTek 8168/8111 B/C/CP/D/DP/E/F PCIe Gigabit Ethernet" }, 185 { RT_VENDORID, RT_DEVICEID_8169, 0, 186 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" }, 187 { RT_VENDORID, RT_DEVICEID_8169SC, 0, 188 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 189 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0, 190 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 191 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0, 192 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 193 { USR_VENDORID, USR_DEVICEID_997902, 0, 194 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 195 }; 196 197 static const struct rl_hwrev const re_hwrevs[] = { 198 { RL_HWREV_8139, RL_8139, "", RL_MTU }, 199 { RL_HWREV_8139A, RL_8139, "A", RL_MTU }, 200 { RL_HWREV_8139AG, RL_8139, "A-G", RL_MTU }, 201 { RL_HWREV_8139B, RL_8139, "B", RL_MTU }, 202 { RL_HWREV_8130, RL_8139, "8130", RL_MTU }, 203 { RL_HWREV_8139C, RL_8139, "C", RL_MTU }, 204 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C", RL_MTU }, 205 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+", RL_MTU }, 206 { RL_HWREV_8168B_SPIN1, RL_8169, "8168", RL_JUMBO_MTU }, 207 { RL_HWREV_8169, RL_8169, "8169", RL_JUMBO_MTU }, 208 { RL_HWREV_8169S, RL_8169, "8169S", RL_JUMBO_MTU }, 209 { RL_HWREV_8110S, RL_8169, "8110S", RL_JUMBO_MTU }, 210 { RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB", RL_JUMBO_MTU }, 211 { RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU }, 212 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL", RL_JUMBO_MTU }, 213 { RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU }, 214 { RL_HWREV_8100, RL_8139, "8100", RL_MTU }, 215 { RL_HWREV_8101, RL_8139, "8101", RL_MTU }, 216 { RL_HWREV_8100E, RL_8169, "8100E", RL_MTU }, 217 { RL_HWREV_8101E, RL_8169, "8101E", RL_MTU }, 218 { RL_HWREV_8102E, RL_8169, "8102E", RL_MTU }, 219 { RL_HWREV_8102EL, RL_8169, "8102EL", RL_MTU }, 220 { RL_HWREV_8102EL_SPIN1, RL_8169, "8102EL", RL_MTU }, 221 { RL_HWREV_8103E, RL_8169, "8103E", RL_MTU }, 222 { RL_HWREV_8401E, RL_8169, "8401E", RL_MTU }, 223 { RL_HWREV_8402, RL_8169, "8402", RL_MTU }, 224 { RL_HWREV_8105E, RL_8169, "8105E", RL_MTU }, 225 { RL_HWREV_8105E_SPIN1, RL_8169, "8105E", RL_MTU }, 226 { RL_HWREV_8168B_SPIN2, RL_8169, "8168", RL_JUMBO_MTU }, 227 { RL_HWREV_8168B_SPIN3, RL_8169, "8168", RL_JUMBO_MTU }, 228 { RL_HWREV_8168C, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K }, 229 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K }, 230 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP", RL_JUMBO_MTU_6K }, 231 { RL_HWREV_8168D, RL_8169, "8168D/8111D", RL_JUMBO_MTU_9K }, 232 { RL_HWREV_8168DP, RL_8169, "8168DP/8111DP", RL_JUMBO_MTU_9K }, 233 { RL_HWREV_8168E, RL_8169, "8168E/8111E", RL_JUMBO_MTU_9K}, 234 { RL_HWREV_8168E_VL, RL_8169, "8168E/8111E-VL", RL_JUMBO_MTU_6K}, 235 { RL_HWREV_8168F, RL_8169, "8168F/8111F", RL_JUMBO_MTU_9K}, 236 { RL_HWREV_8411, RL_8169, "8411", RL_JUMBO_MTU_9K}, 237 { 0, 0, NULL, 0 } 238 }; 239 240 static int re_probe (device_t); 241 static int re_attach (device_t); 242 static int re_detach (device_t); 243 244 static int re_encap (struct rl_softc *, struct mbuf **); 245 246 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 247 static int re_allocmem (device_t, struct rl_softc *); 248 static __inline void re_discard_rxbuf 249 (struct rl_softc *, int); 250 static int re_newbuf (struct rl_softc *, int); 251 static int re_jumbo_newbuf (struct rl_softc *, int); 252 static int re_rx_list_init (struct rl_softc *); 253 static int re_jrx_list_init (struct rl_softc *); 254 static int re_tx_list_init (struct rl_softc *); 255 #ifdef RE_FIXUP_RX 256 static __inline void re_fixup_rx 257 (struct mbuf *); 258 #endif 259 static int re_rxeof (struct rl_softc *, int *); 260 static void re_txeof (struct rl_softc *); 261 #ifdef DEVICE_POLLING 262 static int re_poll (struct ifnet *, enum poll_cmd, int); 263 static int re_poll_locked (struct ifnet *, enum poll_cmd, int); 264 #endif 265 static int re_intr (void *); 266 static void re_intr_msi (void *); 267 static void re_tick (void *); 268 static void re_int_task (void *, int); 269 static void re_start (struct ifnet *); 270 static void re_start_locked (struct ifnet *); 271 static int re_ioctl (struct ifnet *, u_long, caddr_t); 272 static void re_init (void *); 273 static void re_init_locked (struct rl_softc *); 274 static void re_stop (struct rl_softc *); 275 static void re_watchdog (struct rl_softc *); 276 static int re_suspend (device_t); 277 static int re_resume (device_t); 278 static int re_shutdown (device_t); 279 static int re_ifmedia_upd (struct ifnet *); 280 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 281 282 static void re_eeprom_putbyte (struct rl_softc *, int); 283 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 284 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 285 static int re_gmii_readreg (device_t, int, int); 286 static int re_gmii_writereg (device_t, int, int, int); 287 288 static int re_miibus_readreg (device_t, int, int); 289 static int re_miibus_writereg (device_t, int, int, int); 290 static void re_miibus_statchg (device_t); 291 292 static void re_set_jumbo (struct rl_softc *, int); 293 static void re_set_rxmode (struct rl_softc *); 294 static void re_reset (struct rl_softc *); 295 static void re_setwol (struct rl_softc *); 296 static void re_clrwol (struct rl_softc *); 297 298 #ifdef RE_DIAG 299 static int re_diag (struct rl_softc *); 300 #endif 301 302 static void re_add_sysctls (struct rl_softc *); 303 static int re_sysctl_stats (SYSCTL_HANDLER_ARGS); 304 static int sysctl_int_range (SYSCTL_HANDLER_ARGS, int, int); 305 static int sysctl_hw_re_int_mod (SYSCTL_HANDLER_ARGS); 306 307 static device_method_t re_methods[] = { 308 /* Device interface */ 309 DEVMETHOD(device_probe, re_probe), 310 DEVMETHOD(device_attach, re_attach), 311 DEVMETHOD(device_detach, re_detach), 312 DEVMETHOD(device_suspend, re_suspend), 313 DEVMETHOD(device_resume, re_resume), 314 DEVMETHOD(device_shutdown, re_shutdown), 315 316 /* bus interface */ 317 DEVMETHOD(bus_print_child, bus_generic_print_child), 318 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 319 320 /* MII interface */ 321 DEVMETHOD(miibus_readreg, re_miibus_readreg), 322 DEVMETHOD(miibus_writereg, re_miibus_writereg), 323 DEVMETHOD(miibus_statchg, re_miibus_statchg), 324 325 { 0, 0 } 326 }; 327 328 static driver_t re_driver = { 329 "re", 330 re_methods, 331 sizeof(struct rl_softc) 332 }; 333 334 static devclass_t re_devclass; 335 336 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 337 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 338 339 #define EE_SET(x) \ 340 CSR_WRITE_1(sc, RL_EECMD, \ 341 CSR_READ_1(sc, RL_EECMD) | x) 342 343 #define EE_CLR(x) \ 344 CSR_WRITE_1(sc, RL_EECMD, \ 345 CSR_READ_1(sc, RL_EECMD) & ~x) 346 347 /* 348 * Send a read command and address to the EEPROM, check for ACK. 349 */ 350 static void 351 re_eeprom_putbyte(struct rl_softc *sc, int addr) 352 { 353 int d, i; 354 355 d = addr | (RL_9346_READ << sc->rl_eewidth); 356 357 /* 358 * Feed in each bit and strobe the clock. 359 */ 360 361 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 362 if (d & i) { 363 EE_SET(RL_EE_DATAIN); 364 } else { 365 EE_CLR(RL_EE_DATAIN); 366 } 367 DELAY(100); 368 EE_SET(RL_EE_CLK); 369 DELAY(150); 370 EE_CLR(RL_EE_CLK); 371 DELAY(100); 372 } 373 } 374 375 /* 376 * Read a word of data stored in the EEPROM at address 'addr.' 377 */ 378 static void 379 re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest) 380 { 381 int i; 382 u_int16_t word = 0; 383 384 /* 385 * Send address of word we want to read. 386 */ 387 re_eeprom_putbyte(sc, addr); 388 389 /* 390 * Start reading bits from EEPROM. 391 */ 392 for (i = 0x8000; i; i >>= 1) { 393 EE_SET(RL_EE_CLK); 394 DELAY(100); 395 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 396 word |= i; 397 EE_CLR(RL_EE_CLK); 398 DELAY(100); 399 } 400 401 *dest = word; 402 } 403 404 /* 405 * Read a sequence of words from the EEPROM. 406 */ 407 static void 408 re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt) 409 { 410 int i; 411 u_int16_t word = 0, *ptr; 412 413 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 414 415 DELAY(100); 416 417 for (i = 0; i < cnt; i++) { 418 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 419 re_eeprom_getword(sc, off + i, &word); 420 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 421 ptr = (u_int16_t *)(dest + (i * 2)); 422 *ptr = word; 423 } 424 425 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 426 } 427 428 static int 429 re_gmii_readreg(device_t dev, int phy, int reg) 430 { 431 struct rl_softc *sc; 432 u_int32_t rval; 433 int i; 434 435 sc = device_get_softc(dev); 436 437 /* Let the rgephy driver read the GMEDIASTAT register */ 438 439 if (reg == RL_GMEDIASTAT) { 440 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 441 return (rval); 442 } 443 444 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 445 446 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 447 rval = CSR_READ_4(sc, RL_PHYAR); 448 if (rval & RL_PHYAR_BUSY) 449 break; 450 DELAY(25); 451 } 452 453 if (i == RL_PHY_TIMEOUT) { 454 device_printf(sc->rl_dev, "PHY read failed\n"); 455 return (0); 456 } 457 458 /* 459 * Controller requires a 20us delay to process next MDIO request. 460 */ 461 DELAY(20); 462 463 return (rval & RL_PHYAR_PHYDATA); 464 } 465 466 static int 467 re_gmii_writereg(device_t dev, int phy, int reg, int data) 468 { 469 struct rl_softc *sc; 470 u_int32_t rval; 471 int i; 472 473 sc = device_get_softc(dev); 474 475 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 476 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 477 478 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 479 rval = CSR_READ_4(sc, RL_PHYAR); 480 if (!(rval & RL_PHYAR_BUSY)) 481 break; 482 DELAY(25); 483 } 484 485 if (i == RL_PHY_TIMEOUT) { 486 device_printf(sc->rl_dev, "PHY write failed\n"); 487 return (0); 488 } 489 490 /* 491 * Controller requires a 20us delay to process next MDIO request. 492 */ 493 DELAY(20); 494 495 return (0); 496 } 497 498 static int 499 re_miibus_readreg(device_t dev, int phy, int reg) 500 { 501 struct rl_softc *sc; 502 u_int16_t rval = 0; 503 u_int16_t re8139_reg = 0; 504 505 sc = device_get_softc(dev); 506 507 if (sc->rl_type == RL_8169) { 508 rval = re_gmii_readreg(dev, phy, reg); 509 return (rval); 510 } 511 512 switch (reg) { 513 case MII_BMCR: 514 re8139_reg = RL_BMCR; 515 break; 516 case MII_BMSR: 517 re8139_reg = RL_BMSR; 518 break; 519 case MII_ANAR: 520 re8139_reg = RL_ANAR; 521 break; 522 case MII_ANER: 523 re8139_reg = RL_ANER; 524 break; 525 case MII_ANLPAR: 526 re8139_reg = RL_LPAR; 527 break; 528 case MII_PHYIDR1: 529 case MII_PHYIDR2: 530 return (0); 531 /* 532 * Allow the rlphy driver to read the media status 533 * register. If we have a link partner which does not 534 * support NWAY, this is the register which will tell 535 * us the results of parallel detection. 536 */ 537 case RL_MEDIASTAT: 538 rval = CSR_READ_1(sc, RL_MEDIASTAT); 539 return (rval); 540 default: 541 device_printf(sc->rl_dev, "bad phy register\n"); 542 return (0); 543 } 544 rval = CSR_READ_2(sc, re8139_reg); 545 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 546 /* 8139C+ has different bit layout. */ 547 rval &= ~(BMCR_LOOP | BMCR_ISO); 548 } 549 return (rval); 550 } 551 552 static int 553 re_miibus_writereg(device_t dev, int phy, int reg, int data) 554 { 555 struct rl_softc *sc; 556 u_int16_t re8139_reg = 0; 557 int rval = 0; 558 559 sc = device_get_softc(dev); 560 561 if (sc->rl_type == RL_8169) { 562 rval = re_gmii_writereg(dev, phy, reg, data); 563 return (rval); 564 } 565 566 switch (reg) { 567 case MII_BMCR: 568 re8139_reg = RL_BMCR; 569 if (sc->rl_type == RL_8139CPLUS) { 570 /* 8139C+ has different bit layout. */ 571 data &= ~(BMCR_LOOP | BMCR_ISO); 572 } 573 break; 574 case MII_BMSR: 575 re8139_reg = RL_BMSR; 576 break; 577 case MII_ANAR: 578 re8139_reg = RL_ANAR; 579 break; 580 case MII_ANER: 581 re8139_reg = RL_ANER; 582 break; 583 case MII_ANLPAR: 584 re8139_reg = RL_LPAR; 585 break; 586 case MII_PHYIDR1: 587 case MII_PHYIDR2: 588 return (0); 589 break; 590 default: 591 device_printf(sc->rl_dev, "bad phy register\n"); 592 return (0); 593 } 594 CSR_WRITE_2(sc, re8139_reg, data); 595 return (0); 596 } 597 598 static void 599 re_miibus_statchg(device_t dev) 600 { 601 struct rl_softc *sc; 602 struct ifnet *ifp; 603 struct mii_data *mii; 604 605 sc = device_get_softc(dev); 606 mii = device_get_softc(sc->rl_miibus); 607 ifp = sc->rl_ifp; 608 if (mii == NULL || ifp == NULL || 609 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 610 return; 611 612 sc->rl_flags &= ~RL_FLAG_LINK; 613 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 614 (IFM_ACTIVE | IFM_AVALID)) { 615 switch (IFM_SUBTYPE(mii->mii_media_active)) { 616 case IFM_10_T: 617 case IFM_100_TX: 618 sc->rl_flags |= RL_FLAG_LINK; 619 break; 620 case IFM_1000_T: 621 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0) 622 break; 623 sc->rl_flags |= RL_FLAG_LINK; 624 break; 625 default: 626 break; 627 } 628 } 629 /* 630 * RealTek controllers does not provide any interface to 631 * Tx/Rx MACs for resolved speed, duplex and flow-control 632 * parameters. 633 */ 634 } 635 636 /* 637 * Set the RX configuration and 64-bit multicast hash filter. 638 */ 639 static void 640 re_set_rxmode(struct rl_softc *sc) 641 { 642 struct ifnet *ifp; 643 struct ifmultiaddr *ifma; 644 uint32_t hashes[2] = { 0, 0 }; 645 uint32_t h, rxfilt; 646 647 RL_LOCK_ASSERT(sc); 648 649 ifp = sc->rl_ifp; 650 651 rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD; 652 653 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 654 if (ifp->if_flags & IFF_PROMISC) 655 rxfilt |= RL_RXCFG_RX_ALLPHYS; 656 /* 657 * Unlike other hardwares, we have to explicitly set 658 * RL_RXCFG_RX_MULTI to receive multicast frames in 659 * promiscuous mode. 660 */ 661 rxfilt |= RL_RXCFG_RX_MULTI; 662 hashes[0] = hashes[1] = 0xffffffff; 663 goto done; 664 } 665 666 if_maddr_rlock(ifp); 667 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 668 if (ifma->ifma_addr->sa_family != AF_LINK) 669 continue; 670 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 671 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 672 if (h < 32) 673 hashes[0] |= (1 << h); 674 else 675 hashes[1] |= (1 << (h - 32)); 676 } 677 if_maddr_runlock(ifp); 678 679 if (hashes[0] != 0 || hashes[1] != 0) { 680 /* 681 * For some unfathomable reason, RealTek decided to 682 * reverse the order of the multicast hash registers 683 * in the PCI Express parts. This means we have to 684 * write the hash pattern in reverse order for those 685 * devices. 686 */ 687 if ((sc->rl_flags & RL_FLAG_PCIE) != 0) { 688 h = bswap32(hashes[0]); 689 hashes[0] = bswap32(hashes[1]); 690 hashes[1] = h; 691 } 692 rxfilt |= RL_RXCFG_RX_MULTI; 693 } 694 695 done: 696 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 697 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 698 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 699 } 700 701 static void 702 re_reset(struct rl_softc *sc) 703 { 704 int i; 705 706 RL_LOCK_ASSERT(sc); 707 708 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 709 710 for (i = 0; i < RL_TIMEOUT; i++) { 711 DELAY(10); 712 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 713 break; 714 } 715 if (i == RL_TIMEOUT) 716 device_printf(sc->rl_dev, "reset never completed!\n"); 717 718 if ((sc->rl_flags & RL_FLAG_MACRESET) != 0) 719 CSR_WRITE_1(sc, 0x82, 1); 720 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169S) 721 re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0); 722 } 723 724 #ifdef RE_DIAG 725 726 /* 727 * The following routine is designed to test for a defect on some 728 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 729 * lines connected to the bus, however for a 32-bit only card, they 730 * should be pulled high. The result of this defect is that the 731 * NIC will not work right if you plug it into a 64-bit slot: DMA 732 * operations will be done with 64-bit transfers, which will fail 733 * because the 64-bit data lines aren't connected. 734 * 735 * There's no way to work around this (short of talking a soldering 736 * iron to the board), however we can detect it. The method we use 737 * here is to put the NIC into digital loopback mode, set the receiver 738 * to promiscuous mode, and then try to send a frame. We then compare 739 * the frame data we sent to what was received. If the data matches, 740 * then the NIC is working correctly, otherwise we know the user has 741 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 742 * slot. In the latter case, there's no way the NIC can work correctly, 743 * so we print out a message on the console and abort the device attach. 744 */ 745 746 static int 747 re_diag(struct rl_softc *sc) 748 { 749 struct ifnet *ifp = sc->rl_ifp; 750 struct mbuf *m0; 751 struct ether_header *eh; 752 struct rl_desc *cur_rx; 753 u_int16_t status; 754 u_int32_t rxstat; 755 int total_len, i, error = 0, phyaddr; 756 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 757 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 758 759 /* Allocate a single mbuf */ 760 MGETHDR(m0, M_DONTWAIT, MT_DATA); 761 if (m0 == NULL) 762 return (ENOBUFS); 763 764 RL_LOCK(sc); 765 766 /* 767 * Initialize the NIC in test mode. This sets the chip up 768 * so that it can send and receive frames, but performs the 769 * following special functions: 770 * - Puts receiver in promiscuous mode 771 * - Enables digital loopback mode 772 * - Leaves interrupts turned off 773 */ 774 775 ifp->if_flags |= IFF_PROMISC; 776 sc->rl_testmode = 1; 777 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 778 re_init_locked(sc); 779 sc->rl_flags |= RL_FLAG_LINK; 780 if (sc->rl_type == RL_8169) 781 phyaddr = 1; 782 else 783 phyaddr = 0; 784 785 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 786 for (i = 0; i < RL_TIMEOUT; i++) { 787 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 788 if (!(status & BMCR_RESET)) 789 break; 790 } 791 792 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 793 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 794 795 DELAY(100000); 796 797 /* Put some data in the mbuf */ 798 799 eh = mtod(m0, struct ether_header *); 800 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 801 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 802 eh->ether_type = htons(ETHERTYPE_IP); 803 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 804 805 /* 806 * Queue the packet, start transmission. 807 * Note: IF_HANDOFF() ultimately calls re_start() for us. 808 */ 809 810 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 811 RL_UNLOCK(sc); 812 /* XXX: re_diag must not be called when in ALTQ mode */ 813 IF_HANDOFF(&ifp->if_snd, m0, ifp); 814 RL_LOCK(sc); 815 m0 = NULL; 816 817 /* Wait for it to propagate through the chip */ 818 819 DELAY(100000); 820 for (i = 0; i < RL_TIMEOUT; i++) { 821 status = CSR_READ_2(sc, RL_ISR); 822 CSR_WRITE_2(sc, RL_ISR, status); 823 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 824 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 825 break; 826 DELAY(10); 827 } 828 829 if (i == RL_TIMEOUT) { 830 device_printf(sc->rl_dev, 831 "diagnostic failed, failed to receive packet in" 832 " loopback mode\n"); 833 error = EIO; 834 goto done; 835 } 836 837 /* 838 * The packet should have been dumped into the first 839 * entry in the RX DMA ring. Grab it from there. 840 */ 841 842 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 843 sc->rl_ldata.rl_rx_list_map, 844 BUS_DMASYNC_POSTREAD); 845 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 846 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 847 BUS_DMASYNC_POSTREAD); 848 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 849 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 850 851 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 852 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 853 eh = mtod(m0, struct ether_header *); 854 855 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 856 total_len = RL_RXBYTES(cur_rx); 857 rxstat = le32toh(cur_rx->rl_cmdstat); 858 859 if (total_len != ETHER_MIN_LEN) { 860 device_printf(sc->rl_dev, 861 "diagnostic failed, received short packet\n"); 862 error = EIO; 863 goto done; 864 } 865 866 /* Test that the received packet data matches what we sent. */ 867 868 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 869 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 870 ntohs(eh->ether_type) != ETHERTYPE_IP) { 871 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 872 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 873 dst, ":", src, ":", ETHERTYPE_IP); 874 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 875 eh->ether_dhost, ":", eh->ether_shost, ":", 876 ntohs(eh->ether_type)); 877 device_printf(sc->rl_dev, "You may have a defective 32-bit " 878 "NIC plugged into a 64-bit PCI slot.\n"); 879 device_printf(sc->rl_dev, "Please re-install the NIC in a " 880 "32-bit slot for proper operation.\n"); 881 device_printf(sc->rl_dev, "Read the re(4) man page for more " 882 "details.\n"); 883 error = EIO; 884 } 885 886 done: 887 /* Turn interface off, release resources */ 888 889 sc->rl_testmode = 0; 890 sc->rl_flags &= ~RL_FLAG_LINK; 891 ifp->if_flags &= ~IFF_PROMISC; 892 re_stop(sc); 893 if (m0 != NULL) 894 m_freem(m0); 895 896 RL_UNLOCK(sc); 897 898 return (error); 899 } 900 901 #endif 902 903 /* 904 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 905 * IDs against our list and return a device name if we find a match. 906 */ 907 static int 908 re_probe(device_t dev) 909 { 910 const struct rl_type *t; 911 uint16_t devid, vendor; 912 uint16_t revid, sdevid; 913 int i; 914 915 vendor = pci_get_vendor(dev); 916 devid = pci_get_device(dev); 917 revid = pci_get_revid(dev); 918 sdevid = pci_get_subdevice(dev); 919 920 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 921 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 922 /* 923 * Only attach to rev. 3 of the Linksys EG1032 adapter. 924 * Rev. 2 is supported by sk(4). 925 */ 926 return (ENXIO); 927 } 928 } 929 930 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 931 if (revid != 0x20) { 932 /* 8139, let rl(4) take care of this device. */ 933 return (ENXIO); 934 } 935 } 936 937 t = re_devs; 938 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) { 939 if (vendor == t->rl_vid && devid == t->rl_did) { 940 device_set_desc(dev, t->rl_name); 941 return (BUS_PROBE_DEFAULT); 942 } 943 } 944 945 return (ENXIO); 946 } 947 948 /* 949 * Map a single buffer address. 950 */ 951 952 static void 953 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 954 { 955 bus_addr_t *addr; 956 957 if (error) 958 return; 959 960 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 961 addr = arg; 962 *addr = segs->ds_addr; 963 } 964 965 static int 966 re_allocmem(device_t dev, struct rl_softc *sc) 967 { 968 bus_addr_t lowaddr; 969 bus_size_t rx_list_size, tx_list_size; 970 int error; 971 int i; 972 973 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 974 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 975 976 /* 977 * Allocate the parent bus DMA tag appropriate for PCI. 978 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD 979 * register should be set. However some RealTek chips are known 980 * to be buggy on DAC handling, therefore disable DAC by limiting 981 * DMA address space to 32bit. PCIe variants of RealTek chips 982 * may not have the limitation. 983 */ 984 lowaddr = BUS_SPACE_MAXADDR; 985 if ((sc->rl_flags & RL_FLAG_PCIE) == 0) 986 lowaddr = BUS_SPACE_MAXADDR_32BIT; 987 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 988 lowaddr, BUS_SPACE_MAXADDR, NULL, NULL, 989 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 990 NULL, NULL, &sc->rl_parent_tag); 991 if (error) { 992 device_printf(dev, "could not allocate parent DMA tag\n"); 993 return (error); 994 } 995 996 /* 997 * Allocate map for TX mbufs. 998 */ 999 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 1000 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1001 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 1002 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 1003 if (error) { 1004 device_printf(dev, "could not allocate TX DMA tag\n"); 1005 return (error); 1006 } 1007 1008 /* 1009 * Allocate map for RX mbufs. 1010 */ 1011 1012 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 1013 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 1014 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1015 MJUM9BYTES, 1, MJUM9BYTES, 0, NULL, NULL, 1016 &sc->rl_ldata.rl_jrx_mtag); 1017 if (error) { 1018 device_printf(dev, 1019 "could not allocate jumbo RX DMA tag\n"); 1020 return (error); 1021 } 1022 } 1023 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 1024 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1025 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 1026 if (error) { 1027 device_printf(dev, "could not allocate RX DMA tag\n"); 1028 return (error); 1029 } 1030 1031 /* 1032 * Allocate map for TX descriptor list. 1033 */ 1034 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1035 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1036 NULL, tx_list_size, 1, tx_list_size, 0, 1037 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1038 if (error) { 1039 device_printf(dev, "could not allocate TX DMA ring tag\n"); 1040 return (error); 1041 } 1042 1043 /* Allocate DMA'able memory for the TX ring */ 1044 1045 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1046 (void **)&sc->rl_ldata.rl_tx_list, 1047 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1048 &sc->rl_ldata.rl_tx_list_map); 1049 if (error) { 1050 device_printf(dev, "could not allocate TX DMA ring\n"); 1051 return (error); 1052 } 1053 1054 /* Load the map for the TX ring. */ 1055 1056 sc->rl_ldata.rl_tx_list_addr = 0; 1057 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1058 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1059 tx_list_size, re_dma_map_addr, 1060 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1061 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 1062 device_printf(dev, "could not load TX DMA ring\n"); 1063 return (ENOMEM); 1064 } 1065 1066 /* Create DMA maps for TX buffers */ 1067 1068 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1069 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1070 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1071 if (error) { 1072 device_printf(dev, "could not create DMA map for TX\n"); 1073 return (error); 1074 } 1075 } 1076 1077 /* 1078 * Allocate map for RX descriptor list. 1079 */ 1080 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1081 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1082 NULL, rx_list_size, 1, rx_list_size, 0, 1083 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1084 if (error) { 1085 device_printf(dev, "could not create RX DMA ring tag\n"); 1086 return (error); 1087 } 1088 1089 /* Allocate DMA'able memory for the RX ring */ 1090 1091 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1092 (void **)&sc->rl_ldata.rl_rx_list, 1093 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1094 &sc->rl_ldata.rl_rx_list_map); 1095 if (error) { 1096 device_printf(dev, "could not allocate RX DMA ring\n"); 1097 return (error); 1098 } 1099 1100 /* Load the map for the RX ring. */ 1101 1102 sc->rl_ldata.rl_rx_list_addr = 0; 1103 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1104 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1105 rx_list_size, re_dma_map_addr, 1106 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1107 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1108 device_printf(dev, "could not load RX DMA ring\n"); 1109 return (ENOMEM); 1110 } 1111 1112 /* Create DMA maps for RX buffers */ 1113 1114 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 1115 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0, 1116 &sc->rl_ldata.rl_jrx_sparemap); 1117 if (error) { 1118 device_printf(dev, 1119 "could not create spare DMA map for jumbo RX\n"); 1120 return (error); 1121 } 1122 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1123 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0, 1124 &sc->rl_ldata.rl_jrx_desc[i].rx_dmamap); 1125 if (error) { 1126 device_printf(dev, 1127 "could not create DMA map for jumbo RX\n"); 1128 return (error); 1129 } 1130 } 1131 } 1132 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1133 &sc->rl_ldata.rl_rx_sparemap); 1134 if (error) { 1135 device_printf(dev, "could not create spare DMA map for RX\n"); 1136 return (error); 1137 } 1138 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1139 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1140 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1141 if (error) { 1142 device_printf(dev, "could not create DMA map for RX\n"); 1143 return (error); 1144 } 1145 } 1146 1147 /* Create DMA map for statistics. */ 1148 error = bus_dma_tag_create(sc->rl_parent_tag, RL_DUMP_ALIGN, 0, 1149 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1150 sizeof(struct rl_stats), 1, sizeof(struct rl_stats), 0, NULL, NULL, 1151 &sc->rl_ldata.rl_stag); 1152 if (error) { 1153 device_printf(dev, "could not create statistics DMA tag\n"); 1154 return (error); 1155 } 1156 /* Allocate DMA'able memory for statistics. */ 1157 error = bus_dmamem_alloc(sc->rl_ldata.rl_stag, 1158 (void **)&sc->rl_ldata.rl_stats, 1159 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1160 &sc->rl_ldata.rl_smap); 1161 if (error) { 1162 device_printf(dev, 1163 "could not allocate statistics DMA memory\n"); 1164 return (error); 1165 } 1166 /* Load the map for statistics. */ 1167 sc->rl_ldata.rl_stats_addr = 0; 1168 error = bus_dmamap_load(sc->rl_ldata.rl_stag, sc->rl_ldata.rl_smap, 1169 sc->rl_ldata.rl_stats, sizeof(struct rl_stats), re_dma_map_addr, 1170 &sc->rl_ldata.rl_stats_addr, BUS_DMA_NOWAIT); 1171 if (error != 0 || sc->rl_ldata.rl_stats_addr == 0) { 1172 device_printf(dev, "could not load statistics DMA memory\n"); 1173 return (ENOMEM); 1174 } 1175 1176 return (0); 1177 } 1178 1179 /* 1180 * Attach the interface. Allocate softc structures, do ifmedia 1181 * setup and ethernet/BPF attach. 1182 */ 1183 static int 1184 re_attach(device_t dev) 1185 { 1186 u_char eaddr[ETHER_ADDR_LEN]; 1187 u_int16_t as[ETHER_ADDR_LEN / 2]; 1188 struct rl_softc *sc; 1189 struct ifnet *ifp; 1190 const struct rl_hwrev *hw_rev; 1191 u_int32_t cap, ctl; 1192 int hwrev; 1193 u_int16_t devid, re_did = 0; 1194 int error = 0, i, phy, rid; 1195 int msic, msixc, reg; 1196 uint8_t cfg; 1197 1198 sc = device_get_softc(dev); 1199 sc->rl_dev = dev; 1200 1201 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1202 MTX_DEF); 1203 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1204 1205 /* 1206 * Map control/status registers. 1207 */ 1208 pci_enable_busmaster(dev); 1209 1210 devid = pci_get_device(dev); 1211 /* 1212 * Prefer memory space register mapping over IO space. 1213 * Because RTL8169SC does not seem to work when memory mapping 1214 * is used always activate io mapping. 1215 */ 1216 if (devid == RT_DEVICEID_8169SC) 1217 prefer_iomap = 1; 1218 if (prefer_iomap == 0) { 1219 sc->rl_res_id = PCIR_BAR(1); 1220 sc->rl_res_type = SYS_RES_MEMORY; 1221 /* RTL8168/8101E seems to use different BARs. */ 1222 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E) 1223 sc->rl_res_id = PCIR_BAR(2); 1224 } else { 1225 sc->rl_res_id = PCIR_BAR(0); 1226 sc->rl_res_type = SYS_RES_IOPORT; 1227 } 1228 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1229 &sc->rl_res_id, RF_ACTIVE); 1230 if (sc->rl_res == NULL && prefer_iomap == 0) { 1231 sc->rl_res_id = PCIR_BAR(0); 1232 sc->rl_res_type = SYS_RES_IOPORT; 1233 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1234 &sc->rl_res_id, RF_ACTIVE); 1235 } 1236 if (sc->rl_res == NULL) { 1237 device_printf(dev, "couldn't map ports/memory\n"); 1238 error = ENXIO; 1239 goto fail; 1240 } 1241 1242 sc->rl_btag = rman_get_bustag(sc->rl_res); 1243 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1244 1245 msic = pci_msi_count(dev); 1246 msixc = pci_msix_count(dev); 1247 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 1248 sc->rl_flags |= RL_FLAG_PCIE; 1249 sc->rl_expcap = reg; 1250 } 1251 if (bootverbose) { 1252 device_printf(dev, "MSI count : %d\n", msic); 1253 device_printf(dev, "MSI-X count : %d\n", msixc); 1254 } 1255 if (msix_disable > 0) 1256 msixc = 0; 1257 if (msi_disable > 0) 1258 msic = 0; 1259 /* Prefer MSI-X to MSI. */ 1260 if (msixc > 0) { 1261 msixc = 1; 1262 rid = PCIR_BAR(4); 1263 sc->rl_res_pba = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1264 &rid, RF_ACTIVE); 1265 if (sc->rl_res_pba == NULL) { 1266 device_printf(sc->rl_dev, 1267 "could not allocate MSI-X PBA resource\n"); 1268 } 1269 if (sc->rl_res_pba != NULL && 1270 pci_alloc_msix(dev, &msixc) == 0) { 1271 if (msixc == 1) { 1272 device_printf(dev, "Using %d MSI-X message\n", 1273 msixc); 1274 sc->rl_flags |= RL_FLAG_MSIX; 1275 } else 1276 pci_release_msi(dev); 1277 } 1278 if ((sc->rl_flags & RL_FLAG_MSIX) == 0) { 1279 if (sc->rl_res_pba != NULL) 1280 bus_release_resource(dev, SYS_RES_MEMORY, rid, 1281 sc->rl_res_pba); 1282 sc->rl_res_pba = NULL; 1283 msixc = 0; 1284 } 1285 } 1286 /* Prefer MSI to INTx. */ 1287 if (msixc == 0 && msic > 0) { 1288 msic = 1; 1289 if (pci_alloc_msi(dev, &msic) == 0) { 1290 if (msic == RL_MSI_MESSAGES) { 1291 device_printf(dev, "Using %d MSI message\n", 1292 msic); 1293 sc->rl_flags |= RL_FLAG_MSI; 1294 /* Explicitly set MSI enable bit. */ 1295 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1296 cfg = CSR_READ_1(sc, RL_CFG2); 1297 cfg |= RL_CFG2_MSI; 1298 CSR_WRITE_1(sc, RL_CFG2, cfg); 1299 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1300 } else 1301 pci_release_msi(dev); 1302 } 1303 if ((sc->rl_flags & RL_FLAG_MSI) == 0) 1304 msic = 0; 1305 } 1306 1307 /* Allocate interrupt */ 1308 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) { 1309 rid = 0; 1310 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1311 RF_SHAREABLE | RF_ACTIVE); 1312 if (sc->rl_irq[0] == NULL) { 1313 device_printf(dev, "couldn't allocate IRQ resources\n"); 1314 error = ENXIO; 1315 goto fail; 1316 } 1317 } else { 1318 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1319 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1320 SYS_RES_IRQ, &rid, RF_ACTIVE); 1321 if (sc->rl_irq[i] == NULL) { 1322 device_printf(dev, 1323 "couldn't llocate IRQ resources for " 1324 "message %d\n", rid); 1325 error = ENXIO; 1326 goto fail; 1327 } 1328 } 1329 } 1330 1331 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1332 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1333 cfg = CSR_READ_1(sc, RL_CFG2); 1334 if ((cfg & RL_CFG2_MSI) != 0) { 1335 device_printf(dev, "turning off MSI enable bit.\n"); 1336 cfg &= ~RL_CFG2_MSI; 1337 CSR_WRITE_1(sc, RL_CFG2, cfg); 1338 } 1339 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1340 } 1341 1342 /* Disable ASPM L0S/L1. */ 1343 if (sc->rl_expcap != 0) { 1344 cap = pci_read_config(dev, sc->rl_expcap + 1345 PCIR_EXPRESS_LINK_CAP, 2); 1346 if ((cap & PCIM_LINK_CAP_ASPM) != 0) { 1347 ctl = pci_read_config(dev, sc->rl_expcap + 1348 PCIR_EXPRESS_LINK_CTL, 2); 1349 if ((ctl & 0x0003) != 0) { 1350 ctl &= ~0x0003; 1351 pci_write_config(dev, sc->rl_expcap + 1352 PCIR_EXPRESS_LINK_CTL, ctl, 2); 1353 device_printf(dev, "ASPM disabled\n"); 1354 } 1355 } else 1356 device_printf(dev, "no ASPM capability\n"); 1357 } 1358 1359 hw_rev = re_hwrevs; 1360 hwrev = CSR_READ_4(sc, RL_TXCFG); 1361 switch (hwrev & 0x70000000) { 1362 case 0x00000000: 1363 case 0x10000000: 1364 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000); 1365 hwrev &= (RL_TXCFG_HWREV | 0x80000000); 1366 break; 1367 default: 1368 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000); 1369 hwrev &= RL_TXCFG_HWREV; 1370 break; 1371 } 1372 device_printf(dev, "MAC rev. 0x%08x\n", hwrev & 0x00700000); 1373 while (hw_rev->rl_desc != NULL) { 1374 if (hw_rev->rl_rev == hwrev) { 1375 sc->rl_type = hw_rev->rl_type; 1376 sc->rl_hwrev = hw_rev; 1377 break; 1378 } 1379 hw_rev++; 1380 } 1381 if (hw_rev->rl_desc == NULL) { 1382 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev); 1383 error = ENXIO; 1384 goto fail; 1385 } 1386 1387 switch (hw_rev->rl_rev) { 1388 case RL_HWREV_8139CPLUS: 1389 sc->rl_flags |= RL_FLAG_FASTETHER | RL_FLAG_AUTOPAD; 1390 break; 1391 case RL_HWREV_8100E: 1392 case RL_HWREV_8101E: 1393 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_FASTETHER; 1394 break; 1395 case RL_HWREV_8102E: 1396 case RL_HWREV_8102EL: 1397 case RL_HWREV_8102EL_SPIN1: 1398 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1399 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | 1400 RL_FLAG_AUTOPAD; 1401 break; 1402 case RL_HWREV_8103E: 1403 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1404 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | 1405 RL_FLAG_AUTOPAD | RL_FLAG_MACSLEEP; 1406 break; 1407 case RL_HWREV_8401E: 1408 case RL_HWREV_8402: 1409 case RL_HWREV_8105E: 1410 case RL_HWREV_8105E_SPIN1: 1411 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1412 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1413 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD; 1414 break; 1415 case RL_HWREV_8168B_SPIN1: 1416 case RL_HWREV_8168B_SPIN2: 1417 sc->rl_flags |= RL_FLAG_WOLRXENB; 1418 /* FALLTHROUGH */ 1419 case RL_HWREV_8168B_SPIN3: 1420 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT; 1421 break; 1422 case RL_HWREV_8168C_SPIN2: 1423 sc->rl_flags |= RL_FLAG_MACSLEEP; 1424 /* FALLTHROUGH */ 1425 case RL_HWREV_8168C: 1426 if ((hwrev & 0x00700000) == 0x00200000) 1427 sc->rl_flags |= RL_FLAG_MACSLEEP; 1428 /* FALLTHROUGH */ 1429 case RL_HWREV_8168CP: 1430 case RL_HWREV_8168D: 1431 case RL_HWREV_8168DP: 1432 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1433 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1434 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2; 1435 break; 1436 case RL_HWREV_8168E: 1437 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1438 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1439 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2; 1440 break; 1441 case RL_HWREV_8168E_VL: 1442 case RL_HWREV_8168F: 1443 case RL_HWREV_8411: 1444 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1445 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1446 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2; 1447 break; 1448 case RL_HWREV_8169_8110SB: 1449 case RL_HWREV_8169_8110SBL: 1450 case RL_HWREV_8169_8110SC: 1451 case RL_HWREV_8169_8110SCE: 1452 sc->rl_flags |= RL_FLAG_PHYWAKE; 1453 /* FALLTHROUGH */ 1454 case RL_HWREV_8169: 1455 case RL_HWREV_8169S: 1456 case RL_HWREV_8110S: 1457 sc->rl_flags |= RL_FLAG_MACRESET; 1458 break; 1459 default: 1460 break; 1461 } 1462 1463 /* Reset the adapter. */ 1464 RL_LOCK(sc); 1465 re_reset(sc); 1466 RL_UNLOCK(sc); 1467 1468 /* Enable PME. */ 1469 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1470 cfg = CSR_READ_1(sc, RL_CFG1); 1471 cfg |= RL_CFG1_PME; 1472 CSR_WRITE_1(sc, RL_CFG1, cfg); 1473 cfg = CSR_READ_1(sc, RL_CFG5); 1474 cfg &= RL_CFG5_PME_STS; 1475 CSR_WRITE_1(sc, RL_CFG5, cfg); 1476 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1477 1478 if ((sc->rl_flags & RL_FLAG_PAR) != 0) { 1479 /* 1480 * XXX Should have a better way to extract station 1481 * address from EEPROM. 1482 */ 1483 for (i = 0; i < ETHER_ADDR_LEN; i++) 1484 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1485 } else { 1486 sc->rl_eewidth = RL_9356_ADDR_LEN; 1487 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1488 if (re_did != 0x8129) 1489 sc->rl_eewidth = RL_9346_ADDR_LEN; 1490 1491 /* 1492 * Get station address from the EEPROM. 1493 */ 1494 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1495 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1496 as[i] = le16toh(as[i]); 1497 bcopy(as, eaddr, sizeof(eaddr)); 1498 } 1499 1500 if (sc->rl_type == RL_8169) { 1501 /* Set RX length mask and number of descriptors. */ 1502 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1503 sc->rl_txstart = RL_GTXSTART; 1504 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1505 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1506 } else { 1507 /* Set RX length mask and number of descriptors. */ 1508 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1509 sc->rl_txstart = RL_TXSTART; 1510 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1511 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1512 } 1513 1514 error = re_allocmem(dev, sc); 1515 if (error) 1516 goto fail; 1517 re_add_sysctls(sc); 1518 1519 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1520 if (ifp == NULL) { 1521 device_printf(dev, "can not if_alloc()\n"); 1522 error = ENOSPC; 1523 goto fail; 1524 } 1525 1526 /* Take controller out of deep sleep mode. */ 1527 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 1528 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 1529 CSR_WRITE_1(sc, RL_GPIO, 1530 CSR_READ_1(sc, RL_GPIO) | 0x01); 1531 else 1532 CSR_WRITE_1(sc, RL_GPIO, 1533 CSR_READ_1(sc, RL_GPIO) & ~0x01); 1534 } 1535 1536 /* Take PHY out of power down mode. */ 1537 if ((sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) { 1538 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80); 1539 if (hw_rev->rl_rev == RL_HWREV_8401E) 1540 CSR_WRITE_1(sc, 0xD1, CSR_READ_1(sc, 0xD1) & ~0x08); 1541 } 1542 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) { 1543 re_gmii_writereg(dev, 1, 0x1f, 0); 1544 re_gmii_writereg(dev, 1, 0x0e, 0); 1545 } 1546 1547 #define RE_PHYAD_INTERNAL 0 1548 1549 /* Do MII setup. */ 1550 phy = RE_PHYAD_INTERNAL; 1551 if (sc->rl_type == RL_8169) 1552 phy = 1; 1553 error = mii_attach(dev, &sc->rl_miibus, ifp, re_ifmedia_upd, 1554 re_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, MIIF_DOPAUSE); 1555 if (error != 0) { 1556 device_printf(dev, "attaching PHYs failed\n"); 1557 goto fail; 1558 } 1559 1560 ifp->if_softc = sc; 1561 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1562 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1563 ifp->if_ioctl = re_ioctl; 1564 ifp->if_start = re_start; 1565 /* 1566 * RTL8168/8111C generates wrong IP checksummed frame if the 1567 * packet has IP options so disable TX IP checksum offloading. 1568 */ 1569 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168C || 1570 sc->rl_hwrev->rl_rev == RL_HWREV_8168C_SPIN2) 1571 ifp->if_hwassist = CSUM_TCP | CSUM_UDP; 1572 else 1573 ifp->if_hwassist = CSUM_IP | CSUM_TCP | CSUM_UDP; 1574 ifp->if_hwassist |= CSUM_TSO; 1575 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 1576 ifp->if_capenable = ifp->if_capabilities; 1577 ifp->if_init = re_init; 1578 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1579 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1580 IFQ_SET_READY(&ifp->if_snd); 1581 1582 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1583 1584 /* 1585 * Call MI attach routine. 1586 */ 1587 ether_ifattach(ifp, eaddr); 1588 1589 /* VLAN capability setup */ 1590 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1591 if (ifp->if_capabilities & IFCAP_HWCSUM) 1592 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1593 /* Enable WOL if PM is supported. */ 1594 if (pci_find_cap(sc->rl_dev, PCIY_PMG, ®) == 0) 1595 ifp->if_capabilities |= IFCAP_WOL; 1596 ifp->if_capenable = ifp->if_capabilities; 1597 /* 1598 * Don't enable TSO by default. It is known to generate 1599 * corrupted TCP segments(bad TCP options) under certain 1600 * circumtances. 1601 */ 1602 ifp->if_hwassist &= ~CSUM_TSO; 1603 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO); 1604 #ifdef DEVICE_POLLING 1605 ifp->if_capabilities |= IFCAP_POLLING; 1606 #endif 1607 /* 1608 * Tell the upper layer(s) we support long frames. 1609 * Must appear after the call to ether_ifattach() because 1610 * ether_ifattach() sets ifi_hdrlen to the default value. 1611 */ 1612 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1613 1614 #ifdef RE_DIAG 1615 /* 1616 * Perform hardware diagnostic on the original RTL8169. 1617 * Some 32-bit cards were incorrectly wired and would 1618 * malfunction if plugged into a 64-bit slot. 1619 */ 1620 1621 if (hwrev == RL_HWREV_8169) { 1622 error = re_diag(sc); 1623 if (error) { 1624 device_printf(dev, 1625 "attach aborted due to hardware diag failure\n"); 1626 ether_ifdetach(ifp); 1627 goto fail; 1628 } 1629 } 1630 #endif 1631 1632 #ifdef RE_TX_MODERATION 1633 intr_filter = 1; 1634 #endif 1635 /* Hook interrupt last to avoid having to lock softc */ 1636 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 && 1637 intr_filter == 0) { 1638 error = bus_setup_intr(dev, sc->rl_irq[0], 1639 INTR_TYPE_NET | INTR_MPSAFE, NULL, re_intr_msi, sc, 1640 &sc->rl_intrhand[0]); 1641 } else { 1642 error = bus_setup_intr(dev, sc->rl_irq[0], 1643 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1644 &sc->rl_intrhand[0]); 1645 } 1646 if (error) { 1647 device_printf(dev, "couldn't set up irq\n"); 1648 ether_ifdetach(ifp); 1649 } 1650 1651 fail: 1652 1653 if (error) 1654 re_detach(dev); 1655 1656 return (error); 1657 } 1658 1659 /* 1660 * Shutdown hardware and free up resources. This can be called any 1661 * time after the mutex has been initialized. It is called in both 1662 * the error case in attach and the normal detach case so it needs 1663 * to be careful about only freeing resources that have actually been 1664 * allocated. 1665 */ 1666 static int 1667 re_detach(device_t dev) 1668 { 1669 struct rl_softc *sc; 1670 struct ifnet *ifp; 1671 int i, rid; 1672 1673 sc = device_get_softc(dev); 1674 ifp = sc->rl_ifp; 1675 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1676 1677 /* These should only be active if attach succeeded */ 1678 if (device_is_attached(dev)) { 1679 #ifdef DEVICE_POLLING 1680 if (ifp->if_capenable & IFCAP_POLLING) 1681 ether_poll_deregister(ifp); 1682 #endif 1683 RL_LOCK(sc); 1684 #if 0 1685 sc->suspended = 1; 1686 #endif 1687 re_stop(sc); 1688 RL_UNLOCK(sc); 1689 callout_drain(&sc->rl_stat_callout); 1690 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1691 /* 1692 * Force off the IFF_UP flag here, in case someone 1693 * still had a BPF descriptor attached to this 1694 * interface. If they do, ether_ifdetach() will cause 1695 * the BPF code to try and clear the promisc mode 1696 * flag, which will bubble down to re_ioctl(), 1697 * which will try to call re_init() again. This will 1698 * turn the NIC back on and restart the MII ticker, 1699 * which will panic the system when the kernel tries 1700 * to invoke the re_tick() function that isn't there 1701 * anymore. 1702 */ 1703 ifp->if_flags &= ~IFF_UP; 1704 ether_ifdetach(ifp); 1705 } 1706 if (sc->rl_miibus) 1707 device_delete_child(dev, sc->rl_miibus); 1708 bus_generic_detach(dev); 1709 1710 /* 1711 * The rest is resource deallocation, so we should already be 1712 * stopped here. 1713 */ 1714 1715 if (sc->rl_intrhand[0] != NULL) { 1716 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]); 1717 sc->rl_intrhand[0] = NULL; 1718 } 1719 if (ifp != NULL) 1720 if_free(ifp); 1721 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) 1722 rid = 0; 1723 else 1724 rid = 1; 1725 if (sc->rl_irq[0] != NULL) { 1726 bus_release_resource(dev, SYS_RES_IRQ, rid, sc->rl_irq[0]); 1727 sc->rl_irq[0] = NULL; 1728 } 1729 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0) 1730 pci_release_msi(dev); 1731 if (sc->rl_res_pba) { 1732 rid = PCIR_BAR(4); 1733 bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->rl_res_pba); 1734 } 1735 if (sc->rl_res) 1736 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, 1737 sc->rl_res); 1738 1739 /* Unload and free the RX DMA ring memory and map */ 1740 1741 if (sc->rl_ldata.rl_rx_list_tag) { 1742 if (sc->rl_ldata.rl_rx_list_map) 1743 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1744 sc->rl_ldata.rl_rx_list_map); 1745 if (sc->rl_ldata.rl_rx_list_map && sc->rl_ldata.rl_rx_list) 1746 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1747 sc->rl_ldata.rl_rx_list, 1748 sc->rl_ldata.rl_rx_list_map); 1749 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1750 } 1751 1752 /* Unload and free the TX DMA ring memory and map */ 1753 1754 if (sc->rl_ldata.rl_tx_list_tag) { 1755 if (sc->rl_ldata.rl_tx_list_map) 1756 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1757 sc->rl_ldata.rl_tx_list_map); 1758 if (sc->rl_ldata.rl_tx_list_map && sc->rl_ldata.rl_tx_list) 1759 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1760 sc->rl_ldata.rl_tx_list, 1761 sc->rl_ldata.rl_tx_list_map); 1762 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1763 } 1764 1765 /* Destroy all the RX and TX buffer maps */ 1766 1767 if (sc->rl_ldata.rl_tx_mtag) { 1768 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1769 if (sc->rl_ldata.rl_tx_desc[i].tx_dmamap) 1770 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1771 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1772 } 1773 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1774 } 1775 if (sc->rl_ldata.rl_rx_mtag) { 1776 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1777 if (sc->rl_ldata.rl_rx_desc[i].rx_dmamap) 1778 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1779 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1780 } 1781 if (sc->rl_ldata.rl_rx_sparemap) 1782 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1783 sc->rl_ldata.rl_rx_sparemap); 1784 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1785 } 1786 if (sc->rl_ldata.rl_jrx_mtag) { 1787 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1788 if (sc->rl_ldata.rl_jrx_desc[i].rx_dmamap) 1789 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag, 1790 sc->rl_ldata.rl_jrx_desc[i].rx_dmamap); 1791 } 1792 if (sc->rl_ldata.rl_jrx_sparemap) 1793 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag, 1794 sc->rl_ldata.rl_jrx_sparemap); 1795 bus_dma_tag_destroy(sc->rl_ldata.rl_jrx_mtag); 1796 } 1797 /* Unload and free the stats buffer and map */ 1798 1799 if (sc->rl_ldata.rl_stag) { 1800 if (sc->rl_ldata.rl_smap) 1801 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1802 sc->rl_ldata.rl_smap); 1803 if (sc->rl_ldata.rl_smap && sc->rl_ldata.rl_stats) 1804 bus_dmamem_free(sc->rl_ldata.rl_stag, 1805 sc->rl_ldata.rl_stats, sc->rl_ldata.rl_smap); 1806 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1807 } 1808 1809 if (sc->rl_parent_tag) 1810 bus_dma_tag_destroy(sc->rl_parent_tag); 1811 1812 mtx_destroy(&sc->rl_mtx); 1813 1814 return (0); 1815 } 1816 1817 static __inline void 1818 re_discard_rxbuf(struct rl_softc *sc, int idx) 1819 { 1820 struct rl_desc *desc; 1821 struct rl_rxdesc *rxd; 1822 uint32_t cmdstat; 1823 1824 if (sc->rl_ifp->if_mtu > RL_MTU && 1825 (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) 1826 rxd = &sc->rl_ldata.rl_jrx_desc[idx]; 1827 else 1828 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1829 desc = &sc->rl_ldata.rl_rx_list[idx]; 1830 desc->rl_vlanctl = 0; 1831 cmdstat = rxd->rx_size; 1832 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1833 cmdstat |= RL_RDESC_CMD_EOR; 1834 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1835 } 1836 1837 static int 1838 re_newbuf(struct rl_softc *sc, int idx) 1839 { 1840 struct mbuf *m; 1841 struct rl_rxdesc *rxd; 1842 bus_dma_segment_t segs[1]; 1843 bus_dmamap_t map; 1844 struct rl_desc *desc; 1845 uint32_t cmdstat; 1846 int error, nsegs; 1847 1848 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1849 if (m == NULL) 1850 return (ENOBUFS); 1851 1852 m->m_len = m->m_pkthdr.len = MCLBYTES; 1853 #ifdef RE_FIXUP_RX 1854 /* 1855 * This is part of an evil trick to deal with non-x86 platforms. 1856 * The RealTek chip requires RX buffers to be aligned on 64-bit 1857 * boundaries, but that will hose non-x86 machines. To get around 1858 * this, we leave some empty space at the start of each buffer 1859 * and for non-x86 hosts, we copy the buffer back six bytes 1860 * to achieve word alignment. This is slightly more efficient 1861 * than allocating a new buffer, copying the contents, and 1862 * discarding the old buffer. 1863 */ 1864 m_adj(m, RE_ETHER_ALIGN); 1865 #endif 1866 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1867 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1868 if (error != 0) { 1869 m_freem(m); 1870 return (ENOBUFS); 1871 } 1872 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1873 1874 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1875 if (rxd->rx_m != NULL) { 1876 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1877 BUS_DMASYNC_POSTREAD); 1878 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1879 } 1880 1881 rxd->rx_m = m; 1882 map = rxd->rx_dmamap; 1883 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1884 rxd->rx_size = segs[0].ds_len; 1885 sc->rl_ldata.rl_rx_sparemap = map; 1886 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1887 BUS_DMASYNC_PREREAD); 1888 1889 desc = &sc->rl_ldata.rl_rx_list[idx]; 1890 desc->rl_vlanctl = 0; 1891 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1892 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1893 cmdstat = segs[0].ds_len; 1894 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1895 cmdstat |= RL_RDESC_CMD_EOR; 1896 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1897 1898 return (0); 1899 } 1900 1901 static int 1902 re_jumbo_newbuf(struct rl_softc *sc, int idx) 1903 { 1904 struct mbuf *m; 1905 struct rl_rxdesc *rxd; 1906 bus_dma_segment_t segs[1]; 1907 bus_dmamap_t map; 1908 struct rl_desc *desc; 1909 uint32_t cmdstat; 1910 int error, nsegs; 1911 1912 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 1913 if (m == NULL) 1914 return (ENOBUFS); 1915 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1916 #ifdef RE_FIXUP_RX 1917 m_adj(m, RE_ETHER_ALIGN); 1918 #endif 1919 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_jrx_mtag, 1920 sc->rl_ldata.rl_jrx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1921 if (error != 0) { 1922 m_freem(m); 1923 return (ENOBUFS); 1924 } 1925 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1926 1927 rxd = &sc->rl_ldata.rl_jrx_desc[idx]; 1928 if (rxd->rx_m != NULL) { 1929 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap, 1930 BUS_DMASYNC_POSTREAD); 1931 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap); 1932 } 1933 1934 rxd->rx_m = m; 1935 map = rxd->rx_dmamap; 1936 rxd->rx_dmamap = sc->rl_ldata.rl_jrx_sparemap; 1937 rxd->rx_size = segs[0].ds_len; 1938 sc->rl_ldata.rl_jrx_sparemap = map; 1939 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap, 1940 BUS_DMASYNC_PREREAD); 1941 1942 desc = &sc->rl_ldata.rl_rx_list[idx]; 1943 desc->rl_vlanctl = 0; 1944 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1945 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1946 cmdstat = segs[0].ds_len; 1947 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1948 cmdstat |= RL_RDESC_CMD_EOR; 1949 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1950 1951 return (0); 1952 } 1953 1954 #ifdef RE_FIXUP_RX 1955 static __inline void 1956 re_fixup_rx(struct mbuf *m) 1957 { 1958 int i; 1959 uint16_t *src, *dst; 1960 1961 src = mtod(m, uint16_t *); 1962 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1963 1964 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1965 *dst++ = *src++; 1966 1967 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1968 } 1969 #endif 1970 1971 static int 1972 re_tx_list_init(struct rl_softc *sc) 1973 { 1974 struct rl_desc *desc; 1975 int i; 1976 1977 RL_LOCK_ASSERT(sc); 1978 1979 bzero(sc->rl_ldata.rl_tx_list, 1980 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 1981 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1982 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 1983 /* Set EOR. */ 1984 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 1985 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 1986 1987 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1988 sc->rl_ldata.rl_tx_list_map, 1989 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1990 1991 sc->rl_ldata.rl_tx_prodidx = 0; 1992 sc->rl_ldata.rl_tx_considx = 0; 1993 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 1994 1995 return (0); 1996 } 1997 1998 static int 1999 re_rx_list_init(struct rl_softc *sc) 2000 { 2001 int error, i; 2002 2003 bzero(sc->rl_ldata.rl_rx_list, 2004 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 2005 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2006 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 2007 if ((error = re_newbuf(sc, i)) != 0) 2008 return (error); 2009 } 2010 2011 /* Flush the RX descriptors */ 2012 2013 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2014 sc->rl_ldata.rl_rx_list_map, 2015 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2016 2017 sc->rl_ldata.rl_rx_prodidx = 0; 2018 sc->rl_head = sc->rl_tail = NULL; 2019 sc->rl_int_rx_act = 0; 2020 2021 return (0); 2022 } 2023 2024 static int 2025 re_jrx_list_init(struct rl_softc *sc) 2026 { 2027 int error, i; 2028 2029 bzero(sc->rl_ldata.rl_rx_list, 2030 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 2031 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2032 sc->rl_ldata.rl_jrx_desc[i].rx_m = NULL; 2033 if ((error = re_jumbo_newbuf(sc, i)) != 0) 2034 return (error); 2035 } 2036 2037 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2038 sc->rl_ldata.rl_rx_list_map, 2039 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2040 2041 sc->rl_ldata.rl_rx_prodidx = 0; 2042 sc->rl_head = sc->rl_tail = NULL; 2043 sc->rl_int_rx_act = 0; 2044 2045 return (0); 2046 } 2047 2048 /* 2049 * RX handler for C+ and 8169. For the gigE chips, we support 2050 * the reception of jumbo frames that have been fragmented 2051 * across multiple 2K mbuf cluster buffers. 2052 */ 2053 static int 2054 re_rxeof(struct rl_softc *sc, int *rx_npktsp) 2055 { 2056 struct mbuf *m; 2057 struct ifnet *ifp; 2058 int i, rxerr, total_len; 2059 struct rl_desc *cur_rx; 2060 u_int32_t rxstat, rxvlan; 2061 int jumbo, maxpkt = 16, rx_npkts = 0; 2062 2063 RL_LOCK_ASSERT(sc); 2064 2065 ifp = sc->rl_ifp; 2066 if (ifp->if_mtu > RL_MTU && (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) 2067 jumbo = 1; 2068 else 2069 jumbo = 0; 2070 2071 /* Invalidate the descriptor memory */ 2072 2073 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2074 sc->rl_ldata.rl_rx_list_map, 2075 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2076 2077 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 2078 i = RL_RX_DESC_NXT(sc, i)) { 2079 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2080 break; 2081 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 2082 rxstat = le32toh(cur_rx->rl_cmdstat); 2083 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 2084 break; 2085 total_len = rxstat & sc->rl_rxlenmask; 2086 rxvlan = le32toh(cur_rx->rl_vlanctl); 2087 if (jumbo != 0) 2088 m = sc->rl_ldata.rl_jrx_desc[i].rx_m; 2089 else 2090 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 2091 2092 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 2093 (rxstat & (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) != 2094 (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) { 2095 /* 2096 * RTL8168C or later controllers do not 2097 * support multi-fragment packet. 2098 */ 2099 re_discard_rxbuf(sc, i); 2100 continue; 2101 } else if ((rxstat & RL_RDESC_STAT_EOF) == 0) { 2102 if (re_newbuf(sc, i) != 0) { 2103 /* 2104 * If this is part of a multi-fragment packet, 2105 * discard all the pieces. 2106 */ 2107 if (sc->rl_head != NULL) { 2108 m_freem(sc->rl_head); 2109 sc->rl_head = sc->rl_tail = NULL; 2110 } 2111 re_discard_rxbuf(sc, i); 2112 continue; 2113 } 2114 m->m_len = RE_RX_DESC_BUFLEN; 2115 if (sc->rl_head == NULL) 2116 sc->rl_head = sc->rl_tail = m; 2117 else { 2118 m->m_flags &= ~M_PKTHDR; 2119 sc->rl_tail->m_next = m; 2120 sc->rl_tail = m; 2121 } 2122 continue; 2123 } 2124 2125 /* 2126 * NOTE: for the 8139C+, the frame length field 2127 * is always 12 bits in size, but for the gigE chips, 2128 * it is 13 bits (since the max RX frame length is 16K). 2129 * Unfortunately, all 32 bits in the status word 2130 * were already used, so to make room for the extra 2131 * length bit, RealTek took out the 'frame alignment 2132 * error' bit and shifted the other status bits 2133 * over one slot. The OWN, EOR, FS and LS bits are 2134 * still in the same places. We have already extracted 2135 * the frame length and checked the OWN bit, so rather 2136 * than using an alternate bit mapping, we shift the 2137 * status bits one space to the right so we can evaluate 2138 * them using the 8169 status as though it was in the 2139 * same format as that of the 8139C+. 2140 */ 2141 if (sc->rl_type == RL_8169) 2142 rxstat >>= 1; 2143 2144 /* 2145 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 2146 * set, but if CRC is clear, it will still be a valid frame. 2147 */ 2148 if ((rxstat & RL_RDESC_STAT_RXERRSUM) != 0) { 2149 rxerr = 1; 2150 if ((sc->rl_flags & RL_FLAG_JUMBOV2) == 0 && 2151 total_len > 8191 && 2152 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT) 2153 rxerr = 0; 2154 if (rxerr != 0) { 2155 ifp->if_ierrors++; 2156 /* 2157 * If this is part of a multi-fragment packet, 2158 * discard all the pieces. 2159 */ 2160 if (sc->rl_head != NULL) { 2161 m_freem(sc->rl_head); 2162 sc->rl_head = sc->rl_tail = NULL; 2163 } 2164 re_discard_rxbuf(sc, i); 2165 continue; 2166 } 2167 } 2168 2169 /* 2170 * If allocating a replacement mbuf fails, 2171 * reload the current one. 2172 */ 2173 if (jumbo != 0) 2174 rxerr = re_jumbo_newbuf(sc, i); 2175 else 2176 rxerr = re_newbuf(sc, i); 2177 if (rxerr != 0) { 2178 ifp->if_iqdrops++; 2179 if (sc->rl_head != NULL) { 2180 m_freem(sc->rl_head); 2181 sc->rl_head = sc->rl_tail = NULL; 2182 } 2183 re_discard_rxbuf(sc, i); 2184 continue; 2185 } 2186 2187 if (sc->rl_head != NULL) { 2188 if (jumbo != 0) 2189 m->m_len = total_len; 2190 else { 2191 m->m_len = total_len % RE_RX_DESC_BUFLEN; 2192 if (m->m_len == 0) 2193 m->m_len = RE_RX_DESC_BUFLEN; 2194 } 2195 /* 2196 * Special case: if there's 4 bytes or less 2197 * in this buffer, the mbuf can be discarded: 2198 * the last 4 bytes is the CRC, which we don't 2199 * care about anyway. 2200 */ 2201 if (m->m_len <= ETHER_CRC_LEN) { 2202 sc->rl_tail->m_len -= 2203 (ETHER_CRC_LEN - m->m_len); 2204 m_freem(m); 2205 } else { 2206 m->m_len -= ETHER_CRC_LEN; 2207 m->m_flags &= ~M_PKTHDR; 2208 sc->rl_tail->m_next = m; 2209 } 2210 m = sc->rl_head; 2211 sc->rl_head = sc->rl_tail = NULL; 2212 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 2213 } else 2214 m->m_pkthdr.len = m->m_len = 2215 (total_len - ETHER_CRC_LEN); 2216 2217 #ifdef RE_FIXUP_RX 2218 re_fixup_rx(m); 2219 #endif 2220 ifp->if_ipackets++; 2221 m->m_pkthdr.rcvif = ifp; 2222 2223 /* Do RX checksumming if enabled */ 2224 2225 if (ifp->if_capenable & IFCAP_RXCSUM) { 2226 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2227 /* Check IP header checksum */ 2228 if (rxstat & RL_RDESC_STAT_PROTOID) 2229 m->m_pkthdr.csum_flags |= 2230 CSUM_IP_CHECKED; 2231 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 2232 m->m_pkthdr.csum_flags |= 2233 CSUM_IP_VALID; 2234 2235 /* Check TCP/UDP checksum */ 2236 if ((RL_TCPPKT(rxstat) && 2237 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 2238 (RL_UDPPKT(rxstat) && 2239 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 2240 m->m_pkthdr.csum_flags |= 2241 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2242 m->m_pkthdr.csum_data = 0xffff; 2243 } 2244 } else { 2245 /* 2246 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP 2247 */ 2248 if ((rxstat & RL_RDESC_STAT_PROTOID) && 2249 (rxvlan & RL_RDESC_IPV4)) 2250 m->m_pkthdr.csum_flags |= 2251 CSUM_IP_CHECKED; 2252 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) && 2253 (rxvlan & RL_RDESC_IPV4)) 2254 m->m_pkthdr.csum_flags |= 2255 CSUM_IP_VALID; 2256 if (((rxstat & RL_RDESC_STAT_TCP) && 2257 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 2258 ((rxstat & RL_RDESC_STAT_UDP) && 2259 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 2260 m->m_pkthdr.csum_flags |= 2261 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2262 m->m_pkthdr.csum_data = 0xffff; 2263 } 2264 } 2265 } 2266 maxpkt--; 2267 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 2268 m->m_pkthdr.ether_vtag = 2269 bswap16((rxvlan & RL_RDESC_VLANCTL_DATA)); 2270 m->m_flags |= M_VLANTAG; 2271 } 2272 RL_UNLOCK(sc); 2273 (*ifp->if_input)(ifp, m); 2274 RL_LOCK(sc); 2275 rx_npkts++; 2276 } 2277 2278 /* Flush the RX DMA ring */ 2279 2280 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2281 sc->rl_ldata.rl_rx_list_map, 2282 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2283 2284 sc->rl_ldata.rl_rx_prodidx = i; 2285 2286 if (rx_npktsp != NULL) 2287 *rx_npktsp = rx_npkts; 2288 if (maxpkt) 2289 return (EAGAIN); 2290 2291 return (0); 2292 } 2293 2294 static void 2295 re_txeof(struct rl_softc *sc) 2296 { 2297 struct ifnet *ifp; 2298 struct rl_txdesc *txd; 2299 u_int32_t txstat; 2300 int cons; 2301 2302 cons = sc->rl_ldata.rl_tx_considx; 2303 if (cons == sc->rl_ldata.rl_tx_prodidx) 2304 return; 2305 2306 ifp = sc->rl_ifp; 2307 /* Invalidate the TX descriptor list */ 2308 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2309 sc->rl_ldata.rl_tx_list_map, 2310 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2311 2312 for (; cons != sc->rl_ldata.rl_tx_prodidx; 2313 cons = RL_TX_DESC_NXT(sc, cons)) { 2314 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 2315 if (txstat & RL_TDESC_STAT_OWN) 2316 break; 2317 /* 2318 * We only stash mbufs in the last descriptor 2319 * in a fragment chain, which also happens to 2320 * be the only place where the TX status bits 2321 * are valid. 2322 */ 2323 if (txstat & RL_TDESC_CMD_EOF) { 2324 txd = &sc->rl_ldata.rl_tx_desc[cons]; 2325 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2326 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2327 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2328 txd->tx_dmamap); 2329 KASSERT(txd->tx_m != NULL, 2330 ("%s: freeing NULL mbufs!", __func__)); 2331 m_freem(txd->tx_m); 2332 txd->tx_m = NULL; 2333 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 2334 RL_TDESC_STAT_COLCNT)) 2335 ifp->if_collisions++; 2336 if (txstat & RL_TDESC_STAT_TXERRSUM) 2337 ifp->if_oerrors++; 2338 else 2339 ifp->if_opackets++; 2340 } 2341 sc->rl_ldata.rl_tx_free++; 2342 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2343 } 2344 sc->rl_ldata.rl_tx_considx = cons; 2345 2346 /* No changes made to the TX ring, so no flush needed */ 2347 2348 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 2349 #ifdef RE_TX_MODERATION 2350 /* 2351 * If not all descriptors have been reaped yet, reload 2352 * the timer so that we will eventually get another 2353 * interrupt that will cause us to re-enter this routine. 2354 * This is done in case the transmitter has gone idle. 2355 */ 2356 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2357 #endif 2358 } else 2359 sc->rl_watchdog_timer = 0; 2360 } 2361 2362 static void 2363 re_tick(void *xsc) 2364 { 2365 struct rl_softc *sc; 2366 struct mii_data *mii; 2367 2368 sc = xsc; 2369 2370 RL_LOCK_ASSERT(sc); 2371 2372 mii = device_get_softc(sc->rl_miibus); 2373 mii_tick(mii); 2374 if ((sc->rl_flags & RL_FLAG_LINK) == 0) 2375 re_miibus_statchg(sc->rl_dev); 2376 /* 2377 * Reclaim transmitted frames here. Technically it is not 2378 * necessary to do here but it ensures periodic reclamation 2379 * regardless of Tx completion interrupt which seems to be 2380 * lost on PCIe based controllers under certain situations. 2381 */ 2382 re_txeof(sc); 2383 re_watchdog(sc); 2384 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2385 } 2386 2387 #ifdef DEVICE_POLLING 2388 static int 2389 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2390 { 2391 struct rl_softc *sc = ifp->if_softc; 2392 int rx_npkts = 0; 2393 2394 RL_LOCK(sc); 2395 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2396 rx_npkts = re_poll_locked(ifp, cmd, count); 2397 RL_UNLOCK(sc); 2398 return (rx_npkts); 2399 } 2400 2401 static int 2402 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2403 { 2404 struct rl_softc *sc = ifp->if_softc; 2405 int rx_npkts; 2406 2407 RL_LOCK_ASSERT(sc); 2408 2409 sc->rxcycles = count; 2410 re_rxeof(sc, &rx_npkts); 2411 re_txeof(sc); 2412 2413 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2414 re_start_locked(ifp); 2415 2416 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2417 u_int16_t status; 2418 2419 status = CSR_READ_2(sc, RL_ISR); 2420 if (status == 0xffff) 2421 return (rx_npkts); 2422 if (status) 2423 CSR_WRITE_2(sc, RL_ISR, status); 2424 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2425 (sc->rl_flags & RL_FLAG_PCIE)) 2426 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2427 2428 /* 2429 * XXX check behaviour on receiver stalls. 2430 */ 2431 2432 if (status & RL_ISR_SYSTEM_ERR) { 2433 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2434 re_init_locked(sc); 2435 } 2436 } 2437 return (rx_npkts); 2438 } 2439 #endif /* DEVICE_POLLING */ 2440 2441 static int 2442 re_intr(void *arg) 2443 { 2444 struct rl_softc *sc; 2445 uint16_t status; 2446 2447 sc = arg; 2448 2449 status = CSR_READ_2(sc, RL_ISR); 2450 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2451 return (FILTER_STRAY); 2452 CSR_WRITE_2(sc, RL_IMR, 0); 2453 2454 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2455 2456 return (FILTER_HANDLED); 2457 } 2458 2459 static void 2460 re_int_task(void *arg, int npending) 2461 { 2462 struct rl_softc *sc; 2463 struct ifnet *ifp; 2464 u_int16_t status; 2465 int rval = 0; 2466 2467 sc = arg; 2468 ifp = sc->rl_ifp; 2469 2470 RL_LOCK(sc); 2471 2472 status = CSR_READ_2(sc, RL_ISR); 2473 CSR_WRITE_2(sc, RL_ISR, status); 2474 2475 if (sc->suspended || 2476 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2477 RL_UNLOCK(sc); 2478 return; 2479 } 2480 2481 #ifdef DEVICE_POLLING 2482 if (ifp->if_capenable & IFCAP_POLLING) { 2483 RL_UNLOCK(sc); 2484 return; 2485 } 2486 #endif 2487 2488 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2489 rval = re_rxeof(sc, NULL); 2490 2491 /* 2492 * Some chips will ignore a second TX request issued 2493 * while an existing transmission is in progress. If 2494 * the transmitter goes idle but there are still 2495 * packets waiting to be sent, we need to restart the 2496 * channel here to flush them out. This only seems to 2497 * be required with the PCIe devices. 2498 */ 2499 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2500 (sc->rl_flags & RL_FLAG_PCIE)) 2501 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2502 if (status & ( 2503 #ifdef RE_TX_MODERATION 2504 RL_ISR_TIMEOUT_EXPIRED| 2505 #else 2506 RL_ISR_TX_OK| 2507 #endif 2508 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2509 re_txeof(sc); 2510 2511 if (status & RL_ISR_SYSTEM_ERR) { 2512 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2513 re_init_locked(sc); 2514 } 2515 2516 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2517 re_start_locked(ifp); 2518 2519 RL_UNLOCK(sc); 2520 2521 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2522 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2523 return; 2524 } 2525 2526 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2527 } 2528 2529 static void 2530 re_intr_msi(void *xsc) 2531 { 2532 struct rl_softc *sc; 2533 struct ifnet *ifp; 2534 uint16_t intrs, status; 2535 2536 sc = xsc; 2537 RL_LOCK(sc); 2538 2539 ifp = sc->rl_ifp; 2540 #ifdef DEVICE_POLLING 2541 if (ifp->if_capenable & IFCAP_POLLING) { 2542 RL_UNLOCK(sc); 2543 return; 2544 } 2545 #endif 2546 /* Disable interrupts. */ 2547 CSR_WRITE_2(sc, RL_IMR, 0); 2548 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2549 RL_UNLOCK(sc); 2550 return; 2551 } 2552 2553 intrs = RL_INTRS_CPLUS; 2554 status = CSR_READ_2(sc, RL_ISR); 2555 CSR_WRITE_2(sc, RL_ISR, status); 2556 if (sc->rl_int_rx_act > 0) { 2557 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW | 2558 RL_ISR_RX_OVERRUN); 2559 status &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW | 2560 RL_ISR_RX_OVERRUN); 2561 } 2562 2563 if (status & (RL_ISR_TIMEOUT_EXPIRED | RL_ISR_RX_OK | RL_ISR_RX_ERR | 2564 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) { 2565 re_rxeof(sc, NULL); 2566 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2567 if (sc->rl_int_rx_mod != 0 && 2568 (status & (RL_ISR_RX_OK | RL_ISR_RX_ERR | 2569 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) != 0) { 2570 /* Rearm one-shot timer. */ 2571 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2572 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | 2573 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN); 2574 sc->rl_int_rx_act = 1; 2575 } else { 2576 intrs |= RL_ISR_RX_OK | RL_ISR_RX_ERR | 2577 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN; 2578 sc->rl_int_rx_act = 0; 2579 } 2580 } 2581 } 2582 2583 /* 2584 * Some chips will ignore a second TX request issued 2585 * while an existing transmission is in progress. If 2586 * the transmitter goes idle but there are still 2587 * packets waiting to be sent, we need to restart the 2588 * channel here to flush them out. This only seems to 2589 * be required with the PCIe devices. 2590 */ 2591 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2592 (sc->rl_flags & RL_FLAG_PCIE)) 2593 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2594 if (status & (RL_ISR_TX_OK | RL_ISR_TX_ERR | RL_ISR_TX_DESC_UNAVAIL)) 2595 re_txeof(sc); 2596 2597 if (status & RL_ISR_SYSTEM_ERR) { 2598 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2599 re_init_locked(sc); 2600 } 2601 2602 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2603 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2604 re_start_locked(ifp); 2605 CSR_WRITE_2(sc, RL_IMR, intrs); 2606 } 2607 RL_UNLOCK(sc); 2608 } 2609 2610 static int 2611 re_encap(struct rl_softc *sc, struct mbuf **m_head) 2612 { 2613 struct rl_txdesc *txd, *txd_last; 2614 bus_dma_segment_t segs[RL_NTXSEGS]; 2615 bus_dmamap_t map; 2616 struct mbuf *m_new; 2617 struct rl_desc *desc; 2618 int nsegs, prod; 2619 int i, error, ei, si; 2620 int padlen; 2621 uint32_t cmdstat, csum_flags, vlanctl; 2622 2623 RL_LOCK_ASSERT(sc); 2624 M_ASSERTPKTHDR((*m_head)); 2625 2626 /* 2627 * With some of the RealTek chips, using the checksum offload 2628 * support in conjunction with the autopadding feature results 2629 * in the transmission of corrupt frames. For example, if we 2630 * need to send a really small IP fragment that's less than 60 2631 * bytes in size, and IP header checksumming is enabled, the 2632 * resulting ethernet frame that appears on the wire will 2633 * have garbled payload. To work around this, if TX IP checksum 2634 * offload is enabled, we always manually pad short frames out 2635 * to the minimum ethernet frame size. 2636 */ 2637 if ((sc->rl_flags & RL_FLAG_AUTOPAD) == 0 && 2638 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN && 2639 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) { 2640 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2641 if (M_WRITABLE(*m_head) == 0) { 2642 /* Get a writable copy. */ 2643 m_new = m_dup(*m_head, M_DONTWAIT); 2644 m_freem(*m_head); 2645 if (m_new == NULL) { 2646 *m_head = NULL; 2647 return (ENOBUFS); 2648 } 2649 *m_head = m_new; 2650 } 2651 if ((*m_head)->m_next != NULL || 2652 M_TRAILINGSPACE(*m_head) < padlen) { 2653 m_new = m_defrag(*m_head, M_DONTWAIT); 2654 if (m_new == NULL) { 2655 m_freem(*m_head); 2656 *m_head = NULL; 2657 return (ENOBUFS); 2658 } 2659 } else 2660 m_new = *m_head; 2661 2662 /* 2663 * Manually pad short frames, and zero the pad space 2664 * to avoid leaking data. 2665 */ 2666 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2667 m_new->m_pkthdr.len += padlen; 2668 m_new->m_len = m_new->m_pkthdr.len; 2669 *m_head = m_new; 2670 } 2671 2672 prod = sc->rl_ldata.rl_tx_prodidx; 2673 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2674 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2675 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2676 if (error == EFBIG) { 2677 m_new = m_collapse(*m_head, M_DONTWAIT, RL_NTXSEGS); 2678 if (m_new == NULL) { 2679 m_freem(*m_head); 2680 *m_head = NULL; 2681 return (ENOBUFS); 2682 } 2683 *m_head = m_new; 2684 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2685 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2686 if (error != 0) { 2687 m_freem(*m_head); 2688 *m_head = NULL; 2689 return (error); 2690 } 2691 } else if (error != 0) 2692 return (error); 2693 if (nsegs == 0) { 2694 m_freem(*m_head); 2695 *m_head = NULL; 2696 return (EIO); 2697 } 2698 2699 /* Check for number of available descriptors. */ 2700 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2701 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2702 return (ENOBUFS); 2703 } 2704 2705 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2706 BUS_DMASYNC_PREWRITE); 2707 2708 /* 2709 * Set up checksum offload. Note: checksum offload bits must 2710 * appear in all descriptors of a multi-descriptor transmit 2711 * attempt. This is according to testing done with an 8169 2712 * chip. This is a requirement. 2713 */ 2714 vlanctl = 0; 2715 csum_flags = 0; 2716 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2717 if ((sc->rl_flags & RL_FLAG_DESCV2) != 0) { 2718 csum_flags |= RL_TDESC_CMD_LGSEND; 2719 vlanctl |= ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2720 RL_TDESC_CMD_MSSVALV2_SHIFT); 2721 } else { 2722 csum_flags |= RL_TDESC_CMD_LGSEND | 2723 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2724 RL_TDESC_CMD_MSSVAL_SHIFT); 2725 } 2726 } else { 2727 /* 2728 * Unconditionally enable IP checksum if TCP or UDP 2729 * checksum is required. Otherwise, TCP/UDP checksum 2730 * does't make effects. 2731 */ 2732 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) { 2733 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2734 csum_flags |= RL_TDESC_CMD_IPCSUM; 2735 if (((*m_head)->m_pkthdr.csum_flags & 2736 CSUM_TCP) != 0) 2737 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2738 if (((*m_head)->m_pkthdr.csum_flags & 2739 CSUM_UDP) != 0) 2740 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2741 } else { 2742 vlanctl |= RL_TDESC_CMD_IPCSUMV2; 2743 if (((*m_head)->m_pkthdr.csum_flags & 2744 CSUM_TCP) != 0) 2745 vlanctl |= RL_TDESC_CMD_TCPCSUMV2; 2746 if (((*m_head)->m_pkthdr.csum_flags & 2747 CSUM_UDP) != 0) 2748 vlanctl |= RL_TDESC_CMD_UDPCSUMV2; 2749 } 2750 } 2751 } 2752 2753 /* 2754 * Set up hardware VLAN tagging. Note: vlan tag info must 2755 * appear in all descriptors of a multi-descriptor 2756 * transmission attempt. 2757 */ 2758 if ((*m_head)->m_flags & M_VLANTAG) 2759 vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) | 2760 RL_TDESC_VLANCTL_TAG; 2761 2762 si = prod; 2763 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2764 desc = &sc->rl_ldata.rl_tx_list[prod]; 2765 desc->rl_vlanctl = htole32(vlanctl); 2766 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2767 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2768 cmdstat = segs[i].ds_len; 2769 if (i != 0) 2770 cmdstat |= RL_TDESC_CMD_OWN; 2771 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2772 cmdstat |= RL_TDESC_CMD_EOR; 2773 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2774 sc->rl_ldata.rl_tx_free--; 2775 } 2776 /* Update producer index. */ 2777 sc->rl_ldata.rl_tx_prodidx = prod; 2778 2779 /* Set EOF on the last descriptor. */ 2780 ei = RL_TX_DESC_PRV(sc, prod); 2781 desc = &sc->rl_ldata.rl_tx_list[ei]; 2782 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2783 2784 desc = &sc->rl_ldata.rl_tx_list[si]; 2785 /* Set SOF and transfer ownership of packet to the chip. */ 2786 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2787 2788 /* 2789 * Insure that the map for this transmission 2790 * is placed at the array index of the last descriptor 2791 * in this chain. (Swap last and first dmamaps.) 2792 */ 2793 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2794 map = txd->tx_dmamap; 2795 txd->tx_dmamap = txd_last->tx_dmamap; 2796 txd_last->tx_dmamap = map; 2797 txd_last->tx_m = *m_head; 2798 2799 return (0); 2800 } 2801 2802 static void 2803 re_start(struct ifnet *ifp) 2804 { 2805 struct rl_softc *sc; 2806 2807 sc = ifp->if_softc; 2808 RL_LOCK(sc); 2809 re_start_locked(ifp); 2810 RL_UNLOCK(sc); 2811 } 2812 2813 /* 2814 * Main transmit routine for C+ and gigE NICs. 2815 */ 2816 static void 2817 re_start_locked(struct ifnet *ifp) 2818 { 2819 struct rl_softc *sc; 2820 struct mbuf *m_head; 2821 int queued; 2822 2823 sc = ifp->if_softc; 2824 2825 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2826 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) 2827 return; 2828 2829 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2830 sc->rl_ldata.rl_tx_free > 1;) { 2831 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2832 if (m_head == NULL) 2833 break; 2834 2835 if (re_encap(sc, &m_head) != 0) { 2836 if (m_head == NULL) 2837 break; 2838 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2839 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2840 break; 2841 } 2842 2843 /* 2844 * If there's a BPF listener, bounce a copy of this frame 2845 * to him. 2846 */ 2847 ETHER_BPF_MTAP(ifp, m_head); 2848 2849 queued++; 2850 } 2851 2852 if (queued == 0) { 2853 #ifdef RE_TX_MODERATION 2854 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2855 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2856 #endif 2857 return; 2858 } 2859 2860 /* Flush the TX descriptors */ 2861 2862 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2863 sc->rl_ldata.rl_tx_list_map, 2864 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2865 2866 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2867 2868 #ifdef RE_TX_MODERATION 2869 /* 2870 * Use the countdown timer for interrupt moderation. 2871 * 'TX done' interrupts are disabled. Instead, we reset the 2872 * countdown timer, which will begin counting until it hits 2873 * the value in the TIMERINT register, and then trigger an 2874 * interrupt. Each time we write to the TIMERCNT register, 2875 * the timer count is reset to 0. 2876 */ 2877 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2878 #endif 2879 2880 /* 2881 * Set a timeout in case the chip goes out to lunch. 2882 */ 2883 sc->rl_watchdog_timer = 5; 2884 } 2885 2886 static void 2887 re_set_jumbo(struct rl_softc *sc, int jumbo) 2888 { 2889 2890 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168E_VL) { 2891 pci_set_max_read_req(sc->rl_dev, 4096); 2892 return; 2893 } 2894 2895 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2896 if (jumbo != 0) { 2897 CSR_WRITE_1(sc, RL_CFG3, CSR_READ_1(sc, RL_CFG3) | 2898 RL_CFG3_JUMBO_EN0); 2899 switch (sc->rl_hwrev->rl_rev) { 2900 case RL_HWREV_8168DP: 2901 break; 2902 case RL_HWREV_8168E: 2903 CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) | 2904 0x01); 2905 break; 2906 default: 2907 CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) | 2908 RL_CFG4_JUMBO_EN1); 2909 } 2910 } else { 2911 CSR_WRITE_1(sc, RL_CFG3, CSR_READ_1(sc, RL_CFG3) & 2912 ~RL_CFG3_JUMBO_EN0); 2913 switch (sc->rl_hwrev->rl_rev) { 2914 case RL_HWREV_8168DP: 2915 break; 2916 case RL_HWREV_8168E: 2917 CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) & 2918 ~0x01); 2919 break; 2920 default: 2921 CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) & 2922 ~RL_CFG4_JUMBO_EN1); 2923 } 2924 } 2925 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2926 2927 switch (sc->rl_hwrev->rl_rev) { 2928 case RL_HWREV_8168DP: 2929 pci_set_max_read_req(sc->rl_dev, 4096); 2930 break; 2931 default: 2932 if (jumbo != 0) 2933 pci_set_max_read_req(sc->rl_dev, 512); 2934 else 2935 pci_set_max_read_req(sc->rl_dev, 4096); 2936 } 2937 } 2938 2939 static void 2940 re_init(void *xsc) 2941 { 2942 struct rl_softc *sc = xsc; 2943 2944 RL_LOCK(sc); 2945 re_init_locked(sc); 2946 RL_UNLOCK(sc); 2947 } 2948 2949 static void 2950 re_init_locked(struct rl_softc *sc) 2951 { 2952 struct ifnet *ifp = sc->rl_ifp; 2953 struct mii_data *mii; 2954 uint32_t reg; 2955 uint16_t cfg; 2956 union { 2957 uint32_t align_dummy; 2958 u_char eaddr[ETHER_ADDR_LEN]; 2959 } eaddr; 2960 2961 RL_LOCK_ASSERT(sc); 2962 2963 mii = device_get_softc(sc->rl_miibus); 2964 2965 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2966 return; 2967 2968 /* 2969 * Cancel pending I/O and free all RX/TX buffers. 2970 */ 2971 re_stop(sc); 2972 2973 /* Put controller into known state. */ 2974 re_reset(sc); 2975 2976 /* 2977 * For C+ mode, initialize the RX descriptors and mbufs. 2978 */ 2979 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 2980 if (ifp->if_mtu > RL_MTU) { 2981 if (re_jrx_list_init(sc) != 0) { 2982 device_printf(sc->rl_dev, 2983 "no memory for jumbo RX buffers\n"); 2984 re_stop(sc); 2985 return; 2986 } 2987 /* Disable checksum offloading for jumbo frames. */ 2988 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_TSO4); 2989 ifp->if_hwassist &= ~(RE_CSUM_FEATURES | CSUM_TSO); 2990 } else { 2991 if (re_rx_list_init(sc) != 0) { 2992 device_printf(sc->rl_dev, 2993 "no memory for RX buffers\n"); 2994 re_stop(sc); 2995 return; 2996 } 2997 } 2998 re_set_jumbo(sc, ifp->if_mtu > RL_MTU); 2999 } else { 3000 if (re_rx_list_init(sc) != 0) { 3001 device_printf(sc->rl_dev, "no memory for RX buffers\n"); 3002 re_stop(sc); 3003 return; 3004 } 3005 if ((sc->rl_flags & RL_FLAG_PCIE) != 0 && 3006 pci_get_device(sc->rl_dev) != RT_DEVICEID_8101E) { 3007 if (ifp->if_mtu > RL_MTU) 3008 pci_set_max_read_req(sc->rl_dev, 512); 3009 else 3010 pci_set_max_read_req(sc->rl_dev, 4096); 3011 } 3012 } 3013 re_tx_list_init(sc); 3014 3015 /* 3016 * Enable C+ RX and TX mode, as well as VLAN stripping and 3017 * RX checksum offload. We must configure the C+ register 3018 * before all others. 3019 */ 3020 cfg = RL_CPLUSCMD_PCI_MRW; 3021 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 3022 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 3023 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3024 cfg |= RL_CPLUSCMD_VLANSTRIP; 3025 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) { 3026 cfg |= RL_CPLUSCMD_MACSTAT_DIS; 3027 /* XXX magic. */ 3028 cfg |= 0x0001; 3029 } else 3030 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB; 3031 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg); 3032 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SC || 3033 sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) { 3034 reg = 0x000fff00; 3035 if ((CSR_READ_1(sc, RL_CFG2) & RL_CFG2_PCI66MHZ) != 0) 3036 reg |= 0x000000ff; 3037 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) 3038 reg |= 0x00f00000; 3039 CSR_WRITE_4(sc, 0x7c, reg); 3040 /* Disable interrupt mitigation. */ 3041 CSR_WRITE_2(sc, 0xe2, 0); 3042 } 3043 /* 3044 * Disable TSO if interface MTU size is greater than MSS 3045 * allowed in controller. 3046 */ 3047 if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) { 3048 ifp->if_capenable &= ~IFCAP_TSO4; 3049 ifp->if_hwassist &= ~CSUM_TSO; 3050 } 3051 3052 /* 3053 * Init our MAC address. Even though the chipset 3054 * documentation doesn't mention it, we need to enter "Config 3055 * register write enable" mode to modify the ID registers. 3056 */ 3057 /* Copy MAC address on stack to align. */ 3058 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 3059 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 3060 CSR_WRITE_4(sc, RL_IDR0, 3061 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 3062 CSR_WRITE_4(sc, RL_IDR4, 3063 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 3064 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3065 3066 /* 3067 * Load the addresses of the RX and TX lists into the chip. 3068 */ 3069 3070 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 3071 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 3072 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 3073 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 3074 3075 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 3076 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 3077 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 3078 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 3079 3080 /* 3081 * Enable transmit and receive. 3082 */ 3083 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 3084 3085 /* 3086 * Set the initial TX configuration. 3087 */ 3088 if (sc->rl_testmode) { 3089 if (sc->rl_type == RL_8169) 3090 CSR_WRITE_4(sc, RL_TXCFG, 3091 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 3092 else 3093 CSR_WRITE_4(sc, RL_TXCFG, 3094 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 3095 } else 3096 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 3097 3098 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 3099 3100 /* 3101 * Set the initial RX configuration. 3102 */ 3103 re_set_rxmode(sc); 3104 3105 /* Configure interrupt moderation. */ 3106 if (sc->rl_type == RL_8169) { 3107 /* Magic from vendor. */ 3108 CSR_WRITE_2(sc, RL_INTRMOD, 0x5100); 3109 } 3110 3111 #ifdef DEVICE_POLLING 3112 /* 3113 * Disable interrupts if we are polling. 3114 */ 3115 if (ifp->if_capenable & IFCAP_POLLING) 3116 CSR_WRITE_2(sc, RL_IMR, 0); 3117 else /* otherwise ... */ 3118 #endif 3119 3120 /* 3121 * Enable interrupts. 3122 */ 3123 if (sc->rl_testmode) 3124 CSR_WRITE_2(sc, RL_IMR, 0); 3125 else 3126 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 3127 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 3128 3129 /* Set initial TX threshold */ 3130 sc->rl_txthresh = RL_TX_THRESH_INIT; 3131 3132 /* Start RX/TX process. */ 3133 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 3134 #ifdef notdef 3135 /* Enable receiver and transmitter. */ 3136 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 3137 #endif 3138 3139 /* 3140 * Initialize the timer interrupt register so that 3141 * a timer interrupt will be generated once the timer 3142 * reaches a certain number of ticks. The timer is 3143 * reloaded on each transmit. 3144 */ 3145 #ifdef RE_TX_MODERATION 3146 /* 3147 * Use timer interrupt register to moderate TX interrupt 3148 * moderation, which dramatically improves TX frame rate. 3149 */ 3150 if (sc->rl_type == RL_8169) 3151 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 3152 else 3153 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 3154 #else 3155 /* 3156 * Use timer interrupt register to moderate RX interrupt 3157 * moderation. 3158 */ 3159 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 && 3160 intr_filter == 0) { 3161 if (sc->rl_type == RL_8169) 3162 CSR_WRITE_4(sc, RL_TIMERINT_8169, 3163 RL_USECS(sc->rl_int_rx_mod)); 3164 } else { 3165 if (sc->rl_type == RL_8169) 3166 CSR_WRITE_4(sc, RL_TIMERINT_8169, RL_USECS(0)); 3167 } 3168 #endif 3169 3170 /* 3171 * For 8169 gigE NICs, set the max allowed RX packet 3172 * size so we can receive jumbo frames. 3173 */ 3174 if (sc->rl_type == RL_8169) { 3175 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3176 /* 3177 * For controllers that use new jumbo frame scheme, 3178 * set maximum size of jumbo frame depedning on 3179 * controller revisions. 3180 */ 3181 if (ifp->if_mtu > RL_MTU) 3182 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 3183 sc->rl_hwrev->rl_max_mtu + 3184 ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN + 3185 ETHER_CRC_LEN); 3186 else 3187 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 3188 RE_RX_DESC_BUFLEN); 3189 } else if ((sc->rl_flags & RL_FLAG_PCIE) != 0 && 3190 sc->rl_hwrev->rl_max_mtu == RL_MTU) { 3191 /* RTL810x has no jumbo frame support. */ 3192 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, RE_RX_DESC_BUFLEN); 3193 } else 3194 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 3195 } 3196 3197 if (sc->rl_testmode) 3198 return; 3199 3200 mii_mediachg(mii); 3201 3202 CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD); 3203 3204 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3205 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3206 3207 sc->rl_flags &= ~RL_FLAG_LINK; 3208 sc->rl_watchdog_timer = 0; 3209 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 3210 } 3211 3212 /* 3213 * Set media options. 3214 */ 3215 static int 3216 re_ifmedia_upd(struct ifnet *ifp) 3217 { 3218 struct rl_softc *sc; 3219 struct mii_data *mii; 3220 int error; 3221 3222 sc = ifp->if_softc; 3223 mii = device_get_softc(sc->rl_miibus); 3224 RL_LOCK(sc); 3225 error = mii_mediachg(mii); 3226 RL_UNLOCK(sc); 3227 3228 return (error); 3229 } 3230 3231 /* 3232 * Report current media status. 3233 */ 3234 static void 3235 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3236 { 3237 struct rl_softc *sc; 3238 struct mii_data *mii; 3239 3240 sc = ifp->if_softc; 3241 mii = device_get_softc(sc->rl_miibus); 3242 3243 RL_LOCK(sc); 3244 mii_pollstat(mii); 3245 ifmr->ifm_active = mii->mii_media_active; 3246 ifmr->ifm_status = mii->mii_media_status; 3247 RL_UNLOCK(sc); 3248 } 3249 3250 static int 3251 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3252 { 3253 struct rl_softc *sc = ifp->if_softc; 3254 struct ifreq *ifr = (struct ifreq *) data; 3255 struct mii_data *mii; 3256 uint32_t rev; 3257 int error = 0; 3258 3259 switch (command) { 3260 case SIOCSIFMTU: 3261 if (ifr->ifr_mtu < ETHERMIN || 3262 ifr->ifr_mtu > sc->rl_hwrev->rl_max_mtu) { 3263 error = EINVAL; 3264 break; 3265 } 3266 RL_LOCK(sc); 3267 if (ifp->if_mtu != ifr->ifr_mtu) { 3268 ifp->if_mtu = ifr->ifr_mtu; 3269 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 3270 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3271 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3272 re_init_locked(sc); 3273 } 3274 if (ifp->if_mtu > RL_TSO_MTU && 3275 (ifp->if_capenable & IFCAP_TSO4) != 0) { 3276 ifp->if_capenable &= ~(IFCAP_TSO4 | 3277 IFCAP_VLAN_HWTSO); 3278 ifp->if_hwassist &= ~CSUM_TSO; 3279 } 3280 VLAN_CAPABILITIES(ifp); 3281 } 3282 RL_UNLOCK(sc); 3283 break; 3284 case SIOCSIFFLAGS: 3285 RL_LOCK(sc); 3286 if ((ifp->if_flags & IFF_UP) != 0) { 3287 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3288 if (((ifp->if_flags ^ sc->rl_if_flags) 3289 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 3290 re_set_rxmode(sc); 3291 } else 3292 re_init_locked(sc); 3293 } else { 3294 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3295 re_stop(sc); 3296 } 3297 sc->rl_if_flags = ifp->if_flags; 3298 RL_UNLOCK(sc); 3299 break; 3300 case SIOCADDMULTI: 3301 case SIOCDELMULTI: 3302 RL_LOCK(sc); 3303 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3304 re_set_rxmode(sc); 3305 RL_UNLOCK(sc); 3306 break; 3307 case SIOCGIFMEDIA: 3308 case SIOCSIFMEDIA: 3309 mii = device_get_softc(sc->rl_miibus); 3310 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3311 break; 3312 case SIOCSIFCAP: 3313 { 3314 int mask, reinit; 3315 3316 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3317 reinit = 0; 3318 #ifdef DEVICE_POLLING 3319 if (mask & IFCAP_POLLING) { 3320 if (ifr->ifr_reqcap & IFCAP_POLLING) { 3321 error = ether_poll_register(re_poll, ifp); 3322 if (error) 3323 return (error); 3324 RL_LOCK(sc); 3325 /* Disable interrupts */ 3326 CSR_WRITE_2(sc, RL_IMR, 0x0000); 3327 ifp->if_capenable |= IFCAP_POLLING; 3328 RL_UNLOCK(sc); 3329 } else { 3330 error = ether_poll_deregister(ifp); 3331 /* Enable interrupts. */ 3332 RL_LOCK(sc); 3333 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 3334 ifp->if_capenable &= ~IFCAP_POLLING; 3335 RL_UNLOCK(sc); 3336 } 3337 } 3338 #endif /* DEVICE_POLLING */ 3339 RL_LOCK(sc); 3340 if ((mask & IFCAP_TXCSUM) != 0 && 3341 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 3342 ifp->if_capenable ^= IFCAP_TXCSUM; 3343 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) { 3344 rev = sc->rl_hwrev->rl_rev; 3345 if (rev == RL_HWREV_8168C || 3346 rev == RL_HWREV_8168C_SPIN2) 3347 ifp->if_hwassist |= CSUM_TCP | CSUM_UDP; 3348 else 3349 ifp->if_hwassist |= RE_CSUM_FEATURES; 3350 } else 3351 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 3352 reinit = 1; 3353 } 3354 if ((mask & IFCAP_RXCSUM) != 0 && 3355 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 3356 ifp->if_capenable ^= IFCAP_RXCSUM; 3357 reinit = 1; 3358 } 3359 if ((mask & IFCAP_TSO4) != 0 && 3360 (ifp->if_capabilities & IFCAP_TSO) != 0) { 3361 ifp->if_capenable ^= IFCAP_TSO4; 3362 if ((IFCAP_TSO4 & ifp->if_capenable) != 0) 3363 ifp->if_hwassist |= CSUM_TSO; 3364 else 3365 ifp->if_hwassist &= ~CSUM_TSO; 3366 if (ifp->if_mtu > RL_TSO_MTU && 3367 (ifp->if_capenable & IFCAP_TSO4) != 0) { 3368 ifp->if_capenable &= ~IFCAP_TSO4; 3369 ifp->if_hwassist &= ~CSUM_TSO; 3370 } 3371 } 3372 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 3373 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 3374 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 3375 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3376 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 3377 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 3378 /* TSO over VLAN requires VLAN hardware tagging. */ 3379 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 3380 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 3381 reinit = 1; 3382 } 3383 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 3384 (mask & (IFCAP_HWCSUM | IFCAP_TSO4 | 3385 IFCAP_VLAN_HWTSO)) != 0) 3386 reinit = 1; 3387 if ((mask & IFCAP_WOL) != 0 && 3388 (ifp->if_capabilities & IFCAP_WOL) != 0) { 3389 if ((mask & IFCAP_WOL_UCAST) != 0) 3390 ifp->if_capenable ^= IFCAP_WOL_UCAST; 3391 if ((mask & IFCAP_WOL_MCAST) != 0) 3392 ifp->if_capenable ^= IFCAP_WOL_MCAST; 3393 if ((mask & IFCAP_WOL_MAGIC) != 0) 3394 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 3395 } 3396 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) { 3397 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3398 re_init_locked(sc); 3399 } 3400 RL_UNLOCK(sc); 3401 VLAN_CAPABILITIES(ifp); 3402 } 3403 break; 3404 default: 3405 error = ether_ioctl(ifp, command, data); 3406 break; 3407 } 3408 3409 return (error); 3410 } 3411 3412 static void 3413 re_watchdog(struct rl_softc *sc) 3414 { 3415 struct ifnet *ifp; 3416 3417 RL_LOCK_ASSERT(sc); 3418 3419 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 3420 return; 3421 3422 ifp = sc->rl_ifp; 3423 re_txeof(sc); 3424 if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) { 3425 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 3426 "-- recovering\n"); 3427 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3428 re_start_locked(ifp); 3429 return; 3430 } 3431 3432 if_printf(ifp, "watchdog timeout\n"); 3433 ifp->if_oerrors++; 3434 3435 re_rxeof(sc, NULL); 3436 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3437 re_init_locked(sc); 3438 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3439 re_start_locked(ifp); 3440 } 3441 3442 /* 3443 * Stop the adapter and free any mbufs allocated to the 3444 * RX and TX lists. 3445 */ 3446 static void 3447 re_stop(struct rl_softc *sc) 3448 { 3449 int i; 3450 struct ifnet *ifp; 3451 struct rl_txdesc *txd; 3452 struct rl_rxdesc *rxd; 3453 3454 RL_LOCK_ASSERT(sc); 3455 3456 ifp = sc->rl_ifp; 3457 3458 sc->rl_watchdog_timer = 0; 3459 callout_stop(&sc->rl_stat_callout); 3460 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3461 3462 if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0) 3463 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB | 3464 RL_CMD_RX_ENB); 3465 else 3466 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 3467 DELAY(1000); 3468 CSR_WRITE_2(sc, RL_IMR, 0x0000); 3469 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 3470 3471 if (sc->rl_head != NULL) { 3472 m_freem(sc->rl_head); 3473 sc->rl_head = sc->rl_tail = NULL; 3474 } 3475 3476 /* Free the TX list buffers. */ 3477 3478 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 3479 txd = &sc->rl_ldata.rl_tx_desc[i]; 3480 if (txd->tx_m != NULL) { 3481 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 3482 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3483 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 3484 txd->tx_dmamap); 3485 m_freem(txd->tx_m); 3486 txd->tx_m = NULL; 3487 } 3488 } 3489 3490 /* Free the RX list buffers. */ 3491 3492 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 3493 rxd = &sc->rl_ldata.rl_rx_desc[i]; 3494 if (rxd->rx_m != NULL) { 3495 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 3496 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3497 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 3498 rxd->rx_dmamap); 3499 m_freem(rxd->rx_m); 3500 rxd->rx_m = NULL; 3501 } 3502 } 3503 } 3504 3505 /* 3506 * Device suspend routine. Stop the interface and save some PCI 3507 * settings in case the BIOS doesn't restore them properly on 3508 * resume. 3509 */ 3510 static int 3511 re_suspend(device_t dev) 3512 { 3513 struct rl_softc *sc; 3514 3515 sc = device_get_softc(dev); 3516 3517 RL_LOCK(sc); 3518 re_stop(sc); 3519 re_setwol(sc); 3520 sc->suspended = 1; 3521 RL_UNLOCK(sc); 3522 3523 return (0); 3524 } 3525 3526 /* 3527 * Device resume routine. Restore some PCI settings in case the BIOS 3528 * doesn't, re-enable busmastering, and restart the interface if 3529 * appropriate. 3530 */ 3531 static int 3532 re_resume(device_t dev) 3533 { 3534 struct rl_softc *sc; 3535 struct ifnet *ifp; 3536 3537 sc = device_get_softc(dev); 3538 3539 RL_LOCK(sc); 3540 3541 ifp = sc->rl_ifp; 3542 /* Take controller out of sleep mode. */ 3543 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3544 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3545 CSR_WRITE_1(sc, RL_GPIO, 3546 CSR_READ_1(sc, RL_GPIO) | 0x01); 3547 } 3548 3549 /* 3550 * Clear WOL matching such that normal Rx filtering 3551 * wouldn't interfere with WOL patterns. 3552 */ 3553 re_clrwol(sc); 3554 3555 /* reinitialize interface if necessary */ 3556 if (ifp->if_flags & IFF_UP) 3557 re_init_locked(sc); 3558 3559 sc->suspended = 0; 3560 RL_UNLOCK(sc); 3561 3562 return (0); 3563 } 3564 3565 /* 3566 * Stop all chip I/O so that the kernel's probe routines don't 3567 * get confused by errant DMAs when rebooting. 3568 */ 3569 static int 3570 re_shutdown(device_t dev) 3571 { 3572 struct rl_softc *sc; 3573 3574 sc = device_get_softc(dev); 3575 3576 RL_LOCK(sc); 3577 re_stop(sc); 3578 /* 3579 * Mark interface as down since otherwise we will panic if 3580 * interrupt comes in later on, which can happen in some 3581 * cases. 3582 */ 3583 sc->rl_ifp->if_flags &= ~IFF_UP; 3584 re_setwol(sc); 3585 RL_UNLOCK(sc); 3586 3587 return (0); 3588 } 3589 3590 static void 3591 re_setwol(struct rl_softc *sc) 3592 { 3593 struct ifnet *ifp; 3594 int pmc; 3595 uint16_t pmstat; 3596 uint8_t v; 3597 3598 RL_LOCK_ASSERT(sc); 3599 3600 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3601 return; 3602 3603 ifp = sc->rl_ifp; 3604 /* Put controller into sleep mode. */ 3605 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3606 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3607 CSR_WRITE_1(sc, RL_GPIO, 3608 CSR_READ_1(sc, RL_GPIO) & ~0x01); 3609 } 3610 if ((ifp->if_capenable & IFCAP_WOL) != 0 && 3611 (sc->rl_flags & RL_FLAG_WOLRXENB) != 0) 3612 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB); 3613 /* Enable config register write. */ 3614 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3615 3616 /* Enable PME. */ 3617 v = CSR_READ_1(sc, RL_CFG1); 3618 v &= ~RL_CFG1_PME; 3619 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3620 v |= RL_CFG1_PME; 3621 CSR_WRITE_1(sc, RL_CFG1, v); 3622 3623 v = CSR_READ_1(sc, RL_CFG3); 3624 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3625 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3626 v |= RL_CFG3_WOL_MAGIC; 3627 CSR_WRITE_1(sc, RL_CFG3, v); 3628 3629 /* Config register write done. */ 3630 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3631 3632 v = CSR_READ_1(sc, RL_CFG5); 3633 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3634 v &= ~RL_CFG5_WOL_LANWAKE; 3635 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 3636 v |= RL_CFG5_WOL_UCAST; 3637 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 3638 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 3639 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3640 v |= RL_CFG5_WOL_LANWAKE; 3641 CSR_WRITE_1(sc, RL_CFG5, v); 3642 3643 if ((ifp->if_capenable & IFCAP_WOL) != 0 && 3644 (sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) 3645 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) & ~0x80); 3646 /* 3647 * It seems that hardware resets its link speed to 100Mbps in 3648 * power down mode so switching to 100Mbps in driver is not 3649 * needed. 3650 */ 3651 3652 /* Request PME if WOL is requested. */ 3653 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 3654 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3655 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3656 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3657 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 3658 } 3659 3660 static void 3661 re_clrwol(struct rl_softc *sc) 3662 { 3663 int pmc; 3664 uint8_t v; 3665 3666 RL_LOCK_ASSERT(sc); 3667 3668 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3669 return; 3670 3671 /* Enable config register write. */ 3672 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3673 3674 v = CSR_READ_1(sc, RL_CFG3); 3675 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3676 CSR_WRITE_1(sc, RL_CFG3, v); 3677 3678 /* Config register write done. */ 3679 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3680 3681 v = CSR_READ_1(sc, RL_CFG5); 3682 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3683 v &= ~RL_CFG5_WOL_LANWAKE; 3684 CSR_WRITE_1(sc, RL_CFG5, v); 3685 } 3686 3687 static void 3688 re_add_sysctls(struct rl_softc *sc) 3689 { 3690 struct sysctl_ctx_list *ctx; 3691 struct sysctl_oid_list *children; 3692 int error; 3693 3694 ctx = device_get_sysctl_ctx(sc->rl_dev); 3695 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev)); 3696 3697 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "stats", 3698 CTLTYPE_INT | CTLFLAG_RW, sc, 0, re_sysctl_stats, "I", 3699 "Statistics Information"); 3700 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) 3701 return; 3702 3703 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "int_rx_mod", 3704 CTLTYPE_INT | CTLFLAG_RW, &sc->rl_int_rx_mod, 0, 3705 sysctl_hw_re_int_mod, "I", "re RX interrupt moderation"); 3706 /* Pull in device tunables. */ 3707 sc->rl_int_rx_mod = RL_TIMER_DEFAULT; 3708 error = resource_int_value(device_get_name(sc->rl_dev), 3709 device_get_unit(sc->rl_dev), "int_rx_mod", &sc->rl_int_rx_mod); 3710 if (error == 0) { 3711 if (sc->rl_int_rx_mod < RL_TIMER_MIN || 3712 sc->rl_int_rx_mod > RL_TIMER_MAX) { 3713 device_printf(sc->rl_dev, "int_rx_mod value out of " 3714 "range; using default: %d\n", 3715 RL_TIMER_DEFAULT); 3716 sc->rl_int_rx_mod = RL_TIMER_DEFAULT; 3717 } 3718 } 3719 3720 } 3721 3722 static int 3723 re_sysctl_stats(SYSCTL_HANDLER_ARGS) 3724 { 3725 struct rl_softc *sc; 3726 struct rl_stats *stats; 3727 int error, i, result; 3728 3729 result = -1; 3730 error = sysctl_handle_int(oidp, &result, 0, req); 3731 if (error || req->newptr == NULL) 3732 return (error); 3733 3734 if (result == 1) { 3735 sc = (struct rl_softc *)arg1; 3736 RL_LOCK(sc); 3737 if ((sc->rl_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 3738 RL_UNLOCK(sc); 3739 goto done; 3740 } 3741 bus_dmamap_sync(sc->rl_ldata.rl_stag, 3742 sc->rl_ldata.rl_smap, BUS_DMASYNC_PREREAD); 3743 CSR_WRITE_4(sc, RL_DUMPSTATS_HI, 3744 RL_ADDR_HI(sc->rl_ldata.rl_stats_addr)); 3745 CSR_WRITE_4(sc, RL_DUMPSTATS_LO, 3746 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr)); 3747 CSR_WRITE_4(sc, RL_DUMPSTATS_LO, 3748 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr | 3749 RL_DUMPSTATS_START)); 3750 for (i = RL_TIMEOUT; i > 0; i--) { 3751 if ((CSR_READ_4(sc, RL_DUMPSTATS_LO) & 3752 RL_DUMPSTATS_START) == 0) 3753 break; 3754 DELAY(1000); 3755 } 3756 bus_dmamap_sync(sc->rl_ldata.rl_stag, 3757 sc->rl_ldata.rl_smap, BUS_DMASYNC_POSTREAD); 3758 RL_UNLOCK(sc); 3759 if (i == 0) { 3760 device_printf(sc->rl_dev, 3761 "DUMP statistics request timedout\n"); 3762 return (ETIMEDOUT); 3763 } 3764 done: 3765 stats = sc->rl_ldata.rl_stats; 3766 printf("%s statistics:\n", device_get_nameunit(sc->rl_dev)); 3767 printf("Tx frames : %ju\n", 3768 (uintmax_t)le64toh(stats->rl_tx_pkts)); 3769 printf("Rx frames : %ju\n", 3770 (uintmax_t)le64toh(stats->rl_rx_pkts)); 3771 printf("Tx errors : %ju\n", 3772 (uintmax_t)le64toh(stats->rl_tx_errs)); 3773 printf("Rx errors : %u\n", 3774 le32toh(stats->rl_rx_errs)); 3775 printf("Rx missed frames : %u\n", 3776 (uint32_t)le16toh(stats->rl_missed_pkts)); 3777 printf("Rx frame alignment errs : %u\n", 3778 (uint32_t)le16toh(stats->rl_rx_framealign_errs)); 3779 printf("Tx single collisions : %u\n", 3780 le32toh(stats->rl_tx_onecoll)); 3781 printf("Tx multiple collisions : %u\n", 3782 le32toh(stats->rl_tx_multicolls)); 3783 printf("Rx unicast frames : %ju\n", 3784 (uintmax_t)le64toh(stats->rl_rx_ucasts)); 3785 printf("Rx broadcast frames : %ju\n", 3786 (uintmax_t)le64toh(stats->rl_rx_bcasts)); 3787 printf("Rx multicast frames : %u\n", 3788 le32toh(stats->rl_rx_mcasts)); 3789 printf("Tx aborts : %u\n", 3790 (uint32_t)le16toh(stats->rl_tx_aborts)); 3791 printf("Tx underruns : %u\n", 3792 (uint32_t)le16toh(stats->rl_rx_underruns)); 3793 } 3794 3795 return (error); 3796 } 3797 3798 static int 3799 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3800 { 3801 int error, value; 3802 3803 if (arg1 == NULL) 3804 return (EINVAL); 3805 value = *(int *)arg1; 3806 error = sysctl_handle_int(oidp, &value, 0, req); 3807 if (error || req->newptr == NULL) 3808 return (error); 3809 if (value < low || value > high) 3810 return (EINVAL); 3811 *(int *)arg1 = value; 3812 3813 return (0); 3814 } 3815 3816 static int 3817 sysctl_hw_re_int_mod(SYSCTL_HANDLER_ARGS) 3818 { 3819 3820 return (sysctl_int_range(oidp, arg1, arg2, req, RL_TIMER_MIN, 3821 RL_TIMER_MAX)); 3822 } 3823