1 /*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44 /* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111 #ifdef HAVE_KERNEL_OPTION_HEADERS 112 #include "opt_device_polling.h" 113 #endif 114 115 #include <sys/param.h> 116 #include <sys/endian.h> 117 #include <sys/systm.h> 118 #include <sys/sockio.h> 119 #include <sys/mbuf.h> 120 #include <sys/malloc.h> 121 #include <sys/module.h> 122 #include <sys/kernel.h> 123 #include <sys/socket.h> 124 #include <sys/lock.h> 125 #include <sys/mutex.h> 126 #include <sys/sysctl.h> 127 #include <sys/taskqueue.h> 128 129 #include <net/if.h> 130 #include <net/if_var.h> 131 #include <net/if_arp.h> 132 #include <net/ethernet.h> 133 #include <net/if_dl.h> 134 #include <net/if_media.h> 135 #include <net/if_types.h> 136 #include <net/if_vlan_var.h> 137 138 #include <net/bpf.h> 139 140 #include <machine/bus.h> 141 #include <machine/resource.h> 142 #include <sys/bus.h> 143 #include <sys/rman.h> 144 145 #include <dev/mii/mii.h> 146 #include <dev/mii/miivar.h> 147 148 #include <dev/pci/pcireg.h> 149 #include <dev/pci/pcivar.h> 150 151 #include <pci/if_rlreg.h> 152 153 MODULE_DEPEND(re, pci, 1, 1, 1); 154 MODULE_DEPEND(re, ether, 1, 1, 1); 155 MODULE_DEPEND(re, miibus, 1, 1, 1); 156 157 /* "device miibus" required. See GENERIC if you get errors here. */ 158 #include "miibus_if.h" 159 160 /* Tunables. */ 161 static int intr_filter = 0; 162 TUNABLE_INT("hw.re.intr_filter", &intr_filter); 163 static int msi_disable = 0; 164 TUNABLE_INT("hw.re.msi_disable", &msi_disable); 165 static int msix_disable = 0; 166 TUNABLE_INT("hw.re.msix_disable", &msix_disable); 167 static int prefer_iomap = 0; 168 TUNABLE_INT("hw.re.prefer_iomap", &prefer_iomap); 169 170 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 171 172 /* 173 * Various supported device vendors/types and their names. 174 */ 175 static const struct rl_type re_devs[] = { 176 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0, 177 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 178 { DLINK_VENDORID, DLINK_DEVICEID_530T_REVC, 0, 179 "D-Link DGE-530(T) Gigabit Ethernet Adapter" }, 180 { RT_VENDORID, RT_DEVICEID_8139, 0, 181 "RealTek 8139C+ 10/100BaseTX" }, 182 { RT_VENDORID, RT_DEVICEID_8101E, 0, 183 "RealTek 810xE PCIe 10/100baseTX" }, 184 { RT_VENDORID, RT_DEVICEID_8168, 0, 185 "RealTek 8168/8111 B/C/CP/D/DP/E/F/G PCIe Gigabit Ethernet" }, 186 { RT_VENDORID, RT_DEVICEID_8169, 0, 187 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" }, 188 { RT_VENDORID, RT_DEVICEID_8169SC, 0, 189 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 190 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0, 191 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 192 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0, 193 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 194 { USR_VENDORID, USR_DEVICEID_997902, 0, 195 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 196 }; 197 198 static const struct rl_hwrev re_hwrevs[] = { 199 { RL_HWREV_8139, RL_8139, "", RL_MTU }, 200 { RL_HWREV_8139A, RL_8139, "A", RL_MTU }, 201 { RL_HWREV_8139AG, RL_8139, "A-G", RL_MTU }, 202 { RL_HWREV_8139B, RL_8139, "B", RL_MTU }, 203 { RL_HWREV_8130, RL_8139, "8130", RL_MTU }, 204 { RL_HWREV_8139C, RL_8139, "C", RL_MTU }, 205 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C", RL_MTU }, 206 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+", RL_MTU }, 207 { RL_HWREV_8168B_SPIN1, RL_8169, "8168", RL_JUMBO_MTU }, 208 { RL_HWREV_8169, RL_8169, "8169", RL_JUMBO_MTU }, 209 { RL_HWREV_8169S, RL_8169, "8169S", RL_JUMBO_MTU }, 210 { RL_HWREV_8110S, RL_8169, "8110S", RL_JUMBO_MTU }, 211 { RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB", RL_JUMBO_MTU }, 212 { RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU }, 213 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL", RL_JUMBO_MTU }, 214 { RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU }, 215 { RL_HWREV_8100, RL_8139, "8100", RL_MTU }, 216 { RL_HWREV_8101, RL_8139, "8101", RL_MTU }, 217 { RL_HWREV_8100E, RL_8169, "8100E", RL_MTU }, 218 { RL_HWREV_8101E, RL_8169, "8101E", RL_MTU }, 219 { RL_HWREV_8102E, RL_8169, "8102E", RL_MTU }, 220 { RL_HWREV_8102EL, RL_8169, "8102EL", RL_MTU }, 221 { RL_HWREV_8102EL_SPIN1, RL_8169, "8102EL", RL_MTU }, 222 { RL_HWREV_8103E, RL_8169, "8103E", RL_MTU }, 223 { RL_HWREV_8401E, RL_8169, "8401E", RL_MTU }, 224 { RL_HWREV_8402, RL_8169, "8402", RL_MTU }, 225 { RL_HWREV_8105E, RL_8169, "8105E", RL_MTU }, 226 { RL_HWREV_8105E_SPIN1, RL_8169, "8105E", RL_MTU }, 227 { RL_HWREV_8106E, RL_8169, "8106E", RL_MTU }, 228 { RL_HWREV_8168B_SPIN2, RL_8169, "8168", RL_JUMBO_MTU }, 229 { RL_HWREV_8168B_SPIN3, RL_8169, "8168", RL_JUMBO_MTU }, 230 { RL_HWREV_8168C, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K }, 231 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K }, 232 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP", RL_JUMBO_MTU_6K }, 233 { RL_HWREV_8168D, RL_8169, "8168D/8111D", RL_JUMBO_MTU_9K }, 234 { RL_HWREV_8168DP, RL_8169, "8168DP/8111DP", RL_JUMBO_MTU_9K }, 235 { RL_HWREV_8168E, RL_8169, "8168E/8111E", RL_JUMBO_MTU_9K}, 236 { RL_HWREV_8168E_VL, RL_8169, "8168E/8111E-VL", RL_JUMBO_MTU_6K}, 237 { RL_HWREV_8168EP, RL_8169, "8168EP/8111EP", RL_JUMBO_MTU_9K}, 238 { RL_HWREV_8168F, RL_8169, "8168F/8111F", RL_JUMBO_MTU_9K}, 239 { RL_HWREV_8168G, RL_8169, "8168G/8111G", RL_JUMBO_MTU_9K}, 240 { RL_HWREV_8168GU, RL_8169, "8168GU/8111GU", RL_JUMBO_MTU_9K}, 241 { RL_HWREV_8411, RL_8169, "8411", RL_JUMBO_MTU_9K}, 242 { RL_HWREV_8411B, RL_8169, "8411B", RL_JUMBO_MTU_9K}, 243 { 0, 0, NULL, 0 } 244 }; 245 246 static int re_probe (device_t); 247 static int re_attach (device_t); 248 static int re_detach (device_t); 249 250 static int re_encap (struct rl_softc *, struct mbuf **); 251 252 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 253 static int re_allocmem (device_t, struct rl_softc *); 254 static __inline void re_discard_rxbuf 255 (struct rl_softc *, int); 256 static int re_newbuf (struct rl_softc *, int); 257 static int re_jumbo_newbuf (struct rl_softc *, int); 258 static int re_rx_list_init (struct rl_softc *); 259 static int re_jrx_list_init (struct rl_softc *); 260 static int re_tx_list_init (struct rl_softc *); 261 #ifdef RE_FIXUP_RX 262 static __inline void re_fixup_rx 263 (struct mbuf *); 264 #endif 265 static int re_rxeof (struct rl_softc *, int *); 266 static void re_txeof (struct rl_softc *); 267 #ifdef DEVICE_POLLING 268 static int re_poll (struct ifnet *, enum poll_cmd, int); 269 static int re_poll_locked (struct ifnet *, enum poll_cmd, int); 270 #endif 271 static int re_intr (void *); 272 static void re_intr_msi (void *); 273 static void re_tick (void *); 274 static void re_int_task (void *, int); 275 static void re_start (struct ifnet *); 276 static void re_start_locked (struct ifnet *); 277 static int re_ioctl (struct ifnet *, u_long, caddr_t); 278 static void re_init (void *); 279 static void re_init_locked (struct rl_softc *); 280 static void re_stop (struct rl_softc *); 281 static void re_watchdog (struct rl_softc *); 282 static int re_suspend (device_t); 283 static int re_resume (device_t); 284 static int re_shutdown (device_t); 285 static int re_ifmedia_upd (struct ifnet *); 286 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 287 288 static void re_eeprom_putbyte (struct rl_softc *, int); 289 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 290 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 291 static int re_gmii_readreg (device_t, int, int); 292 static int re_gmii_writereg (device_t, int, int, int); 293 294 static int re_miibus_readreg (device_t, int, int); 295 static int re_miibus_writereg (device_t, int, int, int); 296 static void re_miibus_statchg (device_t); 297 298 static void re_set_jumbo (struct rl_softc *, int); 299 static void re_set_rxmode (struct rl_softc *); 300 static void re_reset (struct rl_softc *); 301 static void re_setwol (struct rl_softc *); 302 static void re_clrwol (struct rl_softc *); 303 static void re_set_linkspeed (struct rl_softc *); 304 305 #ifdef DEV_NETMAP /* see ixgbe.c for details */ 306 #include <dev/netmap/if_re_netmap.h> 307 #endif /* !DEV_NETMAP */ 308 309 #ifdef RE_DIAG 310 static int re_diag (struct rl_softc *); 311 #endif 312 313 static void re_add_sysctls (struct rl_softc *); 314 static int re_sysctl_stats (SYSCTL_HANDLER_ARGS); 315 static int sysctl_int_range (SYSCTL_HANDLER_ARGS, int, int); 316 static int sysctl_hw_re_int_mod (SYSCTL_HANDLER_ARGS); 317 318 static device_method_t re_methods[] = { 319 /* Device interface */ 320 DEVMETHOD(device_probe, re_probe), 321 DEVMETHOD(device_attach, re_attach), 322 DEVMETHOD(device_detach, re_detach), 323 DEVMETHOD(device_suspend, re_suspend), 324 DEVMETHOD(device_resume, re_resume), 325 DEVMETHOD(device_shutdown, re_shutdown), 326 327 /* MII interface */ 328 DEVMETHOD(miibus_readreg, re_miibus_readreg), 329 DEVMETHOD(miibus_writereg, re_miibus_writereg), 330 DEVMETHOD(miibus_statchg, re_miibus_statchg), 331 332 DEVMETHOD_END 333 }; 334 335 static driver_t re_driver = { 336 "re", 337 re_methods, 338 sizeof(struct rl_softc) 339 }; 340 341 static devclass_t re_devclass; 342 343 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 344 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 345 346 #define EE_SET(x) \ 347 CSR_WRITE_1(sc, RL_EECMD, \ 348 CSR_READ_1(sc, RL_EECMD) | x) 349 350 #define EE_CLR(x) \ 351 CSR_WRITE_1(sc, RL_EECMD, \ 352 CSR_READ_1(sc, RL_EECMD) & ~x) 353 354 /* 355 * Send a read command and address to the EEPROM, check for ACK. 356 */ 357 static void 358 re_eeprom_putbyte(struct rl_softc *sc, int addr) 359 { 360 int d, i; 361 362 d = addr | (RL_9346_READ << sc->rl_eewidth); 363 364 /* 365 * Feed in each bit and strobe the clock. 366 */ 367 368 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 369 if (d & i) { 370 EE_SET(RL_EE_DATAIN); 371 } else { 372 EE_CLR(RL_EE_DATAIN); 373 } 374 DELAY(100); 375 EE_SET(RL_EE_CLK); 376 DELAY(150); 377 EE_CLR(RL_EE_CLK); 378 DELAY(100); 379 } 380 } 381 382 /* 383 * Read a word of data stored in the EEPROM at address 'addr.' 384 */ 385 static void 386 re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest) 387 { 388 int i; 389 u_int16_t word = 0; 390 391 /* 392 * Send address of word we want to read. 393 */ 394 re_eeprom_putbyte(sc, addr); 395 396 /* 397 * Start reading bits from EEPROM. 398 */ 399 for (i = 0x8000; i; i >>= 1) { 400 EE_SET(RL_EE_CLK); 401 DELAY(100); 402 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 403 word |= i; 404 EE_CLR(RL_EE_CLK); 405 DELAY(100); 406 } 407 408 *dest = word; 409 } 410 411 /* 412 * Read a sequence of words from the EEPROM. 413 */ 414 static void 415 re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt) 416 { 417 int i; 418 u_int16_t word = 0, *ptr; 419 420 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 421 422 DELAY(100); 423 424 for (i = 0; i < cnt; i++) { 425 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 426 re_eeprom_getword(sc, off + i, &word); 427 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 428 ptr = (u_int16_t *)(dest + (i * 2)); 429 *ptr = word; 430 } 431 432 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 433 } 434 435 static int 436 re_gmii_readreg(device_t dev, int phy, int reg) 437 { 438 struct rl_softc *sc; 439 u_int32_t rval; 440 int i; 441 442 sc = device_get_softc(dev); 443 444 /* Let the rgephy driver read the GMEDIASTAT register */ 445 446 if (reg == RL_GMEDIASTAT) { 447 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 448 return (rval); 449 } 450 451 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 452 453 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 454 rval = CSR_READ_4(sc, RL_PHYAR); 455 if (rval & RL_PHYAR_BUSY) 456 break; 457 DELAY(25); 458 } 459 460 if (i == RL_PHY_TIMEOUT) { 461 device_printf(sc->rl_dev, "PHY read failed\n"); 462 return (0); 463 } 464 465 /* 466 * Controller requires a 20us delay to process next MDIO request. 467 */ 468 DELAY(20); 469 470 return (rval & RL_PHYAR_PHYDATA); 471 } 472 473 static int 474 re_gmii_writereg(device_t dev, int phy, int reg, int data) 475 { 476 struct rl_softc *sc; 477 u_int32_t rval; 478 int i; 479 480 sc = device_get_softc(dev); 481 482 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 483 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 484 485 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 486 rval = CSR_READ_4(sc, RL_PHYAR); 487 if (!(rval & RL_PHYAR_BUSY)) 488 break; 489 DELAY(25); 490 } 491 492 if (i == RL_PHY_TIMEOUT) { 493 device_printf(sc->rl_dev, "PHY write failed\n"); 494 return (0); 495 } 496 497 /* 498 * Controller requires a 20us delay to process next MDIO request. 499 */ 500 DELAY(20); 501 502 return (0); 503 } 504 505 static int 506 re_miibus_readreg(device_t dev, int phy, int reg) 507 { 508 struct rl_softc *sc; 509 u_int16_t rval = 0; 510 u_int16_t re8139_reg = 0; 511 512 sc = device_get_softc(dev); 513 514 if (sc->rl_type == RL_8169) { 515 rval = re_gmii_readreg(dev, phy, reg); 516 return (rval); 517 } 518 519 switch (reg) { 520 case MII_BMCR: 521 re8139_reg = RL_BMCR; 522 break; 523 case MII_BMSR: 524 re8139_reg = RL_BMSR; 525 break; 526 case MII_ANAR: 527 re8139_reg = RL_ANAR; 528 break; 529 case MII_ANER: 530 re8139_reg = RL_ANER; 531 break; 532 case MII_ANLPAR: 533 re8139_reg = RL_LPAR; 534 break; 535 case MII_PHYIDR1: 536 case MII_PHYIDR2: 537 return (0); 538 /* 539 * Allow the rlphy driver to read the media status 540 * register. If we have a link partner which does not 541 * support NWAY, this is the register which will tell 542 * us the results of parallel detection. 543 */ 544 case RL_MEDIASTAT: 545 rval = CSR_READ_1(sc, RL_MEDIASTAT); 546 return (rval); 547 default: 548 device_printf(sc->rl_dev, "bad phy register\n"); 549 return (0); 550 } 551 rval = CSR_READ_2(sc, re8139_reg); 552 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 553 /* 8139C+ has different bit layout. */ 554 rval &= ~(BMCR_LOOP | BMCR_ISO); 555 } 556 return (rval); 557 } 558 559 static int 560 re_miibus_writereg(device_t dev, int phy, int reg, int data) 561 { 562 struct rl_softc *sc; 563 u_int16_t re8139_reg = 0; 564 int rval = 0; 565 566 sc = device_get_softc(dev); 567 568 if (sc->rl_type == RL_8169) { 569 rval = re_gmii_writereg(dev, phy, reg, data); 570 return (rval); 571 } 572 573 switch (reg) { 574 case MII_BMCR: 575 re8139_reg = RL_BMCR; 576 if (sc->rl_type == RL_8139CPLUS) { 577 /* 8139C+ has different bit layout. */ 578 data &= ~(BMCR_LOOP | BMCR_ISO); 579 } 580 break; 581 case MII_BMSR: 582 re8139_reg = RL_BMSR; 583 break; 584 case MII_ANAR: 585 re8139_reg = RL_ANAR; 586 break; 587 case MII_ANER: 588 re8139_reg = RL_ANER; 589 break; 590 case MII_ANLPAR: 591 re8139_reg = RL_LPAR; 592 break; 593 case MII_PHYIDR1: 594 case MII_PHYIDR2: 595 return (0); 596 break; 597 default: 598 device_printf(sc->rl_dev, "bad phy register\n"); 599 return (0); 600 } 601 CSR_WRITE_2(sc, re8139_reg, data); 602 return (0); 603 } 604 605 static void 606 re_miibus_statchg(device_t dev) 607 { 608 struct rl_softc *sc; 609 struct ifnet *ifp; 610 struct mii_data *mii; 611 612 sc = device_get_softc(dev); 613 mii = device_get_softc(sc->rl_miibus); 614 ifp = sc->rl_ifp; 615 if (mii == NULL || ifp == NULL || 616 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 617 return; 618 619 sc->rl_flags &= ~RL_FLAG_LINK; 620 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 621 (IFM_ACTIVE | IFM_AVALID)) { 622 switch (IFM_SUBTYPE(mii->mii_media_active)) { 623 case IFM_10_T: 624 case IFM_100_TX: 625 sc->rl_flags |= RL_FLAG_LINK; 626 break; 627 case IFM_1000_T: 628 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0) 629 break; 630 sc->rl_flags |= RL_FLAG_LINK; 631 break; 632 default: 633 break; 634 } 635 } 636 /* 637 * RealTek controllers does not provide any interface to 638 * Tx/Rx MACs for resolved speed, duplex and flow-control 639 * parameters. 640 */ 641 } 642 643 /* 644 * Set the RX configuration and 64-bit multicast hash filter. 645 */ 646 static void 647 re_set_rxmode(struct rl_softc *sc) 648 { 649 struct ifnet *ifp; 650 struct ifmultiaddr *ifma; 651 uint32_t hashes[2] = { 0, 0 }; 652 uint32_t h, rxfilt; 653 654 RL_LOCK_ASSERT(sc); 655 656 ifp = sc->rl_ifp; 657 658 rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD; 659 660 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 661 if (ifp->if_flags & IFF_PROMISC) 662 rxfilt |= RL_RXCFG_RX_ALLPHYS; 663 /* 664 * Unlike other hardwares, we have to explicitly set 665 * RL_RXCFG_RX_MULTI to receive multicast frames in 666 * promiscuous mode. 667 */ 668 rxfilt |= RL_RXCFG_RX_MULTI; 669 hashes[0] = hashes[1] = 0xffffffff; 670 goto done; 671 } 672 673 if_maddr_rlock(ifp); 674 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 675 if (ifma->ifma_addr->sa_family != AF_LINK) 676 continue; 677 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 678 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 679 if (h < 32) 680 hashes[0] |= (1 << h); 681 else 682 hashes[1] |= (1 << (h - 32)); 683 } 684 if_maddr_runlock(ifp); 685 686 if (hashes[0] != 0 || hashes[1] != 0) { 687 /* 688 * For some unfathomable reason, RealTek decided to 689 * reverse the order of the multicast hash registers 690 * in the PCI Express parts. This means we have to 691 * write the hash pattern in reverse order for those 692 * devices. 693 */ 694 if ((sc->rl_flags & RL_FLAG_PCIE) != 0) { 695 h = bswap32(hashes[0]); 696 hashes[0] = bswap32(hashes[1]); 697 hashes[1] = h; 698 } 699 rxfilt |= RL_RXCFG_RX_MULTI; 700 } 701 702 done: 703 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 704 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 705 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 706 } 707 708 static void 709 re_reset(struct rl_softc *sc) 710 { 711 int i; 712 713 RL_LOCK_ASSERT(sc); 714 715 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 716 717 for (i = 0; i < RL_TIMEOUT; i++) { 718 DELAY(10); 719 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 720 break; 721 } 722 if (i == RL_TIMEOUT) 723 device_printf(sc->rl_dev, "reset never completed!\n"); 724 725 if ((sc->rl_flags & RL_FLAG_MACRESET) != 0) 726 CSR_WRITE_1(sc, 0x82, 1); 727 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169S) 728 re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0); 729 } 730 731 #ifdef RE_DIAG 732 733 /* 734 * The following routine is designed to test for a defect on some 735 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 736 * lines connected to the bus, however for a 32-bit only card, they 737 * should be pulled high. The result of this defect is that the 738 * NIC will not work right if you plug it into a 64-bit slot: DMA 739 * operations will be done with 64-bit transfers, which will fail 740 * because the 64-bit data lines aren't connected. 741 * 742 * There's no way to work around this (short of talking a soldering 743 * iron to the board), however we can detect it. The method we use 744 * here is to put the NIC into digital loopback mode, set the receiver 745 * to promiscuous mode, and then try to send a frame. We then compare 746 * the frame data we sent to what was received. If the data matches, 747 * then the NIC is working correctly, otherwise we know the user has 748 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 749 * slot. In the latter case, there's no way the NIC can work correctly, 750 * so we print out a message on the console and abort the device attach. 751 */ 752 753 static int 754 re_diag(struct rl_softc *sc) 755 { 756 struct ifnet *ifp = sc->rl_ifp; 757 struct mbuf *m0; 758 struct ether_header *eh; 759 struct rl_desc *cur_rx; 760 u_int16_t status; 761 u_int32_t rxstat; 762 int total_len, i, error = 0, phyaddr; 763 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 764 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 765 766 /* Allocate a single mbuf */ 767 MGETHDR(m0, M_NOWAIT, MT_DATA); 768 if (m0 == NULL) 769 return (ENOBUFS); 770 771 RL_LOCK(sc); 772 773 /* 774 * Initialize the NIC in test mode. This sets the chip up 775 * so that it can send and receive frames, but performs the 776 * following special functions: 777 * - Puts receiver in promiscuous mode 778 * - Enables digital loopback mode 779 * - Leaves interrupts turned off 780 */ 781 782 ifp->if_flags |= IFF_PROMISC; 783 sc->rl_testmode = 1; 784 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 785 re_init_locked(sc); 786 sc->rl_flags |= RL_FLAG_LINK; 787 if (sc->rl_type == RL_8169) 788 phyaddr = 1; 789 else 790 phyaddr = 0; 791 792 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 793 for (i = 0; i < RL_TIMEOUT; i++) { 794 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 795 if (!(status & BMCR_RESET)) 796 break; 797 } 798 799 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 800 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 801 802 DELAY(100000); 803 804 /* Put some data in the mbuf */ 805 806 eh = mtod(m0, struct ether_header *); 807 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 808 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 809 eh->ether_type = htons(ETHERTYPE_IP); 810 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 811 812 /* 813 * Queue the packet, start transmission. 814 * Note: IF_HANDOFF() ultimately calls re_start() for us. 815 */ 816 817 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 818 RL_UNLOCK(sc); 819 /* XXX: re_diag must not be called when in ALTQ mode */ 820 IF_HANDOFF(&ifp->if_snd, m0, ifp); 821 RL_LOCK(sc); 822 m0 = NULL; 823 824 /* Wait for it to propagate through the chip */ 825 826 DELAY(100000); 827 for (i = 0; i < RL_TIMEOUT; i++) { 828 status = CSR_READ_2(sc, RL_ISR); 829 CSR_WRITE_2(sc, RL_ISR, status); 830 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 831 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 832 break; 833 DELAY(10); 834 } 835 836 if (i == RL_TIMEOUT) { 837 device_printf(sc->rl_dev, 838 "diagnostic failed, failed to receive packet in" 839 " loopback mode\n"); 840 error = EIO; 841 goto done; 842 } 843 844 /* 845 * The packet should have been dumped into the first 846 * entry in the RX DMA ring. Grab it from there. 847 */ 848 849 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 850 sc->rl_ldata.rl_rx_list_map, 851 BUS_DMASYNC_POSTREAD); 852 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 853 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 854 BUS_DMASYNC_POSTREAD); 855 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 856 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 857 858 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 859 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 860 eh = mtod(m0, struct ether_header *); 861 862 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 863 total_len = RL_RXBYTES(cur_rx); 864 rxstat = le32toh(cur_rx->rl_cmdstat); 865 866 if (total_len != ETHER_MIN_LEN) { 867 device_printf(sc->rl_dev, 868 "diagnostic failed, received short packet\n"); 869 error = EIO; 870 goto done; 871 } 872 873 /* Test that the received packet data matches what we sent. */ 874 875 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 876 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 877 ntohs(eh->ether_type) != ETHERTYPE_IP) { 878 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 879 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 880 dst, ":", src, ":", ETHERTYPE_IP); 881 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 882 eh->ether_dhost, ":", eh->ether_shost, ":", 883 ntohs(eh->ether_type)); 884 device_printf(sc->rl_dev, "You may have a defective 32-bit " 885 "NIC plugged into a 64-bit PCI slot.\n"); 886 device_printf(sc->rl_dev, "Please re-install the NIC in a " 887 "32-bit slot for proper operation.\n"); 888 device_printf(sc->rl_dev, "Read the re(4) man page for more " 889 "details.\n"); 890 error = EIO; 891 } 892 893 done: 894 /* Turn interface off, release resources */ 895 896 sc->rl_testmode = 0; 897 sc->rl_flags &= ~RL_FLAG_LINK; 898 ifp->if_flags &= ~IFF_PROMISC; 899 re_stop(sc); 900 if (m0 != NULL) 901 m_freem(m0); 902 903 RL_UNLOCK(sc); 904 905 return (error); 906 } 907 908 #endif 909 910 /* 911 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 912 * IDs against our list and return a device name if we find a match. 913 */ 914 static int 915 re_probe(device_t dev) 916 { 917 const struct rl_type *t; 918 uint16_t devid, vendor; 919 uint16_t revid, sdevid; 920 int i; 921 922 vendor = pci_get_vendor(dev); 923 devid = pci_get_device(dev); 924 revid = pci_get_revid(dev); 925 sdevid = pci_get_subdevice(dev); 926 927 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 928 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 929 /* 930 * Only attach to rev. 3 of the Linksys EG1032 adapter. 931 * Rev. 2 is supported by sk(4). 932 */ 933 return (ENXIO); 934 } 935 } 936 937 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 938 if (revid != 0x20) { 939 /* 8139, let rl(4) take care of this device. */ 940 return (ENXIO); 941 } 942 } 943 944 t = re_devs; 945 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) { 946 if (vendor == t->rl_vid && devid == t->rl_did) { 947 device_set_desc(dev, t->rl_name); 948 return (BUS_PROBE_DEFAULT); 949 } 950 } 951 952 return (ENXIO); 953 } 954 955 /* 956 * Map a single buffer address. 957 */ 958 959 static void 960 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 961 { 962 bus_addr_t *addr; 963 964 if (error) 965 return; 966 967 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 968 addr = arg; 969 *addr = segs->ds_addr; 970 } 971 972 static int 973 re_allocmem(device_t dev, struct rl_softc *sc) 974 { 975 bus_addr_t lowaddr; 976 bus_size_t rx_list_size, tx_list_size; 977 int error; 978 int i; 979 980 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 981 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 982 983 /* 984 * Allocate the parent bus DMA tag appropriate for PCI. 985 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD 986 * register should be set. However some RealTek chips are known 987 * to be buggy on DAC handling, therefore disable DAC by limiting 988 * DMA address space to 32bit. PCIe variants of RealTek chips 989 * may not have the limitation. 990 */ 991 lowaddr = BUS_SPACE_MAXADDR; 992 if ((sc->rl_flags & RL_FLAG_PCIE) == 0) 993 lowaddr = BUS_SPACE_MAXADDR_32BIT; 994 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 995 lowaddr, BUS_SPACE_MAXADDR, NULL, NULL, 996 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 997 NULL, NULL, &sc->rl_parent_tag); 998 if (error) { 999 device_printf(dev, "could not allocate parent DMA tag\n"); 1000 return (error); 1001 } 1002 1003 /* 1004 * Allocate map for TX mbufs. 1005 */ 1006 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 1007 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1008 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 1009 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 1010 if (error) { 1011 device_printf(dev, "could not allocate TX DMA tag\n"); 1012 return (error); 1013 } 1014 1015 /* 1016 * Allocate map for RX mbufs. 1017 */ 1018 1019 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 1020 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 1021 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1022 MJUM9BYTES, 1, MJUM9BYTES, 0, NULL, NULL, 1023 &sc->rl_ldata.rl_jrx_mtag); 1024 if (error) { 1025 device_printf(dev, 1026 "could not allocate jumbo RX DMA tag\n"); 1027 return (error); 1028 } 1029 } 1030 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 1031 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1032 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 1033 if (error) { 1034 device_printf(dev, "could not allocate RX DMA tag\n"); 1035 return (error); 1036 } 1037 1038 /* 1039 * Allocate map for TX descriptor list. 1040 */ 1041 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1042 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1043 NULL, tx_list_size, 1, tx_list_size, 0, 1044 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1045 if (error) { 1046 device_printf(dev, "could not allocate TX DMA ring tag\n"); 1047 return (error); 1048 } 1049 1050 /* Allocate DMA'able memory for the TX ring */ 1051 1052 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1053 (void **)&sc->rl_ldata.rl_tx_list, 1054 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1055 &sc->rl_ldata.rl_tx_list_map); 1056 if (error) { 1057 device_printf(dev, "could not allocate TX DMA ring\n"); 1058 return (error); 1059 } 1060 1061 /* Load the map for the TX ring. */ 1062 1063 sc->rl_ldata.rl_tx_list_addr = 0; 1064 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1065 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1066 tx_list_size, re_dma_map_addr, 1067 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1068 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 1069 device_printf(dev, "could not load TX DMA ring\n"); 1070 return (ENOMEM); 1071 } 1072 1073 /* Create DMA maps for TX buffers */ 1074 1075 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1076 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1077 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1078 if (error) { 1079 device_printf(dev, "could not create DMA map for TX\n"); 1080 return (error); 1081 } 1082 } 1083 1084 /* 1085 * Allocate map for RX descriptor list. 1086 */ 1087 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1088 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1089 NULL, rx_list_size, 1, rx_list_size, 0, 1090 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1091 if (error) { 1092 device_printf(dev, "could not create RX DMA ring tag\n"); 1093 return (error); 1094 } 1095 1096 /* Allocate DMA'able memory for the RX ring */ 1097 1098 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1099 (void **)&sc->rl_ldata.rl_rx_list, 1100 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1101 &sc->rl_ldata.rl_rx_list_map); 1102 if (error) { 1103 device_printf(dev, "could not allocate RX DMA ring\n"); 1104 return (error); 1105 } 1106 1107 /* Load the map for the RX ring. */ 1108 1109 sc->rl_ldata.rl_rx_list_addr = 0; 1110 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1111 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1112 rx_list_size, re_dma_map_addr, 1113 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1114 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1115 device_printf(dev, "could not load RX DMA ring\n"); 1116 return (ENOMEM); 1117 } 1118 1119 /* Create DMA maps for RX buffers */ 1120 1121 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 1122 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0, 1123 &sc->rl_ldata.rl_jrx_sparemap); 1124 if (error) { 1125 device_printf(dev, 1126 "could not create spare DMA map for jumbo RX\n"); 1127 return (error); 1128 } 1129 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1130 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0, 1131 &sc->rl_ldata.rl_jrx_desc[i].rx_dmamap); 1132 if (error) { 1133 device_printf(dev, 1134 "could not create DMA map for jumbo RX\n"); 1135 return (error); 1136 } 1137 } 1138 } 1139 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1140 &sc->rl_ldata.rl_rx_sparemap); 1141 if (error) { 1142 device_printf(dev, "could not create spare DMA map for RX\n"); 1143 return (error); 1144 } 1145 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1146 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1147 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1148 if (error) { 1149 device_printf(dev, "could not create DMA map for RX\n"); 1150 return (error); 1151 } 1152 } 1153 1154 /* Create DMA map for statistics. */ 1155 error = bus_dma_tag_create(sc->rl_parent_tag, RL_DUMP_ALIGN, 0, 1156 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1157 sizeof(struct rl_stats), 1, sizeof(struct rl_stats), 0, NULL, NULL, 1158 &sc->rl_ldata.rl_stag); 1159 if (error) { 1160 device_printf(dev, "could not create statistics DMA tag\n"); 1161 return (error); 1162 } 1163 /* Allocate DMA'able memory for statistics. */ 1164 error = bus_dmamem_alloc(sc->rl_ldata.rl_stag, 1165 (void **)&sc->rl_ldata.rl_stats, 1166 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1167 &sc->rl_ldata.rl_smap); 1168 if (error) { 1169 device_printf(dev, 1170 "could not allocate statistics DMA memory\n"); 1171 return (error); 1172 } 1173 /* Load the map for statistics. */ 1174 sc->rl_ldata.rl_stats_addr = 0; 1175 error = bus_dmamap_load(sc->rl_ldata.rl_stag, sc->rl_ldata.rl_smap, 1176 sc->rl_ldata.rl_stats, sizeof(struct rl_stats), re_dma_map_addr, 1177 &sc->rl_ldata.rl_stats_addr, BUS_DMA_NOWAIT); 1178 if (error != 0 || sc->rl_ldata.rl_stats_addr == 0) { 1179 device_printf(dev, "could not load statistics DMA memory\n"); 1180 return (ENOMEM); 1181 } 1182 1183 return (0); 1184 } 1185 1186 /* 1187 * Attach the interface. Allocate softc structures, do ifmedia 1188 * setup and ethernet/BPF attach. 1189 */ 1190 static int 1191 re_attach(device_t dev) 1192 { 1193 u_char eaddr[ETHER_ADDR_LEN]; 1194 u_int16_t as[ETHER_ADDR_LEN / 2]; 1195 struct rl_softc *sc; 1196 struct ifnet *ifp; 1197 const struct rl_hwrev *hw_rev; 1198 u_int32_t cap, ctl; 1199 int hwrev; 1200 u_int16_t devid, re_did = 0; 1201 int error = 0, i, phy, rid; 1202 int msic, msixc, reg; 1203 uint8_t cfg; 1204 1205 sc = device_get_softc(dev); 1206 sc->rl_dev = dev; 1207 1208 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1209 MTX_DEF); 1210 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1211 1212 /* 1213 * Map control/status registers. 1214 */ 1215 pci_enable_busmaster(dev); 1216 1217 devid = pci_get_device(dev); 1218 /* 1219 * Prefer memory space register mapping over IO space. 1220 * Because RTL8169SC does not seem to work when memory mapping 1221 * is used always activate io mapping. 1222 */ 1223 if (devid == RT_DEVICEID_8169SC) 1224 prefer_iomap = 1; 1225 if (prefer_iomap == 0) { 1226 sc->rl_res_id = PCIR_BAR(1); 1227 sc->rl_res_type = SYS_RES_MEMORY; 1228 /* RTL8168/8101E seems to use different BARs. */ 1229 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E) 1230 sc->rl_res_id = PCIR_BAR(2); 1231 } else { 1232 sc->rl_res_id = PCIR_BAR(0); 1233 sc->rl_res_type = SYS_RES_IOPORT; 1234 } 1235 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1236 &sc->rl_res_id, RF_ACTIVE); 1237 if (sc->rl_res == NULL && prefer_iomap == 0) { 1238 sc->rl_res_id = PCIR_BAR(0); 1239 sc->rl_res_type = SYS_RES_IOPORT; 1240 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1241 &sc->rl_res_id, RF_ACTIVE); 1242 } 1243 if (sc->rl_res == NULL) { 1244 device_printf(dev, "couldn't map ports/memory\n"); 1245 error = ENXIO; 1246 goto fail; 1247 } 1248 1249 sc->rl_btag = rman_get_bustag(sc->rl_res); 1250 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1251 1252 msic = pci_msi_count(dev); 1253 msixc = pci_msix_count(dev); 1254 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 1255 sc->rl_flags |= RL_FLAG_PCIE; 1256 sc->rl_expcap = reg; 1257 } 1258 if (bootverbose) { 1259 device_printf(dev, "MSI count : %d\n", msic); 1260 device_printf(dev, "MSI-X count : %d\n", msixc); 1261 } 1262 if (msix_disable > 0) 1263 msixc = 0; 1264 if (msi_disable > 0) 1265 msic = 0; 1266 /* Prefer MSI-X to MSI. */ 1267 if (msixc > 0) { 1268 msixc = 1; 1269 rid = PCIR_BAR(4); 1270 sc->rl_res_pba = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1271 &rid, RF_ACTIVE); 1272 if (sc->rl_res_pba == NULL) { 1273 device_printf(sc->rl_dev, 1274 "could not allocate MSI-X PBA resource\n"); 1275 } 1276 if (sc->rl_res_pba != NULL && 1277 pci_alloc_msix(dev, &msixc) == 0) { 1278 if (msixc == 1) { 1279 device_printf(dev, "Using %d MSI-X message\n", 1280 msixc); 1281 sc->rl_flags |= RL_FLAG_MSIX; 1282 } else 1283 pci_release_msi(dev); 1284 } 1285 if ((sc->rl_flags & RL_FLAG_MSIX) == 0) { 1286 if (sc->rl_res_pba != NULL) 1287 bus_release_resource(dev, SYS_RES_MEMORY, rid, 1288 sc->rl_res_pba); 1289 sc->rl_res_pba = NULL; 1290 msixc = 0; 1291 } 1292 } 1293 /* Prefer MSI to INTx. */ 1294 if (msixc == 0 && msic > 0) { 1295 msic = 1; 1296 if (pci_alloc_msi(dev, &msic) == 0) { 1297 if (msic == RL_MSI_MESSAGES) { 1298 device_printf(dev, "Using %d MSI message\n", 1299 msic); 1300 sc->rl_flags |= RL_FLAG_MSI; 1301 /* Explicitly set MSI enable bit. */ 1302 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1303 cfg = CSR_READ_1(sc, RL_CFG2); 1304 cfg |= RL_CFG2_MSI; 1305 CSR_WRITE_1(sc, RL_CFG2, cfg); 1306 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1307 } else 1308 pci_release_msi(dev); 1309 } 1310 if ((sc->rl_flags & RL_FLAG_MSI) == 0) 1311 msic = 0; 1312 } 1313 1314 /* Allocate interrupt */ 1315 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) { 1316 rid = 0; 1317 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1318 RF_SHAREABLE | RF_ACTIVE); 1319 if (sc->rl_irq[0] == NULL) { 1320 device_printf(dev, "couldn't allocate IRQ resources\n"); 1321 error = ENXIO; 1322 goto fail; 1323 } 1324 } else { 1325 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1326 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1327 SYS_RES_IRQ, &rid, RF_ACTIVE); 1328 if (sc->rl_irq[i] == NULL) { 1329 device_printf(dev, 1330 "couldn't allocate IRQ resources for " 1331 "message %d\n", rid); 1332 error = ENXIO; 1333 goto fail; 1334 } 1335 } 1336 } 1337 1338 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1339 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1340 cfg = CSR_READ_1(sc, RL_CFG2); 1341 if ((cfg & RL_CFG2_MSI) != 0) { 1342 device_printf(dev, "turning off MSI enable bit.\n"); 1343 cfg &= ~RL_CFG2_MSI; 1344 CSR_WRITE_1(sc, RL_CFG2, cfg); 1345 } 1346 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1347 } 1348 1349 /* Disable ASPM L0S/L1. */ 1350 if (sc->rl_expcap != 0) { 1351 cap = pci_read_config(dev, sc->rl_expcap + 1352 PCIER_LINK_CAP, 2); 1353 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { 1354 ctl = pci_read_config(dev, sc->rl_expcap + 1355 PCIER_LINK_CTL, 2); 1356 if ((ctl & PCIEM_LINK_CTL_ASPMC) != 0) { 1357 ctl &= ~PCIEM_LINK_CTL_ASPMC; 1358 pci_write_config(dev, sc->rl_expcap + 1359 PCIER_LINK_CTL, ctl, 2); 1360 device_printf(dev, "ASPM disabled\n"); 1361 } 1362 } else 1363 device_printf(dev, "no ASPM capability\n"); 1364 } 1365 1366 hw_rev = re_hwrevs; 1367 hwrev = CSR_READ_4(sc, RL_TXCFG); 1368 switch (hwrev & 0x70000000) { 1369 case 0x00000000: 1370 case 0x10000000: 1371 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000); 1372 hwrev &= (RL_TXCFG_HWREV | 0x80000000); 1373 break; 1374 default: 1375 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000); 1376 sc->rl_macrev = hwrev & 0x00700000; 1377 hwrev &= RL_TXCFG_HWREV; 1378 break; 1379 } 1380 device_printf(dev, "MAC rev. 0x%08x\n", sc->rl_macrev); 1381 while (hw_rev->rl_desc != NULL) { 1382 if (hw_rev->rl_rev == hwrev) { 1383 sc->rl_type = hw_rev->rl_type; 1384 sc->rl_hwrev = hw_rev; 1385 break; 1386 } 1387 hw_rev++; 1388 } 1389 if (hw_rev->rl_desc == NULL) { 1390 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev); 1391 error = ENXIO; 1392 goto fail; 1393 } 1394 1395 switch (hw_rev->rl_rev) { 1396 case RL_HWREV_8139CPLUS: 1397 sc->rl_flags |= RL_FLAG_FASTETHER | RL_FLAG_AUTOPAD; 1398 break; 1399 case RL_HWREV_8100E: 1400 case RL_HWREV_8101E: 1401 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_FASTETHER; 1402 break; 1403 case RL_HWREV_8102E: 1404 case RL_HWREV_8102EL: 1405 case RL_HWREV_8102EL_SPIN1: 1406 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1407 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | 1408 RL_FLAG_AUTOPAD; 1409 break; 1410 case RL_HWREV_8103E: 1411 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1412 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | 1413 RL_FLAG_AUTOPAD | RL_FLAG_MACSLEEP; 1414 break; 1415 case RL_HWREV_8401E: 1416 case RL_HWREV_8105E: 1417 case RL_HWREV_8105E_SPIN1: 1418 case RL_HWREV_8106E: 1419 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1420 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1421 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD; 1422 break; 1423 case RL_HWREV_8402: 1424 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1425 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1426 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | 1427 RL_FLAG_CMDSTOP_WAIT_TXQ; 1428 break; 1429 case RL_HWREV_8168B_SPIN1: 1430 case RL_HWREV_8168B_SPIN2: 1431 sc->rl_flags |= RL_FLAG_WOLRXENB; 1432 /* FALLTHROUGH */ 1433 case RL_HWREV_8168B_SPIN3: 1434 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT; 1435 break; 1436 case RL_HWREV_8168C_SPIN2: 1437 sc->rl_flags |= RL_FLAG_MACSLEEP; 1438 /* FALLTHROUGH */ 1439 case RL_HWREV_8168C: 1440 if (sc->rl_macrev == 0x00200000) 1441 sc->rl_flags |= RL_FLAG_MACSLEEP; 1442 /* FALLTHROUGH */ 1443 case RL_HWREV_8168CP: 1444 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1445 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1446 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK; 1447 break; 1448 case RL_HWREV_8168D: 1449 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1450 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1451 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1452 RL_FLAG_WOL_MANLINK; 1453 break; 1454 case RL_HWREV_8168DP: 1455 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1456 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_AUTOPAD | 1457 RL_FLAG_JUMBOV2 | RL_FLAG_WAIT_TXPOLL | RL_FLAG_WOL_MANLINK; 1458 break; 1459 case RL_HWREV_8168E: 1460 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1461 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1462 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1463 RL_FLAG_WOL_MANLINK; 1464 break; 1465 case RL_HWREV_8168E_VL: 1466 case RL_HWREV_8168EP: 1467 case RL_HWREV_8168F: 1468 case RL_HWREV_8168G: 1469 case RL_HWREV_8411: 1470 case RL_HWREV_8411B: 1471 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1472 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1473 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1474 RL_FLAG_CMDSTOP_WAIT_TXQ | RL_FLAG_WOL_MANLINK; 1475 break; 1476 case RL_HWREV_8168GU: 1477 if (pci_get_device(dev) == RT_DEVICEID_8101E) { 1478 /* RTL8106EUS */ 1479 sc->rl_flags |= RL_FLAG_FASTETHER; 1480 } else 1481 sc->rl_flags |= RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK; 1482 1483 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1484 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1485 RL_FLAG_AUTOPAD | RL_FLAG_CMDSTOP_WAIT_TXQ; 1486 break; 1487 case RL_HWREV_8169_8110SB: 1488 case RL_HWREV_8169_8110SBL: 1489 case RL_HWREV_8169_8110SC: 1490 case RL_HWREV_8169_8110SCE: 1491 sc->rl_flags |= RL_FLAG_PHYWAKE; 1492 /* FALLTHROUGH */ 1493 case RL_HWREV_8169: 1494 case RL_HWREV_8169S: 1495 case RL_HWREV_8110S: 1496 sc->rl_flags |= RL_FLAG_MACRESET; 1497 break; 1498 default: 1499 break; 1500 } 1501 1502 if (sc->rl_hwrev->rl_rev == RL_HWREV_8139CPLUS) { 1503 sc->rl_cfg0 = RL_8139_CFG0; 1504 sc->rl_cfg1 = RL_8139_CFG1; 1505 sc->rl_cfg2 = 0; 1506 sc->rl_cfg3 = RL_8139_CFG3; 1507 sc->rl_cfg4 = RL_8139_CFG4; 1508 sc->rl_cfg5 = RL_8139_CFG5; 1509 } else { 1510 sc->rl_cfg0 = RL_CFG0; 1511 sc->rl_cfg1 = RL_CFG1; 1512 sc->rl_cfg2 = RL_CFG2; 1513 sc->rl_cfg3 = RL_CFG3; 1514 sc->rl_cfg4 = RL_CFG4; 1515 sc->rl_cfg5 = RL_CFG5; 1516 } 1517 1518 /* Reset the adapter. */ 1519 RL_LOCK(sc); 1520 re_reset(sc); 1521 RL_UNLOCK(sc); 1522 1523 /* Enable PME. */ 1524 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1525 cfg = CSR_READ_1(sc, sc->rl_cfg1); 1526 cfg |= RL_CFG1_PME; 1527 CSR_WRITE_1(sc, sc->rl_cfg1, cfg); 1528 cfg = CSR_READ_1(sc, sc->rl_cfg5); 1529 cfg &= RL_CFG5_PME_STS; 1530 CSR_WRITE_1(sc, sc->rl_cfg5, cfg); 1531 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1532 1533 if ((sc->rl_flags & RL_FLAG_PAR) != 0) { 1534 /* 1535 * XXX Should have a better way to extract station 1536 * address from EEPROM. 1537 */ 1538 for (i = 0; i < ETHER_ADDR_LEN; i++) 1539 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1540 } else { 1541 sc->rl_eewidth = RL_9356_ADDR_LEN; 1542 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1543 if (re_did != 0x8129) 1544 sc->rl_eewidth = RL_9346_ADDR_LEN; 1545 1546 /* 1547 * Get station address from the EEPROM. 1548 */ 1549 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1550 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1551 as[i] = le16toh(as[i]); 1552 bcopy(as, eaddr, ETHER_ADDR_LEN); 1553 } 1554 1555 if (sc->rl_type == RL_8169) { 1556 /* Set RX length mask and number of descriptors. */ 1557 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1558 sc->rl_txstart = RL_GTXSTART; 1559 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1560 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1561 } else { 1562 /* Set RX length mask and number of descriptors. */ 1563 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1564 sc->rl_txstart = RL_TXSTART; 1565 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1566 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1567 } 1568 1569 error = re_allocmem(dev, sc); 1570 if (error) 1571 goto fail; 1572 re_add_sysctls(sc); 1573 1574 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1575 if (ifp == NULL) { 1576 device_printf(dev, "can not if_alloc()\n"); 1577 error = ENOSPC; 1578 goto fail; 1579 } 1580 1581 /* Take controller out of deep sleep mode. */ 1582 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 1583 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 1584 CSR_WRITE_1(sc, RL_GPIO, 1585 CSR_READ_1(sc, RL_GPIO) | 0x01); 1586 else 1587 CSR_WRITE_1(sc, RL_GPIO, 1588 CSR_READ_1(sc, RL_GPIO) & ~0x01); 1589 } 1590 1591 /* Take PHY out of power down mode. */ 1592 if ((sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) { 1593 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80); 1594 if (hw_rev->rl_rev == RL_HWREV_8401E) 1595 CSR_WRITE_1(sc, 0xD1, CSR_READ_1(sc, 0xD1) & ~0x08); 1596 } 1597 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) { 1598 re_gmii_writereg(dev, 1, 0x1f, 0); 1599 re_gmii_writereg(dev, 1, 0x0e, 0); 1600 } 1601 1602 ifp->if_softc = sc; 1603 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1604 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1605 ifp->if_ioctl = re_ioctl; 1606 ifp->if_start = re_start; 1607 /* 1608 * RTL8168/8111C generates wrong IP checksummed frame if the 1609 * packet has IP options so disable TX IP checksum offloading. 1610 */ 1611 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168C || 1612 sc->rl_hwrev->rl_rev == RL_HWREV_8168C_SPIN2 || 1613 sc->rl_hwrev->rl_rev == RL_HWREV_8168CP) 1614 ifp->if_hwassist = CSUM_TCP | CSUM_UDP; 1615 else 1616 ifp->if_hwassist = CSUM_IP | CSUM_TCP | CSUM_UDP; 1617 ifp->if_hwassist |= CSUM_TSO; 1618 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 1619 ifp->if_capenable = ifp->if_capabilities; 1620 ifp->if_init = re_init; 1621 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1622 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1623 IFQ_SET_READY(&ifp->if_snd); 1624 1625 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1626 1627 #define RE_PHYAD_INTERNAL 0 1628 1629 /* Do MII setup. */ 1630 phy = RE_PHYAD_INTERNAL; 1631 if (sc->rl_type == RL_8169) 1632 phy = 1; 1633 error = mii_attach(dev, &sc->rl_miibus, ifp, re_ifmedia_upd, 1634 re_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, MIIF_DOPAUSE); 1635 if (error != 0) { 1636 device_printf(dev, "attaching PHYs failed\n"); 1637 goto fail; 1638 } 1639 1640 /* 1641 * Call MI attach routine. 1642 */ 1643 ether_ifattach(ifp, eaddr); 1644 1645 /* VLAN capability setup */ 1646 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1647 if (ifp->if_capabilities & IFCAP_HWCSUM) 1648 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1649 /* Enable WOL if PM is supported. */ 1650 if (pci_find_cap(sc->rl_dev, PCIY_PMG, ®) == 0) 1651 ifp->if_capabilities |= IFCAP_WOL; 1652 ifp->if_capenable = ifp->if_capabilities; 1653 ifp->if_capenable &= ~(IFCAP_WOL_UCAST | IFCAP_WOL_MCAST); 1654 /* 1655 * Don't enable TSO by default. It is known to generate 1656 * corrupted TCP segments(bad TCP options) under certain 1657 * circumstances. 1658 */ 1659 ifp->if_hwassist &= ~CSUM_TSO; 1660 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO); 1661 #ifdef DEVICE_POLLING 1662 ifp->if_capabilities |= IFCAP_POLLING; 1663 #endif 1664 /* 1665 * Tell the upper layer(s) we support long frames. 1666 * Must appear after the call to ether_ifattach() because 1667 * ether_ifattach() sets ifi_hdrlen to the default value. 1668 */ 1669 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1670 1671 #ifdef DEV_NETMAP 1672 re_netmap_attach(sc); 1673 #endif /* DEV_NETMAP */ 1674 #ifdef RE_DIAG 1675 /* 1676 * Perform hardware diagnostic on the original RTL8169. 1677 * Some 32-bit cards were incorrectly wired and would 1678 * malfunction if plugged into a 64-bit slot. 1679 */ 1680 1681 if (hwrev == RL_HWREV_8169) { 1682 error = re_diag(sc); 1683 if (error) { 1684 device_printf(dev, 1685 "attach aborted due to hardware diag failure\n"); 1686 ether_ifdetach(ifp); 1687 goto fail; 1688 } 1689 } 1690 #endif 1691 1692 #ifdef RE_TX_MODERATION 1693 intr_filter = 1; 1694 #endif 1695 /* Hook interrupt last to avoid having to lock softc */ 1696 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 && 1697 intr_filter == 0) { 1698 error = bus_setup_intr(dev, sc->rl_irq[0], 1699 INTR_TYPE_NET | INTR_MPSAFE, NULL, re_intr_msi, sc, 1700 &sc->rl_intrhand[0]); 1701 } else { 1702 error = bus_setup_intr(dev, sc->rl_irq[0], 1703 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1704 &sc->rl_intrhand[0]); 1705 } 1706 if (error) { 1707 device_printf(dev, "couldn't set up irq\n"); 1708 ether_ifdetach(ifp); 1709 } 1710 1711 fail: 1712 1713 if (error) 1714 re_detach(dev); 1715 1716 return (error); 1717 } 1718 1719 /* 1720 * Shutdown hardware and free up resources. This can be called any 1721 * time after the mutex has been initialized. It is called in both 1722 * the error case in attach and the normal detach case so it needs 1723 * to be careful about only freeing resources that have actually been 1724 * allocated. 1725 */ 1726 static int 1727 re_detach(device_t dev) 1728 { 1729 struct rl_softc *sc; 1730 struct ifnet *ifp; 1731 int i, rid; 1732 1733 sc = device_get_softc(dev); 1734 ifp = sc->rl_ifp; 1735 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1736 1737 /* These should only be active if attach succeeded */ 1738 if (device_is_attached(dev)) { 1739 #ifdef DEVICE_POLLING 1740 if (ifp->if_capenable & IFCAP_POLLING) 1741 ether_poll_deregister(ifp); 1742 #endif 1743 RL_LOCK(sc); 1744 #if 0 1745 sc->suspended = 1; 1746 #endif 1747 re_stop(sc); 1748 RL_UNLOCK(sc); 1749 callout_drain(&sc->rl_stat_callout); 1750 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1751 /* 1752 * Force off the IFF_UP flag here, in case someone 1753 * still had a BPF descriptor attached to this 1754 * interface. If they do, ether_ifdetach() will cause 1755 * the BPF code to try and clear the promisc mode 1756 * flag, which will bubble down to re_ioctl(), 1757 * which will try to call re_init() again. This will 1758 * turn the NIC back on and restart the MII ticker, 1759 * which will panic the system when the kernel tries 1760 * to invoke the re_tick() function that isn't there 1761 * anymore. 1762 */ 1763 ifp->if_flags &= ~IFF_UP; 1764 ether_ifdetach(ifp); 1765 } 1766 if (sc->rl_miibus) 1767 device_delete_child(dev, sc->rl_miibus); 1768 bus_generic_detach(dev); 1769 1770 /* 1771 * The rest is resource deallocation, so we should already be 1772 * stopped here. 1773 */ 1774 1775 if (sc->rl_intrhand[0] != NULL) { 1776 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]); 1777 sc->rl_intrhand[0] = NULL; 1778 } 1779 if (ifp != NULL) { 1780 #ifdef DEV_NETMAP 1781 netmap_detach(ifp); 1782 #endif /* DEV_NETMAP */ 1783 if_free(ifp); 1784 } 1785 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) 1786 rid = 0; 1787 else 1788 rid = 1; 1789 if (sc->rl_irq[0] != NULL) { 1790 bus_release_resource(dev, SYS_RES_IRQ, rid, sc->rl_irq[0]); 1791 sc->rl_irq[0] = NULL; 1792 } 1793 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0) 1794 pci_release_msi(dev); 1795 if (sc->rl_res_pba) { 1796 rid = PCIR_BAR(4); 1797 bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->rl_res_pba); 1798 } 1799 if (sc->rl_res) 1800 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, 1801 sc->rl_res); 1802 1803 /* Unload and free the RX DMA ring memory and map */ 1804 1805 if (sc->rl_ldata.rl_rx_list_tag) { 1806 if (sc->rl_ldata.rl_rx_list_map) 1807 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1808 sc->rl_ldata.rl_rx_list_map); 1809 if (sc->rl_ldata.rl_rx_list_map && sc->rl_ldata.rl_rx_list) 1810 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1811 sc->rl_ldata.rl_rx_list, 1812 sc->rl_ldata.rl_rx_list_map); 1813 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1814 } 1815 1816 /* Unload and free the TX DMA ring memory and map */ 1817 1818 if (sc->rl_ldata.rl_tx_list_tag) { 1819 if (sc->rl_ldata.rl_tx_list_map) 1820 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1821 sc->rl_ldata.rl_tx_list_map); 1822 if (sc->rl_ldata.rl_tx_list_map && sc->rl_ldata.rl_tx_list) 1823 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1824 sc->rl_ldata.rl_tx_list, 1825 sc->rl_ldata.rl_tx_list_map); 1826 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1827 } 1828 1829 /* Destroy all the RX and TX buffer maps */ 1830 1831 if (sc->rl_ldata.rl_tx_mtag) { 1832 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1833 if (sc->rl_ldata.rl_tx_desc[i].tx_dmamap) 1834 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1835 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1836 } 1837 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1838 } 1839 if (sc->rl_ldata.rl_rx_mtag) { 1840 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1841 if (sc->rl_ldata.rl_rx_desc[i].rx_dmamap) 1842 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1843 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1844 } 1845 if (sc->rl_ldata.rl_rx_sparemap) 1846 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1847 sc->rl_ldata.rl_rx_sparemap); 1848 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1849 } 1850 if (sc->rl_ldata.rl_jrx_mtag) { 1851 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1852 if (sc->rl_ldata.rl_jrx_desc[i].rx_dmamap) 1853 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag, 1854 sc->rl_ldata.rl_jrx_desc[i].rx_dmamap); 1855 } 1856 if (sc->rl_ldata.rl_jrx_sparemap) 1857 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag, 1858 sc->rl_ldata.rl_jrx_sparemap); 1859 bus_dma_tag_destroy(sc->rl_ldata.rl_jrx_mtag); 1860 } 1861 /* Unload and free the stats buffer and map */ 1862 1863 if (sc->rl_ldata.rl_stag) { 1864 if (sc->rl_ldata.rl_smap) 1865 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1866 sc->rl_ldata.rl_smap); 1867 if (sc->rl_ldata.rl_smap && sc->rl_ldata.rl_stats) 1868 bus_dmamem_free(sc->rl_ldata.rl_stag, 1869 sc->rl_ldata.rl_stats, sc->rl_ldata.rl_smap); 1870 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1871 } 1872 1873 if (sc->rl_parent_tag) 1874 bus_dma_tag_destroy(sc->rl_parent_tag); 1875 1876 mtx_destroy(&sc->rl_mtx); 1877 1878 return (0); 1879 } 1880 1881 static __inline void 1882 re_discard_rxbuf(struct rl_softc *sc, int idx) 1883 { 1884 struct rl_desc *desc; 1885 struct rl_rxdesc *rxd; 1886 uint32_t cmdstat; 1887 1888 if (sc->rl_ifp->if_mtu > RL_MTU && 1889 (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) 1890 rxd = &sc->rl_ldata.rl_jrx_desc[idx]; 1891 else 1892 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1893 desc = &sc->rl_ldata.rl_rx_list[idx]; 1894 desc->rl_vlanctl = 0; 1895 cmdstat = rxd->rx_size; 1896 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1897 cmdstat |= RL_RDESC_CMD_EOR; 1898 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1899 } 1900 1901 static int 1902 re_newbuf(struct rl_softc *sc, int idx) 1903 { 1904 struct mbuf *m; 1905 struct rl_rxdesc *rxd; 1906 bus_dma_segment_t segs[1]; 1907 bus_dmamap_t map; 1908 struct rl_desc *desc; 1909 uint32_t cmdstat; 1910 int error, nsegs; 1911 1912 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1913 if (m == NULL) 1914 return (ENOBUFS); 1915 1916 m->m_len = m->m_pkthdr.len = MCLBYTES; 1917 #ifdef RE_FIXUP_RX 1918 /* 1919 * This is part of an evil trick to deal with non-x86 platforms. 1920 * The RealTek chip requires RX buffers to be aligned on 64-bit 1921 * boundaries, but that will hose non-x86 machines. To get around 1922 * this, we leave some empty space at the start of each buffer 1923 * and for non-x86 hosts, we copy the buffer back six bytes 1924 * to achieve word alignment. This is slightly more efficient 1925 * than allocating a new buffer, copying the contents, and 1926 * discarding the old buffer. 1927 */ 1928 m_adj(m, RE_ETHER_ALIGN); 1929 #endif 1930 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1931 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1932 if (error != 0) { 1933 m_freem(m); 1934 return (ENOBUFS); 1935 } 1936 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1937 1938 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1939 if (rxd->rx_m != NULL) { 1940 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1941 BUS_DMASYNC_POSTREAD); 1942 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1943 } 1944 1945 rxd->rx_m = m; 1946 map = rxd->rx_dmamap; 1947 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1948 rxd->rx_size = segs[0].ds_len; 1949 sc->rl_ldata.rl_rx_sparemap = map; 1950 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1951 BUS_DMASYNC_PREREAD); 1952 1953 desc = &sc->rl_ldata.rl_rx_list[idx]; 1954 desc->rl_vlanctl = 0; 1955 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1956 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1957 cmdstat = segs[0].ds_len; 1958 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1959 cmdstat |= RL_RDESC_CMD_EOR; 1960 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1961 1962 return (0); 1963 } 1964 1965 static int 1966 re_jumbo_newbuf(struct rl_softc *sc, int idx) 1967 { 1968 struct mbuf *m; 1969 struct rl_rxdesc *rxd; 1970 bus_dma_segment_t segs[1]; 1971 bus_dmamap_t map; 1972 struct rl_desc *desc; 1973 uint32_t cmdstat; 1974 int error, nsegs; 1975 1976 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 1977 if (m == NULL) 1978 return (ENOBUFS); 1979 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1980 #ifdef RE_FIXUP_RX 1981 m_adj(m, RE_ETHER_ALIGN); 1982 #endif 1983 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_jrx_mtag, 1984 sc->rl_ldata.rl_jrx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1985 if (error != 0) { 1986 m_freem(m); 1987 return (ENOBUFS); 1988 } 1989 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1990 1991 rxd = &sc->rl_ldata.rl_jrx_desc[idx]; 1992 if (rxd->rx_m != NULL) { 1993 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap, 1994 BUS_DMASYNC_POSTREAD); 1995 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap); 1996 } 1997 1998 rxd->rx_m = m; 1999 map = rxd->rx_dmamap; 2000 rxd->rx_dmamap = sc->rl_ldata.rl_jrx_sparemap; 2001 rxd->rx_size = segs[0].ds_len; 2002 sc->rl_ldata.rl_jrx_sparemap = map; 2003 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap, 2004 BUS_DMASYNC_PREREAD); 2005 2006 desc = &sc->rl_ldata.rl_rx_list[idx]; 2007 desc->rl_vlanctl = 0; 2008 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 2009 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 2010 cmdstat = segs[0].ds_len; 2011 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 2012 cmdstat |= RL_RDESC_CMD_EOR; 2013 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 2014 2015 return (0); 2016 } 2017 2018 #ifdef RE_FIXUP_RX 2019 static __inline void 2020 re_fixup_rx(struct mbuf *m) 2021 { 2022 int i; 2023 uint16_t *src, *dst; 2024 2025 src = mtod(m, uint16_t *); 2026 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 2027 2028 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 2029 *dst++ = *src++; 2030 2031 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 2032 } 2033 #endif 2034 2035 static int 2036 re_tx_list_init(struct rl_softc *sc) 2037 { 2038 struct rl_desc *desc; 2039 int i; 2040 2041 RL_LOCK_ASSERT(sc); 2042 2043 bzero(sc->rl_ldata.rl_tx_list, 2044 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 2045 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 2046 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 2047 #ifdef DEV_NETMAP 2048 re_netmap_tx_init(sc); 2049 #endif /* DEV_NETMAP */ 2050 /* Set EOR. */ 2051 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 2052 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 2053 2054 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2055 sc->rl_ldata.rl_tx_list_map, 2056 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2057 2058 sc->rl_ldata.rl_tx_prodidx = 0; 2059 sc->rl_ldata.rl_tx_considx = 0; 2060 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 2061 2062 return (0); 2063 } 2064 2065 static int 2066 re_rx_list_init(struct rl_softc *sc) 2067 { 2068 int error, i; 2069 2070 bzero(sc->rl_ldata.rl_rx_list, 2071 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 2072 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2073 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 2074 if ((error = re_newbuf(sc, i)) != 0) 2075 return (error); 2076 } 2077 #ifdef DEV_NETMAP 2078 re_netmap_rx_init(sc); 2079 #endif /* DEV_NETMAP */ 2080 2081 /* Flush the RX descriptors */ 2082 2083 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2084 sc->rl_ldata.rl_rx_list_map, 2085 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2086 2087 sc->rl_ldata.rl_rx_prodidx = 0; 2088 sc->rl_head = sc->rl_tail = NULL; 2089 sc->rl_int_rx_act = 0; 2090 2091 return (0); 2092 } 2093 2094 static int 2095 re_jrx_list_init(struct rl_softc *sc) 2096 { 2097 int error, i; 2098 2099 bzero(sc->rl_ldata.rl_rx_list, 2100 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 2101 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2102 sc->rl_ldata.rl_jrx_desc[i].rx_m = NULL; 2103 if ((error = re_jumbo_newbuf(sc, i)) != 0) 2104 return (error); 2105 } 2106 2107 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2108 sc->rl_ldata.rl_rx_list_map, 2109 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2110 2111 sc->rl_ldata.rl_rx_prodidx = 0; 2112 sc->rl_head = sc->rl_tail = NULL; 2113 sc->rl_int_rx_act = 0; 2114 2115 return (0); 2116 } 2117 2118 /* 2119 * RX handler for C+ and 8169. For the gigE chips, we support 2120 * the reception of jumbo frames that have been fragmented 2121 * across multiple 2K mbuf cluster buffers. 2122 */ 2123 static int 2124 re_rxeof(struct rl_softc *sc, int *rx_npktsp) 2125 { 2126 struct mbuf *m; 2127 struct ifnet *ifp; 2128 int i, rxerr, total_len; 2129 struct rl_desc *cur_rx; 2130 u_int32_t rxstat, rxvlan; 2131 int jumbo, maxpkt = 16, rx_npkts = 0; 2132 2133 RL_LOCK_ASSERT(sc); 2134 2135 ifp = sc->rl_ifp; 2136 #ifdef DEV_NETMAP 2137 if (netmap_rx_irq(ifp, 0, &rx_npkts)) 2138 return 0; 2139 #endif /* DEV_NETMAP */ 2140 if (ifp->if_mtu > RL_MTU && (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) 2141 jumbo = 1; 2142 else 2143 jumbo = 0; 2144 2145 /* Invalidate the descriptor memory */ 2146 2147 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2148 sc->rl_ldata.rl_rx_list_map, 2149 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2150 2151 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 2152 i = RL_RX_DESC_NXT(sc, i)) { 2153 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2154 break; 2155 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 2156 rxstat = le32toh(cur_rx->rl_cmdstat); 2157 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 2158 break; 2159 total_len = rxstat & sc->rl_rxlenmask; 2160 rxvlan = le32toh(cur_rx->rl_vlanctl); 2161 if (jumbo != 0) 2162 m = sc->rl_ldata.rl_jrx_desc[i].rx_m; 2163 else 2164 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 2165 2166 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 2167 (rxstat & (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) != 2168 (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) { 2169 /* 2170 * RTL8168C or later controllers do not 2171 * support multi-fragment packet. 2172 */ 2173 re_discard_rxbuf(sc, i); 2174 continue; 2175 } else if ((rxstat & RL_RDESC_STAT_EOF) == 0) { 2176 if (re_newbuf(sc, i) != 0) { 2177 /* 2178 * If this is part of a multi-fragment packet, 2179 * discard all the pieces. 2180 */ 2181 if (sc->rl_head != NULL) { 2182 m_freem(sc->rl_head); 2183 sc->rl_head = sc->rl_tail = NULL; 2184 } 2185 re_discard_rxbuf(sc, i); 2186 continue; 2187 } 2188 m->m_len = RE_RX_DESC_BUFLEN; 2189 if (sc->rl_head == NULL) 2190 sc->rl_head = sc->rl_tail = m; 2191 else { 2192 m->m_flags &= ~M_PKTHDR; 2193 sc->rl_tail->m_next = m; 2194 sc->rl_tail = m; 2195 } 2196 continue; 2197 } 2198 2199 /* 2200 * NOTE: for the 8139C+, the frame length field 2201 * is always 12 bits in size, but for the gigE chips, 2202 * it is 13 bits (since the max RX frame length is 16K). 2203 * Unfortunately, all 32 bits in the status word 2204 * were already used, so to make room for the extra 2205 * length bit, RealTek took out the 'frame alignment 2206 * error' bit and shifted the other status bits 2207 * over one slot. The OWN, EOR, FS and LS bits are 2208 * still in the same places. We have already extracted 2209 * the frame length and checked the OWN bit, so rather 2210 * than using an alternate bit mapping, we shift the 2211 * status bits one space to the right so we can evaluate 2212 * them using the 8169 status as though it was in the 2213 * same format as that of the 8139C+. 2214 */ 2215 if (sc->rl_type == RL_8169) 2216 rxstat >>= 1; 2217 2218 /* 2219 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 2220 * set, but if CRC is clear, it will still be a valid frame. 2221 */ 2222 if ((rxstat & RL_RDESC_STAT_RXERRSUM) != 0) { 2223 rxerr = 1; 2224 if ((sc->rl_flags & RL_FLAG_JUMBOV2) == 0 && 2225 total_len > 8191 && 2226 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT) 2227 rxerr = 0; 2228 if (rxerr != 0) { 2229 ifp->if_ierrors++; 2230 /* 2231 * If this is part of a multi-fragment packet, 2232 * discard all the pieces. 2233 */ 2234 if (sc->rl_head != NULL) { 2235 m_freem(sc->rl_head); 2236 sc->rl_head = sc->rl_tail = NULL; 2237 } 2238 re_discard_rxbuf(sc, i); 2239 continue; 2240 } 2241 } 2242 2243 /* 2244 * If allocating a replacement mbuf fails, 2245 * reload the current one. 2246 */ 2247 if (jumbo != 0) 2248 rxerr = re_jumbo_newbuf(sc, i); 2249 else 2250 rxerr = re_newbuf(sc, i); 2251 if (rxerr != 0) { 2252 ifp->if_iqdrops++; 2253 if (sc->rl_head != NULL) { 2254 m_freem(sc->rl_head); 2255 sc->rl_head = sc->rl_tail = NULL; 2256 } 2257 re_discard_rxbuf(sc, i); 2258 continue; 2259 } 2260 2261 if (sc->rl_head != NULL) { 2262 if (jumbo != 0) 2263 m->m_len = total_len; 2264 else { 2265 m->m_len = total_len % RE_RX_DESC_BUFLEN; 2266 if (m->m_len == 0) 2267 m->m_len = RE_RX_DESC_BUFLEN; 2268 } 2269 /* 2270 * Special case: if there's 4 bytes or less 2271 * in this buffer, the mbuf can be discarded: 2272 * the last 4 bytes is the CRC, which we don't 2273 * care about anyway. 2274 */ 2275 if (m->m_len <= ETHER_CRC_LEN) { 2276 sc->rl_tail->m_len -= 2277 (ETHER_CRC_LEN - m->m_len); 2278 m_freem(m); 2279 } else { 2280 m->m_len -= ETHER_CRC_LEN; 2281 m->m_flags &= ~M_PKTHDR; 2282 sc->rl_tail->m_next = m; 2283 } 2284 m = sc->rl_head; 2285 sc->rl_head = sc->rl_tail = NULL; 2286 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 2287 } else 2288 m->m_pkthdr.len = m->m_len = 2289 (total_len - ETHER_CRC_LEN); 2290 2291 #ifdef RE_FIXUP_RX 2292 re_fixup_rx(m); 2293 #endif 2294 ifp->if_ipackets++; 2295 m->m_pkthdr.rcvif = ifp; 2296 2297 /* Do RX checksumming if enabled */ 2298 2299 if (ifp->if_capenable & IFCAP_RXCSUM) { 2300 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2301 /* Check IP header checksum */ 2302 if (rxstat & RL_RDESC_STAT_PROTOID) 2303 m->m_pkthdr.csum_flags |= 2304 CSUM_IP_CHECKED; 2305 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 2306 m->m_pkthdr.csum_flags |= 2307 CSUM_IP_VALID; 2308 2309 /* Check TCP/UDP checksum */ 2310 if ((RL_TCPPKT(rxstat) && 2311 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 2312 (RL_UDPPKT(rxstat) && 2313 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 2314 m->m_pkthdr.csum_flags |= 2315 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2316 m->m_pkthdr.csum_data = 0xffff; 2317 } 2318 } else { 2319 /* 2320 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP 2321 */ 2322 if ((rxstat & RL_RDESC_STAT_PROTOID) && 2323 (rxvlan & RL_RDESC_IPV4)) 2324 m->m_pkthdr.csum_flags |= 2325 CSUM_IP_CHECKED; 2326 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) && 2327 (rxvlan & RL_RDESC_IPV4)) 2328 m->m_pkthdr.csum_flags |= 2329 CSUM_IP_VALID; 2330 if (((rxstat & RL_RDESC_STAT_TCP) && 2331 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 2332 ((rxstat & RL_RDESC_STAT_UDP) && 2333 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 2334 m->m_pkthdr.csum_flags |= 2335 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2336 m->m_pkthdr.csum_data = 0xffff; 2337 } 2338 } 2339 } 2340 maxpkt--; 2341 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 2342 m->m_pkthdr.ether_vtag = 2343 bswap16((rxvlan & RL_RDESC_VLANCTL_DATA)); 2344 m->m_flags |= M_VLANTAG; 2345 } 2346 RL_UNLOCK(sc); 2347 (*ifp->if_input)(ifp, m); 2348 RL_LOCK(sc); 2349 rx_npkts++; 2350 } 2351 2352 /* Flush the RX DMA ring */ 2353 2354 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2355 sc->rl_ldata.rl_rx_list_map, 2356 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2357 2358 sc->rl_ldata.rl_rx_prodidx = i; 2359 2360 if (rx_npktsp != NULL) 2361 *rx_npktsp = rx_npkts; 2362 if (maxpkt) 2363 return (EAGAIN); 2364 2365 return (0); 2366 } 2367 2368 static void 2369 re_txeof(struct rl_softc *sc) 2370 { 2371 struct ifnet *ifp; 2372 struct rl_txdesc *txd; 2373 u_int32_t txstat; 2374 int cons; 2375 2376 cons = sc->rl_ldata.rl_tx_considx; 2377 if (cons == sc->rl_ldata.rl_tx_prodidx) 2378 return; 2379 2380 ifp = sc->rl_ifp; 2381 #ifdef DEV_NETMAP 2382 if (netmap_tx_irq(ifp, 0)) 2383 return; 2384 #endif /* DEV_NETMAP */ 2385 /* Invalidate the TX descriptor list */ 2386 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2387 sc->rl_ldata.rl_tx_list_map, 2388 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2389 2390 for (; cons != sc->rl_ldata.rl_tx_prodidx; 2391 cons = RL_TX_DESC_NXT(sc, cons)) { 2392 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 2393 if (txstat & RL_TDESC_STAT_OWN) 2394 break; 2395 /* 2396 * We only stash mbufs in the last descriptor 2397 * in a fragment chain, which also happens to 2398 * be the only place where the TX status bits 2399 * are valid. 2400 */ 2401 if (txstat & RL_TDESC_CMD_EOF) { 2402 txd = &sc->rl_ldata.rl_tx_desc[cons]; 2403 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2404 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2405 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2406 txd->tx_dmamap); 2407 KASSERT(txd->tx_m != NULL, 2408 ("%s: freeing NULL mbufs!", __func__)); 2409 m_freem(txd->tx_m); 2410 txd->tx_m = NULL; 2411 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 2412 RL_TDESC_STAT_COLCNT)) 2413 ifp->if_collisions++; 2414 if (txstat & RL_TDESC_STAT_TXERRSUM) 2415 ifp->if_oerrors++; 2416 else 2417 ifp->if_opackets++; 2418 } 2419 sc->rl_ldata.rl_tx_free++; 2420 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2421 } 2422 sc->rl_ldata.rl_tx_considx = cons; 2423 2424 /* No changes made to the TX ring, so no flush needed */ 2425 2426 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 2427 #ifdef RE_TX_MODERATION 2428 /* 2429 * If not all descriptors have been reaped yet, reload 2430 * the timer so that we will eventually get another 2431 * interrupt that will cause us to re-enter this routine. 2432 * This is done in case the transmitter has gone idle. 2433 */ 2434 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2435 #endif 2436 } else 2437 sc->rl_watchdog_timer = 0; 2438 } 2439 2440 static void 2441 re_tick(void *xsc) 2442 { 2443 struct rl_softc *sc; 2444 struct mii_data *mii; 2445 2446 sc = xsc; 2447 2448 RL_LOCK_ASSERT(sc); 2449 2450 mii = device_get_softc(sc->rl_miibus); 2451 mii_tick(mii); 2452 if ((sc->rl_flags & RL_FLAG_LINK) == 0) 2453 re_miibus_statchg(sc->rl_dev); 2454 /* 2455 * Reclaim transmitted frames here. Technically it is not 2456 * necessary to do here but it ensures periodic reclamation 2457 * regardless of Tx completion interrupt which seems to be 2458 * lost on PCIe based controllers under certain situations. 2459 */ 2460 re_txeof(sc); 2461 re_watchdog(sc); 2462 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2463 } 2464 2465 #ifdef DEVICE_POLLING 2466 static int 2467 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2468 { 2469 struct rl_softc *sc = ifp->if_softc; 2470 int rx_npkts = 0; 2471 2472 RL_LOCK(sc); 2473 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2474 rx_npkts = re_poll_locked(ifp, cmd, count); 2475 RL_UNLOCK(sc); 2476 return (rx_npkts); 2477 } 2478 2479 static int 2480 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2481 { 2482 struct rl_softc *sc = ifp->if_softc; 2483 int rx_npkts; 2484 2485 RL_LOCK_ASSERT(sc); 2486 2487 sc->rxcycles = count; 2488 re_rxeof(sc, &rx_npkts); 2489 re_txeof(sc); 2490 2491 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2492 re_start_locked(ifp); 2493 2494 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2495 u_int16_t status; 2496 2497 status = CSR_READ_2(sc, RL_ISR); 2498 if (status == 0xffff) 2499 return (rx_npkts); 2500 if (status) 2501 CSR_WRITE_2(sc, RL_ISR, status); 2502 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2503 (sc->rl_flags & RL_FLAG_PCIE)) 2504 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2505 2506 /* 2507 * XXX check behaviour on receiver stalls. 2508 */ 2509 2510 if (status & RL_ISR_SYSTEM_ERR) { 2511 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2512 re_init_locked(sc); 2513 } 2514 } 2515 return (rx_npkts); 2516 } 2517 #endif /* DEVICE_POLLING */ 2518 2519 static int 2520 re_intr(void *arg) 2521 { 2522 struct rl_softc *sc; 2523 uint16_t status; 2524 2525 sc = arg; 2526 2527 status = CSR_READ_2(sc, RL_ISR); 2528 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2529 return (FILTER_STRAY); 2530 CSR_WRITE_2(sc, RL_IMR, 0); 2531 2532 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2533 2534 return (FILTER_HANDLED); 2535 } 2536 2537 static void 2538 re_int_task(void *arg, int npending) 2539 { 2540 struct rl_softc *sc; 2541 struct ifnet *ifp; 2542 u_int16_t status; 2543 int rval = 0; 2544 2545 sc = arg; 2546 ifp = sc->rl_ifp; 2547 2548 RL_LOCK(sc); 2549 2550 status = CSR_READ_2(sc, RL_ISR); 2551 CSR_WRITE_2(sc, RL_ISR, status); 2552 2553 if (sc->suspended || 2554 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2555 RL_UNLOCK(sc); 2556 return; 2557 } 2558 2559 #ifdef DEVICE_POLLING 2560 if (ifp->if_capenable & IFCAP_POLLING) { 2561 RL_UNLOCK(sc); 2562 return; 2563 } 2564 #endif 2565 2566 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2567 rval = re_rxeof(sc, NULL); 2568 2569 /* 2570 * Some chips will ignore a second TX request issued 2571 * while an existing transmission is in progress. If 2572 * the transmitter goes idle but there are still 2573 * packets waiting to be sent, we need to restart the 2574 * channel here to flush them out. This only seems to 2575 * be required with the PCIe devices. 2576 */ 2577 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2578 (sc->rl_flags & RL_FLAG_PCIE)) 2579 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2580 if (status & ( 2581 #ifdef RE_TX_MODERATION 2582 RL_ISR_TIMEOUT_EXPIRED| 2583 #else 2584 RL_ISR_TX_OK| 2585 #endif 2586 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2587 re_txeof(sc); 2588 2589 if (status & RL_ISR_SYSTEM_ERR) { 2590 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2591 re_init_locked(sc); 2592 } 2593 2594 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2595 re_start_locked(ifp); 2596 2597 RL_UNLOCK(sc); 2598 2599 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2600 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2601 return; 2602 } 2603 2604 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2605 } 2606 2607 static void 2608 re_intr_msi(void *xsc) 2609 { 2610 struct rl_softc *sc; 2611 struct ifnet *ifp; 2612 uint16_t intrs, status; 2613 2614 sc = xsc; 2615 RL_LOCK(sc); 2616 2617 ifp = sc->rl_ifp; 2618 #ifdef DEVICE_POLLING 2619 if (ifp->if_capenable & IFCAP_POLLING) { 2620 RL_UNLOCK(sc); 2621 return; 2622 } 2623 #endif 2624 /* Disable interrupts. */ 2625 CSR_WRITE_2(sc, RL_IMR, 0); 2626 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2627 RL_UNLOCK(sc); 2628 return; 2629 } 2630 2631 intrs = RL_INTRS_CPLUS; 2632 status = CSR_READ_2(sc, RL_ISR); 2633 CSR_WRITE_2(sc, RL_ISR, status); 2634 if (sc->rl_int_rx_act > 0) { 2635 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW | 2636 RL_ISR_RX_OVERRUN); 2637 status &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW | 2638 RL_ISR_RX_OVERRUN); 2639 } 2640 2641 if (status & (RL_ISR_TIMEOUT_EXPIRED | RL_ISR_RX_OK | RL_ISR_RX_ERR | 2642 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) { 2643 re_rxeof(sc, NULL); 2644 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2645 if (sc->rl_int_rx_mod != 0 && 2646 (status & (RL_ISR_RX_OK | RL_ISR_RX_ERR | 2647 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) != 0) { 2648 /* Rearm one-shot timer. */ 2649 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2650 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | 2651 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN); 2652 sc->rl_int_rx_act = 1; 2653 } else { 2654 intrs |= RL_ISR_RX_OK | RL_ISR_RX_ERR | 2655 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN; 2656 sc->rl_int_rx_act = 0; 2657 } 2658 } 2659 } 2660 2661 /* 2662 * Some chips will ignore a second TX request issued 2663 * while an existing transmission is in progress. If 2664 * the transmitter goes idle but there are still 2665 * packets waiting to be sent, we need to restart the 2666 * channel here to flush them out. This only seems to 2667 * be required with the PCIe devices. 2668 */ 2669 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2670 (sc->rl_flags & RL_FLAG_PCIE)) 2671 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2672 if (status & (RL_ISR_TX_OK | RL_ISR_TX_ERR | RL_ISR_TX_DESC_UNAVAIL)) 2673 re_txeof(sc); 2674 2675 if (status & RL_ISR_SYSTEM_ERR) { 2676 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2677 re_init_locked(sc); 2678 } 2679 2680 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2681 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2682 re_start_locked(ifp); 2683 CSR_WRITE_2(sc, RL_IMR, intrs); 2684 } 2685 RL_UNLOCK(sc); 2686 } 2687 2688 static int 2689 re_encap(struct rl_softc *sc, struct mbuf **m_head) 2690 { 2691 struct rl_txdesc *txd, *txd_last; 2692 bus_dma_segment_t segs[RL_NTXSEGS]; 2693 bus_dmamap_t map; 2694 struct mbuf *m_new; 2695 struct rl_desc *desc; 2696 int nsegs, prod; 2697 int i, error, ei, si; 2698 int padlen; 2699 uint32_t cmdstat, csum_flags, vlanctl; 2700 2701 RL_LOCK_ASSERT(sc); 2702 M_ASSERTPKTHDR((*m_head)); 2703 2704 /* 2705 * With some of the RealTek chips, using the checksum offload 2706 * support in conjunction with the autopadding feature results 2707 * in the transmission of corrupt frames. For example, if we 2708 * need to send a really small IP fragment that's less than 60 2709 * bytes in size, and IP header checksumming is enabled, the 2710 * resulting ethernet frame that appears on the wire will 2711 * have garbled payload. To work around this, if TX IP checksum 2712 * offload is enabled, we always manually pad short frames out 2713 * to the minimum ethernet frame size. 2714 */ 2715 if ((sc->rl_flags & RL_FLAG_AUTOPAD) == 0 && 2716 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN && 2717 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) { 2718 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2719 if (M_WRITABLE(*m_head) == 0) { 2720 /* Get a writable copy. */ 2721 m_new = m_dup(*m_head, M_NOWAIT); 2722 m_freem(*m_head); 2723 if (m_new == NULL) { 2724 *m_head = NULL; 2725 return (ENOBUFS); 2726 } 2727 *m_head = m_new; 2728 } 2729 if ((*m_head)->m_next != NULL || 2730 M_TRAILINGSPACE(*m_head) < padlen) { 2731 m_new = m_defrag(*m_head, M_NOWAIT); 2732 if (m_new == NULL) { 2733 m_freem(*m_head); 2734 *m_head = NULL; 2735 return (ENOBUFS); 2736 } 2737 } else 2738 m_new = *m_head; 2739 2740 /* 2741 * Manually pad short frames, and zero the pad space 2742 * to avoid leaking data. 2743 */ 2744 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2745 m_new->m_pkthdr.len += padlen; 2746 m_new->m_len = m_new->m_pkthdr.len; 2747 *m_head = m_new; 2748 } 2749 2750 prod = sc->rl_ldata.rl_tx_prodidx; 2751 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2752 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2753 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2754 if (error == EFBIG) { 2755 m_new = m_collapse(*m_head, M_NOWAIT, RL_NTXSEGS); 2756 if (m_new == NULL) { 2757 m_freem(*m_head); 2758 *m_head = NULL; 2759 return (ENOBUFS); 2760 } 2761 *m_head = m_new; 2762 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2763 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2764 if (error != 0) { 2765 m_freem(*m_head); 2766 *m_head = NULL; 2767 return (error); 2768 } 2769 } else if (error != 0) 2770 return (error); 2771 if (nsegs == 0) { 2772 m_freem(*m_head); 2773 *m_head = NULL; 2774 return (EIO); 2775 } 2776 2777 /* Check for number of available descriptors. */ 2778 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2779 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2780 return (ENOBUFS); 2781 } 2782 2783 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2784 BUS_DMASYNC_PREWRITE); 2785 2786 /* 2787 * Set up checksum offload. Note: checksum offload bits must 2788 * appear in all descriptors of a multi-descriptor transmit 2789 * attempt. This is according to testing done with an 8169 2790 * chip. This is a requirement. 2791 */ 2792 vlanctl = 0; 2793 csum_flags = 0; 2794 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2795 if ((sc->rl_flags & RL_FLAG_DESCV2) != 0) { 2796 csum_flags |= RL_TDESC_CMD_LGSEND; 2797 vlanctl |= ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2798 RL_TDESC_CMD_MSSVALV2_SHIFT); 2799 } else { 2800 csum_flags |= RL_TDESC_CMD_LGSEND | 2801 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2802 RL_TDESC_CMD_MSSVAL_SHIFT); 2803 } 2804 } else { 2805 /* 2806 * Unconditionally enable IP checksum if TCP or UDP 2807 * checksum is required. Otherwise, TCP/UDP checksum 2808 * doesn't make effects. 2809 */ 2810 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) { 2811 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2812 csum_flags |= RL_TDESC_CMD_IPCSUM; 2813 if (((*m_head)->m_pkthdr.csum_flags & 2814 CSUM_TCP) != 0) 2815 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2816 if (((*m_head)->m_pkthdr.csum_flags & 2817 CSUM_UDP) != 0) 2818 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2819 } else { 2820 vlanctl |= RL_TDESC_CMD_IPCSUMV2; 2821 if (((*m_head)->m_pkthdr.csum_flags & 2822 CSUM_TCP) != 0) 2823 vlanctl |= RL_TDESC_CMD_TCPCSUMV2; 2824 if (((*m_head)->m_pkthdr.csum_flags & 2825 CSUM_UDP) != 0) 2826 vlanctl |= RL_TDESC_CMD_UDPCSUMV2; 2827 } 2828 } 2829 } 2830 2831 /* 2832 * Set up hardware VLAN tagging. Note: vlan tag info must 2833 * appear in all descriptors of a multi-descriptor 2834 * transmission attempt. 2835 */ 2836 if ((*m_head)->m_flags & M_VLANTAG) 2837 vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) | 2838 RL_TDESC_VLANCTL_TAG; 2839 2840 si = prod; 2841 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2842 desc = &sc->rl_ldata.rl_tx_list[prod]; 2843 desc->rl_vlanctl = htole32(vlanctl); 2844 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2845 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2846 cmdstat = segs[i].ds_len; 2847 if (i != 0) 2848 cmdstat |= RL_TDESC_CMD_OWN; 2849 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2850 cmdstat |= RL_TDESC_CMD_EOR; 2851 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2852 sc->rl_ldata.rl_tx_free--; 2853 } 2854 /* Update producer index. */ 2855 sc->rl_ldata.rl_tx_prodidx = prod; 2856 2857 /* Set EOF on the last descriptor. */ 2858 ei = RL_TX_DESC_PRV(sc, prod); 2859 desc = &sc->rl_ldata.rl_tx_list[ei]; 2860 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2861 2862 desc = &sc->rl_ldata.rl_tx_list[si]; 2863 /* Set SOF and transfer ownership of packet to the chip. */ 2864 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2865 2866 /* 2867 * Insure that the map for this transmission 2868 * is placed at the array index of the last descriptor 2869 * in this chain. (Swap last and first dmamaps.) 2870 */ 2871 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2872 map = txd->tx_dmamap; 2873 txd->tx_dmamap = txd_last->tx_dmamap; 2874 txd_last->tx_dmamap = map; 2875 txd_last->tx_m = *m_head; 2876 2877 return (0); 2878 } 2879 2880 static void 2881 re_start(struct ifnet *ifp) 2882 { 2883 struct rl_softc *sc; 2884 2885 sc = ifp->if_softc; 2886 RL_LOCK(sc); 2887 re_start_locked(ifp); 2888 RL_UNLOCK(sc); 2889 } 2890 2891 /* 2892 * Main transmit routine for C+ and gigE NICs. 2893 */ 2894 static void 2895 re_start_locked(struct ifnet *ifp) 2896 { 2897 struct rl_softc *sc; 2898 struct mbuf *m_head; 2899 int queued; 2900 2901 sc = ifp->if_softc; 2902 2903 #ifdef DEV_NETMAP 2904 /* XXX is this necessary ? */ 2905 if (ifp->if_capenable & IFCAP_NETMAP) { 2906 struct netmap_kring *kring = &NA(ifp)->tx_rings[0]; 2907 if (sc->rl_ldata.rl_tx_prodidx != kring->nr_hwcur) { 2908 /* kick the tx unit */ 2909 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2910 #ifdef RE_TX_MODERATION 2911 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2912 #endif 2913 sc->rl_watchdog_timer = 5; 2914 } 2915 return; 2916 } 2917 #endif /* DEV_NETMAP */ 2918 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2919 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) 2920 return; 2921 2922 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2923 sc->rl_ldata.rl_tx_free > 1;) { 2924 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2925 if (m_head == NULL) 2926 break; 2927 2928 if (re_encap(sc, &m_head) != 0) { 2929 if (m_head == NULL) 2930 break; 2931 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2932 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2933 break; 2934 } 2935 2936 /* 2937 * If there's a BPF listener, bounce a copy of this frame 2938 * to him. 2939 */ 2940 ETHER_BPF_MTAP(ifp, m_head); 2941 2942 queued++; 2943 } 2944 2945 if (queued == 0) { 2946 #ifdef RE_TX_MODERATION 2947 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2948 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2949 #endif 2950 return; 2951 } 2952 2953 /* Flush the TX descriptors */ 2954 2955 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2956 sc->rl_ldata.rl_tx_list_map, 2957 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2958 2959 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2960 2961 #ifdef RE_TX_MODERATION 2962 /* 2963 * Use the countdown timer for interrupt moderation. 2964 * 'TX done' interrupts are disabled. Instead, we reset the 2965 * countdown timer, which will begin counting until it hits 2966 * the value in the TIMERINT register, and then trigger an 2967 * interrupt. Each time we write to the TIMERCNT register, 2968 * the timer count is reset to 0. 2969 */ 2970 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2971 #endif 2972 2973 /* 2974 * Set a timeout in case the chip goes out to lunch. 2975 */ 2976 sc->rl_watchdog_timer = 5; 2977 } 2978 2979 static void 2980 re_set_jumbo(struct rl_softc *sc, int jumbo) 2981 { 2982 2983 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168E_VL) { 2984 pci_set_max_read_req(sc->rl_dev, 4096); 2985 return; 2986 } 2987 2988 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2989 if (jumbo != 0) { 2990 CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) | 2991 RL_CFG3_JUMBO_EN0); 2992 switch (sc->rl_hwrev->rl_rev) { 2993 case RL_HWREV_8168DP: 2994 break; 2995 case RL_HWREV_8168E: 2996 CSR_WRITE_1(sc, sc->rl_cfg4, 2997 CSR_READ_1(sc, sc->rl_cfg4) | 0x01); 2998 break; 2999 default: 3000 CSR_WRITE_1(sc, sc->rl_cfg4, 3001 CSR_READ_1(sc, sc->rl_cfg4) | RL_CFG4_JUMBO_EN1); 3002 } 3003 } else { 3004 CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) & 3005 ~RL_CFG3_JUMBO_EN0); 3006 switch (sc->rl_hwrev->rl_rev) { 3007 case RL_HWREV_8168DP: 3008 break; 3009 case RL_HWREV_8168E: 3010 CSR_WRITE_1(sc, sc->rl_cfg4, 3011 CSR_READ_1(sc, sc->rl_cfg4) & ~0x01); 3012 break; 3013 default: 3014 CSR_WRITE_1(sc, sc->rl_cfg4, 3015 CSR_READ_1(sc, sc->rl_cfg4) & ~RL_CFG4_JUMBO_EN1); 3016 } 3017 } 3018 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3019 3020 switch (sc->rl_hwrev->rl_rev) { 3021 case RL_HWREV_8168DP: 3022 pci_set_max_read_req(sc->rl_dev, 4096); 3023 break; 3024 default: 3025 if (jumbo != 0) 3026 pci_set_max_read_req(sc->rl_dev, 512); 3027 else 3028 pci_set_max_read_req(sc->rl_dev, 4096); 3029 } 3030 } 3031 3032 static void 3033 re_init(void *xsc) 3034 { 3035 struct rl_softc *sc = xsc; 3036 3037 RL_LOCK(sc); 3038 re_init_locked(sc); 3039 RL_UNLOCK(sc); 3040 } 3041 3042 static void 3043 re_init_locked(struct rl_softc *sc) 3044 { 3045 struct ifnet *ifp = sc->rl_ifp; 3046 struct mii_data *mii; 3047 uint32_t reg; 3048 uint16_t cfg; 3049 union { 3050 uint32_t align_dummy; 3051 u_char eaddr[ETHER_ADDR_LEN]; 3052 } eaddr; 3053 3054 RL_LOCK_ASSERT(sc); 3055 3056 mii = device_get_softc(sc->rl_miibus); 3057 3058 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3059 return; 3060 3061 /* 3062 * Cancel pending I/O and free all RX/TX buffers. 3063 */ 3064 re_stop(sc); 3065 3066 /* Put controller into known state. */ 3067 re_reset(sc); 3068 3069 /* 3070 * For C+ mode, initialize the RX descriptors and mbufs. 3071 */ 3072 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3073 if (ifp->if_mtu > RL_MTU) { 3074 if (re_jrx_list_init(sc) != 0) { 3075 device_printf(sc->rl_dev, 3076 "no memory for jumbo RX buffers\n"); 3077 re_stop(sc); 3078 return; 3079 } 3080 /* Disable checksum offloading for jumbo frames. */ 3081 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_TSO4); 3082 ifp->if_hwassist &= ~(RE_CSUM_FEATURES | CSUM_TSO); 3083 } else { 3084 if (re_rx_list_init(sc) != 0) { 3085 device_printf(sc->rl_dev, 3086 "no memory for RX buffers\n"); 3087 re_stop(sc); 3088 return; 3089 } 3090 } 3091 re_set_jumbo(sc, ifp->if_mtu > RL_MTU); 3092 } else { 3093 if (re_rx_list_init(sc) != 0) { 3094 device_printf(sc->rl_dev, "no memory for RX buffers\n"); 3095 re_stop(sc); 3096 return; 3097 } 3098 if ((sc->rl_flags & RL_FLAG_PCIE) != 0 && 3099 pci_get_device(sc->rl_dev) != RT_DEVICEID_8101E) { 3100 if (ifp->if_mtu > RL_MTU) 3101 pci_set_max_read_req(sc->rl_dev, 512); 3102 else 3103 pci_set_max_read_req(sc->rl_dev, 4096); 3104 } 3105 } 3106 re_tx_list_init(sc); 3107 3108 /* 3109 * Enable C+ RX and TX mode, as well as VLAN stripping and 3110 * RX checksum offload. We must configure the C+ register 3111 * before all others. 3112 */ 3113 cfg = RL_CPLUSCMD_PCI_MRW; 3114 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 3115 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 3116 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3117 cfg |= RL_CPLUSCMD_VLANSTRIP; 3118 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) { 3119 cfg |= RL_CPLUSCMD_MACSTAT_DIS; 3120 /* XXX magic. */ 3121 cfg |= 0x0001; 3122 } else 3123 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB; 3124 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg); 3125 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SC || 3126 sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) { 3127 reg = 0x000fff00; 3128 if ((CSR_READ_1(sc, sc->rl_cfg2) & RL_CFG2_PCI66MHZ) != 0) 3129 reg |= 0x000000ff; 3130 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) 3131 reg |= 0x00f00000; 3132 CSR_WRITE_4(sc, 0x7c, reg); 3133 /* Disable interrupt mitigation. */ 3134 CSR_WRITE_2(sc, 0xe2, 0); 3135 } 3136 /* 3137 * Disable TSO if interface MTU size is greater than MSS 3138 * allowed in controller. 3139 */ 3140 if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) { 3141 ifp->if_capenable &= ~IFCAP_TSO4; 3142 ifp->if_hwassist &= ~CSUM_TSO; 3143 } 3144 3145 /* 3146 * Init our MAC address. Even though the chipset 3147 * documentation doesn't mention it, we need to enter "Config 3148 * register write enable" mode to modify the ID registers. 3149 */ 3150 /* Copy MAC address on stack to align. */ 3151 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 3152 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 3153 CSR_WRITE_4(sc, RL_IDR0, 3154 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 3155 CSR_WRITE_4(sc, RL_IDR4, 3156 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 3157 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3158 3159 /* 3160 * Load the addresses of the RX and TX lists into the chip. 3161 */ 3162 3163 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 3164 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 3165 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 3166 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 3167 3168 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 3169 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 3170 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 3171 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 3172 3173 /* 3174 * Enable transmit and receive. 3175 */ 3176 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 3177 3178 /* 3179 * Set the initial TX configuration. 3180 */ 3181 if (sc->rl_testmode) { 3182 if (sc->rl_type == RL_8169) 3183 CSR_WRITE_4(sc, RL_TXCFG, 3184 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 3185 else 3186 CSR_WRITE_4(sc, RL_TXCFG, 3187 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 3188 } else 3189 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 3190 3191 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 3192 3193 /* 3194 * Set the initial RX configuration. 3195 */ 3196 re_set_rxmode(sc); 3197 3198 /* Configure interrupt moderation. */ 3199 if (sc->rl_type == RL_8169) { 3200 /* Magic from vendor. */ 3201 CSR_WRITE_2(sc, RL_INTRMOD, 0x5100); 3202 } 3203 3204 #ifdef DEVICE_POLLING 3205 /* 3206 * Disable interrupts if we are polling. 3207 */ 3208 if (ifp->if_capenable & IFCAP_POLLING) 3209 CSR_WRITE_2(sc, RL_IMR, 0); 3210 else /* otherwise ... */ 3211 #endif 3212 3213 /* 3214 * Enable interrupts. 3215 */ 3216 if (sc->rl_testmode) 3217 CSR_WRITE_2(sc, RL_IMR, 0); 3218 else 3219 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 3220 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 3221 3222 /* Set initial TX threshold */ 3223 sc->rl_txthresh = RL_TX_THRESH_INIT; 3224 3225 /* Start RX/TX process. */ 3226 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 3227 #ifdef notdef 3228 /* Enable receiver and transmitter. */ 3229 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 3230 #endif 3231 3232 /* 3233 * Initialize the timer interrupt register so that 3234 * a timer interrupt will be generated once the timer 3235 * reaches a certain number of ticks. The timer is 3236 * reloaded on each transmit. 3237 */ 3238 #ifdef RE_TX_MODERATION 3239 /* 3240 * Use timer interrupt register to moderate TX interrupt 3241 * moderation, which dramatically improves TX frame rate. 3242 */ 3243 if (sc->rl_type == RL_8169) 3244 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 3245 else 3246 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 3247 #else 3248 /* 3249 * Use timer interrupt register to moderate RX interrupt 3250 * moderation. 3251 */ 3252 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 && 3253 intr_filter == 0) { 3254 if (sc->rl_type == RL_8169) 3255 CSR_WRITE_4(sc, RL_TIMERINT_8169, 3256 RL_USECS(sc->rl_int_rx_mod)); 3257 } else { 3258 if (sc->rl_type == RL_8169) 3259 CSR_WRITE_4(sc, RL_TIMERINT_8169, RL_USECS(0)); 3260 } 3261 #endif 3262 3263 /* 3264 * For 8169 gigE NICs, set the max allowed RX packet 3265 * size so we can receive jumbo frames. 3266 */ 3267 if (sc->rl_type == RL_8169) { 3268 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3269 /* 3270 * For controllers that use new jumbo frame scheme, 3271 * set maximum size of jumbo frame depending on 3272 * controller revisions. 3273 */ 3274 if (ifp->if_mtu > RL_MTU) 3275 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 3276 sc->rl_hwrev->rl_max_mtu + 3277 ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN + 3278 ETHER_CRC_LEN); 3279 else 3280 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 3281 RE_RX_DESC_BUFLEN); 3282 } else if ((sc->rl_flags & RL_FLAG_PCIE) != 0 && 3283 sc->rl_hwrev->rl_max_mtu == RL_MTU) { 3284 /* RTL810x has no jumbo frame support. */ 3285 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, RE_RX_DESC_BUFLEN); 3286 } else 3287 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 3288 } 3289 3290 if (sc->rl_testmode) 3291 return; 3292 3293 CSR_WRITE_1(sc, sc->rl_cfg1, CSR_READ_1(sc, sc->rl_cfg1) | 3294 RL_CFG1_DRVLOAD); 3295 3296 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3297 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3298 3299 sc->rl_flags &= ~RL_FLAG_LINK; 3300 mii_mediachg(mii); 3301 3302 sc->rl_watchdog_timer = 0; 3303 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 3304 } 3305 3306 /* 3307 * Set media options. 3308 */ 3309 static int 3310 re_ifmedia_upd(struct ifnet *ifp) 3311 { 3312 struct rl_softc *sc; 3313 struct mii_data *mii; 3314 int error; 3315 3316 sc = ifp->if_softc; 3317 mii = device_get_softc(sc->rl_miibus); 3318 RL_LOCK(sc); 3319 error = mii_mediachg(mii); 3320 RL_UNLOCK(sc); 3321 3322 return (error); 3323 } 3324 3325 /* 3326 * Report current media status. 3327 */ 3328 static void 3329 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3330 { 3331 struct rl_softc *sc; 3332 struct mii_data *mii; 3333 3334 sc = ifp->if_softc; 3335 mii = device_get_softc(sc->rl_miibus); 3336 3337 RL_LOCK(sc); 3338 mii_pollstat(mii); 3339 ifmr->ifm_active = mii->mii_media_active; 3340 ifmr->ifm_status = mii->mii_media_status; 3341 RL_UNLOCK(sc); 3342 } 3343 3344 static int 3345 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3346 { 3347 struct rl_softc *sc = ifp->if_softc; 3348 struct ifreq *ifr = (struct ifreq *) data; 3349 struct mii_data *mii; 3350 uint32_t rev; 3351 int error = 0; 3352 3353 switch (command) { 3354 case SIOCSIFMTU: 3355 if (ifr->ifr_mtu < ETHERMIN || 3356 ifr->ifr_mtu > sc->rl_hwrev->rl_max_mtu || 3357 ((sc->rl_flags & RL_FLAG_FASTETHER) != 0 && 3358 ifr->ifr_mtu > RL_MTU)) { 3359 error = EINVAL; 3360 break; 3361 } 3362 RL_LOCK(sc); 3363 if (ifp->if_mtu != ifr->ifr_mtu) { 3364 ifp->if_mtu = ifr->ifr_mtu; 3365 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 3366 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3367 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3368 re_init_locked(sc); 3369 } 3370 if (ifp->if_mtu > RL_TSO_MTU && 3371 (ifp->if_capenable & IFCAP_TSO4) != 0) { 3372 ifp->if_capenable &= ~(IFCAP_TSO4 | 3373 IFCAP_VLAN_HWTSO); 3374 ifp->if_hwassist &= ~CSUM_TSO; 3375 } 3376 VLAN_CAPABILITIES(ifp); 3377 } 3378 RL_UNLOCK(sc); 3379 break; 3380 case SIOCSIFFLAGS: 3381 RL_LOCK(sc); 3382 if ((ifp->if_flags & IFF_UP) != 0) { 3383 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3384 if (((ifp->if_flags ^ sc->rl_if_flags) 3385 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 3386 re_set_rxmode(sc); 3387 } else 3388 re_init_locked(sc); 3389 } else { 3390 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3391 re_stop(sc); 3392 } 3393 sc->rl_if_flags = ifp->if_flags; 3394 RL_UNLOCK(sc); 3395 break; 3396 case SIOCADDMULTI: 3397 case SIOCDELMULTI: 3398 RL_LOCK(sc); 3399 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3400 re_set_rxmode(sc); 3401 RL_UNLOCK(sc); 3402 break; 3403 case SIOCGIFMEDIA: 3404 case SIOCSIFMEDIA: 3405 mii = device_get_softc(sc->rl_miibus); 3406 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3407 break; 3408 case SIOCSIFCAP: 3409 { 3410 int mask, reinit; 3411 3412 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3413 reinit = 0; 3414 #ifdef DEVICE_POLLING 3415 if (mask & IFCAP_POLLING) { 3416 if (ifr->ifr_reqcap & IFCAP_POLLING) { 3417 error = ether_poll_register(re_poll, ifp); 3418 if (error) 3419 return (error); 3420 RL_LOCK(sc); 3421 /* Disable interrupts */ 3422 CSR_WRITE_2(sc, RL_IMR, 0x0000); 3423 ifp->if_capenable |= IFCAP_POLLING; 3424 RL_UNLOCK(sc); 3425 } else { 3426 error = ether_poll_deregister(ifp); 3427 /* Enable interrupts. */ 3428 RL_LOCK(sc); 3429 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 3430 ifp->if_capenable &= ~IFCAP_POLLING; 3431 RL_UNLOCK(sc); 3432 } 3433 } 3434 #endif /* DEVICE_POLLING */ 3435 RL_LOCK(sc); 3436 if ((mask & IFCAP_TXCSUM) != 0 && 3437 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 3438 ifp->if_capenable ^= IFCAP_TXCSUM; 3439 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) { 3440 rev = sc->rl_hwrev->rl_rev; 3441 if (rev == RL_HWREV_8168C || 3442 rev == RL_HWREV_8168C_SPIN2 || 3443 rev == RL_HWREV_8168CP) 3444 ifp->if_hwassist |= CSUM_TCP | CSUM_UDP; 3445 else 3446 ifp->if_hwassist |= RE_CSUM_FEATURES; 3447 } else 3448 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 3449 reinit = 1; 3450 } 3451 if ((mask & IFCAP_RXCSUM) != 0 && 3452 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 3453 ifp->if_capenable ^= IFCAP_RXCSUM; 3454 reinit = 1; 3455 } 3456 if ((mask & IFCAP_TSO4) != 0 && 3457 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 3458 ifp->if_capenable ^= IFCAP_TSO4; 3459 if ((IFCAP_TSO4 & ifp->if_capenable) != 0) 3460 ifp->if_hwassist |= CSUM_TSO; 3461 else 3462 ifp->if_hwassist &= ~CSUM_TSO; 3463 if (ifp->if_mtu > RL_TSO_MTU && 3464 (ifp->if_capenable & IFCAP_TSO4) != 0) { 3465 ifp->if_capenable &= ~IFCAP_TSO4; 3466 ifp->if_hwassist &= ~CSUM_TSO; 3467 } 3468 } 3469 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 3470 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 3471 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 3472 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3473 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 3474 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 3475 /* TSO over VLAN requires VLAN hardware tagging. */ 3476 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 3477 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 3478 reinit = 1; 3479 } 3480 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 3481 (mask & (IFCAP_HWCSUM | IFCAP_TSO4 | 3482 IFCAP_VLAN_HWTSO)) != 0) 3483 reinit = 1; 3484 if ((mask & IFCAP_WOL) != 0 && 3485 (ifp->if_capabilities & IFCAP_WOL) != 0) { 3486 if ((mask & IFCAP_WOL_UCAST) != 0) 3487 ifp->if_capenable ^= IFCAP_WOL_UCAST; 3488 if ((mask & IFCAP_WOL_MCAST) != 0) 3489 ifp->if_capenable ^= IFCAP_WOL_MCAST; 3490 if ((mask & IFCAP_WOL_MAGIC) != 0) 3491 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 3492 } 3493 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) { 3494 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3495 re_init_locked(sc); 3496 } 3497 RL_UNLOCK(sc); 3498 VLAN_CAPABILITIES(ifp); 3499 } 3500 break; 3501 default: 3502 error = ether_ioctl(ifp, command, data); 3503 break; 3504 } 3505 3506 return (error); 3507 } 3508 3509 static void 3510 re_watchdog(struct rl_softc *sc) 3511 { 3512 struct ifnet *ifp; 3513 3514 RL_LOCK_ASSERT(sc); 3515 3516 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 3517 return; 3518 3519 ifp = sc->rl_ifp; 3520 re_txeof(sc); 3521 if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) { 3522 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 3523 "-- recovering\n"); 3524 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3525 re_start_locked(ifp); 3526 return; 3527 } 3528 3529 if_printf(ifp, "watchdog timeout\n"); 3530 ifp->if_oerrors++; 3531 3532 re_rxeof(sc, NULL); 3533 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3534 re_init_locked(sc); 3535 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3536 re_start_locked(ifp); 3537 } 3538 3539 /* 3540 * Stop the adapter and free any mbufs allocated to the 3541 * RX and TX lists. 3542 */ 3543 static void 3544 re_stop(struct rl_softc *sc) 3545 { 3546 int i; 3547 struct ifnet *ifp; 3548 struct rl_txdesc *txd; 3549 struct rl_rxdesc *rxd; 3550 3551 RL_LOCK_ASSERT(sc); 3552 3553 ifp = sc->rl_ifp; 3554 3555 sc->rl_watchdog_timer = 0; 3556 callout_stop(&sc->rl_stat_callout); 3557 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3558 3559 /* 3560 * Disable accepting frames to put RX MAC into idle state. 3561 * Otherwise it's possible to get frames while stop command 3562 * execution is in progress and controller can DMA the frame 3563 * to already freed RX buffer during that period. 3564 */ 3565 CSR_WRITE_4(sc, RL_RXCFG, CSR_READ_4(sc, RL_RXCFG) & 3566 ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_MULTI | 3567 RL_RXCFG_RX_BROAD)); 3568 3569 if ((sc->rl_flags & RL_FLAG_WAIT_TXPOLL) != 0) { 3570 for (i = RL_TIMEOUT; i > 0; i--) { 3571 if ((CSR_READ_1(sc, sc->rl_txstart) & 3572 RL_TXSTART_START) == 0) 3573 break; 3574 DELAY(20); 3575 } 3576 if (i == 0) 3577 device_printf(sc->rl_dev, 3578 "stopping TX poll timed out!\n"); 3579 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 3580 } else if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0) { 3581 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB | 3582 RL_CMD_RX_ENB); 3583 if ((sc->rl_flags & RL_FLAG_CMDSTOP_WAIT_TXQ) != 0) { 3584 for (i = RL_TIMEOUT; i > 0; i--) { 3585 if ((CSR_READ_4(sc, RL_TXCFG) & 3586 RL_TXCFG_QUEUE_EMPTY) != 0) 3587 break; 3588 DELAY(100); 3589 } 3590 if (i == 0) 3591 device_printf(sc->rl_dev, 3592 "stopping TXQ timed out!\n"); 3593 } 3594 } else 3595 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 3596 DELAY(1000); 3597 CSR_WRITE_2(sc, RL_IMR, 0x0000); 3598 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 3599 3600 if (sc->rl_head != NULL) { 3601 m_freem(sc->rl_head); 3602 sc->rl_head = sc->rl_tail = NULL; 3603 } 3604 3605 /* Free the TX list buffers. */ 3606 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 3607 txd = &sc->rl_ldata.rl_tx_desc[i]; 3608 if (txd->tx_m != NULL) { 3609 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 3610 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3611 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 3612 txd->tx_dmamap); 3613 m_freem(txd->tx_m); 3614 txd->tx_m = NULL; 3615 } 3616 } 3617 3618 /* Free the RX list buffers. */ 3619 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 3620 rxd = &sc->rl_ldata.rl_rx_desc[i]; 3621 if (rxd->rx_m != NULL) { 3622 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 3623 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3624 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 3625 rxd->rx_dmamap); 3626 m_freem(rxd->rx_m); 3627 rxd->rx_m = NULL; 3628 } 3629 } 3630 3631 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3632 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 3633 rxd = &sc->rl_ldata.rl_jrx_desc[i]; 3634 if (rxd->rx_m != NULL) { 3635 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, 3636 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3637 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, 3638 rxd->rx_dmamap); 3639 m_freem(rxd->rx_m); 3640 rxd->rx_m = NULL; 3641 } 3642 } 3643 } 3644 } 3645 3646 /* 3647 * Device suspend routine. Stop the interface and save some PCI 3648 * settings in case the BIOS doesn't restore them properly on 3649 * resume. 3650 */ 3651 static int 3652 re_suspend(device_t dev) 3653 { 3654 struct rl_softc *sc; 3655 3656 sc = device_get_softc(dev); 3657 3658 RL_LOCK(sc); 3659 re_stop(sc); 3660 re_setwol(sc); 3661 sc->suspended = 1; 3662 RL_UNLOCK(sc); 3663 3664 return (0); 3665 } 3666 3667 /* 3668 * Device resume routine. Restore some PCI settings in case the BIOS 3669 * doesn't, re-enable busmastering, and restart the interface if 3670 * appropriate. 3671 */ 3672 static int 3673 re_resume(device_t dev) 3674 { 3675 struct rl_softc *sc; 3676 struct ifnet *ifp; 3677 3678 sc = device_get_softc(dev); 3679 3680 RL_LOCK(sc); 3681 3682 ifp = sc->rl_ifp; 3683 /* Take controller out of sleep mode. */ 3684 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3685 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3686 CSR_WRITE_1(sc, RL_GPIO, 3687 CSR_READ_1(sc, RL_GPIO) | 0x01); 3688 } 3689 3690 /* 3691 * Clear WOL matching such that normal Rx filtering 3692 * wouldn't interfere with WOL patterns. 3693 */ 3694 re_clrwol(sc); 3695 3696 /* reinitialize interface if necessary */ 3697 if (ifp->if_flags & IFF_UP) 3698 re_init_locked(sc); 3699 3700 sc->suspended = 0; 3701 RL_UNLOCK(sc); 3702 3703 return (0); 3704 } 3705 3706 /* 3707 * Stop all chip I/O so that the kernel's probe routines don't 3708 * get confused by errant DMAs when rebooting. 3709 */ 3710 static int 3711 re_shutdown(device_t dev) 3712 { 3713 struct rl_softc *sc; 3714 3715 sc = device_get_softc(dev); 3716 3717 RL_LOCK(sc); 3718 re_stop(sc); 3719 /* 3720 * Mark interface as down since otherwise we will panic if 3721 * interrupt comes in later on, which can happen in some 3722 * cases. 3723 */ 3724 sc->rl_ifp->if_flags &= ~IFF_UP; 3725 re_setwol(sc); 3726 RL_UNLOCK(sc); 3727 3728 return (0); 3729 } 3730 3731 static void 3732 re_set_linkspeed(struct rl_softc *sc) 3733 { 3734 struct mii_softc *miisc; 3735 struct mii_data *mii; 3736 int aneg, i, phyno; 3737 3738 RL_LOCK_ASSERT(sc); 3739 3740 mii = device_get_softc(sc->rl_miibus); 3741 mii_pollstat(mii); 3742 aneg = 0; 3743 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 3744 (IFM_ACTIVE | IFM_AVALID)) { 3745 switch IFM_SUBTYPE(mii->mii_media_active) { 3746 case IFM_10_T: 3747 case IFM_100_TX: 3748 return; 3749 case IFM_1000_T: 3750 aneg++; 3751 break; 3752 default: 3753 break; 3754 } 3755 } 3756 miisc = LIST_FIRST(&mii->mii_phys); 3757 phyno = miisc->mii_phy; 3758 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 3759 PHY_RESET(miisc); 3760 re_miibus_writereg(sc->rl_dev, phyno, MII_100T2CR, 0); 3761 re_miibus_writereg(sc->rl_dev, phyno, 3762 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 3763 re_miibus_writereg(sc->rl_dev, phyno, 3764 MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 3765 DELAY(1000); 3766 if (aneg != 0) { 3767 /* 3768 * Poll link state until re(4) get a 10/100Mbps link. 3769 */ 3770 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 3771 mii_pollstat(mii); 3772 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 3773 == (IFM_ACTIVE | IFM_AVALID)) { 3774 switch (IFM_SUBTYPE(mii->mii_media_active)) { 3775 case IFM_10_T: 3776 case IFM_100_TX: 3777 return; 3778 default: 3779 break; 3780 } 3781 } 3782 RL_UNLOCK(sc); 3783 pause("relnk", hz); 3784 RL_LOCK(sc); 3785 } 3786 if (i == MII_ANEGTICKS_GIGE) 3787 device_printf(sc->rl_dev, 3788 "establishing a link failed, WOL may not work!"); 3789 } 3790 /* 3791 * No link, force MAC to have 100Mbps, full-duplex link. 3792 * MAC does not require reprogramming on resolved speed/duplex, 3793 * so this is just for completeness. 3794 */ 3795 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 3796 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 3797 } 3798 3799 static void 3800 re_setwol(struct rl_softc *sc) 3801 { 3802 struct ifnet *ifp; 3803 int pmc; 3804 uint16_t pmstat; 3805 uint8_t v; 3806 3807 RL_LOCK_ASSERT(sc); 3808 3809 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3810 return; 3811 3812 ifp = sc->rl_ifp; 3813 /* Put controller into sleep mode. */ 3814 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3815 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3816 CSR_WRITE_1(sc, RL_GPIO, 3817 CSR_READ_1(sc, RL_GPIO) & ~0x01); 3818 } 3819 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 3820 re_set_rxmode(sc); 3821 if ((sc->rl_flags & RL_FLAG_WOL_MANLINK) != 0) 3822 re_set_linkspeed(sc); 3823 if ((sc->rl_flags & RL_FLAG_WOLRXENB) != 0) 3824 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB); 3825 } 3826 /* Enable config register write. */ 3827 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3828 3829 /* Enable PME. */ 3830 v = CSR_READ_1(sc, sc->rl_cfg1); 3831 v &= ~RL_CFG1_PME; 3832 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3833 v |= RL_CFG1_PME; 3834 CSR_WRITE_1(sc, sc->rl_cfg1, v); 3835 3836 v = CSR_READ_1(sc, sc->rl_cfg3); 3837 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3838 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3839 v |= RL_CFG3_WOL_MAGIC; 3840 CSR_WRITE_1(sc, sc->rl_cfg3, v); 3841 3842 v = CSR_READ_1(sc, sc->rl_cfg5); 3843 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST | 3844 RL_CFG5_WOL_LANWAKE); 3845 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 3846 v |= RL_CFG5_WOL_UCAST; 3847 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 3848 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 3849 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3850 v |= RL_CFG5_WOL_LANWAKE; 3851 CSR_WRITE_1(sc, sc->rl_cfg5, v); 3852 3853 /* Config register write done. */ 3854 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3855 3856 if ((ifp->if_capenable & IFCAP_WOL) == 0 && 3857 (sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) 3858 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) & ~0x80); 3859 /* 3860 * It seems that hardware resets its link speed to 100Mbps in 3861 * power down mode so switching to 100Mbps in driver is not 3862 * needed. 3863 */ 3864 3865 /* Request PME if WOL is requested. */ 3866 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 3867 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3868 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3869 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3870 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 3871 } 3872 3873 static void 3874 re_clrwol(struct rl_softc *sc) 3875 { 3876 int pmc; 3877 uint8_t v; 3878 3879 RL_LOCK_ASSERT(sc); 3880 3881 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3882 return; 3883 3884 /* Enable config register write. */ 3885 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3886 3887 v = CSR_READ_1(sc, sc->rl_cfg3); 3888 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3889 CSR_WRITE_1(sc, sc->rl_cfg3, v); 3890 3891 /* Config register write done. */ 3892 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3893 3894 v = CSR_READ_1(sc, sc->rl_cfg5); 3895 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3896 v &= ~RL_CFG5_WOL_LANWAKE; 3897 CSR_WRITE_1(sc, sc->rl_cfg5, v); 3898 } 3899 3900 static void 3901 re_add_sysctls(struct rl_softc *sc) 3902 { 3903 struct sysctl_ctx_list *ctx; 3904 struct sysctl_oid_list *children; 3905 int error; 3906 3907 ctx = device_get_sysctl_ctx(sc->rl_dev); 3908 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev)); 3909 3910 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "stats", 3911 CTLTYPE_INT | CTLFLAG_RW, sc, 0, re_sysctl_stats, "I", 3912 "Statistics Information"); 3913 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) 3914 return; 3915 3916 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "int_rx_mod", 3917 CTLTYPE_INT | CTLFLAG_RW, &sc->rl_int_rx_mod, 0, 3918 sysctl_hw_re_int_mod, "I", "re RX interrupt moderation"); 3919 /* Pull in device tunables. */ 3920 sc->rl_int_rx_mod = RL_TIMER_DEFAULT; 3921 error = resource_int_value(device_get_name(sc->rl_dev), 3922 device_get_unit(sc->rl_dev), "int_rx_mod", &sc->rl_int_rx_mod); 3923 if (error == 0) { 3924 if (sc->rl_int_rx_mod < RL_TIMER_MIN || 3925 sc->rl_int_rx_mod > RL_TIMER_MAX) { 3926 device_printf(sc->rl_dev, "int_rx_mod value out of " 3927 "range; using default: %d\n", 3928 RL_TIMER_DEFAULT); 3929 sc->rl_int_rx_mod = RL_TIMER_DEFAULT; 3930 } 3931 } 3932 3933 } 3934 3935 static int 3936 re_sysctl_stats(SYSCTL_HANDLER_ARGS) 3937 { 3938 struct rl_softc *sc; 3939 struct rl_stats *stats; 3940 int error, i, result; 3941 3942 result = -1; 3943 error = sysctl_handle_int(oidp, &result, 0, req); 3944 if (error || req->newptr == NULL) 3945 return (error); 3946 3947 if (result == 1) { 3948 sc = (struct rl_softc *)arg1; 3949 RL_LOCK(sc); 3950 if ((sc->rl_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 3951 RL_UNLOCK(sc); 3952 goto done; 3953 } 3954 bus_dmamap_sync(sc->rl_ldata.rl_stag, 3955 sc->rl_ldata.rl_smap, BUS_DMASYNC_PREREAD); 3956 CSR_WRITE_4(sc, RL_DUMPSTATS_HI, 3957 RL_ADDR_HI(sc->rl_ldata.rl_stats_addr)); 3958 CSR_WRITE_4(sc, RL_DUMPSTATS_LO, 3959 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr)); 3960 CSR_WRITE_4(sc, RL_DUMPSTATS_LO, 3961 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr | 3962 RL_DUMPSTATS_START)); 3963 for (i = RL_TIMEOUT; i > 0; i--) { 3964 if ((CSR_READ_4(sc, RL_DUMPSTATS_LO) & 3965 RL_DUMPSTATS_START) == 0) 3966 break; 3967 DELAY(1000); 3968 } 3969 bus_dmamap_sync(sc->rl_ldata.rl_stag, 3970 sc->rl_ldata.rl_smap, BUS_DMASYNC_POSTREAD); 3971 RL_UNLOCK(sc); 3972 if (i == 0) { 3973 device_printf(sc->rl_dev, 3974 "DUMP statistics request timed out\n"); 3975 return (ETIMEDOUT); 3976 } 3977 done: 3978 stats = sc->rl_ldata.rl_stats; 3979 printf("%s statistics:\n", device_get_nameunit(sc->rl_dev)); 3980 printf("Tx frames : %ju\n", 3981 (uintmax_t)le64toh(stats->rl_tx_pkts)); 3982 printf("Rx frames : %ju\n", 3983 (uintmax_t)le64toh(stats->rl_rx_pkts)); 3984 printf("Tx errors : %ju\n", 3985 (uintmax_t)le64toh(stats->rl_tx_errs)); 3986 printf("Rx errors : %u\n", 3987 le32toh(stats->rl_rx_errs)); 3988 printf("Rx missed frames : %u\n", 3989 (uint32_t)le16toh(stats->rl_missed_pkts)); 3990 printf("Rx frame alignment errs : %u\n", 3991 (uint32_t)le16toh(stats->rl_rx_framealign_errs)); 3992 printf("Tx single collisions : %u\n", 3993 le32toh(stats->rl_tx_onecoll)); 3994 printf("Tx multiple collisions : %u\n", 3995 le32toh(stats->rl_tx_multicolls)); 3996 printf("Rx unicast frames : %ju\n", 3997 (uintmax_t)le64toh(stats->rl_rx_ucasts)); 3998 printf("Rx broadcast frames : %ju\n", 3999 (uintmax_t)le64toh(stats->rl_rx_bcasts)); 4000 printf("Rx multicast frames : %u\n", 4001 le32toh(stats->rl_rx_mcasts)); 4002 printf("Tx aborts : %u\n", 4003 (uint32_t)le16toh(stats->rl_tx_aborts)); 4004 printf("Tx underruns : %u\n", 4005 (uint32_t)le16toh(stats->rl_rx_underruns)); 4006 } 4007 4008 return (error); 4009 } 4010 4011 static int 4012 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4013 { 4014 int error, value; 4015 4016 if (arg1 == NULL) 4017 return (EINVAL); 4018 value = *(int *)arg1; 4019 error = sysctl_handle_int(oidp, &value, 0, req); 4020 if (error || req->newptr == NULL) 4021 return (error); 4022 if (value < low || value > high) 4023 return (EINVAL); 4024 *(int *)arg1 = value; 4025 4026 return (0); 4027 } 4028 4029 static int 4030 sysctl_hw_re_int_mod(SYSCTL_HANDLER_ARGS) 4031 { 4032 4033 return (sysctl_int_range(oidp, arg1, arg2, req, RL_TIMER_MIN, 4034 RL_TIMER_MAX)); 4035 } 4036