1 /*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44 /* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111 #ifdef HAVE_KERNEL_OPTION_HEADERS 112 #include "opt_device_polling.h" 113 #endif 114 115 #include <sys/param.h> 116 #include <sys/endian.h> 117 #include <sys/systm.h> 118 #include <sys/sockio.h> 119 #include <sys/mbuf.h> 120 #include <sys/malloc.h> 121 #include <sys/module.h> 122 #include <sys/kernel.h> 123 #include <sys/socket.h> 124 #include <sys/lock.h> 125 #include <sys/mutex.h> 126 #include <sys/taskqueue.h> 127 128 #include <net/if.h> 129 #include <net/if_arp.h> 130 #include <net/ethernet.h> 131 #include <net/if_dl.h> 132 #include <net/if_media.h> 133 #include <net/if_types.h> 134 #include <net/if_vlan_var.h> 135 136 #include <net/bpf.h> 137 138 #include <machine/bus.h> 139 #include <machine/resource.h> 140 #include <sys/bus.h> 141 #include <sys/rman.h> 142 143 #include <dev/mii/mii.h> 144 #include <dev/mii/miivar.h> 145 146 #include <dev/pci/pcireg.h> 147 #include <dev/pci/pcivar.h> 148 149 #include <pci/if_rlreg.h> 150 151 MODULE_DEPEND(re, pci, 1, 1, 1); 152 MODULE_DEPEND(re, ether, 1, 1, 1); 153 MODULE_DEPEND(re, miibus, 1, 1, 1); 154 155 /* "device miibus" required. See GENERIC if you get errors here. */ 156 #include "miibus_if.h" 157 158 /* 159 * Default to using PIO access for this driver. 160 */ 161 #define RE_USEIOSPACE 162 163 /* Tunables. */ 164 static int msi_disable = 0; 165 TUNABLE_INT("hw.re.msi_disable", &msi_disable); 166 167 #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 168 169 /* 170 * Various supported device vendors/types and their names. 171 */ 172 static struct rl_type re_devs[] = { 173 { DLINK_VENDORID, DLINK_DEVICEID_528T, RL_HWREV_8169S, 174 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 175 { DLINK_VENDORID, DLINK_DEVICEID_528T, RL_HWREV_8169_8110SB, 176 "D-Link DGE-528(T) Rev.B1 Gigabit Ethernet Adapter" }, 177 { RT_VENDORID, RT_DEVICEID_8139, RL_HWREV_8139CPLUS, 178 "RealTek 8139C+ 10/100BaseTX" }, 179 { RT_VENDORID, RT_DEVICEID_8101E, RL_HWREV_8101E, 180 "RealTek 8101E PCIe 10/100baseTX" }, 181 { RT_VENDORID, RT_DEVICEID_8168, RL_HWREV_8168_SPIN1, 182 "RealTek 8168/8111B PCIe Gigabit Ethernet" }, 183 { RT_VENDORID, RT_DEVICEID_8168, RL_HWREV_8168_SPIN2, 184 "RealTek 8168/8111B PCIe Gigabit Ethernet" }, 185 { RT_VENDORID, RT_DEVICEID_8168, RL_HWREV_8168_SPIN3, 186 "RealTek 8168/8111B PCIe Gigabit Ethernet" }, 187 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169, 188 "RealTek 8169 Gigabit Ethernet" }, 189 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169S, 190 "RealTek 8169S Single-chip Gigabit Ethernet" }, 191 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169_8110SB, 192 "RealTek 8169SB/8110SB Single-chip Gigabit Ethernet" }, 193 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169_8110SC, 194 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 195 { RT_VENDORID, RT_DEVICEID_8169SC, RL_HWREV_8169_8110SC, 196 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 197 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8110S, 198 "RealTek 8110S Single-chip Gigabit Ethernet" }, 199 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, RL_HWREV_8169S, 200 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 201 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, RL_HWREV_8169S, 202 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 203 { USR_VENDORID, USR_DEVICEID_997902, RL_HWREV_8169S, 204 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 205 }; 206 207 static struct rl_hwrev re_hwrevs[] = { 208 { RL_HWREV_8139, RL_8139, "" }, 209 { RL_HWREV_8139A, RL_8139, "A" }, 210 { RL_HWREV_8139AG, RL_8139, "A-G" }, 211 { RL_HWREV_8139B, RL_8139, "B" }, 212 { RL_HWREV_8130, RL_8139, "8130" }, 213 { RL_HWREV_8139C, RL_8139, "C" }, 214 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 215 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 216 { RL_HWREV_8168_SPIN1, RL_8169, "8168"}, 217 { RL_HWREV_8169, RL_8169, "8169"}, 218 { RL_HWREV_8169S, RL_8169, "8169S"}, 219 { RL_HWREV_8110S, RL_8169, "8110S"}, 220 { RL_HWREV_8169_8110SB, RL_8169, "8169SB"}, 221 { RL_HWREV_8169_8110SC, RL_8169, "8169SC"}, 222 { RL_HWREV_8100, RL_8139, "8100"}, 223 { RL_HWREV_8101, RL_8139, "8101"}, 224 { RL_HWREV_8100E, RL_8169, "8100E"}, 225 { RL_HWREV_8101E, RL_8169, "8101E"}, 226 { RL_HWREV_8168_SPIN2, RL_8169, "8168"}, 227 { RL_HWREV_8168_SPIN3, RL_8169, "8168"}, 228 { 0, 0, NULL } 229 }; 230 231 static int re_probe (device_t); 232 static int re_attach (device_t); 233 static int re_detach (device_t); 234 235 static int re_encap (struct rl_softc *, struct mbuf **); 236 237 static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 238 static int re_allocmem (device_t, struct rl_softc *); 239 static __inline void re_discard_rxbuf 240 (struct rl_softc *, int); 241 static int re_newbuf (struct rl_softc *, int); 242 static int re_rx_list_init (struct rl_softc *); 243 static int re_tx_list_init (struct rl_softc *); 244 #ifdef RE_FIXUP_RX 245 static __inline void re_fixup_rx 246 (struct mbuf *); 247 #endif 248 static int re_rxeof (struct rl_softc *); 249 static void re_txeof (struct rl_softc *); 250 #ifdef DEVICE_POLLING 251 static void re_poll (struct ifnet *, enum poll_cmd, int); 252 static void re_poll_locked (struct ifnet *, enum poll_cmd, int); 253 #endif 254 static int re_intr (void *); 255 static void re_tick (void *); 256 static void re_tx_task (void *, int); 257 static void re_int_task (void *, int); 258 static void re_start (struct ifnet *); 259 static int re_ioctl (struct ifnet *, u_long, caddr_t); 260 static void re_init (void *); 261 static void re_init_locked (struct rl_softc *); 262 static void re_stop (struct rl_softc *); 263 static void re_watchdog (struct rl_softc *); 264 static int re_suspend (device_t); 265 static int re_resume (device_t); 266 static int re_shutdown (device_t); 267 static int re_ifmedia_upd (struct ifnet *); 268 static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 269 270 static void re_eeprom_putbyte (struct rl_softc *, int); 271 static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 272 static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 273 static int re_gmii_readreg (device_t, int, int); 274 static int re_gmii_writereg (device_t, int, int, int); 275 276 static int re_miibus_readreg (device_t, int, int); 277 static int re_miibus_writereg (device_t, int, int, int); 278 static void re_miibus_statchg (device_t); 279 280 static void re_setmulti (struct rl_softc *); 281 static void re_reset (struct rl_softc *); 282 static void re_setwol (struct rl_softc *); 283 static void re_clrwol (struct rl_softc *); 284 285 #ifdef RE_DIAG 286 static int re_diag (struct rl_softc *); 287 #endif 288 289 #ifdef RE_USEIOSPACE 290 #define RL_RES SYS_RES_IOPORT 291 #define RL_RID RL_PCI_LOIO 292 #else 293 #define RL_RES SYS_RES_MEMORY 294 #define RL_RID RL_PCI_LOMEM 295 #endif 296 297 static device_method_t re_methods[] = { 298 /* Device interface */ 299 DEVMETHOD(device_probe, re_probe), 300 DEVMETHOD(device_attach, re_attach), 301 DEVMETHOD(device_detach, re_detach), 302 DEVMETHOD(device_suspend, re_suspend), 303 DEVMETHOD(device_resume, re_resume), 304 DEVMETHOD(device_shutdown, re_shutdown), 305 306 /* bus interface */ 307 DEVMETHOD(bus_print_child, bus_generic_print_child), 308 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 309 310 /* MII interface */ 311 DEVMETHOD(miibus_readreg, re_miibus_readreg), 312 DEVMETHOD(miibus_writereg, re_miibus_writereg), 313 DEVMETHOD(miibus_statchg, re_miibus_statchg), 314 315 { 0, 0 } 316 }; 317 318 static driver_t re_driver = { 319 "re", 320 re_methods, 321 sizeof(struct rl_softc) 322 }; 323 324 static devclass_t re_devclass; 325 326 DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 327 DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0); 328 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 329 330 #define EE_SET(x) \ 331 CSR_WRITE_1(sc, RL_EECMD, \ 332 CSR_READ_1(sc, RL_EECMD) | x) 333 334 #define EE_CLR(x) \ 335 CSR_WRITE_1(sc, RL_EECMD, \ 336 CSR_READ_1(sc, RL_EECMD) & ~x) 337 338 /* 339 * Send a read command and address to the EEPROM, check for ACK. 340 */ 341 static void 342 re_eeprom_putbyte(sc, addr) 343 struct rl_softc *sc; 344 int addr; 345 { 346 register int d, i; 347 348 d = addr | (RL_9346_READ << sc->rl_eewidth); 349 350 /* 351 * Feed in each bit and strobe the clock. 352 */ 353 354 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 355 if (d & i) { 356 EE_SET(RL_EE_DATAIN); 357 } else { 358 EE_CLR(RL_EE_DATAIN); 359 } 360 DELAY(100); 361 EE_SET(RL_EE_CLK); 362 DELAY(150); 363 EE_CLR(RL_EE_CLK); 364 DELAY(100); 365 } 366 367 return; 368 } 369 370 /* 371 * Read a word of data stored in the EEPROM at address 'addr.' 372 */ 373 static void 374 re_eeprom_getword(sc, addr, dest) 375 struct rl_softc *sc; 376 int addr; 377 u_int16_t *dest; 378 { 379 register int i; 380 u_int16_t word = 0; 381 382 /* 383 * Send address of word we want to read. 384 */ 385 re_eeprom_putbyte(sc, addr); 386 387 /* 388 * Start reading bits from EEPROM. 389 */ 390 for (i = 0x8000; i; i >>= 1) { 391 EE_SET(RL_EE_CLK); 392 DELAY(100); 393 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 394 word |= i; 395 EE_CLR(RL_EE_CLK); 396 DELAY(100); 397 } 398 399 *dest = word; 400 401 return; 402 } 403 404 /* 405 * Read a sequence of words from the EEPROM. 406 */ 407 static void 408 re_read_eeprom(sc, dest, off, cnt) 409 struct rl_softc *sc; 410 caddr_t dest; 411 int off; 412 int cnt; 413 { 414 int i; 415 u_int16_t word = 0, *ptr; 416 417 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 418 419 DELAY(100); 420 421 for (i = 0; i < cnt; i++) { 422 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 423 re_eeprom_getword(sc, off + i, &word); 424 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 425 ptr = (u_int16_t *)(dest + (i * 2)); 426 *ptr = word; 427 } 428 429 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 430 431 return; 432 } 433 434 static int 435 re_gmii_readreg(dev, phy, reg) 436 device_t dev; 437 int phy, reg; 438 { 439 struct rl_softc *sc; 440 u_int32_t rval; 441 int i; 442 443 if (phy != 1) 444 return (0); 445 446 sc = device_get_softc(dev); 447 448 /* Let the rgephy driver read the GMEDIASTAT register */ 449 450 if (reg == RL_GMEDIASTAT) { 451 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 452 return (rval); 453 } 454 455 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 456 DELAY(1000); 457 458 for (i = 0; i < RL_TIMEOUT; i++) { 459 rval = CSR_READ_4(sc, RL_PHYAR); 460 if (rval & RL_PHYAR_BUSY) 461 break; 462 DELAY(100); 463 } 464 465 if (i == RL_TIMEOUT) { 466 device_printf(sc->rl_dev, "PHY read failed\n"); 467 return (0); 468 } 469 470 return (rval & RL_PHYAR_PHYDATA); 471 } 472 473 static int 474 re_gmii_writereg(dev, phy, reg, data) 475 device_t dev; 476 int phy, reg, data; 477 { 478 struct rl_softc *sc; 479 u_int32_t rval; 480 int i; 481 482 sc = device_get_softc(dev); 483 484 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 485 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 486 DELAY(1000); 487 488 for (i = 0; i < RL_TIMEOUT; i++) { 489 rval = CSR_READ_4(sc, RL_PHYAR); 490 if (!(rval & RL_PHYAR_BUSY)) 491 break; 492 DELAY(100); 493 } 494 495 if (i == RL_TIMEOUT) { 496 device_printf(sc->rl_dev, "PHY write failed\n"); 497 return (0); 498 } 499 500 return (0); 501 } 502 503 static int 504 re_miibus_readreg(dev, phy, reg) 505 device_t dev; 506 int phy, reg; 507 { 508 struct rl_softc *sc; 509 u_int16_t rval = 0; 510 u_int16_t re8139_reg = 0; 511 512 sc = device_get_softc(dev); 513 514 if (sc->rl_type == RL_8169) { 515 rval = re_gmii_readreg(dev, phy, reg); 516 return (rval); 517 } 518 519 /* Pretend the internal PHY is only at address 0 */ 520 if (phy) { 521 return (0); 522 } 523 switch (reg) { 524 case MII_BMCR: 525 re8139_reg = RL_BMCR; 526 break; 527 case MII_BMSR: 528 re8139_reg = RL_BMSR; 529 break; 530 case MII_ANAR: 531 re8139_reg = RL_ANAR; 532 break; 533 case MII_ANER: 534 re8139_reg = RL_ANER; 535 break; 536 case MII_ANLPAR: 537 re8139_reg = RL_LPAR; 538 break; 539 case MII_PHYIDR1: 540 case MII_PHYIDR2: 541 return (0); 542 /* 543 * Allow the rlphy driver to read the media status 544 * register. If we have a link partner which does not 545 * support NWAY, this is the register which will tell 546 * us the results of parallel detection. 547 */ 548 case RL_MEDIASTAT: 549 rval = CSR_READ_1(sc, RL_MEDIASTAT); 550 return (rval); 551 default: 552 device_printf(sc->rl_dev, "bad phy register\n"); 553 return (0); 554 } 555 rval = CSR_READ_2(sc, re8139_reg); 556 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 557 /* 8139C+ has different bit layout. */ 558 rval &= ~(BMCR_LOOP | BMCR_ISO); 559 } 560 return (rval); 561 } 562 563 static int 564 re_miibus_writereg(dev, phy, reg, data) 565 device_t dev; 566 int phy, reg, data; 567 { 568 struct rl_softc *sc; 569 u_int16_t re8139_reg = 0; 570 int rval = 0; 571 572 sc = device_get_softc(dev); 573 574 if (sc->rl_type == RL_8169) { 575 rval = re_gmii_writereg(dev, phy, reg, data); 576 return (rval); 577 } 578 579 /* Pretend the internal PHY is only at address 0 */ 580 if (phy) 581 return (0); 582 583 switch (reg) { 584 case MII_BMCR: 585 re8139_reg = RL_BMCR; 586 if (sc->rl_type == RL_8139CPLUS) { 587 /* 8139C+ has different bit layout. */ 588 data &= ~(BMCR_LOOP | BMCR_ISO); 589 } 590 break; 591 case MII_BMSR: 592 re8139_reg = RL_BMSR; 593 break; 594 case MII_ANAR: 595 re8139_reg = RL_ANAR; 596 break; 597 case MII_ANER: 598 re8139_reg = RL_ANER; 599 break; 600 case MII_ANLPAR: 601 re8139_reg = RL_LPAR; 602 break; 603 case MII_PHYIDR1: 604 case MII_PHYIDR2: 605 return (0); 606 break; 607 default: 608 device_printf(sc->rl_dev, "bad phy register\n"); 609 return (0); 610 } 611 CSR_WRITE_2(sc, re8139_reg, data); 612 return (0); 613 } 614 615 static void 616 re_miibus_statchg(dev) 617 device_t dev; 618 { 619 620 } 621 622 /* 623 * Program the 64-bit multicast hash filter. 624 */ 625 static void 626 re_setmulti(sc) 627 struct rl_softc *sc; 628 { 629 struct ifnet *ifp; 630 int h = 0; 631 u_int32_t hashes[2] = { 0, 0 }; 632 struct ifmultiaddr *ifma; 633 u_int32_t rxfilt; 634 int mcnt = 0; 635 u_int32_t hwrev; 636 637 RL_LOCK_ASSERT(sc); 638 639 ifp = sc->rl_ifp; 640 641 642 rxfilt = CSR_READ_4(sc, RL_RXCFG); 643 rxfilt &= ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_MULTI); 644 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 645 if (ifp->if_flags & IFF_PROMISC) 646 rxfilt |= RL_RXCFG_RX_ALLPHYS; 647 /* 648 * Unlike other hardwares, we have to explicitly set 649 * RL_RXCFG_RX_MULTI to receive multicast frames in 650 * promiscuous mode. 651 */ 652 rxfilt |= RL_RXCFG_RX_MULTI; 653 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 654 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 655 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 656 return; 657 } 658 659 /* first, zot all the existing hash bits */ 660 CSR_WRITE_4(sc, RL_MAR0, 0); 661 CSR_WRITE_4(sc, RL_MAR4, 0); 662 663 /* now program new ones */ 664 IF_ADDR_LOCK(ifp); 665 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 666 if (ifma->ifma_addr->sa_family != AF_LINK) 667 continue; 668 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 669 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 670 if (h < 32) 671 hashes[0] |= (1 << h); 672 else 673 hashes[1] |= (1 << (h - 32)); 674 mcnt++; 675 } 676 IF_ADDR_UNLOCK(ifp); 677 678 if (mcnt) 679 rxfilt |= RL_RXCFG_RX_MULTI; 680 else 681 rxfilt &= ~RL_RXCFG_RX_MULTI; 682 683 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 684 685 /* 686 * For some unfathomable reason, RealTek decided to reverse 687 * the order of the multicast hash registers in the PCI Express 688 * parts. This means we have to write the hash pattern in reverse 689 * order for those devices. 690 */ 691 692 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 693 694 switch (hwrev) { 695 case RL_HWREV_8100E: 696 case RL_HWREV_8101E: 697 case RL_HWREV_8168_SPIN1: 698 case RL_HWREV_8168_SPIN2: 699 case RL_HWREV_8168_SPIN3: 700 CSR_WRITE_4(sc, RL_MAR0, bswap32(hashes[1])); 701 CSR_WRITE_4(sc, RL_MAR4, bswap32(hashes[0])); 702 break; 703 default: 704 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 705 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 706 break; 707 } 708 } 709 710 static void 711 re_reset(sc) 712 struct rl_softc *sc; 713 { 714 register int i; 715 716 RL_LOCK_ASSERT(sc); 717 718 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 719 720 for (i = 0; i < RL_TIMEOUT; i++) { 721 DELAY(10); 722 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 723 break; 724 } 725 if (i == RL_TIMEOUT) 726 device_printf(sc->rl_dev, "reset never completed!\n"); 727 728 CSR_WRITE_1(sc, 0x82, 1); 729 } 730 731 #ifdef RE_DIAG 732 733 /* 734 * The following routine is designed to test for a defect on some 735 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 736 * lines connected to the bus, however for a 32-bit only card, they 737 * should be pulled high. The result of this defect is that the 738 * NIC will not work right if you plug it into a 64-bit slot: DMA 739 * operations will be done with 64-bit transfers, which will fail 740 * because the 64-bit data lines aren't connected. 741 * 742 * There's no way to work around this (short of talking a soldering 743 * iron to the board), however we can detect it. The method we use 744 * here is to put the NIC into digital loopback mode, set the receiver 745 * to promiscuous mode, and then try to send a frame. We then compare 746 * the frame data we sent to what was received. If the data matches, 747 * then the NIC is working correctly, otherwise we know the user has 748 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 749 * slot. In the latter case, there's no way the NIC can work correctly, 750 * so we print out a message on the console and abort the device attach. 751 */ 752 753 static int 754 re_diag(sc) 755 struct rl_softc *sc; 756 { 757 struct ifnet *ifp = sc->rl_ifp; 758 struct mbuf *m0; 759 struct ether_header *eh; 760 struct rl_desc *cur_rx; 761 u_int16_t status; 762 u_int32_t rxstat; 763 int total_len, i, error = 0, phyaddr; 764 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 765 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 766 767 /* Allocate a single mbuf */ 768 MGETHDR(m0, M_DONTWAIT, MT_DATA); 769 if (m0 == NULL) 770 return (ENOBUFS); 771 772 RL_LOCK(sc); 773 774 /* 775 * Initialize the NIC in test mode. This sets the chip up 776 * so that it can send and receive frames, but performs the 777 * following special functions: 778 * - Puts receiver in promiscuous mode 779 * - Enables digital loopback mode 780 * - Leaves interrupts turned off 781 */ 782 783 ifp->if_flags |= IFF_PROMISC; 784 sc->rl_testmode = 1; 785 re_reset(sc); 786 re_init_locked(sc); 787 sc->rl_link = 1; 788 if (sc->rl_type == RL_8169) 789 phyaddr = 1; 790 else 791 phyaddr = 0; 792 793 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 794 for (i = 0; i < RL_TIMEOUT; i++) { 795 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 796 if (!(status & BMCR_RESET)) 797 break; 798 } 799 800 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 801 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 802 803 DELAY(100000); 804 805 /* Put some data in the mbuf */ 806 807 eh = mtod(m0, struct ether_header *); 808 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 809 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 810 eh->ether_type = htons(ETHERTYPE_IP); 811 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 812 813 /* 814 * Queue the packet, start transmission. 815 * Note: IF_HANDOFF() ultimately calls re_start() for us. 816 */ 817 818 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 819 RL_UNLOCK(sc); 820 /* XXX: re_diag must not be called when in ALTQ mode */ 821 IF_HANDOFF(&ifp->if_snd, m0, ifp); 822 RL_LOCK(sc); 823 m0 = NULL; 824 825 /* Wait for it to propagate through the chip */ 826 827 DELAY(100000); 828 for (i = 0; i < RL_TIMEOUT; i++) { 829 status = CSR_READ_2(sc, RL_ISR); 830 CSR_WRITE_2(sc, RL_ISR, status); 831 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 832 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 833 break; 834 DELAY(10); 835 } 836 837 if (i == RL_TIMEOUT) { 838 device_printf(sc->rl_dev, 839 "diagnostic failed, failed to receive packet in" 840 " loopback mode\n"); 841 error = EIO; 842 goto done; 843 } 844 845 /* 846 * The packet should have been dumped into the first 847 * entry in the RX DMA ring. Grab it from there. 848 */ 849 850 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 851 sc->rl_ldata.rl_rx_list_map, 852 BUS_DMASYNC_POSTREAD); 853 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 854 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 855 BUS_DMASYNC_POSTREAD); 856 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 857 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 858 859 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 860 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 861 eh = mtod(m0, struct ether_header *); 862 863 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 864 total_len = RL_RXBYTES(cur_rx); 865 rxstat = le32toh(cur_rx->rl_cmdstat); 866 867 if (total_len != ETHER_MIN_LEN) { 868 device_printf(sc->rl_dev, 869 "diagnostic failed, received short packet\n"); 870 error = EIO; 871 goto done; 872 } 873 874 /* Test that the received packet data matches what we sent. */ 875 876 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 877 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 878 ntohs(eh->ether_type) != ETHERTYPE_IP) { 879 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 880 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 881 dst, ":", src, ":", ETHERTYPE_IP); 882 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 883 eh->ether_dhost, ":", eh->ether_shost, ":", 884 ntohs(eh->ether_type)); 885 device_printf(sc->rl_dev, "You may have a defective 32-bit " 886 "NIC plugged into a 64-bit PCI slot.\n"); 887 device_printf(sc->rl_dev, "Please re-install the NIC in a " 888 "32-bit slot for proper operation.\n"); 889 device_printf(sc->rl_dev, "Read the re(4) man page for more " 890 "details.\n"); 891 error = EIO; 892 } 893 894 done: 895 /* Turn interface off, release resources */ 896 897 sc->rl_testmode = 0; 898 sc->rl_link = 0; 899 ifp->if_flags &= ~IFF_PROMISC; 900 re_stop(sc); 901 if (m0 != NULL) 902 m_freem(m0); 903 904 RL_UNLOCK(sc); 905 906 return (error); 907 } 908 909 #endif 910 911 /* 912 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 913 * IDs against our list and return a device name if we find a match. 914 */ 915 static int 916 re_probe(dev) 917 device_t dev; 918 { 919 struct rl_type *t; 920 uint16_t devid, vendor; 921 uint16_t revid, sdevid; 922 int i; 923 924 vendor = pci_get_vendor(dev); 925 devid = pci_get_device(dev); 926 revid = pci_get_revid(dev); 927 sdevid = pci_get_subdevice(dev); 928 929 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 930 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 931 /* 932 * Only attach to rev. 3 of the Linksys EG1032 adapter. 933 * Rev. 2 is supported by sk(4). 934 */ 935 return (ENXIO); 936 } 937 } 938 939 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 940 if (revid != 0x20) { 941 /* 8139, let rl(4) take care of this device. */ 942 return (ENXIO); 943 } 944 } 945 946 t = re_devs; 947 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) { 948 if (vendor == t->rl_vid && devid == t->rl_did) { 949 device_set_desc(dev, t->rl_name); 950 return (BUS_PROBE_DEFAULT); 951 } 952 } 953 954 return (ENXIO); 955 } 956 957 /* 958 * Map a single buffer address. 959 */ 960 961 static void 962 re_dma_map_addr(arg, segs, nseg, error) 963 void *arg; 964 bus_dma_segment_t *segs; 965 int nseg; 966 int error; 967 { 968 bus_addr_t *addr; 969 970 if (error) 971 return; 972 973 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 974 addr = arg; 975 *addr = segs->ds_addr; 976 } 977 978 static int 979 re_allocmem(dev, sc) 980 device_t dev; 981 struct rl_softc *sc; 982 { 983 bus_size_t rx_list_size, tx_list_size; 984 int error; 985 int i; 986 987 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 988 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 989 990 /* 991 * Allocate the parent bus DMA tag appropriate for PCI. 992 */ 993 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 994 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 995 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 996 NULL, NULL, &sc->rl_parent_tag); 997 if (error) { 998 device_printf(dev, "could not allocate parent DMA tag\n"); 999 return (error); 1000 } 1001 1002 /* 1003 * Allocate map for TX mbufs. 1004 */ 1005 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 1006 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1007 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 1008 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 1009 if (error) { 1010 device_printf(dev, "could not allocate TX DMA tag\n"); 1011 return (error); 1012 } 1013 1014 /* 1015 * Allocate map for RX mbufs. 1016 */ 1017 1018 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 1019 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1020 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 1021 if (error) { 1022 device_printf(dev, "could not allocate RX DMA tag\n"); 1023 return (error); 1024 } 1025 1026 /* 1027 * Allocate map for TX descriptor list. 1028 */ 1029 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1030 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1031 NULL, tx_list_size, 1, tx_list_size, 0, 1032 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1033 if (error) { 1034 device_printf(dev, "could not allocate TX DMA ring tag\n"); 1035 return (error); 1036 } 1037 1038 /* Allocate DMA'able memory for the TX ring */ 1039 1040 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1041 (void **)&sc->rl_ldata.rl_tx_list, 1042 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1043 &sc->rl_ldata.rl_tx_list_map); 1044 if (error) { 1045 device_printf(dev, "could not allocate TX DMA ring\n"); 1046 return (error); 1047 } 1048 1049 /* Load the map for the TX ring. */ 1050 1051 sc->rl_ldata.rl_tx_list_addr = 0; 1052 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1053 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1054 tx_list_size, re_dma_map_addr, 1055 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1056 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 1057 device_printf(dev, "could not load TX DMA ring\n"); 1058 return (ENOMEM); 1059 } 1060 1061 /* Create DMA maps for TX buffers */ 1062 1063 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1064 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1065 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1066 if (error) { 1067 device_printf(dev, "could not create DMA map for TX\n"); 1068 return (error); 1069 } 1070 } 1071 1072 /* 1073 * Allocate map for RX descriptor list. 1074 */ 1075 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1076 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1077 NULL, rx_list_size, 1, rx_list_size, 0, 1078 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1079 if (error) { 1080 device_printf(dev, "could not create RX DMA ring tag\n"); 1081 return (error); 1082 } 1083 1084 /* Allocate DMA'able memory for the RX ring */ 1085 1086 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1087 (void **)&sc->rl_ldata.rl_rx_list, 1088 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1089 &sc->rl_ldata.rl_rx_list_map); 1090 if (error) { 1091 device_printf(dev, "could not allocate RX DMA ring\n"); 1092 return (error); 1093 } 1094 1095 /* Load the map for the RX ring. */ 1096 1097 sc->rl_ldata.rl_rx_list_addr = 0; 1098 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1099 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1100 rx_list_size, re_dma_map_addr, 1101 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1102 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1103 device_printf(dev, "could not load RX DMA ring\n"); 1104 return (ENOMEM); 1105 } 1106 1107 /* Create DMA maps for RX buffers */ 1108 1109 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1110 &sc->rl_ldata.rl_rx_sparemap); 1111 if (error) { 1112 device_printf(dev, "could not create spare DMA map for RX\n"); 1113 return (error); 1114 } 1115 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1116 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1117 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1118 if (error) { 1119 device_printf(dev, "could not create DMA map for RX\n"); 1120 return (error); 1121 } 1122 } 1123 1124 return (0); 1125 } 1126 1127 /* 1128 * Attach the interface. Allocate softc structures, do ifmedia 1129 * setup and ethernet/BPF attach. 1130 */ 1131 static int 1132 re_attach(dev) 1133 device_t dev; 1134 { 1135 u_char eaddr[ETHER_ADDR_LEN]; 1136 u_int16_t as[ETHER_ADDR_LEN / 2]; 1137 struct rl_softc *sc; 1138 struct ifnet *ifp; 1139 struct rl_hwrev *hw_rev; 1140 int hwrev; 1141 u_int16_t re_did = 0; 1142 int error = 0, rid, i; 1143 int msic, reg; 1144 1145 sc = device_get_softc(dev); 1146 sc->rl_dev = dev; 1147 1148 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1149 MTX_DEF); 1150 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1151 1152 /* 1153 * Map control/status registers. 1154 */ 1155 pci_enable_busmaster(dev); 1156 1157 rid = RL_RID; 1158 sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 1159 RF_ACTIVE); 1160 1161 if (sc->rl_res == NULL) { 1162 device_printf(dev, "couldn't map ports/memory\n"); 1163 error = ENXIO; 1164 goto fail; 1165 } 1166 1167 sc->rl_btag = rman_get_bustag(sc->rl_res); 1168 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1169 1170 msic = 0; 1171 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 1172 msic = pci_msi_count(dev); 1173 if (bootverbose) 1174 device_printf(dev, "MSI count : %d\n", msic); 1175 } 1176 if (msic == RL_MSI_MESSAGES && msi_disable == 0) { 1177 if (pci_alloc_msi(dev, &msic) == 0) { 1178 if (msic == RL_MSI_MESSAGES) { 1179 device_printf(dev, "Using %d MSI messages\n", 1180 msic); 1181 sc->rl_msi = 1; 1182 } else 1183 pci_release_msi(dev); 1184 } 1185 } 1186 1187 /* Allocate interrupt */ 1188 if (sc->rl_msi == 0) { 1189 rid = 0; 1190 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1191 RF_SHAREABLE | RF_ACTIVE); 1192 if (sc->rl_irq[0] == NULL) { 1193 device_printf(dev, "couldn't allocate IRQ resources\n"); 1194 error = ENXIO; 1195 goto fail; 1196 } 1197 } else { 1198 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1199 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1200 SYS_RES_IRQ, &rid, RF_ACTIVE); 1201 if (sc->rl_irq[i] == NULL) { 1202 device_printf(dev, 1203 "couldn't llocate IRQ resources for " 1204 "message %d\n", rid); 1205 error = ENXIO; 1206 goto fail; 1207 } 1208 } 1209 } 1210 1211 /* Reset the adapter. */ 1212 RL_LOCK(sc); 1213 re_reset(sc); 1214 RL_UNLOCK(sc); 1215 1216 hw_rev = re_hwrevs; 1217 hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 1218 while (hw_rev->rl_desc != NULL) { 1219 if (hw_rev->rl_rev == hwrev) { 1220 sc->rl_type = hw_rev->rl_type; 1221 break; 1222 } 1223 hw_rev++; 1224 } 1225 if (hw_rev->rl_desc == NULL) { 1226 device_printf(dev, "Unknown H/W revision: %08x\n", hwrev); 1227 error = ENXIO; 1228 goto fail; 1229 } 1230 1231 sc->rl_eewidth = RL_9356_ADDR_LEN; 1232 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1233 if (re_did != 0x8129) 1234 sc->rl_eewidth = RL_9346_ADDR_LEN; 1235 1236 /* 1237 * Get station address from the EEPROM. 1238 */ 1239 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1240 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1241 as[i] = le16toh(as[i]); 1242 bcopy(as, eaddr, sizeof(eaddr)); 1243 1244 if (sc->rl_type == RL_8169) { 1245 /* Set RX length mask and number of descriptors. */ 1246 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1247 sc->rl_txstart = RL_GTXSTART; 1248 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1249 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1250 } else { 1251 /* Set RX length mask and number of descriptors. */ 1252 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1253 sc->rl_txstart = RL_TXSTART; 1254 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1255 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1256 } 1257 if (hw_rev->rl_desc == NULL) { 1258 device_printf(dev, "Unsupported revision : 0x%08x\n", hwrev); 1259 error = ENXIO; 1260 goto fail; 1261 } 1262 1263 error = re_allocmem(dev, sc); 1264 if (error) 1265 goto fail; 1266 1267 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1268 if (ifp == NULL) { 1269 device_printf(dev, "can not if_alloc()\n"); 1270 error = ENOSPC; 1271 goto fail; 1272 } 1273 1274 /* Do MII setup */ 1275 if (mii_phy_probe(dev, &sc->rl_miibus, 1276 re_ifmedia_upd, re_ifmedia_sts)) { 1277 device_printf(dev, "MII without any phy!\n"); 1278 error = ENXIO; 1279 goto fail; 1280 } 1281 1282 /* Take PHY out of power down mode. */ 1283 if (sc->rl_type == RL_8169) { 1284 uint32_t rev; 1285 1286 rev = CSR_READ_4(sc, RL_TXCFG); 1287 /* HWVERID 0, 1 and 2 : bit26-30, bit23 */ 1288 rev &= 0x7c800000; 1289 if (rev != 0) { 1290 /* RTL8169S single chip */ 1291 switch (rev) { 1292 case RL_HWREV_8169_8110SB: 1293 case RL_HWREV_8169_8110SC: 1294 case RL_HWREV_8168_SPIN2: 1295 case RL_HWREV_8168_SPIN3: 1296 re_gmii_writereg(dev, 1, 0x1f, 0); 1297 re_gmii_writereg(dev, 1, 0x0e, 0); 1298 break; 1299 default: 1300 break; 1301 } 1302 } 1303 } 1304 1305 ifp->if_softc = sc; 1306 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1307 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1308 ifp->if_ioctl = re_ioctl; 1309 ifp->if_start = re_start; 1310 ifp->if_hwassist = RE_CSUM_FEATURES | CSUM_TSO; 1311 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 1312 ifp->if_capenable = ifp->if_capabilities; 1313 ifp->if_init = re_init; 1314 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1315 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1316 IFQ_SET_READY(&ifp->if_snd); 1317 1318 TASK_INIT(&sc->rl_txtask, 1, re_tx_task, ifp); 1319 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1320 1321 /* 1322 * Call MI attach routine. 1323 */ 1324 ether_ifattach(ifp, eaddr); 1325 1326 /* VLAN capability setup */ 1327 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1328 if (ifp->if_capabilities & IFCAP_HWCSUM) 1329 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1330 /* Enable WOL if PM is supported. */ 1331 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, ®) == 0) 1332 ifp->if_capabilities |= IFCAP_WOL; 1333 ifp->if_capenable = ifp->if_capabilities; 1334 #ifdef DEVICE_POLLING 1335 ifp->if_capabilities |= IFCAP_POLLING; 1336 #endif 1337 /* 1338 * Tell the upper layer(s) we support long frames. 1339 * Must appear after the call to ether_ifattach() because 1340 * ether_ifattach() sets ifi_hdrlen to the default value. 1341 */ 1342 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1343 1344 #ifdef RE_DIAG 1345 /* 1346 * Perform hardware diagnostic on the original RTL8169. 1347 * Some 32-bit cards were incorrectly wired and would 1348 * malfunction if plugged into a 64-bit slot. 1349 */ 1350 1351 if (hwrev == RL_HWREV_8169) { 1352 error = re_diag(sc); 1353 if (error) { 1354 device_printf(dev, 1355 "attach aborted due to hardware diag failure\n"); 1356 ether_ifdetach(ifp); 1357 goto fail; 1358 } 1359 } 1360 #endif 1361 1362 /* Hook interrupt last to avoid having to lock softc */ 1363 if (sc->rl_msi == 0) 1364 error = bus_setup_intr(dev, sc->rl_irq[0], 1365 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1366 &sc->rl_intrhand[0]); 1367 else { 1368 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1369 error = bus_setup_intr(dev, sc->rl_irq[i], 1370 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1371 &sc->rl_intrhand[i]); 1372 if (error != 0) 1373 break; 1374 } 1375 } 1376 if (error) { 1377 device_printf(dev, "couldn't set up irq\n"); 1378 ether_ifdetach(ifp); 1379 } 1380 1381 fail: 1382 1383 if (error) 1384 re_detach(dev); 1385 1386 return (error); 1387 } 1388 1389 /* 1390 * Shutdown hardware and free up resources. This can be called any 1391 * time after the mutex has been initialized. It is called in both 1392 * the error case in attach and the normal detach case so it needs 1393 * to be careful about only freeing resources that have actually been 1394 * allocated. 1395 */ 1396 static int 1397 re_detach(dev) 1398 device_t dev; 1399 { 1400 struct rl_softc *sc; 1401 struct ifnet *ifp; 1402 int i, rid; 1403 1404 sc = device_get_softc(dev); 1405 ifp = sc->rl_ifp; 1406 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1407 1408 #ifdef DEVICE_POLLING 1409 if (ifp->if_capenable & IFCAP_POLLING) 1410 ether_poll_deregister(ifp); 1411 #endif 1412 /* These should only be active if attach succeeded */ 1413 if (device_is_attached(dev)) { 1414 RL_LOCK(sc); 1415 #if 0 1416 sc->suspended = 1; 1417 #endif 1418 re_stop(sc); 1419 RL_UNLOCK(sc); 1420 callout_drain(&sc->rl_stat_callout); 1421 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1422 taskqueue_drain(taskqueue_fast, &sc->rl_txtask); 1423 /* 1424 * Force off the IFF_UP flag here, in case someone 1425 * still had a BPF descriptor attached to this 1426 * interface. If they do, ether_ifdetach() will cause 1427 * the BPF code to try and clear the promisc mode 1428 * flag, which will bubble down to re_ioctl(), 1429 * which will try to call re_init() again. This will 1430 * turn the NIC back on and restart the MII ticker, 1431 * which will panic the system when the kernel tries 1432 * to invoke the re_tick() function that isn't there 1433 * anymore. 1434 */ 1435 ifp->if_flags &= ~IFF_UP; 1436 ether_ifdetach(ifp); 1437 } 1438 if (sc->rl_miibus) 1439 device_delete_child(dev, sc->rl_miibus); 1440 bus_generic_detach(dev); 1441 1442 /* 1443 * The rest is resource deallocation, so we should already be 1444 * stopped here. 1445 */ 1446 1447 for (i = 0; i < RL_MSI_MESSAGES; i++) { 1448 if (sc->rl_intrhand[i] != NULL) { 1449 bus_teardown_intr(dev, sc->rl_irq[i], 1450 sc->rl_intrhand[i]); 1451 sc->rl_intrhand[i] = NULL; 1452 } 1453 } 1454 if (ifp != NULL) 1455 if_free(ifp); 1456 if (sc->rl_msi == 0) { 1457 if (sc->rl_irq[0] != NULL) { 1458 bus_release_resource(dev, SYS_RES_IRQ, 0, 1459 sc->rl_irq[0]); 1460 sc->rl_irq[0] = NULL; 1461 } 1462 } else { 1463 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1464 if (sc->rl_irq[i] != NULL) { 1465 bus_release_resource(dev, SYS_RES_IRQ, rid, 1466 sc->rl_irq[i]); 1467 sc->rl_irq[i] = NULL; 1468 } 1469 } 1470 pci_release_msi(dev); 1471 } 1472 if (sc->rl_res) 1473 bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1474 1475 /* Unload and free the RX DMA ring memory and map */ 1476 1477 if (sc->rl_ldata.rl_rx_list_tag) { 1478 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1479 sc->rl_ldata.rl_rx_list_map); 1480 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1481 sc->rl_ldata.rl_rx_list, 1482 sc->rl_ldata.rl_rx_list_map); 1483 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1484 } 1485 1486 /* Unload and free the TX DMA ring memory and map */ 1487 1488 if (sc->rl_ldata.rl_tx_list_tag) { 1489 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1490 sc->rl_ldata.rl_tx_list_map); 1491 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1492 sc->rl_ldata.rl_tx_list, 1493 sc->rl_ldata.rl_tx_list_map); 1494 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1495 } 1496 1497 /* Destroy all the RX and TX buffer maps */ 1498 1499 if (sc->rl_ldata.rl_tx_mtag) { 1500 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1501 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1502 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1503 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1504 } 1505 if (sc->rl_ldata.rl_rx_mtag) { 1506 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) 1507 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1508 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1509 if (sc->rl_ldata.rl_rx_sparemap) 1510 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1511 sc->rl_ldata.rl_rx_sparemap); 1512 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1513 } 1514 1515 /* Unload and free the stats buffer and map */ 1516 1517 if (sc->rl_ldata.rl_stag) { 1518 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1519 sc->rl_ldata.rl_rx_list_map); 1520 bus_dmamem_free(sc->rl_ldata.rl_stag, 1521 sc->rl_ldata.rl_stats, 1522 sc->rl_ldata.rl_smap); 1523 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1524 } 1525 1526 if (sc->rl_parent_tag) 1527 bus_dma_tag_destroy(sc->rl_parent_tag); 1528 1529 mtx_destroy(&sc->rl_mtx); 1530 1531 return (0); 1532 } 1533 1534 static __inline void 1535 re_discard_rxbuf(sc, idx) 1536 struct rl_softc *sc; 1537 int idx; 1538 { 1539 struct rl_desc *desc; 1540 struct rl_rxdesc *rxd; 1541 uint32_t cmdstat; 1542 1543 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1544 desc = &sc->rl_ldata.rl_rx_list[idx]; 1545 desc->rl_vlanctl = 0; 1546 cmdstat = rxd->rx_size; 1547 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1548 cmdstat |= RL_RDESC_CMD_EOR; 1549 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1550 } 1551 1552 static int 1553 re_newbuf(sc, idx) 1554 struct rl_softc *sc; 1555 int idx; 1556 { 1557 struct mbuf *m; 1558 struct rl_rxdesc *rxd; 1559 bus_dma_segment_t segs[1]; 1560 bus_dmamap_t map; 1561 struct rl_desc *desc; 1562 uint32_t cmdstat; 1563 int error, nsegs; 1564 1565 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1566 if (m == NULL) 1567 return (ENOBUFS); 1568 1569 m->m_len = m->m_pkthdr.len = MCLBYTES; 1570 #ifdef RE_FIXUP_RX 1571 /* 1572 * This is part of an evil trick to deal with non-x86 platforms. 1573 * The RealTek chip requires RX buffers to be aligned on 64-bit 1574 * boundaries, but that will hose non-x86 machines. To get around 1575 * this, we leave some empty space at the start of each buffer 1576 * and for non-x86 hosts, we copy the buffer back six bytes 1577 * to achieve word alignment. This is slightly more efficient 1578 * than allocating a new buffer, copying the contents, and 1579 * discarding the old buffer. 1580 */ 1581 m_adj(m, RE_ETHER_ALIGN); 1582 #endif 1583 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1584 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1585 if (error != 0) { 1586 m_freem(m); 1587 return (ENOBUFS); 1588 } 1589 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1590 1591 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1592 if (rxd->rx_m != NULL) { 1593 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1594 BUS_DMASYNC_POSTREAD); 1595 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1596 } 1597 1598 rxd->rx_m = m; 1599 map = rxd->rx_dmamap; 1600 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1601 rxd->rx_size = segs[0].ds_len; 1602 sc->rl_ldata.rl_rx_sparemap = map; 1603 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1604 BUS_DMASYNC_PREREAD); 1605 1606 desc = &sc->rl_ldata.rl_rx_list[idx]; 1607 desc->rl_vlanctl = 0; 1608 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1609 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1610 cmdstat = segs[0].ds_len; 1611 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1612 cmdstat |= RL_RDESC_CMD_EOR; 1613 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1614 1615 return (0); 1616 } 1617 1618 #ifdef RE_FIXUP_RX 1619 static __inline void 1620 re_fixup_rx(m) 1621 struct mbuf *m; 1622 { 1623 int i; 1624 uint16_t *src, *dst; 1625 1626 src = mtod(m, uint16_t *); 1627 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 1628 1629 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1630 *dst++ = *src++; 1631 1632 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 1633 1634 return; 1635 } 1636 #endif 1637 1638 static int 1639 re_tx_list_init(sc) 1640 struct rl_softc *sc; 1641 { 1642 struct rl_desc *desc; 1643 int i; 1644 1645 RL_LOCK_ASSERT(sc); 1646 1647 bzero(sc->rl_ldata.rl_tx_list, 1648 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 1649 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1650 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 1651 /* Set EOR. */ 1652 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 1653 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 1654 1655 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1656 sc->rl_ldata.rl_tx_list_map, 1657 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1658 1659 sc->rl_ldata.rl_tx_prodidx = 0; 1660 sc->rl_ldata.rl_tx_considx = 0; 1661 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 1662 1663 return (0); 1664 } 1665 1666 static int 1667 re_rx_list_init(sc) 1668 struct rl_softc *sc; 1669 { 1670 int error, i; 1671 1672 bzero(sc->rl_ldata.rl_rx_list, 1673 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 1674 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1675 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 1676 if ((error = re_newbuf(sc, i)) != 0) 1677 return (error); 1678 } 1679 1680 /* Flush the RX descriptors */ 1681 1682 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1683 sc->rl_ldata.rl_rx_list_map, 1684 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1685 1686 sc->rl_ldata.rl_rx_prodidx = 0; 1687 sc->rl_head = sc->rl_tail = NULL; 1688 1689 return (0); 1690 } 1691 1692 /* 1693 * RX handler for C+ and 8169. For the gigE chips, we support 1694 * the reception of jumbo frames that have been fragmented 1695 * across multiple 2K mbuf cluster buffers. 1696 */ 1697 static int 1698 re_rxeof(sc) 1699 struct rl_softc *sc; 1700 { 1701 struct mbuf *m; 1702 struct ifnet *ifp; 1703 int i, total_len; 1704 struct rl_desc *cur_rx; 1705 u_int32_t rxstat, rxvlan; 1706 int maxpkt = 16; 1707 1708 RL_LOCK_ASSERT(sc); 1709 1710 ifp = sc->rl_ifp; 1711 1712 /* Invalidate the descriptor memory */ 1713 1714 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1715 sc->rl_ldata.rl_rx_list_map, 1716 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1717 1718 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 1719 i = RL_RX_DESC_NXT(sc, i)) { 1720 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1721 rxstat = le32toh(cur_rx->rl_cmdstat); 1722 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 1723 break; 1724 total_len = rxstat & sc->rl_rxlenmask; 1725 rxvlan = le32toh(cur_rx->rl_vlanctl); 1726 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 1727 1728 if (!(rxstat & RL_RDESC_STAT_EOF)) { 1729 if (re_newbuf(sc, i) != 0) { 1730 /* 1731 * If this is part of a multi-fragment packet, 1732 * discard all the pieces. 1733 */ 1734 if (sc->rl_head != NULL) { 1735 m_freem(sc->rl_head); 1736 sc->rl_head = sc->rl_tail = NULL; 1737 } 1738 re_discard_rxbuf(sc, i); 1739 continue; 1740 } 1741 m->m_len = RE_RX_DESC_BUFLEN; 1742 if (sc->rl_head == NULL) 1743 sc->rl_head = sc->rl_tail = m; 1744 else { 1745 m->m_flags &= ~M_PKTHDR; 1746 sc->rl_tail->m_next = m; 1747 sc->rl_tail = m; 1748 } 1749 continue; 1750 } 1751 1752 /* 1753 * NOTE: for the 8139C+, the frame length field 1754 * is always 12 bits in size, but for the gigE chips, 1755 * it is 13 bits (since the max RX frame length is 16K). 1756 * Unfortunately, all 32 bits in the status word 1757 * were already used, so to make room for the extra 1758 * length bit, RealTek took out the 'frame alignment 1759 * error' bit and shifted the other status bits 1760 * over one slot. The OWN, EOR, FS and LS bits are 1761 * still in the same places. We have already extracted 1762 * the frame length and checked the OWN bit, so rather 1763 * than using an alternate bit mapping, we shift the 1764 * status bits one space to the right so we can evaluate 1765 * them using the 8169 status as though it was in the 1766 * same format as that of the 8139C+. 1767 */ 1768 if (sc->rl_type == RL_8169) 1769 rxstat >>= 1; 1770 1771 /* 1772 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 1773 * set, but if CRC is clear, it will still be a valid frame. 1774 */ 1775 if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 && 1776 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) { 1777 ifp->if_ierrors++; 1778 /* 1779 * If this is part of a multi-fragment packet, 1780 * discard all the pieces. 1781 */ 1782 if (sc->rl_head != NULL) { 1783 m_freem(sc->rl_head); 1784 sc->rl_head = sc->rl_tail = NULL; 1785 } 1786 re_discard_rxbuf(sc, i); 1787 continue; 1788 } 1789 1790 /* 1791 * If allocating a replacement mbuf fails, 1792 * reload the current one. 1793 */ 1794 1795 if (re_newbuf(sc, i) != 0) { 1796 ifp->if_iqdrops++; 1797 if (sc->rl_head != NULL) { 1798 m_freem(sc->rl_head); 1799 sc->rl_head = sc->rl_tail = NULL; 1800 } 1801 re_discard_rxbuf(sc, i); 1802 continue; 1803 } 1804 1805 if (sc->rl_head != NULL) { 1806 m->m_len = total_len % RE_RX_DESC_BUFLEN; 1807 if (m->m_len == 0) 1808 m->m_len = RE_RX_DESC_BUFLEN; 1809 /* 1810 * Special case: if there's 4 bytes or less 1811 * in this buffer, the mbuf can be discarded: 1812 * the last 4 bytes is the CRC, which we don't 1813 * care about anyway. 1814 */ 1815 if (m->m_len <= ETHER_CRC_LEN) { 1816 sc->rl_tail->m_len -= 1817 (ETHER_CRC_LEN - m->m_len); 1818 m_freem(m); 1819 } else { 1820 m->m_len -= ETHER_CRC_LEN; 1821 m->m_flags &= ~M_PKTHDR; 1822 sc->rl_tail->m_next = m; 1823 } 1824 m = sc->rl_head; 1825 sc->rl_head = sc->rl_tail = NULL; 1826 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1827 } else 1828 m->m_pkthdr.len = m->m_len = 1829 (total_len - ETHER_CRC_LEN); 1830 1831 #ifdef RE_FIXUP_RX 1832 re_fixup_rx(m); 1833 #endif 1834 ifp->if_ipackets++; 1835 m->m_pkthdr.rcvif = ifp; 1836 1837 /* Do RX checksumming if enabled */ 1838 1839 if (ifp->if_capenable & IFCAP_RXCSUM) { 1840 1841 /* Check IP header checksum */ 1842 if (rxstat & RL_RDESC_STAT_PROTOID) 1843 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1844 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1845 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1846 1847 /* Check TCP/UDP checksum */ 1848 if ((RL_TCPPKT(rxstat) && 1849 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1850 (RL_UDPPKT(rxstat) && 1851 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1852 m->m_pkthdr.csum_flags |= 1853 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1854 m->m_pkthdr.csum_data = 0xffff; 1855 } 1856 } 1857 maxpkt--; 1858 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 1859 m->m_pkthdr.ether_vtag = 1860 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)); 1861 m->m_flags |= M_VLANTAG; 1862 } 1863 RL_UNLOCK(sc); 1864 (*ifp->if_input)(ifp, m); 1865 RL_LOCK(sc); 1866 } 1867 1868 /* Flush the RX DMA ring */ 1869 1870 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1871 sc->rl_ldata.rl_rx_list_map, 1872 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1873 1874 sc->rl_ldata.rl_rx_prodidx = i; 1875 1876 if (maxpkt) 1877 return(EAGAIN); 1878 1879 return(0); 1880 } 1881 1882 static void 1883 re_txeof(sc) 1884 struct rl_softc *sc; 1885 { 1886 struct ifnet *ifp; 1887 struct rl_txdesc *txd; 1888 u_int32_t txstat; 1889 int cons; 1890 1891 cons = sc->rl_ldata.rl_tx_considx; 1892 if (cons == sc->rl_ldata.rl_tx_prodidx) 1893 return; 1894 1895 ifp = sc->rl_ifp; 1896 /* Invalidate the TX descriptor list */ 1897 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1898 sc->rl_ldata.rl_tx_list_map, 1899 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1900 1901 for (; cons != sc->rl_ldata.rl_tx_prodidx; 1902 cons = RL_TX_DESC_NXT(sc, cons)) { 1903 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 1904 if (txstat & RL_TDESC_STAT_OWN) 1905 break; 1906 /* 1907 * We only stash mbufs in the last descriptor 1908 * in a fragment chain, which also happens to 1909 * be the only place where the TX status bits 1910 * are valid. 1911 */ 1912 if (txstat & RL_TDESC_CMD_EOF) { 1913 txd = &sc->rl_ldata.rl_tx_desc[cons]; 1914 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 1915 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 1916 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 1917 txd->tx_dmamap); 1918 KASSERT(txd->tx_m != NULL, 1919 ("%s: freeing NULL mbufs!", __func__)); 1920 m_freem(txd->tx_m); 1921 txd->tx_m = NULL; 1922 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 1923 RL_TDESC_STAT_COLCNT)) 1924 ifp->if_collisions++; 1925 if (txstat & RL_TDESC_STAT_TXERRSUM) 1926 ifp->if_oerrors++; 1927 else 1928 ifp->if_opackets++; 1929 } 1930 sc->rl_ldata.rl_tx_free++; 1931 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1932 } 1933 sc->rl_ldata.rl_tx_considx = cons; 1934 1935 /* No changes made to the TX ring, so no flush needed */ 1936 1937 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 1938 /* 1939 * Some chips will ignore a second TX request issued 1940 * while an existing transmission is in progress. If 1941 * the transmitter goes idle but there are still 1942 * packets waiting to be sent, we need to restart the 1943 * channel here to flush them out. This only seems to 1944 * be required with the PCIe devices. 1945 */ 1946 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 1947 1948 #ifdef RE_TX_MODERATION 1949 /* 1950 * If not all descriptors have been reaped yet, reload 1951 * the timer so that we will eventually get another 1952 * interrupt that will cause us to re-enter this routine. 1953 * This is done in case the transmitter has gone idle. 1954 */ 1955 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 1956 #endif 1957 } else 1958 sc->rl_watchdog_timer = 0; 1959 } 1960 1961 static void 1962 re_tick(xsc) 1963 void *xsc; 1964 { 1965 struct rl_softc *sc; 1966 struct mii_data *mii; 1967 struct ifnet *ifp; 1968 1969 sc = xsc; 1970 ifp = sc->rl_ifp; 1971 1972 RL_LOCK_ASSERT(sc); 1973 1974 re_watchdog(sc); 1975 1976 mii = device_get_softc(sc->rl_miibus); 1977 mii_tick(mii); 1978 if (sc->rl_link) { 1979 if (!(mii->mii_media_status & IFM_ACTIVE)) 1980 sc->rl_link = 0; 1981 } else { 1982 if (mii->mii_media_status & IFM_ACTIVE && 1983 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1984 sc->rl_link = 1; 1985 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1986 taskqueue_enqueue_fast(taskqueue_fast, 1987 &sc->rl_txtask); 1988 } 1989 } 1990 1991 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 1992 } 1993 1994 #ifdef DEVICE_POLLING 1995 static void 1996 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1997 { 1998 struct rl_softc *sc = ifp->if_softc; 1999 2000 RL_LOCK(sc); 2001 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2002 re_poll_locked(ifp, cmd, count); 2003 RL_UNLOCK(sc); 2004 } 2005 2006 static void 2007 re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2008 { 2009 struct rl_softc *sc = ifp->if_softc; 2010 2011 RL_LOCK_ASSERT(sc); 2012 2013 sc->rxcycles = count; 2014 re_rxeof(sc); 2015 re_txeof(sc); 2016 2017 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2018 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2019 2020 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2021 u_int16_t status; 2022 2023 status = CSR_READ_2(sc, RL_ISR); 2024 if (status == 0xffff) 2025 return; 2026 if (status) 2027 CSR_WRITE_2(sc, RL_ISR, status); 2028 2029 /* 2030 * XXX check behaviour on receiver stalls. 2031 */ 2032 2033 if (status & RL_ISR_SYSTEM_ERR) { 2034 re_reset(sc); 2035 re_init_locked(sc); 2036 } 2037 } 2038 } 2039 #endif /* DEVICE_POLLING */ 2040 2041 static int 2042 re_intr(arg) 2043 void *arg; 2044 { 2045 struct rl_softc *sc; 2046 uint16_t status; 2047 2048 sc = arg; 2049 2050 status = CSR_READ_2(sc, RL_ISR); 2051 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2052 return (FILTER_STRAY); 2053 CSR_WRITE_2(sc, RL_IMR, 0); 2054 2055 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2056 2057 return (FILTER_HANDLED); 2058 } 2059 2060 static void 2061 re_int_task(arg, npending) 2062 void *arg; 2063 int npending; 2064 { 2065 struct rl_softc *sc; 2066 struct ifnet *ifp; 2067 u_int16_t status; 2068 int rval = 0; 2069 2070 sc = arg; 2071 ifp = sc->rl_ifp; 2072 2073 RL_LOCK(sc); 2074 2075 status = CSR_READ_2(sc, RL_ISR); 2076 CSR_WRITE_2(sc, RL_ISR, status); 2077 2078 if (sc->suspended || 2079 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2080 RL_UNLOCK(sc); 2081 return; 2082 } 2083 2084 #ifdef DEVICE_POLLING 2085 if (ifp->if_capenable & IFCAP_POLLING) { 2086 RL_UNLOCK(sc); 2087 return; 2088 } 2089 #endif 2090 2091 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2092 rval = re_rxeof(sc); 2093 2094 #ifdef RE_TX_MODERATION 2095 if (status & (RL_ISR_TIMEOUT_EXPIRED| 2096 #else 2097 if (status & (RL_ISR_TX_OK| 2098 #endif 2099 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2100 re_txeof(sc); 2101 2102 if (status & RL_ISR_SYSTEM_ERR) { 2103 re_reset(sc); 2104 re_init_locked(sc); 2105 } 2106 2107 if (status & RL_ISR_LINKCHG) { 2108 callout_stop(&sc->rl_stat_callout); 2109 re_tick(sc); 2110 } 2111 2112 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2113 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2114 2115 RL_UNLOCK(sc); 2116 2117 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2118 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2119 return; 2120 } 2121 2122 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2123 2124 return; 2125 } 2126 2127 static int 2128 re_encap(sc, m_head) 2129 struct rl_softc *sc; 2130 struct mbuf **m_head; 2131 { 2132 struct rl_txdesc *txd, *txd_last; 2133 bus_dma_segment_t segs[RL_NTXSEGS]; 2134 bus_dmamap_t map; 2135 struct mbuf *m_new; 2136 struct rl_desc *desc; 2137 int nsegs, prod; 2138 int i, error, ei, si; 2139 int padlen; 2140 uint32_t cmdstat, csum_flags; 2141 2142 RL_LOCK_ASSERT(sc); 2143 M_ASSERTPKTHDR((*m_head)); 2144 2145 /* 2146 * With some of the RealTek chips, using the checksum offload 2147 * support in conjunction with the autopadding feature results 2148 * in the transmission of corrupt frames. For example, if we 2149 * need to send a really small IP fragment that's less than 60 2150 * bytes in size, and IP header checksumming is enabled, the 2151 * resulting ethernet frame that appears on the wire will 2152 * have garbled payload. To work around this, if TX checksum 2153 * offload is enabled, we always manually pad short frames out 2154 * to the minimum ethernet frame size. 2155 * 2156 * Note: this appears unnecessary for TCP, and doing it for TCP 2157 * with PCIe adapters seems to result in bad checksums. 2158 */ 2159 if ((*m_head)->m_pkthdr.csum_flags & (CSUM_IP | CSUM_UDP) && 2160 ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) == 0 && 2161 (*m_head)->m_pkthdr.len < RL_MIN_FRAMELEN) { 2162 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2163 if (M_WRITABLE(*m_head) == 0) { 2164 /* Get a writable copy. */ 2165 m_new = m_dup(*m_head, M_DONTWAIT); 2166 m_freem(*m_head); 2167 if (m_new == NULL) { 2168 *m_head = NULL; 2169 return (ENOBUFS); 2170 } 2171 *m_head = m_new; 2172 } 2173 if ((*m_head)->m_next != NULL || 2174 M_TRAILINGSPACE(*m_head) < padlen) { 2175 m_new = m_defrag(*m_head, M_DONTWAIT); 2176 if (m_new == NULL) { 2177 m_freem(*m_head); 2178 *m_head = NULL; 2179 return (ENOBUFS); 2180 } 2181 } else 2182 m_new = *m_head; 2183 2184 /* 2185 * Manually pad short frames, and zero the pad space 2186 * to avoid leaking data. 2187 */ 2188 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2189 m_new->m_pkthdr.len += padlen; 2190 m_new->m_len = m_new->m_pkthdr.len; 2191 *m_head = m_new; 2192 } 2193 2194 prod = sc->rl_ldata.rl_tx_prodidx; 2195 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2196 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2197 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2198 if (error == EFBIG) { 2199 m_new = m_collapse(*m_head, M_DONTWAIT, RL_NTXSEGS); 2200 if (m_new == NULL) { 2201 m_freem(*m_head); 2202 *m_head = NULL; 2203 return (ENOBUFS); 2204 } 2205 *m_head = m_new; 2206 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2207 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2208 if (error != 0) { 2209 m_freem(*m_head); 2210 *m_head = NULL; 2211 return (error); 2212 } 2213 } else if (error != 0) 2214 return (error); 2215 if (nsegs == 0) { 2216 m_freem(*m_head); 2217 *m_head = NULL; 2218 return (EIO); 2219 } 2220 2221 /* Check for number of available descriptors. */ 2222 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2223 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2224 return (ENOBUFS); 2225 } 2226 2227 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2228 BUS_DMASYNC_PREWRITE); 2229 2230 /* 2231 * Set up checksum offload. Note: checksum offload bits must 2232 * appear in all descriptors of a multi-descriptor transmit 2233 * attempt. This is according to testing done with an 8169 2234 * chip. This is a requirement. 2235 */ 2236 csum_flags = 0; 2237 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) 2238 csum_flags = RL_TDESC_CMD_LGSEND | 2239 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2240 RL_TDESC_CMD_MSSVAL_SHIFT); 2241 else { 2242 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) 2243 csum_flags |= RL_TDESC_CMD_IPCSUM; 2244 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) 2245 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2246 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) 2247 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2248 } 2249 2250 si = prod; 2251 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2252 desc = &sc->rl_ldata.rl_tx_list[prod]; 2253 desc->rl_vlanctl = 0; 2254 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2255 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2256 cmdstat = segs[i].ds_len; 2257 if (i != 0) 2258 cmdstat |= RL_TDESC_CMD_OWN; 2259 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2260 cmdstat |= RL_TDESC_CMD_EOR; 2261 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2262 sc->rl_ldata.rl_tx_free--; 2263 } 2264 /* Update producer index. */ 2265 sc->rl_ldata.rl_tx_prodidx = prod; 2266 2267 /* Set EOF on the last descriptor. */ 2268 ei = RL_TX_DESC_PRV(sc, prod); 2269 desc = &sc->rl_ldata.rl_tx_list[ei]; 2270 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2271 2272 desc = &sc->rl_ldata.rl_tx_list[si]; 2273 /* 2274 * Set up hardware VLAN tagging. Note: vlan tag info must 2275 * appear in the first descriptor of a multi-descriptor 2276 * transmission attempt. 2277 */ 2278 if ((*m_head)->m_flags & M_VLANTAG) 2279 desc->rl_vlanctl = 2280 htole32(htons((*m_head)->m_pkthdr.ether_vtag) | 2281 RL_TDESC_VLANCTL_TAG); 2282 /* Set SOF and transfer ownership of packet to the chip. */ 2283 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2284 2285 /* 2286 * Insure that the map for this transmission 2287 * is placed at the array index of the last descriptor 2288 * in this chain. (Swap last and first dmamaps.) 2289 */ 2290 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2291 map = txd->tx_dmamap; 2292 txd->tx_dmamap = txd_last->tx_dmamap; 2293 txd_last->tx_dmamap = map; 2294 txd_last->tx_m = *m_head; 2295 2296 return (0); 2297 } 2298 2299 static void 2300 re_tx_task(arg, npending) 2301 void *arg; 2302 int npending; 2303 { 2304 struct ifnet *ifp; 2305 2306 ifp = arg; 2307 re_start(ifp); 2308 2309 return; 2310 } 2311 2312 /* 2313 * Main transmit routine for C+ and gigE NICs. 2314 */ 2315 static void 2316 re_start(ifp) 2317 struct ifnet *ifp; 2318 { 2319 struct rl_softc *sc; 2320 struct mbuf *m_head; 2321 int queued; 2322 2323 sc = ifp->if_softc; 2324 2325 RL_LOCK(sc); 2326 2327 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2328 IFF_DRV_RUNNING || sc->rl_link == 0) { 2329 RL_UNLOCK(sc); 2330 return; 2331 } 2332 2333 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2334 sc->rl_ldata.rl_tx_free > 1;) { 2335 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2336 if (m_head == NULL) 2337 break; 2338 2339 if (re_encap(sc, &m_head) != 0) { 2340 if (m_head == NULL) 2341 break; 2342 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2343 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2344 break; 2345 } 2346 2347 /* 2348 * If there's a BPF listener, bounce a copy of this frame 2349 * to him. 2350 */ 2351 ETHER_BPF_MTAP(ifp, m_head); 2352 2353 queued++; 2354 } 2355 2356 if (queued == 0) { 2357 #ifdef RE_TX_MODERATION 2358 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2359 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2360 #endif 2361 RL_UNLOCK(sc); 2362 return; 2363 } 2364 2365 /* Flush the TX descriptors */ 2366 2367 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2368 sc->rl_ldata.rl_tx_list_map, 2369 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2370 2371 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2372 2373 #ifdef RE_TX_MODERATION 2374 /* 2375 * Use the countdown timer for interrupt moderation. 2376 * 'TX done' interrupts are disabled. Instead, we reset the 2377 * countdown timer, which will begin counting until it hits 2378 * the value in the TIMERINT register, and then trigger an 2379 * interrupt. Each time we write to the TIMERCNT register, 2380 * the timer count is reset to 0. 2381 */ 2382 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2383 #endif 2384 2385 /* 2386 * Set a timeout in case the chip goes out to lunch. 2387 */ 2388 sc->rl_watchdog_timer = 5; 2389 2390 RL_UNLOCK(sc); 2391 2392 return; 2393 } 2394 2395 static void 2396 re_init(xsc) 2397 void *xsc; 2398 { 2399 struct rl_softc *sc = xsc; 2400 2401 RL_LOCK(sc); 2402 re_init_locked(sc); 2403 RL_UNLOCK(sc); 2404 } 2405 2406 static void 2407 re_init_locked(sc) 2408 struct rl_softc *sc; 2409 { 2410 struct ifnet *ifp = sc->rl_ifp; 2411 struct mii_data *mii; 2412 u_int32_t rxcfg = 0; 2413 union { 2414 uint32_t align_dummy; 2415 u_char eaddr[ETHER_ADDR_LEN]; 2416 } eaddr; 2417 2418 RL_LOCK_ASSERT(sc); 2419 2420 mii = device_get_softc(sc->rl_miibus); 2421 2422 /* 2423 * Cancel pending I/O and free all RX/TX buffers. 2424 */ 2425 re_stop(sc); 2426 2427 /* 2428 * Enable C+ RX and TX mode, as well as VLAN stripping and 2429 * RX checksum offload. We must configure the C+ register 2430 * before all others. 2431 */ 2432 CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB| 2433 RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW| 2434 RL_CPLUSCMD_VLANSTRIP|RL_CPLUSCMD_RXCSUM_ENB); 2435 2436 /* 2437 * Init our MAC address. Even though the chipset 2438 * documentation doesn't mention it, we need to enter "Config 2439 * register write enable" mode to modify the ID registers. 2440 */ 2441 /* Copy MAC address on stack to align. */ 2442 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 2443 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2444 CSR_WRITE_4(sc, RL_IDR0, 2445 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 2446 CSR_WRITE_4(sc, RL_IDR4, 2447 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 2448 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2449 2450 /* 2451 * For C+ mode, initialize the RX descriptors and mbufs. 2452 */ 2453 re_rx_list_init(sc); 2454 re_tx_list_init(sc); 2455 2456 /* 2457 * Load the addresses of the RX and TX lists into the chip. 2458 */ 2459 2460 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2461 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2462 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2463 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2464 2465 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2466 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2467 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2468 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2469 2470 /* 2471 * Enable transmit and receive. 2472 */ 2473 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2474 2475 /* 2476 * Set the initial TX and RX configuration. 2477 */ 2478 if (sc->rl_testmode) { 2479 if (sc->rl_type == RL_8169) 2480 CSR_WRITE_4(sc, RL_TXCFG, 2481 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2482 else 2483 CSR_WRITE_4(sc, RL_TXCFG, 2484 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2485 } else 2486 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2487 2488 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2489 2490 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 2491 2492 /* Set the individual bit to receive frames for this host only. */ 2493 rxcfg = CSR_READ_4(sc, RL_RXCFG); 2494 rxcfg |= RL_RXCFG_RX_INDIV; 2495 2496 /* If we want promiscuous mode, set the allframes bit. */ 2497 if (ifp->if_flags & IFF_PROMISC) 2498 rxcfg |= RL_RXCFG_RX_ALLPHYS; 2499 else 2500 rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 2501 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2502 2503 /* 2504 * Set capture broadcast bit to capture broadcast frames. 2505 */ 2506 if (ifp->if_flags & IFF_BROADCAST) 2507 rxcfg |= RL_RXCFG_RX_BROAD; 2508 else 2509 rxcfg &= ~RL_RXCFG_RX_BROAD; 2510 CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2511 2512 /* 2513 * Program the multicast filter, if necessary. 2514 */ 2515 re_setmulti(sc); 2516 2517 #ifdef DEVICE_POLLING 2518 /* 2519 * Disable interrupts if we are polling. 2520 */ 2521 if (ifp->if_capenable & IFCAP_POLLING) 2522 CSR_WRITE_2(sc, RL_IMR, 0); 2523 else /* otherwise ... */ 2524 #endif 2525 2526 /* 2527 * Enable interrupts. 2528 */ 2529 if (sc->rl_testmode) 2530 CSR_WRITE_2(sc, RL_IMR, 0); 2531 else 2532 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2533 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 2534 2535 /* Set initial TX threshold */ 2536 sc->rl_txthresh = RL_TX_THRESH_INIT; 2537 2538 /* Start RX/TX process. */ 2539 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2540 #ifdef notdef 2541 /* Enable receiver and transmitter. */ 2542 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2543 #endif 2544 2545 #ifdef RE_TX_MODERATION 2546 /* 2547 * Initialize the timer interrupt register so that 2548 * a timer interrupt will be generated once the timer 2549 * reaches a certain number of ticks. The timer is 2550 * reloaded on each transmit. This gives us TX interrupt 2551 * moderation, which dramatically improves TX frame rate. 2552 */ 2553 if (sc->rl_type == RL_8169) 2554 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2555 else 2556 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2557 #endif 2558 2559 /* 2560 * For 8169 gigE NICs, set the max allowed RX packet 2561 * size so we can receive jumbo frames. 2562 */ 2563 if (sc->rl_type == RL_8169) 2564 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2565 2566 if (sc->rl_testmode) 2567 return; 2568 2569 mii_mediachg(mii); 2570 2571 CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD); 2572 2573 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2574 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2575 2576 sc->rl_link = 0; 2577 sc->rl_watchdog_timer = 0; 2578 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2579 } 2580 2581 /* 2582 * Set media options. 2583 */ 2584 static int 2585 re_ifmedia_upd(ifp) 2586 struct ifnet *ifp; 2587 { 2588 struct rl_softc *sc; 2589 struct mii_data *mii; 2590 2591 sc = ifp->if_softc; 2592 mii = device_get_softc(sc->rl_miibus); 2593 RL_LOCK(sc); 2594 mii_mediachg(mii); 2595 RL_UNLOCK(sc); 2596 2597 return (0); 2598 } 2599 2600 /* 2601 * Report current media status. 2602 */ 2603 static void 2604 re_ifmedia_sts(ifp, ifmr) 2605 struct ifnet *ifp; 2606 struct ifmediareq *ifmr; 2607 { 2608 struct rl_softc *sc; 2609 struct mii_data *mii; 2610 2611 sc = ifp->if_softc; 2612 mii = device_get_softc(sc->rl_miibus); 2613 2614 RL_LOCK(sc); 2615 mii_pollstat(mii); 2616 RL_UNLOCK(sc); 2617 ifmr->ifm_active = mii->mii_media_active; 2618 ifmr->ifm_status = mii->mii_media_status; 2619 } 2620 2621 static int 2622 re_ioctl(ifp, command, data) 2623 struct ifnet *ifp; 2624 u_long command; 2625 caddr_t data; 2626 { 2627 struct rl_softc *sc = ifp->if_softc; 2628 struct ifreq *ifr = (struct ifreq *) data; 2629 struct mii_data *mii; 2630 int error = 0; 2631 2632 switch (command) { 2633 case SIOCSIFMTU: 2634 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > RL_JUMBO_MTU) { 2635 error = EINVAL; 2636 break; 2637 } 2638 if (sc->rl_type == RL_8139CPLUS && 2639 ifr->ifr_mtu > RL_MAX_FRAMELEN) { 2640 error = EINVAL; 2641 break; 2642 } 2643 RL_LOCK(sc); 2644 if (ifp->if_mtu != ifr->ifr_mtu) 2645 ifp->if_mtu = ifr->ifr_mtu; 2646 RL_UNLOCK(sc); 2647 break; 2648 case SIOCSIFFLAGS: 2649 RL_LOCK(sc); 2650 if ((ifp->if_flags & IFF_UP) != 0) { 2651 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2652 if (((ifp->if_flags ^ sc->rl_if_flags) 2653 & IFF_PROMISC) != 0) 2654 re_setmulti(sc); 2655 } else 2656 re_init_locked(sc); 2657 } else { 2658 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2659 re_stop(sc); 2660 } 2661 sc->rl_if_flags = ifp->if_flags; 2662 RL_UNLOCK(sc); 2663 break; 2664 case SIOCADDMULTI: 2665 case SIOCDELMULTI: 2666 RL_LOCK(sc); 2667 re_setmulti(sc); 2668 RL_UNLOCK(sc); 2669 break; 2670 case SIOCGIFMEDIA: 2671 case SIOCSIFMEDIA: 2672 mii = device_get_softc(sc->rl_miibus); 2673 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2674 break; 2675 case SIOCSIFCAP: 2676 { 2677 int mask, reinit; 2678 2679 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2680 reinit = 0; 2681 #ifdef DEVICE_POLLING 2682 if (mask & IFCAP_POLLING) { 2683 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2684 error = ether_poll_register(re_poll, ifp); 2685 if (error) 2686 return(error); 2687 RL_LOCK(sc); 2688 /* Disable interrupts */ 2689 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2690 ifp->if_capenable |= IFCAP_POLLING; 2691 RL_UNLOCK(sc); 2692 } else { 2693 error = ether_poll_deregister(ifp); 2694 /* Enable interrupts. */ 2695 RL_LOCK(sc); 2696 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2697 ifp->if_capenable &= ~IFCAP_POLLING; 2698 RL_UNLOCK(sc); 2699 } 2700 } 2701 #endif /* DEVICE_POLLING */ 2702 if (mask & IFCAP_HWCSUM) { 2703 ifp->if_capenable ^= IFCAP_HWCSUM; 2704 if (ifp->if_capenable & IFCAP_TXCSUM) 2705 ifp->if_hwassist |= RE_CSUM_FEATURES; 2706 else 2707 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 2708 reinit = 1; 2709 } 2710 if (mask & IFCAP_VLAN_HWTAGGING) { 2711 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2712 reinit = 1; 2713 } 2714 if (mask & IFCAP_TSO4) { 2715 ifp->if_capenable ^= IFCAP_TSO4; 2716 if ((IFCAP_TSO4 & ifp->if_capenable) && 2717 (IFCAP_TSO4 & ifp->if_capabilities)) 2718 ifp->if_hwassist |= CSUM_TSO; 2719 else 2720 ifp->if_hwassist &= ~CSUM_TSO; 2721 } 2722 if ((mask & IFCAP_WOL) != 0 && 2723 (ifp->if_capabilities & IFCAP_WOL) != 0) { 2724 if ((mask & IFCAP_WOL_UCAST) != 0) 2725 ifp->if_capenable ^= IFCAP_WOL_UCAST; 2726 if ((mask & IFCAP_WOL_MCAST) != 0) 2727 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2728 if ((mask & IFCAP_WOL_MAGIC) != 0) 2729 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2730 } 2731 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) 2732 re_init(sc); 2733 VLAN_CAPABILITIES(ifp); 2734 } 2735 break; 2736 default: 2737 error = ether_ioctl(ifp, command, data); 2738 break; 2739 } 2740 2741 return (error); 2742 } 2743 2744 static void 2745 re_watchdog(sc) 2746 struct rl_softc *sc; 2747 { 2748 2749 RL_LOCK_ASSERT(sc); 2750 2751 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 2752 return; 2753 2754 device_printf(sc->rl_dev, "watchdog timeout\n"); 2755 sc->rl_ifp->if_oerrors++; 2756 2757 re_txeof(sc); 2758 re_rxeof(sc); 2759 re_init_locked(sc); 2760 } 2761 2762 /* 2763 * Stop the adapter and free any mbufs allocated to the 2764 * RX and TX lists. 2765 */ 2766 static void 2767 re_stop(sc) 2768 struct rl_softc *sc; 2769 { 2770 register int i; 2771 struct ifnet *ifp; 2772 struct rl_txdesc *txd; 2773 struct rl_rxdesc *rxd; 2774 2775 RL_LOCK_ASSERT(sc); 2776 2777 ifp = sc->rl_ifp; 2778 2779 sc->rl_watchdog_timer = 0; 2780 callout_stop(&sc->rl_stat_callout); 2781 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2782 2783 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2784 CSR_WRITE_2(sc, RL_IMR, 0x0000); 2785 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 2786 2787 if (sc->rl_head != NULL) { 2788 m_freem(sc->rl_head); 2789 sc->rl_head = sc->rl_tail = NULL; 2790 } 2791 2792 /* Free the TX list buffers. */ 2793 2794 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 2795 txd = &sc->rl_ldata.rl_tx_desc[i]; 2796 if (txd->tx_m != NULL) { 2797 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2798 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2799 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2800 txd->tx_dmamap); 2801 m_freem(txd->tx_m); 2802 txd->tx_m = NULL; 2803 } 2804 } 2805 2806 /* Free the RX list buffers. */ 2807 2808 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2809 rxd = &sc->rl_ldata.rl_rx_desc[i]; 2810 if (rxd->rx_m != NULL) { 2811 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2812 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2813 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 2814 rxd->rx_dmamap); 2815 m_freem(rxd->rx_m); 2816 rxd->rx_m = NULL; 2817 } 2818 } 2819 } 2820 2821 /* 2822 * Device suspend routine. Stop the interface and save some PCI 2823 * settings in case the BIOS doesn't restore them properly on 2824 * resume. 2825 */ 2826 static int 2827 re_suspend(dev) 2828 device_t dev; 2829 { 2830 struct rl_softc *sc; 2831 2832 sc = device_get_softc(dev); 2833 2834 RL_LOCK(sc); 2835 re_stop(sc); 2836 re_setwol(sc); 2837 sc->suspended = 1; 2838 RL_UNLOCK(sc); 2839 2840 return (0); 2841 } 2842 2843 /* 2844 * Device resume routine. Restore some PCI settings in case the BIOS 2845 * doesn't, re-enable busmastering, and restart the interface if 2846 * appropriate. 2847 */ 2848 static int 2849 re_resume(dev) 2850 device_t dev; 2851 { 2852 struct rl_softc *sc; 2853 struct ifnet *ifp; 2854 2855 sc = device_get_softc(dev); 2856 2857 RL_LOCK(sc); 2858 2859 ifp = sc->rl_ifp; 2860 2861 /* reinitialize interface if necessary */ 2862 if (ifp->if_flags & IFF_UP) 2863 re_init_locked(sc); 2864 2865 /* 2866 * Clear WOL matching such that normal Rx filtering 2867 * wouldn't interfere with WOL patterns. 2868 */ 2869 re_clrwol(sc); 2870 sc->suspended = 0; 2871 RL_UNLOCK(sc); 2872 2873 return (0); 2874 } 2875 2876 /* 2877 * Stop all chip I/O so that the kernel's probe routines don't 2878 * get confused by errant DMAs when rebooting. 2879 */ 2880 static int 2881 re_shutdown(dev) 2882 device_t dev; 2883 { 2884 struct rl_softc *sc; 2885 2886 sc = device_get_softc(dev); 2887 2888 RL_LOCK(sc); 2889 re_stop(sc); 2890 /* 2891 * Mark interface as down since otherwise we will panic if 2892 * interrupt comes in later on, which can happen in some 2893 * cases. 2894 */ 2895 sc->rl_ifp->if_flags &= ~IFF_UP; 2896 re_setwol(sc); 2897 RL_UNLOCK(sc); 2898 2899 return (0); 2900 } 2901 2902 static void 2903 re_setwol(sc) 2904 struct rl_softc *sc; 2905 { 2906 struct ifnet *ifp; 2907 int pmc; 2908 uint16_t pmstat; 2909 uint8_t v; 2910 2911 RL_LOCK_ASSERT(sc); 2912 2913 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 2914 return; 2915 2916 ifp = sc->rl_ifp; 2917 /* Enable config register write. */ 2918 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 2919 2920 /* Enable PME. */ 2921 v = CSR_READ_1(sc, RL_CFG1); 2922 v &= ~RL_CFG1_PME; 2923 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2924 v |= RL_CFG1_PME; 2925 CSR_WRITE_1(sc, RL_CFG1, v); 2926 2927 v = CSR_READ_1(sc, RL_CFG3); 2928 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 2929 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2930 v |= RL_CFG3_WOL_MAGIC; 2931 CSR_WRITE_1(sc, RL_CFG3, v); 2932 2933 /* Config register write done. */ 2934 CSR_WRITE_1(sc, RL_EECMD, 0); 2935 2936 v = CSR_READ_1(sc, RL_CFG5); 2937 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 2938 v &= ~RL_CFG5_WOL_LANWAKE; 2939 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 2940 v |= RL_CFG5_WOL_UCAST; 2941 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 2942 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 2943 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2944 v |= RL_CFG5_WOL_LANWAKE; 2945 CSR_WRITE_1(sc, RL_CFG5, v); 2946 2947 /* 2948 * It seems that hardware resets its link speed to 100Mbps in 2949 * power down mode so switching to 100Mbps in driver is not 2950 * needed. 2951 */ 2952 2953 /* Request PME if WOL is requested. */ 2954 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 2955 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2956 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2957 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2958 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 2959 } 2960 2961 static void 2962 re_clrwol(sc) 2963 struct rl_softc *sc; 2964 { 2965 int pmc; 2966 uint8_t v; 2967 2968 RL_LOCK_ASSERT(sc); 2969 2970 if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 2971 return; 2972 2973 /* Enable config register write. */ 2974 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 2975 2976 v = CSR_READ_1(sc, RL_CFG3); 2977 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 2978 CSR_WRITE_1(sc, RL_CFG3, v); 2979 2980 /* Config register write done. */ 2981 CSR_WRITE_1(sc, RL_EECMD, 0); 2982 2983 v = CSR_READ_1(sc, RL_CFG5); 2984 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 2985 v &= ~RL_CFG5_WOL_LANWAKE; 2986 CSR_WRITE_1(sc, RL_CFG5, v); 2987 } 2988