xref: /freebsd/sys/dev/re/if_re.c (revision fd3ae0f5be1e8b9dd8caf6ceec9af1b6855d9d48)
1098ca2bdSWarner Losh /*-
2a94100faSBill Paul  * Copyright (c) 1997, 1998-2003
3a94100faSBill Paul  *	Bill Paul <wpaul@windriver.com>.  All rights reserved.
4a94100faSBill Paul  *
5a94100faSBill Paul  * Redistribution and use in source and binary forms, with or without
6a94100faSBill Paul  * modification, are permitted provided that the following conditions
7a94100faSBill Paul  * are met:
8a94100faSBill Paul  * 1. Redistributions of source code must retain the above copyright
9a94100faSBill Paul  *    notice, this list of conditions and the following disclaimer.
10a94100faSBill Paul  * 2. Redistributions in binary form must reproduce the above copyright
11a94100faSBill Paul  *    notice, this list of conditions and the following disclaimer in the
12a94100faSBill Paul  *    documentation and/or other materials provided with the distribution.
13a94100faSBill Paul  * 3. All advertising materials mentioning features or use of this software
14a94100faSBill Paul  *    must display the following acknowledgement:
15a94100faSBill Paul  *	This product includes software developed by Bill Paul.
16a94100faSBill Paul  * 4. Neither the name of the author nor the names of any co-contributors
17a94100faSBill Paul  *    may be used to endorse or promote products derived from this software
18a94100faSBill Paul  *    without specific prior written permission.
19a94100faSBill Paul  *
20a94100faSBill Paul  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21a94100faSBill Paul  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22a94100faSBill Paul  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23a94100faSBill Paul  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24a94100faSBill Paul  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25a94100faSBill Paul  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26a94100faSBill Paul  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27a94100faSBill Paul  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28a94100faSBill Paul  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29a94100faSBill Paul  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30a94100faSBill Paul  * THE POSSIBILITY OF SUCH DAMAGE.
31a94100faSBill Paul  */
32a94100faSBill Paul 
334dc52c32SDavid E. O'Brien #include <sys/cdefs.h>
344dc52c32SDavid E. O'Brien __FBSDID("$FreeBSD$");
354dc52c32SDavid E. O'Brien 
36a94100faSBill Paul /*
37ed510fb0SBill Paul  * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver
38a94100faSBill Paul  *
39a94100faSBill Paul  * Written by Bill Paul <wpaul@windriver.com>
40a94100faSBill Paul  * Senior Networking Software Engineer
41a94100faSBill Paul  * Wind River Systems
42a94100faSBill Paul  */
43a94100faSBill Paul 
44a94100faSBill Paul /*
45a94100faSBill Paul  * This driver is designed to support RealTek's next generation of
46a94100faSBill Paul  * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
47ed510fb0SBill Paul  * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S,
48ed510fb0SBill Paul  * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E.
49a94100faSBill Paul  *
50a94100faSBill Paul  * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
51a94100faSBill Paul  * with the older 8139 family, however it also supports a special
52a94100faSBill Paul  * C+ mode of operation that provides several new performance enhancing
53a94100faSBill Paul  * features. These include:
54a94100faSBill Paul  *
55a94100faSBill Paul  *	o Descriptor based DMA mechanism. Each descriptor represents
56a94100faSBill Paul  *	  a single packet fragment. Data buffers may be aligned on
57a94100faSBill Paul  *	  any byte boundary.
58a94100faSBill Paul  *
59a94100faSBill Paul  *	o 64-bit DMA
60a94100faSBill Paul  *
61a94100faSBill Paul  *	o TCP/IP checksum offload for both RX and TX
62a94100faSBill Paul  *
63a94100faSBill Paul  *	o High and normal priority transmit DMA rings
64a94100faSBill Paul  *
65a94100faSBill Paul  *	o VLAN tag insertion and extraction
66a94100faSBill Paul  *
67a94100faSBill Paul  *	o TCP large send (segmentation offload)
68a94100faSBill Paul  *
69a94100faSBill Paul  * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
70a94100faSBill Paul  * programming API is fairly straightforward. The RX filtering, EEPROM
71a94100faSBill Paul  * access and PHY access is the same as it is on the older 8139 series
72a94100faSBill Paul  * chips.
73a94100faSBill Paul  *
74a94100faSBill Paul  * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
75a94100faSBill Paul  * same programming API and feature set as the 8139C+ with the following
76a94100faSBill Paul  * differences and additions:
77a94100faSBill Paul  *
78a94100faSBill Paul  *	o 1000Mbps mode
79a94100faSBill Paul  *
80a94100faSBill Paul  *	o Jumbo frames
81a94100faSBill Paul  *
82a94100faSBill Paul  *	o GMII and TBI ports/registers for interfacing with copper
83a94100faSBill Paul  *	  or fiber PHYs
84a94100faSBill Paul  *
85a94100faSBill Paul  *	o RX and TX DMA rings can have up to 1024 descriptors
86a94100faSBill Paul  *	  (the 8139C+ allows a maximum of 64)
87a94100faSBill Paul  *
88a94100faSBill Paul  *	o Slight differences in register layout from the 8139C+
89a94100faSBill Paul  *
90a94100faSBill Paul  * The TX start and timer interrupt registers are at different locations
91a94100faSBill Paul  * on the 8169 than they are on the 8139C+. Also, the status word in the
92a94100faSBill Paul  * RX descriptor has a slightly different bit layout. The 8169 does not
93a94100faSBill Paul  * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
94a94100faSBill Paul  * copper gigE PHY.
95a94100faSBill Paul  *
96a94100faSBill Paul  * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
97a94100faSBill Paul  * (the 'S' stands for 'single-chip'). These devices have the same
98a94100faSBill Paul  * programming API as the older 8169, but also have some vendor-specific
99a94100faSBill Paul  * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
100a94100faSBill Paul  * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
101a94100faSBill Paul  *
102a94100faSBill Paul  * This driver takes advantage of the RX and TX checksum offload and
103a94100faSBill Paul  * VLAN tag insertion/extraction features. It also implements TX
104a94100faSBill Paul  * interrupt moderation using the timer interrupt registers, which
105a94100faSBill Paul  * significantly reduces TX interrupt load. There is also support
106a94100faSBill Paul  * for jumbo frames, however the 8169/8169S/8110S can not transmit
10722a11c96SJohn-Mark Gurney  * jumbo frames larger than 7440, so the max MTU possible with this
10822a11c96SJohn-Mark Gurney  * driver is 7422 bytes.
109a94100faSBill Paul  */
110a94100faSBill Paul 
111f0796cd2SGleb Smirnoff #ifdef HAVE_KERNEL_OPTION_HEADERS
112f0796cd2SGleb Smirnoff #include "opt_device_polling.h"
113f0796cd2SGleb Smirnoff #endif
114f0796cd2SGleb Smirnoff 
115a94100faSBill Paul #include <sys/param.h>
116a94100faSBill Paul #include <sys/endian.h>
117a94100faSBill Paul #include <sys/systm.h>
118a94100faSBill Paul #include <sys/sockio.h>
119a94100faSBill Paul #include <sys/mbuf.h>
120a94100faSBill Paul #include <sys/malloc.h>
121fe12f24bSPoul-Henning Kamp #include <sys/module.h>
122a94100faSBill Paul #include <sys/kernel.h>
123a94100faSBill Paul #include <sys/socket.h>
124ed510fb0SBill Paul #include <sys/lock.h>
125ed510fb0SBill Paul #include <sys/mutex.h>
1260534aae0SPyun YongHyeon #include <sys/sysctl.h>
127ed510fb0SBill Paul #include <sys/taskqueue.h>
128a94100faSBill Paul 
129a94100faSBill Paul #include <net/if.h>
130a94100faSBill Paul #include <net/if_arp.h>
131a94100faSBill Paul #include <net/ethernet.h>
132a94100faSBill Paul #include <net/if_dl.h>
133a94100faSBill Paul #include <net/if_media.h>
134fc74a9f9SBrooks Davis #include <net/if_types.h>
135a94100faSBill Paul #include <net/if_vlan_var.h>
136a94100faSBill Paul 
137a94100faSBill Paul #include <net/bpf.h>
138a94100faSBill Paul 
139a94100faSBill Paul #include <machine/bus.h>
140a94100faSBill Paul #include <machine/resource.h>
141a94100faSBill Paul #include <sys/bus.h>
142a94100faSBill Paul #include <sys/rman.h>
143a94100faSBill Paul 
144a94100faSBill Paul #include <dev/mii/mii.h>
145a94100faSBill Paul #include <dev/mii/miivar.h>
146a94100faSBill Paul 
147a94100faSBill Paul #include <dev/pci/pcireg.h>
148a94100faSBill Paul #include <dev/pci/pcivar.h>
149a94100faSBill Paul 
150d65abd66SPyun YongHyeon #include <pci/if_rlreg.h>
151d65abd66SPyun YongHyeon 
152a94100faSBill Paul MODULE_DEPEND(re, pci, 1, 1, 1);
153a94100faSBill Paul MODULE_DEPEND(re, ether, 1, 1, 1);
154a94100faSBill Paul MODULE_DEPEND(re, miibus, 1, 1, 1);
155a94100faSBill Paul 
156298bfdf3SWarner Losh /* "device miibus" required.  See GENERIC if you get errors here. */
157a94100faSBill Paul #include "miibus_if.h"
158a94100faSBill Paul 
1595774c5ffSPyun YongHyeon /* Tunables. */
160502be0f7SPyun YongHyeon static int intr_filter = 0;
161502be0f7SPyun YongHyeon TUNABLE_INT("hw.re.intr_filter", &intr_filter);
162c2d2e19cSPyun YongHyeon static int msi_disable = 0;
1635774c5ffSPyun YongHyeon TUNABLE_INT("hw.re.msi_disable", &msi_disable);
1644a58fd45SPyun YongHyeon static int msix_disable = 0;
1654a58fd45SPyun YongHyeon TUNABLE_INT("hw.re.msix_disable", &msix_disable);
1662c21710bSPyun YongHyeon static int prefer_iomap = 0;
1672c21710bSPyun YongHyeon TUNABLE_INT("hw.re.prefer_iomap", &prefer_iomap);
1685774c5ffSPyun YongHyeon 
169a94100faSBill Paul #define RE_CSUM_FEATURES    (CSUM_IP | CSUM_TCP | CSUM_UDP)
170a94100faSBill Paul 
171a94100faSBill Paul /*
172a94100faSBill Paul  * Various supported device vendors/types and their names.
173a94100faSBill Paul  */
17429658c96SDimitry Andric static const struct rl_type re_devs[] = {
1759dfcacbeSPyun YongHyeon 	{ DLINK_VENDORID, DLINK_DEVICEID_528T, 0,
17632aa5f0eSAnton Berezin 	    "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
177caa19d50SPyun YongHyeon 	{ DLINK_VENDORID, DLINK_DEVICEID_530T_REVC, 0,
178caa19d50SPyun YongHyeon 	    "D-Link DGE-530(T) Gigabit Ethernet Adapter" },
1799dfcacbeSPyun YongHyeon 	{ RT_VENDORID, RT_DEVICEID_8139, 0,
180a94100faSBill Paul 	    "RealTek 8139C+ 10/100BaseTX" },
1819dfcacbeSPyun YongHyeon 	{ RT_VENDORID, RT_DEVICEID_8101E, 0,
18254899a96SPyun YongHyeon 	    "RealTek 810xE PCIe 10/100baseTX" },
1839dfcacbeSPyun YongHyeon 	{ RT_VENDORID, RT_DEVICEID_8168, 0,
184d467ffaaSPyun YongHyeon 	    "RealTek 8168/8111 B/C/CP/D/DP/E/F PCIe Gigabit Ethernet" },
1859dfcacbeSPyun YongHyeon 	{ RT_VENDORID, RT_DEVICEID_8169, 0,
186715922d7SPyun YongHyeon 	    "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" },
1879dfcacbeSPyun YongHyeon 	{ RT_VENDORID, RT_DEVICEID_8169SC, 0,
1882ee2c3b4SRemko Lodder 	    "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
1899dfcacbeSPyun YongHyeon 	{ COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0,
190ea263191SMIHIRA Sanpei Yoshiro 	    "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" },
1919dfcacbeSPyun YongHyeon 	{ LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0,
19226390635SJohn Baldwin 	    "Linksys EG1032 (RTL8169S) Gigabit Ethernet" },
1939dfcacbeSPyun YongHyeon 	{ USR_VENDORID, USR_DEVICEID_997902, 0,
194dfdb409eSPyun YongHyeon 	    "US Robotics 997902 (RTL8169S) Gigabit Ethernet" }
195a94100faSBill Paul };
196a94100faSBill Paul 
19729658c96SDimitry Andric static const struct rl_hwrev re_hwrevs[] = {
19881eee0ebSPyun YongHyeon 	{ RL_HWREV_8139, RL_8139, "", RL_MTU },
19981eee0ebSPyun YongHyeon 	{ RL_HWREV_8139A, RL_8139, "A", RL_MTU },
20081eee0ebSPyun YongHyeon 	{ RL_HWREV_8139AG, RL_8139, "A-G", RL_MTU },
20181eee0ebSPyun YongHyeon 	{ RL_HWREV_8139B, RL_8139, "B", RL_MTU },
20281eee0ebSPyun YongHyeon 	{ RL_HWREV_8130, RL_8139, "8130", RL_MTU },
20381eee0ebSPyun YongHyeon 	{ RL_HWREV_8139C, RL_8139, "C", RL_MTU },
20481eee0ebSPyun YongHyeon 	{ RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C", RL_MTU },
20581eee0ebSPyun YongHyeon 	{ RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+", RL_MTU },
206ef278cb4SPyun YongHyeon 	{ RL_HWREV_8168B_SPIN1, RL_8169, "8168", RL_JUMBO_MTU },
20781eee0ebSPyun YongHyeon 	{ RL_HWREV_8169, RL_8169, "8169", RL_JUMBO_MTU },
20881eee0ebSPyun YongHyeon 	{ RL_HWREV_8169S, RL_8169, "8169S", RL_JUMBO_MTU },
20981eee0ebSPyun YongHyeon 	{ RL_HWREV_8110S, RL_8169, "8110S", RL_JUMBO_MTU },
21081eee0ebSPyun YongHyeon 	{ RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB", RL_JUMBO_MTU },
21181eee0ebSPyun YongHyeon 	{ RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU },
21281eee0ebSPyun YongHyeon 	{ RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL", RL_JUMBO_MTU },
21381eee0ebSPyun YongHyeon 	{ RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU },
21481eee0ebSPyun YongHyeon 	{ RL_HWREV_8100, RL_8139, "8100", RL_MTU },
21581eee0ebSPyun YongHyeon 	{ RL_HWREV_8101, RL_8139, "8101", RL_MTU },
21681eee0ebSPyun YongHyeon 	{ RL_HWREV_8100E, RL_8169, "8100E", RL_MTU },
21781eee0ebSPyun YongHyeon 	{ RL_HWREV_8101E, RL_8169, "8101E", RL_MTU },
21881eee0ebSPyun YongHyeon 	{ RL_HWREV_8102E, RL_8169, "8102E", RL_MTU },
21981eee0ebSPyun YongHyeon 	{ RL_HWREV_8102EL, RL_8169, "8102EL", RL_MTU },
22081eee0ebSPyun YongHyeon 	{ RL_HWREV_8102EL_SPIN1, RL_8169, "8102EL", RL_MTU },
22181eee0ebSPyun YongHyeon 	{ RL_HWREV_8103E, RL_8169, "8103E", RL_MTU },
22239e69201SPyun YongHyeon 	{ RL_HWREV_8401E, RL_8169, "8401E", RL_MTU },
223a9e3362aSPyun YongHyeon 	{ RL_HWREV_8402, RL_8169, "8402", RL_MTU },
22454899a96SPyun YongHyeon 	{ RL_HWREV_8105E, RL_8169, "8105E", RL_MTU },
2256b0a8e04SPyun YongHyeon 	{ RL_HWREV_8105E_SPIN1, RL_8169, "8105E", RL_MTU },
226ef278cb4SPyun YongHyeon 	{ RL_HWREV_8168B_SPIN2, RL_8169, "8168", RL_JUMBO_MTU },
227ef278cb4SPyun YongHyeon 	{ RL_HWREV_8168B_SPIN3, RL_8169, "8168", RL_JUMBO_MTU },
22881eee0ebSPyun YongHyeon 	{ RL_HWREV_8168C, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K },
22981eee0ebSPyun YongHyeon 	{ RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K },
23081eee0ebSPyun YongHyeon 	{ RL_HWREV_8168CP, RL_8169, "8168CP/8111CP", RL_JUMBO_MTU_6K },
23181eee0ebSPyun YongHyeon 	{ RL_HWREV_8168D, RL_8169, "8168D/8111D", RL_JUMBO_MTU_9K },
23281eee0ebSPyun YongHyeon 	{ RL_HWREV_8168DP, RL_8169, "8168DP/8111DP", RL_JUMBO_MTU_9K },
23381eee0ebSPyun YongHyeon 	{ RL_HWREV_8168E, RL_8169, "8168E/8111E", RL_JUMBO_MTU_9K},
23481eee0ebSPyun YongHyeon 	{ RL_HWREV_8168E_VL, RL_8169, "8168E/8111E-VL", RL_JUMBO_MTU_6K},
235d467ffaaSPyun YongHyeon 	{ RL_HWREV_8168F, RL_8169, "8168F/8111F", RL_JUMBO_MTU_9K},
236d56f7f52SPyun YongHyeon 	{ RL_HWREV_8411, RL_8169, "8411", RL_JUMBO_MTU_9K},
23781eee0ebSPyun YongHyeon 	{ 0, 0, NULL, 0 }
238a94100faSBill Paul };
239a94100faSBill Paul 
240a94100faSBill Paul static int re_probe		(device_t);
241a94100faSBill Paul static int re_attach		(device_t);
242a94100faSBill Paul static int re_detach		(device_t);
243a94100faSBill Paul 
244d65abd66SPyun YongHyeon static int re_encap		(struct rl_softc *, struct mbuf **);
245a94100faSBill Paul 
246a94100faSBill Paul static void re_dma_map_addr	(void *, bus_dma_segment_t *, int, int);
247a94100faSBill Paul static int re_allocmem		(device_t, struct rl_softc *);
248d65abd66SPyun YongHyeon static __inline void re_discard_rxbuf
249d65abd66SPyun YongHyeon 				(struct rl_softc *, int);
250d65abd66SPyun YongHyeon static int re_newbuf		(struct rl_softc *, int);
25181eee0ebSPyun YongHyeon static int re_jumbo_newbuf	(struct rl_softc *, int);
252a94100faSBill Paul static int re_rx_list_init	(struct rl_softc *);
25381eee0ebSPyun YongHyeon static int re_jrx_list_init	(struct rl_softc *);
254a94100faSBill Paul static int re_tx_list_init	(struct rl_softc *);
25522a11c96SJohn-Mark Gurney #ifdef RE_FIXUP_RX
25622a11c96SJohn-Mark Gurney static __inline void re_fixup_rx
25722a11c96SJohn-Mark Gurney 				(struct mbuf *);
25822a11c96SJohn-Mark Gurney #endif
2591abcdbd1SAttilio Rao static int re_rxeof		(struct rl_softc *, int *);
260a94100faSBill Paul static void re_txeof		(struct rl_softc *);
26197b9d4baSJohn-Mark Gurney #ifdef DEVICE_POLLING
2621abcdbd1SAttilio Rao static int re_poll		(struct ifnet *, enum poll_cmd, int);
2631abcdbd1SAttilio Rao static int re_poll_locked	(struct ifnet *, enum poll_cmd, int);
26497b9d4baSJohn-Mark Gurney #endif
265ef544f63SPaolo Pisati static int re_intr		(void *);
266502be0f7SPyun YongHyeon static void re_intr_msi		(void *);
267a94100faSBill Paul static void re_tick		(void *);
268ed510fb0SBill Paul static void re_int_task		(void *, int);
269a94100faSBill Paul static void re_start		(struct ifnet *);
270d180a66fSPyun YongHyeon static void re_start_locked	(struct ifnet *);
271a94100faSBill Paul static int re_ioctl		(struct ifnet *, u_long, caddr_t);
272a94100faSBill Paul static void re_init		(void *);
27397b9d4baSJohn-Mark Gurney static void re_init_locked	(struct rl_softc *);
274a94100faSBill Paul static void re_stop		(struct rl_softc *);
2751d545c7aSMarius Strobl static void re_watchdog		(struct rl_softc *);
276a94100faSBill Paul static int re_suspend		(device_t);
277a94100faSBill Paul static int re_resume		(device_t);
2786a087a87SPyun YongHyeon static int re_shutdown		(device_t);
279a94100faSBill Paul static int re_ifmedia_upd	(struct ifnet *);
280a94100faSBill Paul static void re_ifmedia_sts	(struct ifnet *, struct ifmediareq *);
281a94100faSBill Paul 
282a94100faSBill Paul static void re_eeprom_putbyte	(struct rl_softc *, int);
283a94100faSBill Paul static void re_eeprom_getword	(struct rl_softc *, int, u_int16_t *);
284ed510fb0SBill Paul static void re_read_eeprom	(struct rl_softc *, caddr_t, int, int);
285a94100faSBill Paul static int re_gmii_readreg	(device_t, int, int);
286a94100faSBill Paul static int re_gmii_writereg	(device_t, int, int, int);
287a94100faSBill Paul 
288a94100faSBill Paul static int re_miibus_readreg	(device_t, int, int);
289a94100faSBill Paul static int re_miibus_writereg	(device_t, int, int, int);
290a94100faSBill Paul static void re_miibus_statchg	(device_t);
291a94100faSBill Paul 
29281eee0ebSPyun YongHyeon static void re_set_jumbo	(struct rl_softc *, int);
293ff191365SJung-uk Kim static void re_set_rxmode		(struct rl_softc *);
294a94100faSBill Paul static void re_reset		(struct rl_softc *);
2957467bd53SPyun YongHyeon static void re_setwol		(struct rl_softc *);
2967467bd53SPyun YongHyeon static void re_clrwol		(struct rl_softc *);
2976830588dSPyun YongHyeon static void re_set_linkspeed	(struct rl_softc *);
298a94100faSBill Paul 
299579a6e3cSLuigi Rizzo #ifdef DEV_NETMAP	/* see ixgbe.c for details */
300579a6e3cSLuigi Rizzo #include <dev/netmap/if_re_netmap.h>
301579a6e3cSLuigi Rizzo #endif /* !DEV_NETMAP */
302579a6e3cSLuigi Rizzo 
303ed510fb0SBill Paul #ifdef RE_DIAG
304a94100faSBill Paul static int re_diag		(struct rl_softc *);
305ed510fb0SBill Paul #endif
306a94100faSBill Paul 
3070534aae0SPyun YongHyeon static void re_add_sysctls	(struct rl_softc *);
3080534aae0SPyun YongHyeon static int re_sysctl_stats	(SYSCTL_HANDLER_ARGS);
309502be0f7SPyun YongHyeon static int sysctl_int_range	(SYSCTL_HANDLER_ARGS, int, int);
310502be0f7SPyun YongHyeon static int sysctl_hw_re_int_mod	(SYSCTL_HANDLER_ARGS);
3110534aae0SPyun YongHyeon 
312a94100faSBill Paul static device_method_t re_methods[] = {
313a94100faSBill Paul 	/* Device interface */
314a94100faSBill Paul 	DEVMETHOD(device_probe,		re_probe),
315a94100faSBill Paul 	DEVMETHOD(device_attach,	re_attach),
316a94100faSBill Paul 	DEVMETHOD(device_detach,	re_detach),
317a94100faSBill Paul 	DEVMETHOD(device_suspend,	re_suspend),
318a94100faSBill Paul 	DEVMETHOD(device_resume,	re_resume),
319a94100faSBill Paul 	DEVMETHOD(device_shutdown,	re_shutdown),
320a94100faSBill Paul 
321a94100faSBill Paul 	/* MII interface */
322a94100faSBill Paul 	DEVMETHOD(miibus_readreg,	re_miibus_readreg),
323a94100faSBill Paul 	DEVMETHOD(miibus_writereg,	re_miibus_writereg),
324a94100faSBill Paul 	DEVMETHOD(miibus_statchg,	re_miibus_statchg),
325a94100faSBill Paul 
3264b7ec270SMarius Strobl 	DEVMETHOD_END
327a94100faSBill Paul };
328a94100faSBill Paul 
329a94100faSBill Paul static driver_t re_driver = {
330a94100faSBill Paul 	"re",
331a94100faSBill Paul 	re_methods,
332a94100faSBill Paul 	sizeof(struct rl_softc)
333a94100faSBill Paul };
334a94100faSBill Paul 
335a94100faSBill Paul static devclass_t re_devclass;
336a94100faSBill Paul 
337a94100faSBill Paul DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0);
338a94100faSBill Paul DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0);
339a94100faSBill Paul 
340a94100faSBill Paul #define EE_SET(x)					\
341a94100faSBill Paul 	CSR_WRITE_1(sc, RL_EECMD,			\
342a94100faSBill Paul 		CSR_READ_1(sc, RL_EECMD) | x)
343a94100faSBill Paul 
344a94100faSBill Paul #define EE_CLR(x)					\
345a94100faSBill Paul 	CSR_WRITE_1(sc, RL_EECMD,			\
346a94100faSBill Paul 		CSR_READ_1(sc, RL_EECMD) & ~x)
347a94100faSBill Paul 
348a94100faSBill Paul /*
349a94100faSBill Paul  * Send a read command and address to the EEPROM, check for ACK.
350a94100faSBill Paul  */
351a94100faSBill Paul static void
3527b5ffebfSPyun YongHyeon re_eeprom_putbyte(struct rl_softc *sc, int addr)
353a94100faSBill Paul {
3540ce0868aSPyun YongHyeon 	int			d, i;
355a94100faSBill Paul 
356ed510fb0SBill Paul 	d = addr | (RL_9346_READ << sc->rl_eewidth);
357a94100faSBill Paul 
358a94100faSBill Paul 	/*
359a94100faSBill Paul 	 * Feed in each bit and strobe the clock.
360a94100faSBill Paul 	 */
361ed510fb0SBill Paul 
362ed510fb0SBill Paul 	for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) {
363a94100faSBill Paul 		if (d & i) {
364a94100faSBill Paul 			EE_SET(RL_EE_DATAIN);
365a94100faSBill Paul 		} else {
366a94100faSBill Paul 			EE_CLR(RL_EE_DATAIN);
367a94100faSBill Paul 		}
368a94100faSBill Paul 		DELAY(100);
369a94100faSBill Paul 		EE_SET(RL_EE_CLK);
370a94100faSBill Paul 		DELAY(150);
371a94100faSBill Paul 		EE_CLR(RL_EE_CLK);
372a94100faSBill Paul 		DELAY(100);
373a94100faSBill Paul 	}
374a94100faSBill Paul }
375a94100faSBill Paul 
376a94100faSBill Paul /*
377a94100faSBill Paul  * Read a word of data stored in the EEPROM at address 'addr.'
378a94100faSBill Paul  */
379a94100faSBill Paul static void
3807b5ffebfSPyun YongHyeon re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest)
381a94100faSBill Paul {
3820ce0868aSPyun YongHyeon 	int			i;
383a94100faSBill Paul 	u_int16_t		word = 0;
384a94100faSBill Paul 
385a94100faSBill Paul 	/*
386a94100faSBill Paul 	 * Send address of word we want to read.
387a94100faSBill Paul 	 */
388a94100faSBill Paul 	re_eeprom_putbyte(sc, addr);
389a94100faSBill Paul 
390a94100faSBill Paul 	/*
391a94100faSBill Paul 	 * Start reading bits from EEPROM.
392a94100faSBill Paul 	 */
393a94100faSBill Paul 	for (i = 0x8000; i; i >>= 1) {
394a94100faSBill Paul 		EE_SET(RL_EE_CLK);
395a94100faSBill Paul 		DELAY(100);
396a94100faSBill Paul 		if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
397a94100faSBill Paul 			word |= i;
398a94100faSBill Paul 		EE_CLR(RL_EE_CLK);
399a94100faSBill Paul 		DELAY(100);
400a94100faSBill Paul 	}
401a94100faSBill Paul 
402a94100faSBill Paul 	*dest = word;
403a94100faSBill Paul }
404a94100faSBill Paul 
405a94100faSBill Paul /*
406a94100faSBill Paul  * Read a sequence of words from the EEPROM.
407a94100faSBill Paul  */
408a94100faSBill Paul static void
4097b5ffebfSPyun YongHyeon re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt)
410a94100faSBill Paul {
411a94100faSBill Paul 	int			i;
412a94100faSBill Paul 	u_int16_t		word = 0, *ptr;
413a94100faSBill Paul 
414ed510fb0SBill Paul 	CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM);
415ed510fb0SBill Paul 
416ed510fb0SBill Paul         DELAY(100);
417ed510fb0SBill Paul 
418a94100faSBill Paul 	for (i = 0; i < cnt; i++) {
419ed510fb0SBill Paul 		CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL);
420a94100faSBill Paul 		re_eeprom_getword(sc, off + i, &word);
421ed510fb0SBill Paul 		CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL);
422a94100faSBill Paul 		ptr = (u_int16_t *)(dest + (i * 2));
423be099007SPyun YongHyeon                 *ptr = word;
424a94100faSBill Paul 	}
425ed510fb0SBill Paul 
426ed510fb0SBill Paul 	CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM);
427a94100faSBill Paul }
428a94100faSBill Paul 
429a94100faSBill Paul static int
4307b5ffebfSPyun YongHyeon re_gmii_readreg(device_t dev, int phy, int reg)
431a94100faSBill Paul {
432a94100faSBill Paul 	struct rl_softc		*sc;
433a94100faSBill Paul 	u_int32_t		rval;
434a94100faSBill Paul 	int			i;
435a94100faSBill Paul 
436a94100faSBill Paul 	sc = device_get_softc(dev);
437a94100faSBill Paul 
4389bac70b8SBill Paul 	/* Let the rgephy driver read the GMEDIASTAT register */
4399bac70b8SBill Paul 
4409bac70b8SBill Paul 	if (reg == RL_GMEDIASTAT) {
4419bac70b8SBill Paul 		rval = CSR_READ_1(sc, RL_GMEDIASTAT);
4429bac70b8SBill Paul 		return (rval);
4439bac70b8SBill Paul 	}
4449bac70b8SBill Paul 
445a94100faSBill Paul 	CSR_WRITE_4(sc, RL_PHYAR, reg << 16);
446a94100faSBill Paul 
44796b774f4SPyun YongHyeon 	for (i = 0; i < RL_PHY_TIMEOUT; i++) {
448a94100faSBill Paul 		rval = CSR_READ_4(sc, RL_PHYAR);
449a94100faSBill Paul 		if (rval & RL_PHYAR_BUSY)
450a94100faSBill Paul 			break;
4512bc085c6SPyun YongHyeon 		DELAY(25);
452a94100faSBill Paul 	}
453a94100faSBill Paul 
45496b774f4SPyun YongHyeon 	if (i == RL_PHY_TIMEOUT) {
4556b9f5c94SGleb Smirnoff 		device_printf(sc->rl_dev, "PHY read failed\n");
456a94100faSBill Paul 		return (0);
457a94100faSBill Paul 	}
458a94100faSBill Paul 
4592bc085c6SPyun YongHyeon 	/*
4602bc085c6SPyun YongHyeon 	 * Controller requires a 20us delay to process next MDIO request.
4612bc085c6SPyun YongHyeon 	 */
4622bc085c6SPyun YongHyeon 	DELAY(20);
4632bc085c6SPyun YongHyeon 
464a94100faSBill Paul 	return (rval & RL_PHYAR_PHYDATA);
465a94100faSBill Paul }
466a94100faSBill Paul 
467a94100faSBill Paul static int
4687b5ffebfSPyun YongHyeon re_gmii_writereg(device_t dev, int phy, int reg, int data)
469a94100faSBill Paul {
470a94100faSBill Paul 	struct rl_softc		*sc;
471a94100faSBill Paul 	u_int32_t		rval;
472a94100faSBill Paul 	int			i;
473a94100faSBill Paul 
474a94100faSBill Paul 	sc = device_get_softc(dev);
475a94100faSBill Paul 
476a94100faSBill Paul 	CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) |
4779bac70b8SBill Paul 	    (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY);
478a94100faSBill Paul 
47996b774f4SPyun YongHyeon 	for (i = 0; i < RL_PHY_TIMEOUT; i++) {
480a94100faSBill Paul 		rval = CSR_READ_4(sc, RL_PHYAR);
481a94100faSBill Paul 		if (!(rval & RL_PHYAR_BUSY))
482a94100faSBill Paul 			break;
4832bc085c6SPyun YongHyeon 		DELAY(25);
484a94100faSBill Paul 	}
485a94100faSBill Paul 
48696b774f4SPyun YongHyeon 	if (i == RL_PHY_TIMEOUT) {
4876b9f5c94SGleb Smirnoff 		device_printf(sc->rl_dev, "PHY write failed\n");
488a94100faSBill Paul 		return (0);
489a94100faSBill Paul 	}
490a94100faSBill Paul 
4912bc085c6SPyun YongHyeon 	/*
4922bc085c6SPyun YongHyeon 	 * Controller requires a 20us delay to process next MDIO request.
4932bc085c6SPyun YongHyeon 	 */
4942bc085c6SPyun YongHyeon 	DELAY(20);
4952bc085c6SPyun YongHyeon 
496a94100faSBill Paul 	return (0);
497a94100faSBill Paul }
498a94100faSBill Paul 
499a94100faSBill Paul static int
5007b5ffebfSPyun YongHyeon re_miibus_readreg(device_t dev, int phy, int reg)
501a94100faSBill Paul {
502a94100faSBill Paul 	struct rl_softc		*sc;
503a94100faSBill Paul 	u_int16_t		rval = 0;
504a94100faSBill Paul 	u_int16_t		re8139_reg = 0;
505a94100faSBill Paul 
506a94100faSBill Paul 	sc = device_get_softc(dev);
507a94100faSBill Paul 
508a94100faSBill Paul 	if (sc->rl_type == RL_8169) {
509a94100faSBill Paul 		rval = re_gmii_readreg(dev, phy, reg);
510a94100faSBill Paul 		return (rval);
511a94100faSBill Paul 	}
512a94100faSBill Paul 
513a94100faSBill Paul 	switch (reg) {
514a94100faSBill Paul 	case MII_BMCR:
515a94100faSBill Paul 		re8139_reg = RL_BMCR;
516a94100faSBill Paul 		break;
517a94100faSBill Paul 	case MII_BMSR:
518a94100faSBill Paul 		re8139_reg = RL_BMSR;
519a94100faSBill Paul 		break;
520a94100faSBill Paul 	case MII_ANAR:
521a94100faSBill Paul 		re8139_reg = RL_ANAR;
522a94100faSBill Paul 		break;
523a94100faSBill Paul 	case MII_ANER:
524a94100faSBill Paul 		re8139_reg = RL_ANER;
525a94100faSBill Paul 		break;
526a94100faSBill Paul 	case MII_ANLPAR:
527a94100faSBill Paul 		re8139_reg = RL_LPAR;
528a94100faSBill Paul 		break;
529a94100faSBill Paul 	case MII_PHYIDR1:
530a94100faSBill Paul 	case MII_PHYIDR2:
531a94100faSBill Paul 		return (0);
532a94100faSBill Paul 	/*
533a94100faSBill Paul 	 * Allow the rlphy driver to read the media status
534a94100faSBill Paul 	 * register. If we have a link partner which does not
535a94100faSBill Paul 	 * support NWAY, this is the register which will tell
536a94100faSBill Paul 	 * us the results of parallel detection.
537a94100faSBill Paul 	 */
538a94100faSBill Paul 	case RL_MEDIASTAT:
539a94100faSBill Paul 		rval = CSR_READ_1(sc, RL_MEDIASTAT);
540a94100faSBill Paul 		return (rval);
541a94100faSBill Paul 	default:
5426b9f5c94SGleb Smirnoff 		device_printf(sc->rl_dev, "bad phy register\n");
543a94100faSBill Paul 		return (0);
544a94100faSBill Paul 	}
545a94100faSBill Paul 	rval = CSR_READ_2(sc, re8139_reg);
546baa12772SPyun YongHyeon 	if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) {
547baa12772SPyun YongHyeon 		/* 8139C+ has different bit layout. */
548baa12772SPyun YongHyeon 		rval &= ~(BMCR_LOOP | BMCR_ISO);
549baa12772SPyun YongHyeon 	}
550a94100faSBill Paul 	return (rval);
551a94100faSBill Paul }
552a94100faSBill Paul 
553a94100faSBill Paul static int
5547b5ffebfSPyun YongHyeon re_miibus_writereg(device_t dev, int phy, int reg, int data)
555a94100faSBill Paul {
556a94100faSBill Paul 	struct rl_softc		*sc;
557a94100faSBill Paul 	u_int16_t		re8139_reg = 0;
558a94100faSBill Paul 	int			rval = 0;
559a94100faSBill Paul 
560a94100faSBill Paul 	sc = device_get_softc(dev);
561a94100faSBill Paul 
562a94100faSBill Paul 	if (sc->rl_type == RL_8169) {
563a94100faSBill Paul 		rval = re_gmii_writereg(dev, phy, reg, data);
564a94100faSBill Paul 		return (rval);
565a94100faSBill Paul 	}
566a94100faSBill Paul 
567a94100faSBill Paul 	switch (reg) {
568a94100faSBill Paul 	case MII_BMCR:
569a94100faSBill Paul 		re8139_reg = RL_BMCR;
570baa12772SPyun YongHyeon 		if (sc->rl_type == RL_8139CPLUS) {
571baa12772SPyun YongHyeon 			/* 8139C+ has different bit layout. */
572baa12772SPyun YongHyeon 			data &= ~(BMCR_LOOP | BMCR_ISO);
573baa12772SPyun YongHyeon 		}
574a94100faSBill Paul 		break;
575a94100faSBill Paul 	case MII_BMSR:
576a94100faSBill Paul 		re8139_reg = RL_BMSR;
577a94100faSBill Paul 		break;
578a94100faSBill Paul 	case MII_ANAR:
579a94100faSBill Paul 		re8139_reg = RL_ANAR;
580a94100faSBill Paul 		break;
581a94100faSBill Paul 	case MII_ANER:
582a94100faSBill Paul 		re8139_reg = RL_ANER;
583a94100faSBill Paul 		break;
584a94100faSBill Paul 	case MII_ANLPAR:
585a94100faSBill Paul 		re8139_reg = RL_LPAR;
586a94100faSBill Paul 		break;
587a94100faSBill Paul 	case MII_PHYIDR1:
588a94100faSBill Paul 	case MII_PHYIDR2:
589a94100faSBill Paul 		return (0);
590a94100faSBill Paul 		break;
591a94100faSBill Paul 	default:
5926b9f5c94SGleb Smirnoff 		device_printf(sc->rl_dev, "bad phy register\n");
593a94100faSBill Paul 		return (0);
594a94100faSBill Paul 	}
595a94100faSBill Paul 	CSR_WRITE_2(sc, re8139_reg, data);
596a94100faSBill Paul 	return (0);
597a94100faSBill Paul }
598a94100faSBill Paul 
599a94100faSBill Paul static void
6007b5ffebfSPyun YongHyeon re_miibus_statchg(device_t dev)
601a94100faSBill Paul {
602130b6dfbSPyun YongHyeon 	struct rl_softc		*sc;
603130b6dfbSPyun YongHyeon 	struct ifnet		*ifp;
604130b6dfbSPyun YongHyeon 	struct mii_data		*mii;
605a11e2f18SBruce M Simpson 
606130b6dfbSPyun YongHyeon 	sc = device_get_softc(dev);
607130b6dfbSPyun YongHyeon 	mii = device_get_softc(sc->rl_miibus);
608130b6dfbSPyun YongHyeon 	ifp = sc->rl_ifp;
609130b6dfbSPyun YongHyeon 	if (mii == NULL || ifp == NULL ||
610130b6dfbSPyun YongHyeon 	    (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
611130b6dfbSPyun YongHyeon 		return;
612130b6dfbSPyun YongHyeon 
613130b6dfbSPyun YongHyeon 	sc->rl_flags &= ~RL_FLAG_LINK;
614130b6dfbSPyun YongHyeon 	if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
615130b6dfbSPyun YongHyeon 	    (IFM_ACTIVE | IFM_AVALID)) {
616130b6dfbSPyun YongHyeon 		switch (IFM_SUBTYPE(mii->mii_media_active)) {
617130b6dfbSPyun YongHyeon 		case IFM_10_T:
618130b6dfbSPyun YongHyeon 		case IFM_100_TX:
619130b6dfbSPyun YongHyeon 			sc->rl_flags |= RL_FLAG_LINK;
620130b6dfbSPyun YongHyeon 			break;
621130b6dfbSPyun YongHyeon 		case IFM_1000_T:
622130b6dfbSPyun YongHyeon 			if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0)
623130b6dfbSPyun YongHyeon 				break;
624130b6dfbSPyun YongHyeon 			sc->rl_flags |= RL_FLAG_LINK;
625130b6dfbSPyun YongHyeon 			break;
626130b6dfbSPyun YongHyeon 		default:
627130b6dfbSPyun YongHyeon 			break;
628130b6dfbSPyun YongHyeon 		}
629130b6dfbSPyun YongHyeon 	}
630130b6dfbSPyun YongHyeon 	/*
631130b6dfbSPyun YongHyeon 	 * RealTek controllers does not provide any interface to
632130b6dfbSPyun YongHyeon 	 * Tx/Rx MACs for resolved speed, duplex and flow-control
633130b6dfbSPyun YongHyeon 	 * parameters.
634130b6dfbSPyun YongHyeon 	 */
635a94100faSBill Paul }
636a94100faSBill Paul 
637a94100faSBill Paul /*
638ff191365SJung-uk Kim  * Set the RX configuration and 64-bit multicast hash filter.
639a94100faSBill Paul  */
640a94100faSBill Paul static void
641ff191365SJung-uk Kim re_set_rxmode(struct rl_softc *sc)
642a94100faSBill Paul {
643a94100faSBill Paul 	struct ifnet		*ifp;
644a94100faSBill Paul 	struct ifmultiaddr	*ifma;
645ff191365SJung-uk Kim 	uint32_t		hashes[2] = { 0, 0 };
646ff191365SJung-uk Kim 	uint32_t		h, rxfilt;
647a94100faSBill Paul 
64897b9d4baSJohn-Mark Gurney 	RL_LOCK_ASSERT(sc);
64997b9d4baSJohn-Mark Gurney 
650fc74a9f9SBrooks Davis 	ifp = sc->rl_ifp;
651a94100faSBill Paul 
652ff191365SJung-uk Kim 	rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD;
653a94100faSBill Paul 
654ff191365SJung-uk Kim 	if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
6557c103000SPyun YongHyeon 		if (ifp->if_flags & IFF_PROMISC)
6567c103000SPyun YongHyeon 			rxfilt |= RL_RXCFG_RX_ALLPHYS;
657a0637caaSPyun YongHyeon 		/*
658a0637caaSPyun YongHyeon 		 * Unlike other hardwares, we have to explicitly set
659a0637caaSPyun YongHyeon 		 * RL_RXCFG_RX_MULTI to receive multicast frames in
660a0637caaSPyun YongHyeon 		 * promiscuous mode.
661a0637caaSPyun YongHyeon 		 */
662a94100faSBill Paul 		rxfilt |= RL_RXCFG_RX_MULTI;
663ff191365SJung-uk Kim 		hashes[0] = hashes[1] = 0xffffffff;
664ff191365SJung-uk Kim 		goto done;
665a94100faSBill Paul 	}
666a94100faSBill Paul 
667eb956cd0SRobert Watson 	if_maddr_rlock(ifp);
668a94100faSBill Paul 	TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
669a94100faSBill Paul 		if (ifma->ifma_addr->sa_family != AF_LINK)
670a94100faSBill Paul 			continue;
6710e939c0cSChristian Weisgerber 		h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
6720e939c0cSChristian Weisgerber 		    ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
673a94100faSBill Paul 		if (h < 32)
674a94100faSBill Paul 			hashes[0] |= (1 << h);
675a94100faSBill Paul 		else
676a94100faSBill Paul 			hashes[1] |= (1 << (h - 32));
677a94100faSBill Paul 	}
678eb956cd0SRobert Watson 	if_maddr_runlock(ifp);
679a94100faSBill Paul 
680ff191365SJung-uk Kim 	if (hashes[0] != 0 || hashes[1] != 0) {
681bb7dfefbSBill Paul 		/*
682ff191365SJung-uk Kim 		 * For some unfathomable reason, RealTek decided to
683ff191365SJung-uk Kim 		 * reverse the order of the multicast hash registers
684ff191365SJung-uk Kim 		 * in the PCI Express parts.  This means we have to
685ff191365SJung-uk Kim 		 * write the hash pattern in reverse order for those
686ff191365SJung-uk Kim 		 * devices.
687bb7dfefbSBill Paul 		 */
688aaab4fbeSJung-uk Kim 		if ((sc->rl_flags & RL_FLAG_PCIE) != 0) {
689ff191365SJung-uk Kim 			h = bswap32(hashes[0]);
690ff191365SJung-uk Kim 			hashes[0] = bswap32(hashes[1]);
691ff191365SJung-uk Kim 			hashes[1] = h;
692ff191365SJung-uk Kim 		}
693ff191365SJung-uk Kim 		rxfilt |= RL_RXCFG_RX_MULTI;
694ff191365SJung-uk Kim 	}
695ff191365SJung-uk Kim 
696ff191365SJung-uk Kim done:
697a94100faSBill Paul 	CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
698a94100faSBill Paul 	CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
699ff191365SJung-uk Kim 	CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
700bb7dfefbSBill Paul }
701a94100faSBill Paul 
702a94100faSBill Paul static void
7037b5ffebfSPyun YongHyeon re_reset(struct rl_softc *sc)
704a94100faSBill Paul {
7050ce0868aSPyun YongHyeon 	int			i;
706a94100faSBill Paul 
70797b9d4baSJohn-Mark Gurney 	RL_LOCK_ASSERT(sc);
70897b9d4baSJohn-Mark Gurney 
709a94100faSBill Paul 	CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
710a94100faSBill Paul 
711a94100faSBill Paul 	for (i = 0; i < RL_TIMEOUT; i++) {
712a94100faSBill Paul 		DELAY(10);
713a94100faSBill Paul 		if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
714a94100faSBill Paul 			break;
715a94100faSBill Paul 	}
716a94100faSBill Paul 	if (i == RL_TIMEOUT)
7176b9f5c94SGleb Smirnoff 		device_printf(sc->rl_dev, "reset never completed!\n");
718a94100faSBill Paul 
719566ca8caSJung-uk Kim 	if ((sc->rl_flags & RL_FLAG_MACRESET) != 0)
720a94100faSBill Paul 		CSR_WRITE_1(sc, 0x82, 1);
72181eee0ebSPyun YongHyeon 	if (sc->rl_hwrev->rl_rev == RL_HWREV_8169S)
722566ca8caSJung-uk Kim 		re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0);
723a94100faSBill Paul }
724a94100faSBill Paul 
725ed510fb0SBill Paul #ifdef RE_DIAG
726ed510fb0SBill Paul 
727a94100faSBill Paul /*
728a94100faSBill Paul  * The following routine is designed to test for a defect on some
729a94100faSBill Paul  * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
730a94100faSBill Paul  * lines connected to the bus, however for a 32-bit only card, they
731a94100faSBill Paul  * should be pulled high. The result of this defect is that the
732a94100faSBill Paul  * NIC will not work right if you plug it into a 64-bit slot: DMA
733a94100faSBill Paul  * operations will be done with 64-bit transfers, which will fail
734a94100faSBill Paul  * because the 64-bit data lines aren't connected.
735a94100faSBill Paul  *
736a94100faSBill Paul  * There's no way to work around this (short of talking a soldering
737a94100faSBill Paul  * iron to the board), however we can detect it. The method we use
738a94100faSBill Paul  * here is to put the NIC into digital loopback mode, set the receiver
739a94100faSBill Paul  * to promiscuous mode, and then try to send a frame. We then compare
740a94100faSBill Paul  * the frame data we sent to what was received. If the data matches,
741a94100faSBill Paul  * then the NIC is working correctly, otherwise we know the user has
742a94100faSBill Paul  * a defective NIC which has been mistakenly plugged into a 64-bit PCI
743a94100faSBill Paul  * slot. In the latter case, there's no way the NIC can work correctly,
744a94100faSBill Paul  * so we print out a message on the console and abort the device attach.
745a94100faSBill Paul  */
746a94100faSBill Paul 
747a94100faSBill Paul static int
7487b5ffebfSPyun YongHyeon re_diag(struct rl_softc *sc)
749a94100faSBill Paul {
750fc74a9f9SBrooks Davis 	struct ifnet		*ifp = sc->rl_ifp;
751a94100faSBill Paul 	struct mbuf		*m0;
752a94100faSBill Paul 	struct ether_header	*eh;
753a94100faSBill Paul 	struct rl_desc		*cur_rx;
754a94100faSBill Paul 	u_int16_t		status;
755a94100faSBill Paul 	u_int32_t		rxstat;
756ed510fb0SBill Paul 	int			total_len, i, error = 0, phyaddr;
757a94100faSBill Paul 	u_int8_t		dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
758a94100faSBill Paul 	u_int8_t		src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
759a94100faSBill Paul 
760a94100faSBill Paul 	/* Allocate a single mbuf */
761c6499eccSGleb Smirnoff 	MGETHDR(m0, M_NOWAIT, MT_DATA);
762a94100faSBill Paul 	if (m0 == NULL)
763a94100faSBill Paul 		return (ENOBUFS);
764a94100faSBill Paul 
76597b9d4baSJohn-Mark Gurney 	RL_LOCK(sc);
76697b9d4baSJohn-Mark Gurney 
767a94100faSBill Paul 	/*
768a94100faSBill Paul 	 * Initialize the NIC in test mode. This sets the chip up
769a94100faSBill Paul 	 * so that it can send and receive frames, but performs the
770a94100faSBill Paul 	 * following special functions:
771a94100faSBill Paul 	 * - Puts receiver in promiscuous mode
772a94100faSBill Paul 	 * - Enables digital loopback mode
773a94100faSBill Paul 	 * - Leaves interrupts turned off
774a94100faSBill Paul 	 */
775a94100faSBill Paul 
776a94100faSBill Paul 	ifp->if_flags |= IFF_PROMISC;
777a94100faSBill Paul 	sc->rl_testmode = 1;
7788476c243SPyun YongHyeon 	ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
77997b9d4baSJohn-Mark Gurney 	re_init_locked(sc);
780351a76f9SPyun YongHyeon 	sc->rl_flags |= RL_FLAG_LINK;
781ed510fb0SBill Paul 	if (sc->rl_type == RL_8169)
782ed510fb0SBill Paul 		phyaddr = 1;
783ed510fb0SBill Paul 	else
784ed510fb0SBill Paul 		phyaddr = 0;
785ed510fb0SBill Paul 
786ed510fb0SBill Paul 	re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET);
787ed510fb0SBill Paul 	for (i = 0; i < RL_TIMEOUT; i++) {
788ed510fb0SBill Paul 		status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR);
789ed510fb0SBill Paul 		if (!(status & BMCR_RESET))
790ed510fb0SBill Paul 			break;
791ed510fb0SBill Paul 	}
792ed510fb0SBill Paul 
793ed510fb0SBill Paul 	re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP);
794ed510fb0SBill Paul 	CSR_WRITE_2(sc, RL_ISR, RL_INTRS);
795ed510fb0SBill Paul 
796804af9a1SBill Paul 	DELAY(100000);
797a94100faSBill Paul 
798a94100faSBill Paul 	/* Put some data in the mbuf */
799a94100faSBill Paul 
800a94100faSBill Paul 	eh = mtod(m0, struct ether_header *);
801a94100faSBill Paul 	bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN);
802a94100faSBill Paul 	bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN);
803a94100faSBill Paul 	eh->ether_type = htons(ETHERTYPE_IP);
804a94100faSBill Paul 	m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
805a94100faSBill Paul 
8067cae6651SBill Paul 	/*
8077cae6651SBill Paul 	 * Queue the packet, start transmission.
8087cae6651SBill Paul 	 * Note: IF_HANDOFF() ultimately calls re_start() for us.
8097cae6651SBill Paul 	 */
810a94100faSBill Paul 
811abc8ff44SBill Paul 	CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
81297b9d4baSJohn-Mark Gurney 	RL_UNLOCK(sc);
81352732175SMax Laier 	/* XXX: re_diag must not be called when in ALTQ mode */
8147cae6651SBill Paul 	IF_HANDOFF(&ifp->if_snd, m0, ifp);
81597b9d4baSJohn-Mark Gurney 	RL_LOCK(sc);
816a94100faSBill Paul 	m0 = NULL;
817a94100faSBill Paul 
818a94100faSBill Paul 	/* Wait for it to propagate through the chip */
819a94100faSBill Paul 
820abc8ff44SBill Paul 	DELAY(100000);
821a94100faSBill Paul 	for (i = 0; i < RL_TIMEOUT; i++) {
822a94100faSBill Paul 		status = CSR_READ_2(sc, RL_ISR);
823ed510fb0SBill Paul 		CSR_WRITE_2(sc, RL_ISR, status);
824abc8ff44SBill Paul 		if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) ==
825abc8ff44SBill Paul 		    (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK))
826a94100faSBill Paul 			break;
827a94100faSBill Paul 		DELAY(10);
828a94100faSBill Paul 	}
829a94100faSBill Paul 
830a94100faSBill Paul 	if (i == RL_TIMEOUT) {
8316b9f5c94SGleb Smirnoff 		device_printf(sc->rl_dev,
8326b9f5c94SGleb Smirnoff 		    "diagnostic failed, failed to receive packet in"
8336b9f5c94SGleb Smirnoff 		    " loopback mode\n");
834a94100faSBill Paul 		error = EIO;
835a94100faSBill Paul 		goto done;
836a94100faSBill Paul 	}
837a94100faSBill Paul 
838a94100faSBill Paul 	/*
839a94100faSBill Paul 	 * The packet should have been dumped into the first
840a94100faSBill Paul 	 * entry in the RX DMA ring. Grab it from there.
841a94100faSBill Paul 	 */
842a94100faSBill Paul 
843a94100faSBill Paul 	bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
844a94100faSBill Paul 	    sc->rl_ldata.rl_rx_list_map,
845a94100faSBill Paul 	    BUS_DMASYNC_POSTREAD);
846d65abd66SPyun YongHyeon 	bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag,
847d65abd66SPyun YongHyeon 	    sc->rl_ldata.rl_rx_desc[0].rx_dmamap,
848d65abd66SPyun YongHyeon 	    BUS_DMASYNC_POSTREAD);
849d65abd66SPyun YongHyeon 	bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag,
850d65abd66SPyun YongHyeon 	    sc->rl_ldata.rl_rx_desc[0].rx_dmamap);
851a94100faSBill Paul 
852d65abd66SPyun YongHyeon 	m0 = sc->rl_ldata.rl_rx_desc[0].rx_m;
853d65abd66SPyun YongHyeon 	sc->rl_ldata.rl_rx_desc[0].rx_m = NULL;
854a94100faSBill Paul 	eh = mtod(m0, struct ether_header *);
855a94100faSBill Paul 
856a94100faSBill Paul 	cur_rx = &sc->rl_ldata.rl_rx_list[0];
857a94100faSBill Paul 	total_len = RL_RXBYTES(cur_rx);
858a94100faSBill Paul 	rxstat = le32toh(cur_rx->rl_cmdstat);
859a94100faSBill Paul 
860a94100faSBill Paul 	if (total_len != ETHER_MIN_LEN) {
8616b9f5c94SGleb Smirnoff 		device_printf(sc->rl_dev,
8626b9f5c94SGleb Smirnoff 		    "diagnostic failed, received short packet\n");
863a94100faSBill Paul 		error = EIO;
864a94100faSBill Paul 		goto done;
865a94100faSBill Paul 	}
866a94100faSBill Paul 
867a94100faSBill Paul 	/* Test that the received packet data matches what we sent. */
868a94100faSBill Paul 
869a94100faSBill Paul 	if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) ||
870a94100faSBill Paul 	    bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) ||
871a94100faSBill Paul 	    ntohs(eh->ether_type) != ETHERTYPE_IP) {
8726b9f5c94SGleb Smirnoff 		device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n");
8736b9f5c94SGleb Smirnoff 		device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n",
874a94100faSBill Paul 		    dst, ":", src, ":", ETHERTYPE_IP);
8756b9f5c94SGleb Smirnoff 		device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n",
876a94100faSBill Paul 		    eh->ether_dhost, ":", eh->ether_shost, ":",
877a94100faSBill Paul 		    ntohs(eh->ether_type));
8786b9f5c94SGleb Smirnoff 		device_printf(sc->rl_dev, "You may have a defective 32-bit "
8796b9f5c94SGleb Smirnoff 		    "NIC plugged into a 64-bit PCI slot.\n");
8806b9f5c94SGleb Smirnoff 		device_printf(sc->rl_dev, "Please re-install the NIC in a "
8816b9f5c94SGleb Smirnoff 		    "32-bit slot for proper operation.\n");
8826b9f5c94SGleb Smirnoff 		device_printf(sc->rl_dev, "Read the re(4) man page for more "
8836b9f5c94SGleb Smirnoff 		    "details.\n");
884a94100faSBill Paul 		error = EIO;
885a94100faSBill Paul 	}
886a94100faSBill Paul 
887a94100faSBill Paul done:
888a94100faSBill Paul 	/* Turn interface off, release resources */
889a94100faSBill Paul 
890a94100faSBill Paul 	sc->rl_testmode = 0;
891351a76f9SPyun YongHyeon 	sc->rl_flags &= ~RL_FLAG_LINK;
892a94100faSBill Paul 	ifp->if_flags &= ~IFF_PROMISC;
893a94100faSBill Paul 	re_stop(sc);
894a94100faSBill Paul 	if (m0 != NULL)
895a94100faSBill Paul 		m_freem(m0);
896a94100faSBill Paul 
89797b9d4baSJohn-Mark Gurney 	RL_UNLOCK(sc);
89897b9d4baSJohn-Mark Gurney 
899a94100faSBill Paul 	return (error);
900a94100faSBill Paul }
901a94100faSBill Paul 
902ed510fb0SBill Paul #endif
903ed510fb0SBill Paul 
904a94100faSBill Paul /*
905a94100faSBill Paul  * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
906a94100faSBill Paul  * IDs against our list and return a device name if we find a match.
907a94100faSBill Paul  */
908a94100faSBill Paul static int
9097b5ffebfSPyun YongHyeon re_probe(device_t dev)
910a94100faSBill Paul {
911b3030306SMarius Strobl 	const struct rl_type	*t;
912dfdb409eSPyun YongHyeon 	uint16_t		devid, vendor;
913dfdb409eSPyun YongHyeon 	uint16_t		revid, sdevid;
914dfdb409eSPyun YongHyeon 	int			i;
915a94100faSBill Paul 
916dfdb409eSPyun YongHyeon 	vendor = pci_get_vendor(dev);
917dfdb409eSPyun YongHyeon 	devid = pci_get_device(dev);
918dfdb409eSPyun YongHyeon 	revid = pci_get_revid(dev);
919dfdb409eSPyun YongHyeon 	sdevid = pci_get_subdevice(dev);
920a94100faSBill Paul 
921dfdb409eSPyun YongHyeon 	if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) {
922dfdb409eSPyun YongHyeon 		if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) {
92326390635SJohn Baldwin 			/*
92426390635SJohn Baldwin 			 * Only attach to rev. 3 of the Linksys EG1032 adapter.
925dfdb409eSPyun YongHyeon 			 * Rev. 2 is supported by sk(4).
92626390635SJohn Baldwin 			 */
927a94100faSBill Paul 			return (ENXIO);
928a94100faSBill Paul 		}
929dfdb409eSPyun YongHyeon 	}
930dfdb409eSPyun YongHyeon 
931dfdb409eSPyun YongHyeon 	if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) {
932dfdb409eSPyun YongHyeon 		if (revid != 0x20) {
933dfdb409eSPyun YongHyeon 			/* 8139, let rl(4) take care of this device. */
934dfdb409eSPyun YongHyeon 			return (ENXIO);
935dfdb409eSPyun YongHyeon 		}
936dfdb409eSPyun YongHyeon 	}
937dfdb409eSPyun YongHyeon 
938dfdb409eSPyun YongHyeon 	t = re_devs;
939dfdb409eSPyun YongHyeon 	for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) {
940dfdb409eSPyun YongHyeon 		if (vendor == t->rl_vid && devid == t->rl_did) {
941a94100faSBill Paul 			device_set_desc(dev, t->rl_name);
942d2b677bbSWarner Losh 			return (BUS_PROBE_DEFAULT);
943a94100faSBill Paul 		}
944a94100faSBill Paul 	}
945a94100faSBill Paul 
946a94100faSBill Paul 	return (ENXIO);
947a94100faSBill Paul }
948a94100faSBill Paul 
949a94100faSBill Paul /*
950a94100faSBill Paul  * Map a single buffer address.
951a94100faSBill Paul  */
952a94100faSBill Paul 
953a94100faSBill Paul static void
9547b5ffebfSPyun YongHyeon re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
955a94100faSBill Paul {
9568fd99e38SPyun YongHyeon 	bus_addr_t		*addr;
957a94100faSBill Paul 
958a94100faSBill Paul 	if (error)
959a94100faSBill Paul 		return;
960a94100faSBill Paul 
961a94100faSBill Paul 	KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
962a94100faSBill Paul 	addr = arg;
963a94100faSBill Paul 	*addr = segs->ds_addr;
964a94100faSBill Paul }
965a94100faSBill Paul 
966a94100faSBill Paul static int
9677b5ffebfSPyun YongHyeon re_allocmem(device_t dev, struct rl_softc *sc)
968a94100faSBill Paul {
96966366ca4SPyun YongHyeon 	bus_addr_t		lowaddr;
970d65abd66SPyun YongHyeon 	bus_size_t		rx_list_size, tx_list_size;
971a94100faSBill Paul 	int			error;
972a94100faSBill Paul 	int			i;
973a94100faSBill Paul 
974d65abd66SPyun YongHyeon 	rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc);
975d65abd66SPyun YongHyeon 	tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc);
976d65abd66SPyun YongHyeon 
977d65abd66SPyun YongHyeon 	/*
978d65abd66SPyun YongHyeon 	 * Allocate the parent bus DMA tag appropriate for PCI.
979ce628393SPyun YongHyeon 	 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD
980ce628393SPyun YongHyeon 	 * register should be set. However some RealTek chips are known
981ce628393SPyun YongHyeon 	 * to be buggy on DAC handling, therefore disable DAC by limiting
982ce628393SPyun YongHyeon 	 * DMA address space to 32bit. PCIe variants of RealTek chips
98366366ca4SPyun YongHyeon 	 * may not have the limitation.
984d65abd66SPyun YongHyeon 	 */
98566366ca4SPyun YongHyeon 	lowaddr = BUS_SPACE_MAXADDR;
98666366ca4SPyun YongHyeon 	if ((sc->rl_flags & RL_FLAG_PCIE) == 0)
98766366ca4SPyun YongHyeon 		lowaddr = BUS_SPACE_MAXADDR_32BIT;
988d65abd66SPyun YongHyeon 	error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
98966366ca4SPyun YongHyeon 	    lowaddr, BUS_SPACE_MAXADDR, NULL, NULL,
990d65abd66SPyun YongHyeon 	    BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
991d65abd66SPyun YongHyeon 	    NULL, NULL, &sc->rl_parent_tag);
992d65abd66SPyun YongHyeon 	if (error) {
993d65abd66SPyun YongHyeon 		device_printf(dev, "could not allocate parent DMA tag\n");
994d65abd66SPyun YongHyeon 		return (error);
995d65abd66SPyun YongHyeon 	}
996d65abd66SPyun YongHyeon 
997d65abd66SPyun YongHyeon 	/*
998d65abd66SPyun YongHyeon 	 * Allocate map for TX mbufs.
999d65abd66SPyun YongHyeon 	 */
1000d65abd66SPyun YongHyeon 	error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0,
1001d65abd66SPyun YongHyeon 	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
1002d65abd66SPyun YongHyeon 	    NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0,
1003d65abd66SPyun YongHyeon 	    NULL, NULL, &sc->rl_ldata.rl_tx_mtag);
1004d65abd66SPyun YongHyeon 	if (error) {
1005d65abd66SPyun YongHyeon 		device_printf(dev, "could not allocate TX DMA tag\n");
1006d65abd66SPyun YongHyeon 		return (error);
1007d65abd66SPyun YongHyeon 	}
1008d65abd66SPyun YongHyeon 
1009a94100faSBill Paul 	/*
1010a94100faSBill Paul 	 * Allocate map for RX mbufs.
1011a94100faSBill Paul 	 */
1012d65abd66SPyun YongHyeon 
101381eee0ebSPyun YongHyeon 	if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
101481eee0ebSPyun YongHyeon 		error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t),
101581eee0ebSPyun YongHyeon 		    0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
101681eee0ebSPyun YongHyeon 		    MJUM9BYTES, 1, MJUM9BYTES, 0, NULL, NULL,
101781eee0ebSPyun YongHyeon 		    &sc->rl_ldata.rl_jrx_mtag);
101881eee0ebSPyun YongHyeon 		if (error) {
101981eee0ebSPyun YongHyeon 			device_printf(dev,
102081eee0ebSPyun YongHyeon 			    "could not allocate jumbo RX DMA tag\n");
102181eee0ebSPyun YongHyeon 			return (error);
102281eee0ebSPyun YongHyeon 		}
102381eee0ebSPyun YongHyeon 	}
1024d65abd66SPyun YongHyeon 	error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0,
1025d65abd66SPyun YongHyeon 	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1026d65abd66SPyun YongHyeon 	    MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag);
1027a94100faSBill Paul 	if (error) {
1028d65abd66SPyun YongHyeon 		device_printf(dev, "could not allocate RX DMA tag\n");
1029d65abd66SPyun YongHyeon 		return (error);
1030a94100faSBill Paul 	}
1031a94100faSBill Paul 
1032a94100faSBill Paul 	/*
1033a94100faSBill Paul 	 * Allocate map for TX descriptor list.
1034a94100faSBill Paul 	 */
1035a94100faSBill Paul 	error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
1036a94100faSBill Paul 	    0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1037d65abd66SPyun YongHyeon 	    NULL, tx_list_size, 1, tx_list_size, 0,
1038a94100faSBill Paul 	    NULL, NULL, &sc->rl_ldata.rl_tx_list_tag);
1039a94100faSBill Paul 	if (error) {
1040d65abd66SPyun YongHyeon 		device_printf(dev, "could not allocate TX DMA ring tag\n");
1041d65abd66SPyun YongHyeon 		return (error);
1042a94100faSBill Paul 	}
1043a94100faSBill Paul 
1044a94100faSBill Paul 	/* Allocate DMA'able memory for the TX ring */
1045a94100faSBill Paul 
1046a94100faSBill Paul 	error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag,
1047d65abd66SPyun YongHyeon 	    (void **)&sc->rl_ldata.rl_tx_list,
1048d65abd66SPyun YongHyeon 	    BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
1049a94100faSBill Paul 	    &sc->rl_ldata.rl_tx_list_map);
1050d65abd66SPyun YongHyeon 	if (error) {
1051d65abd66SPyun YongHyeon 		device_printf(dev, "could not allocate TX DMA ring\n");
1052d65abd66SPyun YongHyeon 		return (error);
1053d65abd66SPyun YongHyeon 	}
1054a94100faSBill Paul 
1055a94100faSBill Paul 	/* Load the map for the TX ring. */
1056a94100faSBill Paul 
1057d65abd66SPyun YongHyeon 	sc->rl_ldata.rl_tx_list_addr = 0;
1058a94100faSBill Paul 	error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag,
1059a94100faSBill Paul 	     sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list,
1060d65abd66SPyun YongHyeon 	     tx_list_size, re_dma_map_addr,
1061a94100faSBill Paul 	     &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT);
1062d65abd66SPyun YongHyeon 	if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) {
1063d65abd66SPyun YongHyeon 		device_printf(dev, "could not load TX DMA ring\n");
1064d65abd66SPyun YongHyeon 		return (ENOMEM);
1065d65abd66SPyun YongHyeon 	}
1066a94100faSBill Paul 
1067a94100faSBill Paul 	/* Create DMA maps for TX buffers */
1068a94100faSBill Paul 
1069d65abd66SPyun YongHyeon 	for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) {
1070d65abd66SPyun YongHyeon 		error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0,
1071d65abd66SPyun YongHyeon 		    &sc->rl_ldata.rl_tx_desc[i].tx_dmamap);
1072a94100faSBill Paul 		if (error) {
1073d65abd66SPyun YongHyeon 			device_printf(dev, "could not create DMA map for TX\n");
1074d65abd66SPyun YongHyeon 			return (error);
1075a94100faSBill Paul 		}
1076a94100faSBill Paul 	}
1077a94100faSBill Paul 
1078a94100faSBill Paul 	/*
1079a94100faSBill Paul 	 * Allocate map for RX descriptor list.
1080a94100faSBill Paul 	 */
1081a94100faSBill Paul 	error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN,
1082a94100faSBill Paul 	    0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
1083d65abd66SPyun YongHyeon 	    NULL, rx_list_size, 1, rx_list_size, 0,
1084a94100faSBill Paul 	    NULL, NULL, &sc->rl_ldata.rl_rx_list_tag);
1085a94100faSBill Paul 	if (error) {
1086d65abd66SPyun YongHyeon 		device_printf(dev, "could not create RX DMA ring tag\n");
1087d65abd66SPyun YongHyeon 		return (error);
1088a94100faSBill Paul 	}
1089a94100faSBill Paul 
1090a94100faSBill Paul 	/* Allocate DMA'able memory for the RX ring */
1091a94100faSBill Paul 
1092a94100faSBill Paul 	error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag,
1093d65abd66SPyun YongHyeon 	    (void **)&sc->rl_ldata.rl_rx_list,
1094d65abd66SPyun YongHyeon 	    BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
1095a94100faSBill Paul 	    &sc->rl_ldata.rl_rx_list_map);
1096d65abd66SPyun YongHyeon 	if (error) {
1097d65abd66SPyun YongHyeon 		device_printf(dev, "could not allocate RX DMA ring\n");
1098d65abd66SPyun YongHyeon 		return (error);
1099d65abd66SPyun YongHyeon 	}
1100a94100faSBill Paul 
1101a94100faSBill Paul 	/* Load the map for the RX ring. */
1102a94100faSBill Paul 
1103d65abd66SPyun YongHyeon 	sc->rl_ldata.rl_rx_list_addr = 0;
1104a94100faSBill Paul 	error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag,
1105a94100faSBill Paul 	     sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list,
1106d65abd66SPyun YongHyeon 	     rx_list_size, re_dma_map_addr,
1107a94100faSBill Paul 	     &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT);
1108d65abd66SPyun YongHyeon 	if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) {
1109d65abd66SPyun YongHyeon 		device_printf(dev, "could not load RX DMA ring\n");
1110d65abd66SPyun YongHyeon 		return (ENOMEM);
1111d65abd66SPyun YongHyeon 	}
1112a94100faSBill Paul 
1113a94100faSBill Paul 	/* Create DMA maps for RX buffers */
1114a94100faSBill Paul 
111581eee0ebSPyun YongHyeon 	if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
111681eee0ebSPyun YongHyeon 		error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0,
111781eee0ebSPyun YongHyeon 		    &sc->rl_ldata.rl_jrx_sparemap);
111881eee0ebSPyun YongHyeon 		if (error) {
111981eee0ebSPyun YongHyeon 			device_printf(dev,
112081eee0ebSPyun YongHyeon 			    "could not create spare DMA map for jumbo RX\n");
112181eee0ebSPyun YongHyeon 			return (error);
112281eee0ebSPyun YongHyeon 		}
112381eee0ebSPyun YongHyeon 		for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
112481eee0ebSPyun YongHyeon 			error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0,
112581eee0ebSPyun YongHyeon 			    &sc->rl_ldata.rl_jrx_desc[i].rx_dmamap);
112681eee0ebSPyun YongHyeon 			if (error) {
112781eee0ebSPyun YongHyeon 				device_printf(dev,
112881eee0ebSPyun YongHyeon 				    "could not create DMA map for jumbo RX\n");
112981eee0ebSPyun YongHyeon 				return (error);
113081eee0ebSPyun YongHyeon 			}
113181eee0ebSPyun YongHyeon 		}
113281eee0ebSPyun YongHyeon 	}
1133d65abd66SPyun YongHyeon 	error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0,
1134d65abd66SPyun YongHyeon 	    &sc->rl_ldata.rl_rx_sparemap);
1135a94100faSBill Paul 	if (error) {
1136d65abd66SPyun YongHyeon 		device_printf(dev, "could not create spare DMA map for RX\n");
1137d65abd66SPyun YongHyeon 		return (error);
1138d65abd66SPyun YongHyeon 	}
1139d65abd66SPyun YongHyeon 	for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
1140d65abd66SPyun YongHyeon 		error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0,
1141d65abd66SPyun YongHyeon 		    &sc->rl_ldata.rl_rx_desc[i].rx_dmamap);
1142d65abd66SPyun YongHyeon 		if (error) {
1143d65abd66SPyun YongHyeon 			device_printf(dev, "could not create DMA map for RX\n");
1144d65abd66SPyun YongHyeon 			return (error);
1145a94100faSBill Paul 		}
1146a94100faSBill Paul 	}
1147a94100faSBill Paul 
11480534aae0SPyun YongHyeon 	/* Create DMA map for statistics. */
11490534aae0SPyun YongHyeon 	error = bus_dma_tag_create(sc->rl_parent_tag, RL_DUMP_ALIGN, 0,
11500534aae0SPyun YongHyeon 	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
11510534aae0SPyun YongHyeon 	    sizeof(struct rl_stats), 1, sizeof(struct rl_stats), 0, NULL, NULL,
11520534aae0SPyun YongHyeon 	    &sc->rl_ldata.rl_stag);
11530534aae0SPyun YongHyeon 	if (error) {
11540534aae0SPyun YongHyeon 		device_printf(dev, "could not create statistics DMA tag\n");
11550534aae0SPyun YongHyeon 		return (error);
11560534aae0SPyun YongHyeon 	}
11570534aae0SPyun YongHyeon 	/* Allocate DMA'able memory for statistics. */
11580534aae0SPyun YongHyeon 	error = bus_dmamem_alloc(sc->rl_ldata.rl_stag,
11590534aae0SPyun YongHyeon 	    (void **)&sc->rl_ldata.rl_stats,
11600534aae0SPyun YongHyeon 	    BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
11610534aae0SPyun YongHyeon 	    &sc->rl_ldata.rl_smap);
11620534aae0SPyun YongHyeon 	if (error) {
11630534aae0SPyun YongHyeon 		device_printf(dev,
11640534aae0SPyun YongHyeon 		    "could not allocate statistics DMA memory\n");
11650534aae0SPyun YongHyeon 		return (error);
11660534aae0SPyun YongHyeon 	}
11670534aae0SPyun YongHyeon 	/* Load the map for statistics. */
11680534aae0SPyun YongHyeon 	sc->rl_ldata.rl_stats_addr = 0;
11690534aae0SPyun YongHyeon 	error = bus_dmamap_load(sc->rl_ldata.rl_stag, sc->rl_ldata.rl_smap,
11700534aae0SPyun YongHyeon 	    sc->rl_ldata.rl_stats, sizeof(struct rl_stats), re_dma_map_addr,
11710534aae0SPyun YongHyeon 	     &sc->rl_ldata.rl_stats_addr, BUS_DMA_NOWAIT);
11720534aae0SPyun YongHyeon 	if (error != 0 || sc->rl_ldata.rl_stats_addr == 0) {
11730534aae0SPyun YongHyeon 		device_printf(dev, "could not load statistics DMA memory\n");
11740534aae0SPyun YongHyeon 		return (ENOMEM);
11750534aae0SPyun YongHyeon 	}
11760534aae0SPyun YongHyeon 
1177a94100faSBill Paul 	return (0);
1178a94100faSBill Paul }
1179a94100faSBill Paul 
1180a94100faSBill Paul /*
1181a94100faSBill Paul  * Attach the interface. Allocate softc structures, do ifmedia
1182a94100faSBill Paul  * setup and ethernet/BPF attach.
1183a94100faSBill Paul  */
1184a94100faSBill Paul static int
11857b5ffebfSPyun YongHyeon re_attach(device_t dev)
1186a94100faSBill Paul {
1187a94100faSBill Paul 	u_char			eaddr[ETHER_ADDR_LEN];
1188be099007SPyun YongHyeon 	u_int16_t		as[ETHER_ADDR_LEN / 2];
1189a94100faSBill Paul 	struct rl_softc		*sc;
1190a94100faSBill Paul 	struct ifnet		*ifp;
1191b3030306SMarius Strobl 	const struct rl_hwrev	*hw_rev;
1192017f1c8dSPyun YongHyeon 	u_int32_t		cap, ctl;
1193a94100faSBill Paul 	int			hwrev;
1194ace7ed5dSPyun YongHyeon 	u_int16_t		devid, re_did = 0;
11958e5d93dbSMarius Strobl 	int			error = 0, i, phy, rid;
11964a58fd45SPyun YongHyeon 	int			msic, msixc, reg;
119703ca7ae8SPyun YongHyeon 	uint8_t			cfg;
1198a94100faSBill Paul 
1199a94100faSBill Paul 	sc = device_get_softc(dev);
1200ed510fb0SBill Paul 	sc->rl_dev = dev;
1201a94100faSBill Paul 
1202a94100faSBill Paul 	mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
120397b9d4baSJohn-Mark Gurney 	    MTX_DEF);
1204d1754a9bSJohn Baldwin 	callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
1205d1754a9bSJohn Baldwin 
1206a94100faSBill Paul 	/*
1207a94100faSBill Paul 	 * Map control/status registers.
1208a94100faSBill Paul 	 */
1209a94100faSBill Paul 	pci_enable_busmaster(dev);
1210a94100faSBill Paul 
1211ace7ed5dSPyun YongHyeon 	devid = pci_get_device(dev);
12122c21710bSPyun YongHyeon 	/*
12132c21710bSPyun YongHyeon 	 * Prefer memory space register mapping over IO space.
12142c21710bSPyun YongHyeon 	 * Because RTL8169SC does not seem to work when memory mapping
12152c21710bSPyun YongHyeon 	 * is used always activate io mapping.
12162c21710bSPyun YongHyeon 	 */
12172c21710bSPyun YongHyeon 	if (devid == RT_DEVICEID_8169SC)
12182c21710bSPyun YongHyeon 		prefer_iomap = 1;
12192c21710bSPyun YongHyeon 	if (prefer_iomap == 0) {
1220ace7ed5dSPyun YongHyeon 		sc->rl_res_id = PCIR_BAR(1);
1221ace7ed5dSPyun YongHyeon 		sc->rl_res_type = SYS_RES_MEMORY;
1222ace7ed5dSPyun YongHyeon 		/* RTL8168/8101E seems to use different BARs. */
1223ace7ed5dSPyun YongHyeon 		if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E)
1224ace7ed5dSPyun YongHyeon 			sc->rl_res_id = PCIR_BAR(2);
12252c21710bSPyun YongHyeon 	} else {
12262c21710bSPyun YongHyeon 		sc->rl_res_id = PCIR_BAR(0);
12272c21710bSPyun YongHyeon 		sc->rl_res_type = SYS_RES_IOPORT;
12282c21710bSPyun YongHyeon 	}
1229ace7ed5dSPyun YongHyeon 	sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
1230ace7ed5dSPyun YongHyeon 	    &sc->rl_res_id, RF_ACTIVE);
12312c21710bSPyun YongHyeon 	if (sc->rl_res == NULL && prefer_iomap == 0) {
1232ace7ed5dSPyun YongHyeon 		sc->rl_res_id = PCIR_BAR(0);
1233ace7ed5dSPyun YongHyeon 		sc->rl_res_type = SYS_RES_IOPORT;
1234ace7ed5dSPyun YongHyeon 		sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type,
1235ace7ed5dSPyun YongHyeon 		    &sc->rl_res_id, RF_ACTIVE);
12362c21710bSPyun YongHyeon 	}
1237ace7ed5dSPyun YongHyeon 	if (sc->rl_res == NULL) {
1238d1754a9bSJohn Baldwin 		device_printf(dev, "couldn't map ports/memory\n");
1239a94100faSBill Paul 		error = ENXIO;
1240a94100faSBill Paul 		goto fail;
1241a94100faSBill Paul 	}
1242a94100faSBill Paul 
1243a94100faSBill Paul 	sc->rl_btag = rman_get_bustag(sc->rl_res);
1244a94100faSBill Paul 	sc->rl_bhandle = rman_get_bushandle(sc->rl_res);
1245a94100faSBill Paul 
12465774c5ffSPyun YongHyeon 	msic = pci_msi_count(dev);
12474a58fd45SPyun YongHyeon 	msixc = pci_msix_count(dev);
1248017f1c8dSPyun YongHyeon 	if (pci_find_cap(dev, PCIY_EXPRESS, &reg) == 0) {
12494a58fd45SPyun YongHyeon 		sc->rl_flags |= RL_FLAG_PCIE;
1250017f1c8dSPyun YongHyeon 		sc->rl_expcap = reg;
1251017f1c8dSPyun YongHyeon 	}
12524a58fd45SPyun YongHyeon 	if (bootverbose) {
12535774c5ffSPyun YongHyeon 		device_printf(dev, "MSI count : %d\n", msic);
12544a58fd45SPyun YongHyeon 		device_printf(dev, "MSI-X count : %d\n", msixc);
12555774c5ffSPyun YongHyeon 	}
12564a58fd45SPyun YongHyeon 	if (msix_disable > 0)
12574a58fd45SPyun YongHyeon 		msixc = 0;
12584a58fd45SPyun YongHyeon 	if (msi_disable > 0)
12594a58fd45SPyun YongHyeon 		msic = 0;
12604a58fd45SPyun YongHyeon 	/* Prefer MSI-X to MSI. */
12614a58fd45SPyun YongHyeon 	if (msixc > 0) {
12624a58fd45SPyun YongHyeon 		msixc = 1;
12634a58fd45SPyun YongHyeon 		rid = PCIR_BAR(4);
12644a58fd45SPyun YongHyeon 		sc->rl_res_pba = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
12654a58fd45SPyun YongHyeon 		    &rid, RF_ACTIVE);
12664a58fd45SPyun YongHyeon 		if (sc->rl_res_pba == NULL) {
12674a58fd45SPyun YongHyeon 			device_printf(sc->rl_dev,
12684a58fd45SPyun YongHyeon 			    "could not allocate MSI-X PBA resource\n");
12694a58fd45SPyun YongHyeon 		}
12704a58fd45SPyun YongHyeon 		if (sc->rl_res_pba != NULL &&
12714a58fd45SPyun YongHyeon 		    pci_alloc_msix(dev, &msixc) == 0) {
12724a58fd45SPyun YongHyeon 			if (msixc == 1) {
12734a58fd45SPyun YongHyeon 				device_printf(dev, "Using %d MSI-X message\n",
12744a58fd45SPyun YongHyeon 				    msixc);
12754a58fd45SPyun YongHyeon 				sc->rl_flags |= RL_FLAG_MSIX;
12764a58fd45SPyun YongHyeon 			} else
12774a58fd45SPyun YongHyeon 				pci_release_msi(dev);
12784a58fd45SPyun YongHyeon 		}
12794a58fd45SPyun YongHyeon 		if ((sc->rl_flags & RL_FLAG_MSIX) == 0) {
12804a58fd45SPyun YongHyeon 			if (sc->rl_res_pba != NULL)
12814a58fd45SPyun YongHyeon 				bus_release_resource(dev, SYS_RES_MEMORY, rid,
12824a58fd45SPyun YongHyeon 				    sc->rl_res_pba);
12834a58fd45SPyun YongHyeon 			sc->rl_res_pba = NULL;
12844a58fd45SPyun YongHyeon 			msixc = 0;
12854a58fd45SPyun YongHyeon 		}
12864a58fd45SPyun YongHyeon 	}
12874a58fd45SPyun YongHyeon 	/* Prefer MSI to INTx. */
12884a58fd45SPyun YongHyeon 	if (msixc == 0 && msic > 0) {
1289f1bb696aSPyun YongHyeon 		msic = 1;
12905774c5ffSPyun YongHyeon 		if (pci_alloc_msi(dev, &msic) == 0) {
12915774c5ffSPyun YongHyeon 			if (msic == RL_MSI_MESSAGES) {
12924a58fd45SPyun YongHyeon 				device_printf(dev, "Using %d MSI message\n",
12935774c5ffSPyun YongHyeon 				    msic);
1294351a76f9SPyun YongHyeon 				sc->rl_flags |= RL_FLAG_MSI;
1295339a44fbSPyun YongHyeon 				/* Explicitly set MSI enable bit. */
1296339a44fbSPyun YongHyeon 				CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
1297339a44fbSPyun YongHyeon 				cfg = CSR_READ_1(sc, RL_CFG2);
1298339a44fbSPyun YongHyeon 				cfg |= RL_CFG2_MSI;
1299339a44fbSPyun YongHyeon 				CSR_WRITE_1(sc, RL_CFG2, cfg);
1300f98dd8cfSPyun YongHyeon 				CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
13015774c5ffSPyun YongHyeon 			} else
13025774c5ffSPyun YongHyeon 				pci_release_msi(dev);
13035774c5ffSPyun YongHyeon 		}
13044a58fd45SPyun YongHyeon 		if ((sc->rl_flags & RL_FLAG_MSI) == 0)
13054a58fd45SPyun YongHyeon 			msic = 0;
13065774c5ffSPyun YongHyeon 	}
1307a94100faSBill Paul 
13085774c5ffSPyun YongHyeon 	/* Allocate interrupt */
13094a58fd45SPyun YongHyeon 	if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) {
13105774c5ffSPyun YongHyeon 		rid = 0;
13115774c5ffSPyun YongHyeon 		sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
13125774c5ffSPyun YongHyeon 		    RF_SHAREABLE | RF_ACTIVE);
13135774c5ffSPyun YongHyeon 		if (sc->rl_irq[0] == NULL) {
13145774c5ffSPyun YongHyeon 			device_printf(dev, "couldn't allocate IRQ resources\n");
1315a94100faSBill Paul 			error = ENXIO;
1316a94100faSBill Paul 			goto fail;
1317a94100faSBill Paul 		}
13185774c5ffSPyun YongHyeon 	} else {
13195774c5ffSPyun YongHyeon 		for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) {
13205774c5ffSPyun YongHyeon 			sc->rl_irq[i] = bus_alloc_resource_any(dev,
13215774c5ffSPyun YongHyeon 			    SYS_RES_IRQ, &rid, RF_ACTIVE);
13225774c5ffSPyun YongHyeon 			if (sc->rl_irq[i] == NULL) {
13235774c5ffSPyun YongHyeon 				device_printf(dev,
13242df05392SSergey Kandaurov 				    "couldn't allocate IRQ resources for "
13255774c5ffSPyun YongHyeon 				    "message %d\n", rid);
13265774c5ffSPyun YongHyeon 				error = ENXIO;
13275774c5ffSPyun YongHyeon 				goto fail;
13285774c5ffSPyun YongHyeon 			}
13295774c5ffSPyun YongHyeon 		}
13305774c5ffSPyun YongHyeon 	}
1331a94100faSBill Paul 
13324d2bf239SPyun YongHyeon 	if ((sc->rl_flags & RL_FLAG_MSI) == 0) {
13334d2bf239SPyun YongHyeon 		CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
13344d2bf239SPyun YongHyeon 		cfg = CSR_READ_1(sc, RL_CFG2);
13354d2bf239SPyun YongHyeon 		if ((cfg & RL_CFG2_MSI) != 0) {
13364d2bf239SPyun YongHyeon 			device_printf(dev, "turning off MSI enable bit.\n");
13374d2bf239SPyun YongHyeon 			cfg &= ~RL_CFG2_MSI;
13384d2bf239SPyun YongHyeon 			CSR_WRITE_1(sc, RL_CFG2, cfg);
13394d2bf239SPyun YongHyeon 		}
13404d2bf239SPyun YongHyeon 		CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
13414d2bf239SPyun YongHyeon 	}
13424d2bf239SPyun YongHyeon 
1343017f1c8dSPyun YongHyeon 	/* Disable ASPM L0S/L1. */
1344017f1c8dSPyun YongHyeon 	if (sc->rl_expcap != 0) {
1345017f1c8dSPyun YongHyeon 		cap = pci_read_config(dev, sc->rl_expcap +
1346389c8bd5SGavin Atkinson 		    PCIER_LINK_CAP, 2);
1347389c8bd5SGavin Atkinson 		if ((cap & PCIEM_LINK_CAP_ASPM) != 0) {
1348017f1c8dSPyun YongHyeon 			ctl = pci_read_config(dev, sc->rl_expcap +
1349389c8bd5SGavin Atkinson 			    PCIER_LINK_CTL, 2);
1350e935190aSGavin Atkinson 			if ((ctl & PCIEM_LINK_CTL_ASPMC) != 0) {
1351e935190aSGavin Atkinson 				ctl &= ~PCIEM_LINK_CTL_ASPMC;
1352017f1c8dSPyun YongHyeon 				pci_write_config(dev, sc->rl_expcap +
1353389c8bd5SGavin Atkinson 				    PCIER_LINK_CTL, ctl, 2);
1354017f1c8dSPyun YongHyeon 				device_printf(dev, "ASPM disabled\n");
1355017f1c8dSPyun YongHyeon 			}
1356017f1c8dSPyun YongHyeon 		} else
1357017f1c8dSPyun YongHyeon 			device_printf(dev, "no ASPM capability\n");
1358017f1c8dSPyun YongHyeon 	}
1359017f1c8dSPyun YongHyeon 
1360abc8ff44SBill Paul 	hw_rev = re_hwrevs;
1361a810fc83SPyun YongHyeon 	hwrev = CSR_READ_4(sc, RL_TXCFG);
1362566ca8caSJung-uk Kim 	switch (hwrev & 0x70000000) {
1363566ca8caSJung-uk Kim 	case 0x00000000:
1364566ca8caSJung-uk Kim 	case 0x10000000:
1365566ca8caSJung-uk Kim 		device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000);
1366566ca8caSJung-uk Kim 		hwrev &= (RL_TXCFG_HWREV | 0x80000000);
1367566ca8caSJung-uk Kim 		break;
1368566ca8caSJung-uk Kim 	default:
1369a810fc83SPyun YongHyeon 		device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000);
1370*fd3ae0f5SPyun YongHyeon 		sc->rl_macrev = hwrev & 0x00700000;
1371a810fc83SPyun YongHyeon 		hwrev &= RL_TXCFG_HWREV;
1372566ca8caSJung-uk Kim 		break;
1373566ca8caSJung-uk Kim 	}
1374*fd3ae0f5SPyun YongHyeon 	device_printf(dev, "MAC rev. 0x%08x\n", sc->rl_macrev);
1375abc8ff44SBill Paul 	while (hw_rev->rl_desc != NULL) {
1376abc8ff44SBill Paul 		if (hw_rev->rl_rev == hwrev) {
1377abc8ff44SBill Paul 			sc->rl_type = hw_rev->rl_type;
137881eee0ebSPyun YongHyeon 			sc->rl_hwrev = hw_rev;
1379abc8ff44SBill Paul 			break;
1380abc8ff44SBill Paul 		}
1381abc8ff44SBill Paul 		hw_rev++;
1382abc8ff44SBill Paul 	}
1383d65abd66SPyun YongHyeon 	if (hw_rev->rl_desc == NULL) {
1384a810fc83SPyun YongHyeon 		device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev);
1385d65abd66SPyun YongHyeon 		error = ENXIO;
1386d65abd66SPyun YongHyeon 		goto fail;
1387d65abd66SPyun YongHyeon 	}
1388abc8ff44SBill Paul 
1389351a76f9SPyun YongHyeon 	switch (hw_rev->rl_rev) {
1390351a76f9SPyun YongHyeon 	case RL_HWREV_8139CPLUS:
139181eee0ebSPyun YongHyeon 		sc->rl_flags |= RL_FLAG_FASTETHER | RL_FLAG_AUTOPAD;
1392351a76f9SPyun YongHyeon 		break;
1393351a76f9SPyun YongHyeon 	case RL_HWREV_8100E:
1394351a76f9SPyun YongHyeon 	case RL_HWREV_8101E:
139581eee0ebSPyun YongHyeon 		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_FASTETHER;
1396351a76f9SPyun YongHyeon 		break;
1397b1d62f0fSPyun YongHyeon 	case RL_HWREV_8102E:
1398b1d62f0fSPyun YongHyeon 	case RL_HWREV_8102EL:
13993d22427cSTai-hwa Liang 	case RL_HWREV_8102EL_SPIN1:
140081eee0ebSPyun YongHyeon 		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 |
140181eee0ebSPyun YongHyeon 		    RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP |
140281eee0ebSPyun YongHyeon 		    RL_FLAG_AUTOPAD;
1403b1d62f0fSPyun YongHyeon 		break;
14048281a098SPyun YongHyeon 	case RL_HWREV_8103E:
140581eee0ebSPyun YongHyeon 		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 |
140681eee0ebSPyun YongHyeon 		    RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP |
140781eee0ebSPyun YongHyeon 		    RL_FLAG_AUTOPAD | RL_FLAG_MACSLEEP;
14088281a098SPyun YongHyeon 		break;
140939e69201SPyun YongHyeon 	case RL_HWREV_8401E:
141054899a96SPyun YongHyeon 	case RL_HWREV_8105E:
14116b0a8e04SPyun YongHyeon 	case RL_HWREV_8105E_SPIN1:
141254899a96SPyun YongHyeon 		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
141354899a96SPyun YongHyeon 		    RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
141454899a96SPyun YongHyeon 		    RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD;
141554899a96SPyun YongHyeon 		break;
1416eef0e496SPyun YongHyeon 	case RL_HWREV_8402:
1417eef0e496SPyun YongHyeon 		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
1418eef0e496SPyun YongHyeon 		    RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
1419eef0e496SPyun YongHyeon 		    RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD |
1420eef0e496SPyun YongHyeon 		    RL_FLAG_CMDSTOP_WAIT_TXQ;
1421eef0e496SPyun YongHyeon 		break;
1422ef278cb4SPyun YongHyeon 	case RL_HWREV_8168B_SPIN1:
1423ef278cb4SPyun YongHyeon 	case RL_HWREV_8168B_SPIN2:
1424886ff602SPyun YongHyeon 		sc->rl_flags |= RL_FLAG_WOLRXENB;
1425886ff602SPyun YongHyeon 		/* FALLTHROUGH */
1426ef278cb4SPyun YongHyeon 	case RL_HWREV_8168B_SPIN3:
1427aaab4fbeSJung-uk Kim 		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT;
1428deb5c680SPyun YongHyeon 		break;
1429deb5c680SPyun YongHyeon 	case RL_HWREV_8168C_SPIN2:
143061f45a72SPyun YongHyeon 		sc->rl_flags |= RL_FLAG_MACSLEEP;
143161f45a72SPyun YongHyeon 		/* FALLTHROUGH */
143261f45a72SPyun YongHyeon 	case RL_HWREV_8168C:
1433*fd3ae0f5SPyun YongHyeon 		if (sc->rl_macrev == 0x00200000)
143461f45a72SPyun YongHyeon 			sc->rl_flags |= RL_FLAG_MACSLEEP;
143561f45a72SPyun YongHyeon 		/* FALLTHROUGH */
1436deb5c680SPyun YongHyeon 	case RL_HWREV_8168CP:
1437aaab4fbeSJung-uk Kim 		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
1438f2e491c9SPyun YongHyeon 		    RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP |
14396830588dSPyun YongHyeon 		    RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK;
1440351a76f9SPyun YongHyeon 		break;
1441df2dc2b3SPyun YongHyeon 	case RL_HWREV_8168D:
1442df2dc2b3SPyun YongHyeon 		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
1443df2dc2b3SPyun YongHyeon 		    RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
1444df2dc2b3SPyun YongHyeon 		    RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 |
1445df2dc2b3SPyun YongHyeon 		    RL_FLAG_WOL_MANLINK;
1446df2dc2b3SPyun YongHyeon 		break;
1447eef0e496SPyun YongHyeon 	case RL_HWREV_8168DP:
1448eef0e496SPyun YongHyeon 		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
1449eef0e496SPyun YongHyeon 		    RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_AUTOPAD |
14506830588dSPyun YongHyeon 		    RL_FLAG_JUMBOV2 | RL_FLAG_WAIT_TXPOLL | RL_FLAG_WOL_MANLINK;
1451eef0e496SPyun YongHyeon 		break;
1452d0c45156SPyun YongHyeon 	case RL_HWREV_8168E:
1453d0c45156SPyun YongHyeon 		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
1454d0c45156SPyun YongHyeon 		    RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
14556830588dSPyun YongHyeon 		    RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 |
14566830588dSPyun YongHyeon 		    RL_FLAG_WOL_MANLINK;
1457d0c45156SPyun YongHyeon 		break;
1458f0431c5bSPyun YongHyeon 	case RL_HWREV_8168E_VL:
1459d467ffaaSPyun YongHyeon 	case RL_HWREV_8168F:
1460d56f7f52SPyun YongHyeon 	case RL_HWREV_8411:
1461f0431c5bSPyun YongHyeon 		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
1462f0431c5bSPyun YongHyeon 		    RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP |
1463eef0e496SPyun YongHyeon 		    RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 |
14646830588dSPyun YongHyeon 		    RL_FLAG_CMDSTOP_WAIT_TXQ | RL_FLAG_WOL_MANLINK;
1465f0431c5bSPyun YongHyeon 		break;
1466566ca8caSJung-uk Kim 	case RL_HWREV_8169_8110SB:
1467566ca8caSJung-uk Kim 	case RL_HWREV_8169_8110SBL:
1468566ca8caSJung-uk Kim 	case RL_HWREV_8169_8110SC:
1469566ca8caSJung-uk Kim 	case RL_HWREV_8169_8110SCE:
1470566ca8caSJung-uk Kim 		sc->rl_flags |= RL_FLAG_PHYWAKE;
1471566ca8caSJung-uk Kim 		/* FALLTHROUGH */
14720596d7e6SPyun YongHyeon 	case RL_HWREV_8169:
14730596d7e6SPyun YongHyeon 	case RL_HWREV_8169S:
1474566ca8caSJung-uk Kim 	case RL_HWREV_8110S:
1475566ca8caSJung-uk Kim 		sc->rl_flags |= RL_FLAG_MACRESET;
1476351a76f9SPyun YongHyeon 		break;
1477351a76f9SPyun YongHyeon 	default:
1478351a76f9SPyun YongHyeon 		break;
1479351a76f9SPyun YongHyeon 	}
1480351a76f9SPyun YongHyeon 
1481e7e7593cSPyun YongHyeon 	if (sc->rl_hwrev->rl_rev == RL_HWREV_8139CPLUS) {
1482e7e7593cSPyun YongHyeon 		sc->rl_cfg0 = RL_8139_CFG0;
1483e7e7593cSPyun YongHyeon 		sc->rl_cfg1 = RL_8139_CFG1;
1484e7e7593cSPyun YongHyeon 		sc->rl_cfg2 = 0;
1485e7e7593cSPyun YongHyeon 		sc->rl_cfg3 = RL_8139_CFG3;
1486e7e7593cSPyun YongHyeon 		sc->rl_cfg4 = RL_8139_CFG4;
1487e7e7593cSPyun YongHyeon 		sc->rl_cfg5 = RL_8139_CFG5;
1488e7e7593cSPyun YongHyeon 	} else {
1489e7e7593cSPyun YongHyeon 		sc->rl_cfg0 = RL_CFG0;
1490e7e7593cSPyun YongHyeon 		sc->rl_cfg1 = RL_CFG1;
1491e7e7593cSPyun YongHyeon 		sc->rl_cfg2 = RL_CFG2;
1492e7e7593cSPyun YongHyeon 		sc->rl_cfg3 = RL_CFG3;
1493e7e7593cSPyun YongHyeon 		sc->rl_cfg4 = RL_CFG4;
1494e7e7593cSPyun YongHyeon 		sc->rl_cfg5 = RL_CFG5;
1495e7e7593cSPyun YongHyeon 	}
1496e7e7593cSPyun YongHyeon 
149793252626SPyun YongHyeon 	/* Reset the adapter. */
149893252626SPyun YongHyeon 	RL_LOCK(sc);
149993252626SPyun YongHyeon 	re_reset(sc);
150093252626SPyun YongHyeon 	RL_UNLOCK(sc);
150193252626SPyun YongHyeon 
1502deb5c680SPyun YongHyeon 	/* Enable PME. */
1503deb5c680SPyun YongHyeon 	CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
1504e7e7593cSPyun YongHyeon 	cfg = CSR_READ_1(sc, sc->rl_cfg1);
1505deb5c680SPyun YongHyeon 	cfg |= RL_CFG1_PME;
1506e7e7593cSPyun YongHyeon 	CSR_WRITE_1(sc, sc->rl_cfg1, cfg);
1507e7e7593cSPyun YongHyeon 	cfg = CSR_READ_1(sc, sc->rl_cfg5);
1508deb5c680SPyun YongHyeon 	cfg &= RL_CFG5_PME_STS;
1509e7e7593cSPyun YongHyeon 	CSR_WRITE_1(sc, sc->rl_cfg5, cfg);
1510deb5c680SPyun YongHyeon 	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1511deb5c680SPyun YongHyeon 
1512deb5c680SPyun YongHyeon 	if ((sc->rl_flags & RL_FLAG_PAR) != 0) {
1513deb5c680SPyun YongHyeon 		/*
1514deb5c680SPyun YongHyeon 		 * XXX Should have a better way to extract station
1515deb5c680SPyun YongHyeon 		 * address from EEPROM.
1516deb5c680SPyun YongHyeon 		 */
1517deb5c680SPyun YongHyeon 		for (i = 0; i < ETHER_ADDR_LEN; i++)
1518deb5c680SPyun YongHyeon 			eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i);
1519deb5c680SPyun YongHyeon 	} else {
1520141f92e7SPyun YongHyeon 		sc->rl_eewidth = RL_9356_ADDR_LEN;
1521ed510fb0SBill Paul 		re_read_eeprom(sc, (caddr_t)&re_did, 0, 1);
1522a94100faSBill Paul 		if (re_did != 0x8129)
1523141f92e7SPyun YongHyeon 			sc->rl_eewidth = RL_9346_ADDR_LEN;
1524a94100faSBill Paul 
1525a94100faSBill Paul 		/*
1526a94100faSBill Paul 		 * Get station address from the EEPROM.
1527a94100faSBill Paul 		 */
1528ed510fb0SBill Paul 		re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3);
1529be099007SPyun YongHyeon 		for (i = 0; i < ETHER_ADDR_LEN / 2; i++)
1530be099007SPyun YongHyeon 			as[i] = le16toh(as[i]);
1531de8925a2SKevin Lo 		bcopy(as, eaddr, ETHER_ADDR_LEN);
1532deb5c680SPyun YongHyeon 	}
1533ed510fb0SBill Paul 
1534ed510fb0SBill Paul 	if (sc->rl_type == RL_8169) {
1535d65abd66SPyun YongHyeon 		/* Set RX length mask and number of descriptors. */
1536ed510fb0SBill Paul 		sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN;
1537ed510fb0SBill Paul 		sc->rl_txstart = RL_GTXSTART;
1538d65abd66SPyun YongHyeon 		sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT;
1539d65abd66SPyun YongHyeon 		sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT;
1540ed510fb0SBill Paul 	} else {
1541d65abd66SPyun YongHyeon 		/* Set RX length mask and number of descriptors. */
1542ed510fb0SBill Paul 		sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN;
1543ed510fb0SBill Paul 		sc->rl_txstart = RL_TXSTART;
1544d65abd66SPyun YongHyeon 		sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT;
1545d65abd66SPyun YongHyeon 		sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT;
1546abc8ff44SBill Paul 	}
15479bac70b8SBill Paul 
1548a94100faSBill Paul 	error = re_allocmem(dev, sc);
1549a94100faSBill Paul 	if (error)
1550a94100faSBill Paul 		goto fail;
15510534aae0SPyun YongHyeon 	re_add_sysctls(sc);
1552a94100faSBill Paul 
1553cd036ec1SBrooks Davis 	ifp = sc->rl_ifp = if_alloc(IFT_ETHER);
1554cd036ec1SBrooks Davis 	if (ifp == NULL) {
1555d1754a9bSJohn Baldwin 		device_printf(dev, "can not if_alloc()\n");
1556cd036ec1SBrooks Davis 		error = ENOSPC;
1557cd036ec1SBrooks Davis 		goto fail;
1558cd036ec1SBrooks Davis 	}
1559cd036ec1SBrooks Davis 
156061f45a72SPyun YongHyeon 	/* Take controller out of deep sleep mode. */
156161f45a72SPyun YongHyeon 	if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) {
156261f45a72SPyun YongHyeon 		if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80)
156361f45a72SPyun YongHyeon 			CSR_WRITE_1(sc, RL_GPIO,
156461f45a72SPyun YongHyeon 			    CSR_READ_1(sc, RL_GPIO) | 0x01);
156561f45a72SPyun YongHyeon 		else
156661f45a72SPyun YongHyeon 			CSR_WRITE_1(sc, RL_GPIO,
156761f45a72SPyun YongHyeon 			    CSR_READ_1(sc, RL_GPIO) & ~0x01);
156861f45a72SPyun YongHyeon 	}
156961f45a72SPyun YongHyeon 
1570351a76f9SPyun YongHyeon 	/* Take PHY out of power down mode. */
157139e69201SPyun YongHyeon 	if ((sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) {
1572d0c45156SPyun YongHyeon 		CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80);
157339e69201SPyun YongHyeon 		if (hw_rev->rl_rev == RL_HWREV_8401E)
157439e69201SPyun YongHyeon 			CSR_WRITE_1(sc, 0xD1, CSR_READ_1(sc, 0xD1) & ~0x08);
157539e69201SPyun YongHyeon 	}
1576351a76f9SPyun YongHyeon 	if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) {
1577351a76f9SPyun YongHyeon 		re_gmii_writereg(dev, 1, 0x1f, 0);
1578351a76f9SPyun YongHyeon 		re_gmii_writereg(dev, 1, 0x0e, 0);
1579351a76f9SPyun YongHyeon 	}
1580351a76f9SPyun YongHyeon 
1581a94100faSBill Paul 	ifp->if_softc = sc;
15829bf40edeSBrooks Davis 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1583a94100faSBill Paul 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1584a94100faSBill Paul 	ifp->if_ioctl = re_ioctl;
1585a94100faSBill Paul 	ifp->if_start = re_start;
1586bc2a1002SPyun YongHyeon 	/*
1587bc2a1002SPyun YongHyeon 	 * RTL8168/8111C generates wrong IP checksummed frame if the
1588bc2a1002SPyun YongHyeon 	 * packet has IP options so disable TX IP checksum offloading.
1589bc2a1002SPyun YongHyeon 	 */
1590bc2a1002SPyun YongHyeon 	if (sc->rl_hwrev->rl_rev == RL_HWREV_8168C ||
15913c2a957dSPyun YongHyeon 	    sc->rl_hwrev->rl_rev == RL_HWREV_8168C_SPIN2 ||
15923c2a957dSPyun YongHyeon 	    sc->rl_hwrev->rl_rev == RL_HWREV_8168CP)
1593bc2a1002SPyun YongHyeon 		ifp->if_hwassist = CSUM_TCP | CSUM_UDP;
1594bc2a1002SPyun YongHyeon 	else
1595bc2a1002SPyun YongHyeon 		ifp->if_hwassist = CSUM_IP | CSUM_TCP | CSUM_UDP;
1596bc2a1002SPyun YongHyeon 	ifp->if_hwassist |= CSUM_TSO;
1597d6d7d923SPyun YongHyeon 	ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4;
1598498bd0d3SBill Paul 	ifp->if_capenable = ifp->if_capabilities;
1599a94100faSBill Paul 	ifp->if_init = re_init;
160052732175SMax Laier 	IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN);
160152732175SMax Laier 	ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN;
160252732175SMax Laier 	IFQ_SET_READY(&ifp->if_snd);
1603a94100faSBill Paul 
1604ed510fb0SBill Paul 	TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc);
1605ed510fb0SBill Paul 
1606fed3ed71SPyun YongHyeon #define	RE_PHYAD_INTERNAL	 0
1607fed3ed71SPyun YongHyeon 
1608fed3ed71SPyun YongHyeon 	/* Do MII setup. */
1609fed3ed71SPyun YongHyeon 	phy = RE_PHYAD_INTERNAL;
1610fed3ed71SPyun YongHyeon 	if (sc->rl_type == RL_8169)
1611fed3ed71SPyun YongHyeon 		phy = 1;
1612fed3ed71SPyun YongHyeon 	error = mii_attach(dev, &sc->rl_miibus, ifp, re_ifmedia_upd,
1613fed3ed71SPyun YongHyeon 	    re_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, MIIF_DOPAUSE);
1614fed3ed71SPyun YongHyeon 	if (error != 0) {
1615fed3ed71SPyun YongHyeon 		device_printf(dev, "attaching PHYs failed\n");
1616fed3ed71SPyun YongHyeon 		goto fail;
1617fed3ed71SPyun YongHyeon 	}
1618fed3ed71SPyun YongHyeon 
1619a94100faSBill Paul 	/*
1620a94100faSBill Paul 	 * Call MI attach routine.
1621a94100faSBill Paul 	 */
1622a94100faSBill Paul 	ether_ifattach(ifp, eaddr);
1623a94100faSBill Paul 
1624960fd5b3SPyun YongHyeon 	/* VLAN capability setup */
1625960fd5b3SPyun YongHyeon 	ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
1626960fd5b3SPyun YongHyeon 	if (ifp->if_capabilities & IFCAP_HWCSUM)
1627960fd5b3SPyun YongHyeon 		ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
16287467bd53SPyun YongHyeon 	/* Enable WOL if PM is supported. */
16293b0a4aefSJohn Baldwin 	if (pci_find_cap(sc->rl_dev, PCIY_PMG, &reg) == 0)
16307467bd53SPyun YongHyeon 		ifp->if_capabilities |= IFCAP_WOL;
1631960fd5b3SPyun YongHyeon 	ifp->if_capenable = ifp->if_capabilities;
163244f7cbf5SPyun YongHyeon 	ifp->if_capenable &= ~(IFCAP_WOL_UCAST | IFCAP_WOL_MCAST);
1633a2a8420cSPyun YongHyeon 	/*
1634f9ad4da7SPyun YongHyeon 	 * Don't enable TSO by default.  It is known to generate
1635f9ad4da7SPyun YongHyeon 	 * corrupted TCP segments(bad TCP options) under certain
16362df05392SSergey Kandaurov 	 * circumstances.
1637a2a8420cSPyun YongHyeon 	 */
1638a2a8420cSPyun YongHyeon 	ifp->if_hwassist &= ~CSUM_TSO;
1639ecafbbb5SPyun YongHyeon 	ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO);
1640960fd5b3SPyun YongHyeon #ifdef DEVICE_POLLING
1641960fd5b3SPyun YongHyeon 	ifp->if_capabilities |= IFCAP_POLLING;
1642960fd5b3SPyun YongHyeon #endif
1643960fd5b3SPyun YongHyeon 	/*
1644960fd5b3SPyun YongHyeon 	 * Tell the upper layer(s) we support long frames.
1645960fd5b3SPyun YongHyeon 	 * Must appear after the call to ether_ifattach() because
1646960fd5b3SPyun YongHyeon 	 * ether_ifattach() sets ifi_hdrlen to the default value.
1647960fd5b3SPyun YongHyeon 	 */
1648960fd5b3SPyun YongHyeon 	ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1649960fd5b3SPyun YongHyeon 
1650579a6e3cSLuigi Rizzo #ifdef DEV_NETMAP
1651579a6e3cSLuigi Rizzo 	re_netmap_attach(sc);
1652579a6e3cSLuigi Rizzo #endif /* DEV_NETMAP */
1653ed510fb0SBill Paul #ifdef RE_DIAG
1654ed510fb0SBill Paul 	/*
1655ed510fb0SBill Paul 	 * Perform hardware diagnostic on the original RTL8169.
1656ed510fb0SBill Paul 	 * Some 32-bit cards were incorrectly wired and would
1657ed510fb0SBill Paul 	 * malfunction if plugged into a 64-bit slot.
1658ed510fb0SBill Paul 	 */
1659a94100faSBill Paul 
1660ed510fb0SBill Paul 	if (hwrev == RL_HWREV_8169) {
1661ed510fb0SBill Paul 		error = re_diag(sc);
1662a94100faSBill Paul 		if (error) {
1663ed510fb0SBill Paul 			device_printf(dev,
1664ed510fb0SBill Paul 		    	"attach aborted due to hardware diag failure\n");
1665a94100faSBill Paul 			ether_ifdetach(ifp);
1666a94100faSBill Paul 			goto fail;
1667a94100faSBill Paul 		}
1668ed510fb0SBill Paul 	}
1669ed510fb0SBill Paul #endif
1670a94100faSBill Paul 
1671502be0f7SPyun YongHyeon #ifdef RE_TX_MODERATION
1672502be0f7SPyun YongHyeon 	intr_filter = 1;
1673502be0f7SPyun YongHyeon #endif
1674a94100faSBill Paul 	/* Hook interrupt last to avoid having to lock softc */
1675502be0f7SPyun YongHyeon 	if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 &&
1676502be0f7SPyun YongHyeon 	    intr_filter == 0) {
1677502be0f7SPyun YongHyeon 		error = bus_setup_intr(dev, sc->rl_irq[0],
1678502be0f7SPyun YongHyeon 		    INTR_TYPE_NET | INTR_MPSAFE, NULL, re_intr_msi, sc,
1679502be0f7SPyun YongHyeon 		    &sc->rl_intrhand[0]);
1680502be0f7SPyun YongHyeon 	} else {
16815774c5ffSPyun YongHyeon 		error = bus_setup_intr(dev, sc->rl_irq[0],
16825774c5ffSPyun YongHyeon 		    INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc,
16835774c5ffSPyun YongHyeon 		    &sc->rl_intrhand[0]);
16845774c5ffSPyun YongHyeon 	}
1685a94100faSBill Paul 	if (error) {
1686d1754a9bSJohn Baldwin 		device_printf(dev, "couldn't set up irq\n");
1687a94100faSBill Paul 		ether_ifdetach(ifp);
1688a94100faSBill Paul 	}
1689a94100faSBill Paul 
1690a94100faSBill Paul fail:
1691ed510fb0SBill Paul 
1692a94100faSBill Paul 	if (error)
1693a94100faSBill Paul 		re_detach(dev);
1694a94100faSBill Paul 
1695a94100faSBill Paul 	return (error);
1696a94100faSBill Paul }
1697a94100faSBill Paul 
1698a94100faSBill Paul /*
1699a94100faSBill Paul  * Shutdown hardware and free up resources. This can be called any
1700a94100faSBill Paul  * time after the mutex has been initialized. It is called in both
1701a94100faSBill Paul  * the error case in attach and the normal detach case so it needs
1702a94100faSBill Paul  * to be careful about only freeing resources that have actually been
1703a94100faSBill Paul  * allocated.
1704a94100faSBill Paul  */
1705a94100faSBill Paul static int
17067b5ffebfSPyun YongHyeon re_detach(device_t dev)
1707a94100faSBill Paul {
1708a94100faSBill Paul 	struct rl_softc		*sc;
1709a94100faSBill Paul 	struct ifnet		*ifp;
17105774c5ffSPyun YongHyeon 	int			i, rid;
1711a94100faSBill Paul 
1712a94100faSBill Paul 	sc = device_get_softc(dev);
1713fc74a9f9SBrooks Davis 	ifp = sc->rl_ifp;
1714aedd16d9SJohn-Mark Gurney 	KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized"));
171597b9d4baSJohn-Mark Gurney 
171681cf2eb6SPyun YongHyeon 	/* These should only be active if attach succeeded */
171781cf2eb6SPyun YongHyeon 	if (device_is_attached(dev)) {
171840929967SGleb Smirnoff #ifdef DEVICE_POLLING
171940929967SGleb Smirnoff 		if (ifp->if_capenable & IFCAP_POLLING)
172040929967SGleb Smirnoff 			ether_poll_deregister(ifp);
172140929967SGleb Smirnoff #endif
172297b9d4baSJohn-Mark Gurney 		RL_LOCK(sc);
172397b9d4baSJohn-Mark Gurney #if 0
172497b9d4baSJohn-Mark Gurney 		sc->suspended = 1;
172597b9d4baSJohn-Mark Gurney #endif
1726a94100faSBill Paul 		re_stop(sc);
1727525e6a87SRuslan Ermilov 		RL_UNLOCK(sc);
1728d1754a9bSJohn Baldwin 		callout_drain(&sc->rl_stat_callout);
17293d4c1b57SJohn Baldwin 		taskqueue_drain(taskqueue_fast, &sc->rl_inttask);
1730a94100faSBill Paul 		/*
1731a94100faSBill Paul 		 * Force off the IFF_UP flag here, in case someone
1732a94100faSBill Paul 		 * still had a BPF descriptor attached to this
173397b9d4baSJohn-Mark Gurney 		 * interface. If they do, ether_ifdetach() will cause
1734a94100faSBill Paul 		 * the BPF code to try and clear the promisc mode
1735a94100faSBill Paul 		 * flag, which will bubble down to re_ioctl(),
1736a94100faSBill Paul 		 * which will try to call re_init() again. This will
1737a94100faSBill Paul 		 * turn the NIC back on and restart the MII ticker,
1738a94100faSBill Paul 		 * which will panic the system when the kernel tries
1739a94100faSBill Paul 		 * to invoke the re_tick() function that isn't there
1740a94100faSBill Paul 		 * anymore.
1741a94100faSBill Paul 		 */
1742a94100faSBill Paul 		ifp->if_flags &= ~IFF_UP;
1743525e6a87SRuslan Ermilov 		ether_ifdetach(ifp);
1744a94100faSBill Paul 	}
1745a94100faSBill Paul 	if (sc->rl_miibus)
1746a94100faSBill Paul 		device_delete_child(dev, sc->rl_miibus);
1747a94100faSBill Paul 	bus_generic_detach(dev);
1748a94100faSBill Paul 
174997b9d4baSJohn-Mark Gurney 	/*
175097b9d4baSJohn-Mark Gurney 	 * The rest is resource deallocation, so we should already be
175197b9d4baSJohn-Mark Gurney 	 * stopped here.
175297b9d4baSJohn-Mark Gurney 	 */
175397b9d4baSJohn-Mark Gurney 
1754502be0f7SPyun YongHyeon 	if (sc->rl_intrhand[0] != NULL) {
1755502be0f7SPyun YongHyeon 		bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]);
1756502be0f7SPyun YongHyeon 		sc->rl_intrhand[0] = NULL;
17575774c5ffSPyun YongHyeon 	}
175882242c11SKevin Lo 	if (ifp != NULL) {
175982242c11SKevin Lo #ifdef DEV_NETMAP
176082242c11SKevin Lo 		netmap_detach(ifp);
176182242c11SKevin Lo #endif /* DEV_NETMAP */
1762ad4f426eSWarner Losh 		if_free(ifp);
176382242c11SKevin Lo 	}
1764502be0f7SPyun YongHyeon 	if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0)
1765502be0f7SPyun YongHyeon 		rid = 0;
1766502be0f7SPyun YongHyeon 	else
1767502be0f7SPyun YongHyeon 		rid = 1;
17685774c5ffSPyun YongHyeon 	if (sc->rl_irq[0] != NULL) {
1769502be0f7SPyun YongHyeon 		bus_release_resource(dev, SYS_RES_IRQ, rid, sc->rl_irq[0]);
17705774c5ffSPyun YongHyeon 		sc->rl_irq[0] = NULL;
17715774c5ffSPyun YongHyeon 	}
1772502be0f7SPyun YongHyeon 	if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0)
17735774c5ffSPyun YongHyeon 		pci_release_msi(dev);
17744a58fd45SPyun YongHyeon 	if (sc->rl_res_pba) {
17754a58fd45SPyun YongHyeon 		rid = PCIR_BAR(4);
17764a58fd45SPyun YongHyeon 		bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->rl_res_pba);
17774a58fd45SPyun YongHyeon 	}
1778a94100faSBill Paul 	if (sc->rl_res)
1779ace7ed5dSPyun YongHyeon 		bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id,
1780ace7ed5dSPyun YongHyeon 		    sc->rl_res);
1781a94100faSBill Paul 
1782a94100faSBill Paul 	/* Unload and free the RX DMA ring memory and map */
1783a94100faSBill Paul 
1784a94100faSBill Paul 	if (sc->rl_ldata.rl_rx_list_tag) {
17850534aae0SPyun YongHyeon 		if (sc->rl_ldata.rl_rx_list_map)
1786a94100faSBill Paul 			bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag,
1787a94100faSBill Paul 			    sc->rl_ldata.rl_rx_list_map);
17880534aae0SPyun YongHyeon 		if (sc->rl_ldata.rl_rx_list_map && sc->rl_ldata.rl_rx_list)
1789a94100faSBill Paul 			bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag,
1790a94100faSBill Paul 			    sc->rl_ldata.rl_rx_list,
1791a94100faSBill Paul 			    sc->rl_ldata.rl_rx_list_map);
1792a94100faSBill Paul 		bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag);
1793a94100faSBill Paul 	}
1794a94100faSBill Paul 
1795a94100faSBill Paul 	/* Unload and free the TX DMA ring memory and map */
1796a94100faSBill Paul 
1797a94100faSBill Paul 	if (sc->rl_ldata.rl_tx_list_tag) {
17980534aae0SPyun YongHyeon 		if (sc->rl_ldata.rl_tx_list_map)
1799a94100faSBill Paul 			bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag,
1800a94100faSBill Paul 			    sc->rl_ldata.rl_tx_list_map);
18010534aae0SPyun YongHyeon 		if (sc->rl_ldata.rl_tx_list_map && sc->rl_ldata.rl_tx_list)
1802a94100faSBill Paul 			bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag,
1803a94100faSBill Paul 			    sc->rl_ldata.rl_tx_list,
1804a94100faSBill Paul 			    sc->rl_ldata.rl_tx_list_map);
1805a94100faSBill Paul 		bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag);
1806a94100faSBill Paul 	}
1807a94100faSBill Paul 
1808a94100faSBill Paul 	/* Destroy all the RX and TX buffer maps */
1809a94100faSBill Paul 
1810d65abd66SPyun YongHyeon 	if (sc->rl_ldata.rl_tx_mtag) {
18119e18005dSPyun YongHyeon 		for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) {
18129e18005dSPyun YongHyeon 			if (sc->rl_ldata.rl_tx_desc[i].tx_dmamap)
1813d65abd66SPyun YongHyeon 				bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag,
1814d65abd66SPyun YongHyeon 				    sc->rl_ldata.rl_tx_desc[i].tx_dmamap);
18159e18005dSPyun YongHyeon 		}
1816d65abd66SPyun YongHyeon 		bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag);
1817d65abd66SPyun YongHyeon 	}
1818d65abd66SPyun YongHyeon 	if (sc->rl_ldata.rl_rx_mtag) {
18199e18005dSPyun YongHyeon 		for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
18209e18005dSPyun YongHyeon 			if (sc->rl_ldata.rl_rx_desc[i].rx_dmamap)
1821d65abd66SPyun YongHyeon 				bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag,
1822d65abd66SPyun YongHyeon 				    sc->rl_ldata.rl_rx_desc[i].rx_dmamap);
18239e18005dSPyun YongHyeon 		}
1824d65abd66SPyun YongHyeon 		if (sc->rl_ldata.rl_rx_sparemap)
1825d65abd66SPyun YongHyeon 			bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag,
1826d65abd66SPyun YongHyeon 			    sc->rl_ldata.rl_rx_sparemap);
1827d65abd66SPyun YongHyeon 		bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag);
1828a94100faSBill Paul 	}
182981eee0ebSPyun YongHyeon 	if (sc->rl_ldata.rl_jrx_mtag) {
183081eee0ebSPyun YongHyeon 		for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
183181eee0ebSPyun YongHyeon 			if (sc->rl_ldata.rl_jrx_desc[i].rx_dmamap)
183281eee0ebSPyun YongHyeon 				bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag,
183381eee0ebSPyun YongHyeon 				    sc->rl_ldata.rl_jrx_desc[i].rx_dmamap);
183481eee0ebSPyun YongHyeon 		}
183581eee0ebSPyun YongHyeon 		if (sc->rl_ldata.rl_jrx_sparemap)
183681eee0ebSPyun YongHyeon 			bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag,
183781eee0ebSPyun YongHyeon 			    sc->rl_ldata.rl_jrx_sparemap);
183881eee0ebSPyun YongHyeon 		bus_dma_tag_destroy(sc->rl_ldata.rl_jrx_mtag);
183981eee0ebSPyun YongHyeon 	}
1840a94100faSBill Paul 	/* Unload and free the stats buffer and map */
1841a94100faSBill Paul 
1842a94100faSBill Paul 	if (sc->rl_ldata.rl_stag) {
18430534aae0SPyun YongHyeon 		if (sc->rl_ldata.rl_smap)
1844a94100faSBill Paul 			bus_dmamap_unload(sc->rl_ldata.rl_stag,
1845a94100faSBill Paul 			    sc->rl_ldata.rl_smap);
18460534aae0SPyun YongHyeon 		if (sc->rl_ldata.rl_smap && sc->rl_ldata.rl_stats)
18470534aae0SPyun YongHyeon 			bus_dmamem_free(sc->rl_ldata.rl_stag,
18480534aae0SPyun YongHyeon 			    sc->rl_ldata.rl_stats, sc->rl_ldata.rl_smap);
1849a94100faSBill Paul 		bus_dma_tag_destroy(sc->rl_ldata.rl_stag);
1850a94100faSBill Paul 	}
1851a94100faSBill Paul 
1852a94100faSBill Paul 	if (sc->rl_parent_tag)
1853a94100faSBill Paul 		bus_dma_tag_destroy(sc->rl_parent_tag);
1854a94100faSBill Paul 
1855a94100faSBill Paul 	mtx_destroy(&sc->rl_mtx);
1856a94100faSBill Paul 
1857a94100faSBill Paul 	return (0);
1858a94100faSBill Paul }
1859a94100faSBill Paul 
1860d65abd66SPyun YongHyeon static __inline void
18617b5ffebfSPyun YongHyeon re_discard_rxbuf(struct rl_softc *sc, int idx)
1862a94100faSBill Paul {
1863d65abd66SPyun YongHyeon 	struct rl_desc		*desc;
1864d65abd66SPyun YongHyeon 	struct rl_rxdesc	*rxd;
1865d65abd66SPyun YongHyeon 	uint32_t		cmdstat;
1866a94100faSBill Paul 
186781eee0ebSPyun YongHyeon 	if (sc->rl_ifp->if_mtu > RL_MTU &&
186881eee0ebSPyun YongHyeon 	    (sc->rl_flags & RL_FLAG_JUMBOV2) != 0)
186981eee0ebSPyun YongHyeon 		rxd = &sc->rl_ldata.rl_jrx_desc[idx];
187081eee0ebSPyun YongHyeon 	else
1871d65abd66SPyun YongHyeon 		rxd = &sc->rl_ldata.rl_rx_desc[idx];
1872d65abd66SPyun YongHyeon 	desc = &sc->rl_ldata.rl_rx_list[idx];
1873d65abd66SPyun YongHyeon 	desc->rl_vlanctl = 0;
1874d65abd66SPyun YongHyeon 	cmdstat = rxd->rx_size;
1875d65abd66SPyun YongHyeon 	if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1)
1876d65abd66SPyun YongHyeon 		cmdstat |= RL_RDESC_CMD_EOR;
1877d65abd66SPyun YongHyeon 	desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN);
1878d65abd66SPyun YongHyeon }
1879d65abd66SPyun YongHyeon 
1880d65abd66SPyun YongHyeon static int
18817b5ffebfSPyun YongHyeon re_newbuf(struct rl_softc *sc, int idx)
1882d65abd66SPyun YongHyeon {
1883d65abd66SPyun YongHyeon 	struct mbuf		*m;
1884d65abd66SPyun YongHyeon 	struct rl_rxdesc	*rxd;
1885d65abd66SPyun YongHyeon 	bus_dma_segment_t	segs[1];
1886d65abd66SPyun YongHyeon 	bus_dmamap_t		map;
1887d65abd66SPyun YongHyeon 	struct rl_desc		*desc;
1888d65abd66SPyun YongHyeon 	uint32_t		cmdstat;
1889d65abd66SPyun YongHyeon 	int			error, nsegs;
1890d65abd66SPyun YongHyeon 
1891c6499eccSGleb Smirnoff 	m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1892d65abd66SPyun YongHyeon 	if (m == NULL)
1893a94100faSBill Paul 		return (ENOBUFS);
1894a94100faSBill Paul 
1895a94100faSBill Paul 	m->m_len = m->m_pkthdr.len = MCLBYTES;
189622a11c96SJohn-Mark Gurney #ifdef RE_FIXUP_RX
189722a11c96SJohn-Mark Gurney 	/*
189822a11c96SJohn-Mark Gurney 	 * This is part of an evil trick to deal with non-x86 platforms.
189922a11c96SJohn-Mark Gurney 	 * The RealTek chip requires RX buffers to be aligned on 64-bit
190022a11c96SJohn-Mark Gurney 	 * boundaries, but that will hose non-x86 machines. To get around
190122a11c96SJohn-Mark Gurney 	 * this, we leave some empty space at the start of each buffer
190222a11c96SJohn-Mark Gurney 	 * and for non-x86 hosts, we copy the buffer back six bytes
190322a11c96SJohn-Mark Gurney 	 * to achieve word alignment. This is slightly more efficient
190422a11c96SJohn-Mark Gurney 	 * than allocating a new buffer, copying the contents, and
190522a11c96SJohn-Mark Gurney 	 * discarding the old buffer.
190622a11c96SJohn-Mark Gurney 	 */
190722a11c96SJohn-Mark Gurney 	m_adj(m, RE_ETHER_ALIGN);
190822a11c96SJohn-Mark Gurney #endif
1909d65abd66SPyun YongHyeon 	error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag,
1910d65abd66SPyun YongHyeon 	    sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT);
1911d65abd66SPyun YongHyeon 	if (error != 0) {
1912d65abd66SPyun YongHyeon 		m_freem(m);
1913d65abd66SPyun YongHyeon 		return (ENOBUFS);
1914d65abd66SPyun YongHyeon 	}
1915d65abd66SPyun YongHyeon 	KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs));
1916a94100faSBill Paul 
1917d65abd66SPyun YongHyeon 	rxd = &sc->rl_ldata.rl_rx_desc[idx];
1918d65abd66SPyun YongHyeon 	if (rxd->rx_m != NULL) {
1919d65abd66SPyun YongHyeon 		bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap,
1920d65abd66SPyun YongHyeon 		    BUS_DMASYNC_POSTREAD);
1921d65abd66SPyun YongHyeon 		bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap);
1922a94100faSBill Paul 	}
1923a94100faSBill Paul 
1924d65abd66SPyun YongHyeon 	rxd->rx_m = m;
1925d65abd66SPyun YongHyeon 	map = rxd->rx_dmamap;
1926d65abd66SPyun YongHyeon 	rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap;
1927d65abd66SPyun YongHyeon 	rxd->rx_size = segs[0].ds_len;
1928d65abd66SPyun YongHyeon 	sc->rl_ldata.rl_rx_sparemap = map;
1929d65abd66SPyun YongHyeon 	bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap,
1930a94100faSBill Paul 	    BUS_DMASYNC_PREREAD);
1931a94100faSBill Paul 
1932d65abd66SPyun YongHyeon 	desc = &sc->rl_ldata.rl_rx_list[idx];
1933d65abd66SPyun YongHyeon 	desc->rl_vlanctl = 0;
1934d65abd66SPyun YongHyeon 	desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr));
1935d65abd66SPyun YongHyeon 	desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr));
1936d65abd66SPyun YongHyeon 	cmdstat = segs[0].ds_len;
1937d65abd66SPyun YongHyeon 	if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1)
1938d65abd66SPyun YongHyeon 		cmdstat |= RL_RDESC_CMD_EOR;
1939d65abd66SPyun YongHyeon 	desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN);
1940d65abd66SPyun YongHyeon 
1941a94100faSBill Paul 	return (0);
1942a94100faSBill Paul }
1943a94100faSBill Paul 
194481eee0ebSPyun YongHyeon static int
194581eee0ebSPyun YongHyeon re_jumbo_newbuf(struct rl_softc *sc, int idx)
194681eee0ebSPyun YongHyeon {
194781eee0ebSPyun YongHyeon 	struct mbuf		*m;
194881eee0ebSPyun YongHyeon 	struct rl_rxdesc	*rxd;
194981eee0ebSPyun YongHyeon 	bus_dma_segment_t	segs[1];
195081eee0ebSPyun YongHyeon 	bus_dmamap_t		map;
195181eee0ebSPyun YongHyeon 	struct rl_desc		*desc;
195281eee0ebSPyun YongHyeon 	uint32_t		cmdstat;
195381eee0ebSPyun YongHyeon 	int			error, nsegs;
195481eee0ebSPyun YongHyeon 
1955c6499eccSGleb Smirnoff 	m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
195681eee0ebSPyun YongHyeon 	if (m == NULL)
195781eee0ebSPyun YongHyeon 		return (ENOBUFS);
195881eee0ebSPyun YongHyeon 	m->m_len = m->m_pkthdr.len = MJUM9BYTES;
195981eee0ebSPyun YongHyeon #ifdef RE_FIXUP_RX
196081eee0ebSPyun YongHyeon 	m_adj(m, RE_ETHER_ALIGN);
196181eee0ebSPyun YongHyeon #endif
196281eee0ebSPyun YongHyeon 	error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_jrx_mtag,
196381eee0ebSPyun YongHyeon 	    sc->rl_ldata.rl_jrx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT);
196481eee0ebSPyun YongHyeon 	if (error != 0) {
196581eee0ebSPyun YongHyeon 		m_freem(m);
196681eee0ebSPyun YongHyeon 		return (ENOBUFS);
196781eee0ebSPyun YongHyeon 	}
196881eee0ebSPyun YongHyeon 	KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs));
196981eee0ebSPyun YongHyeon 
197081eee0ebSPyun YongHyeon 	rxd = &sc->rl_ldata.rl_jrx_desc[idx];
197181eee0ebSPyun YongHyeon 	if (rxd->rx_m != NULL) {
197281eee0ebSPyun YongHyeon 		bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap,
197381eee0ebSPyun YongHyeon 		    BUS_DMASYNC_POSTREAD);
197481eee0ebSPyun YongHyeon 		bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap);
197581eee0ebSPyun YongHyeon 	}
197681eee0ebSPyun YongHyeon 
197781eee0ebSPyun YongHyeon 	rxd->rx_m = m;
197881eee0ebSPyun YongHyeon 	map = rxd->rx_dmamap;
197981eee0ebSPyun YongHyeon 	rxd->rx_dmamap = sc->rl_ldata.rl_jrx_sparemap;
198081eee0ebSPyun YongHyeon 	rxd->rx_size = segs[0].ds_len;
198181eee0ebSPyun YongHyeon 	sc->rl_ldata.rl_jrx_sparemap = map;
198281eee0ebSPyun YongHyeon 	bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap,
198381eee0ebSPyun YongHyeon 	    BUS_DMASYNC_PREREAD);
198481eee0ebSPyun YongHyeon 
198581eee0ebSPyun YongHyeon 	desc = &sc->rl_ldata.rl_rx_list[idx];
198681eee0ebSPyun YongHyeon 	desc->rl_vlanctl = 0;
198781eee0ebSPyun YongHyeon 	desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr));
198881eee0ebSPyun YongHyeon 	desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr));
198981eee0ebSPyun YongHyeon 	cmdstat = segs[0].ds_len;
199081eee0ebSPyun YongHyeon 	if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1)
199181eee0ebSPyun YongHyeon 		cmdstat |= RL_RDESC_CMD_EOR;
199281eee0ebSPyun YongHyeon 	desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN);
199381eee0ebSPyun YongHyeon 
199481eee0ebSPyun YongHyeon 	return (0);
199581eee0ebSPyun YongHyeon }
199681eee0ebSPyun YongHyeon 
199722a11c96SJohn-Mark Gurney #ifdef RE_FIXUP_RX
199822a11c96SJohn-Mark Gurney static __inline void
19997b5ffebfSPyun YongHyeon re_fixup_rx(struct mbuf *m)
200022a11c96SJohn-Mark Gurney {
200122a11c96SJohn-Mark Gurney 	int                     i;
200222a11c96SJohn-Mark Gurney 	uint16_t                *src, *dst;
200322a11c96SJohn-Mark Gurney 
200422a11c96SJohn-Mark Gurney 	src = mtod(m, uint16_t *);
200522a11c96SJohn-Mark Gurney 	dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src;
200622a11c96SJohn-Mark Gurney 
200722a11c96SJohn-Mark Gurney 	for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
200822a11c96SJohn-Mark Gurney 		*dst++ = *src++;
200922a11c96SJohn-Mark Gurney 
201022a11c96SJohn-Mark Gurney 	m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN;
201122a11c96SJohn-Mark Gurney }
201222a11c96SJohn-Mark Gurney #endif
201322a11c96SJohn-Mark Gurney 
2014a94100faSBill Paul static int
20157b5ffebfSPyun YongHyeon re_tx_list_init(struct rl_softc *sc)
2016a94100faSBill Paul {
2017d65abd66SPyun YongHyeon 	struct rl_desc		*desc;
2018d65abd66SPyun YongHyeon 	int			i;
201997b9d4baSJohn-Mark Gurney 
202097b9d4baSJohn-Mark Gurney 	RL_LOCK_ASSERT(sc);
202197b9d4baSJohn-Mark Gurney 
2022d65abd66SPyun YongHyeon 	bzero(sc->rl_ldata.rl_tx_list,
2023d65abd66SPyun YongHyeon 	    sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc));
2024d65abd66SPyun YongHyeon 	for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++)
2025d65abd66SPyun YongHyeon 		sc->rl_ldata.rl_tx_desc[i].tx_m = NULL;
2026579a6e3cSLuigi Rizzo #ifdef DEV_NETMAP
2027579a6e3cSLuigi Rizzo 	re_netmap_tx_init(sc);
2028579a6e3cSLuigi Rizzo #endif /* DEV_NETMAP */
2029d65abd66SPyun YongHyeon 	/* Set EOR. */
2030d65abd66SPyun YongHyeon 	desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1];
2031d65abd66SPyun YongHyeon 	desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR);
2032a94100faSBill Paul 
2033a94100faSBill Paul 	bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
2034d65abd66SPyun YongHyeon 	    sc->rl_ldata.rl_tx_list_map,
2035d65abd66SPyun YongHyeon 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2036d65abd66SPyun YongHyeon 
2037a94100faSBill Paul 	sc->rl_ldata.rl_tx_prodidx = 0;
2038a94100faSBill Paul 	sc->rl_ldata.rl_tx_considx = 0;
2039d65abd66SPyun YongHyeon 	sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt;
2040a94100faSBill Paul 
2041a94100faSBill Paul 	return (0);
2042a94100faSBill Paul }
2043a94100faSBill Paul 
2044a94100faSBill Paul static int
20457b5ffebfSPyun YongHyeon re_rx_list_init(struct rl_softc *sc)
2046a94100faSBill Paul {
2047d65abd66SPyun YongHyeon 	int			error, i;
2048a94100faSBill Paul 
2049d65abd66SPyun YongHyeon 	bzero(sc->rl_ldata.rl_rx_list,
2050d65abd66SPyun YongHyeon 	    sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc));
2051d65abd66SPyun YongHyeon 	for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
2052d65abd66SPyun YongHyeon 		sc->rl_ldata.rl_rx_desc[i].rx_m = NULL;
2053d65abd66SPyun YongHyeon 		if ((error = re_newbuf(sc, i)) != 0)
2054d65abd66SPyun YongHyeon 			return (error);
2055a94100faSBill Paul 	}
2056579a6e3cSLuigi Rizzo #ifdef DEV_NETMAP
2057579a6e3cSLuigi Rizzo 	re_netmap_rx_init(sc);
2058579a6e3cSLuigi Rizzo #endif /* DEV_NETMAP */
2059a94100faSBill Paul 
2060a94100faSBill Paul 	/* Flush the RX descriptors */
2061a94100faSBill Paul 
2062a94100faSBill Paul 	bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
2063a94100faSBill Paul 	    sc->rl_ldata.rl_rx_list_map,
2064a94100faSBill Paul 	    BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
2065a94100faSBill Paul 
2066a94100faSBill Paul 	sc->rl_ldata.rl_rx_prodidx = 0;
2067a94100faSBill Paul 	sc->rl_head = sc->rl_tail = NULL;
2068502be0f7SPyun YongHyeon 	sc->rl_int_rx_act = 0;
2069a94100faSBill Paul 
2070a94100faSBill Paul 	return (0);
2071a94100faSBill Paul }
2072a94100faSBill Paul 
207381eee0ebSPyun YongHyeon static int
207481eee0ebSPyun YongHyeon re_jrx_list_init(struct rl_softc *sc)
207581eee0ebSPyun YongHyeon {
207681eee0ebSPyun YongHyeon 	int			error, i;
207781eee0ebSPyun YongHyeon 
207881eee0ebSPyun YongHyeon 	bzero(sc->rl_ldata.rl_rx_list,
207981eee0ebSPyun YongHyeon 	    sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc));
208081eee0ebSPyun YongHyeon 	for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
208181eee0ebSPyun YongHyeon 		sc->rl_ldata.rl_jrx_desc[i].rx_m = NULL;
208281eee0ebSPyun YongHyeon 		if ((error = re_jumbo_newbuf(sc, i)) != 0)
208381eee0ebSPyun YongHyeon 			return (error);
208481eee0ebSPyun YongHyeon 	}
208581eee0ebSPyun YongHyeon 
208681eee0ebSPyun YongHyeon 	bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
208781eee0ebSPyun YongHyeon 	    sc->rl_ldata.rl_rx_list_map,
208881eee0ebSPyun YongHyeon 	    BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
208981eee0ebSPyun YongHyeon 
209081eee0ebSPyun YongHyeon 	sc->rl_ldata.rl_rx_prodidx = 0;
209181eee0ebSPyun YongHyeon 	sc->rl_head = sc->rl_tail = NULL;
2092502be0f7SPyun YongHyeon 	sc->rl_int_rx_act = 0;
209381eee0ebSPyun YongHyeon 
209481eee0ebSPyun YongHyeon 	return (0);
209581eee0ebSPyun YongHyeon }
209681eee0ebSPyun YongHyeon 
2097a94100faSBill Paul /*
2098a94100faSBill Paul  * RX handler for C+ and 8169. For the gigE chips, we support
2099a94100faSBill Paul  * the reception of jumbo frames that have been fragmented
2100a94100faSBill Paul  * across multiple 2K mbuf cluster buffers.
2101a94100faSBill Paul  */
2102ed510fb0SBill Paul static int
21031abcdbd1SAttilio Rao re_rxeof(struct rl_softc *sc, int *rx_npktsp)
2104a94100faSBill Paul {
2105a94100faSBill Paul 	struct mbuf		*m;
2106a94100faSBill Paul 	struct ifnet		*ifp;
210781eee0ebSPyun YongHyeon 	int			i, rxerr, total_len;
2108a94100faSBill Paul 	struct rl_desc		*cur_rx;
2109a94100faSBill Paul 	u_int32_t		rxstat, rxvlan;
211081eee0ebSPyun YongHyeon 	int			jumbo, maxpkt = 16, rx_npkts = 0;
2111a94100faSBill Paul 
21125120abbfSSam Leffler 	RL_LOCK_ASSERT(sc);
21135120abbfSSam Leffler 
2114fc74a9f9SBrooks Davis 	ifp = sc->rl_ifp;
2115579a6e3cSLuigi Rizzo #ifdef DEV_NETMAP
2116d61ba752SLuigi Rizzo 	if (netmap_rx_irq(ifp, 0 | (NETMAP_LOCKED_ENTER|NETMAP_LOCKED_EXIT),
2117d61ba752SLuigi Rizzo 	    &rx_npkts))
2118579a6e3cSLuigi Rizzo 		return 0;
2119579a6e3cSLuigi Rizzo #endif /* DEV_NETMAP */
212081eee0ebSPyun YongHyeon 	if (ifp->if_mtu > RL_MTU && (sc->rl_flags & RL_FLAG_JUMBOV2) != 0)
212181eee0ebSPyun YongHyeon 		jumbo = 1;
212281eee0ebSPyun YongHyeon 	else
212381eee0ebSPyun YongHyeon 		jumbo = 0;
2124a94100faSBill Paul 
2125a94100faSBill Paul 	/* Invalidate the descriptor memory */
2126a94100faSBill Paul 
2127a94100faSBill Paul 	bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
2128a94100faSBill Paul 	    sc->rl_ldata.rl_rx_list_map,
2129d65abd66SPyun YongHyeon 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2130a94100faSBill Paul 
2131d65abd66SPyun YongHyeon 	for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0;
2132d65abd66SPyun YongHyeon 	    i = RL_RX_DESC_NXT(sc, i)) {
21335b6d1d9dSPyun YongHyeon 		if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
21345b6d1d9dSPyun YongHyeon 			break;
2135a94100faSBill Paul 		cur_rx = &sc->rl_ldata.rl_rx_list[i];
2136a94100faSBill Paul 		rxstat = le32toh(cur_rx->rl_cmdstat);
2137d65abd66SPyun YongHyeon 		if ((rxstat & RL_RDESC_STAT_OWN) != 0)
2138d65abd66SPyun YongHyeon 			break;
2139d65abd66SPyun YongHyeon 		total_len = rxstat & sc->rl_rxlenmask;
2140a94100faSBill Paul 		rxvlan = le32toh(cur_rx->rl_vlanctl);
214181eee0ebSPyun YongHyeon 		if (jumbo != 0)
214281eee0ebSPyun YongHyeon 			m = sc->rl_ldata.rl_jrx_desc[i].rx_m;
214381eee0ebSPyun YongHyeon 		else
2144d65abd66SPyun YongHyeon 			m = sc->rl_ldata.rl_rx_desc[i].rx_m;
2145a94100faSBill Paul 
214681eee0ebSPyun YongHyeon 		if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 &&
214781eee0ebSPyun YongHyeon 		    (rxstat & (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) !=
214881eee0ebSPyun YongHyeon 		    (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) {
214981eee0ebSPyun YongHyeon 			/*
215081eee0ebSPyun YongHyeon 			 * RTL8168C or later controllers do not
215181eee0ebSPyun YongHyeon 			 * support multi-fragment packet.
215281eee0ebSPyun YongHyeon 			 */
215381eee0ebSPyun YongHyeon 			re_discard_rxbuf(sc, i);
215481eee0ebSPyun YongHyeon 			continue;
215581eee0ebSPyun YongHyeon 		} else if ((rxstat & RL_RDESC_STAT_EOF) == 0) {
2156d65abd66SPyun YongHyeon 			if (re_newbuf(sc, i) != 0) {
2157d65abd66SPyun YongHyeon 				/*
2158d65abd66SPyun YongHyeon 				 * If this is part of a multi-fragment packet,
2159d65abd66SPyun YongHyeon 				 * discard all the pieces.
2160d65abd66SPyun YongHyeon 				 */
2161d65abd66SPyun YongHyeon 				if (sc->rl_head != NULL) {
2162d65abd66SPyun YongHyeon 					m_freem(sc->rl_head);
2163d65abd66SPyun YongHyeon 					sc->rl_head = sc->rl_tail = NULL;
2164d65abd66SPyun YongHyeon 				}
2165d65abd66SPyun YongHyeon 				re_discard_rxbuf(sc, i);
2166d65abd66SPyun YongHyeon 				continue;
2167d65abd66SPyun YongHyeon 			}
216822a11c96SJohn-Mark Gurney 			m->m_len = RE_RX_DESC_BUFLEN;
2169a94100faSBill Paul 			if (sc->rl_head == NULL)
2170a94100faSBill Paul 				sc->rl_head = sc->rl_tail = m;
2171a94100faSBill Paul 			else {
2172a94100faSBill Paul 				m->m_flags &= ~M_PKTHDR;
2173a94100faSBill Paul 				sc->rl_tail->m_next = m;
2174a94100faSBill Paul 				sc->rl_tail = m;
2175a94100faSBill Paul 			}
2176a94100faSBill Paul 			continue;
2177a94100faSBill Paul 		}
2178a94100faSBill Paul 
2179a94100faSBill Paul 		/*
2180a94100faSBill Paul 		 * NOTE: for the 8139C+, the frame length field
2181a94100faSBill Paul 		 * is always 12 bits in size, but for the gigE chips,
2182a94100faSBill Paul 		 * it is 13 bits (since the max RX frame length is 16K).
2183a94100faSBill Paul 		 * Unfortunately, all 32 bits in the status word
2184a94100faSBill Paul 		 * were already used, so to make room for the extra
2185a94100faSBill Paul 		 * length bit, RealTek took out the 'frame alignment
2186a94100faSBill Paul 		 * error' bit and shifted the other status bits
2187a94100faSBill Paul 		 * over one slot. The OWN, EOR, FS and LS bits are
2188a94100faSBill Paul 		 * still in the same places. We have already extracted
2189a94100faSBill Paul 		 * the frame length and checked the OWN bit, so rather
2190a94100faSBill Paul 		 * than using an alternate bit mapping, we shift the
2191a94100faSBill Paul 		 * status bits one space to the right so we can evaluate
2192a94100faSBill Paul 		 * them using the 8169 status as though it was in the
2193a94100faSBill Paul 		 * same format as that of the 8139C+.
2194a94100faSBill Paul 		 */
2195a94100faSBill Paul 		if (sc->rl_type == RL_8169)
2196a94100faSBill Paul 			rxstat >>= 1;
2197a94100faSBill Paul 
219822a11c96SJohn-Mark Gurney 		/*
219922a11c96SJohn-Mark Gurney 		 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be
220022a11c96SJohn-Mark Gurney 		 * set, but if CRC is clear, it will still be a valid frame.
220122a11c96SJohn-Mark Gurney 		 */
220281eee0ebSPyun YongHyeon 		if ((rxstat & RL_RDESC_STAT_RXERRSUM) != 0) {
220381eee0ebSPyun YongHyeon 			rxerr = 1;
220481eee0ebSPyun YongHyeon 			if ((sc->rl_flags & RL_FLAG_JUMBOV2) == 0 &&
220581eee0ebSPyun YongHyeon 			    total_len > 8191 &&
220681eee0ebSPyun YongHyeon 			    (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)
220781eee0ebSPyun YongHyeon 				rxerr = 0;
220881eee0ebSPyun YongHyeon 			if (rxerr != 0) {
2209a94100faSBill Paul 				ifp->if_ierrors++;
2210a94100faSBill Paul 				/*
2211a94100faSBill Paul 				 * If this is part of a multi-fragment packet,
2212a94100faSBill Paul 				 * discard all the pieces.
2213a94100faSBill Paul 				 */
2214a94100faSBill Paul 				if (sc->rl_head != NULL) {
2215a94100faSBill Paul 					m_freem(sc->rl_head);
2216a94100faSBill Paul 					sc->rl_head = sc->rl_tail = NULL;
2217a94100faSBill Paul 				}
2218d65abd66SPyun YongHyeon 				re_discard_rxbuf(sc, i);
2219a94100faSBill Paul 				continue;
2220a94100faSBill Paul 			}
222181eee0ebSPyun YongHyeon 		}
2222a94100faSBill Paul 
2223a94100faSBill Paul 		/*
2224a94100faSBill Paul 		 * If allocating a replacement mbuf fails,
2225a94100faSBill Paul 		 * reload the current one.
2226a94100faSBill Paul 		 */
222781eee0ebSPyun YongHyeon 		if (jumbo != 0)
222881eee0ebSPyun YongHyeon 			rxerr = re_jumbo_newbuf(sc, i);
222981eee0ebSPyun YongHyeon 		else
223081eee0ebSPyun YongHyeon 			rxerr = re_newbuf(sc, i);
223181eee0ebSPyun YongHyeon 		if (rxerr != 0) {
2232d65abd66SPyun YongHyeon 			ifp->if_iqdrops++;
2233a94100faSBill Paul 			if (sc->rl_head != NULL) {
2234a94100faSBill Paul 				m_freem(sc->rl_head);
2235a94100faSBill Paul 				sc->rl_head = sc->rl_tail = NULL;
2236a94100faSBill Paul 			}
2237d65abd66SPyun YongHyeon 			re_discard_rxbuf(sc, i);
2238a94100faSBill Paul 			continue;
2239a94100faSBill Paul 		}
2240a94100faSBill Paul 
2241a94100faSBill Paul 		if (sc->rl_head != NULL) {
224281eee0ebSPyun YongHyeon 			if (jumbo != 0)
224381eee0ebSPyun YongHyeon 				m->m_len = total_len;
224481eee0ebSPyun YongHyeon 			else {
224522a11c96SJohn-Mark Gurney 				m->m_len = total_len % RE_RX_DESC_BUFLEN;
224622a11c96SJohn-Mark Gurney 				if (m->m_len == 0)
224722a11c96SJohn-Mark Gurney 					m->m_len = RE_RX_DESC_BUFLEN;
224881eee0ebSPyun YongHyeon 			}
2249a94100faSBill Paul 			/*
2250a94100faSBill Paul 			 * Special case: if there's 4 bytes or less
2251a94100faSBill Paul 			 * in this buffer, the mbuf can be discarded:
2252a94100faSBill Paul 			 * the last 4 bytes is the CRC, which we don't
2253a94100faSBill Paul 			 * care about anyway.
2254a94100faSBill Paul 			 */
2255a94100faSBill Paul 			if (m->m_len <= ETHER_CRC_LEN) {
2256a94100faSBill Paul 				sc->rl_tail->m_len -=
2257a94100faSBill Paul 				    (ETHER_CRC_LEN - m->m_len);
2258a94100faSBill Paul 				m_freem(m);
2259a94100faSBill Paul 			} else {
2260a94100faSBill Paul 				m->m_len -= ETHER_CRC_LEN;
2261a94100faSBill Paul 				m->m_flags &= ~M_PKTHDR;
2262a94100faSBill Paul 				sc->rl_tail->m_next = m;
2263a94100faSBill Paul 			}
2264a94100faSBill Paul 			m = sc->rl_head;
2265a94100faSBill Paul 			sc->rl_head = sc->rl_tail = NULL;
2266a94100faSBill Paul 			m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
2267a94100faSBill Paul 		} else
2268a94100faSBill Paul 			m->m_pkthdr.len = m->m_len =
2269a94100faSBill Paul 			    (total_len - ETHER_CRC_LEN);
2270a94100faSBill Paul 
227122a11c96SJohn-Mark Gurney #ifdef RE_FIXUP_RX
227222a11c96SJohn-Mark Gurney 		re_fixup_rx(m);
227322a11c96SJohn-Mark Gurney #endif
2274a94100faSBill Paul 		ifp->if_ipackets++;
2275a94100faSBill Paul 		m->m_pkthdr.rcvif = ifp;
2276a94100faSBill Paul 
2277a94100faSBill Paul 		/* Do RX checksumming if enabled */
2278a94100faSBill Paul 
2279a94100faSBill Paul 		if (ifp->if_capenable & IFCAP_RXCSUM) {
2280deb5c680SPyun YongHyeon 			if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) {
2281a94100faSBill Paul 				/* Check IP header checksum */
2282a94100faSBill Paul 				if (rxstat & RL_RDESC_STAT_PROTOID)
2283deb5c680SPyun YongHyeon 					m->m_pkthdr.csum_flags |=
2284deb5c680SPyun YongHyeon 					    CSUM_IP_CHECKED;
2285a94100faSBill Paul 				if (!(rxstat & RL_RDESC_STAT_IPSUMBAD))
2286deb5c680SPyun YongHyeon 					m->m_pkthdr.csum_flags |=
2287deb5c680SPyun YongHyeon 					    CSUM_IP_VALID;
2288a94100faSBill Paul 
2289a94100faSBill Paul 				/* Check TCP/UDP checksum */
2290a94100faSBill Paul 				if ((RL_TCPPKT(rxstat) &&
2291a94100faSBill Paul 				    !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) ||
2292a94100faSBill Paul 				    (RL_UDPPKT(rxstat) &&
2293a94100faSBill Paul 				     !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) {
2294a94100faSBill Paul 					m->m_pkthdr.csum_flags |=
2295a94100faSBill Paul 						CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
2296a94100faSBill Paul 					m->m_pkthdr.csum_data = 0xffff;
2297a94100faSBill Paul 				}
2298deb5c680SPyun YongHyeon 			} else {
2299deb5c680SPyun YongHyeon 				/*
2300deb5c680SPyun YongHyeon 				 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP
2301deb5c680SPyun YongHyeon 				 */
2302deb5c680SPyun YongHyeon 				if ((rxstat & RL_RDESC_STAT_PROTOID) &&
2303deb5c680SPyun YongHyeon 				    (rxvlan & RL_RDESC_IPV4))
2304deb5c680SPyun YongHyeon 					m->m_pkthdr.csum_flags |=
2305deb5c680SPyun YongHyeon 					    CSUM_IP_CHECKED;
2306deb5c680SPyun YongHyeon 				if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) &&
2307deb5c680SPyun YongHyeon 				    (rxvlan & RL_RDESC_IPV4))
2308deb5c680SPyun YongHyeon 					m->m_pkthdr.csum_flags |=
2309deb5c680SPyun YongHyeon 					    CSUM_IP_VALID;
2310deb5c680SPyun YongHyeon 				if (((rxstat & RL_RDESC_STAT_TCP) &&
2311deb5c680SPyun YongHyeon 				    !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) ||
2312deb5c680SPyun YongHyeon 				    ((rxstat & RL_RDESC_STAT_UDP) &&
2313deb5c680SPyun YongHyeon 				    !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) {
2314deb5c680SPyun YongHyeon 					m->m_pkthdr.csum_flags |=
2315deb5c680SPyun YongHyeon 						CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
2316deb5c680SPyun YongHyeon 					m->m_pkthdr.csum_data = 0xffff;
2317deb5c680SPyun YongHyeon 				}
2318deb5c680SPyun YongHyeon 			}
2319a94100faSBill Paul 		}
2320ed510fb0SBill Paul 		maxpkt--;
2321d147662cSGleb Smirnoff 		if (rxvlan & RL_RDESC_VLANCTL_TAG) {
232278ba57b9SAndre Oppermann 			m->m_pkthdr.ether_vtag =
2323bddff934SPyun YongHyeon 			    bswap16((rxvlan & RL_RDESC_VLANCTL_DATA));
232478ba57b9SAndre Oppermann 			m->m_flags |= M_VLANTAG;
2325d147662cSGleb Smirnoff 		}
23265120abbfSSam Leffler 		RL_UNLOCK(sc);
2327a94100faSBill Paul 		(*ifp->if_input)(ifp, m);
23285120abbfSSam Leffler 		RL_LOCK(sc);
23291abcdbd1SAttilio Rao 		rx_npkts++;
2330a94100faSBill Paul 	}
2331a94100faSBill Paul 
2332a94100faSBill Paul 	/* Flush the RX DMA ring */
2333a94100faSBill Paul 
2334a94100faSBill Paul 	bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
2335a94100faSBill Paul 	    sc->rl_ldata.rl_rx_list_map,
2336a94100faSBill Paul 	    BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
2337a94100faSBill Paul 
2338a94100faSBill Paul 	sc->rl_ldata.rl_rx_prodidx = i;
2339ed510fb0SBill Paul 
23401abcdbd1SAttilio Rao 	if (rx_npktsp != NULL)
23411abcdbd1SAttilio Rao 		*rx_npktsp = rx_npkts;
2342ed510fb0SBill Paul 	if (maxpkt)
2343ed510fb0SBill Paul 		return (EAGAIN);
2344ed510fb0SBill Paul 
2345ed510fb0SBill Paul 	return (0);
2346a94100faSBill Paul }
2347a94100faSBill Paul 
2348a94100faSBill Paul static void
23497b5ffebfSPyun YongHyeon re_txeof(struct rl_softc *sc)
2350a94100faSBill Paul {
2351a94100faSBill Paul 	struct ifnet		*ifp;
2352d65abd66SPyun YongHyeon 	struct rl_txdesc	*txd;
2353a94100faSBill Paul 	u_int32_t		txstat;
2354d65abd66SPyun YongHyeon 	int			cons;
2355d65abd66SPyun YongHyeon 
2356d65abd66SPyun YongHyeon 	cons = sc->rl_ldata.rl_tx_considx;
2357d65abd66SPyun YongHyeon 	if (cons == sc->rl_ldata.rl_tx_prodidx)
2358d65abd66SPyun YongHyeon 		return;
2359a94100faSBill Paul 
2360fc74a9f9SBrooks Davis 	ifp = sc->rl_ifp;
2361579a6e3cSLuigi Rizzo #ifdef DEV_NETMAP
2362d61ba752SLuigi Rizzo 	if (netmap_tx_irq(ifp, 0 | (NETMAP_LOCKED_ENTER|NETMAP_LOCKED_EXIT)))
2363579a6e3cSLuigi Rizzo 		return;
2364579a6e3cSLuigi Rizzo #endif /* DEV_NETMAP */
2365a94100faSBill Paul 	/* Invalidate the TX descriptor list */
2366a94100faSBill Paul 	bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
2367a94100faSBill Paul 	    sc->rl_ldata.rl_tx_list_map,
2368d65abd66SPyun YongHyeon 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2369a94100faSBill Paul 
2370d65abd66SPyun YongHyeon 	for (; cons != sc->rl_ldata.rl_tx_prodidx;
2371d65abd66SPyun YongHyeon 	    cons = RL_TX_DESC_NXT(sc, cons)) {
2372d65abd66SPyun YongHyeon 		txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat);
2373d65abd66SPyun YongHyeon 		if (txstat & RL_TDESC_STAT_OWN)
2374a94100faSBill Paul 			break;
2375a94100faSBill Paul 		/*
2376a94100faSBill Paul 		 * We only stash mbufs in the last descriptor
2377a94100faSBill Paul 		 * in a fragment chain, which also happens to
2378a94100faSBill Paul 		 * be the only place where the TX status bits
2379a94100faSBill Paul 		 * are valid.
2380a94100faSBill Paul 		 */
2381a94100faSBill Paul 		if (txstat & RL_TDESC_CMD_EOF) {
2382d65abd66SPyun YongHyeon 			txd = &sc->rl_ldata.rl_tx_desc[cons];
2383d65abd66SPyun YongHyeon 			bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag,
2384d65abd66SPyun YongHyeon 			    txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2385d65abd66SPyun YongHyeon 			bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag,
2386d65abd66SPyun YongHyeon 			    txd->tx_dmamap);
2387d65abd66SPyun YongHyeon 			KASSERT(txd->tx_m != NULL,
2388d65abd66SPyun YongHyeon 			    ("%s: freeing NULL mbufs!", __func__));
2389d65abd66SPyun YongHyeon 			m_freem(txd->tx_m);
2390d65abd66SPyun YongHyeon 			txd->tx_m = NULL;
2391a94100faSBill Paul 			if (txstat & (RL_TDESC_STAT_EXCESSCOL|
2392a94100faSBill Paul 			    RL_TDESC_STAT_COLCNT))
2393a94100faSBill Paul 				ifp->if_collisions++;
2394a94100faSBill Paul 			if (txstat & RL_TDESC_STAT_TXERRSUM)
2395a94100faSBill Paul 				ifp->if_oerrors++;
2396a94100faSBill Paul 			else
2397a94100faSBill Paul 				ifp->if_opackets++;
2398a94100faSBill Paul 		}
2399a94100faSBill Paul 		sc->rl_ldata.rl_tx_free++;
2400d65abd66SPyun YongHyeon 		ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2401a94100faSBill Paul 	}
2402d65abd66SPyun YongHyeon 	sc->rl_ldata.rl_tx_considx = cons;
2403a94100faSBill Paul 
2404a94100faSBill Paul 	/* No changes made to the TX ring, so no flush needed */
2405a94100faSBill Paul 
2406d65abd66SPyun YongHyeon 	if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) {
2407ed510fb0SBill Paul #ifdef RE_TX_MODERATION
2408a94100faSBill Paul 		/*
2409b4b95879SMarius Strobl 		 * If not all descriptors have been reaped yet, reload
2410b4b95879SMarius Strobl 		 * the timer so that we will eventually get another
2411a94100faSBill Paul 		 * interrupt that will cause us to re-enter this routine.
2412a94100faSBill Paul 		 * This is done in case the transmitter has gone idle.
2413a94100faSBill Paul 		 */
2414a94100faSBill Paul 		CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2415ed510fb0SBill Paul #endif
2416b4b95879SMarius Strobl 	} else
2417b4b95879SMarius Strobl 		sc->rl_watchdog_timer = 0;
2418a94100faSBill Paul }
2419a94100faSBill Paul 
2420a94100faSBill Paul static void
24217b5ffebfSPyun YongHyeon re_tick(void *xsc)
2422a94100faSBill Paul {
2423a94100faSBill Paul 	struct rl_softc		*sc;
2424d1754a9bSJohn Baldwin 	struct mii_data		*mii;
2425a94100faSBill Paul 
2426a94100faSBill Paul 	sc = xsc;
242797b9d4baSJohn-Mark Gurney 
242897b9d4baSJohn-Mark Gurney 	RL_LOCK_ASSERT(sc);
242997b9d4baSJohn-Mark Gurney 
24301d545c7aSMarius Strobl 	mii = device_get_softc(sc->rl_miibus);
2431a94100faSBill Paul 	mii_tick(mii);
24320fe200d9SPyun YongHyeon 	if ((sc->rl_flags & RL_FLAG_LINK) == 0)
24330fe200d9SPyun YongHyeon 		re_miibus_statchg(sc->rl_dev);
2434c2d2e19cSPyun YongHyeon 	/*
2435c2d2e19cSPyun YongHyeon 	 * Reclaim transmitted frames here. Technically it is not
2436c2d2e19cSPyun YongHyeon 	 * necessary to do here but it ensures periodic reclamation
2437c2d2e19cSPyun YongHyeon 	 * regardless of Tx completion interrupt which seems to be
2438c2d2e19cSPyun YongHyeon 	 * lost on PCIe based controllers under certain situations.
2439c2d2e19cSPyun YongHyeon 	 */
2440c2d2e19cSPyun YongHyeon 	re_txeof(sc);
2441130b6dfbSPyun YongHyeon 	re_watchdog(sc);
2442d1754a9bSJohn Baldwin 	callout_reset(&sc->rl_stat_callout, hz, re_tick, sc);
2443a94100faSBill Paul }
2444a94100faSBill Paul 
2445a94100faSBill Paul #ifdef DEVICE_POLLING
24461abcdbd1SAttilio Rao static int
2447a94100faSBill Paul re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2448a94100faSBill Paul {
2449a94100faSBill Paul 	struct rl_softc *sc = ifp->if_softc;
24501abcdbd1SAttilio Rao 	int rx_npkts = 0;
2451a94100faSBill Paul 
2452a94100faSBill Paul 	RL_LOCK(sc);
245340929967SGleb Smirnoff 	if (ifp->if_drv_flags & IFF_DRV_RUNNING)
24541abcdbd1SAttilio Rao 		rx_npkts = re_poll_locked(ifp, cmd, count);
245597b9d4baSJohn-Mark Gurney 	RL_UNLOCK(sc);
24561abcdbd1SAttilio Rao 	return (rx_npkts);
245797b9d4baSJohn-Mark Gurney }
245897b9d4baSJohn-Mark Gurney 
24591abcdbd1SAttilio Rao static int
246097b9d4baSJohn-Mark Gurney re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
246197b9d4baSJohn-Mark Gurney {
246297b9d4baSJohn-Mark Gurney 	struct rl_softc *sc = ifp->if_softc;
24631abcdbd1SAttilio Rao 	int rx_npkts;
246497b9d4baSJohn-Mark Gurney 
246597b9d4baSJohn-Mark Gurney 	RL_LOCK_ASSERT(sc);
246697b9d4baSJohn-Mark Gurney 
2467a94100faSBill Paul 	sc->rxcycles = count;
24681abcdbd1SAttilio Rao 	re_rxeof(sc, &rx_npkts);
2469a94100faSBill Paul 	re_txeof(sc);
2470a94100faSBill Paul 
247137652939SMax Laier 	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2472d180a66fSPyun YongHyeon 		re_start_locked(ifp);
2473a94100faSBill Paul 
2474a94100faSBill Paul 	if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
2475a94100faSBill Paul 		u_int16_t       status;
2476a94100faSBill Paul 
2477a94100faSBill Paul 		status = CSR_READ_2(sc, RL_ISR);
2478a94100faSBill Paul 		if (status == 0xffff)
24791abcdbd1SAttilio Rao 			return (rx_npkts);
2480a94100faSBill Paul 		if (status)
2481a94100faSBill Paul 			CSR_WRITE_2(sc, RL_ISR, status);
2482818951afSPyun YongHyeon 		if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) &&
2483818951afSPyun YongHyeon 		    (sc->rl_flags & RL_FLAG_PCIE))
2484818951afSPyun YongHyeon 			CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2485a94100faSBill Paul 
2486a94100faSBill Paul 		/*
2487a94100faSBill Paul 		 * XXX check behaviour on receiver stalls.
2488a94100faSBill Paul 		 */
2489a94100faSBill Paul 
24908476c243SPyun YongHyeon 		if (status & RL_ISR_SYSTEM_ERR) {
24918476c243SPyun YongHyeon 			ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
249297b9d4baSJohn-Mark Gurney 			re_init_locked(sc);
2493a94100faSBill Paul 		}
24948476c243SPyun YongHyeon 	}
24951abcdbd1SAttilio Rao 	return (rx_npkts);
2496a94100faSBill Paul }
2497a94100faSBill Paul #endif /* DEVICE_POLLING */
2498a94100faSBill Paul 
2499ef544f63SPaolo Pisati static int
25007b5ffebfSPyun YongHyeon re_intr(void *arg)
2501a94100faSBill Paul {
2502a94100faSBill Paul 	struct rl_softc		*sc;
2503ed510fb0SBill Paul 	uint16_t		status;
2504a94100faSBill Paul 
2505a94100faSBill Paul 	sc = arg;
2506ed510fb0SBill Paul 
2507ed510fb0SBill Paul 	status = CSR_READ_2(sc, RL_ISR);
2508498bd0d3SBill Paul 	if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0)
2509ef544f63SPaolo Pisati                 return (FILTER_STRAY);
2510ed510fb0SBill Paul 	CSR_WRITE_2(sc, RL_IMR, 0);
2511ed510fb0SBill Paul 
2512ed510fb0SBill Paul 	taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask);
2513ed510fb0SBill Paul 
2514ef544f63SPaolo Pisati 	return (FILTER_HANDLED);
2515ed510fb0SBill Paul }
2516ed510fb0SBill Paul 
2517ed510fb0SBill Paul static void
25187b5ffebfSPyun YongHyeon re_int_task(void *arg, int npending)
2519ed510fb0SBill Paul {
2520ed510fb0SBill Paul 	struct rl_softc		*sc;
2521ed510fb0SBill Paul 	struct ifnet		*ifp;
2522ed510fb0SBill Paul 	u_int16_t		status;
2523ed510fb0SBill Paul 	int			rval = 0;
2524ed510fb0SBill Paul 
2525ed510fb0SBill Paul 	sc = arg;
2526ed510fb0SBill Paul 	ifp = sc->rl_ifp;
2527a94100faSBill Paul 
2528a94100faSBill Paul 	RL_LOCK(sc);
252997b9d4baSJohn-Mark Gurney 
2530a94100faSBill Paul 	status = CSR_READ_2(sc, RL_ISR);
2531a94100faSBill Paul         CSR_WRITE_2(sc, RL_ISR, status);
2532a94100faSBill Paul 
2533d65abd66SPyun YongHyeon 	if (sc->suspended ||
2534d65abd66SPyun YongHyeon 	    (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2535ed510fb0SBill Paul 		RL_UNLOCK(sc);
2536ed510fb0SBill Paul 		return;
2537ed510fb0SBill Paul 	}
2538a94100faSBill Paul 
2539ed510fb0SBill Paul #ifdef DEVICE_POLLING
2540ed510fb0SBill Paul 	if  (ifp->if_capenable & IFCAP_POLLING) {
2541ed510fb0SBill Paul 		RL_UNLOCK(sc);
2542ed510fb0SBill Paul 		return;
2543ed510fb0SBill Paul 	}
2544ed510fb0SBill Paul #endif
2545a94100faSBill Paul 
2546ed510fb0SBill Paul 	if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW))
25471abcdbd1SAttilio Rao 		rval = re_rxeof(sc, NULL);
2548ed510fb0SBill Paul 
2549818951afSPyun YongHyeon 	/*
2550818951afSPyun YongHyeon 	 * Some chips will ignore a second TX request issued
2551818951afSPyun YongHyeon 	 * while an existing transmission is in progress. If
2552818951afSPyun YongHyeon 	 * the transmitter goes idle but there are still
2553818951afSPyun YongHyeon 	 * packets waiting to be sent, we need to restart the
2554818951afSPyun YongHyeon 	 * channel here to flush them out. This only seems to
2555818951afSPyun YongHyeon 	 * be required with the PCIe devices.
2556818951afSPyun YongHyeon 	 */
2557818951afSPyun YongHyeon 	if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) &&
2558818951afSPyun YongHyeon 	    (sc->rl_flags & RL_FLAG_PCIE))
2559818951afSPyun YongHyeon 		CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
25603d85c23dSPyun YongHyeon 	if (status & (
2561ed510fb0SBill Paul #ifdef RE_TX_MODERATION
25623d85c23dSPyun YongHyeon 	    RL_ISR_TIMEOUT_EXPIRED|
2563ed510fb0SBill Paul #else
25643d85c23dSPyun YongHyeon 	    RL_ISR_TX_OK|
2565ed510fb0SBill Paul #endif
2566ed510fb0SBill Paul 	    RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL))
2567a94100faSBill Paul 		re_txeof(sc);
2568a94100faSBill Paul 
25698476c243SPyun YongHyeon 	if (status & RL_ISR_SYSTEM_ERR) {
25708476c243SPyun YongHyeon 		ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
257197b9d4baSJohn-Mark Gurney 		re_init_locked(sc);
25728476c243SPyun YongHyeon 	}
2573a94100faSBill Paul 
257452732175SMax Laier 	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2575d180a66fSPyun YongHyeon 		re_start_locked(ifp);
2576a94100faSBill Paul 
2577a94100faSBill Paul 	RL_UNLOCK(sc);
2578ed510fb0SBill Paul 
2579ed510fb0SBill Paul         if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) {
2580ed510fb0SBill Paul 		taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask);
2581ed510fb0SBill Paul 		return;
2582ed510fb0SBill Paul 	}
2583ed510fb0SBill Paul 
2584ed510fb0SBill Paul 	CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
2585a94100faSBill Paul }
2586a94100faSBill Paul 
2587502be0f7SPyun YongHyeon static void
2588502be0f7SPyun YongHyeon re_intr_msi(void *xsc)
2589502be0f7SPyun YongHyeon {
2590502be0f7SPyun YongHyeon 	struct rl_softc		*sc;
2591502be0f7SPyun YongHyeon 	struct ifnet		*ifp;
2592502be0f7SPyun YongHyeon 	uint16_t		intrs, status;
2593502be0f7SPyun YongHyeon 
2594502be0f7SPyun YongHyeon 	sc = xsc;
2595502be0f7SPyun YongHyeon 	RL_LOCK(sc);
2596502be0f7SPyun YongHyeon 
2597502be0f7SPyun YongHyeon 	ifp = sc->rl_ifp;
2598502be0f7SPyun YongHyeon #ifdef DEVICE_POLLING
2599502be0f7SPyun YongHyeon 	if (ifp->if_capenable & IFCAP_POLLING) {
2600502be0f7SPyun YongHyeon 		RL_UNLOCK(sc);
2601502be0f7SPyun YongHyeon 		return;
2602502be0f7SPyun YongHyeon 	}
2603502be0f7SPyun YongHyeon #endif
2604502be0f7SPyun YongHyeon 	/* Disable interrupts. */
2605502be0f7SPyun YongHyeon 	CSR_WRITE_2(sc, RL_IMR, 0);
2606502be0f7SPyun YongHyeon 	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2607502be0f7SPyun YongHyeon 		RL_UNLOCK(sc);
2608502be0f7SPyun YongHyeon 		return;
2609502be0f7SPyun YongHyeon 	}
2610502be0f7SPyun YongHyeon 
2611502be0f7SPyun YongHyeon 	intrs = RL_INTRS_CPLUS;
2612502be0f7SPyun YongHyeon 	status = CSR_READ_2(sc, RL_ISR);
2613502be0f7SPyun YongHyeon         CSR_WRITE_2(sc, RL_ISR, status);
2614502be0f7SPyun YongHyeon 	if (sc->rl_int_rx_act > 0) {
2615502be0f7SPyun YongHyeon 		intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW |
2616502be0f7SPyun YongHyeon 		    RL_ISR_RX_OVERRUN);
2617502be0f7SPyun YongHyeon 		status &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW |
2618502be0f7SPyun YongHyeon 		    RL_ISR_RX_OVERRUN);
2619502be0f7SPyun YongHyeon 	}
2620502be0f7SPyun YongHyeon 
2621502be0f7SPyun YongHyeon 	if (status & (RL_ISR_TIMEOUT_EXPIRED | RL_ISR_RX_OK | RL_ISR_RX_ERR |
2622502be0f7SPyun YongHyeon 	    RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) {
2623502be0f7SPyun YongHyeon 		re_rxeof(sc, NULL);
2624502be0f7SPyun YongHyeon 		if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2625502be0f7SPyun YongHyeon 			if (sc->rl_int_rx_mod != 0 &&
2626502be0f7SPyun YongHyeon 			    (status & (RL_ISR_RX_OK | RL_ISR_RX_ERR |
2627502be0f7SPyun YongHyeon 			    RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) != 0) {
2628502be0f7SPyun YongHyeon 				/* Rearm one-shot timer. */
2629502be0f7SPyun YongHyeon 				CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2630502be0f7SPyun YongHyeon 				intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR |
2631502be0f7SPyun YongHyeon 				    RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN);
2632502be0f7SPyun YongHyeon 				sc->rl_int_rx_act = 1;
2633502be0f7SPyun YongHyeon 			} else {
2634502be0f7SPyun YongHyeon 				intrs |= RL_ISR_RX_OK | RL_ISR_RX_ERR |
2635502be0f7SPyun YongHyeon 				    RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN;
2636502be0f7SPyun YongHyeon 				sc->rl_int_rx_act = 0;
2637502be0f7SPyun YongHyeon 			}
2638502be0f7SPyun YongHyeon 		}
2639502be0f7SPyun YongHyeon 	}
2640502be0f7SPyun YongHyeon 
2641502be0f7SPyun YongHyeon 	/*
2642502be0f7SPyun YongHyeon 	 * Some chips will ignore a second TX request issued
2643502be0f7SPyun YongHyeon 	 * while an existing transmission is in progress. If
2644502be0f7SPyun YongHyeon 	 * the transmitter goes idle but there are still
2645502be0f7SPyun YongHyeon 	 * packets waiting to be sent, we need to restart the
2646502be0f7SPyun YongHyeon 	 * channel here to flush them out. This only seems to
2647502be0f7SPyun YongHyeon 	 * be required with the PCIe devices.
2648502be0f7SPyun YongHyeon 	 */
2649502be0f7SPyun YongHyeon 	if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) &&
2650502be0f7SPyun YongHyeon 	    (sc->rl_flags & RL_FLAG_PCIE))
2651502be0f7SPyun YongHyeon 		CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2652502be0f7SPyun YongHyeon 	if (status & (RL_ISR_TX_OK | RL_ISR_TX_ERR | RL_ISR_TX_DESC_UNAVAIL))
2653502be0f7SPyun YongHyeon 		re_txeof(sc);
2654502be0f7SPyun YongHyeon 
2655502be0f7SPyun YongHyeon 	if (status & RL_ISR_SYSTEM_ERR) {
2656502be0f7SPyun YongHyeon 		ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2657502be0f7SPyun YongHyeon 		re_init_locked(sc);
2658502be0f7SPyun YongHyeon 	}
2659502be0f7SPyun YongHyeon 
2660502be0f7SPyun YongHyeon 	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2661502be0f7SPyun YongHyeon 		if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2662502be0f7SPyun YongHyeon 			re_start_locked(ifp);
2663502be0f7SPyun YongHyeon 		CSR_WRITE_2(sc, RL_IMR, intrs);
2664502be0f7SPyun YongHyeon 	}
2665502be0f7SPyun YongHyeon 	RL_UNLOCK(sc);
2666502be0f7SPyun YongHyeon }
2667502be0f7SPyun YongHyeon 
2668d65abd66SPyun YongHyeon static int
26697b5ffebfSPyun YongHyeon re_encap(struct rl_softc *sc, struct mbuf **m_head)
2670d65abd66SPyun YongHyeon {
2671d65abd66SPyun YongHyeon 	struct rl_txdesc	*txd, *txd_last;
2672d65abd66SPyun YongHyeon 	bus_dma_segment_t	segs[RL_NTXSEGS];
2673d65abd66SPyun YongHyeon 	bus_dmamap_t		map;
2674d65abd66SPyun YongHyeon 	struct mbuf		*m_new;
2675d65abd66SPyun YongHyeon 	struct rl_desc		*desc;
2676d65abd66SPyun YongHyeon 	int			nsegs, prod;
2677d65abd66SPyun YongHyeon 	int			i, error, ei, si;
2678d65abd66SPyun YongHyeon 	int			padlen;
2679ccf34c81SPyun YongHyeon 	uint32_t		cmdstat, csum_flags, vlanctl;
2680a94100faSBill Paul 
2681d65abd66SPyun YongHyeon 	RL_LOCK_ASSERT(sc);
2682738489d1SPyun YongHyeon 	M_ASSERTPKTHDR((*m_head));
26830fc4974fSBill Paul 
26840fc4974fSBill Paul 	/*
26850fc4974fSBill Paul 	 * With some of the RealTek chips, using the checksum offload
26860fc4974fSBill Paul 	 * support in conjunction with the autopadding feature results
26870fc4974fSBill Paul 	 * in the transmission of corrupt frames. For example, if we
26880fc4974fSBill Paul 	 * need to send a really small IP fragment that's less than 60
26890fc4974fSBill Paul 	 * bytes in size, and IP header checksumming is enabled, the
26900fc4974fSBill Paul 	 * resulting ethernet frame that appears on the wire will
269199c8ae87SPyun YongHyeon 	 * have garbled payload. To work around this, if TX IP checksum
26920fc4974fSBill Paul 	 * offload is enabled, we always manually pad short frames out
2693d65abd66SPyun YongHyeon 	 * to the minimum ethernet frame size.
26940fc4974fSBill Paul 	 */
2695f2e491c9SPyun YongHyeon 	if ((sc->rl_flags & RL_FLAG_AUTOPAD) == 0 &&
2696deb5c680SPyun YongHyeon 	    (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN &&
269799c8ae87SPyun YongHyeon 	    ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) {
2698d65abd66SPyun YongHyeon 		padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len;
2699d65abd66SPyun YongHyeon 		if (M_WRITABLE(*m_head) == 0) {
2700d65abd66SPyun YongHyeon 			/* Get a writable copy. */
2701c6499eccSGleb Smirnoff 			m_new = m_dup(*m_head, M_NOWAIT);
2702d65abd66SPyun YongHyeon 			m_freem(*m_head);
2703d65abd66SPyun YongHyeon 			if (m_new == NULL) {
2704d65abd66SPyun YongHyeon 				*m_head = NULL;
2705a94100faSBill Paul 				return (ENOBUFS);
2706a94100faSBill Paul 			}
2707d65abd66SPyun YongHyeon 			*m_head = m_new;
2708d65abd66SPyun YongHyeon 		}
2709d65abd66SPyun YongHyeon 		if ((*m_head)->m_next != NULL ||
2710d65abd66SPyun YongHyeon 		    M_TRAILINGSPACE(*m_head) < padlen) {
2711c6499eccSGleb Smirnoff 			m_new = m_defrag(*m_head, M_NOWAIT);
2712b4b95879SMarius Strobl 			if (m_new == NULL) {
2713b4b95879SMarius Strobl 				m_freem(*m_head);
2714b4b95879SMarius Strobl 				*m_head = NULL;
271580a2a305SJohn-Mark Gurney 				return (ENOBUFS);
2716b4b95879SMarius Strobl 			}
2717d65abd66SPyun YongHyeon 		} else
2718d65abd66SPyun YongHyeon 			m_new = *m_head;
2719a94100faSBill Paul 
27200fc4974fSBill Paul 		/*
27210fc4974fSBill Paul 		 * Manually pad short frames, and zero the pad space
27220fc4974fSBill Paul 		 * to avoid leaking data.
27230fc4974fSBill Paul 		 */
2724d65abd66SPyun YongHyeon 		bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen);
2725d65abd66SPyun YongHyeon 		m_new->m_pkthdr.len += padlen;
27260fc4974fSBill Paul 		m_new->m_len = m_new->m_pkthdr.len;
2727d65abd66SPyun YongHyeon 		*m_head = m_new;
27280fc4974fSBill Paul 	}
27290fc4974fSBill Paul 
2730d65abd66SPyun YongHyeon 	prod = sc->rl_ldata.rl_tx_prodidx;
2731d65abd66SPyun YongHyeon 	txd = &sc->rl_ldata.rl_tx_desc[prod];
2732d65abd66SPyun YongHyeon 	error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap,
2733d65abd66SPyun YongHyeon 	    *m_head, segs, &nsegs, BUS_DMA_NOWAIT);
2734d65abd66SPyun YongHyeon 	if (error == EFBIG) {
2735c6499eccSGleb Smirnoff 		m_new = m_collapse(*m_head, M_NOWAIT, RL_NTXSEGS);
2736d65abd66SPyun YongHyeon 		if (m_new == NULL) {
2737d65abd66SPyun YongHyeon 			m_freem(*m_head);
2738b4b95879SMarius Strobl 			*m_head = NULL;
2739d65abd66SPyun YongHyeon 			return (ENOBUFS);
2740a94100faSBill Paul 		}
2741d65abd66SPyun YongHyeon 		*m_head = m_new;
2742d65abd66SPyun YongHyeon 		error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag,
2743d65abd66SPyun YongHyeon 		    txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT);
2744d65abd66SPyun YongHyeon 		if (error != 0) {
2745d65abd66SPyun YongHyeon 			m_freem(*m_head);
2746d65abd66SPyun YongHyeon 			*m_head = NULL;
2747d65abd66SPyun YongHyeon 			return (error);
2748a94100faSBill Paul 		}
2749d65abd66SPyun YongHyeon 	} else if (error != 0)
2750d65abd66SPyun YongHyeon 		return (error);
2751d65abd66SPyun YongHyeon 	if (nsegs == 0) {
2752d65abd66SPyun YongHyeon 		m_freem(*m_head);
2753d65abd66SPyun YongHyeon 		*m_head = NULL;
2754d65abd66SPyun YongHyeon 		return (EIO);
2755d65abd66SPyun YongHyeon 	}
2756d65abd66SPyun YongHyeon 
2757d65abd66SPyun YongHyeon 	/* Check for number of available descriptors. */
2758d65abd66SPyun YongHyeon 	if (sc->rl_ldata.rl_tx_free - nsegs <= 1) {
2759d65abd66SPyun YongHyeon 		bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap);
2760d65abd66SPyun YongHyeon 		return (ENOBUFS);
2761d65abd66SPyun YongHyeon 	}
2762d65abd66SPyun YongHyeon 
2763d65abd66SPyun YongHyeon 	bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap,
2764d65abd66SPyun YongHyeon 	    BUS_DMASYNC_PREWRITE);
2765a94100faSBill Paul 
2766a94100faSBill Paul 	/*
2767d65abd66SPyun YongHyeon 	 * Set up checksum offload. Note: checksum offload bits must
2768d65abd66SPyun YongHyeon 	 * appear in all descriptors of a multi-descriptor transmit
2769d65abd66SPyun YongHyeon 	 * attempt. This is according to testing done with an 8169
2770d65abd66SPyun YongHyeon 	 * chip. This is a requirement.
2771a94100faSBill Paul 	 */
2772deb5c680SPyun YongHyeon 	vlanctl = 0;
2773d65abd66SPyun YongHyeon 	csum_flags = 0;
2774d6d7d923SPyun YongHyeon 	if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
2775d6d7d923SPyun YongHyeon 		if ((sc->rl_flags & RL_FLAG_DESCV2) != 0) {
2776d6d7d923SPyun YongHyeon 			csum_flags |= RL_TDESC_CMD_LGSEND;
2777d6d7d923SPyun YongHyeon 			vlanctl |= ((uint32_t)(*m_head)->m_pkthdr.tso_segsz <<
2778d6d7d923SPyun YongHyeon 			    RL_TDESC_CMD_MSSVALV2_SHIFT);
2779d6d7d923SPyun YongHyeon 		} else {
2780d6d7d923SPyun YongHyeon 			csum_flags |= RL_TDESC_CMD_LGSEND |
2781d65abd66SPyun YongHyeon 			    ((uint32_t)(*m_head)->m_pkthdr.tso_segsz <<
2782d65abd66SPyun YongHyeon 			    RL_TDESC_CMD_MSSVAL_SHIFT);
2783d6d7d923SPyun YongHyeon 		}
2784d6d7d923SPyun YongHyeon 	} else {
278599c8ae87SPyun YongHyeon 		/*
278699c8ae87SPyun YongHyeon 		 * Unconditionally enable IP checksum if TCP or UDP
278799c8ae87SPyun YongHyeon 		 * checksum is required. Otherwise, TCP/UDP checksum
27882df05392SSergey Kandaurov 		 * doesn't make effects.
278999c8ae87SPyun YongHyeon 		 */
279099c8ae87SPyun YongHyeon 		if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) {
2791deb5c680SPyun YongHyeon 			if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) {
2792d65abd66SPyun YongHyeon 				csum_flags |= RL_TDESC_CMD_IPCSUM;
2793deb5c680SPyun YongHyeon 				if (((*m_head)->m_pkthdr.csum_flags &
2794deb5c680SPyun YongHyeon 				    CSUM_TCP) != 0)
2795d65abd66SPyun YongHyeon 					csum_flags |= RL_TDESC_CMD_TCPCSUM;
2796deb5c680SPyun YongHyeon 				if (((*m_head)->m_pkthdr.csum_flags &
2797deb5c680SPyun YongHyeon 				    CSUM_UDP) != 0)
2798d65abd66SPyun YongHyeon 					csum_flags |= RL_TDESC_CMD_UDPCSUM;
2799deb5c680SPyun YongHyeon 			} else {
2800deb5c680SPyun YongHyeon 				vlanctl |= RL_TDESC_CMD_IPCSUMV2;
2801deb5c680SPyun YongHyeon 				if (((*m_head)->m_pkthdr.csum_flags &
2802deb5c680SPyun YongHyeon 				    CSUM_TCP) != 0)
2803deb5c680SPyun YongHyeon 					vlanctl |= RL_TDESC_CMD_TCPCSUMV2;
2804deb5c680SPyun YongHyeon 				if (((*m_head)->m_pkthdr.csum_flags &
2805deb5c680SPyun YongHyeon 				    CSUM_UDP) != 0)
2806deb5c680SPyun YongHyeon 					vlanctl |= RL_TDESC_CMD_UDPCSUMV2;
2807deb5c680SPyun YongHyeon 			}
2808d65abd66SPyun YongHyeon 		}
280999c8ae87SPyun YongHyeon 	}
2810a94100faSBill Paul 
2811ccf34c81SPyun YongHyeon 	/*
2812ccf34c81SPyun YongHyeon 	 * Set up hardware VLAN tagging. Note: vlan tag info must
2813ccf34c81SPyun YongHyeon 	 * appear in all descriptors of a multi-descriptor
2814ccf34c81SPyun YongHyeon 	 * transmission attempt.
2815ccf34c81SPyun YongHyeon 	 */
2816ccf34c81SPyun YongHyeon 	if ((*m_head)->m_flags & M_VLANTAG)
2817bddff934SPyun YongHyeon 		vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) |
2818deb5c680SPyun YongHyeon 		    RL_TDESC_VLANCTL_TAG;
2819ccf34c81SPyun YongHyeon 
2820d65abd66SPyun YongHyeon 	si = prod;
2821d65abd66SPyun YongHyeon 	for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) {
2822d65abd66SPyun YongHyeon 		desc = &sc->rl_ldata.rl_tx_list[prod];
2823deb5c680SPyun YongHyeon 		desc->rl_vlanctl = htole32(vlanctl);
2824d65abd66SPyun YongHyeon 		desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr));
2825d65abd66SPyun YongHyeon 		desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr));
2826d65abd66SPyun YongHyeon 		cmdstat = segs[i].ds_len;
2827d65abd66SPyun YongHyeon 		if (i != 0)
2828d65abd66SPyun YongHyeon 			cmdstat |= RL_TDESC_CMD_OWN;
2829d65abd66SPyun YongHyeon 		if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1)
2830d65abd66SPyun YongHyeon 			cmdstat |= RL_TDESC_CMD_EOR;
2831d65abd66SPyun YongHyeon 		desc->rl_cmdstat = htole32(cmdstat | csum_flags);
2832d65abd66SPyun YongHyeon 		sc->rl_ldata.rl_tx_free--;
2833d65abd66SPyun YongHyeon 	}
2834d65abd66SPyun YongHyeon 	/* Update producer index. */
2835d65abd66SPyun YongHyeon 	sc->rl_ldata.rl_tx_prodidx = prod;
2836a94100faSBill Paul 
2837d65abd66SPyun YongHyeon 	/* Set EOF on the last descriptor. */
2838d65abd66SPyun YongHyeon 	ei = RL_TX_DESC_PRV(sc, prod);
2839d65abd66SPyun YongHyeon 	desc = &sc->rl_ldata.rl_tx_list[ei];
2840d65abd66SPyun YongHyeon 	desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF);
2841d65abd66SPyun YongHyeon 
2842d65abd66SPyun YongHyeon 	desc = &sc->rl_ldata.rl_tx_list[si];
2843d65abd66SPyun YongHyeon 	/* Set SOF and transfer ownership of packet to the chip. */
2844d65abd66SPyun YongHyeon 	desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF);
2845a94100faSBill Paul 
2846d65abd66SPyun YongHyeon 	/*
2847d65abd66SPyun YongHyeon 	 * Insure that the map for this transmission
2848d65abd66SPyun YongHyeon 	 * is placed at the array index of the last descriptor
2849d65abd66SPyun YongHyeon 	 * in this chain.  (Swap last and first dmamaps.)
2850d65abd66SPyun YongHyeon 	 */
2851d65abd66SPyun YongHyeon 	txd_last = &sc->rl_ldata.rl_tx_desc[ei];
2852d65abd66SPyun YongHyeon 	map = txd->tx_dmamap;
2853d65abd66SPyun YongHyeon 	txd->tx_dmamap = txd_last->tx_dmamap;
2854d65abd66SPyun YongHyeon 	txd_last->tx_dmamap = map;
2855d65abd66SPyun YongHyeon 	txd_last->tx_m = *m_head;
2856a94100faSBill Paul 
2857a94100faSBill Paul 	return (0);
2858a94100faSBill Paul }
2859a94100faSBill Paul 
286097b9d4baSJohn-Mark Gurney static void
2861d180a66fSPyun YongHyeon re_start(struct ifnet *ifp)
286297b9d4baSJohn-Mark Gurney {
2863d180a66fSPyun YongHyeon 	struct rl_softc		*sc;
286497b9d4baSJohn-Mark Gurney 
2865d180a66fSPyun YongHyeon 	sc = ifp->if_softc;
2866d180a66fSPyun YongHyeon 	RL_LOCK(sc);
2867d180a66fSPyun YongHyeon 	re_start_locked(ifp);
2868d180a66fSPyun YongHyeon 	RL_UNLOCK(sc);
286997b9d4baSJohn-Mark Gurney }
287097b9d4baSJohn-Mark Gurney 
2871a94100faSBill Paul /*
2872a94100faSBill Paul  * Main transmit routine for C+ and gigE NICs.
2873a94100faSBill Paul  */
2874a94100faSBill Paul static void
2875d180a66fSPyun YongHyeon re_start_locked(struct ifnet *ifp)
2876a94100faSBill Paul {
2877a94100faSBill Paul 	struct rl_softc		*sc;
2878d65abd66SPyun YongHyeon 	struct mbuf		*m_head;
2879d65abd66SPyun YongHyeon 	int			queued;
2880a94100faSBill Paul 
2881a94100faSBill Paul 	sc = ifp->if_softc;
288297b9d4baSJohn-Mark Gurney 
2883579a6e3cSLuigi Rizzo #ifdef DEV_NETMAP
2884579a6e3cSLuigi Rizzo 	/* XXX is this necessary ? */
2885579a6e3cSLuigi Rizzo 	if (ifp->if_capenable & IFCAP_NETMAP) {
2886579a6e3cSLuigi Rizzo 		struct netmap_kring *kring = &NA(ifp)->tx_rings[0];
2887579a6e3cSLuigi Rizzo 		if (sc->rl_ldata.rl_tx_prodidx != kring->nr_hwcur) {
2888579a6e3cSLuigi Rizzo 			/* kick the tx unit */
2889579a6e3cSLuigi Rizzo 			CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2890579a6e3cSLuigi Rizzo #ifdef RE_TX_MODERATION
2891579a6e3cSLuigi Rizzo 			CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2892579a6e3cSLuigi Rizzo #endif
2893579a6e3cSLuigi Rizzo 			sc->rl_watchdog_timer = 5;
2894579a6e3cSLuigi Rizzo 		}
2895579a6e3cSLuigi Rizzo 		return;
2896579a6e3cSLuigi Rizzo 	}
2897579a6e3cSLuigi Rizzo #endif /* DEV_NETMAP */
2898d65abd66SPyun YongHyeon 	if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2899d180a66fSPyun YongHyeon 	    IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0)
2900ed510fb0SBill Paul 		return;
2901a94100faSBill Paul 
2902d65abd66SPyun YongHyeon 	for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2903d65abd66SPyun YongHyeon 	    sc->rl_ldata.rl_tx_free > 1;) {
290452732175SMax Laier 		IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2905a94100faSBill Paul 		if (m_head == NULL)
2906a94100faSBill Paul 			break;
2907a94100faSBill Paul 
2908d65abd66SPyun YongHyeon 		if (re_encap(sc, &m_head) != 0) {
2909b4b95879SMarius Strobl 			if (m_head == NULL)
2910b4b95879SMarius Strobl 				break;
291152732175SMax Laier 			IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
291213f4c340SRobert Watson 			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2913a94100faSBill Paul 			break;
2914a94100faSBill Paul 		}
2915a94100faSBill Paul 
2916a94100faSBill Paul 		/*
2917a94100faSBill Paul 		 * If there's a BPF listener, bounce a copy of this frame
2918a94100faSBill Paul 		 * to him.
2919a94100faSBill Paul 		 */
292059a0d28bSChristian S.J. Peron 		ETHER_BPF_MTAP(ifp, m_head);
292152732175SMax Laier 
292252732175SMax Laier 		queued++;
2923a94100faSBill Paul 	}
2924a94100faSBill Paul 
2925ed510fb0SBill Paul 	if (queued == 0) {
2926ed510fb0SBill Paul #ifdef RE_TX_MODERATION
2927d65abd66SPyun YongHyeon 		if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt)
2928ed510fb0SBill Paul 			CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2929ed510fb0SBill Paul #endif
293052732175SMax Laier 		return;
2931ed510fb0SBill Paul 	}
293252732175SMax Laier 
2933a94100faSBill Paul 	/* Flush the TX descriptors */
2934a94100faSBill Paul 
2935a94100faSBill Paul 	bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
2936a94100faSBill Paul 	    sc->rl_ldata.rl_tx_list_map,
2937a94100faSBill Paul 	    BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
2938a94100faSBill Paul 
29390fc4974fSBill Paul 	CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);
2940a94100faSBill Paul 
2941ed510fb0SBill Paul #ifdef RE_TX_MODERATION
2942a94100faSBill Paul 	/*
2943a94100faSBill Paul 	 * Use the countdown timer for interrupt moderation.
2944a94100faSBill Paul 	 * 'TX done' interrupts are disabled. Instead, we reset the
2945a94100faSBill Paul 	 * countdown timer, which will begin counting until it hits
2946a94100faSBill Paul 	 * the value in the TIMERINT register, and then trigger an
2947a94100faSBill Paul 	 * interrupt. Each time we write to the TIMERCNT register,
2948a94100faSBill Paul 	 * the timer count is reset to 0.
2949a94100faSBill Paul 	 */
2950a94100faSBill Paul 	CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2951ed510fb0SBill Paul #endif
2952a94100faSBill Paul 
2953a94100faSBill Paul 	/*
2954a94100faSBill Paul 	 * Set a timeout in case the chip goes out to lunch.
2955a94100faSBill Paul 	 */
29561d545c7aSMarius Strobl 	sc->rl_watchdog_timer = 5;
2957a94100faSBill Paul }
2958a94100faSBill Paul 
2959a94100faSBill Paul static void
296081eee0ebSPyun YongHyeon re_set_jumbo(struct rl_softc *sc, int jumbo)
296181eee0ebSPyun YongHyeon {
296281eee0ebSPyun YongHyeon 
296381eee0ebSPyun YongHyeon 	if (sc->rl_hwrev->rl_rev == RL_HWREV_8168E_VL) {
296481eee0ebSPyun YongHyeon 		pci_set_max_read_req(sc->rl_dev, 4096);
296581eee0ebSPyun YongHyeon 		return;
296681eee0ebSPyun YongHyeon 	}
296781eee0ebSPyun YongHyeon 
296881eee0ebSPyun YongHyeon 	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
296981eee0ebSPyun YongHyeon 	if (jumbo != 0) {
2970e7e7593cSPyun YongHyeon 		CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) |
297181eee0ebSPyun YongHyeon 		    RL_CFG3_JUMBO_EN0);
297281eee0ebSPyun YongHyeon 		switch (sc->rl_hwrev->rl_rev) {
297381eee0ebSPyun YongHyeon 		case RL_HWREV_8168DP:
297481eee0ebSPyun YongHyeon 			break;
297581eee0ebSPyun YongHyeon 		case RL_HWREV_8168E:
2976e7e7593cSPyun YongHyeon 			CSR_WRITE_1(sc, sc->rl_cfg4,
2977e7e7593cSPyun YongHyeon 			    CSR_READ_1(sc, sc->rl_cfg4) | 0x01);
297881eee0ebSPyun YongHyeon 			break;
297981eee0ebSPyun YongHyeon 		default:
2980e7e7593cSPyun YongHyeon 			CSR_WRITE_1(sc, sc->rl_cfg4,
2981e7e7593cSPyun YongHyeon 			    CSR_READ_1(sc, sc->rl_cfg4) | RL_CFG4_JUMBO_EN1);
298281eee0ebSPyun YongHyeon 		}
298381eee0ebSPyun YongHyeon 	} else {
2984e7e7593cSPyun YongHyeon 		CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) &
298581eee0ebSPyun YongHyeon 		    ~RL_CFG3_JUMBO_EN0);
298681eee0ebSPyun YongHyeon 		switch (sc->rl_hwrev->rl_rev) {
298781eee0ebSPyun YongHyeon 		case RL_HWREV_8168DP:
298881eee0ebSPyun YongHyeon 			break;
298981eee0ebSPyun YongHyeon 		case RL_HWREV_8168E:
2990e7e7593cSPyun YongHyeon 			CSR_WRITE_1(sc, sc->rl_cfg4,
2991e7e7593cSPyun YongHyeon 			    CSR_READ_1(sc, sc->rl_cfg4) & ~0x01);
299281eee0ebSPyun YongHyeon 			break;
299381eee0ebSPyun YongHyeon 		default:
2994e7e7593cSPyun YongHyeon 			CSR_WRITE_1(sc, sc->rl_cfg4,
2995e7e7593cSPyun YongHyeon 			    CSR_READ_1(sc, sc->rl_cfg4) & ~RL_CFG4_JUMBO_EN1);
299681eee0ebSPyun YongHyeon 		}
299781eee0ebSPyun YongHyeon 	}
299881eee0ebSPyun YongHyeon 	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
299981eee0ebSPyun YongHyeon 
300081eee0ebSPyun YongHyeon 	switch (sc->rl_hwrev->rl_rev) {
300181eee0ebSPyun YongHyeon 	case RL_HWREV_8168DP:
300281eee0ebSPyun YongHyeon 		pci_set_max_read_req(sc->rl_dev, 4096);
300381eee0ebSPyun YongHyeon 		break;
300481eee0ebSPyun YongHyeon 	default:
300581eee0ebSPyun YongHyeon 		if (jumbo != 0)
300681eee0ebSPyun YongHyeon 			pci_set_max_read_req(sc->rl_dev, 512);
300781eee0ebSPyun YongHyeon 		else
300881eee0ebSPyun YongHyeon 			pci_set_max_read_req(sc->rl_dev, 4096);
300981eee0ebSPyun YongHyeon 	}
301081eee0ebSPyun YongHyeon }
301181eee0ebSPyun YongHyeon 
301281eee0ebSPyun YongHyeon static void
30137b5ffebfSPyun YongHyeon re_init(void *xsc)
3014a94100faSBill Paul {
3015a94100faSBill Paul 	struct rl_softc		*sc = xsc;
301697b9d4baSJohn-Mark Gurney 
301797b9d4baSJohn-Mark Gurney 	RL_LOCK(sc);
301897b9d4baSJohn-Mark Gurney 	re_init_locked(sc);
301997b9d4baSJohn-Mark Gurney 	RL_UNLOCK(sc);
302097b9d4baSJohn-Mark Gurney }
302197b9d4baSJohn-Mark Gurney 
302297b9d4baSJohn-Mark Gurney static void
30237b5ffebfSPyun YongHyeon re_init_locked(struct rl_softc *sc)
302497b9d4baSJohn-Mark Gurney {
3025fc74a9f9SBrooks Davis 	struct ifnet		*ifp = sc->rl_ifp;
3026a94100faSBill Paul 	struct mii_data		*mii;
3027566ca8caSJung-uk Kim 	uint32_t		reg;
302870acaecfSPyun YongHyeon 	uint16_t		cfg;
30294d3d7085SBernd Walter 	union {
30304d3d7085SBernd Walter 		uint32_t align_dummy;
30314d3d7085SBernd Walter 		u_char eaddr[ETHER_ADDR_LEN];
30324d3d7085SBernd Walter         } eaddr;
3033a94100faSBill Paul 
303497b9d4baSJohn-Mark Gurney 	RL_LOCK_ASSERT(sc);
303597b9d4baSJohn-Mark Gurney 
3036a94100faSBill Paul 	mii = device_get_softc(sc->rl_miibus);
3037a94100faSBill Paul 
30388476c243SPyun YongHyeon 	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
30398476c243SPyun YongHyeon 		return;
30408476c243SPyun YongHyeon 
3041a94100faSBill Paul 	/*
3042a94100faSBill Paul 	 * Cancel pending I/O and free all RX/TX buffers.
3043a94100faSBill Paul 	 */
3044a94100faSBill Paul 	re_stop(sc);
3045a94100faSBill Paul 
3046b659f1f0SPyun YongHyeon 	/* Put controller into known state. */
3047b659f1f0SPyun YongHyeon 	re_reset(sc);
3048b659f1f0SPyun YongHyeon 
3049a94100faSBill Paul 	/*
30504a814a5eSPyun YongHyeon 	 * For C+ mode, initialize the RX descriptors and mbufs.
30514a814a5eSPyun YongHyeon 	 */
305281eee0ebSPyun YongHyeon 	if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
305381eee0ebSPyun YongHyeon 		if (ifp->if_mtu > RL_MTU) {
305481eee0ebSPyun YongHyeon 			if (re_jrx_list_init(sc) != 0) {
305581eee0ebSPyun YongHyeon 				device_printf(sc->rl_dev,
305681eee0ebSPyun YongHyeon 				    "no memory for jumbo RX buffers\n");
305781eee0ebSPyun YongHyeon 				re_stop(sc);
305881eee0ebSPyun YongHyeon 				return;
305981eee0ebSPyun YongHyeon 			}
306081eee0ebSPyun YongHyeon 			/* Disable checksum offloading for jumbo frames. */
306181eee0ebSPyun YongHyeon 			ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_TSO4);
306281eee0ebSPyun YongHyeon 			ifp->if_hwassist &= ~(RE_CSUM_FEATURES | CSUM_TSO);
306381eee0ebSPyun YongHyeon 		} else {
306481eee0ebSPyun YongHyeon 			if (re_rx_list_init(sc) != 0) {
306581eee0ebSPyun YongHyeon 				device_printf(sc->rl_dev,
306681eee0ebSPyun YongHyeon 				    "no memory for RX buffers\n");
306781eee0ebSPyun YongHyeon 				re_stop(sc);
306881eee0ebSPyun YongHyeon 				return;
306981eee0ebSPyun YongHyeon 			}
307081eee0ebSPyun YongHyeon 		}
307181eee0ebSPyun YongHyeon 		re_set_jumbo(sc, ifp->if_mtu > RL_MTU);
307281eee0ebSPyun YongHyeon 	} else {
30734a814a5eSPyun YongHyeon 		if (re_rx_list_init(sc) != 0) {
30744a814a5eSPyun YongHyeon 			device_printf(sc->rl_dev, "no memory for RX buffers\n");
30754a814a5eSPyun YongHyeon 			re_stop(sc);
30764a814a5eSPyun YongHyeon 			return;
30774a814a5eSPyun YongHyeon 		}
307881eee0ebSPyun YongHyeon 		if ((sc->rl_flags & RL_FLAG_PCIE) != 0 &&
307981eee0ebSPyun YongHyeon 		    pci_get_device(sc->rl_dev) != RT_DEVICEID_8101E) {
308081eee0ebSPyun YongHyeon 			if (ifp->if_mtu > RL_MTU)
308181eee0ebSPyun YongHyeon 				pci_set_max_read_req(sc->rl_dev, 512);
308281eee0ebSPyun YongHyeon 			else
308381eee0ebSPyun YongHyeon 				pci_set_max_read_req(sc->rl_dev, 4096);
308481eee0ebSPyun YongHyeon 		}
308581eee0ebSPyun YongHyeon 	}
30864a814a5eSPyun YongHyeon 	re_tx_list_init(sc);
30874a814a5eSPyun YongHyeon 
30884a814a5eSPyun YongHyeon 	/*
3089c2c6548bSBill Paul 	 * Enable C+ RX and TX mode, as well as VLAN stripping and
3090edd03374SBill Paul 	 * RX checksum offload. We must configure the C+ register
3091c2c6548bSBill Paul 	 * before all others.
3092c2c6548bSBill Paul 	 */
309370acaecfSPyun YongHyeon 	cfg = RL_CPLUSCMD_PCI_MRW;
309470acaecfSPyun YongHyeon 	if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
309570acaecfSPyun YongHyeon 		cfg |= RL_CPLUSCMD_RXCSUM_ENB;
309670acaecfSPyun YongHyeon 	if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
309770acaecfSPyun YongHyeon 		cfg |= RL_CPLUSCMD_VLANSTRIP;
3098deb5c680SPyun YongHyeon 	if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) {
3099deb5c680SPyun YongHyeon 		cfg |= RL_CPLUSCMD_MACSTAT_DIS;
3100deb5c680SPyun YongHyeon 		/* XXX magic. */
3101deb5c680SPyun YongHyeon 		cfg |= 0x0001;
3102deb5c680SPyun YongHyeon 	} else
3103deb5c680SPyun YongHyeon 		cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB;
3104deb5c680SPyun YongHyeon 	CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg);
310581eee0ebSPyun YongHyeon 	if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SC ||
310681eee0ebSPyun YongHyeon 	    sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) {
3107566ca8caSJung-uk Kim 		reg = 0x000fff00;
3108e7e7593cSPyun YongHyeon 		if ((CSR_READ_1(sc, sc->rl_cfg2) & RL_CFG2_PCI66MHZ) != 0)
3109566ca8caSJung-uk Kim 			reg |= 0x000000ff;
311081eee0ebSPyun YongHyeon 		if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE)
3111566ca8caSJung-uk Kim 			reg |= 0x00f00000;
3112566ca8caSJung-uk Kim 		CSR_WRITE_4(sc, 0x7c, reg);
3113566ca8caSJung-uk Kim 		/* Disable interrupt mitigation. */
3114566ca8caSJung-uk Kim 		CSR_WRITE_2(sc, 0xe2, 0);
3115566ca8caSJung-uk Kim 	}
3116ae644087SPyun YongHyeon 	/*
3117ae644087SPyun YongHyeon 	 * Disable TSO if interface MTU size is greater than MSS
3118ae644087SPyun YongHyeon 	 * allowed in controller.
3119ae644087SPyun YongHyeon 	 */
3120ae644087SPyun YongHyeon 	if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) {
3121ae644087SPyun YongHyeon 		ifp->if_capenable &= ~IFCAP_TSO4;
3122ae644087SPyun YongHyeon 		ifp->if_hwassist &= ~CSUM_TSO;
3123ae644087SPyun YongHyeon 	}
3124c2c6548bSBill Paul 
3125c2c6548bSBill Paul 	/*
3126a94100faSBill Paul 	 * Init our MAC address.  Even though the chipset
3127a94100faSBill Paul 	 * documentation doesn't mention it, we need to enter "Config
3128a94100faSBill Paul 	 * register write enable" mode to modify the ID registers.
3129a94100faSBill Paul 	 */
31304d3d7085SBernd Walter 	/* Copy MAC address on stack to align. */
31314d3d7085SBernd Walter 	bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN);
3132a94100faSBill Paul 	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
3133ed510fb0SBill Paul 	CSR_WRITE_4(sc, RL_IDR0,
3134ed510fb0SBill Paul 	    htole32(*(u_int32_t *)(&eaddr.eaddr[0])));
3135ed510fb0SBill Paul 	CSR_WRITE_4(sc, RL_IDR4,
3136ed510fb0SBill Paul 	    htole32(*(u_int32_t *)(&eaddr.eaddr[4])));
3137a94100faSBill Paul 	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
3138a94100faSBill Paul 
3139a94100faSBill Paul 	/*
3140d01fac16SPyun YongHyeon 	 * Load the addresses of the RX and TX lists into the chip.
3141d01fac16SPyun YongHyeon 	 */
3142d01fac16SPyun YongHyeon 
3143d01fac16SPyun YongHyeon 	CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI,
3144d01fac16SPyun YongHyeon 	    RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr));
3145d01fac16SPyun YongHyeon 	CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO,
3146d01fac16SPyun YongHyeon 	    RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr));
3147d01fac16SPyun YongHyeon 
3148d01fac16SPyun YongHyeon 	CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI,
3149d01fac16SPyun YongHyeon 	    RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr));
3150d01fac16SPyun YongHyeon 	CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO,
3151d01fac16SPyun YongHyeon 	    RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr));
3152d01fac16SPyun YongHyeon 
3153d01fac16SPyun YongHyeon 	/*
3154a94100faSBill Paul 	 * Enable transmit and receive.
3155a94100faSBill Paul 	 */
3156a94100faSBill Paul 	CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
3157a94100faSBill Paul 
3158a94100faSBill Paul 	/*
3159ff191365SJung-uk Kim 	 * Set the initial TX configuration.
3160a94100faSBill Paul 	 */
3161abc8ff44SBill Paul 	if (sc->rl_testmode) {
3162abc8ff44SBill Paul 		if (sc->rl_type == RL_8169)
3163abc8ff44SBill Paul 			CSR_WRITE_4(sc, RL_TXCFG,
3164abc8ff44SBill Paul 			    RL_TXCFG_CONFIG|RL_LOOPTEST_ON);
3165a94100faSBill Paul 		else
3166abc8ff44SBill Paul 			CSR_WRITE_4(sc, RL_TXCFG,
3167abc8ff44SBill Paul 			    RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS);
3168abc8ff44SBill Paul 	} else
3169a94100faSBill Paul 		CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
3170d01fac16SPyun YongHyeon 
3171d01fac16SPyun YongHyeon 	CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16);
3172d01fac16SPyun YongHyeon 
3173a94100faSBill Paul 	/*
3174ff191365SJung-uk Kim 	 * Set the initial RX configuration.
3175a94100faSBill Paul 	 */
3176ff191365SJung-uk Kim 	re_set_rxmode(sc);
3177a94100faSBill Paul 
3178483cc440SPyun YongHyeon 	/* Configure interrupt moderation. */
3179483cc440SPyun YongHyeon 	if (sc->rl_type == RL_8169) {
3180483cc440SPyun YongHyeon 		/* Magic from vendor. */
31815e6906eeSPyun YongHyeon 		CSR_WRITE_2(sc, RL_INTRMOD, 0x5100);
3182483cc440SPyun YongHyeon 	}
3183483cc440SPyun YongHyeon 
3184a94100faSBill Paul #ifdef DEVICE_POLLING
3185a94100faSBill Paul 	/*
3186a94100faSBill Paul 	 * Disable interrupts if we are polling.
3187a94100faSBill Paul 	 */
318840929967SGleb Smirnoff 	if (ifp->if_capenable & IFCAP_POLLING)
3189a94100faSBill Paul 		CSR_WRITE_2(sc, RL_IMR, 0);
3190a94100faSBill Paul 	else	/* otherwise ... */
319140929967SGleb Smirnoff #endif
3192ed510fb0SBill Paul 
3193a94100faSBill Paul 	/*
3194a94100faSBill Paul 	 * Enable interrupts.
3195a94100faSBill Paul 	 */
3196a94100faSBill Paul 	if (sc->rl_testmode)
3197a94100faSBill Paul 		CSR_WRITE_2(sc, RL_IMR, 0);
3198a94100faSBill Paul 	else
3199a94100faSBill Paul 		CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
3200ed510fb0SBill Paul 	CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS);
3201a94100faSBill Paul 
3202a94100faSBill Paul 	/* Set initial TX threshold */
3203a94100faSBill Paul 	sc->rl_txthresh = RL_TX_THRESH_INIT;
3204a94100faSBill Paul 
3205a94100faSBill Paul 	/* Start RX/TX process. */
3206a94100faSBill Paul 	CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
3207a94100faSBill Paul #ifdef notdef
3208a94100faSBill Paul 	/* Enable receiver and transmitter. */
3209a94100faSBill Paul 	CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
3210a94100faSBill Paul #endif
3211a94100faSBill Paul 
3212a94100faSBill Paul 	/*
3213a94100faSBill Paul 	 * Initialize the timer interrupt register so that
3214a94100faSBill Paul 	 * a timer interrupt will be generated once the timer
3215a94100faSBill Paul 	 * reaches a certain number of ticks. The timer is
3216502be0f7SPyun YongHyeon 	 * reloaded on each transmit.
3217502be0f7SPyun YongHyeon 	 */
3218502be0f7SPyun YongHyeon #ifdef RE_TX_MODERATION
3219502be0f7SPyun YongHyeon 	/*
3220502be0f7SPyun YongHyeon 	 * Use timer interrupt register to moderate TX interrupt
3221a94100faSBill Paul 	 * moderation, which dramatically improves TX frame rate.
3222a94100faSBill Paul 	 */
3223a94100faSBill Paul 	if (sc->rl_type == RL_8169)
3224a94100faSBill Paul 		CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800);
3225a94100faSBill Paul 	else
3226a94100faSBill Paul 		CSR_WRITE_4(sc, RL_TIMERINT, 0x400);
3227502be0f7SPyun YongHyeon #else
3228502be0f7SPyun YongHyeon 	/*
3229502be0f7SPyun YongHyeon 	 * Use timer interrupt register to moderate RX interrupt
3230502be0f7SPyun YongHyeon 	 * moderation.
3231502be0f7SPyun YongHyeon 	 */
3232502be0f7SPyun YongHyeon 	if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 &&
3233502be0f7SPyun YongHyeon 	    intr_filter == 0) {
3234502be0f7SPyun YongHyeon 		if (sc->rl_type == RL_8169)
3235502be0f7SPyun YongHyeon 			CSR_WRITE_4(sc, RL_TIMERINT_8169,
3236502be0f7SPyun YongHyeon 			    RL_USECS(sc->rl_int_rx_mod));
3237502be0f7SPyun YongHyeon 	} else {
3238502be0f7SPyun YongHyeon 		if (sc->rl_type == RL_8169)
3239502be0f7SPyun YongHyeon 			CSR_WRITE_4(sc, RL_TIMERINT_8169, RL_USECS(0));
3240502be0f7SPyun YongHyeon 	}
3241ed510fb0SBill Paul #endif
3242a94100faSBill Paul 
3243a94100faSBill Paul 	/*
3244a94100faSBill Paul 	 * For 8169 gigE NICs, set the max allowed RX packet
3245a94100faSBill Paul 	 * size so we can receive jumbo frames.
3246a94100faSBill Paul 	 */
324789feeee4SPyun YongHyeon 	if (sc->rl_type == RL_8169) {
324881eee0ebSPyun YongHyeon 		if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
324981eee0ebSPyun YongHyeon 			/*
325081eee0ebSPyun YongHyeon 			 * For controllers that use new jumbo frame scheme,
32512df05392SSergey Kandaurov 			 * set maximum size of jumbo frame depending on
325281eee0ebSPyun YongHyeon 			 * controller revisions.
325381eee0ebSPyun YongHyeon 			 */
325481eee0ebSPyun YongHyeon 			if (ifp->if_mtu > RL_MTU)
325581eee0ebSPyun YongHyeon 				CSR_WRITE_2(sc, RL_MAXRXPKTLEN,
325681eee0ebSPyun YongHyeon 				    sc->rl_hwrev->rl_max_mtu +
325781eee0ebSPyun YongHyeon 				    ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN +
325881eee0ebSPyun YongHyeon 				    ETHER_CRC_LEN);
325989feeee4SPyun YongHyeon 			else
326081eee0ebSPyun YongHyeon 				CSR_WRITE_2(sc, RL_MAXRXPKTLEN,
326181eee0ebSPyun YongHyeon 				    RE_RX_DESC_BUFLEN);
326281eee0ebSPyun YongHyeon 		} else if ((sc->rl_flags & RL_FLAG_PCIE) != 0 &&
326381eee0ebSPyun YongHyeon 		    sc->rl_hwrev->rl_max_mtu == RL_MTU) {
326481eee0ebSPyun YongHyeon 			/* RTL810x has no jumbo frame support. */
326581eee0ebSPyun YongHyeon 			CSR_WRITE_2(sc, RL_MAXRXPKTLEN, RE_RX_DESC_BUFLEN);
326681eee0ebSPyun YongHyeon 		} else
3267a94100faSBill Paul 			CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383);
326889feeee4SPyun YongHyeon 	}
3269a94100faSBill Paul 
327097b9d4baSJohn-Mark Gurney 	if (sc->rl_testmode)
3271a94100faSBill Paul 		return;
3272a94100faSBill Paul 
3273e7e7593cSPyun YongHyeon 	CSR_WRITE_1(sc, sc->rl_cfg1, CSR_READ_1(sc, sc->rl_cfg1) |
3274e7e7593cSPyun YongHyeon 	    RL_CFG1_DRVLOAD);
3275a94100faSBill Paul 
327613f4c340SRobert Watson 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
327713f4c340SRobert Watson 	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3278a94100faSBill Paul 
3279351a76f9SPyun YongHyeon 	sc->rl_flags &= ~RL_FLAG_LINK;
32801662c49eSPyun YongHyeon 	mii_mediachg(mii);
32811662c49eSPyun YongHyeon 
32821d545c7aSMarius Strobl 	sc->rl_watchdog_timer = 0;
3283d1754a9bSJohn Baldwin 	callout_reset(&sc->rl_stat_callout, hz, re_tick, sc);
3284a94100faSBill Paul }
3285a94100faSBill Paul 
3286a94100faSBill Paul /*
3287a94100faSBill Paul  * Set media options.
3288a94100faSBill Paul  */
3289a94100faSBill Paul static int
32907b5ffebfSPyun YongHyeon re_ifmedia_upd(struct ifnet *ifp)
3291a94100faSBill Paul {
3292a94100faSBill Paul 	struct rl_softc		*sc;
3293a94100faSBill Paul 	struct mii_data		*mii;
32946f0f9b12SPyun YongHyeon 	int			error;
3295a94100faSBill Paul 
3296a94100faSBill Paul 	sc = ifp->if_softc;
3297a94100faSBill Paul 	mii = device_get_softc(sc->rl_miibus);
3298d1754a9bSJohn Baldwin 	RL_LOCK(sc);
32996f0f9b12SPyun YongHyeon 	error = mii_mediachg(mii);
3300d1754a9bSJohn Baldwin 	RL_UNLOCK(sc);
3301a94100faSBill Paul 
33026f0f9b12SPyun YongHyeon 	return (error);
3303a94100faSBill Paul }
3304a94100faSBill Paul 
3305a94100faSBill Paul /*
3306a94100faSBill Paul  * Report current media status.
3307a94100faSBill Paul  */
3308a94100faSBill Paul static void
33097b5ffebfSPyun YongHyeon re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3310a94100faSBill Paul {
3311a94100faSBill Paul 	struct rl_softc		*sc;
3312a94100faSBill Paul 	struct mii_data		*mii;
3313a94100faSBill Paul 
3314a94100faSBill Paul 	sc = ifp->if_softc;
3315a94100faSBill Paul 	mii = device_get_softc(sc->rl_miibus);
3316a94100faSBill Paul 
3317d1754a9bSJohn Baldwin 	RL_LOCK(sc);
3318a94100faSBill Paul 	mii_pollstat(mii);
3319a94100faSBill Paul 	ifmr->ifm_active = mii->mii_media_active;
3320a94100faSBill Paul 	ifmr->ifm_status = mii->mii_media_status;
332157c81d92SPyun YongHyeon 	RL_UNLOCK(sc);
3322a94100faSBill Paul }
3323a94100faSBill Paul 
3324a94100faSBill Paul static int
33257b5ffebfSPyun YongHyeon re_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3326a94100faSBill Paul {
3327a94100faSBill Paul 	struct rl_softc		*sc = ifp->if_softc;
3328a94100faSBill Paul 	struct ifreq		*ifr = (struct ifreq *) data;
3329a94100faSBill Paul 	struct mii_data		*mii;
3330bc2a1002SPyun YongHyeon 	uint32_t		rev;
333140929967SGleb Smirnoff 	int			error = 0;
3332a94100faSBill Paul 
3333a94100faSBill Paul 	switch (command) {
3334a94100faSBill Paul 	case SIOCSIFMTU:
333581eee0ebSPyun YongHyeon 		if (ifr->ifr_mtu < ETHERMIN ||
333681eee0ebSPyun YongHyeon 		    ifr->ifr_mtu > sc->rl_hwrev->rl_max_mtu) {
3337c1d0b573SPyun YongHyeon 			error = EINVAL;
3338c1d0b573SPyun YongHyeon 			break;
3339c1d0b573SPyun YongHyeon 		}
3340c1d0b573SPyun YongHyeon 		RL_LOCK(sc);
334181eee0ebSPyun YongHyeon 		if (ifp->if_mtu != ifr->ifr_mtu) {
3342a94100faSBill Paul 			ifp->if_mtu = ifr->ifr_mtu;
334381eee0ebSPyun YongHyeon 			if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 &&
334481eee0ebSPyun YongHyeon 			    (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
334581eee0ebSPyun YongHyeon 				ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
334681eee0ebSPyun YongHyeon 				re_init_locked(sc);
334781eee0ebSPyun YongHyeon 			}
3348ae644087SPyun YongHyeon 			if (ifp->if_mtu > RL_TSO_MTU &&
3349ae644087SPyun YongHyeon 			    (ifp->if_capenable & IFCAP_TSO4) != 0) {
335081eee0ebSPyun YongHyeon 				ifp->if_capenable &= ~(IFCAP_TSO4 |
335181eee0ebSPyun YongHyeon 				    IFCAP_VLAN_HWTSO);
3352ae644087SPyun YongHyeon 				ifp->if_hwassist &= ~CSUM_TSO;
335381eee0ebSPyun YongHyeon 			}
3354ecafbbb5SPyun YongHyeon 			VLAN_CAPABILITIES(ifp);
3355ae644087SPyun YongHyeon 		}
3356d1754a9bSJohn Baldwin 		RL_UNLOCK(sc);
3357a94100faSBill Paul 		break;
3358a94100faSBill Paul 	case SIOCSIFFLAGS:
335997b9d4baSJohn-Mark Gurney 		RL_LOCK(sc);
3360eed497bbSPyun YongHyeon 		if ((ifp->if_flags & IFF_UP) != 0) {
3361eed497bbSPyun YongHyeon 			if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
3362eed497bbSPyun YongHyeon 				if (((ifp->if_flags ^ sc->rl_if_flags)
33633021aef8SPyun YongHyeon 				    & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
3364ff191365SJung-uk Kim 					re_set_rxmode(sc);
3365eed497bbSPyun YongHyeon 			} else
336697b9d4baSJohn-Mark Gurney 				re_init_locked(sc);
3367eed497bbSPyun YongHyeon 		} else {
3368eed497bbSPyun YongHyeon 			if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
3369a94100faSBill Paul 				re_stop(sc);
3370eed497bbSPyun YongHyeon 		}
3371eed497bbSPyun YongHyeon 		sc->rl_if_flags = ifp->if_flags;
337297b9d4baSJohn-Mark Gurney 		RL_UNLOCK(sc);
3373a94100faSBill Paul 		break;
3374a94100faSBill Paul 	case SIOCADDMULTI:
3375a94100faSBill Paul 	case SIOCDELMULTI:
337697b9d4baSJohn-Mark Gurney 		RL_LOCK(sc);
33778476c243SPyun YongHyeon 		if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
3378ff191365SJung-uk Kim 			re_set_rxmode(sc);
337997b9d4baSJohn-Mark Gurney 		RL_UNLOCK(sc);
3380a94100faSBill Paul 		break;
3381a94100faSBill Paul 	case SIOCGIFMEDIA:
3382a94100faSBill Paul 	case SIOCSIFMEDIA:
3383a94100faSBill Paul 		mii = device_get_softc(sc->rl_miibus);
3384a94100faSBill Paul 		error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
3385a94100faSBill Paul 		break;
3386a94100faSBill Paul 	case SIOCSIFCAP:
338740929967SGleb Smirnoff 	    {
3388f051cb85SGleb Smirnoff 		int mask, reinit;
3389f051cb85SGleb Smirnoff 
3390f051cb85SGleb Smirnoff 		mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3391f051cb85SGleb Smirnoff 		reinit = 0;
339240929967SGleb Smirnoff #ifdef DEVICE_POLLING
339340929967SGleb Smirnoff 		if (mask & IFCAP_POLLING) {
339440929967SGleb Smirnoff 			if (ifr->ifr_reqcap & IFCAP_POLLING) {
339540929967SGleb Smirnoff 				error = ether_poll_register(re_poll, ifp);
339640929967SGleb Smirnoff 				if (error)
339740929967SGleb Smirnoff 					return (error);
3398d1754a9bSJohn Baldwin 				RL_LOCK(sc);
339940929967SGleb Smirnoff 				/* Disable interrupts */
340040929967SGleb Smirnoff 				CSR_WRITE_2(sc, RL_IMR, 0x0000);
340140929967SGleb Smirnoff 				ifp->if_capenable |= IFCAP_POLLING;
340240929967SGleb Smirnoff 				RL_UNLOCK(sc);
340340929967SGleb Smirnoff 			} else {
340440929967SGleb Smirnoff 				error = ether_poll_deregister(ifp);
340540929967SGleb Smirnoff 				/* Enable interrupts. */
340640929967SGleb Smirnoff 				RL_LOCK(sc);
340740929967SGleb Smirnoff 				CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
340840929967SGleb Smirnoff 				ifp->if_capenable &= ~IFCAP_POLLING;
340940929967SGleb Smirnoff 				RL_UNLOCK(sc);
341040929967SGleb Smirnoff 			}
341140929967SGleb Smirnoff 		}
341240929967SGleb Smirnoff #endif /* DEVICE_POLLING */
3413600af6c2SPyun YongHyeon 		RL_LOCK(sc);
3414d3b181aeSPyun YongHyeon 		if ((mask & IFCAP_TXCSUM) != 0 &&
3415d3b181aeSPyun YongHyeon 		    (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
3416d3b181aeSPyun YongHyeon 			ifp->if_capenable ^= IFCAP_TXCSUM;
3417bc2a1002SPyun YongHyeon 			if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) {
3418bc2a1002SPyun YongHyeon 				rev = sc->rl_hwrev->rl_rev;
3419bc2a1002SPyun YongHyeon 				if (rev == RL_HWREV_8168C ||
34203c2a957dSPyun YongHyeon 				    rev == RL_HWREV_8168C_SPIN2 ||
34213c2a957dSPyun YongHyeon 				    rev == RL_HWREV_8168CP)
3422bc2a1002SPyun YongHyeon 					ifp->if_hwassist |= CSUM_TCP | CSUM_UDP;
3423a94100faSBill Paul 				else
3424bc2a1002SPyun YongHyeon 					ifp->if_hwassist |= RE_CSUM_FEATURES;
3425bc2a1002SPyun YongHyeon 			} else
3426b61178a9SPyun YongHyeon 				ifp->if_hwassist &= ~RE_CSUM_FEATURES;
3427f051cb85SGleb Smirnoff 			reinit = 1;
342840929967SGleb Smirnoff 		}
3429d3b181aeSPyun YongHyeon 		if ((mask & IFCAP_RXCSUM) != 0 &&
3430d3b181aeSPyun YongHyeon 		    (ifp->if_capabilities & IFCAP_RXCSUM) != 0) {
3431d3b181aeSPyun YongHyeon 			ifp->if_capenable ^= IFCAP_RXCSUM;
3432d3b181aeSPyun YongHyeon 			reinit = 1;
3433d3b181aeSPyun YongHyeon 		}
3434ecafbbb5SPyun YongHyeon 		if ((mask & IFCAP_TSO4) != 0 &&
3435fca1e0abSBjoern A. Zeeb 		    (ifp->if_capabilities & IFCAP_TSO4) != 0) {
3436dc74159dSPyun YongHyeon 			ifp->if_capenable ^= IFCAP_TSO4;
3437ecafbbb5SPyun YongHyeon 			if ((IFCAP_TSO4 & ifp->if_capenable) != 0)
3438dc74159dSPyun YongHyeon 				ifp->if_hwassist |= CSUM_TSO;
3439dc74159dSPyun YongHyeon 			else
3440dc74159dSPyun YongHyeon 				ifp->if_hwassist &= ~CSUM_TSO;
3441ae644087SPyun YongHyeon 			if (ifp->if_mtu > RL_TSO_MTU &&
3442ae644087SPyun YongHyeon 			    (ifp->if_capenable & IFCAP_TSO4) != 0) {
3443ae644087SPyun YongHyeon 				ifp->if_capenable &= ~IFCAP_TSO4;
3444ae644087SPyun YongHyeon 				ifp->if_hwassist &= ~CSUM_TSO;
3445ae644087SPyun YongHyeon 			}
3446dc74159dSPyun YongHyeon 		}
3447ecafbbb5SPyun YongHyeon 		if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
3448ecafbbb5SPyun YongHyeon 		    (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
3449ecafbbb5SPyun YongHyeon 			ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
3450ecafbbb5SPyun YongHyeon 		if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
3451ecafbbb5SPyun YongHyeon 		    (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
3452ecafbbb5SPyun YongHyeon 			ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
3453ecafbbb5SPyun YongHyeon 			/* TSO over VLAN requires VLAN hardware tagging. */
3454ecafbbb5SPyun YongHyeon 			if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
3455ecafbbb5SPyun YongHyeon 				ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
3456ecafbbb5SPyun YongHyeon 			reinit = 1;
3457ecafbbb5SPyun YongHyeon 		}
345881eee0ebSPyun YongHyeon 		if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 &&
345981eee0ebSPyun YongHyeon 		    (mask & (IFCAP_HWCSUM | IFCAP_TSO4 |
346081eee0ebSPyun YongHyeon 		    IFCAP_VLAN_HWTSO)) != 0)
346181eee0ebSPyun YongHyeon 				reinit = 1;
34627467bd53SPyun YongHyeon 		if ((mask & IFCAP_WOL) != 0 &&
34637467bd53SPyun YongHyeon 		    (ifp->if_capabilities & IFCAP_WOL) != 0) {
34647467bd53SPyun YongHyeon 			if ((mask & IFCAP_WOL_UCAST) != 0)
34657467bd53SPyun YongHyeon 				ifp->if_capenable ^= IFCAP_WOL_UCAST;
34667467bd53SPyun YongHyeon 			if ((mask & IFCAP_WOL_MCAST) != 0)
34677467bd53SPyun YongHyeon 				ifp->if_capenable ^= IFCAP_WOL_MCAST;
34687467bd53SPyun YongHyeon 			if ((mask & IFCAP_WOL_MAGIC) != 0)
34697467bd53SPyun YongHyeon 				ifp->if_capenable ^= IFCAP_WOL_MAGIC;
34707467bd53SPyun YongHyeon 		}
34718476c243SPyun YongHyeon 		if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) {
34728476c243SPyun YongHyeon 			ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3473600af6c2SPyun YongHyeon 			re_init_locked(sc);
34748476c243SPyun YongHyeon 		}
3475600af6c2SPyun YongHyeon 		RL_UNLOCK(sc);
3476960fd5b3SPyun YongHyeon 		VLAN_CAPABILITIES(ifp);
347740929967SGleb Smirnoff 	    }
3478a94100faSBill Paul 		break;
3479a94100faSBill Paul 	default:
3480a94100faSBill Paul 		error = ether_ioctl(ifp, command, data);
3481a94100faSBill Paul 		break;
3482a94100faSBill Paul 	}
3483a94100faSBill Paul 
3484a94100faSBill Paul 	return (error);
3485a94100faSBill Paul }
3486a94100faSBill Paul 
3487a94100faSBill Paul static void
34887b5ffebfSPyun YongHyeon re_watchdog(struct rl_softc *sc)
34891d545c7aSMarius Strobl {
3490130b6dfbSPyun YongHyeon 	struct ifnet		*ifp;
3491a94100faSBill Paul 
34921d545c7aSMarius Strobl 	RL_LOCK_ASSERT(sc);
34931d545c7aSMarius Strobl 
34941d545c7aSMarius Strobl 	if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0)
34951d545c7aSMarius Strobl 		return;
34961d545c7aSMarius Strobl 
3497130b6dfbSPyun YongHyeon 	ifp = sc->rl_ifp;
3498a94100faSBill Paul 	re_txeof(sc);
3499130b6dfbSPyun YongHyeon 	if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) {
3500130b6dfbSPyun YongHyeon 		if_printf(ifp, "watchdog timeout (missed Tx interrupts) "
3501130b6dfbSPyun YongHyeon 		    "-- recovering\n");
3502130b6dfbSPyun YongHyeon 		if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3503d180a66fSPyun YongHyeon 			re_start_locked(ifp);
3504130b6dfbSPyun YongHyeon 		return;
3505130b6dfbSPyun YongHyeon 	}
3506130b6dfbSPyun YongHyeon 
3507130b6dfbSPyun YongHyeon 	if_printf(ifp, "watchdog timeout\n");
3508130b6dfbSPyun YongHyeon 	ifp->if_oerrors++;
3509130b6dfbSPyun YongHyeon 
35101abcdbd1SAttilio Rao 	re_rxeof(sc, NULL);
35118476c243SPyun YongHyeon 	ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
351297b9d4baSJohn-Mark Gurney 	re_init_locked(sc);
3513130b6dfbSPyun YongHyeon 	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
3514d180a66fSPyun YongHyeon 		re_start_locked(ifp);
3515a94100faSBill Paul }
3516a94100faSBill Paul 
3517a94100faSBill Paul /*
3518a94100faSBill Paul  * Stop the adapter and free any mbufs allocated to the
3519a94100faSBill Paul  * RX and TX lists.
3520a94100faSBill Paul  */
3521a94100faSBill Paul static void
35227b5ffebfSPyun YongHyeon re_stop(struct rl_softc *sc)
3523a94100faSBill Paul {
35240ce0868aSPyun YongHyeon 	int			i;
3525a94100faSBill Paul 	struct ifnet		*ifp;
3526d65abd66SPyun YongHyeon 	struct rl_txdesc	*txd;
3527d65abd66SPyun YongHyeon 	struct rl_rxdesc	*rxd;
3528a94100faSBill Paul 
352997b9d4baSJohn-Mark Gurney 	RL_LOCK_ASSERT(sc);
353097b9d4baSJohn-Mark Gurney 
3531fc74a9f9SBrooks Davis 	ifp = sc->rl_ifp;
3532a94100faSBill Paul 
35331d545c7aSMarius Strobl 	sc->rl_watchdog_timer = 0;
3534d1754a9bSJohn Baldwin 	callout_stop(&sc->rl_stat_callout);
353513f4c340SRobert Watson 	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3536a94100faSBill Paul 
3537fcb220acSPyun YongHyeon 	/*
3538fcb220acSPyun YongHyeon 	 * Disable accepting frames to put RX MAC into idle state.
3539fcb220acSPyun YongHyeon 	 * Otherwise it's possible to get frames while stop command
3540fcb220acSPyun YongHyeon 	 * execution is in progress and controller can DMA the frame
3541fcb220acSPyun YongHyeon 	 * to already freed RX buffer during that period.
3542fcb220acSPyun YongHyeon 	 */
3543fcb220acSPyun YongHyeon 	CSR_WRITE_4(sc, RL_RXCFG, CSR_READ_4(sc, RL_RXCFG) &
3544fcb220acSPyun YongHyeon 	    ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_MULTI |
3545fcb220acSPyun YongHyeon 	    RL_RXCFG_RX_BROAD));
3546fcb220acSPyun YongHyeon 
3547eef0e496SPyun YongHyeon 	if ((sc->rl_flags & RL_FLAG_WAIT_TXPOLL) != 0) {
3548eef0e496SPyun YongHyeon 		for (i = RL_TIMEOUT; i > 0; i--) {
3549eef0e496SPyun YongHyeon 			if ((CSR_READ_1(sc, sc->rl_txstart) &
3550eef0e496SPyun YongHyeon 			    RL_TXSTART_START) == 0)
3551eef0e496SPyun YongHyeon 				break;
3552eef0e496SPyun YongHyeon 			DELAY(20);
3553eef0e496SPyun YongHyeon 		}
3554eef0e496SPyun YongHyeon 		if (i == 0)
3555eef0e496SPyun YongHyeon 			device_printf(sc->rl_dev,
3556eef0e496SPyun YongHyeon 			    "stopping TX poll timed out!\n");
3557eef0e496SPyun YongHyeon 		CSR_WRITE_1(sc, RL_COMMAND, 0x00);
3558eef0e496SPyun YongHyeon 	} else if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0) {
3559ead8fc66SPyun YongHyeon 		CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB |
3560ead8fc66SPyun YongHyeon 		    RL_CMD_RX_ENB);
3561eef0e496SPyun YongHyeon 		if ((sc->rl_flags & RL_FLAG_CMDSTOP_WAIT_TXQ) != 0) {
3562eef0e496SPyun YongHyeon 			for (i = RL_TIMEOUT; i > 0; i--) {
3563eef0e496SPyun YongHyeon 				if ((CSR_READ_4(sc, RL_TXCFG) &
3564eef0e496SPyun YongHyeon 				    RL_TXCFG_QUEUE_EMPTY) != 0)
3565eef0e496SPyun YongHyeon 					break;
3566eef0e496SPyun YongHyeon 				DELAY(100);
3567eef0e496SPyun YongHyeon 			}
3568eef0e496SPyun YongHyeon 			if (i == 0)
3569eef0e496SPyun YongHyeon 				device_printf(sc->rl_dev,
3570eef0e496SPyun YongHyeon 				   "stopping TXQ timed out!\n");
3571eef0e496SPyun YongHyeon 		}
3572eef0e496SPyun YongHyeon 	} else
3573a94100faSBill Paul 		CSR_WRITE_1(sc, RL_COMMAND, 0x00);
3574ead8fc66SPyun YongHyeon 	DELAY(1000);
3575a94100faSBill Paul 	CSR_WRITE_2(sc, RL_IMR, 0x0000);
3576ed510fb0SBill Paul 	CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
3577a94100faSBill Paul 
3578a94100faSBill Paul 	if (sc->rl_head != NULL) {
3579a94100faSBill Paul 		m_freem(sc->rl_head);
3580a94100faSBill Paul 		sc->rl_head = sc->rl_tail = NULL;
3581a94100faSBill Paul 	}
3582a94100faSBill Paul 
3583a94100faSBill Paul 	/* Free the TX list buffers. */
3584d65abd66SPyun YongHyeon 	for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) {
3585d65abd66SPyun YongHyeon 		txd = &sc->rl_ldata.rl_tx_desc[i];
3586d65abd66SPyun YongHyeon 		if (txd->tx_m != NULL) {
3587d65abd66SPyun YongHyeon 			bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag,
3588d65abd66SPyun YongHyeon 			    txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
3589d65abd66SPyun YongHyeon 			bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag,
3590d65abd66SPyun YongHyeon 			    txd->tx_dmamap);
3591d65abd66SPyun YongHyeon 			m_freem(txd->tx_m);
3592d65abd66SPyun YongHyeon 			txd->tx_m = NULL;
3593a94100faSBill Paul 		}
3594a94100faSBill Paul 	}
3595a94100faSBill Paul 
3596a94100faSBill Paul 	/* Free the RX list buffers. */
3597d65abd66SPyun YongHyeon 	for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
3598d65abd66SPyun YongHyeon 		rxd = &sc->rl_ldata.rl_rx_desc[i];
3599d65abd66SPyun YongHyeon 		if (rxd->rx_m != NULL) {
3600cba16362SPyun YongHyeon 			bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag,
3601d65abd66SPyun YongHyeon 			    rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
3602d65abd66SPyun YongHyeon 			bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag,
3603d65abd66SPyun YongHyeon 			    rxd->rx_dmamap);
3604d65abd66SPyun YongHyeon 			m_freem(rxd->rx_m);
3605d65abd66SPyun YongHyeon 			rxd->rx_m = NULL;
3606a94100faSBill Paul 		}
3607a94100faSBill Paul 	}
36081f32d3b7SPyun YongHyeon 
36091f32d3b7SPyun YongHyeon 	if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) {
36101f32d3b7SPyun YongHyeon 		for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) {
36111f32d3b7SPyun YongHyeon 			rxd = &sc->rl_ldata.rl_jrx_desc[i];
36121f32d3b7SPyun YongHyeon 			if (rxd->rx_m != NULL) {
36131f32d3b7SPyun YongHyeon 				bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag,
36141f32d3b7SPyun YongHyeon 				    rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
36151f32d3b7SPyun YongHyeon 				bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag,
36161f32d3b7SPyun YongHyeon 				    rxd->rx_dmamap);
36171f32d3b7SPyun YongHyeon 				m_freem(rxd->rx_m);
36181f32d3b7SPyun YongHyeon 				rxd->rx_m = NULL;
36191f32d3b7SPyun YongHyeon 			}
36201f32d3b7SPyun YongHyeon 		}
36211f32d3b7SPyun YongHyeon 	}
3622a94100faSBill Paul }
3623a94100faSBill Paul 
3624a94100faSBill Paul /*
3625a94100faSBill Paul  * Device suspend routine.  Stop the interface and save some PCI
3626a94100faSBill Paul  * settings in case the BIOS doesn't restore them properly on
3627a94100faSBill Paul  * resume.
3628a94100faSBill Paul  */
3629a94100faSBill Paul static int
36307b5ffebfSPyun YongHyeon re_suspend(device_t dev)
3631a94100faSBill Paul {
3632a94100faSBill Paul 	struct rl_softc		*sc;
3633a94100faSBill Paul 
3634a94100faSBill Paul 	sc = device_get_softc(dev);
3635a94100faSBill Paul 
363697b9d4baSJohn-Mark Gurney 	RL_LOCK(sc);
3637a94100faSBill Paul 	re_stop(sc);
36387467bd53SPyun YongHyeon 	re_setwol(sc);
3639a94100faSBill Paul 	sc->suspended = 1;
364097b9d4baSJohn-Mark Gurney 	RL_UNLOCK(sc);
3641a94100faSBill Paul 
3642a94100faSBill Paul 	return (0);
3643a94100faSBill Paul }
3644a94100faSBill Paul 
3645a94100faSBill Paul /*
3646a94100faSBill Paul  * Device resume routine.  Restore some PCI settings in case the BIOS
3647a94100faSBill Paul  * doesn't, re-enable busmastering, and restart the interface if
3648a94100faSBill Paul  * appropriate.
3649a94100faSBill Paul  */
3650a94100faSBill Paul static int
36517b5ffebfSPyun YongHyeon re_resume(device_t dev)
3652a94100faSBill Paul {
3653a94100faSBill Paul 	struct rl_softc		*sc;
3654a94100faSBill Paul 	struct ifnet		*ifp;
3655a94100faSBill Paul 
3656a94100faSBill Paul 	sc = device_get_softc(dev);
365797b9d4baSJohn-Mark Gurney 
365897b9d4baSJohn-Mark Gurney 	RL_LOCK(sc);
365997b9d4baSJohn-Mark Gurney 
3660fc74a9f9SBrooks Davis 	ifp = sc->rl_ifp;
366161f45a72SPyun YongHyeon 	/* Take controller out of sleep mode. */
366261f45a72SPyun YongHyeon 	if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) {
366361f45a72SPyun YongHyeon 		if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80)
366461f45a72SPyun YongHyeon 			CSR_WRITE_1(sc, RL_GPIO,
366561f45a72SPyun YongHyeon 			    CSR_READ_1(sc, RL_GPIO) | 0x01);
366661f45a72SPyun YongHyeon 	}
3667a94100faSBill Paul 
36687467bd53SPyun YongHyeon 	/*
36697467bd53SPyun YongHyeon 	 * Clear WOL matching such that normal Rx filtering
36707467bd53SPyun YongHyeon 	 * wouldn't interfere with WOL patterns.
36717467bd53SPyun YongHyeon 	 */
36727467bd53SPyun YongHyeon 	re_clrwol(sc);
367301d1a6c3SPyun YongHyeon 
367401d1a6c3SPyun YongHyeon 	/* reinitialize interface if necessary */
367501d1a6c3SPyun YongHyeon 	if (ifp->if_flags & IFF_UP)
367601d1a6c3SPyun YongHyeon 		re_init_locked(sc);
367701d1a6c3SPyun YongHyeon 
3678a94100faSBill Paul 	sc->suspended = 0;
367997b9d4baSJohn-Mark Gurney 	RL_UNLOCK(sc);
3680a94100faSBill Paul 
3681a94100faSBill Paul 	return (0);
3682a94100faSBill Paul }
3683a94100faSBill Paul 
3684a94100faSBill Paul /*
3685a94100faSBill Paul  * Stop all chip I/O so that the kernel's probe routines don't
3686a94100faSBill Paul  * get confused by errant DMAs when rebooting.
3687a94100faSBill Paul  */
36886a087a87SPyun YongHyeon static int
36897b5ffebfSPyun YongHyeon re_shutdown(device_t dev)
3690a94100faSBill Paul {
3691a94100faSBill Paul 	struct rl_softc		*sc;
3692a94100faSBill Paul 
3693a94100faSBill Paul 	sc = device_get_softc(dev);
3694a94100faSBill Paul 
369597b9d4baSJohn-Mark Gurney 	RL_LOCK(sc);
3696a94100faSBill Paul 	re_stop(sc);
3697536fde34SMaxim Sobolev 	/*
3698536fde34SMaxim Sobolev 	 * Mark interface as down since otherwise we will panic if
3699536fde34SMaxim Sobolev 	 * interrupt comes in later on, which can happen in some
370072293673SRuslan Ermilov 	 * cases.
3701536fde34SMaxim Sobolev 	 */
3702536fde34SMaxim Sobolev 	sc->rl_ifp->if_flags &= ~IFF_UP;
37037467bd53SPyun YongHyeon 	re_setwol(sc);
370497b9d4baSJohn-Mark Gurney 	RL_UNLOCK(sc);
37056a087a87SPyun YongHyeon 
37066a087a87SPyun YongHyeon 	return (0);
3707a94100faSBill Paul }
37087467bd53SPyun YongHyeon 
37097467bd53SPyun YongHyeon static void
37106830588dSPyun YongHyeon re_set_linkspeed(struct rl_softc *sc)
37116830588dSPyun YongHyeon {
37126830588dSPyun YongHyeon 	struct mii_softc *miisc;
37136830588dSPyun YongHyeon 	struct mii_data *mii;
37146830588dSPyun YongHyeon 	int aneg, i, phyno;
37156830588dSPyun YongHyeon 
37166830588dSPyun YongHyeon 	RL_LOCK_ASSERT(sc);
37176830588dSPyun YongHyeon 
37186830588dSPyun YongHyeon 	mii = device_get_softc(sc->rl_miibus);
37196830588dSPyun YongHyeon 	mii_pollstat(mii);
37206830588dSPyun YongHyeon 	aneg = 0;
37216830588dSPyun YongHyeon 	if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
37226830588dSPyun YongHyeon 	    (IFM_ACTIVE | IFM_AVALID)) {
37236830588dSPyun YongHyeon 		switch IFM_SUBTYPE(mii->mii_media_active) {
37246830588dSPyun YongHyeon 		case IFM_10_T:
37256830588dSPyun YongHyeon 		case IFM_100_TX:
37266830588dSPyun YongHyeon 			return;
37276830588dSPyun YongHyeon 		case IFM_1000_T:
37286830588dSPyun YongHyeon 			aneg++;
37296830588dSPyun YongHyeon 			break;
37306830588dSPyun YongHyeon 		default:
37316830588dSPyun YongHyeon 			break;
37326830588dSPyun YongHyeon 		}
37336830588dSPyun YongHyeon 	}
37346830588dSPyun YongHyeon 	miisc = LIST_FIRST(&mii->mii_phys);
37356830588dSPyun YongHyeon 	phyno = miisc->mii_phy;
37366830588dSPyun YongHyeon 	LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
37376830588dSPyun YongHyeon 		PHY_RESET(miisc);
37386830588dSPyun YongHyeon 	re_miibus_writereg(sc->rl_dev, phyno, MII_100T2CR, 0);
37396830588dSPyun YongHyeon 	re_miibus_writereg(sc->rl_dev, phyno,
37406830588dSPyun YongHyeon 	    MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
37416830588dSPyun YongHyeon 	re_miibus_writereg(sc->rl_dev, phyno,
37426830588dSPyun YongHyeon 	    MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG);
37436830588dSPyun YongHyeon 	DELAY(1000);
37446830588dSPyun YongHyeon 	if (aneg != 0) {
37456830588dSPyun YongHyeon 		/*
37466830588dSPyun YongHyeon 		 * Poll link state until re(4) get a 10/100Mbps link.
37476830588dSPyun YongHyeon 		 */
37486830588dSPyun YongHyeon 		for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
37496830588dSPyun YongHyeon 			mii_pollstat(mii);
37506830588dSPyun YongHyeon 			if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID))
37516830588dSPyun YongHyeon 			    == (IFM_ACTIVE | IFM_AVALID)) {
37526830588dSPyun YongHyeon 				switch (IFM_SUBTYPE(mii->mii_media_active)) {
37536830588dSPyun YongHyeon 				case IFM_10_T:
37546830588dSPyun YongHyeon 				case IFM_100_TX:
37556830588dSPyun YongHyeon 					return;
37566830588dSPyun YongHyeon 				default:
37576830588dSPyun YongHyeon 					break;
37586830588dSPyun YongHyeon 				}
37596830588dSPyun YongHyeon 			}
37606830588dSPyun YongHyeon 			RL_UNLOCK(sc);
37616830588dSPyun YongHyeon 			pause("relnk", hz);
37626830588dSPyun YongHyeon 			RL_LOCK(sc);
37636830588dSPyun YongHyeon 		}
37646830588dSPyun YongHyeon 		if (i == MII_ANEGTICKS_GIGE)
37656830588dSPyun YongHyeon 			device_printf(sc->rl_dev,
37666830588dSPyun YongHyeon 			    "establishing a link failed, WOL may not work!");
37676830588dSPyun YongHyeon 	}
37686830588dSPyun YongHyeon 	/*
37696830588dSPyun YongHyeon 	 * No link, force MAC to have 100Mbps, full-duplex link.
37706830588dSPyun YongHyeon 	 * MAC does not require reprogramming on resolved speed/duplex,
37716830588dSPyun YongHyeon 	 * so this is just for completeness.
37726830588dSPyun YongHyeon 	 */
37736830588dSPyun YongHyeon 	mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
37746830588dSPyun YongHyeon 	mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
37756830588dSPyun YongHyeon }
37766830588dSPyun YongHyeon 
37776830588dSPyun YongHyeon static void
37787b5ffebfSPyun YongHyeon re_setwol(struct rl_softc *sc)
37797467bd53SPyun YongHyeon {
37807467bd53SPyun YongHyeon 	struct ifnet		*ifp;
37817467bd53SPyun YongHyeon 	int			pmc;
37827467bd53SPyun YongHyeon 	uint16_t		pmstat;
37837467bd53SPyun YongHyeon 	uint8_t			v;
37847467bd53SPyun YongHyeon 
37857467bd53SPyun YongHyeon 	RL_LOCK_ASSERT(sc);
37867467bd53SPyun YongHyeon 
37873b0a4aefSJohn Baldwin 	if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
37887467bd53SPyun YongHyeon 		return;
37897467bd53SPyun YongHyeon 
37907467bd53SPyun YongHyeon 	ifp = sc->rl_ifp;
379161f45a72SPyun YongHyeon 	/* Put controller into sleep mode. */
379261f45a72SPyun YongHyeon 	if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) {
379361f45a72SPyun YongHyeon 		if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80)
379461f45a72SPyun YongHyeon 			CSR_WRITE_1(sc, RL_GPIO,
379561f45a72SPyun YongHyeon 			    CSR_READ_1(sc, RL_GPIO) & ~0x01);
379661f45a72SPyun YongHyeon 	}
3797fcb220acSPyun YongHyeon 	if ((ifp->if_capenable & IFCAP_WOL) != 0) {
3798fcb220acSPyun YongHyeon 		re_set_rxmode(sc);
37996830588dSPyun YongHyeon 		if ((sc->rl_flags & RL_FLAG_WOL_MANLINK) != 0)
38006830588dSPyun YongHyeon 			re_set_linkspeed(sc);
3801fcb220acSPyun YongHyeon 		if ((sc->rl_flags & RL_FLAG_WOLRXENB) != 0)
3802886ff602SPyun YongHyeon 			CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB);
3803fcb220acSPyun YongHyeon 	}
38047467bd53SPyun YongHyeon 	/* Enable config register write. */
38057467bd53SPyun YongHyeon 	CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
38067467bd53SPyun YongHyeon 
38077467bd53SPyun YongHyeon 	/* Enable PME. */
3808e7e7593cSPyun YongHyeon 	v = CSR_READ_1(sc, sc->rl_cfg1);
38097467bd53SPyun YongHyeon 	v &= ~RL_CFG1_PME;
38107467bd53SPyun YongHyeon 	if ((ifp->if_capenable & IFCAP_WOL) != 0)
38117467bd53SPyun YongHyeon 		v |= RL_CFG1_PME;
3812e7e7593cSPyun YongHyeon 	CSR_WRITE_1(sc, sc->rl_cfg1, v);
38137467bd53SPyun YongHyeon 
3814e7e7593cSPyun YongHyeon 	v = CSR_READ_1(sc, sc->rl_cfg3);
38157467bd53SPyun YongHyeon 	v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
38167467bd53SPyun YongHyeon 	if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
38177467bd53SPyun YongHyeon 		v |= RL_CFG3_WOL_MAGIC;
3818e7e7593cSPyun YongHyeon 	CSR_WRITE_1(sc, sc->rl_cfg3, v);
38197467bd53SPyun YongHyeon 
3820e7e7593cSPyun YongHyeon 	v = CSR_READ_1(sc, sc->rl_cfg5);
382144f7cbf5SPyun YongHyeon 	v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST |
382244f7cbf5SPyun YongHyeon 	    RL_CFG5_WOL_LANWAKE);
38237467bd53SPyun YongHyeon 	if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0)
38247467bd53SPyun YongHyeon 		v |= RL_CFG5_WOL_UCAST;
38257467bd53SPyun YongHyeon 	if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
38267467bd53SPyun YongHyeon 		v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST;
38277467bd53SPyun YongHyeon 	if ((ifp->if_capenable & IFCAP_WOL) != 0)
38287467bd53SPyun YongHyeon 		v |= RL_CFG5_WOL_LANWAKE;
3829e7e7593cSPyun YongHyeon 	CSR_WRITE_1(sc, sc->rl_cfg5, v);
38307467bd53SPyun YongHyeon 
383144f7cbf5SPyun YongHyeon 	/* Config register write done. */
383244f7cbf5SPyun YongHyeon 	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
383344f7cbf5SPyun YongHyeon 
3834bc6b129bSPyun YongHyeon 	if ((ifp->if_capenable & IFCAP_WOL) == 0 &&
3835d0c45156SPyun YongHyeon 	    (sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0)
3836d0c45156SPyun YongHyeon 		CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) & ~0x80);
38377467bd53SPyun YongHyeon 	/*
38387467bd53SPyun YongHyeon 	 * It seems that hardware resets its link speed to 100Mbps in
38397467bd53SPyun YongHyeon 	 * power down mode so switching to 100Mbps in driver is not
38407467bd53SPyun YongHyeon 	 * needed.
38417467bd53SPyun YongHyeon 	 */
38427467bd53SPyun YongHyeon 
38437467bd53SPyun YongHyeon 	/* Request PME if WOL is requested. */
38447467bd53SPyun YongHyeon 	pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2);
38457467bd53SPyun YongHyeon 	pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
38467467bd53SPyun YongHyeon 	if ((ifp->if_capenable & IFCAP_WOL) != 0)
38477467bd53SPyun YongHyeon 		pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
38487467bd53SPyun YongHyeon 	pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
38497467bd53SPyun YongHyeon }
38507467bd53SPyun YongHyeon 
38517467bd53SPyun YongHyeon static void
38527b5ffebfSPyun YongHyeon re_clrwol(struct rl_softc *sc)
38537467bd53SPyun YongHyeon {
38547467bd53SPyun YongHyeon 	int			pmc;
38557467bd53SPyun YongHyeon 	uint8_t			v;
38567467bd53SPyun YongHyeon 
38577467bd53SPyun YongHyeon 	RL_LOCK_ASSERT(sc);
38587467bd53SPyun YongHyeon 
38593b0a4aefSJohn Baldwin 	if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0)
38607467bd53SPyun YongHyeon 		return;
38617467bd53SPyun YongHyeon 
38627467bd53SPyun YongHyeon 	/* Enable config register write. */
38637467bd53SPyun YongHyeon 	CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
38647467bd53SPyun YongHyeon 
3865e7e7593cSPyun YongHyeon 	v = CSR_READ_1(sc, sc->rl_cfg3);
38667467bd53SPyun YongHyeon 	v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
3867e7e7593cSPyun YongHyeon 	CSR_WRITE_1(sc, sc->rl_cfg3, v);
38687467bd53SPyun YongHyeon 
38697467bd53SPyun YongHyeon 	/* Config register write done. */
3870f98dd8cfSPyun YongHyeon 	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
38717467bd53SPyun YongHyeon 
3872e7e7593cSPyun YongHyeon 	v = CSR_READ_1(sc, sc->rl_cfg5);
38737467bd53SPyun YongHyeon 	v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST);
38747467bd53SPyun YongHyeon 	v &= ~RL_CFG5_WOL_LANWAKE;
3875e7e7593cSPyun YongHyeon 	CSR_WRITE_1(sc, sc->rl_cfg5, v);
38767467bd53SPyun YongHyeon }
38770534aae0SPyun YongHyeon 
38780534aae0SPyun YongHyeon static void
38790534aae0SPyun YongHyeon re_add_sysctls(struct rl_softc *sc)
38800534aae0SPyun YongHyeon {
38810534aae0SPyun YongHyeon 	struct sysctl_ctx_list	*ctx;
38820534aae0SPyun YongHyeon 	struct sysctl_oid_list	*children;
3883502be0f7SPyun YongHyeon 	int			error;
38840534aae0SPyun YongHyeon 
38850534aae0SPyun YongHyeon 	ctx = device_get_sysctl_ctx(sc->rl_dev);
38860534aae0SPyun YongHyeon 	children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev));
38870534aae0SPyun YongHyeon 
38880534aae0SPyun YongHyeon 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "stats",
38890534aae0SPyun YongHyeon 	    CTLTYPE_INT | CTLFLAG_RW, sc, 0, re_sysctl_stats, "I",
38900534aae0SPyun YongHyeon 	    "Statistics Information");
3891502be0f7SPyun YongHyeon 	if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0)
3892502be0f7SPyun YongHyeon 		return;
3893502be0f7SPyun YongHyeon 
3894502be0f7SPyun YongHyeon 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "int_rx_mod",
3895502be0f7SPyun YongHyeon 	    CTLTYPE_INT | CTLFLAG_RW, &sc->rl_int_rx_mod, 0,
3896502be0f7SPyun YongHyeon 	    sysctl_hw_re_int_mod, "I", "re RX interrupt moderation");
3897502be0f7SPyun YongHyeon 	/* Pull in device tunables. */
3898502be0f7SPyun YongHyeon 	sc->rl_int_rx_mod = RL_TIMER_DEFAULT;
3899502be0f7SPyun YongHyeon 	error = resource_int_value(device_get_name(sc->rl_dev),
3900502be0f7SPyun YongHyeon 	    device_get_unit(sc->rl_dev), "int_rx_mod", &sc->rl_int_rx_mod);
3901502be0f7SPyun YongHyeon 	if (error == 0) {
3902502be0f7SPyun YongHyeon 		if (sc->rl_int_rx_mod < RL_TIMER_MIN ||
3903502be0f7SPyun YongHyeon 		    sc->rl_int_rx_mod > RL_TIMER_MAX) {
3904502be0f7SPyun YongHyeon 			device_printf(sc->rl_dev, "int_rx_mod value out of "
3905502be0f7SPyun YongHyeon 			    "range; using default: %d\n",
3906502be0f7SPyun YongHyeon 			    RL_TIMER_DEFAULT);
3907502be0f7SPyun YongHyeon 			sc->rl_int_rx_mod = RL_TIMER_DEFAULT;
3908502be0f7SPyun YongHyeon 		}
3909502be0f7SPyun YongHyeon 	}
3910502be0f7SPyun YongHyeon 
39110534aae0SPyun YongHyeon }
39120534aae0SPyun YongHyeon 
39130534aae0SPyun YongHyeon static int
39140534aae0SPyun YongHyeon re_sysctl_stats(SYSCTL_HANDLER_ARGS)
39150534aae0SPyun YongHyeon {
39160534aae0SPyun YongHyeon 	struct rl_softc		*sc;
39170534aae0SPyun YongHyeon 	struct rl_stats		*stats;
39180534aae0SPyun YongHyeon 	int			error, i, result;
39190534aae0SPyun YongHyeon 
39200534aae0SPyun YongHyeon 	result = -1;
39210534aae0SPyun YongHyeon 	error = sysctl_handle_int(oidp, &result, 0, req);
39220534aae0SPyun YongHyeon 	if (error || req->newptr == NULL)
39230534aae0SPyun YongHyeon 		return (error);
39240534aae0SPyun YongHyeon 
39250534aae0SPyun YongHyeon 	if (result == 1) {
39260534aae0SPyun YongHyeon 		sc = (struct rl_softc *)arg1;
39270534aae0SPyun YongHyeon 		RL_LOCK(sc);
392816a4824bSPyun YongHyeon 		if ((sc->rl_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
392916a4824bSPyun YongHyeon 			RL_UNLOCK(sc);
393016a4824bSPyun YongHyeon 			goto done;
393116a4824bSPyun YongHyeon 		}
39320534aae0SPyun YongHyeon 		bus_dmamap_sync(sc->rl_ldata.rl_stag,
39330534aae0SPyun YongHyeon 		    sc->rl_ldata.rl_smap, BUS_DMASYNC_PREREAD);
39340534aae0SPyun YongHyeon 		CSR_WRITE_4(sc, RL_DUMPSTATS_HI,
39350534aae0SPyun YongHyeon 		    RL_ADDR_HI(sc->rl_ldata.rl_stats_addr));
39360534aae0SPyun YongHyeon 		CSR_WRITE_4(sc, RL_DUMPSTATS_LO,
39370534aae0SPyun YongHyeon 		    RL_ADDR_LO(sc->rl_ldata.rl_stats_addr));
39380534aae0SPyun YongHyeon 		CSR_WRITE_4(sc, RL_DUMPSTATS_LO,
39390534aae0SPyun YongHyeon 		    RL_ADDR_LO(sc->rl_ldata.rl_stats_addr |
39400534aae0SPyun YongHyeon 		    RL_DUMPSTATS_START));
39410534aae0SPyun YongHyeon 		for (i = RL_TIMEOUT; i > 0; i--) {
39420534aae0SPyun YongHyeon 			if ((CSR_READ_4(sc, RL_DUMPSTATS_LO) &
39430534aae0SPyun YongHyeon 			    RL_DUMPSTATS_START) == 0)
39440534aae0SPyun YongHyeon 				break;
39450534aae0SPyun YongHyeon 			DELAY(1000);
39460534aae0SPyun YongHyeon 		}
39470534aae0SPyun YongHyeon 		bus_dmamap_sync(sc->rl_ldata.rl_stag,
39480534aae0SPyun YongHyeon 		    sc->rl_ldata.rl_smap, BUS_DMASYNC_POSTREAD);
39490534aae0SPyun YongHyeon 		RL_UNLOCK(sc);
39500534aae0SPyun YongHyeon 		if (i == 0) {
39510534aae0SPyun YongHyeon 			device_printf(sc->rl_dev,
39520534aae0SPyun YongHyeon 			    "DUMP statistics request timed out\n");
39530534aae0SPyun YongHyeon 			return (ETIMEDOUT);
39540534aae0SPyun YongHyeon 		}
395516a4824bSPyun YongHyeon done:
39560534aae0SPyun YongHyeon 		stats = sc->rl_ldata.rl_stats;
39570534aae0SPyun YongHyeon 		printf("%s statistics:\n", device_get_nameunit(sc->rl_dev));
39580534aae0SPyun YongHyeon 		printf("Tx frames : %ju\n",
39590534aae0SPyun YongHyeon 		    (uintmax_t)le64toh(stats->rl_tx_pkts));
39600534aae0SPyun YongHyeon 		printf("Rx frames : %ju\n",
39610534aae0SPyun YongHyeon 		    (uintmax_t)le64toh(stats->rl_rx_pkts));
39620534aae0SPyun YongHyeon 		printf("Tx errors : %ju\n",
39630534aae0SPyun YongHyeon 		    (uintmax_t)le64toh(stats->rl_tx_errs));
39640534aae0SPyun YongHyeon 		printf("Rx errors : %u\n",
39650534aae0SPyun YongHyeon 		    le32toh(stats->rl_rx_errs));
39660534aae0SPyun YongHyeon 		printf("Rx missed frames : %u\n",
39670534aae0SPyun YongHyeon 		    (uint32_t)le16toh(stats->rl_missed_pkts));
39680534aae0SPyun YongHyeon 		printf("Rx frame alignment errs : %u\n",
39690534aae0SPyun YongHyeon 		    (uint32_t)le16toh(stats->rl_rx_framealign_errs));
39700534aae0SPyun YongHyeon 		printf("Tx single collisions : %u\n",
39710534aae0SPyun YongHyeon 		    le32toh(stats->rl_tx_onecoll));
39720534aae0SPyun YongHyeon 		printf("Tx multiple collisions : %u\n",
39730534aae0SPyun YongHyeon 		    le32toh(stats->rl_tx_multicolls));
39740534aae0SPyun YongHyeon 		printf("Rx unicast frames : %ju\n",
39750534aae0SPyun YongHyeon 		    (uintmax_t)le64toh(stats->rl_rx_ucasts));
39760534aae0SPyun YongHyeon 		printf("Rx broadcast frames : %ju\n",
39770534aae0SPyun YongHyeon 		    (uintmax_t)le64toh(stats->rl_rx_bcasts));
39780534aae0SPyun YongHyeon 		printf("Rx multicast frames : %u\n",
39790534aae0SPyun YongHyeon 		    le32toh(stats->rl_rx_mcasts));
39800534aae0SPyun YongHyeon 		printf("Tx aborts : %u\n",
39810534aae0SPyun YongHyeon 		    (uint32_t)le16toh(stats->rl_tx_aborts));
39820534aae0SPyun YongHyeon 		printf("Tx underruns : %u\n",
39830534aae0SPyun YongHyeon 		    (uint32_t)le16toh(stats->rl_rx_underruns));
39840534aae0SPyun YongHyeon 	}
39850534aae0SPyun YongHyeon 
39860534aae0SPyun YongHyeon 	return (error);
39870534aae0SPyun YongHyeon }
3988502be0f7SPyun YongHyeon 
3989502be0f7SPyun YongHyeon static int
3990502be0f7SPyun YongHyeon sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3991502be0f7SPyun YongHyeon {
3992502be0f7SPyun YongHyeon 	int error, value;
3993502be0f7SPyun YongHyeon 
3994502be0f7SPyun YongHyeon 	if (arg1 == NULL)
3995502be0f7SPyun YongHyeon 		return (EINVAL);
3996502be0f7SPyun YongHyeon 	value = *(int *)arg1;
3997502be0f7SPyun YongHyeon 	error = sysctl_handle_int(oidp, &value, 0, req);
3998502be0f7SPyun YongHyeon 	if (error || req->newptr == NULL)
3999502be0f7SPyun YongHyeon 		return (error);
4000502be0f7SPyun YongHyeon 	if (value < low || value > high)
4001502be0f7SPyun YongHyeon 		return (EINVAL);
4002502be0f7SPyun YongHyeon 	*(int *)arg1 = value;
4003502be0f7SPyun YongHyeon 
4004502be0f7SPyun YongHyeon 	return (0);
4005502be0f7SPyun YongHyeon }
4006502be0f7SPyun YongHyeon 
4007502be0f7SPyun YongHyeon static int
4008502be0f7SPyun YongHyeon sysctl_hw_re_int_mod(SYSCTL_HANDLER_ARGS)
4009502be0f7SPyun YongHyeon {
4010502be0f7SPyun YongHyeon 
4011502be0f7SPyun YongHyeon 	return (sysctl_int_range(oidp, arg1, arg2, req, RL_TIMER_MIN,
4012502be0f7SPyun YongHyeon 	    RL_TIMER_MAX));
4013502be0f7SPyun YongHyeon }
4014