1098ca2bdSWarner Losh /*- 2a94100faSBill Paul * Copyright (c) 1997, 1998-2003 3a94100faSBill Paul * Bill Paul <wpaul@windriver.com>. All rights reserved. 4a94100faSBill Paul * 5a94100faSBill Paul * Redistribution and use in source and binary forms, with or without 6a94100faSBill Paul * modification, are permitted provided that the following conditions 7a94100faSBill Paul * are met: 8a94100faSBill Paul * 1. Redistributions of source code must retain the above copyright 9a94100faSBill Paul * notice, this list of conditions and the following disclaimer. 10a94100faSBill Paul * 2. Redistributions in binary form must reproduce the above copyright 11a94100faSBill Paul * notice, this list of conditions and the following disclaimer in the 12a94100faSBill Paul * documentation and/or other materials provided with the distribution. 13a94100faSBill Paul * 3. All advertising materials mentioning features or use of this software 14a94100faSBill Paul * must display the following acknowledgement: 15a94100faSBill Paul * This product includes software developed by Bill Paul. 16a94100faSBill Paul * 4. Neither the name of the author nor the names of any co-contributors 17a94100faSBill Paul * may be used to endorse or promote products derived from this software 18a94100faSBill Paul * without specific prior written permission. 19a94100faSBill Paul * 20a94100faSBill Paul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21a94100faSBill Paul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22a94100faSBill Paul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23a94100faSBill Paul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24a94100faSBill Paul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25a94100faSBill Paul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26a94100faSBill Paul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27a94100faSBill Paul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28a94100faSBill Paul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29a94100faSBill Paul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30a94100faSBill Paul * THE POSSIBILITY OF SUCH DAMAGE. 31a94100faSBill Paul */ 32a94100faSBill Paul 334dc52c32SDavid E. O'Brien #include <sys/cdefs.h> 344dc52c32SDavid E. O'Brien __FBSDID("$FreeBSD$"); 354dc52c32SDavid E. O'Brien 36a94100faSBill Paul /* 37ed510fb0SBill Paul * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38a94100faSBill Paul * 39a94100faSBill Paul * Written by Bill Paul <wpaul@windriver.com> 40a94100faSBill Paul * Senior Networking Software Engineer 41a94100faSBill Paul * Wind River Systems 42a94100faSBill Paul */ 43a94100faSBill Paul 44a94100faSBill Paul /* 45a94100faSBill Paul * This driver is designed to support RealTek's next generation of 46a94100faSBill Paul * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47ed510fb0SBill Paul * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48ed510fb0SBill Paul * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49a94100faSBill Paul * 50a94100faSBill Paul * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51a94100faSBill Paul * with the older 8139 family, however it also supports a special 52a94100faSBill Paul * C+ mode of operation that provides several new performance enhancing 53a94100faSBill Paul * features. These include: 54a94100faSBill Paul * 55a94100faSBill Paul * o Descriptor based DMA mechanism. Each descriptor represents 56a94100faSBill Paul * a single packet fragment. Data buffers may be aligned on 57a94100faSBill Paul * any byte boundary. 58a94100faSBill Paul * 59a94100faSBill Paul * o 64-bit DMA 60a94100faSBill Paul * 61a94100faSBill Paul * o TCP/IP checksum offload for both RX and TX 62a94100faSBill Paul * 63a94100faSBill Paul * o High and normal priority transmit DMA rings 64a94100faSBill Paul * 65a94100faSBill Paul * o VLAN tag insertion and extraction 66a94100faSBill Paul * 67a94100faSBill Paul * o TCP large send (segmentation offload) 68a94100faSBill Paul * 69a94100faSBill Paul * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70a94100faSBill Paul * programming API is fairly straightforward. The RX filtering, EEPROM 71a94100faSBill Paul * access and PHY access is the same as it is on the older 8139 series 72a94100faSBill Paul * chips. 73a94100faSBill Paul * 74a94100faSBill Paul * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75a94100faSBill Paul * same programming API and feature set as the 8139C+ with the following 76a94100faSBill Paul * differences and additions: 77a94100faSBill Paul * 78a94100faSBill Paul * o 1000Mbps mode 79a94100faSBill Paul * 80a94100faSBill Paul * o Jumbo frames 81a94100faSBill Paul * 82a94100faSBill Paul * o GMII and TBI ports/registers for interfacing with copper 83a94100faSBill Paul * or fiber PHYs 84a94100faSBill Paul * 85a94100faSBill Paul * o RX and TX DMA rings can have up to 1024 descriptors 86a94100faSBill Paul * (the 8139C+ allows a maximum of 64) 87a94100faSBill Paul * 88a94100faSBill Paul * o Slight differences in register layout from the 8139C+ 89a94100faSBill Paul * 90a94100faSBill Paul * The TX start and timer interrupt registers are at different locations 91a94100faSBill Paul * on the 8169 than they are on the 8139C+. Also, the status word in the 92a94100faSBill Paul * RX descriptor has a slightly different bit layout. The 8169 does not 93a94100faSBill Paul * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94a94100faSBill Paul * copper gigE PHY. 95a94100faSBill Paul * 96a94100faSBill Paul * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97a94100faSBill Paul * (the 'S' stands for 'single-chip'). These devices have the same 98a94100faSBill Paul * programming API as the older 8169, but also have some vendor-specific 99a94100faSBill Paul * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100a94100faSBill Paul * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101a94100faSBill Paul * 102a94100faSBill Paul * This driver takes advantage of the RX and TX checksum offload and 103a94100faSBill Paul * VLAN tag insertion/extraction features. It also implements TX 104a94100faSBill Paul * interrupt moderation using the timer interrupt registers, which 105a94100faSBill Paul * significantly reduces TX interrupt load. There is also support 106a94100faSBill Paul * for jumbo frames, however the 8169/8169S/8110S can not transmit 10722a11c96SJohn-Mark Gurney * jumbo frames larger than 7440, so the max MTU possible with this 10822a11c96SJohn-Mark Gurney * driver is 7422 bytes. 109a94100faSBill Paul */ 110a94100faSBill Paul 111f0796cd2SGleb Smirnoff #ifdef HAVE_KERNEL_OPTION_HEADERS 112f0796cd2SGleb Smirnoff #include "opt_device_polling.h" 113f0796cd2SGleb Smirnoff #endif 114f0796cd2SGleb Smirnoff 115a94100faSBill Paul #include <sys/param.h> 116a94100faSBill Paul #include <sys/endian.h> 117a94100faSBill Paul #include <sys/systm.h> 118a94100faSBill Paul #include <sys/sockio.h> 119a94100faSBill Paul #include <sys/mbuf.h> 120a94100faSBill Paul #include <sys/malloc.h> 121fe12f24bSPoul-Henning Kamp #include <sys/module.h> 122a94100faSBill Paul #include <sys/kernel.h> 123a94100faSBill Paul #include <sys/socket.h> 124ed510fb0SBill Paul #include <sys/lock.h> 125ed510fb0SBill Paul #include <sys/mutex.h> 126ed510fb0SBill Paul #include <sys/taskqueue.h> 127a94100faSBill Paul 128a94100faSBill Paul #include <net/if.h> 129a94100faSBill Paul #include <net/if_arp.h> 130a94100faSBill Paul #include <net/ethernet.h> 131a94100faSBill Paul #include <net/if_dl.h> 132a94100faSBill Paul #include <net/if_media.h> 133fc74a9f9SBrooks Davis #include <net/if_types.h> 134a94100faSBill Paul #include <net/if_vlan_var.h> 135a94100faSBill Paul 136a94100faSBill Paul #include <net/bpf.h> 137a94100faSBill Paul 138a94100faSBill Paul #include <machine/bus.h> 139a94100faSBill Paul #include <machine/resource.h> 140a94100faSBill Paul #include <sys/bus.h> 141a94100faSBill Paul #include <sys/rman.h> 142a94100faSBill Paul 143a94100faSBill Paul #include <dev/mii/mii.h> 144a94100faSBill Paul #include <dev/mii/miivar.h> 145a94100faSBill Paul 146a94100faSBill Paul #include <dev/pci/pcireg.h> 147a94100faSBill Paul #include <dev/pci/pcivar.h> 148a94100faSBill Paul 149d65abd66SPyun YongHyeon #include <pci/if_rlreg.h> 150d65abd66SPyun YongHyeon 151a94100faSBill Paul MODULE_DEPEND(re, pci, 1, 1, 1); 152a94100faSBill Paul MODULE_DEPEND(re, ether, 1, 1, 1); 153a94100faSBill Paul MODULE_DEPEND(re, miibus, 1, 1, 1); 154a94100faSBill Paul 155298bfdf3SWarner Losh /* "device miibus" required. See GENERIC if you get errors here. */ 156a94100faSBill Paul #include "miibus_if.h" 157a94100faSBill Paul 158a94100faSBill Paul /* 159a94100faSBill Paul * Default to using PIO access for this driver. 160a94100faSBill Paul */ 161a94100faSBill Paul #define RE_USEIOSPACE 162a94100faSBill Paul 1635774c5ffSPyun YongHyeon /* Tunables. */ 1645774c5ffSPyun YongHyeon static int msi_disable = 0; 1655774c5ffSPyun YongHyeon TUNABLE_INT("hw.re.msi_disable", &msi_disable); 1665774c5ffSPyun YongHyeon 167a94100faSBill Paul #define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 168a94100faSBill Paul 169a94100faSBill Paul /* 170a94100faSBill Paul * Various supported device vendors/types and their names. 171a94100faSBill Paul */ 172a94100faSBill Paul static struct rl_type re_devs[] = { 17332aa5f0eSAnton Berezin { DLINK_VENDORID, DLINK_DEVICEID_528T, RL_HWREV_8169S, 17432aa5f0eSAnton Berezin "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 1753b9982e5SRemko Lodder { DLINK_VENDORID, DLINK_DEVICEID_528T, RL_HWREV_8169_8110SB, 1763b9982e5SRemko Lodder "D-Link DGE-528(T) Rev.B1 Gigabit Ethernet Adapter" }, 177a94100faSBill Paul { RT_VENDORID, RT_DEVICEID_8139, RL_HWREV_8139CPLUS, 178a94100faSBill Paul "RealTek 8139C+ 10/100BaseTX" }, 179ed510fb0SBill Paul { RT_VENDORID, RT_DEVICEID_8101E, RL_HWREV_8101E, 180ed510fb0SBill Paul "RealTek 8101E PCIe 10/100baseTX" }, 181498bd0d3SBill Paul { RT_VENDORID, RT_DEVICEID_8168, RL_HWREV_8168_SPIN1, 182498bd0d3SBill Paul "RealTek 8168/8111B PCIe Gigabit Ethernet" }, 183498bd0d3SBill Paul { RT_VENDORID, RT_DEVICEID_8168, RL_HWREV_8168_SPIN2, 184498bd0d3SBill Paul "RealTek 8168/8111B PCIe Gigabit Ethernet" }, 1851acbb78aSPyun YongHyeon { RT_VENDORID, RT_DEVICEID_8168, RL_HWREV_8168_SPIN3, 1861acbb78aSPyun YongHyeon "RealTek 8168/8111B PCIe Gigabit Ethernet" }, 187a94100faSBill Paul { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169, 188a94100faSBill Paul "RealTek 8169 Gigabit Ethernet" }, 18969a6b7fbSBill Paul { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169S, 19069a6b7fbSBill Paul "RealTek 8169S Single-chip Gigabit Ethernet" }, 191ed510fb0SBill Paul { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169_8110SB, 192ed510fb0SBill Paul "RealTek 8169SB/8110SB Single-chip Gigabit Ethernet" }, 1932ee2c3b4SRemko Lodder { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169_8110SC, 1942ee2c3b4SRemko Lodder "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 195498bd0d3SBill Paul { RT_VENDORID, RT_DEVICEID_8169SC, RL_HWREV_8169_8110SC, 196ed510fb0SBill Paul "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 19769a6b7fbSBill Paul { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8110S, 19869a6b7fbSBill Paul "RealTek 8110S Single-chip Gigabit Ethernet" }, 199ea263191SMIHIRA Sanpei Yoshiro { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, RL_HWREV_8169S, 200ea263191SMIHIRA Sanpei Yoshiro "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 20126390635SJohn Baldwin { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, RL_HWREV_8169S, 20226390635SJohn Baldwin "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 2030fc4974fSBill Paul { USR_VENDORID, USR_DEVICEID_997902, RL_HWREV_8169S, 204dfdb409eSPyun YongHyeon "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 205a94100faSBill Paul }; 206a94100faSBill Paul 207a94100faSBill Paul static struct rl_hwrev re_hwrevs[] = { 208a94100faSBill Paul { RL_HWREV_8139, RL_8139, "" }, 209a94100faSBill Paul { RL_HWREV_8139A, RL_8139, "A" }, 210a94100faSBill Paul { RL_HWREV_8139AG, RL_8139, "A-G" }, 211a94100faSBill Paul { RL_HWREV_8139B, RL_8139, "B" }, 212a94100faSBill Paul { RL_HWREV_8130, RL_8139, "8130" }, 213a94100faSBill Paul { RL_HWREV_8139C, RL_8139, "C" }, 214a94100faSBill Paul { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" }, 215a94100faSBill Paul { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"}, 216498bd0d3SBill Paul { RL_HWREV_8168_SPIN1, RL_8169, "8168"}, 217a94100faSBill Paul { RL_HWREV_8169, RL_8169, "8169"}, 21869a6b7fbSBill Paul { RL_HWREV_8169S, RL_8169, "8169S"}, 21969a6b7fbSBill Paul { RL_HWREV_8110S, RL_8169, "8110S"}, 220ed510fb0SBill Paul { RL_HWREV_8169_8110SB, RL_8169, "8169SB"}, 221ed510fb0SBill Paul { RL_HWREV_8169_8110SC, RL_8169, "8169SC"}, 222a94100faSBill Paul { RL_HWREV_8100, RL_8139, "8100"}, 223a94100faSBill Paul { RL_HWREV_8101, RL_8139, "8101"}, 224ed510fb0SBill Paul { RL_HWREV_8100E, RL_8169, "8100E"}, 225ed510fb0SBill Paul { RL_HWREV_8101E, RL_8169, "8101E"}, 226498bd0d3SBill Paul { RL_HWREV_8168_SPIN2, RL_8169, "8168"}, 2271acbb78aSPyun YongHyeon { RL_HWREV_8168_SPIN3, RL_8169, "8168"}, 228a94100faSBill Paul { 0, 0, NULL } 229a94100faSBill Paul }; 230a94100faSBill Paul 231a94100faSBill Paul static int re_probe (device_t); 232a94100faSBill Paul static int re_attach (device_t); 233a94100faSBill Paul static int re_detach (device_t); 234a94100faSBill Paul 235d65abd66SPyun YongHyeon static int re_encap (struct rl_softc *, struct mbuf **); 236a94100faSBill Paul 237a94100faSBill Paul static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 238a94100faSBill Paul static int re_allocmem (device_t, struct rl_softc *); 239d65abd66SPyun YongHyeon static __inline void re_discard_rxbuf 240d65abd66SPyun YongHyeon (struct rl_softc *, int); 241d65abd66SPyun YongHyeon static int re_newbuf (struct rl_softc *, int); 242a94100faSBill Paul static int re_rx_list_init (struct rl_softc *); 243a94100faSBill Paul static int re_tx_list_init (struct rl_softc *); 24422a11c96SJohn-Mark Gurney #ifdef RE_FIXUP_RX 24522a11c96SJohn-Mark Gurney static __inline void re_fixup_rx 24622a11c96SJohn-Mark Gurney (struct mbuf *); 24722a11c96SJohn-Mark Gurney #endif 248ed510fb0SBill Paul static int re_rxeof (struct rl_softc *); 249a94100faSBill Paul static void re_txeof (struct rl_softc *); 25097b9d4baSJohn-Mark Gurney #ifdef DEVICE_POLLING 2510187838bSRuslan Ermilov static void re_poll (struct ifnet *, enum poll_cmd, int); 2520187838bSRuslan Ermilov static void re_poll_locked (struct ifnet *, enum poll_cmd, int); 25397b9d4baSJohn-Mark Gurney #endif 254ef544f63SPaolo Pisati static int re_intr (void *); 255a94100faSBill Paul static void re_tick (void *); 256ed510fb0SBill Paul static void re_tx_task (void *, int); 257ed510fb0SBill Paul static void re_int_task (void *, int); 258a94100faSBill Paul static void re_start (struct ifnet *); 259a94100faSBill Paul static int re_ioctl (struct ifnet *, u_long, caddr_t); 260a94100faSBill Paul static void re_init (void *); 26197b9d4baSJohn-Mark Gurney static void re_init_locked (struct rl_softc *); 262a94100faSBill Paul static void re_stop (struct rl_softc *); 2631d545c7aSMarius Strobl static void re_watchdog (struct rl_softc *); 264a94100faSBill Paul static int re_suspend (device_t); 265a94100faSBill Paul static int re_resume (device_t); 2666a087a87SPyun YongHyeon static int re_shutdown (device_t); 267a94100faSBill Paul static int re_ifmedia_upd (struct ifnet *); 268a94100faSBill Paul static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 269a94100faSBill Paul 270a94100faSBill Paul static void re_eeprom_putbyte (struct rl_softc *, int); 271a94100faSBill Paul static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 272ed510fb0SBill Paul static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 273a94100faSBill Paul static int re_gmii_readreg (device_t, int, int); 274a94100faSBill Paul static int re_gmii_writereg (device_t, int, int, int); 275a94100faSBill Paul 276a94100faSBill Paul static int re_miibus_readreg (device_t, int, int); 277a94100faSBill Paul static int re_miibus_writereg (device_t, int, int, int); 278a94100faSBill Paul static void re_miibus_statchg (device_t); 279a94100faSBill Paul 280a94100faSBill Paul static void re_setmulti (struct rl_softc *); 281a94100faSBill Paul static void re_reset (struct rl_softc *); 2827467bd53SPyun YongHyeon static void re_setwol (struct rl_softc *); 2837467bd53SPyun YongHyeon static void re_clrwol (struct rl_softc *); 284a94100faSBill Paul 285ed510fb0SBill Paul #ifdef RE_DIAG 286a94100faSBill Paul static int re_diag (struct rl_softc *); 287ed510fb0SBill Paul #endif 288a94100faSBill Paul 289a94100faSBill Paul #ifdef RE_USEIOSPACE 290a94100faSBill Paul #define RL_RES SYS_RES_IOPORT 291a94100faSBill Paul #define RL_RID RL_PCI_LOIO 292a94100faSBill Paul #else 293a94100faSBill Paul #define RL_RES SYS_RES_MEMORY 294a94100faSBill Paul #define RL_RID RL_PCI_LOMEM 295a94100faSBill Paul #endif 296a94100faSBill Paul 297a94100faSBill Paul static device_method_t re_methods[] = { 298a94100faSBill Paul /* Device interface */ 299a94100faSBill Paul DEVMETHOD(device_probe, re_probe), 300a94100faSBill Paul DEVMETHOD(device_attach, re_attach), 301a94100faSBill Paul DEVMETHOD(device_detach, re_detach), 302a94100faSBill Paul DEVMETHOD(device_suspend, re_suspend), 303a94100faSBill Paul DEVMETHOD(device_resume, re_resume), 304a94100faSBill Paul DEVMETHOD(device_shutdown, re_shutdown), 305a94100faSBill Paul 306a94100faSBill Paul /* bus interface */ 307a94100faSBill Paul DEVMETHOD(bus_print_child, bus_generic_print_child), 308a94100faSBill Paul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 309a94100faSBill Paul 310a94100faSBill Paul /* MII interface */ 311a94100faSBill Paul DEVMETHOD(miibus_readreg, re_miibus_readreg), 312a94100faSBill Paul DEVMETHOD(miibus_writereg, re_miibus_writereg), 313a94100faSBill Paul DEVMETHOD(miibus_statchg, re_miibus_statchg), 314a94100faSBill Paul 315a94100faSBill Paul { 0, 0 } 316a94100faSBill Paul }; 317a94100faSBill Paul 318a94100faSBill Paul static driver_t re_driver = { 319a94100faSBill Paul "re", 320a94100faSBill Paul re_methods, 321a94100faSBill Paul sizeof(struct rl_softc) 322a94100faSBill Paul }; 323a94100faSBill Paul 324a94100faSBill Paul static devclass_t re_devclass; 325a94100faSBill Paul 326a94100faSBill Paul DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 327347934faSWarner Losh DRIVER_MODULE(re, cardbus, re_driver, re_devclass, 0, 0); 328a94100faSBill Paul DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 329a94100faSBill Paul 330a94100faSBill Paul #define EE_SET(x) \ 331a94100faSBill Paul CSR_WRITE_1(sc, RL_EECMD, \ 332a94100faSBill Paul CSR_READ_1(sc, RL_EECMD) | x) 333a94100faSBill Paul 334a94100faSBill Paul #define EE_CLR(x) \ 335a94100faSBill Paul CSR_WRITE_1(sc, RL_EECMD, \ 336a94100faSBill Paul CSR_READ_1(sc, RL_EECMD) & ~x) 337a94100faSBill Paul 338a94100faSBill Paul /* 339a94100faSBill Paul * Send a read command and address to the EEPROM, check for ACK. 340a94100faSBill Paul */ 341a94100faSBill Paul static void 342a94100faSBill Paul re_eeprom_putbyte(sc, addr) 343a94100faSBill Paul struct rl_softc *sc; 344a94100faSBill Paul int addr; 345a94100faSBill Paul { 346a94100faSBill Paul register int d, i; 347a94100faSBill Paul 348ed510fb0SBill Paul d = addr | (RL_9346_READ << sc->rl_eewidth); 349a94100faSBill Paul 350a94100faSBill Paul /* 351a94100faSBill Paul * Feed in each bit and strobe the clock. 352a94100faSBill Paul */ 353ed510fb0SBill Paul 354ed510fb0SBill Paul for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 355a94100faSBill Paul if (d & i) { 356a94100faSBill Paul EE_SET(RL_EE_DATAIN); 357a94100faSBill Paul } else { 358a94100faSBill Paul EE_CLR(RL_EE_DATAIN); 359a94100faSBill Paul } 360a94100faSBill Paul DELAY(100); 361a94100faSBill Paul EE_SET(RL_EE_CLK); 362a94100faSBill Paul DELAY(150); 363a94100faSBill Paul EE_CLR(RL_EE_CLK); 364a94100faSBill Paul DELAY(100); 365a94100faSBill Paul } 366ed510fb0SBill Paul 367ed510fb0SBill Paul return; 368a94100faSBill Paul } 369a94100faSBill Paul 370a94100faSBill Paul /* 371a94100faSBill Paul * Read a word of data stored in the EEPROM at address 'addr.' 372a94100faSBill Paul */ 373a94100faSBill Paul static void 374a94100faSBill Paul re_eeprom_getword(sc, addr, dest) 375a94100faSBill Paul struct rl_softc *sc; 376a94100faSBill Paul int addr; 377a94100faSBill Paul u_int16_t *dest; 378a94100faSBill Paul { 379a94100faSBill Paul register int i; 380a94100faSBill Paul u_int16_t word = 0; 381a94100faSBill Paul 382a94100faSBill Paul /* 383a94100faSBill Paul * Send address of word we want to read. 384a94100faSBill Paul */ 385a94100faSBill Paul re_eeprom_putbyte(sc, addr); 386a94100faSBill Paul 387a94100faSBill Paul /* 388a94100faSBill Paul * Start reading bits from EEPROM. 389a94100faSBill Paul */ 390a94100faSBill Paul for (i = 0x8000; i; i >>= 1) { 391a94100faSBill Paul EE_SET(RL_EE_CLK); 392a94100faSBill Paul DELAY(100); 393a94100faSBill Paul if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 394a94100faSBill Paul word |= i; 395a94100faSBill Paul EE_CLR(RL_EE_CLK); 396a94100faSBill Paul DELAY(100); 397a94100faSBill Paul } 398a94100faSBill Paul 399a94100faSBill Paul *dest = word; 400ed510fb0SBill Paul 401ed510fb0SBill Paul return; 402a94100faSBill Paul } 403a94100faSBill Paul 404a94100faSBill Paul /* 405a94100faSBill Paul * Read a sequence of words from the EEPROM. 406a94100faSBill Paul */ 407a94100faSBill Paul static void 408ed510fb0SBill Paul re_read_eeprom(sc, dest, off, cnt) 409a94100faSBill Paul struct rl_softc *sc; 410a94100faSBill Paul caddr_t dest; 411a94100faSBill Paul int off; 412a94100faSBill Paul int cnt; 413a94100faSBill Paul { 414a94100faSBill Paul int i; 415a94100faSBill Paul u_int16_t word = 0, *ptr; 416a94100faSBill Paul 417ed510fb0SBill Paul CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 418ed510fb0SBill Paul 419ed510fb0SBill Paul DELAY(100); 420ed510fb0SBill Paul 421a94100faSBill Paul for (i = 0; i < cnt; i++) { 422ed510fb0SBill Paul CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 423a94100faSBill Paul re_eeprom_getword(sc, off + i, &word); 424ed510fb0SBill Paul CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 425a94100faSBill Paul ptr = (u_int16_t *)(dest + (i * 2)); 426be099007SPyun YongHyeon *ptr = word; 427a94100faSBill Paul } 428ed510fb0SBill Paul 429ed510fb0SBill Paul CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 430ed510fb0SBill Paul 431ed510fb0SBill Paul return; 432a94100faSBill Paul } 433a94100faSBill Paul 434a94100faSBill Paul static int 435a94100faSBill Paul re_gmii_readreg(dev, phy, reg) 436a94100faSBill Paul device_t dev; 437a94100faSBill Paul int phy, reg; 438a94100faSBill Paul { 439a94100faSBill Paul struct rl_softc *sc; 440a94100faSBill Paul u_int32_t rval; 441a94100faSBill Paul int i; 442a94100faSBill Paul 443a94100faSBill Paul if (phy != 1) 444a94100faSBill Paul return (0); 445a94100faSBill Paul 446a94100faSBill Paul sc = device_get_softc(dev); 447a94100faSBill Paul 4489bac70b8SBill Paul /* Let the rgephy driver read the GMEDIASTAT register */ 4499bac70b8SBill Paul 4509bac70b8SBill Paul if (reg == RL_GMEDIASTAT) { 4519bac70b8SBill Paul rval = CSR_READ_1(sc, RL_GMEDIASTAT); 4529bac70b8SBill Paul return (rval); 4539bac70b8SBill Paul } 4549bac70b8SBill Paul 455a94100faSBill Paul CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 456a94100faSBill Paul DELAY(1000); 457a94100faSBill Paul 458a94100faSBill Paul for (i = 0; i < RL_TIMEOUT; i++) { 459a94100faSBill Paul rval = CSR_READ_4(sc, RL_PHYAR); 460a94100faSBill Paul if (rval & RL_PHYAR_BUSY) 461a94100faSBill Paul break; 462a94100faSBill Paul DELAY(100); 463a94100faSBill Paul } 464a94100faSBill Paul 465a94100faSBill Paul if (i == RL_TIMEOUT) { 4666b9f5c94SGleb Smirnoff device_printf(sc->rl_dev, "PHY read failed\n"); 467a94100faSBill Paul return (0); 468a94100faSBill Paul } 469a94100faSBill Paul 470a94100faSBill Paul return (rval & RL_PHYAR_PHYDATA); 471a94100faSBill Paul } 472a94100faSBill Paul 473a94100faSBill Paul static int 474a94100faSBill Paul re_gmii_writereg(dev, phy, reg, data) 475a94100faSBill Paul device_t dev; 476a94100faSBill Paul int phy, reg, data; 477a94100faSBill Paul { 478a94100faSBill Paul struct rl_softc *sc; 479a94100faSBill Paul u_int32_t rval; 480a94100faSBill Paul int i; 481a94100faSBill Paul 482a94100faSBill Paul sc = device_get_softc(dev); 483a94100faSBill Paul 484a94100faSBill Paul CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 4859bac70b8SBill Paul (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 486a94100faSBill Paul DELAY(1000); 487a94100faSBill Paul 488a94100faSBill Paul for (i = 0; i < RL_TIMEOUT; i++) { 489a94100faSBill Paul rval = CSR_READ_4(sc, RL_PHYAR); 490a94100faSBill Paul if (!(rval & RL_PHYAR_BUSY)) 491a94100faSBill Paul break; 492a94100faSBill Paul DELAY(100); 493a94100faSBill Paul } 494a94100faSBill Paul 495a94100faSBill Paul if (i == RL_TIMEOUT) { 4966b9f5c94SGleb Smirnoff device_printf(sc->rl_dev, "PHY write failed\n"); 497a94100faSBill Paul return (0); 498a94100faSBill Paul } 499a94100faSBill Paul 500a94100faSBill Paul return (0); 501a94100faSBill Paul } 502a94100faSBill Paul 503a94100faSBill Paul static int 504a94100faSBill Paul re_miibus_readreg(dev, phy, reg) 505a94100faSBill Paul device_t dev; 506a94100faSBill Paul int phy, reg; 507a94100faSBill Paul { 508a94100faSBill Paul struct rl_softc *sc; 509a94100faSBill Paul u_int16_t rval = 0; 510a94100faSBill Paul u_int16_t re8139_reg = 0; 511a94100faSBill Paul 512a94100faSBill Paul sc = device_get_softc(dev); 513a94100faSBill Paul 514a94100faSBill Paul if (sc->rl_type == RL_8169) { 515a94100faSBill Paul rval = re_gmii_readreg(dev, phy, reg); 516a94100faSBill Paul return (rval); 517a94100faSBill Paul } 518a94100faSBill Paul 519a94100faSBill Paul /* Pretend the internal PHY is only at address 0 */ 520a94100faSBill Paul if (phy) { 521a94100faSBill Paul return (0); 522a94100faSBill Paul } 523a94100faSBill Paul switch (reg) { 524a94100faSBill Paul case MII_BMCR: 525a94100faSBill Paul re8139_reg = RL_BMCR; 526a94100faSBill Paul break; 527a94100faSBill Paul case MII_BMSR: 528a94100faSBill Paul re8139_reg = RL_BMSR; 529a94100faSBill Paul break; 530a94100faSBill Paul case MII_ANAR: 531a94100faSBill Paul re8139_reg = RL_ANAR; 532a94100faSBill Paul break; 533a94100faSBill Paul case MII_ANER: 534a94100faSBill Paul re8139_reg = RL_ANER; 535a94100faSBill Paul break; 536a94100faSBill Paul case MII_ANLPAR: 537a94100faSBill Paul re8139_reg = RL_LPAR; 538a94100faSBill Paul break; 539a94100faSBill Paul case MII_PHYIDR1: 540a94100faSBill Paul case MII_PHYIDR2: 541a94100faSBill Paul return (0); 542a94100faSBill Paul /* 543a94100faSBill Paul * Allow the rlphy driver to read the media status 544a94100faSBill Paul * register. If we have a link partner which does not 545a94100faSBill Paul * support NWAY, this is the register which will tell 546a94100faSBill Paul * us the results of parallel detection. 547a94100faSBill Paul */ 548a94100faSBill Paul case RL_MEDIASTAT: 549a94100faSBill Paul rval = CSR_READ_1(sc, RL_MEDIASTAT); 550a94100faSBill Paul return (rval); 551a94100faSBill Paul default: 5526b9f5c94SGleb Smirnoff device_printf(sc->rl_dev, "bad phy register\n"); 553a94100faSBill Paul return (0); 554a94100faSBill Paul } 555a94100faSBill Paul rval = CSR_READ_2(sc, re8139_reg); 556baa12772SPyun YongHyeon if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 557baa12772SPyun YongHyeon /* 8139C+ has different bit layout. */ 558baa12772SPyun YongHyeon rval &= ~(BMCR_LOOP | BMCR_ISO); 559baa12772SPyun YongHyeon } 560a94100faSBill Paul return (rval); 561a94100faSBill Paul } 562a94100faSBill Paul 563a94100faSBill Paul static int 564a94100faSBill Paul re_miibus_writereg(dev, phy, reg, data) 565a94100faSBill Paul device_t dev; 566a94100faSBill Paul int phy, reg, data; 567a94100faSBill Paul { 568a94100faSBill Paul struct rl_softc *sc; 569a94100faSBill Paul u_int16_t re8139_reg = 0; 570a94100faSBill Paul int rval = 0; 571a94100faSBill Paul 572a94100faSBill Paul sc = device_get_softc(dev); 573a94100faSBill Paul 574a94100faSBill Paul if (sc->rl_type == RL_8169) { 575a94100faSBill Paul rval = re_gmii_writereg(dev, phy, reg, data); 576a94100faSBill Paul return (rval); 577a94100faSBill Paul } 578a94100faSBill Paul 579a94100faSBill Paul /* Pretend the internal PHY is only at address 0 */ 58097b9d4baSJohn-Mark Gurney if (phy) 581a94100faSBill Paul return (0); 58297b9d4baSJohn-Mark Gurney 583a94100faSBill Paul switch (reg) { 584a94100faSBill Paul case MII_BMCR: 585a94100faSBill Paul re8139_reg = RL_BMCR; 586baa12772SPyun YongHyeon if (sc->rl_type == RL_8139CPLUS) { 587baa12772SPyun YongHyeon /* 8139C+ has different bit layout. */ 588baa12772SPyun YongHyeon data &= ~(BMCR_LOOP | BMCR_ISO); 589baa12772SPyun YongHyeon } 590a94100faSBill Paul break; 591a94100faSBill Paul case MII_BMSR: 592a94100faSBill Paul re8139_reg = RL_BMSR; 593a94100faSBill Paul break; 594a94100faSBill Paul case MII_ANAR: 595a94100faSBill Paul re8139_reg = RL_ANAR; 596a94100faSBill Paul break; 597a94100faSBill Paul case MII_ANER: 598a94100faSBill Paul re8139_reg = RL_ANER; 599a94100faSBill Paul break; 600a94100faSBill Paul case MII_ANLPAR: 601a94100faSBill Paul re8139_reg = RL_LPAR; 602a94100faSBill Paul break; 603a94100faSBill Paul case MII_PHYIDR1: 604a94100faSBill Paul case MII_PHYIDR2: 605a94100faSBill Paul return (0); 606a94100faSBill Paul break; 607a94100faSBill Paul default: 6086b9f5c94SGleb Smirnoff device_printf(sc->rl_dev, "bad phy register\n"); 609a94100faSBill Paul return (0); 610a94100faSBill Paul } 611a94100faSBill Paul CSR_WRITE_2(sc, re8139_reg, data); 612a94100faSBill Paul return (0); 613a94100faSBill Paul } 614a94100faSBill Paul 615a94100faSBill Paul static void 616a94100faSBill Paul re_miibus_statchg(dev) 617a94100faSBill Paul device_t dev; 618a94100faSBill Paul { 619a11e2f18SBruce M Simpson 620a94100faSBill Paul } 621a94100faSBill Paul 622a94100faSBill Paul /* 623a94100faSBill Paul * Program the 64-bit multicast hash filter. 624a94100faSBill Paul */ 625a94100faSBill Paul static void 626a94100faSBill Paul re_setmulti(sc) 627a94100faSBill Paul struct rl_softc *sc; 628a94100faSBill Paul { 629a94100faSBill Paul struct ifnet *ifp; 630a94100faSBill Paul int h = 0; 631a94100faSBill Paul u_int32_t hashes[2] = { 0, 0 }; 632a94100faSBill Paul struct ifmultiaddr *ifma; 633a94100faSBill Paul u_int32_t rxfilt; 634a94100faSBill Paul int mcnt = 0; 635bb7dfefbSBill Paul u_int32_t hwrev; 636a94100faSBill Paul 63797b9d4baSJohn-Mark Gurney RL_LOCK_ASSERT(sc); 63897b9d4baSJohn-Mark Gurney 639fc74a9f9SBrooks Davis ifp = sc->rl_ifp; 640a94100faSBill Paul 641a94100faSBill Paul 6427c103000SPyun YongHyeon rxfilt = CSR_READ_4(sc, RL_RXCFG); 6437c103000SPyun YongHyeon rxfilt &= ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_MULTI); 644a94100faSBill Paul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 6457c103000SPyun YongHyeon if (ifp->if_flags & IFF_PROMISC) 6467c103000SPyun YongHyeon rxfilt |= RL_RXCFG_RX_ALLPHYS; 647a0637caaSPyun YongHyeon /* 648a0637caaSPyun YongHyeon * Unlike other hardwares, we have to explicitly set 649a0637caaSPyun YongHyeon * RL_RXCFG_RX_MULTI to receive multicast frames in 650a0637caaSPyun YongHyeon * promiscuous mode. 651a0637caaSPyun YongHyeon */ 652a94100faSBill Paul rxfilt |= RL_RXCFG_RX_MULTI; 653a94100faSBill Paul CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 654a94100faSBill Paul CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF); 655a94100faSBill Paul CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF); 656a94100faSBill Paul return; 657a94100faSBill Paul } 658a94100faSBill Paul 659a94100faSBill Paul /* first, zot all the existing hash bits */ 660a94100faSBill Paul CSR_WRITE_4(sc, RL_MAR0, 0); 661a94100faSBill Paul CSR_WRITE_4(sc, RL_MAR4, 0); 662a94100faSBill Paul 663a94100faSBill Paul /* now program new ones */ 66413b203d0SRobert Watson IF_ADDR_LOCK(ifp); 665a94100faSBill Paul TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 666a94100faSBill Paul if (ifma->ifma_addr->sa_family != AF_LINK) 667a94100faSBill Paul continue; 6680e939c0cSChristian Weisgerber h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 6690e939c0cSChristian Weisgerber ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 670a94100faSBill Paul if (h < 32) 671a94100faSBill Paul hashes[0] |= (1 << h); 672a94100faSBill Paul else 673a94100faSBill Paul hashes[1] |= (1 << (h - 32)); 674a94100faSBill Paul mcnt++; 675a94100faSBill Paul } 67613b203d0SRobert Watson IF_ADDR_UNLOCK(ifp); 677a94100faSBill Paul 678a94100faSBill Paul if (mcnt) 679a94100faSBill Paul rxfilt |= RL_RXCFG_RX_MULTI; 680a94100faSBill Paul else 681a94100faSBill Paul rxfilt &= ~RL_RXCFG_RX_MULTI; 682a94100faSBill Paul 683a94100faSBill Paul CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 684bb7dfefbSBill Paul 685bb7dfefbSBill Paul /* 686bb7dfefbSBill Paul * For some unfathomable reason, RealTek decided to reverse 687bb7dfefbSBill Paul * the order of the multicast hash registers in the PCI Express 688bb7dfefbSBill Paul * parts. This means we have to write the hash pattern in reverse 689bb7dfefbSBill Paul * order for those devices. 690bb7dfefbSBill Paul */ 691bb7dfefbSBill Paul 692bb7dfefbSBill Paul hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 693bb7dfefbSBill Paul 6941acbb78aSPyun YongHyeon switch (hwrev) { 6951acbb78aSPyun YongHyeon case RL_HWREV_8100E: 6961acbb78aSPyun YongHyeon case RL_HWREV_8101E: 6971acbb78aSPyun YongHyeon case RL_HWREV_8168_SPIN1: 6981acbb78aSPyun YongHyeon case RL_HWREV_8168_SPIN2: 6991acbb78aSPyun YongHyeon case RL_HWREV_8168_SPIN3: 700bb7dfefbSBill Paul CSR_WRITE_4(sc, RL_MAR0, bswap32(hashes[1])); 701bb7dfefbSBill Paul CSR_WRITE_4(sc, RL_MAR4, bswap32(hashes[0])); 7021acbb78aSPyun YongHyeon break; 7031acbb78aSPyun YongHyeon default: 704a94100faSBill Paul CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 705a94100faSBill Paul CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 7061acbb78aSPyun YongHyeon break; 707a94100faSBill Paul } 708bb7dfefbSBill Paul } 709a94100faSBill Paul 710a94100faSBill Paul static void 711a94100faSBill Paul re_reset(sc) 712a94100faSBill Paul struct rl_softc *sc; 713a94100faSBill Paul { 714a94100faSBill Paul register int i; 715a94100faSBill Paul 71697b9d4baSJohn-Mark Gurney RL_LOCK_ASSERT(sc); 71797b9d4baSJohn-Mark Gurney 718a94100faSBill Paul CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 719a94100faSBill Paul 720a94100faSBill Paul for (i = 0; i < RL_TIMEOUT; i++) { 721a94100faSBill Paul DELAY(10); 722a94100faSBill Paul if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 723a94100faSBill Paul break; 724a94100faSBill Paul } 725a94100faSBill Paul if (i == RL_TIMEOUT) 7266b9f5c94SGleb Smirnoff device_printf(sc->rl_dev, "reset never completed!\n"); 727a94100faSBill Paul 728a94100faSBill Paul CSR_WRITE_1(sc, 0x82, 1); 729a94100faSBill Paul } 730a94100faSBill Paul 731ed510fb0SBill Paul #ifdef RE_DIAG 732ed510fb0SBill Paul 733a94100faSBill Paul /* 734a94100faSBill Paul * The following routine is designed to test for a defect on some 735a94100faSBill Paul * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 736a94100faSBill Paul * lines connected to the bus, however for a 32-bit only card, they 737a94100faSBill Paul * should be pulled high. The result of this defect is that the 738a94100faSBill Paul * NIC will not work right if you plug it into a 64-bit slot: DMA 739a94100faSBill Paul * operations will be done with 64-bit transfers, which will fail 740a94100faSBill Paul * because the 64-bit data lines aren't connected. 741a94100faSBill Paul * 742a94100faSBill Paul * There's no way to work around this (short of talking a soldering 743a94100faSBill Paul * iron to the board), however we can detect it. The method we use 744a94100faSBill Paul * here is to put the NIC into digital loopback mode, set the receiver 745a94100faSBill Paul * to promiscuous mode, and then try to send a frame. We then compare 746a94100faSBill Paul * the frame data we sent to what was received. If the data matches, 747a94100faSBill Paul * then the NIC is working correctly, otherwise we know the user has 748a94100faSBill Paul * a defective NIC which has been mistakenly plugged into a 64-bit PCI 749a94100faSBill Paul * slot. In the latter case, there's no way the NIC can work correctly, 750a94100faSBill Paul * so we print out a message on the console and abort the device attach. 751a94100faSBill Paul */ 752a94100faSBill Paul 753a94100faSBill Paul static int 754a94100faSBill Paul re_diag(sc) 755a94100faSBill Paul struct rl_softc *sc; 756a94100faSBill Paul { 757fc74a9f9SBrooks Davis struct ifnet *ifp = sc->rl_ifp; 758a94100faSBill Paul struct mbuf *m0; 759a94100faSBill Paul struct ether_header *eh; 760a94100faSBill Paul struct rl_desc *cur_rx; 761a94100faSBill Paul u_int16_t status; 762a94100faSBill Paul u_int32_t rxstat; 763ed510fb0SBill Paul int total_len, i, error = 0, phyaddr; 764a94100faSBill Paul u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 765a94100faSBill Paul u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 766a94100faSBill Paul 767a94100faSBill Paul /* Allocate a single mbuf */ 768a94100faSBill Paul MGETHDR(m0, M_DONTWAIT, MT_DATA); 769a94100faSBill Paul if (m0 == NULL) 770a94100faSBill Paul return (ENOBUFS); 771a94100faSBill Paul 77297b9d4baSJohn-Mark Gurney RL_LOCK(sc); 77397b9d4baSJohn-Mark Gurney 774a94100faSBill Paul /* 775a94100faSBill Paul * Initialize the NIC in test mode. This sets the chip up 776a94100faSBill Paul * so that it can send and receive frames, but performs the 777a94100faSBill Paul * following special functions: 778a94100faSBill Paul * - Puts receiver in promiscuous mode 779a94100faSBill Paul * - Enables digital loopback mode 780a94100faSBill Paul * - Leaves interrupts turned off 781a94100faSBill Paul */ 782a94100faSBill Paul 783a94100faSBill Paul ifp->if_flags |= IFF_PROMISC; 784a94100faSBill Paul sc->rl_testmode = 1; 785ed510fb0SBill Paul re_reset(sc); 78697b9d4baSJohn-Mark Gurney re_init_locked(sc); 787ed510fb0SBill Paul sc->rl_link = 1; 788ed510fb0SBill Paul if (sc->rl_type == RL_8169) 789ed510fb0SBill Paul phyaddr = 1; 790ed510fb0SBill Paul else 791ed510fb0SBill Paul phyaddr = 0; 792ed510fb0SBill Paul 793ed510fb0SBill Paul re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 794ed510fb0SBill Paul for (i = 0; i < RL_TIMEOUT; i++) { 795ed510fb0SBill Paul status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 796ed510fb0SBill Paul if (!(status & BMCR_RESET)) 797ed510fb0SBill Paul break; 798ed510fb0SBill Paul } 799ed510fb0SBill Paul 800ed510fb0SBill Paul re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 801ed510fb0SBill Paul CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 802ed510fb0SBill Paul 803804af9a1SBill Paul DELAY(100000); 804a94100faSBill Paul 805a94100faSBill Paul /* Put some data in the mbuf */ 806a94100faSBill Paul 807a94100faSBill Paul eh = mtod(m0, struct ether_header *); 808a94100faSBill Paul bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 809a94100faSBill Paul bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 810a94100faSBill Paul eh->ether_type = htons(ETHERTYPE_IP); 811a94100faSBill Paul m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 812a94100faSBill Paul 8137cae6651SBill Paul /* 8147cae6651SBill Paul * Queue the packet, start transmission. 8157cae6651SBill Paul * Note: IF_HANDOFF() ultimately calls re_start() for us. 8167cae6651SBill Paul */ 817a94100faSBill Paul 818abc8ff44SBill Paul CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 81997b9d4baSJohn-Mark Gurney RL_UNLOCK(sc); 82052732175SMax Laier /* XXX: re_diag must not be called when in ALTQ mode */ 8217cae6651SBill Paul IF_HANDOFF(&ifp->if_snd, m0, ifp); 82297b9d4baSJohn-Mark Gurney RL_LOCK(sc); 823a94100faSBill Paul m0 = NULL; 824a94100faSBill Paul 825a94100faSBill Paul /* Wait for it to propagate through the chip */ 826a94100faSBill Paul 827abc8ff44SBill Paul DELAY(100000); 828a94100faSBill Paul for (i = 0; i < RL_TIMEOUT; i++) { 829a94100faSBill Paul status = CSR_READ_2(sc, RL_ISR); 830ed510fb0SBill Paul CSR_WRITE_2(sc, RL_ISR, status); 831abc8ff44SBill Paul if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 832abc8ff44SBill Paul (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 833a94100faSBill Paul break; 834a94100faSBill Paul DELAY(10); 835a94100faSBill Paul } 836a94100faSBill Paul 837a94100faSBill Paul if (i == RL_TIMEOUT) { 8386b9f5c94SGleb Smirnoff device_printf(sc->rl_dev, 8396b9f5c94SGleb Smirnoff "diagnostic failed, failed to receive packet in" 8406b9f5c94SGleb Smirnoff " loopback mode\n"); 841a94100faSBill Paul error = EIO; 842a94100faSBill Paul goto done; 843a94100faSBill Paul } 844a94100faSBill Paul 845a94100faSBill Paul /* 846a94100faSBill Paul * The packet should have been dumped into the first 847a94100faSBill Paul * entry in the RX DMA ring. Grab it from there. 848a94100faSBill Paul */ 849a94100faSBill Paul 850a94100faSBill Paul bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 851a94100faSBill Paul sc->rl_ldata.rl_rx_list_map, 852a94100faSBill Paul BUS_DMASYNC_POSTREAD); 853d65abd66SPyun YongHyeon bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 854d65abd66SPyun YongHyeon sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 855d65abd66SPyun YongHyeon BUS_DMASYNC_POSTREAD); 856d65abd66SPyun YongHyeon bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 857d65abd66SPyun YongHyeon sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 858a94100faSBill Paul 859d65abd66SPyun YongHyeon m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 860d65abd66SPyun YongHyeon sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 861a94100faSBill Paul eh = mtod(m0, struct ether_header *); 862a94100faSBill Paul 863a94100faSBill Paul cur_rx = &sc->rl_ldata.rl_rx_list[0]; 864a94100faSBill Paul total_len = RL_RXBYTES(cur_rx); 865a94100faSBill Paul rxstat = le32toh(cur_rx->rl_cmdstat); 866a94100faSBill Paul 867a94100faSBill Paul if (total_len != ETHER_MIN_LEN) { 8686b9f5c94SGleb Smirnoff device_printf(sc->rl_dev, 8696b9f5c94SGleb Smirnoff "diagnostic failed, received short packet\n"); 870a94100faSBill Paul error = EIO; 871a94100faSBill Paul goto done; 872a94100faSBill Paul } 873a94100faSBill Paul 874a94100faSBill Paul /* Test that the received packet data matches what we sent. */ 875a94100faSBill Paul 876a94100faSBill Paul if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 877a94100faSBill Paul bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 878a94100faSBill Paul ntohs(eh->ether_type) != ETHERTYPE_IP) { 8796b9f5c94SGleb Smirnoff device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 8806b9f5c94SGleb Smirnoff device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 881a94100faSBill Paul dst, ":", src, ":", ETHERTYPE_IP); 8826b9f5c94SGleb Smirnoff device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 883a94100faSBill Paul eh->ether_dhost, ":", eh->ether_shost, ":", 884a94100faSBill Paul ntohs(eh->ether_type)); 8856b9f5c94SGleb Smirnoff device_printf(sc->rl_dev, "You may have a defective 32-bit " 8866b9f5c94SGleb Smirnoff "NIC plugged into a 64-bit PCI slot.\n"); 8876b9f5c94SGleb Smirnoff device_printf(sc->rl_dev, "Please re-install the NIC in a " 8886b9f5c94SGleb Smirnoff "32-bit slot for proper operation.\n"); 8896b9f5c94SGleb Smirnoff device_printf(sc->rl_dev, "Read the re(4) man page for more " 8906b9f5c94SGleb Smirnoff "details.\n"); 891a94100faSBill Paul error = EIO; 892a94100faSBill Paul } 893a94100faSBill Paul 894a94100faSBill Paul done: 895a94100faSBill Paul /* Turn interface off, release resources */ 896a94100faSBill Paul 897a94100faSBill Paul sc->rl_testmode = 0; 898ed510fb0SBill Paul sc->rl_link = 0; 899a94100faSBill Paul ifp->if_flags &= ~IFF_PROMISC; 900a94100faSBill Paul re_stop(sc); 901a94100faSBill Paul if (m0 != NULL) 902a94100faSBill Paul m_freem(m0); 903a94100faSBill Paul 90497b9d4baSJohn-Mark Gurney RL_UNLOCK(sc); 90597b9d4baSJohn-Mark Gurney 906a94100faSBill Paul return (error); 907a94100faSBill Paul } 908a94100faSBill Paul 909ed510fb0SBill Paul #endif 910ed510fb0SBill Paul 911a94100faSBill Paul /* 912a94100faSBill Paul * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 913a94100faSBill Paul * IDs against our list and return a device name if we find a match. 914a94100faSBill Paul */ 915a94100faSBill Paul static int 916a94100faSBill Paul re_probe(dev) 917a94100faSBill Paul device_t dev; 918a94100faSBill Paul { 919a94100faSBill Paul struct rl_type *t; 920dfdb409eSPyun YongHyeon uint16_t devid, vendor; 921dfdb409eSPyun YongHyeon uint16_t revid, sdevid; 922dfdb409eSPyun YongHyeon int i; 923a94100faSBill Paul 924dfdb409eSPyun YongHyeon vendor = pci_get_vendor(dev); 925dfdb409eSPyun YongHyeon devid = pci_get_device(dev); 926dfdb409eSPyun YongHyeon revid = pci_get_revid(dev); 927dfdb409eSPyun YongHyeon sdevid = pci_get_subdevice(dev); 928a94100faSBill Paul 929dfdb409eSPyun YongHyeon if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 930dfdb409eSPyun YongHyeon if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 93126390635SJohn Baldwin /* 93226390635SJohn Baldwin * Only attach to rev. 3 of the Linksys EG1032 adapter. 933dfdb409eSPyun YongHyeon * Rev. 2 is supported by sk(4). 93426390635SJohn Baldwin */ 935a94100faSBill Paul return (ENXIO); 936a94100faSBill Paul } 937dfdb409eSPyun YongHyeon } 938dfdb409eSPyun YongHyeon 939dfdb409eSPyun YongHyeon if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 940dfdb409eSPyun YongHyeon if (revid != 0x20) { 941dfdb409eSPyun YongHyeon /* 8139, let rl(4) take care of this device. */ 942dfdb409eSPyun YongHyeon return (ENXIO); 943dfdb409eSPyun YongHyeon } 944dfdb409eSPyun YongHyeon } 945dfdb409eSPyun YongHyeon 946dfdb409eSPyun YongHyeon t = re_devs; 947dfdb409eSPyun YongHyeon for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) { 948dfdb409eSPyun YongHyeon if (vendor == t->rl_vid && devid == t->rl_did) { 949a94100faSBill Paul device_set_desc(dev, t->rl_name); 950d2b677bbSWarner Losh return (BUS_PROBE_DEFAULT); 951a94100faSBill Paul } 952a94100faSBill Paul } 953a94100faSBill Paul 954a94100faSBill Paul return (ENXIO); 955a94100faSBill Paul } 956a94100faSBill Paul 957a94100faSBill Paul /* 958a94100faSBill Paul * Map a single buffer address. 959a94100faSBill Paul */ 960a94100faSBill Paul 961a94100faSBill Paul static void 962a94100faSBill Paul re_dma_map_addr(arg, segs, nseg, error) 963a94100faSBill Paul void *arg; 964a94100faSBill Paul bus_dma_segment_t *segs; 965a94100faSBill Paul int nseg; 966a94100faSBill Paul int error; 967a94100faSBill Paul { 9688fd99e38SPyun YongHyeon bus_addr_t *addr; 969a94100faSBill Paul 970a94100faSBill Paul if (error) 971a94100faSBill Paul return; 972a94100faSBill Paul 973a94100faSBill Paul KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 974a94100faSBill Paul addr = arg; 975a94100faSBill Paul *addr = segs->ds_addr; 976a94100faSBill Paul } 977a94100faSBill Paul 978a94100faSBill Paul static int 979a94100faSBill Paul re_allocmem(dev, sc) 980a94100faSBill Paul device_t dev; 981a94100faSBill Paul struct rl_softc *sc; 982a94100faSBill Paul { 983d65abd66SPyun YongHyeon bus_size_t rx_list_size, tx_list_size; 984a94100faSBill Paul int error; 985a94100faSBill Paul int i; 986a94100faSBill Paul 987d65abd66SPyun YongHyeon rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 988d65abd66SPyun YongHyeon tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 989d65abd66SPyun YongHyeon 990d65abd66SPyun YongHyeon /* 991d65abd66SPyun YongHyeon * Allocate the parent bus DMA tag appropriate for PCI. 992d65abd66SPyun YongHyeon */ 993d65abd66SPyun YongHyeon error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 994d65abd66SPyun YongHyeon BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 995d65abd66SPyun YongHyeon BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 996d65abd66SPyun YongHyeon NULL, NULL, &sc->rl_parent_tag); 997d65abd66SPyun YongHyeon if (error) { 998d65abd66SPyun YongHyeon device_printf(dev, "could not allocate parent DMA tag\n"); 999d65abd66SPyun YongHyeon return (error); 1000d65abd66SPyun YongHyeon } 1001d65abd66SPyun YongHyeon 1002d65abd66SPyun YongHyeon /* 1003d65abd66SPyun YongHyeon * Allocate map for TX mbufs. 1004d65abd66SPyun YongHyeon */ 1005d65abd66SPyun YongHyeon error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 1006d65abd66SPyun YongHyeon BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1007d65abd66SPyun YongHyeon NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 1008d65abd66SPyun YongHyeon NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 1009d65abd66SPyun YongHyeon if (error) { 1010d65abd66SPyun YongHyeon device_printf(dev, "could not allocate TX DMA tag\n"); 1011d65abd66SPyun YongHyeon return (error); 1012d65abd66SPyun YongHyeon } 1013d65abd66SPyun YongHyeon 1014a94100faSBill Paul /* 1015a94100faSBill Paul * Allocate map for RX mbufs. 1016a94100faSBill Paul */ 1017d65abd66SPyun YongHyeon 1018d65abd66SPyun YongHyeon error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 1019d65abd66SPyun YongHyeon BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1020d65abd66SPyun YongHyeon MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 1021a94100faSBill Paul if (error) { 1022d65abd66SPyun YongHyeon device_printf(dev, "could not allocate RX DMA tag\n"); 1023d65abd66SPyun YongHyeon return (error); 1024a94100faSBill Paul } 1025a94100faSBill Paul 1026a94100faSBill Paul /* 1027a94100faSBill Paul * Allocate map for TX descriptor list. 1028a94100faSBill Paul */ 1029a94100faSBill Paul error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1030a94100faSBill Paul 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1031d65abd66SPyun YongHyeon NULL, tx_list_size, 1, tx_list_size, 0, 1032a94100faSBill Paul NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1033a94100faSBill Paul if (error) { 1034d65abd66SPyun YongHyeon device_printf(dev, "could not allocate TX DMA ring tag\n"); 1035d65abd66SPyun YongHyeon return (error); 1036a94100faSBill Paul } 1037a94100faSBill Paul 1038a94100faSBill Paul /* Allocate DMA'able memory for the TX ring */ 1039a94100faSBill Paul 1040a94100faSBill Paul error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1041d65abd66SPyun YongHyeon (void **)&sc->rl_ldata.rl_tx_list, 1042d65abd66SPyun YongHyeon BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1043a94100faSBill Paul &sc->rl_ldata.rl_tx_list_map); 1044d65abd66SPyun YongHyeon if (error) { 1045d65abd66SPyun YongHyeon device_printf(dev, "could not allocate TX DMA ring\n"); 1046d65abd66SPyun YongHyeon return (error); 1047d65abd66SPyun YongHyeon } 1048a94100faSBill Paul 1049a94100faSBill Paul /* Load the map for the TX ring. */ 1050a94100faSBill Paul 1051d65abd66SPyun YongHyeon sc->rl_ldata.rl_tx_list_addr = 0; 1052a94100faSBill Paul error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1053a94100faSBill Paul sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1054d65abd66SPyun YongHyeon tx_list_size, re_dma_map_addr, 1055a94100faSBill Paul &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1056d65abd66SPyun YongHyeon if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 1057d65abd66SPyun YongHyeon device_printf(dev, "could not load TX DMA ring\n"); 1058d65abd66SPyun YongHyeon return (ENOMEM); 1059d65abd66SPyun YongHyeon } 1060a94100faSBill Paul 1061a94100faSBill Paul /* Create DMA maps for TX buffers */ 1062a94100faSBill Paul 1063d65abd66SPyun YongHyeon for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1064d65abd66SPyun YongHyeon error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1065d65abd66SPyun YongHyeon &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1066a94100faSBill Paul if (error) { 1067d65abd66SPyun YongHyeon device_printf(dev, "could not create DMA map for TX\n"); 1068d65abd66SPyun YongHyeon return (error); 1069a94100faSBill Paul } 1070a94100faSBill Paul } 1071a94100faSBill Paul 1072a94100faSBill Paul /* 1073a94100faSBill Paul * Allocate map for RX descriptor list. 1074a94100faSBill Paul */ 1075a94100faSBill Paul error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1076a94100faSBill Paul 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1077d65abd66SPyun YongHyeon NULL, rx_list_size, 1, rx_list_size, 0, 1078a94100faSBill Paul NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1079a94100faSBill Paul if (error) { 1080d65abd66SPyun YongHyeon device_printf(dev, "could not create RX DMA ring tag\n"); 1081d65abd66SPyun YongHyeon return (error); 1082a94100faSBill Paul } 1083a94100faSBill Paul 1084a94100faSBill Paul /* Allocate DMA'able memory for the RX ring */ 1085a94100faSBill Paul 1086a94100faSBill Paul error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1087d65abd66SPyun YongHyeon (void **)&sc->rl_ldata.rl_rx_list, 1088d65abd66SPyun YongHyeon BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1089a94100faSBill Paul &sc->rl_ldata.rl_rx_list_map); 1090d65abd66SPyun YongHyeon if (error) { 1091d65abd66SPyun YongHyeon device_printf(dev, "could not allocate RX DMA ring\n"); 1092d65abd66SPyun YongHyeon return (error); 1093d65abd66SPyun YongHyeon } 1094a94100faSBill Paul 1095a94100faSBill Paul /* Load the map for the RX ring. */ 1096a94100faSBill Paul 1097d65abd66SPyun YongHyeon sc->rl_ldata.rl_rx_list_addr = 0; 1098a94100faSBill Paul error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1099a94100faSBill Paul sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1100d65abd66SPyun YongHyeon rx_list_size, re_dma_map_addr, 1101a94100faSBill Paul &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1102d65abd66SPyun YongHyeon if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1103d65abd66SPyun YongHyeon device_printf(dev, "could not load RX DMA ring\n"); 1104d65abd66SPyun YongHyeon return (ENOMEM); 1105d65abd66SPyun YongHyeon } 1106a94100faSBill Paul 1107a94100faSBill Paul /* Create DMA maps for RX buffers */ 1108a94100faSBill Paul 1109d65abd66SPyun YongHyeon error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1110d65abd66SPyun YongHyeon &sc->rl_ldata.rl_rx_sparemap); 1111a94100faSBill Paul if (error) { 1112d65abd66SPyun YongHyeon device_printf(dev, "could not create spare DMA map for RX\n"); 1113d65abd66SPyun YongHyeon return (error); 1114d65abd66SPyun YongHyeon } 1115d65abd66SPyun YongHyeon for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1116d65abd66SPyun YongHyeon error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1117d65abd66SPyun YongHyeon &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1118d65abd66SPyun YongHyeon if (error) { 1119d65abd66SPyun YongHyeon device_printf(dev, "could not create DMA map for RX\n"); 1120d65abd66SPyun YongHyeon return (error); 1121a94100faSBill Paul } 1122a94100faSBill Paul } 1123a94100faSBill Paul 1124a94100faSBill Paul return (0); 1125a94100faSBill Paul } 1126a94100faSBill Paul 1127a94100faSBill Paul /* 1128a94100faSBill Paul * Attach the interface. Allocate softc structures, do ifmedia 1129a94100faSBill Paul * setup and ethernet/BPF attach. 1130a94100faSBill Paul */ 1131a94100faSBill Paul static int 1132a94100faSBill Paul re_attach(dev) 1133a94100faSBill Paul device_t dev; 1134a94100faSBill Paul { 1135a94100faSBill Paul u_char eaddr[ETHER_ADDR_LEN]; 1136be099007SPyun YongHyeon u_int16_t as[ETHER_ADDR_LEN / 2]; 1137a94100faSBill Paul struct rl_softc *sc; 1138a94100faSBill Paul struct ifnet *ifp; 1139a94100faSBill Paul struct rl_hwrev *hw_rev; 1140a94100faSBill Paul int hwrev; 1141a94100faSBill Paul u_int16_t re_did = 0; 1142d1754a9bSJohn Baldwin int error = 0, rid, i; 11435774c5ffSPyun YongHyeon int msic, reg; 1144a94100faSBill Paul 1145a94100faSBill Paul sc = device_get_softc(dev); 1146ed510fb0SBill Paul sc->rl_dev = dev; 1147a94100faSBill Paul 1148a94100faSBill Paul mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 114997b9d4baSJohn-Mark Gurney MTX_DEF); 1150d1754a9bSJohn Baldwin callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1151d1754a9bSJohn Baldwin 1152a94100faSBill Paul /* 1153a94100faSBill Paul * Map control/status registers. 1154a94100faSBill Paul */ 1155a94100faSBill Paul pci_enable_busmaster(dev); 1156a94100faSBill Paul 1157a94100faSBill Paul rid = RL_RID; 11585f96beb9SNate Lawson sc->rl_res = bus_alloc_resource_any(dev, RL_RES, &rid, 11595f96beb9SNate Lawson RF_ACTIVE); 1160a94100faSBill Paul 1161a94100faSBill Paul if (sc->rl_res == NULL) { 1162d1754a9bSJohn Baldwin device_printf(dev, "couldn't map ports/memory\n"); 1163a94100faSBill Paul error = ENXIO; 1164a94100faSBill Paul goto fail; 1165a94100faSBill Paul } 1166a94100faSBill Paul 1167a94100faSBill Paul sc->rl_btag = rman_get_bustag(sc->rl_res); 1168a94100faSBill Paul sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1169a94100faSBill Paul 11705774c5ffSPyun YongHyeon msic = 0; 11715774c5ffSPyun YongHyeon if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 11725774c5ffSPyun YongHyeon msic = pci_msi_count(dev); 11735774c5ffSPyun YongHyeon if (bootverbose) 11745774c5ffSPyun YongHyeon device_printf(dev, "MSI count : %d\n", msic); 11755774c5ffSPyun YongHyeon } 11765774c5ffSPyun YongHyeon if (msic == RL_MSI_MESSAGES && msi_disable == 0) { 11775774c5ffSPyun YongHyeon if (pci_alloc_msi(dev, &msic) == 0) { 11785774c5ffSPyun YongHyeon if (msic == RL_MSI_MESSAGES) { 11795774c5ffSPyun YongHyeon device_printf(dev, "Using %d MSI messages\n", 11805774c5ffSPyun YongHyeon msic); 11815774c5ffSPyun YongHyeon sc->rl_msi = 1; 11825774c5ffSPyun YongHyeon } else 11835774c5ffSPyun YongHyeon pci_release_msi(dev); 11845774c5ffSPyun YongHyeon } 11855774c5ffSPyun YongHyeon } 1186a94100faSBill Paul 11875774c5ffSPyun YongHyeon /* Allocate interrupt */ 11885774c5ffSPyun YongHyeon if (sc->rl_msi == 0) { 11895774c5ffSPyun YongHyeon rid = 0; 11905774c5ffSPyun YongHyeon sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 11915774c5ffSPyun YongHyeon RF_SHAREABLE | RF_ACTIVE); 11925774c5ffSPyun YongHyeon if (sc->rl_irq[0] == NULL) { 11935774c5ffSPyun YongHyeon device_printf(dev, "couldn't allocate IRQ resources\n"); 1194a94100faSBill Paul error = ENXIO; 1195a94100faSBill Paul goto fail; 1196a94100faSBill Paul } 11975774c5ffSPyun YongHyeon } else { 11985774c5ffSPyun YongHyeon for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 11995774c5ffSPyun YongHyeon sc->rl_irq[i] = bus_alloc_resource_any(dev, 12005774c5ffSPyun YongHyeon SYS_RES_IRQ, &rid, RF_ACTIVE); 12015774c5ffSPyun YongHyeon if (sc->rl_irq[i] == NULL) { 12025774c5ffSPyun YongHyeon device_printf(dev, 12035774c5ffSPyun YongHyeon "couldn't llocate IRQ resources for " 12045774c5ffSPyun YongHyeon "message %d\n", rid); 12055774c5ffSPyun YongHyeon error = ENXIO; 12065774c5ffSPyun YongHyeon goto fail; 12075774c5ffSPyun YongHyeon } 12085774c5ffSPyun YongHyeon } 12095774c5ffSPyun YongHyeon } 1210a94100faSBill Paul 1211a94100faSBill Paul /* Reset the adapter. */ 121297b9d4baSJohn-Mark Gurney RL_LOCK(sc); 1213a94100faSBill Paul re_reset(sc); 121497b9d4baSJohn-Mark Gurney RL_UNLOCK(sc); 1215abc8ff44SBill Paul 1216abc8ff44SBill Paul hw_rev = re_hwrevs; 1217abc8ff44SBill Paul hwrev = CSR_READ_4(sc, RL_TXCFG) & RL_TXCFG_HWREV; 1218abc8ff44SBill Paul while (hw_rev->rl_desc != NULL) { 1219abc8ff44SBill Paul if (hw_rev->rl_rev == hwrev) { 1220abc8ff44SBill Paul sc->rl_type = hw_rev->rl_type; 1221abc8ff44SBill Paul break; 1222abc8ff44SBill Paul } 1223abc8ff44SBill Paul hw_rev++; 1224abc8ff44SBill Paul } 1225d65abd66SPyun YongHyeon if (hw_rev->rl_desc == NULL) { 1226d65abd66SPyun YongHyeon device_printf(dev, "Unknown H/W revision: %08x\n", hwrev); 1227d65abd66SPyun YongHyeon error = ENXIO; 1228d65abd66SPyun YongHyeon goto fail; 1229d65abd66SPyun YongHyeon } 1230abc8ff44SBill Paul 1231141f92e7SPyun YongHyeon sc->rl_eewidth = RL_9356_ADDR_LEN; 1232ed510fb0SBill Paul re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1233a94100faSBill Paul if (re_did != 0x8129) 1234141f92e7SPyun YongHyeon sc->rl_eewidth = RL_9346_ADDR_LEN; 1235a94100faSBill Paul 1236a94100faSBill Paul /* 1237a94100faSBill Paul * Get station address from the EEPROM. 1238a94100faSBill Paul */ 1239ed510fb0SBill Paul re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1240be099007SPyun YongHyeon for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1241be099007SPyun YongHyeon as[i] = le16toh(as[i]); 1242be099007SPyun YongHyeon bcopy(as, eaddr, sizeof(eaddr)); 1243ed510fb0SBill Paul 1244ed510fb0SBill Paul if (sc->rl_type == RL_8169) { 1245d65abd66SPyun YongHyeon /* Set RX length mask and number of descriptors. */ 1246ed510fb0SBill Paul sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1247ed510fb0SBill Paul sc->rl_txstart = RL_GTXSTART; 1248d65abd66SPyun YongHyeon sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1249d65abd66SPyun YongHyeon sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1250ed510fb0SBill Paul } else { 1251d65abd66SPyun YongHyeon /* Set RX length mask and number of descriptors. */ 1252ed510fb0SBill Paul sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1253ed510fb0SBill Paul sc->rl_txstart = RL_TXSTART; 1254d65abd66SPyun YongHyeon sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1255d65abd66SPyun YongHyeon sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1256abc8ff44SBill Paul } 1257dfdb409eSPyun YongHyeon if (hw_rev->rl_desc == NULL) { 1258dfdb409eSPyun YongHyeon device_printf(dev, "Unsupported revision : 0x%08x\n", hwrev); 1259dfdb409eSPyun YongHyeon error = ENXIO; 1260dfdb409eSPyun YongHyeon goto fail; 1261dfdb409eSPyun YongHyeon } 12629bac70b8SBill Paul 1263a94100faSBill Paul error = re_allocmem(dev, sc); 1264a94100faSBill Paul if (error) 1265a94100faSBill Paul goto fail; 1266a94100faSBill Paul 1267cd036ec1SBrooks Davis ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1268cd036ec1SBrooks Davis if (ifp == NULL) { 1269d1754a9bSJohn Baldwin device_printf(dev, "can not if_alloc()\n"); 1270cd036ec1SBrooks Davis error = ENOSPC; 1271cd036ec1SBrooks Davis goto fail; 1272cd036ec1SBrooks Davis } 1273cd036ec1SBrooks Davis 1274a94100faSBill Paul /* Do MII setup */ 1275a94100faSBill Paul if (mii_phy_probe(dev, &sc->rl_miibus, 1276a94100faSBill Paul re_ifmedia_upd, re_ifmedia_sts)) { 1277d1754a9bSJohn Baldwin device_printf(dev, "MII without any phy!\n"); 1278a94100faSBill Paul error = ENXIO; 1279a94100faSBill Paul goto fail; 1280a94100faSBill Paul } 1281a94100faSBill Paul 1282c4aca09aSPyun YongHyeon /* Take PHY out of power down mode. */ 1283c4aca09aSPyun YongHyeon if (sc->rl_type == RL_8169) { 1284c4aca09aSPyun YongHyeon uint32_t rev; 1285c4aca09aSPyun YongHyeon 1286c4aca09aSPyun YongHyeon rev = CSR_READ_4(sc, RL_TXCFG); 1287c4aca09aSPyun YongHyeon /* HWVERID 0, 1 and 2 : bit26-30, bit23 */ 1288c4aca09aSPyun YongHyeon rev &= 0x7c800000; 1289c4aca09aSPyun YongHyeon if (rev != 0) { 1290c4aca09aSPyun YongHyeon /* RTL8169S single chip */ 1291c4aca09aSPyun YongHyeon switch (rev) { 1292c4aca09aSPyun YongHyeon case RL_HWREV_8169_8110SB: 1293c4aca09aSPyun YongHyeon case RL_HWREV_8169_8110SC: 1294c4aca09aSPyun YongHyeon case RL_HWREV_8168_SPIN2: 12951acbb78aSPyun YongHyeon case RL_HWREV_8168_SPIN3: 1296c4aca09aSPyun YongHyeon re_gmii_writereg(dev, 1, 0x1f, 0); 1297c4aca09aSPyun YongHyeon re_gmii_writereg(dev, 1, 0x0e, 0); 1298c4aca09aSPyun YongHyeon break; 1299c4aca09aSPyun YongHyeon default: 1300c4aca09aSPyun YongHyeon break; 1301c4aca09aSPyun YongHyeon } 1302c4aca09aSPyun YongHyeon } 1303c4aca09aSPyun YongHyeon } 1304c4aca09aSPyun YongHyeon 1305a94100faSBill Paul ifp->if_softc = sc; 13069bf40edeSBrooks Davis if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1307a94100faSBill Paul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1308a94100faSBill Paul ifp->if_ioctl = re_ioctl; 1309a94100faSBill Paul ifp->if_start = re_start; 1310d65abd66SPyun YongHyeon ifp->if_hwassist = RE_CSUM_FEATURES | CSUM_TSO; 1311d65abd66SPyun YongHyeon ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 1312498bd0d3SBill Paul ifp->if_capenable = ifp->if_capabilities; 1313a94100faSBill Paul ifp->if_init = re_init; 131452732175SMax Laier IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 131552732175SMax Laier ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 131652732175SMax Laier IFQ_SET_READY(&ifp->if_snd); 1317a94100faSBill Paul 1318ed510fb0SBill Paul TASK_INIT(&sc->rl_txtask, 1, re_tx_task, ifp); 1319ed510fb0SBill Paul TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1320ed510fb0SBill Paul 1321a94100faSBill Paul /* 1322a94100faSBill Paul * Call MI attach routine. 1323a94100faSBill Paul */ 1324a94100faSBill Paul ether_ifattach(ifp, eaddr); 1325a94100faSBill Paul 1326960fd5b3SPyun YongHyeon /* VLAN capability setup */ 1327960fd5b3SPyun YongHyeon ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1328960fd5b3SPyun YongHyeon if (ifp->if_capabilities & IFCAP_HWCSUM) 1329960fd5b3SPyun YongHyeon ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 13307467bd53SPyun YongHyeon /* Enable WOL if PM is supported. */ 13317467bd53SPyun YongHyeon if (pci_find_extcap(sc->rl_dev, PCIY_PMG, ®) == 0) 13327467bd53SPyun YongHyeon ifp->if_capabilities |= IFCAP_WOL; 1333960fd5b3SPyun YongHyeon ifp->if_capenable = ifp->if_capabilities; 1334960fd5b3SPyun YongHyeon #ifdef DEVICE_POLLING 1335960fd5b3SPyun YongHyeon ifp->if_capabilities |= IFCAP_POLLING; 1336960fd5b3SPyun YongHyeon #endif 1337960fd5b3SPyun YongHyeon /* 1338960fd5b3SPyun YongHyeon * Tell the upper layer(s) we support long frames. 1339960fd5b3SPyun YongHyeon * Must appear after the call to ether_ifattach() because 1340960fd5b3SPyun YongHyeon * ether_ifattach() sets ifi_hdrlen to the default value. 1341960fd5b3SPyun YongHyeon */ 1342960fd5b3SPyun YongHyeon ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1343960fd5b3SPyun YongHyeon 1344ed510fb0SBill Paul #ifdef RE_DIAG 1345ed510fb0SBill Paul /* 1346ed510fb0SBill Paul * Perform hardware diagnostic on the original RTL8169. 1347ed510fb0SBill Paul * Some 32-bit cards were incorrectly wired and would 1348ed510fb0SBill Paul * malfunction if plugged into a 64-bit slot. 1349ed510fb0SBill Paul */ 1350a94100faSBill Paul 1351ed510fb0SBill Paul if (hwrev == RL_HWREV_8169) { 1352ed510fb0SBill Paul error = re_diag(sc); 1353a94100faSBill Paul if (error) { 1354ed510fb0SBill Paul device_printf(dev, 1355ed510fb0SBill Paul "attach aborted due to hardware diag failure\n"); 1356a94100faSBill Paul ether_ifdetach(ifp); 1357a94100faSBill Paul goto fail; 1358a94100faSBill Paul } 1359ed510fb0SBill Paul } 1360ed510fb0SBill Paul #endif 1361a94100faSBill Paul 1362a94100faSBill Paul /* Hook interrupt last to avoid having to lock softc */ 13635774c5ffSPyun YongHyeon if (sc->rl_msi == 0) 13645774c5ffSPyun YongHyeon error = bus_setup_intr(dev, sc->rl_irq[0], 13655774c5ffSPyun YongHyeon INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 13665774c5ffSPyun YongHyeon &sc->rl_intrhand[0]); 13675774c5ffSPyun YongHyeon else { 13685774c5ffSPyun YongHyeon for (i = 0; i < RL_MSI_MESSAGES; i++) { 13695774c5ffSPyun YongHyeon error = bus_setup_intr(dev, sc->rl_irq[i], 13705774c5ffSPyun YongHyeon INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 13715774c5ffSPyun YongHyeon &sc->rl_intrhand[i]); 13725774c5ffSPyun YongHyeon if (error != 0) 13735774c5ffSPyun YongHyeon break; 13745774c5ffSPyun YongHyeon } 13755774c5ffSPyun YongHyeon } 1376a94100faSBill Paul if (error) { 1377d1754a9bSJohn Baldwin device_printf(dev, "couldn't set up irq\n"); 1378a94100faSBill Paul ether_ifdetach(ifp); 1379a94100faSBill Paul } 1380a94100faSBill Paul 1381a94100faSBill Paul fail: 1382ed510fb0SBill Paul 1383a94100faSBill Paul if (error) 1384a94100faSBill Paul re_detach(dev); 1385a94100faSBill Paul 1386a94100faSBill Paul return (error); 1387a94100faSBill Paul } 1388a94100faSBill Paul 1389a94100faSBill Paul /* 1390a94100faSBill Paul * Shutdown hardware and free up resources. This can be called any 1391a94100faSBill Paul * time after the mutex has been initialized. It is called in both 1392a94100faSBill Paul * the error case in attach and the normal detach case so it needs 1393a94100faSBill Paul * to be careful about only freeing resources that have actually been 1394a94100faSBill Paul * allocated. 1395a94100faSBill Paul */ 1396a94100faSBill Paul static int 1397a94100faSBill Paul re_detach(dev) 1398a94100faSBill Paul device_t dev; 1399a94100faSBill Paul { 1400a94100faSBill Paul struct rl_softc *sc; 1401a94100faSBill Paul struct ifnet *ifp; 14025774c5ffSPyun YongHyeon int i, rid; 1403a94100faSBill Paul 1404a94100faSBill Paul sc = device_get_softc(dev); 1405fc74a9f9SBrooks Davis ifp = sc->rl_ifp; 1406aedd16d9SJohn-Mark Gurney KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 140797b9d4baSJohn-Mark Gurney 140840929967SGleb Smirnoff #ifdef DEVICE_POLLING 140940929967SGleb Smirnoff if (ifp->if_capenable & IFCAP_POLLING) 141040929967SGleb Smirnoff ether_poll_deregister(ifp); 141140929967SGleb Smirnoff #endif 141297b9d4baSJohn-Mark Gurney /* These should only be active if attach succeeded */ 1413525e6a87SRuslan Ermilov if (device_is_attached(dev)) { 141497b9d4baSJohn-Mark Gurney RL_LOCK(sc); 141597b9d4baSJohn-Mark Gurney #if 0 141697b9d4baSJohn-Mark Gurney sc->suspended = 1; 141797b9d4baSJohn-Mark Gurney #endif 1418a94100faSBill Paul re_stop(sc); 1419525e6a87SRuslan Ermilov RL_UNLOCK(sc); 1420d1754a9bSJohn Baldwin callout_drain(&sc->rl_stat_callout); 14213d4c1b57SJohn Baldwin taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 14223d4c1b57SJohn Baldwin taskqueue_drain(taskqueue_fast, &sc->rl_txtask); 1423a94100faSBill Paul /* 1424a94100faSBill Paul * Force off the IFF_UP flag here, in case someone 1425a94100faSBill Paul * still had a BPF descriptor attached to this 142697b9d4baSJohn-Mark Gurney * interface. If they do, ether_ifdetach() will cause 1427a94100faSBill Paul * the BPF code to try and clear the promisc mode 1428a94100faSBill Paul * flag, which will bubble down to re_ioctl(), 1429a94100faSBill Paul * which will try to call re_init() again. This will 1430a94100faSBill Paul * turn the NIC back on and restart the MII ticker, 1431a94100faSBill Paul * which will panic the system when the kernel tries 1432a94100faSBill Paul * to invoke the re_tick() function that isn't there 1433a94100faSBill Paul * anymore. 1434a94100faSBill Paul */ 1435a94100faSBill Paul ifp->if_flags &= ~IFF_UP; 1436525e6a87SRuslan Ermilov ether_ifdetach(ifp); 1437a94100faSBill Paul } 1438a94100faSBill Paul if (sc->rl_miibus) 1439a94100faSBill Paul device_delete_child(dev, sc->rl_miibus); 1440a94100faSBill Paul bus_generic_detach(dev); 1441a94100faSBill Paul 144297b9d4baSJohn-Mark Gurney /* 144397b9d4baSJohn-Mark Gurney * The rest is resource deallocation, so we should already be 144497b9d4baSJohn-Mark Gurney * stopped here. 144597b9d4baSJohn-Mark Gurney */ 144697b9d4baSJohn-Mark Gurney 14475774c5ffSPyun YongHyeon for (i = 0; i < RL_MSI_MESSAGES; i++) { 14485774c5ffSPyun YongHyeon if (sc->rl_intrhand[i] != NULL) { 14495774c5ffSPyun YongHyeon bus_teardown_intr(dev, sc->rl_irq[i], 14505774c5ffSPyun YongHyeon sc->rl_intrhand[i]); 14515774c5ffSPyun YongHyeon sc->rl_intrhand[i] = NULL; 14525774c5ffSPyun YongHyeon } 14535774c5ffSPyun YongHyeon } 1454ad4f426eSWarner Losh if (ifp != NULL) 1455ad4f426eSWarner Losh if_free(ifp); 14565774c5ffSPyun YongHyeon if (sc->rl_msi == 0) { 14575774c5ffSPyun YongHyeon if (sc->rl_irq[0] != NULL) { 14585774c5ffSPyun YongHyeon bus_release_resource(dev, SYS_RES_IRQ, 0, 14595774c5ffSPyun YongHyeon sc->rl_irq[0]); 14605774c5ffSPyun YongHyeon sc->rl_irq[0] = NULL; 14615774c5ffSPyun YongHyeon } 14625774c5ffSPyun YongHyeon } else { 14635774c5ffSPyun YongHyeon for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 14645774c5ffSPyun YongHyeon if (sc->rl_irq[i] != NULL) { 14655774c5ffSPyun YongHyeon bus_release_resource(dev, SYS_RES_IRQ, rid, 14665774c5ffSPyun YongHyeon sc->rl_irq[i]); 14675774c5ffSPyun YongHyeon sc->rl_irq[i] = NULL; 14685774c5ffSPyun YongHyeon } 14695774c5ffSPyun YongHyeon } 14705774c5ffSPyun YongHyeon pci_release_msi(dev); 14715774c5ffSPyun YongHyeon } 1472a94100faSBill Paul if (sc->rl_res) 1473a94100faSBill Paul bus_release_resource(dev, RL_RES, RL_RID, sc->rl_res); 1474a94100faSBill Paul 1475a94100faSBill Paul /* Unload and free the RX DMA ring memory and map */ 1476a94100faSBill Paul 1477a94100faSBill Paul if (sc->rl_ldata.rl_rx_list_tag) { 1478a94100faSBill Paul bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1479a94100faSBill Paul sc->rl_ldata.rl_rx_list_map); 1480a94100faSBill Paul bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1481a94100faSBill Paul sc->rl_ldata.rl_rx_list, 1482a94100faSBill Paul sc->rl_ldata.rl_rx_list_map); 1483a94100faSBill Paul bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1484a94100faSBill Paul } 1485a94100faSBill Paul 1486a94100faSBill Paul /* Unload and free the TX DMA ring memory and map */ 1487a94100faSBill Paul 1488a94100faSBill Paul if (sc->rl_ldata.rl_tx_list_tag) { 1489a94100faSBill Paul bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1490a94100faSBill Paul sc->rl_ldata.rl_tx_list_map); 1491a94100faSBill Paul bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1492a94100faSBill Paul sc->rl_ldata.rl_tx_list, 1493a94100faSBill Paul sc->rl_ldata.rl_tx_list_map); 1494a94100faSBill Paul bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1495a94100faSBill Paul } 1496a94100faSBill Paul 1497a94100faSBill Paul /* Destroy all the RX and TX buffer maps */ 1498a94100faSBill Paul 1499d65abd66SPyun YongHyeon if (sc->rl_ldata.rl_tx_mtag) { 1500d65abd66SPyun YongHyeon for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1501d65abd66SPyun YongHyeon bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1502d65abd66SPyun YongHyeon sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1503d65abd66SPyun YongHyeon bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1504d65abd66SPyun YongHyeon } 1505d65abd66SPyun YongHyeon if (sc->rl_ldata.rl_rx_mtag) { 1506d65abd66SPyun YongHyeon for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) 1507d65abd66SPyun YongHyeon bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1508d65abd66SPyun YongHyeon sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1509d65abd66SPyun YongHyeon if (sc->rl_ldata.rl_rx_sparemap) 1510d65abd66SPyun YongHyeon bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1511d65abd66SPyun YongHyeon sc->rl_ldata.rl_rx_sparemap); 1512d65abd66SPyun YongHyeon bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1513a94100faSBill Paul } 1514a94100faSBill Paul 1515a94100faSBill Paul /* Unload and free the stats buffer and map */ 1516a94100faSBill Paul 1517a94100faSBill Paul if (sc->rl_ldata.rl_stag) { 1518a94100faSBill Paul bus_dmamap_unload(sc->rl_ldata.rl_stag, 1519a94100faSBill Paul sc->rl_ldata.rl_rx_list_map); 1520a94100faSBill Paul bus_dmamem_free(sc->rl_ldata.rl_stag, 1521a94100faSBill Paul sc->rl_ldata.rl_stats, 1522a94100faSBill Paul sc->rl_ldata.rl_smap); 1523a94100faSBill Paul bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1524a94100faSBill Paul } 1525a94100faSBill Paul 1526a94100faSBill Paul if (sc->rl_parent_tag) 1527a94100faSBill Paul bus_dma_tag_destroy(sc->rl_parent_tag); 1528a94100faSBill Paul 1529a94100faSBill Paul mtx_destroy(&sc->rl_mtx); 1530a94100faSBill Paul 1531a94100faSBill Paul return (0); 1532a94100faSBill Paul } 1533a94100faSBill Paul 1534d65abd66SPyun YongHyeon static __inline void 1535d65abd66SPyun YongHyeon re_discard_rxbuf(sc, idx) 1536a94100faSBill Paul struct rl_softc *sc; 1537a94100faSBill Paul int idx; 1538a94100faSBill Paul { 1539d65abd66SPyun YongHyeon struct rl_desc *desc; 1540d65abd66SPyun YongHyeon struct rl_rxdesc *rxd; 1541d65abd66SPyun YongHyeon uint32_t cmdstat; 1542a94100faSBill Paul 1543d65abd66SPyun YongHyeon rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1544d65abd66SPyun YongHyeon desc = &sc->rl_ldata.rl_rx_list[idx]; 1545d65abd66SPyun YongHyeon desc->rl_vlanctl = 0; 1546d65abd66SPyun YongHyeon cmdstat = rxd->rx_size; 1547d65abd66SPyun YongHyeon if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1548d65abd66SPyun YongHyeon cmdstat |= RL_RDESC_CMD_EOR; 1549d65abd66SPyun YongHyeon desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1550d65abd66SPyun YongHyeon } 1551d65abd66SPyun YongHyeon 1552d65abd66SPyun YongHyeon static int 1553d65abd66SPyun YongHyeon re_newbuf(sc, idx) 1554d65abd66SPyun YongHyeon struct rl_softc *sc; 1555d65abd66SPyun YongHyeon int idx; 1556d65abd66SPyun YongHyeon { 1557d65abd66SPyun YongHyeon struct mbuf *m; 1558d65abd66SPyun YongHyeon struct rl_rxdesc *rxd; 1559d65abd66SPyun YongHyeon bus_dma_segment_t segs[1]; 1560d65abd66SPyun YongHyeon bus_dmamap_t map; 1561d65abd66SPyun YongHyeon struct rl_desc *desc; 1562d65abd66SPyun YongHyeon uint32_t cmdstat; 1563d65abd66SPyun YongHyeon int error, nsegs; 1564d65abd66SPyun YongHyeon 1565d65abd66SPyun YongHyeon m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1566d65abd66SPyun YongHyeon if (m == NULL) 1567a94100faSBill Paul return (ENOBUFS); 1568a94100faSBill Paul 1569a94100faSBill Paul m->m_len = m->m_pkthdr.len = MCLBYTES; 157022a11c96SJohn-Mark Gurney #ifdef RE_FIXUP_RX 157122a11c96SJohn-Mark Gurney /* 157222a11c96SJohn-Mark Gurney * This is part of an evil trick to deal with non-x86 platforms. 157322a11c96SJohn-Mark Gurney * The RealTek chip requires RX buffers to be aligned on 64-bit 157422a11c96SJohn-Mark Gurney * boundaries, but that will hose non-x86 machines. To get around 157522a11c96SJohn-Mark Gurney * this, we leave some empty space at the start of each buffer 157622a11c96SJohn-Mark Gurney * and for non-x86 hosts, we copy the buffer back six bytes 157722a11c96SJohn-Mark Gurney * to achieve word alignment. This is slightly more efficient 157822a11c96SJohn-Mark Gurney * than allocating a new buffer, copying the contents, and 157922a11c96SJohn-Mark Gurney * discarding the old buffer. 158022a11c96SJohn-Mark Gurney */ 158122a11c96SJohn-Mark Gurney m_adj(m, RE_ETHER_ALIGN); 158222a11c96SJohn-Mark Gurney #endif 1583d65abd66SPyun YongHyeon error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1584d65abd66SPyun YongHyeon sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1585d65abd66SPyun YongHyeon if (error != 0) { 1586d65abd66SPyun YongHyeon m_freem(m); 1587d65abd66SPyun YongHyeon return (ENOBUFS); 1588d65abd66SPyun YongHyeon } 1589d65abd66SPyun YongHyeon KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1590a94100faSBill Paul 1591d65abd66SPyun YongHyeon rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1592d65abd66SPyun YongHyeon if (rxd->rx_m != NULL) { 1593d65abd66SPyun YongHyeon bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1594d65abd66SPyun YongHyeon BUS_DMASYNC_POSTREAD); 1595d65abd66SPyun YongHyeon bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1596a94100faSBill Paul } 1597a94100faSBill Paul 1598d65abd66SPyun YongHyeon rxd->rx_m = m; 1599d65abd66SPyun YongHyeon map = rxd->rx_dmamap; 1600d65abd66SPyun YongHyeon rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1601d65abd66SPyun YongHyeon rxd->rx_size = segs[0].ds_len; 1602d65abd66SPyun YongHyeon sc->rl_ldata.rl_rx_sparemap = map; 1603d65abd66SPyun YongHyeon bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1604a94100faSBill Paul BUS_DMASYNC_PREREAD); 1605a94100faSBill Paul 1606d65abd66SPyun YongHyeon desc = &sc->rl_ldata.rl_rx_list[idx]; 1607d65abd66SPyun YongHyeon desc->rl_vlanctl = 0; 1608d65abd66SPyun YongHyeon desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1609d65abd66SPyun YongHyeon desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1610d65abd66SPyun YongHyeon cmdstat = segs[0].ds_len; 1611d65abd66SPyun YongHyeon if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1612d65abd66SPyun YongHyeon cmdstat |= RL_RDESC_CMD_EOR; 1613d65abd66SPyun YongHyeon desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1614d65abd66SPyun YongHyeon 1615a94100faSBill Paul return (0); 1616a94100faSBill Paul } 1617a94100faSBill Paul 161822a11c96SJohn-Mark Gurney #ifdef RE_FIXUP_RX 161922a11c96SJohn-Mark Gurney static __inline void 162022a11c96SJohn-Mark Gurney re_fixup_rx(m) 162122a11c96SJohn-Mark Gurney struct mbuf *m; 162222a11c96SJohn-Mark Gurney { 162322a11c96SJohn-Mark Gurney int i; 162422a11c96SJohn-Mark Gurney uint16_t *src, *dst; 162522a11c96SJohn-Mark Gurney 162622a11c96SJohn-Mark Gurney src = mtod(m, uint16_t *); 162722a11c96SJohn-Mark Gurney dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 162822a11c96SJohn-Mark Gurney 162922a11c96SJohn-Mark Gurney for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 163022a11c96SJohn-Mark Gurney *dst++ = *src++; 163122a11c96SJohn-Mark Gurney 163222a11c96SJohn-Mark Gurney m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 163322a11c96SJohn-Mark Gurney 163422a11c96SJohn-Mark Gurney return; 163522a11c96SJohn-Mark Gurney } 163622a11c96SJohn-Mark Gurney #endif 163722a11c96SJohn-Mark Gurney 1638a94100faSBill Paul static int 1639a94100faSBill Paul re_tx_list_init(sc) 1640a94100faSBill Paul struct rl_softc *sc; 1641a94100faSBill Paul { 1642d65abd66SPyun YongHyeon struct rl_desc *desc; 1643d65abd66SPyun YongHyeon int i; 164497b9d4baSJohn-Mark Gurney 164597b9d4baSJohn-Mark Gurney RL_LOCK_ASSERT(sc); 164697b9d4baSJohn-Mark Gurney 1647d65abd66SPyun YongHyeon bzero(sc->rl_ldata.rl_tx_list, 1648d65abd66SPyun YongHyeon sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 1649d65abd66SPyun YongHyeon for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 1650d65abd66SPyun YongHyeon sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 1651d65abd66SPyun YongHyeon /* Set EOR. */ 1652d65abd66SPyun YongHyeon desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 1653d65abd66SPyun YongHyeon desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 1654a94100faSBill Paul 1655a94100faSBill Paul bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1656d65abd66SPyun YongHyeon sc->rl_ldata.rl_tx_list_map, 1657d65abd66SPyun YongHyeon BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1658d65abd66SPyun YongHyeon 1659a94100faSBill Paul sc->rl_ldata.rl_tx_prodidx = 0; 1660a94100faSBill Paul sc->rl_ldata.rl_tx_considx = 0; 1661d65abd66SPyun YongHyeon sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 1662a94100faSBill Paul 1663a94100faSBill Paul return (0); 1664a94100faSBill Paul } 1665a94100faSBill Paul 1666a94100faSBill Paul static int 1667a94100faSBill Paul re_rx_list_init(sc) 1668a94100faSBill Paul struct rl_softc *sc; 1669a94100faSBill Paul { 1670d65abd66SPyun YongHyeon int error, i; 1671a94100faSBill Paul 1672d65abd66SPyun YongHyeon bzero(sc->rl_ldata.rl_rx_list, 1673d65abd66SPyun YongHyeon sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 1674d65abd66SPyun YongHyeon for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1675d65abd66SPyun YongHyeon sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 1676d65abd66SPyun YongHyeon if ((error = re_newbuf(sc, i)) != 0) 1677d65abd66SPyun YongHyeon return (error); 1678a94100faSBill Paul } 1679a94100faSBill Paul 1680a94100faSBill Paul /* Flush the RX descriptors */ 1681a94100faSBill Paul 1682a94100faSBill Paul bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1683a94100faSBill Paul sc->rl_ldata.rl_rx_list_map, 1684a94100faSBill Paul BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1685a94100faSBill Paul 1686a94100faSBill Paul sc->rl_ldata.rl_rx_prodidx = 0; 1687a94100faSBill Paul sc->rl_head = sc->rl_tail = NULL; 1688a94100faSBill Paul 1689a94100faSBill Paul return (0); 1690a94100faSBill Paul } 1691a94100faSBill Paul 1692a94100faSBill Paul /* 1693a94100faSBill Paul * RX handler for C+ and 8169. For the gigE chips, we support 1694a94100faSBill Paul * the reception of jumbo frames that have been fragmented 1695a94100faSBill Paul * across multiple 2K mbuf cluster buffers. 1696a94100faSBill Paul */ 1697ed510fb0SBill Paul static int 1698a94100faSBill Paul re_rxeof(sc) 1699a94100faSBill Paul struct rl_softc *sc; 1700a94100faSBill Paul { 1701a94100faSBill Paul struct mbuf *m; 1702a94100faSBill Paul struct ifnet *ifp; 1703a94100faSBill Paul int i, total_len; 1704a94100faSBill Paul struct rl_desc *cur_rx; 1705a94100faSBill Paul u_int32_t rxstat, rxvlan; 1706ed510fb0SBill Paul int maxpkt = 16; 1707a94100faSBill Paul 17085120abbfSSam Leffler RL_LOCK_ASSERT(sc); 17095120abbfSSam Leffler 1710fc74a9f9SBrooks Davis ifp = sc->rl_ifp; 1711a94100faSBill Paul 1712a94100faSBill Paul /* Invalidate the descriptor memory */ 1713a94100faSBill Paul 1714a94100faSBill Paul bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1715a94100faSBill Paul sc->rl_ldata.rl_rx_list_map, 1716d65abd66SPyun YongHyeon BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1717a94100faSBill Paul 1718d65abd66SPyun YongHyeon for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 1719d65abd66SPyun YongHyeon i = RL_RX_DESC_NXT(sc, i)) { 1720a94100faSBill Paul cur_rx = &sc->rl_ldata.rl_rx_list[i]; 1721a94100faSBill Paul rxstat = le32toh(cur_rx->rl_cmdstat); 1722d65abd66SPyun YongHyeon if ((rxstat & RL_RDESC_STAT_OWN) != 0) 1723d65abd66SPyun YongHyeon break; 1724d65abd66SPyun YongHyeon total_len = rxstat & sc->rl_rxlenmask; 1725a94100faSBill Paul rxvlan = le32toh(cur_rx->rl_vlanctl); 1726d65abd66SPyun YongHyeon m = sc->rl_ldata.rl_rx_desc[i].rx_m; 1727a94100faSBill Paul 1728a94100faSBill Paul if (!(rxstat & RL_RDESC_STAT_EOF)) { 1729d65abd66SPyun YongHyeon if (re_newbuf(sc, i) != 0) { 1730d65abd66SPyun YongHyeon /* 1731d65abd66SPyun YongHyeon * If this is part of a multi-fragment packet, 1732d65abd66SPyun YongHyeon * discard all the pieces. 1733d65abd66SPyun YongHyeon */ 1734d65abd66SPyun YongHyeon if (sc->rl_head != NULL) { 1735d65abd66SPyun YongHyeon m_freem(sc->rl_head); 1736d65abd66SPyun YongHyeon sc->rl_head = sc->rl_tail = NULL; 1737d65abd66SPyun YongHyeon } 1738d65abd66SPyun YongHyeon re_discard_rxbuf(sc, i); 1739d65abd66SPyun YongHyeon continue; 1740d65abd66SPyun YongHyeon } 174122a11c96SJohn-Mark Gurney m->m_len = RE_RX_DESC_BUFLEN; 1742a94100faSBill Paul if (sc->rl_head == NULL) 1743a94100faSBill Paul sc->rl_head = sc->rl_tail = m; 1744a94100faSBill Paul else { 1745a94100faSBill Paul m->m_flags &= ~M_PKTHDR; 1746a94100faSBill Paul sc->rl_tail->m_next = m; 1747a94100faSBill Paul sc->rl_tail = m; 1748a94100faSBill Paul } 1749a94100faSBill Paul continue; 1750a94100faSBill Paul } 1751a94100faSBill Paul 1752a94100faSBill Paul /* 1753a94100faSBill Paul * NOTE: for the 8139C+, the frame length field 1754a94100faSBill Paul * is always 12 bits in size, but for the gigE chips, 1755a94100faSBill Paul * it is 13 bits (since the max RX frame length is 16K). 1756a94100faSBill Paul * Unfortunately, all 32 bits in the status word 1757a94100faSBill Paul * were already used, so to make room for the extra 1758a94100faSBill Paul * length bit, RealTek took out the 'frame alignment 1759a94100faSBill Paul * error' bit and shifted the other status bits 1760a94100faSBill Paul * over one slot. The OWN, EOR, FS and LS bits are 1761a94100faSBill Paul * still in the same places. We have already extracted 1762a94100faSBill Paul * the frame length and checked the OWN bit, so rather 1763a94100faSBill Paul * than using an alternate bit mapping, we shift the 1764a94100faSBill Paul * status bits one space to the right so we can evaluate 1765a94100faSBill Paul * them using the 8169 status as though it was in the 1766a94100faSBill Paul * same format as that of the 8139C+. 1767a94100faSBill Paul */ 1768a94100faSBill Paul if (sc->rl_type == RL_8169) 1769a94100faSBill Paul rxstat >>= 1; 1770a94100faSBill Paul 177122a11c96SJohn-Mark Gurney /* 177222a11c96SJohn-Mark Gurney * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 177322a11c96SJohn-Mark Gurney * set, but if CRC is clear, it will still be a valid frame. 177422a11c96SJohn-Mark Gurney */ 177522a11c96SJohn-Mark Gurney if (rxstat & RL_RDESC_STAT_RXERRSUM && !(total_len > 8191 && 177622a11c96SJohn-Mark Gurney (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT)) { 1777a94100faSBill Paul ifp->if_ierrors++; 1778a94100faSBill Paul /* 1779a94100faSBill Paul * If this is part of a multi-fragment packet, 1780a94100faSBill Paul * discard all the pieces. 1781a94100faSBill Paul */ 1782a94100faSBill Paul if (sc->rl_head != NULL) { 1783a94100faSBill Paul m_freem(sc->rl_head); 1784a94100faSBill Paul sc->rl_head = sc->rl_tail = NULL; 1785a94100faSBill Paul } 1786d65abd66SPyun YongHyeon re_discard_rxbuf(sc, i); 1787a94100faSBill Paul continue; 1788a94100faSBill Paul } 1789a94100faSBill Paul 1790a94100faSBill Paul /* 1791a94100faSBill Paul * If allocating a replacement mbuf fails, 1792a94100faSBill Paul * reload the current one. 1793a94100faSBill Paul */ 1794a94100faSBill Paul 1795d65abd66SPyun YongHyeon if (re_newbuf(sc, i) != 0) { 1796d65abd66SPyun YongHyeon ifp->if_iqdrops++; 1797a94100faSBill Paul if (sc->rl_head != NULL) { 1798a94100faSBill Paul m_freem(sc->rl_head); 1799a94100faSBill Paul sc->rl_head = sc->rl_tail = NULL; 1800a94100faSBill Paul } 1801d65abd66SPyun YongHyeon re_discard_rxbuf(sc, i); 1802a94100faSBill Paul continue; 1803a94100faSBill Paul } 1804a94100faSBill Paul 1805a94100faSBill Paul if (sc->rl_head != NULL) { 180622a11c96SJohn-Mark Gurney m->m_len = total_len % RE_RX_DESC_BUFLEN; 180722a11c96SJohn-Mark Gurney if (m->m_len == 0) 180822a11c96SJohn-Mark Gurney m->m_len = RE_RX_DESC_BUFLEN; 1809a94100faSBill Paul /* 1810a94100faSBill Paul * Special case: if there's 4 bytes or less 1811a94100faSBill Paul * in this buffer, the mbuf can be discarded: 1812a94100faSBill Paul * the last 4 bytes is the CRC, which we don't 1813a94100faSBill Paul * care about anyway. 1814a94100faSBill Paul */ 1815a94100faSBill Paul if (m->m_len <= ETHER_CRC_LEN) { 1816a94100faSBill Paul sc->rl_tail->m_len -= 1817a94100faSBill Paul (ETHER_CRC_LEN - m->m_len); 1818a94100faSBill Paul m_freem(m); 1819a94100faSBill Paul } else { 1820a94100faSBill Paul m->m_len -= ETHER_CRC_LEN; 1821a94100faSBill Paul m->m_flags &= ~M_PKTHDR; 1822a94100faSBill Paul sc->rl_tail->m_next = m; 1823a94100faSBill Paul } 1824a94100faSBill Paul m = sc->rl_head; 1825a94100faSBill Paul sc->rl_head = sc->rl_tail = NULL; 1826a94100faSBill Paul m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1827a94100faSBill Paul } else 1828a94100faSBill Paul m->m_pkthdr.len = m->m_len = 1829a94100faSBill Paul (total_len - ETHER_CRC_LEN); 1830a94100faSBill Paul 183122a11c96SJohn-Mark Gurney #ifdef RE_FIXUP_RX 183222a11c96SJohn-Mark Gurney re_fixup_rx(m); 183322a11c96SJohn-Mark Gurney #endif 1834a94100faSBill Paul ifp->if_ipackets++; 1835a94100faSBill Paul m->m_pkthdr.rcvif = ifp; 1836a94100faSBill Paul 1837a94100faSBill Paul /* Do RX checksumming if enabled */ 1838a94100faSBill Paul 1839a94100faSBill Paul if (ifp->if_capenable & IFCAP_RXCSUM) { 1840a94100faSBill Paul 1841a94100faSBill Paul /* Check IP header checksum */ 1842a94100faSBill Paul if (rxstat & RL_RDESC_STAT_PROTOID) 1843a94100faSBill Paul m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1844a94100faSBill Paul if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 1845a94100faSBill Paul m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1846a94100faSBill Paul 1847a94100faSBill Paul /* Check TCP/UDP checksum */ 1848a94100faSBill Paul if ((RL_TCPPKT(rxstat) && 1849a94100faSBill Paul !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 1850a94100faSBill Paul (RL_UDPPKT(rxstat) && 1851a94100faSBill Paul !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 1852a94100faSBill Paul m->m_pkthdr.csum_flags |= 1853a94100faSBill Paul CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1854a94100faSBill Paul m->m_pkthdr.csum_data = 0xffff; 1855a94100faSBill Paul } 1856a94100faSBill Paul } 1857ed510fb0SBill Paul maxpkt--; 1858d147662cSGleb Smirnoff if (rxvlan & RL_RDESC_VLANCTL_TAG) { 185978ba57b9SAndre Oppermann m->m_pkthdr.ether_vtag = 186078ba57b9SAndre Oppermann ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)); 186178ba57b9SAndre Oppermann m->m_flags |= M_VLANTAG; 1862d147662cSGleb Smirnoff } 18635120abbfSSam Leffler RL_UNLOCK(sc); 1864a94100faSBill Paul (*ifp->if_input)(ifp, m); 18655120abbfSSam Leffler RL_LOCK(sc); 1866a94100faSBill Paul } 1867a94100faSBill Paul 1868a94100faSBill Paul /* Flush the RX DMA ring */ 1869a94100faSBill Paul 1870a94100faSBill Paul bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 1871a94100faSBill Paul sc->rl_ldata.rl_rx_list_map, 1872a94100faSBill Paul BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1873a94100faSBill Paul 1874a94100faSBill Paul sc->rl_ldata.rl_rx_prodidx = i; 1875ed510fb0SBill Paul 1876ed510fb0SBill Paul if (maxpkt) 1877ed510fb0SBill Paul return(EAGAIN); 1878ed510fb0SBill Paul 1879ed510fb0SBill Paul return(0); 1880a94100faSBill Paul } 1881a94100faSBill Paul 1882a94100faSBill Paul static void 1883a94100faSBill Paul re_txeof(sc) 1884a94100faSBill Paul struct rl_softc *sc; 1885a94100faSBill Paul { 1886a94100faSBill Paul struct ifnet *ifp; 1887d65abd66SPyun YongHyeon struct rl_txdesc *txd; 1888a94100faSBill Paul u_int32_t txstat; 1889d65abd66SPyun YongHyeon int cons; 1890d65abd66SPyun YongHyeon 1891d65abd66SPyun YongHyeon cons = sc->rl_ldata.rl_tx_considx; 1892d65abd66SPyun YongHyeon if (cons == sc->rl_ldata.rl_tx_prodidx) 1893d65abd66SPyun YongHyeon return; 1894a94100faSBill Paul 1895fc74a9f9SBrooks Davis ifp = sc->rl_ifp; 1896a94100faSBill Paul /* Invalidate the TX descriptor list */ 1897a94100faSBill Paul bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 1898a94100faSBill Paul sc->rl_ldata.rl_tx_list_map, 1899d65abd66SPyun YongHyeon BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1900a94100faSBill Paul 1901d65abd66SPyun YongHyeon for (; cons != sc->rl_ldata.rl_tx_prodidx; 1902d65abd66SPyun YongHyeon cons = RL_TX_DESC_NXT(sc, cons)) { 1903d65abd66SPyun YongHyeon txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 1904d65abd66SPyun YongHyeon if (txstat & RL_TDESC_STAT_OWN) 1905a94100faSBill Paul break; 1906a94100faSBill Paul /* 1907a94100faSBill Paul * We only stash mbufs in the last descriptor 1908a94100faSBill Paul * in a fragment chain, which also happens to 1909a94100faSBill Paul * be the only place where the TX status bits 1910a94100faSBill Paul * are valid. 1911a94100faSBill Paul */ 1912a94100faSBill Paul if (txstat & RL_TDESC_CMD_EOF) { 1913d65abd66SPyun YongHyeon txd = &sc->rl_ldata.rl_tx_desc[cons]; 1914d65abd66SPyun YongHyeon bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 1915d65abd66SPyun YongHyeon txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 1916d65abd66SPyun YongHyeon bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 1917d65abd66SPyun YongHyeon txd->tx_dmamap); 1918d65abd66SPyun YongHyeon KASSERT(txd->tx_m != NULL, 1919d65abd66SPyun YongHyeon ("%s: freeing NULL mbufs!", __func__)); 1920d65abd66SPyun YongHyeon m_freem(txd->tx_m); 1921d65abd66SPyun YongHyeon txd->tx_m = NULL; 1922a94100faSBill Paul if (txstat & (RL_TDESC_STAT_EXCESSCOL| 1923a94100faSBill Paul RL_TDESC_STAT_COLCNT)) 1924a94100faSBill Paul ifp->if_collisions++; 1925a94100faSBill Paul if (txstat & RL_TDESC_STAT_TXERRSUM) 1926a94100faSBill Paul ifp->if_oerrors++; 1927a94100faSBill Paul else 1928a94100faSBill Paul ifp->if_opackets++; 1929a94100faSBill Paul } 1930a94100faSBill Paul sc->rl_ldata.rl_tx_free++; 1931d65abd66SPyun YongHyeon ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1932a94100faSBill Paul } 1933d65abd66SPyun YongHyeon sc->rl_ldata.rl_tx_considx = cons; 1934a94100faSBill Paul 1935a94100faSBill Paul /* No changes made to the TX ring, so no flush needed */ 1936a94100faSBill Paul 1937d65abd66SPyun YongHyeon if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 19380fc4974fSBill Paul /* 1939b4b95879SMarius Strobl * Some chips will ignore a second TX request issued 1940b4b95879SMarius Strobl * while an existing transmission is in progress. If 1941b4b95879SMarius Strobl * the transmitter goes idle but there are still 1942b4b95879SMarius Strobl * packets waiting to be sent, we need to restart the 1943b4b95879SMarius Strobl * channel here to flush them out. This only seems to 1944b4b95879SMarius Strobl * be required with the PCIe devices. 19450fc4974fSBill Paul */ 19460fc4974fSBill Paul CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 19470fc4974fSBill Paul 1948ed510fb0SBill Paul #ifdef RE_TX_MODERATION 1949a94100faSBill Paul /* 1950b4b95879SMarius Strobl * If not all descriptors have been reaped yet, reload 1951b4b95879SMarius Strobl * the timer so that we will eventually get another 1952a94100faSBill Paul * interrupt that will cause us to re-enter this routine. 1953a94100faSBill Paul * This is done in case the transmitter has gone idle. 1954a94100faSBill Paul */ 1955a94100faSBill Paul CSR_WRITE_4(sc, RL_TIMERCNT, 1); 1956ed510fb0SBill Paul #endif 1957b4b95879SMarius Strobl } else 1958b4b95879SMarius Strobl sc->rl_watchdog_timer = 0; 1959a94100faSBill Paul } 1960a94100faSBill Paul 1961a94100faSBill Paul static void 1962a94100faSBill Paul re_tick(xsc) 1963a94100faSBill Paul void *xsc; 1964a94100faSBill Paul { 1965a94100faSBill Paul struct rl_softc *sc; 1966d1754a9bSJohn Baldwin struct mii_data *mii; 1967ed510fb0SBill Paul struct ifnet *ifp; 1968a94100faSBill Paul 1969a94100faSBill Paul sc = xsc; 1970ed510fb0SBill Paul ifp = sc->rl_ifp; 197197b9d4baSJohn-Mark Gurney 197297b9d4baSJohn-Mark Gurney RL_LOCK_ASSERT(sc); 197397b9d4baSJohn-Mark Gurney 19741d545c7aSMarius Strobl re_watchdog(sc); 1975a94100faSBill Paul 19761d545c7aSMarius Strobl mii = device_get_softc(sc->rl_miibus); 1977a94100faSBill Paul mii_tick(mii); 1978ed510fb0SBill Paul if (sc->rl_link) { 1979ed510fb0SBill Paul if (!(mii->mii_media_status & IFM_ACTIVE)) 1980ed510fb0SBill Paul sc->rl_link = 0; 1981ed510fb0SBill Paul } else { 1982ed510fb0SBill Paul if (mii->mii_media_status & IFM_ACTIVE && 1983ed510fb0SBill Paul IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1984ed510fb0SBill Paul sc->rl_link = 1; 1985ed510fb0SBill Paul if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1986ed510fb0SBill Paul taskqueue_enqueue_fast(taskqueue_fast, 1987ed510fb0SBill Paul &sc->rl_txtask); 1988ed510fb0SBill Paul } 1989ed510fb0SBill Paul } 1990a94100faSBill Paul 1991d1754a9bSJohn Baldwin callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 1992a94100faSBill Paul } 1993a94100faSBill Paul 1994a94100faSBill Paul #ifdef DEVICE_POLLING 1995a94100faSBill Paul static void 1996a94100faSBill Paul re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1997a94100faSBill Paul { 1998a94100faSBill Paul struct rl_softc *sc = ifp->if_softc; 1999a94100faSBill Paul 2000a94100faSBill Paul RL_LOCK(sc); 200140929967SGleb Smirnoff if (ifp->if_drv_flags & IFF_DRV_RUNNING) 200297b9d4baSJohn-Mark Gurney re_poll_locked(ifp, cmd, count); 200397b9d4baSJohn-Mark Gurney RL_UNLOCK(sc); 200497b9d4baSJohn-Mark Gurney } 200597b9d4baSJohn-Mark Gurney 200697b9d4baSJohn-Mark Gurney static void 200797b9d4baSJohn-Mark Gurney re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 200897b9d4baSJohn-Mark Gurney { 200997b9d4baSJohn-Mark Gurney struct rl_softc *sc = ifp->if_softc; 201097b9d4baSJohn-Mark Gurney 201197b9d4baSJohn-Mark Gurney RL_LOCK_ASSERT(sc); 201297b9d4baSJohn-Mark Gurney 2013a94100faSBill Paul sc->rxcycles = count; 2014a94100faSBill Paul re_rxeof(sc); 2015a94100faSBill Paul re_txeof(sc); 2016a94100faSBill Paul 201737652939SMax Laier if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2018ed510fb0SBill Paul taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2019a94100faSBill Paul 2020a94100faSBill Paul if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2021a94100faSBill Paul u_int16_t status; 2022a94100faSBill Paul 2023a94100faSBill Paul status = CSR_READ_2(sc, RL_ISR); 2024a94100faSBill Paul if (status == 0xffff) 202597b9d4baSJohn-Mark Gurney return; 2026a94100faSBill Paul if (status) 2027a94100faSBill Paul CSR_WRITE_2(sc, RL_ISR, status); 2028a94100faSBill Paul 2029a94100faSBill Paul /* 2030a94100faSBill Paul * XXX check behaviour on receiver stalls. 2031a94100faSBill Paul */ 2032a94100faSBill Paul 2033a94100faSBill Paul if (status & RL_ISR_SYSTEM_ERR) { 2034a94100faSBill Paul re_reset(sc); 203597b9d4baSJohn-Mark Gurney re_init_locked(sc); 2036a94100faSBill Paul } 2037a94100faSBill Paul } 2038a94100faSBill Paul } 2039a94100faSBill Paul #endif /* DEVICE_POLLING */ 2040a94100faSBill Paul 2041ef544f63SPaolo Pisati static int 2042a94100faSBill Paul re_intr(arg) 2043a94100faSBill Paul void *arg; 2044a94100faSBill Paul { 2045a94100faSBill Paul struct rl_softc *sc; 2046ed510fb0SBill Paul uint16_t status; 2047a94100faSBill Paul 2048a94100faSBill Paul sc = arg; 2049ed510fb0SBill Paul 2050ed510fb0SBill Paul status = CSR_READ_2(sc, RL_ISR); 2051498bd0d3SBill Paul if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2052ef544f63SPaolo Pisati return (FILTER_STRAY); 2053ed510fb0SBill Paul CSR_WRITE_2(sc, RL_IMR, 0); 2054ed510fb0SBill Paul 2055ed510fb0SBill Paul taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2056ed510fb0SBill Paul 2057ef544f63SPaolo Pisati return (FILTER_HANDLED); 2058ed510fb0SBill Paul } 2059ed510fb0SBill Paul 2060ed510fb0SBill Paul static void 2061ed510fb0SBill Paul re_int_task(arg, npending) 2062ed510fb0SBill Paul void *arg; 2063ed510fb0SBill Paul int npending; 2064ed510fb0SBill Paul { 2065ed510fb0SBill Paul struct rl_softc *sc; 2066ed510fb0SBill Paul struct ifnet *ifp; 2067ed510fb0SBill Paul u_int16_t status; 2068ed510fb0SBill Paul int rval = 0; 2069ed510fb0SBill Paul 2070ed510fb0SBill Paul sc = arg; 2071ed510fb0SBill Paul ifp = sc->rl_ifp; 2072a94100faSBill Paul 2073a94100faSBill Paul RL_LOCK(sc); 207497b9d4baSJohn-Mark Gurney 2075a94100faSBill Paul status = CSR_READ_2(sc, RL_ISR); 2076a94100faSBill Paul CSR_WRITE_2(sc, RL_ISR, status); 2077a94100faSBill Paul 2078d65abd66SPyun YongHyeon if (sc->suspended || 2079d65abd66SPyun YongHyeon (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2080ed510fb0SBill Paul RL_UNLOCK(sc); 2081ed510fb0SBill Paul return; 2082ed510fb0SBill Paul } 2083a94100faSBill Paul 2084ed510fb0SBill Paul #ifdef DEVICE_POLLING 2085ed510fb0SBill Paul if (ifp->if_capenable & IFCAP_POLLING) { 2086ed510fb0SBill Paul RL_UNLOCK(sc); 2087ed510fb0SBill Paul return; 2088ed510fb0SBill Paul } 2089ed510fb0SBill Paul #endif 2090a94100faSBill Paul 2091ed510fb0SBill Paul if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2092ed510fb0SBill Paul rval = re_rxeof(sc); 2093ed510fb0SBill Paul 2094ed510fb0SBill Paul #ifdef RE_TX_MODERATION 2095ed510fb0SBill Paul if (status & (RL_ISR_TIMEOUT_EXPIRED| 2096ed510fb0SBill Paul #else 2097ed510fb0SBill Paul if (status & (RL_ISR_TX_OK| 2098ed510fb0SBill Paul #endif 2099ed510fb0SBill Paul RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2100a94100faSBill Paul re_txeof(sc); 2101a94100faSBill Paul 2102a94100faSBill Paul if (status & RL_ISR_SYSTEM_ERR) { 2103a94100faSBill Paul re_reset(sc); 210497b9d4baSJohn-Mark Gurney re_init_locked(sc); 2105a94100faSBill Paul } 2106a94100faSBill Paul 2107a94100faSBill Paul if (status & RL_ISR_LINKCHG) { 2108d1754a9bSJohn Baldwin callout_stop(&sc->rl_stat_callout); 2109d1754a9bSJohn Baldwin re_tick(sc); 2110a94100faSBill Paul } 2111a94100faSBill Paul 211252732175SMax Laier if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2113ed510fb0SBill Paul taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask); 2114a94100faSBill Paul 2115a94100faSBill Paul RL_UNLOCK(sc); 2116ed510fb0SBill Paul 2117ed510fb0SBill Paul if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2118ed510fb0SBill Paul taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2119ed510fb0SBill Paul return; 2120ed510fb0SBill Paul } 2121ed510fb0SBill Paul 2122ed510fb0SBill Paul CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2123ed510fb0SBill Paul 2124ed510fb0SBill Paul return; 2125a94100faSBill Paul } 2126a94100faSBill Paul 2127d65abd66SPyun YongHyeon static int 2128d65abd66SPyun YongHyeon re_encap(sc, m_head) 2129d65abd66SPyun YongHyeon struct rl_softc *sc; 2130d65abd66SPyun YongHyeon struct mbuf **m_head; 2131d65abd66SPyun YongHyeon { 2132d65abd66SPyun YongHyeon struct rl_txdesc *txd, *txd_last; 2133d65abd66SPyun YongHyeon bus_dma_segment_t segs[RL_NTXSEGS]; 2134d65abd66SPyun YongHyeon bus_dmamap_t map; 2135d65abd66SPyun YongHyeon struct mbuf *m_new; 2136d65abd66SPyun YongHyeon struct rl_desc *desc; 2137d65abd66SPyun YongHyeon int nsegs, prod; 2138d65abd66SPyun YongHyeon int i, error, ei, si; 2139d65abd66SPyun YongHyeon int padlen; 2140ccf34c81SPyun YongHyeon uint32_t cmdstat, csum_flags, vlanctl; 2141a94100faSBill Paul 2142d65abd66SPyun YongHyeon RL_LOCK_ASSERT(sc); 2143738489d1SPyun YongHyeon M_ASSERTPKTHDR((*m_head)); 21440fc4974fSBill Paul 21450fc4974fSBill Paul /* 21460fc4974fSBill Paul * With some of the RealTek chips, using the checksum offload 21470fc4974fSBill Paul * support in conjunction with the autopadding feature results 21480fc4974fSBill Paul * in the transmission of corrupt frames. For example, if we 21490fc4974fSBill Paul * need to send a really small IP fragment that's less than 60 21500fc4974fSBill Paul * bytes in size, and IP header checksumming is enabled, the 21510fc4974fSBill Paul * resulting ethernet frame that appears on the wire will 21520fc4974fSBill Paul * have garbled payload. To work around this, if TX checksum 21530fc4974fSBill Paul * offload is enabled, we always manually pad short frames out 2154d65abd66SPyun YongHyeon * to the minimum ethernet frame size. 2155e2bcb489SBill Paul * 2156e2bcb489SBill Paul * Note: this appears unnecessary for TCP, and doing it for TCP 2157e2bcb489SBill Paul * with PCIe adapters seems to result in bad checksums. 21580fc4974fSBill Paul */ 2159d65abd66SPyun YongHyeon if ((*m_head)->m_pkthdr.csum_flags & (CSUM_IP | CSUM_UDP) && 2160d65abd66SPyun YongHyeon ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) == 0 && 2161d65abd66SPyun YongHyeon (*m_head)->m_pkthdr.len < RL_MIN_FRAMELEN) { 2162d65abd66SPyun YongHyeon padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2163d65abd66SPyun YongHyeon if (M_WRITABLE(*m_head) == 0) { 2164d65abd66SPyun YongHyeon /* Get a writable copy. */ 2165d65abd66SPyun YongHyeon m_new = m_dup(*m_head, M_DONTWAIT); 2166d65abd66SPyun YongHyeon m_freem(*m_head); 2167d65abd66SPyun YongHyeon if (m_new == NULL) { 2168d65abd66SPyun YongHyeon *m_head = NULL; 2169a94100faSBill Paul return (ENOBUFS); 2170a94100faSBill Paul } 2171d65abd66SPyun YongHyeon *m_head = m_new; 2172d65abd66SPyun YongHyeon } 2173d65abd66SPyun YongHyeon if ((*m_head)->m_next != NULL || 2174d65abd66SPyun YongHyeon M_TRAILINGSPACE(*m_head) < padlen) { 217580a2a305SJohn-Mark Gurney m_new = m_defrag(*m_head, M_DONTWAIT); 2176b4b95879SMarius Strobl if (m_new == NULL) { 2177b4b95879SMarius Strobl m_freem(*m_head); 2178b4b95879SMarius Strobl *m_head = NULL; 217980a2a305SJohn-Mark Gurney return (ENOBUFS); 2180b4b95879SMarius Strobl } 2181d65abd66SPyun YongHyeon } else 2182d65abd66SPyun YongHyeon m_new = *m_head; 2183a94100faSBill Paul 21840fc4974fSBill Paul /* 21850fc4974fSBill Paul * Manually pad short frames, and zero the pad space 21860fc4974fSBill Paul * to avoid leaking data. 21870fc4974fSBill Paul */ 2188d65abd66SPyun YongHyeon bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2189d65abd66SPyun YongHyeon m_new->m_pkthdr.len += padlen; 21900fc4974fSBill Paul m_new->m_len = m_new->m_pkthdr.len; 2191d65abd66SPyun YongHyeon *m_head = m_new; 21920fc4974fSBill Paul } 21930fc4974fSBill Paul 2194d65abd66SPyun YongHyeon prod = sc->rl_ldata.rl_tx_prodidx; 2195d65abd66SPyun YongHyeon txd = &sc->rl_ldata.rl_tx_desc[prod]; 2196d65abd66SPyun YongHyeon error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2197d65abd66SPyun YongHyeon *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2198d65abd66SPyun YongHyeon if (error == EFBIG) { 2199304a4c6fSJohn Baldwin m_new = m_collapse(*m_head, M_DONTWAIT, RL_NTXSEGS); 2200d65abd66SPyun YongHyeon if (m_new == NULL) { 2201d65abd66SPyun YongHyeon m_freem(*m_head); 2202b4b95879SMarius Strobl *m_head = NULL; 2203d65abd66SPyun YongHyeon return (ENOBUFS); 2204a94100faSBill Paul } 2205d65abd66SPyun YongHyeon *m_head = m_new; 2206d65abd66SPyun YongHyeon error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2207d65abd66SPyun YongHyeon txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2208d65abd66SPyun YongHyeon if (error != 0) { 2209d65abd66SPyun YongHyeon m_freem(*m_head); 2210d65abd66SPyun YongHyeon *m_head = NULL; 2211d65abd66SPyun YongHyeon return (error); 2212a94100faSBill Paul } 2213d65abd66SPyun YongHyeon } else if (error != 0) 2214d65abd66SPyun YongHyeon return (error); 2215d65abd66SPyun YongHyeon if (nsegs == 0) { 2216d65abd66SPyun YongHyeon m_freem(*m_head); 2217d65abd66SPyun YongHyeon *m_head = NULL; 2218d65abd66SPyun YongHyeon return (EIO); 2219d65abd66SPyun YongHyeon } 2220d65abd66SPyun YongHyeon 2221d65abd66SPyun YongHyeon /* Check for number of available descriptors. */ 2222d65abd66SPyun YongHyeon if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2223d65abd66SPyun YongHyeon bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2224d65abd66SPyun YongHyeon return (ENOBUFS); 2225d65abd66SPyun YongHyeon } 2226d65abd66SPyun YongHyeon 2227d65abd66SPyun YongHyeon bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2228d65abd66SPyun YongHyeon BUS_DMASYNC_PREWRITE); 2229a94100faSBill Paul 2230a94100faSBill Paul /* 2231d65abd66SPyun YongHyeon * Set up checksum offload. Note: checksum offload bits must 2232d65abd66SPyun YongHyeon * appear in all descriptors of a multi-descriptor transmit 2233d65abd66SPyun YongHyeon * attempt. This is according to testing done with an 8169 2234d65abd66SPyun YongHyeon * chip. This is a requirement. 2235a94100faSBill Paul */ 2236d65abd66SPyun YongHyeon csum_flags = 0; 2237d65abd66SPyun YongHyeon if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) 2238d65abd66SPyun YongHyeon csum_flags = RL_TDESC_CMD_LGSEND | 2239d65abd66SPyun YongHyeon ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2240d65abd66SPyun YongHyeon RL_TDESC_CMD_MSSVAL_SHIFT); 2241d65abd66SPyun YongHyeon else { 2242d65abd66SPyun YongHyeon if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) 2243d65abd66SPyun YongHyeon csum_flags |= RL_TDESC_CMD_IPCSUM; 2244d65abd66SPyun YongHyeon if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) 2245d65abd66SPyun YongHyeon csum_flags |= RL_TDESC_CMD_TCPCSUM; 2246d65abd66SPyun YongHyeon if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) 2247d65abd66SPyun YongHyeon csum_flags |= RL_TDESC_CMD_UDPCSUM; 2248d65abd66SPyun YongHyeon } 2249a94100faSBill Paul 2250ccf34c81SPyun YongHyeon /* 2251ccf34c81SPyun YongHyeon * Set up hardware VLAN tagging. Note: vlan tag info must 2252ccf34c81SPyun YongHyeon * appear in all descriptors of a multi-descriptor 2253ccf34c81SPyun YongHyeon * transmission attempt. 2254ccf34c81SPyun YongHyeon */ 2255ccf34c81SPyun YongHyeon vlanctl = 0; 2256ccf34c81SPyun YongHyeon if ((*m_head)->m_flags & M_VLANTAG) 2257ccf34c81SPyun YongHyeon vlanctl = 2258ccf34c81SPyun YongHyeon htole32(htons((*m_head)->m_pkthdr.ether_vtag) | 2259ccf34c81SPyun YongHyeon RL_TDESC_VLANCTL_TAG); 2260ccf34c81SPyun YongHyeon 2261d65abd66SPyun YongHyeon si = prod; 2262d65abd66SPyun YongHyeon for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2263d65abd66SPyun YongHyeon desc = &sc->rl_ldata.rl_tx_list[prod]; 2264ccf34c81SPyun YongHyeon desc->rl_vlanctl = vlanctl; 2265d65abd66SPyun YongHyeon desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2266d65abd66SPyun YongHyeon desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2267d65abd66SPyun YongHyeon cmdstat = segs[i].ds_len; 2268d65abd66SPyun YongHyeon if (i != 0) 2269d65abd66SPyun YongHyeon cmdstat |= RL_TDESC_CMD_OWN; 2270d65abd66SPyun YongHyeon if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2271d65abd66SPyun YongHyeon cmdstat |= RL_TDESC_CMD_EOR; 2272d65abd66SPyun YongHyeon desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2273d65abd66SPyun YongHyeon sc->rl_ldata.rl_tx_free--; 2274d65abd66SPyun YongHyeon } 2275d65abd66SPyun YongHyeon /* Update producer index. */ 2276d65abd66SPyun YongHyeon sc->rl_ldata.rl_tx_prodidx = prod; 2277a94100faSBill Paul 2278d65abd66SPyun YongHyeon /* Set EOF on the last descriptor. */ 2279d65abd66SPyun YongHyeon ei = RL_TX_DESC_PRV(sc, prod); 2280d65abd66SPyun YongHyeon desc = &sc->rl_ldata.rl_tx_list[ei]; 2281d65abd66SPyun YongHyeon desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2282d65abd66SPyun YongHyeon 2283d65abd66SPyun YongHyeon desc = &sc->rl_ldata.rl_tx_list[si]; 2284d65abd66SPyun YongHyeon /* Set SOF and transfer ownership of packet to the chip. */ 2285d65abd66SPyun YongHyeon desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2286a94100faSBill Paul 2287d65abd66SPyun YongHyeon /* 2288d65abd66SPyun YongHyeon * Insure that the map for this transmission 2289d65abd66SPyun YongHyeon * is placed at the array index of the last descriptor 2290d65abd66SPyun YongHyeon * in this chain. (Swap last and first dmamaps.) 2291d65abd66SPyun YongHyeon */ 2292d65abd66SPyun YongHyeon txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2293d65abd66SPyun YongHyeon map = txd->tx_dmamap; 2294d65abd66SPyun YongHyeon txd->tx_dmamap = txd_last->tx_dmamap; 2295d65abd66SPyun YongHyeon txd_last->tx_dmamap = map; 2296d65abd66SPyun YongHyeon txd_last->tx_m = *m_head; 2297a94100faSBill Paul 2298a94100faSBill Paul return (0); 2299a94100faSBill Paul } 2300a94100faSBill Paul 230197b9d4baSJohn-Mark Gurney static void 2302ed510fb0SBill Paul re_tx_task(arg, npending) 2303ed510fb0SBill Paul void *arg; 2304ed510fb0SBill Paul int npending; 230597b9d4baSJohn-Mark Gurney { 2306ed510fb0SBill Paul struct ifnet *ifp; 230797b9d4baSJohn-Mark Gurney 2308ed510fb0SBill Paul ifp = arg; 2309ed510fb0SBill Paul re_start(ifp); 2310ed510fb0SBill Paul 2311ed510fb0SBill Paul return; 231297b9d4baSJohn-Mark Gurney } 231397b9d4baSJohn-Mark Gurney 2314a94100faSBill Paul /* 2315a94100faSBill Paul * Main transmit routine for C+ and gigE NICs. 2316a94100faSBill Paul */ 2317a94100faSBill Paul static void 2318ed510fb0SBill Paul re_start(ifp) 2319a94100faSBill Paul struct ifnet *ifp; 2320a94100faSBill Paul { 2321a94100faSBill Paul struct rl_softc *sc; 2322d65abd66SPyun YongHyeon struct mbuf *m_head; 2323d65abd66SPyun YongHyeon int queued; 2324a94100faSBill Paul 2325a94100faSBill Paul sc = ifp->if_softc; 232697b9d4baSJohn-Mark Gurney 2327ed510fb0SBill Paul RL_LOCK(sc); 2328ed510fb0SBill Paul 2329d65abd66SPyun YongHyeon if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2330d65abd66SPyun YongHyeon IFF_DRV_RUNNING || sc->rl_link == 0) { 2331ed510fb0SBill Paul RL_UNLOCK(sc); 2332ed510fb0SBill Paul return; 2333ed510fb0SBill Paul } 2334a94100faSBill Paul 2335d65abd66SPyun YongHyeon for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2336d65abd66SPyun YongHyeon sc->rl_ldata.rl_tx_free > 1;) { 233752732175SMax Laier IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2338a94100faSBill Paul if (m_head == NULL) 2339a94100faSBill Paul break; 2340a94100faSBill Paul 2341d65abd66SPyun YongHyeon if (re_encap(sc, &m_head) != 0) { 2342b4b95879SMarius Strobl if (m_head == NULL) 2343b4b95879SMarius Strobl break; 234452732175SMax Laier IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 234513f4c340SRobert Watson ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2346a94100faSBill Paul break; 2347a94100faSBill Paul } 2348a94100faSBill Paul 2349a94100faSBill Paul /* 2350a94100faSBill Paul * If there's a BPF listener, bounce a copy of this frame 2351a94100faSBill Paul * to him. 2352a94100faSBill Paul */ 235359a0d28bSChristian S.J. Peron ETHER_BPF_MTAP(ifp, m_head); 235452732175SMax Laier 235552732175SMax Laier queued++; 2356a94100faSBill Paul } 2357a94100faSBill Paul 2358ed510fb0SBill Paul if (queued == 0) { 2359ed510fb0SBill Paul #ifdef RE_TX_MODERATION 2360d65abd66SPyun YongHyeon if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2361ed510fb0SBill Paul CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2362ed510fb0SBill Paul #endif 2363ed510fb0SBill Paul RL_UNLOCK(sc); 236452732175SMax Laier return; 2365ed510fb0SBill Paul } 236652732175SMax Laier 2367a94100faSBill Paul /* Flush the TX descriptors */ 2368a94100faSBill Paul 2369a94100faSBill Paul bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2370a94100faSBill Paul sc->rl_ldata.rl_tx_list_map, 2371a94100faSBill Paul BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2372a94100faSBill Paul 23730fc4974fSBill Paul CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2374a94100faSBill Paul 2375ed510fb0SBill Paul #ifdef RE_TX_MODERATION 2376a94100faSBill Paul /* 2377a94100faSBill Paul * Use the countdown timer for interrupt moderation. 2378a94100faSBill Paul * 'TX done' interrupts are disabled. Instead, we reset the 2379a94100faSBill Paul * countdown timer, which will begin counting until it hits 2380a94100faSBill Paul * the value in the TIMERINT register, and then trigger an 2381a94100faSBill Paul * interrupt. Each time we write to the TIMERCNT register, 2382a94100faSBill Paul * the timer count is reset to 0. 2383a94100faSBill Paul */ 2384a94100faSBill Paul CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2385ed510fb0SBill Paul #endif 2386a94100faSBill Paul 2387a94100faSBill Paul /* 2388a94100faSBill Paul * Set a timeout in case the chip goes out to lunch. 2389a94100faSBill Paul */ 23901d545c7aSMarius Strobl sc->rl_watchdog_timer = 5; 2391ed510fb0SBill Paul 2392ed510fb0SBill Paul RL_UNLOCK(sc); 2393ed510fb0SBill Paul 2394ed510fb0SBill Paul return; 2395a94100faSBill Paul } 2396a94100faSBill Paul 2397a94100faSBill Paul static void 2398a94100faSBill Paul re_init(xsc) 2399a94100faSBill Paul void *xsc; 2400a94100faSBill Paul { 2401a94100faSBill Paul struct rl_softc *sc = xsc; 240297b9d4baSJohn-Mark Gurney 240397b9d4baSJohn-Mark Gurney RL_LOCK(sc); 240497b9d4baSJohn-Mark Gurney re_init_locked(sc); 240597b9d4baSJohn-Mark Gurney RL_UNLOCK(sc); 240697b9d4baSJohn-Mark Gurney } 240797b9d4baSJohn-Mark Gurney 240897b9d4baSJohn-Mark Gurney static void 240997b9d4baSJohn-Mark Gurney re_init_locked(sc) 241097b9d4baSJohn-Mark Gurney struct rl_softc *sc; 241197b9d4baSJohn-Mark Gurney { 2412fc74a9f9SBrooks Davis struct ifnet *ifp = sc->rl_ifp; 2413a94100faSBill Paul struct mii_data *mii; 2414a94100faSBill Paul u_int32_t rxcfg = 0; 241570acaecfSPyun YongHyeon uint16_t cfg; 24164d3d7085SBernd Walter union { 24174d3d7085SBernd Walter uint32_t align_dummy; 24184d3d7085SBernd Walter u_char eaddr[ETHER_ADDR_LEN]; 24194d3d7085SBernd Walter } eaddr; 2420a94100faSBill Paul 242197b9d4baSJohn-Mark Gurney RL_LOCK_ASSERT(sc); 242297b9d4baSJohn-Mark Gurney 2423a94100faSBill Paul mii = device_get_softc(sc->rl_miibus); 2424a94100faSBill Paul 2425a94100faSBill Paul /* 2426a94100faSBill Paul * Cancel pending I/O and free all RX/TX buffers. 2427a94100faSBill Paul */ 2428a94100faSBill Paul re_stop(sc); 2429a94100faSBill Paul 2430a94100faSBill Paul /* 2431c2c6548bSBill Paul * Enable C+ RX and TX mode, as well as VLAN stripping and 2432edd03374SBill Paul * RX checksum offload. We must configure the C+ register 2433c2c6548bSBill Paul * before all others. 2434c2c6548bSBill Paul */ 243570acaecfSPyun YongHyeon cfg = RL_CPLUSCMD_PCI_MRW; 243670acaecfSPyun YongHyeon if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 243770acaecfSPyun YongHyeon cfg |= RL_CPLUSCMD_RXCSUM_ENB; 243870acaecfSPyun YongHyeon if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 243970acaecfSPyun YongHyeon cfg |= RL_CPLUSCMD_VLANSTRIP; 244070acaecfSPyun YongHyeon CSR_WRITE_2(sc, RL_CPLUS_CMD, 244170acaecfSPyun YongHyeon cfg | RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB); 2442c2c6548bSBill Paul 2443c2c6548bSBill Paul /* 2444a94100faSBill Paul * Init our MAC address. Even though the chipset 2445a94100faSBill Paul * documentation doesn't mention it, we need to enter "Config 2446a94100faSBill Paul * register write enable" mode to modify the ID registers. 2447a94100faSBill Paul */ 24484d3d7085SBernd Walter /* Copy MAC address on stack to align. */ 24494d3d7085SBernd Walter bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 2450a94100faSBill Paul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2451ed510fb0SBill Paul CSR_WRITE_4(sc, RL_IDR0, 2452ed510fb0SBill Paul htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 2453ed510fb0SBill Paul CSR_WRITE_4(sc, RL_IDR4, 2454ed510fb0SBill Paul htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 2455a94100faSBill Paul CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 2456a94100faSBill Paul 2457a94100faSBill Paul /* 2458a94100faSBill Paul * For C+ mode, initialize the RX descriptors and mbufs. 2459a94100faSBill Paul */ 2460a94100faSBill Paul re_rx_list_init(sc); 2461a94100faSBill Paul re_tx_list_init(sc); 2462a94100faSBill Paul 2463a94100faSBill Paul /* 2464d01fac16SPyun YongHyeon * Load the addresses of the RX and TX lists into the chip. 2465d01fac16SPyun YongHyeon */ 2466d01fac16SPyun YongHyeon 2467d01fac16SPyun YongHyeon CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 2468d01fac16SPyun YongHyeon RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 2469d01fac16SPyun YongHyeon CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 2470d01fac16SPyun YongHyeon RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 2471d01fac16SPyun YongHyeon 2472d01fac16SPyun YongHyeon CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 2473d01fac16SPyun YongHyeon RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 2474d01fac16SPyun YongHyeon CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 2475d01fac16SPyun YongHyeon RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 2476d01fac16SPyun YongHyeon 2477d01fac16SPyun YongHyeon /* 2478a94100faSBill Paul * Enable transmit and receive. 2479a94100faSBill Paul */ 2480a94100faSBill Paul CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2481a94100faSBill Paul 2482a94100faSBill Paul /* 2483a94100faSBill Paul * Set the initial TX and RX configuration. 2484a94100faSBill Paul */ 2485abc8ff44SBill Paul if (sc->rl_testmode) { 2486abc8ff44SBill Paul if (sc->rl_type == RL_8169) 2487abc8ff44SBill Paul CSR_WRITE_4(sc, RL_TXCFG, 2488abc8ff44SBill Paul RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 2489a94100faSBill Paul else 2490abc8ff44SBill Paul CSR_WRITE_4(sc, RL_TXCFG, 2491abc8ff44SBill Paul RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 2492abc8ff44SBill Paul } else 2493a94100faSBill Paul CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 2494d01fac16SPyun YongHyeon 2495d01fac16SPyun YongHyeon CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 2496d01fac16SPyun YongHyeon 2497a94100faSBill Paul CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG); 2498a94100faSBill Paul 2499a94100faSBill Paul /* Set the individual bit to receive frames for this host only. */ 2500a94100faSBill Paul rxcfg = CSR_READ_4(sc, RL_RXCFG); 2501a94100faSBill Paul rxcfg |= RL_RXCFG_RX_INDIV; 2502a94100faSBill Paul 2503a94100faSBill Paul /* If we want promiscuous mode, set the allframes bit. */ 250461021536SJohn-Mark Gurney if (ifp->if_flags & IFF_PROMISC) 2505a94100faSBill Paul rxcfg |= RL_RXCFG_RX_ALLPHYS; 250661021536SJohn-Mark Gurney else 2507a94100faSBill Paul rxcfg &= ~RL_RXCFG_RX_ALLPHYS; 2508a94100faSBill Paul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2509a94100faSBill Paul 2510a94100faSBill Paul /* 2511a94100faSBill Paul * Set capture broadcast bit to capture broadcast frames. 2512a94100faSBill Paul */ 251361021536SJohn-Mark Gurney if (ifp->if_flags & IFF_BROADCAST) 2514a94100faSBill Paul rxcfg |= RL_RXCFG_RX_BROAD; 251561021536SJohn-Mark Gurney else 2516a94100faSBill Paul rxcfg &= ~RL_RXCFG_RX_BROAD; 2517a94100faSBill Paul CSR_WRITE_4(sc, RL_RXCFG, rxcfg); 2518a94100faSBill Paul 2519a94100faSBill Paul /* 2520a94100faSBill Paul * Program the multicast filter, if necessary. 2521a94100faSBill Paul */ 2522a94100faSBill Paul re_setmulti(sc); 2523a94100faSBill Paul 2524a94100faSBill Paul #ifdef DEVICE_POLLING 2525a94100faSBill Paul /* 2526a94100faSBill Paul * Disable interrupts if we are polling. 2527a94100faSBill Paul */ 252840929967SGleb Smirnoff if (ifp->if_capenable & IFCAP_POLLING) 2529a94100faSBill Paul CSR_WRITE_2(sc, RL_IMR, 0); 2530a94100faSBill Paul else /* otherwise ... */ 253140929967SGleb Smirnoff #endif 2532ed510fb0SBill Paul 2533a94100faSBill Paul /* 2534a94100faSBill Paul * Enable interrupts. 2535a94100faSBill Paul */ 2536a94100faSBill Paul if (sc->rl_testmode) 2537a94100faSBill Paul CSR_WRITE_2(sc, RL_IMR, 0); 2538a94100faSBill Paul else 2539a94100faSBill Paul CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2540ed510fb0SBill Paul CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 2541a94100faSBill Paul 2542a94100faSBill Paul /* Set initial TX threshold */ 2543a94100faSBill Paul sc->rl_txthresh = RL_TX_THRESH_INIT; 2544a94100faSBill Paul 2545a94100faSBill Paul /* Start RX/TX process. */ 2546a94100faSBill Paul CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 2547a94100faSBill Paul #ifdef notdef 2548a94100faSBill Paul /* Enable receiver and transmitter. */ 2549a94100faSBill Paul CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 2550a94100faSBill Paul #endif 2551a94100faSBill Paul 2552ed510fb0SBill Paul #ifdef RE_TX_MODERATION 2553a94100faSBill Paul /* 2554a94100faSBill Paul * Initialize the timer interrupt register so that 2555a94100faSBill Paul * a timer interrupt will be generated once the timer 2556a94100faSBill Paul * reaches a certain number of ticks. The timer is 2557a94100faSBill Paul * reloaded on each transmit. This gives us TX interrupt 2558a94100faSBill Paul * moderation, which dramatically improves TX frame rate. 2559a94100faSBill Paul */ 2560a94100faSBill Paul if (sc->rl_type == RL_8169) 2561a94100faSBill Paul CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 2562a94100faSBill Paul else 2563a94100faSBill Paul CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 2564ed510fb0SBill Paul #endif 2565a94100faSBill Paul 2566a94100faSBill Paul /* 2567a94100faSBill Paul * For 8169 gigE NICs, set the max allowed RX packet 2568a94100faSBill Paul * size so we can receive jumbo frames. 2569a94100faSBill Paul */ 2570a94100faSBill Paul if (sc->rl_type == RL_8169) 2571a94100faSBill Paul CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 2572a94100faSBill Paul 257397b9d4baSJohn-Mark Gurney if (sc->rl_testmode) 2574a94100faSBill Paul return; 2575a94100faSBill Paul 2576a94100faSBill Paul mii_mediachg(mii); 2577a94100faSBill Paul 257819ecd231SPyun YongHyeon CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD); 2579a94100faSBill Paul 258013f4c340SRobert Watson ifp->if_drv_flags |= IFF_DRV_RUNNING; 258113f4c340SRobert Watson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2582a94100faSBill Paul 2583ed510fb0SBill Paul sc->rl_link = 0; 25841d545c7aSMarius Strobl sc->rl_watchdog_timer = 0; 2585d1754a9bSJohn Baldwin callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2586a94100faSBill Paul } 2587a94100faSBill Paul 2588a94100faSBill Paul /* 2589a94100faSBill Paul * Set media options. 2590a94100faSBill Paul */ 2591a94100faSBill Paul static int 2592a94100faSBill Paul re_ifmedia_upd(ifp) 2593a94100faSBill Paul struct ifnet *ifp; 2594a94100faSBill Paul { 2595a94100faSBill Paul struct rl_softc *sc; 2596a94100faSBill Paul struct mii_data *mii; 2597a94100faSBill Paul 2598a94100faSBill Paul sc = ifp->if_softc; 2599a94100faSBill Paul mii = device_get_softc(sc->rl_miibus); 2600d1754a9bSJohn Baldwin RL_LOCK(sc); 2601a94100faSBill Paul mii_mediachg(mii); 2602d1754a9bSJohn Baldwin RL_UNLOCK(sc); 2603a94100faSBill Paul 2604a94100faSBill Paul return (0); 2605a94100faSBill Paul } 2606a94100faSBill Paul 2607a94100faSBill Paul /* 2608a94100faSBill Paul * Report current media status. 2609a94100faSBill Paul */ 2610a94100faSBill Paul static void 2611a94100faSBill Paul re_ifmedia_sts(ifp, ifmr) 2612a94100faSBill Paul struct ifnet *ifp; 2613a94100faSBill Paul struct ifmediareq *ifmr; 2614a94100faSBill Paul { 2615a94100faSBill Paul struct rl_softc *sc; 2616a94100faSBill Paul struct mii_data *mii; 2617a94100faSBill Paul 2618a94100faSBill Paul sc = ifp->if_softc; 2619a94100faSBill Paul mii = device_get_softc(sc->rl_miibus); 2620a94100faSBill Paul 2621d1754a9bSJohn Baldwin RL_LOCK(sc); 2622a94100faSBill Paul mii_pollstat(mii); 2623d1754a9bSJohn Baldwin RL_UNLOCK(sc); 2624a94100faSBill Paul ifmr->ifm_active = mii->mii_media_active; 2625a94100faSBill Paul ifmr->ifm_status = mii->mii_media_status; 2626a94100faSBill Paul } 2627a94100faSBill Paul 2628a94100faSBill Paul static int 2629a94100faSBill Paul re_ioctl(ifp, command, data) 2630a94100faSBill Paul struct ifnet *ifp; 2631a94100faSBill Paul u_long command; 2632a94100faSBill Paul caddr_t data; 2633a94100faSBill Paul { 2634a94100faSBill Paul struct rl_softc *sc = ifp->if_softc; 2635a94100faSBill Paul struct ifreq *ifr = (struct ifreq *) data; 2636a94100faSBill Paul struct mii_data *mii; 263740929967SGleb Smirnoff int error = 0; 2638a94100faSBill Paul 2639a94100faSBill Paul switch (command) { 2640a94100faSBill Paul case SIOCSIFMTU: 2641c1d0b573SPyun YongHyeon if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > RL_JUMBO_MTU) { 2642a94100faSBill Paul error = EINVAL; 2643c1d0b573SPyun YongHyeon break; 2644c1d0b573SPyun YongHyeon } 2645c1d0b573SPyun YongHyeon if (sc->rl_type == RL_8139CPLUS && 2646c1d0b573SPyun YongHyeon ifr->ifr_mtu > RL_MAX_FRAMELEN) { 2647c1d0b573SPyun YongHyeon error = EINVAL; 2648c1d0b573SPyun YongHyeon break; 2649c1d0b573SPyun YongHyeon } 2650c1d0b573SPyun YongHyeon RL_LOCK(sc); 2651c1d0b573SPyun YongHyeon if (ifp->if_mtu != ifr->ifr_mtu) 2652a94100faSBill Paul ifp->if_mtu = ifr->ifr_mtu; 2653d1754a9bSJohn Baldwin RL_UNLOCK(sc); 2654a94100faSBill Paul break; 2655a94100faSBill Paul case SIOCSIFFLAGS: 265697b9d4baSJohn-Mark Gurney RL_LOCK(sc); 2657eed497bbSPyun YongHyeon if ((ifp->if_flags & IFF_UP) != 0) { 2658eed497bbSPyun YongHyeon if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2659eed497bbSPyun YongHyeon if (((ifp->if_flags ^ sc->rl_if_flags) 2660eed497bbSPyun YongHyeon & IFF_PROMISC) != 0) 2661eed497bbSPyun YongHyeon re_setmulti(sc); 2662eed497bbSPyun YongHyeon } else 266397b9d4baSJohn-Mark Gurney re_init_locked(sc); 2664eed497bbSPyun YongHyeon } else { 2665eed497bbSPyun YongHyeon if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2666a94100faSBill Paul re_stop(sc); 2667eed497bbSPyun YongHyeon } 2668eed497bbSPyun YongHyeon sc->rl_if_flags = ifp->if_flags; 266997b9d4baSJohn-Mark Gurney RL_UNLOCK(sc); 2670a94100faSBill Paul break; 2671a94100faSBill Paul case SIOCADDMULTI: 2672a94100faSBill Paul case SIOCDELMULTI: 267397b9d4baSJohn-Mark Gurney RL_LOCK(sc); 2674a94100faSBill Paul re_setmulti(sc); 267597b9d4baSJohn-Mark Gurney RL_UNLOCK(sc); 2676a94100faSBill Paul break; 2677a94100faSBill Paul case SIOCGIFMEDIA: 2678a94100faSBill Paul case SIOCSIFMEDIA: 2679a94100faSBill Paul mii = device_get_softc(sc->rl_miibus); 2680a94100faSBill Paul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2681a94100faSBill Paul break; 2682a94100faSBill Paul case SIOCSIFCAP: 268340929967SGleb Smirnoff { 2684f051cb85SGleb Smirnoff int mask, reinit; 2685f051cb85SGleb Smirnoff 2686f051cb85SGleb Smirnoff mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2687f051cb85SGleb Smirnoff reinit = 0; 268840929967SGleb Smirnoff #ifdef DEVICE_POLLING 268940929967SGleb Smirnoff if (mask & IFCAP_POLLING) { 269040929967SGleb Smirnoff if (ifr->ifr_reqcap & IFCAP_POLLING) { 269140929967SGleb Smirnoff error = ether_poll_register(re_poll, ifp); 269240929967SGleb Smirnoff if (error) 269340929967SGleb Smirnoff return(error); 2694d1754a9bSJohn Baldwin RL_LOCK(sc); 269540929967SGleb Smirnoff /* Disable interrupts */ 269640929967SGleb Smirnoff CSR_WRITE_2(sc, RL_IMR, 0x0000); 269740929967SGleb Smirnoff ifp->if_capenable |= IFCAP_POLLING; 269840929967SGleb Smirnoff RL_UNLOCK(sc); 269940929967SGleb Smirnoff } else { 270040929967SGleb Smirnoff error = ether_poll_deregister(ifp); 270140929967SGleb Smirnoff /* Enable interrupts. */ 270240929967SGleb Smirnoff RL_LOCK(sc); 270340929967SGleb Smirnoff CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 270440929967SGleb Smirnoff ifp->if_capenable &= ~IFCAP_POLLING; 270540929967SGleb Smirnoff RL_UNLOCK(sc); 270640929967SGleb Smirnoff } 270740929967SGleb Smirnoff } 270840929967SGleb Smirnoff #endif /* DEVICE_POLLING */ 270940929967SGleb Smirnoff if (mask & IFCAP_HWCSUM) { 2710f051cb85SGleb Smirnoff ifp->if_capenable ^= IFCAP_HWCSUM; 2711a94100faSBill Paul if (ifp->if_capenable & IFCAP_TXCSUM) 2712dc74159dSPyun YongHyeon ifp->if_hwassist |= RE_CSUM_FEATURES; 2713a94100faSBill Paul else 2714b61178a9SPyun YongHyeon ifp->if_hwassist &= ~RE_CSUM_FEATURES; 2715f051cb85SGleb Smirnoff reinit = 1; 271640929967SGleb Smirnoff } 2717f051cb85SGleb Smirnoff if (mask & IFCAP_VLAN_HWTAGGING) { 2718f051cb85SGleb Smirnoff ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2719f051cb85SGleb Smirnoff reinit = 1; 2720f051cb85SGleb Smirnoff } 2721dc74159dSPyun YongHyeon if (mask & IFCAP_TSO4) { 2722dc74159dSPyun YongHyeon ifp->if_capenable ^= IFCAP_TSO4; 2723dc74159dSPyun YongHyeon if ((IFCAP_TSO4 & ifp->if_capenable) && 2724dc74159dSPyun YongHyeon (IFCAP_TSO4 & ifp->if_capabilities)) 2725dc74159dSPyun YongHyeon ifp->if_hwassist |= CSUM_TSO; 2726dc74159dSPyun YongHyeon else 2727dc74159dSPyun YongHyeon ifp->if_hwassist &= ~CSUM_TSO; 2728dc74159dSPyun YongHyeon } 27297467bd53SPyun YongHyeon if ((mask & IFCAP_WOL) != 0 && 27307467bd53SPyun YongHyeon (ifp->if_capabilities & IFCAP_WOL) != 0) { 27317467bd53SPyun YongHyeon if ((mask & IFCAP_WOL_UCAST) != 0) 27327467bd53SPyun YongHyeon ifp->if_capenable ^= IFCAP_WOL_UCAST; 27337467bd53SPyun YongHyeon if ((mask & IFCAP_WOL_MCAST) != 0) 27347467bd53SPyun YongHyeon ifp->if_capenable ^= IFCAP_WOL_MCAST; 27357467bd53SPyun YongHyeon if ((mask & IFCAP_WOL_MAGIC) != 0) 27367467bd53SPyun YongHyeon ifp->if_capenable ^= IFCAP_WOL_MAGIC; 27377467bd53SPyun YongHyeon } 2738f051cb85SGleb Smirnoff if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) 2739f051cb85SGleb Smirnoff re_init(sc); 2740960fd5b3SPyun YongHyeon VLAN_CAPABILITIES(ifp); 274140929967SGleb Smirnoff } 2742a94100faSBill Paul break; 2743a94100faSBill Paul default: 2744a94100faSBill Paul error = ether_ioctl(ifp, command, data); 2745a94100faSBill Paul break; 2746a94100faSBill Paul } 2747a94100faSBill Paul 2748a94100faSBill Paul return (error); 2749a94100faSBill Paul } 2750a94100faSBill Paul 2751a94100faSBill Paul static void 27521d545c7aSMarius Strobl re_watchdog(sc) 2753a94100faSBill Paul struct rl_softc *sc; 27541d545c7aSMarius Strobl { 2755a94100faSBill Paul 27561d545c7aSMarius Strobl RL_LOCK_ASSERT(sc); 27571d545c7aSMarius Strobl 27581d545c7aSMarius Strobl if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 27591d545c7aSMarius Strobl return; 27601d545c7aSMarius Strobl 27611d545c7aSMarius Strobl device_printf(sc->rl_dev, "watchdog timeout\n"); 27621d545c7aSMarius Strobl sc->rl_ifp->if_oerrors++; 2763a94100faSBill Paul 2764a94100faSBill Paul re_txeof(sc); 2765a94100faSBill Paul re_rxeof(sc); 276697b9d4baSJohn-Mark Gurney re_init_locked(sc); 2767a94100faSBill Paul } 2768a94100faSBill Paul 2769a94100faSBill Paul /* 2770a94100faSBill Paul * Stop the adapter and free any mbufs allocated to the 2771a94100faSBill Paul * RX and TX lists. 2772a94100faSBill Paul */ 2773a94100faSBill Paul static void 2774a94100faSBill Paul re_stop(sc) 2775a94100faSBill Paul struct rl_softc *sc; 2776a94100faSBill Paul { 2777a94100faSBill Paul register int i; 2778a94100faSBill Paul struct ifnet *ifp; 2779d65abd66SPyun YongHyeon struct rl_txdesc *txd; 2780d65abd66SPyun YongHyeon struct rl_rxdesc *rxd; 2781a94100faSBill Paul 278297b9d4baSJohn-Mark Gurney RL_LOCK_ASSERT(sc); 278397b9d4baSJohn-Mark Gurney 2784fc74a9f9SBrooks Davis ifp = sc->rl_ifp; 2785a94100faSBill Paul 27861d545c7aSMarius Strobl sc->rl_watchdog_timer = 0; 2787d1754a9bSJohn Baldwin callout_stop(&sc->rl_stat_callout); 278813f4c340SRobert Watson ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2789a94100faSBill Paul 2790a94100faSBill Paul CSR_WRITE_1(sc, RL_COMMAND, 0x00); 2791a94100faSBill Paul CSR_WRITE_2(sc, RL_IMR, 0x0000); 2792ed510fb0SBill Paul CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 2793a94100faSBill Paul 2794a94100faSBill Paul if (sc->rl_head != NULL) { 2795a94100faSBill Paul m_freem(sc->rl_head); 2796a94100faSBill Paul sc->rl_head = sc->rl_tail = NULL; 2797a94100faSBill Paul } 2798a94100faSBill Paul 2799a94100faSBill Paul /* Free the TX list buffers. */ 2800a94100faSBill Paul 2801d65abd66SPyun YongHyeon for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 2802d65abd66SPyun YongHyeon txd = &sc->rl_ldata.rl_tx_desc[i]; 2803d65abd66SPyun YongHyeon if (txd->tx_m != NULL) { 2804d65abd66SPyun YongHyeon bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2805d65abd66SPyun YongHyeon txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2806d65abd66SPyun YongHyeon bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2807d65abd66SPyun YongHyeon txd->tx_dmamap); 2808d65abd66SPyun YongHyeon m_freem(txd->tx_m); 2809d65abd66SPyun YongHyeon txd->tx_m = NULL; 2810a94100faSBill Paul } 2811a94100faSBill Paul } 2812a94100faSBill Paul 2813a94100faSBill Paul /* Free the RX list buffers. */ 2814a94100faSBill Paul 2815d65abd66SPyun YongHyeon for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2816d65abd66SPyun YongHyeon rxd = &sc->rl_ldata.rl_rx_desc[i]; 2817d65abd66SPyun YongHyeon if (rxd->rx_m != NULL) { 2818d65abd66SPyun YongHyeon bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2819d65abd66SPyun YongHyeon rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2820d65abd66SPyun YongHyeon bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 2821d65abd66SPyun YongHyeon rxd->rx_dmamap); 2822d65abd66SPyun YongHyeon m_freem(rxd->rx_m); 2823d65abd66SPyun YongHyeon rxd->rx_m = NULL; 2824a94100faSBill Paul } 2825a94100faSBill Paul } 2826a94100faSBill Paul } 2827a94100faSBill Paul 2828a94100faSBill Paul /* 2829a94100faSBill Paul * Device suspend routine. Stop the interface and save some PCI 2830a94100faSBill Paul * settings in case the BIOS doesn't restore them properly on 2831a94100faSBill Paul * resume. 2832a94100faSBill Paul */ 2833a94100faSBill Paul static int 2834a94100faSBill Paul re_suspend(dev) 2835a94100faSBill Paul device_t dev; 2836a94100faSBill Paul { 2837a94100faSBill Paul struct rl_softc *sc; 2838a94100faSBill Paul 2839a94100faSBill Paul sc = device_get_softc(dev); 2840a94100faSBill Paul 284197b9d4baSJohn-Mark Gurney RL_LOCK(sc); 2842a94100faSBill Paul re_stop(sc); 28437467bd53SPyun YongHyeon re_setwol(sc); 2844a94100faSBill Paul sc->suspended = 1; 284597b9d4baSJohn-Mark Gurney RL_UNLOCK(sc); 2846a94100faSBill Paul 2847a94100faSBill Paul return (0); 2848a94100faSBill Paul } 2849a94100faSBill Paul 2850a94100faSBill Paul /* 2851a94100faSBill Paul * Device resume routine. Restore some PCI settings in case the BIOS 2852a94100faSBill Paul * doesn't, re-enable busmastering, and restart the interface if 2853a94100faSBill Paul * appropriate. 2854a94100faSBill Paul */ 2855a94100faSBill Paul static int 2856a94100faSBill Paul re_resume(dev) 2857a94100faSBill Paul device_t dev; 2858a94100faSBill Paul { 2859a94100faSBill Paul struct rl_softc *sc; 2860a94100faSBill Paul struct ifnet *ifp; 2861a94100faSBill Paul 2862a94100faSBill Paul sc = device_get_softc(dev); 286397b9d4baSJohn-Mark Gurney 286497b9d4baSJohn-Mark Gurney RL_LOCK(sc); 286597b9d4baSJohn-Mark Gurney 2866fc74a9f9SBrooks Davis ifp = sc->rl_ifp; 2867a94100faSBill Paul 2868a94100faSBill Paul /* reinitialize interface if necessary */ 2869a94100faSBill Paul if (ifp->if_flags & IFF_UP) 287097b9d4baSJohn-Mark Gurney re_init_locked(sc); 2871a94100faSBill Paul 28727467bd53SPyun YongHyeon /* 28737467bd53SPyun YongHyeon * Clear WOL matching such that normal Rx filtering 28747467bd53SPyun YongHyeon * wouldn't interfere with WOL patterns. 28757467bd53SPyun YongHyeon */ 28767467bd53SPyun YongHyeon re_clrwol(sc); 2877a94100faSBill Paul sc->suspended = 0; 287897b9d4baSJohn-Mark Gurney RL_UNLOCK(sc); 2879a94100faSBill Paul 2880a94100faSBill Paul return (0); 2881a94100faSBill Paul } 2882a94100faSBill Paul 2883a94100faSBill Paul /* 2884a94100faSBill Paul * Stop all chip I/O so that the kernel's probe routines don't 2885a94100faSBill Paul * get confused by errant DMAs when rebooting. 2886a94100faSBill Paul */ 28876a087a87SPyun YongHyeon static int 2888a94100faSBill Paul re_shutdown(dev) 2889a94100faSBill Paul device_t dev; 2890a94100faSBill Paul { 2891a94100faSBill Paul struct rl_softc *sc; 2892a94100faSBill Paul 2893a94100faSBill Paul sc = device_get_softc(dev); 2894a94100faSBill Paul 289597b9d4baSJohn-Mark Gurney RL_LOCK(sc); 2896a94100faSBill Paul re_stop(sc); 2897536fde34SMaxim Sobolev /* 2898536fde34SMaxim Sobolev * Mark interface as down since otherwise we will panic if 2899536fde34SMaxim Sobolev * interrupt comes in later on, which can happen in some 290072293673SRuslan Ermilov * cases. 2901536fde34SMaxim Sobolev */ 2902536fde34SMaxim Sobolev sc->rl_ifp->if_flags &= ~IFF_UP; 29037467bd53SPyun YongHyeon re_setwol(sc); 290497b9d4baSJohn-Mark Gurney RL_UNLOCK(sc); 29056a087a87SPyun YongHyeon 29066a087a87SPyun YongHyeon return (0); 2907a94100faSBill Paul } 29087467bd53SPyun YongHyeon 29097467bd53SPyun YongHyeon static void 29107467bd53SPyun YongHyeon re_setwol(sc) 29117467bd53SPyun YongHyeon struct rl_softc *sc; 29127467bd53SPyun YongHyeon { 29137467bd53SPyun YongHyeon struct ifnet *ifp; 29147467bd53SPyun YongHyeon int pmc; 29157467bd53SPyun YongHyeon uint16_t pmstat; 29167467bd53SPyun YongHyeon uint8_t v; 29177467bd53SPyun YongHyeon 29187467bd53SPyun YongHyeon RL_LOCK_ASSERT(sc); 29197467bd53SPyun YongHyeon 29207467bd53SPyun YongHyeon if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 29217467bd53SPyun YongHyeon return; 29227467bd53SPyun YongHyeon 29237467bd53SPyun YongHyeon ifp = sc->rl_ifp; 29247467bd53SPyun YongHyeon /* Enable config register write. */ 29257467bd53SPyun YongHyeon CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 29267467bd53SPyun YongHyeon 29277467bd53SPyun YongHyeon /* Enable PME. */ 29287467bd53SPyun YongHyeon v = CSR_READ_1(sc, RL_CFG1); 29297467bd53SPyun YongHyeon v &= ~RL_CFG1_PME; 29307467bd53SPyun YongHyeon if ((ifp->if_capenable & IFCAP_WOL) != 0) 29317467bd53SPyun YongHyeon v |= RL_CFG1_PME; 29327467bd53SPyun YongHyeon CSR_WRITE_1(sc, RL_CFG1, v); 29337467bd53SPyun YongHyeon 29347467bd53SPyun YongHyeon v = CSR_READ_1(sc, RL_CFG3); 29357467bd53SPyun YongHyeon v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 29367467bd53SPyun YongHyeon if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 29377467bd53SPyun YongHyeon v |= RL_CFG3_WOL_MAGIC; 29387467bd53SPyun YongHyeon CSR_WRITE_1(sc, RL_CFG3, v); 29397467bd53SPyun YongHyeon 29407467bd53SPyun YongHyeon /* Config register write done. */ 29417467bd53SPyun YongHyeon CSR_WRITE_1(sc, RL_EECMD, 0); 29427467bd53SPyun YongHyeon 29437467bd53SPyun YongHyeon v = CSR_READ_1(sc, RL_CFG5); 29447467bd53SPyun YongHyeon v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 29457467bd53SPyun YongHyeon v &= ~RL_CFG5_WOL_LANWAKE; 29467467bd53SPyun YongHyeon if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 29477467bd53SPyun YongHyeon v |= RL_CFG5_WOL_UCAST; 29487467bd53SPyun YongHyeon if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 29497467bd53SPyun YongHyeon v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 29507467bd53SPyun YongHyeon if ((ifp->if_capenable & IFCAP_WOL) != 0) 29517467bd53SPyun YongHyeon v |= RL_CFG5_WOL_LANWAKE; 29527467bd53SPyun YongHyeon CSR_WRITE_1(sc, RL_CFG5, v); 29537467bd53SPyun YongHyeon 29547467bd53SPyun YongHyeon /* 29557467bd53SPyun YongHyeon * It seems that hardware resets its link speed to 100Mbps in 29567467bd53SPyun YongHyeon * power down mode so switching to 100Mbps in driver is not 29577467bd53SPyun YongHyeon * needed. 29587467bd53SPyun YongHyeon */ 29597467bd53SPyun YongHyeon 29607467bd53SPyun YongHyeon /* Request PME if WOL is requested. */ 29617467bd53SPyun YongHyeon pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 29627467bd53SPyun YongHyeon pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 29637467bd53SPyun YongHyeon if ((ifp->if_capenable & IFCAP_WOL) != 0) 29647467bd53SPyun YongHyeon pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 29657467bd53SPyun YongHyeon pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 29667467bd53SPyun YongHyeon } 29677467bd53SPyun YongHyeon 29687467bd53SPyun YongHyeon static void 29697467bd53SPyun YongHyeon re_clrwol(sc) 29707467bd53SPyun YongHyeon struct rl_softc *sc; 29717467bd53SPyun YongHyeon { 29727467bd53SPyun YongHyeon int pmc; 29737467bd53SPyun YongHyeon uint8_t v; 29747467bd53SPyun YongHyeon 29757467bd53SPyun YongHyeon RL_LOCK_ASSERT(sc); 29767467bd53SPyun YongHyeon 29777467bd53SPyun YongHyeon if (pci_find_extcap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 29787467bd53SPyun YongHyeon return; 29797467bd53SPyun YongHyeon 29807467bd53SPyun YongHyeon /* Enable config register write. */ 29817467bd53SPyun YongHyeon CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 29827467bd53SPyun YongHyeon 29837467bd53SPyun YongHyeon v = CSR_READ_1(sc, RL_CFG3); 29847467bd53SPyun YongHyeon v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 29857467bd53SPyun YongHyeon CSR_WRITE_1(sc, RL_CFG3, v); 29867467bd53SPyun YongHyeon 29877467bd53SPyun YongHyeon /* Config register write done. */ 29887467bd53SPyun YongHyeon CSR_WRITE_1(sc, RL_EECMD, 0); 29897467bd53SPyun YongHyeon 29907467bd53SPyun YongHyeon v = CSR_READ_1(sc, RL_CFG5); 29917467bd53SPyun YongHyeon v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 29927467bd53SPyun YongHyeon v &= ~RL_CFG5_WOL_LANWAKE; 29937467bd53SPyun YongHyeon CSR_WRITE_1(sc, RL_CFG5, v); 29947467bd53SPyun YongHyeon } 2995