1 /*- 2 * Copyright (c) 2007 Damien Bergamini <damien.bergamini@free.fr> 3 * Copyright (c) 2012 Bernhard Schmidt <bschmidt@FreeBSD.org> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $OpenBSD: rt2860reg.h,v 1.30 2010/05/10 18:17:10 damien Exp $ 18 * $FreeBSD$ 19 */ 20 21 #define RT2860_NOISE_FLOOR -95 22 23 /* PCI registers */ 24 #define RT2860_PCI_CFG 0x0000 25 #define RT2860_PCI_EECTRL 0x0004 26 #define RT2860_PCI_MCUCTRL 0x0008 27 #define RT2860_PCI_SYSCTRL 0x000c 28 #define RT2860_PCIE_JTAG 0x0010 29 30 #define RT3090_AUX_CTRL 0x010c 31 32 #define RT3070_OPT_14 0x0114 33 34 /* SCH/DMA registers */ 35 #define RT2860_INT_STATUS 0x0200 36 #define RT2860_INT_MASK 0x0204 37 #define RT2860_WPDMA_GLO_CFG 0x0208 38 #define RT2860_WPDMA_RST_IDX 0x020c 39 #define RT2860_DELAY_INT_CFG 0x0210 40 #define RT2860_WMM_AIFSN_CFG 0x0214 41 #define RT2860_WMM_CWMIN_CFG 0x0218 42 #define RT2860_WMM_CWMAX_CFG 0x021c 43 #define RT2860_WMM_TXOP0_CFG 0x0220 44 #define RT2860_WMM_TXOP1_CFG 0x0224 45 #define RT2860_GPIO_CTRL 0x0228 46 #define RT2860_MCU_CMD_REG 0x022c 47 #define RT2860_TX_BASE_PTR(qid) (0x0230 + (qid) * 16) 48 #define RT2860_TX_MAX_CNT(qid) (0x0234 + (qid) * 16) 49 #define RT2860_TX_CTX_IDX(qid) (0x0238 + (qid) * 16) 50 #define RT2860_TX_DTX_IDX(qid) (0x023c + (qid) * 16) 51 #define RT2860_RX_BASE_PTR 0x0290 52 #define RT2860_RX_MAX_CNT 0x0294 53 #define RT2860_RX_CALC_IDX 0x0298 54 #define RT2860_FS_DRX_IDX 0x029c 55 #define RT2860_USB_DMA_CFG 0x02a0 /* RT2870 only */ 56 #define RT2860_US_CYC_CNT 0x02a4 57 58 /* PBF registers */ 59 #define RT2860_SYS_CTRL 0x0400 60 #define RT2860_HOST_CMD 0x0404 61 #define RT2860_PBF_CFG 0x0408 62 #define RT2860_MAX_PCNT 0x040c 63 #define RT2860_BUF_CTRL 0x0410 64 #define RT2860_MCU_INT_STA 0x0414 65 #define RT2860_MCU_INT_ENA 0x0418 66 #define RT2860_TXQ_IO(qid) (0x041c + (qid) * 4) 67 #define RT2860_RX0Q_IO 0x0424 68 #define RT2860_BCN_OFFSET0 0x042c 69 #define RT2860_BCN_OFFSET1 0x0430 70 #define RT2860_TXRXQ_STA 0x0434 71 #define RT2860_TXRXQ_PCNT 0x0438 72 #define RT2860_PBF_DBG 0x043c 73 #define RT2860_CAP_CTRL 0x0440 74 75 /* RT3070 registers */ 76 #define RT3070_RF_CSR_CFG 0x0500 77 #define RT3070_EFUSE_CTRL 0x0580 78 #define RT3070_EFUSE_DATA0 0x0590 79 #define RT3070_EFUSE_DATA1 0x0594 80 #define RT3070_EFUSE_DATA2 0x0598 81 #define RT3070_EFUSE_DATA3 0x059c 82 #define RT3090_OSC_CTRL 0x05a4 83 #define RT3070_LDO_CFG0 0x05d4 84 #define RT3070_GPIO_SWITCH 0x05dc 85 86 /* MAC registers */ 87 #define RT2860_ASIC_VER_ID 0x1000 88 #define RT2860_MAC_SYS_CTRL 0x1004 89 #define RT2860_MAC_ADDR_DW0 0x1008 90 #define RT2860_MAC_ADDR_DW1 0x100c 91 #define RT2860_MAC_BSSID_DW0 0x1010 92 #define RT2860_MAC_BSSID_DW1 0x1014 93 #define RT2860_MAX_LEN_CFG 0x1018 94 #define RT2860_BBP_CSR_CFG 0x101c 95 #define RT2860_RF_CSR_CFG0 0x1020 96 #define RT2860_RF_CSR_CFG1 0x1024 97 #define RT2860_RF_CSR_CFG2 0x1028 98 #define RT2860_LED_CFG 0x102c 99 100 /* undocumented registers */ 101 #define RT2860_DEBUG 0x10f4 102 103 /* MAC Timing control registers */ 104 #define RT2860_XIFS_TIME_CFG 0x1100 105 #define RT2860_BKOFF_SLOT_CFG 0x1104 106 #define RT2860_NAV_TIME_CFG 0x1108 107 #define RT2860_CH_TIME_CFG 0x110c 108 #define RT2860_PBF_LIFE_TIMER 0x1110 109 #define RT2860_BCN_TIME_CFG 0x1114 110 #define RT2860_TBTT_SYNC_CFG 0x1118 111 #define RT2860_TSF_TIMER_DW0 0x111c 112 #define RT2860_TSF_TIMER_DW1 0x1120 113 #define RT2860_TBTT_TIMER 0x1124 114 #define RT2860_INT_TIMER_CFG 0x1128 115 #define RT2860_INT_TIMER_EN 0x112c 116 #define RT2860_CH_IDLE_TIME 0x1130 117 118 /* MAC Power Save configuration registers */ 119 #define RT2860_MAC_STATUS_REG 0x1200 120 #define RT2860_PWR_PIN_CFG 0x1204 121 #define RT2860_AUTO_WAKEUP_CFG 0x1208 122 123 /* MAC TX configuration registers */ 124 #define RT2860_EDCA_AC_CFG(aci) (0x1300 + (aci) * 4) 125 #define RT2860_EDCA_TID_AC_MAP 0x1310 126 #define RT2860_TX_PWR_CFG(ridx) (0x1314 + (ridx) * 4) 127 #define RT2860_TX_PIN_CFG 0x1328 128 #define RT2860_TX_BAND_CFG 0x132c 129 #define RT2860_TX_SW_CFG0 0x1330 130 #define RT2860_TX_SW_CFG1 0x1334 131 #define RT2860_TX_SW_CFG2 0x1338 132 #define RT2860_TXOP_THRES_CFG 0x133c 133 #define RT2860_TXOP_CTRL_CFG 0x1340 134 #define RT2860_TX_RTS_CFG 0x1344 135 #define RT2860_TX_TIMEOUT_CFG 0x1348 136 #define RT2860_TX_RTY_CFG 0x134c 137 #define RT2860_TX_LINK_CFG 0x1350 138 #define RT2860_HT_FBK_CFG0 0x1354 139 #define RT2860_HT_FBK_CFG1 0x1358 140 #define RT2860_LG_FBK_CFG0 0x135c 141 #define RT2860_LG_FBK_CFG1 0x1360 142 #define RT2860_CCK_PROT_CFG 0x1364 143 #define RT2860_OFDM_PROT_CFG 0x1368 144 #define RT2860_MM20_PROT_CFG 0x136c 145 #define RT2860_MM40_PROT_CFG 0x1370 146 #define RT2860_GF20_PROT_CFG 0x1374 147 #define RT2860_GF40_PROT_CFG 0x1378 148 #define RT2860_EXP_CTS_TIME 0x137c 149 #define RT2860_EXP_ACK_TIME 0x1380 150 151 /* MAC RX configuration registers */ 152 #define RT2860_RX_FILTR_CFG 0x1400 153 #define RT2860_AUTO_RSP_CFG 0x1404 154 #define RT2860_LEGACY_BASIC_RATE 0x1408 155 #define RT2860_HT_BASIC_RATE 0x140c 156 #define RT2860_HT_CTRL_CFG 0x1410 157 #define RT2860_SIFS_COST_CFG 0x1414 158 #define RT2860_RX_PARSER_CFG 0x1418 159 160 /* MAC Security configuration registers */ 161 #define RT2860_TX_SEC_CNT0 0x1500 162 #define RT2860_RX_SEC_CNT0 0x1504 163 #define RT2860_CCMP_FC_MUTE 0x1508 164 165 /* MAC HCCA/PSMP configuration registers */ 166 #define RT2860_TXOP_HLDR_ADDR0 0x1600 167 #define RT2860_TXOP_HLDR_ADDR1 0x1604 168 #define RT2860_TXOP_HLDR_ET 0x1608 169 #define RT2860_QOS_CFPOLL_RA_DW0 0x160c 170 #define RT2860_QOS_CFPOLL_A1_DW1 0x1610 171 #define RT2860_QOS_CFPOLL_QC 0x1614 172 173 /* MAC Statistics Counters */ 174 #define RT2860_RX_STA_CNT0 0x1700 175 #define RT2860_RX_STA_CNT1 0x1704 176 #define RT2860_RX_STA_CNT2 0x1708 177 #define RT2860_TX_STA_CNT0 0x170c 178 #define RT2860_TX_STA_CNT1 0x1710 179 #define RT2860_TX_STA_CNT2 0x1714 180 #define RT2860_TX_STAT_FIFO 0x1718 181 182 /* RX WCID search table */ 183 #define RT2860_WCID_ENTRY(wcid) (0x1800 + (wcid) * 8) 184 185 #define RT2860_FW_BASE 0x2000 186 #define RT2870_FW_BASE 0x3000 187 188 /* Pair-wise key table */ 189 #define RT2860_PKEY(wcid) (0x4000 + (wcid) * 32) 190 191 /* IV/EIV table */ 192 #define RT2860_IVEIV(wcid) (0x6000 + (wcid) * 8) 193 194 /* WCID attribute table */ 195 #define RT2860_WCID_ATTR(wcid) (0x6800 + (wcid) * 4) 196 197 /* Shared Key Table */ 198 #define RT2860_SKEY(vap, kidx) (0x6c00 + (vap) * 128 + (kidx) * 32) 199 200 /* Shared Key Mode */ 201 #define RT2860_SKEY_MODE_0_7 0x7000 202 #define RT2860_SKEY_MODE_8_15 0x7004 203 #define RT2860_SKEY_MODE_16_23 0x7008 204 #define RT2860_SKEY_MODE_24_31 0x700c 205 206 /* Shared Memory between MCU and host */ 207 #define RT2860_H2M_MAILBOX 0x7010 208 #define RT2860_H2M_MAILBOX_CID 0x7014 209 #define RT2860_H2M_MAILBOX_STATUS 0x701c 210 #define RT2860_H2M_BBPAGENT 0x7028 211 #define RT2860_BCN_BASE(vap) (0x7800 + (vap) * 512) 212 213 214 /* possible flags for RT2860_PCI_CFG */ 215 #define RT2860_PCI_CFG_USB (1 << 17) 216 #define RT2860_PCI_CFG_PCI (1 << 16) 217 218 /* possible flags for register RT2860_PCI_EECTRL */ 219 #define RT2860_C (1 << 0) 220 #define RT2860_S (1 << 1) 221 #define RT2860_D (1 << 2) 222 #define RT2860_SHIFT_D 2 223 #define RT2860_Q (1 << 3) 224 #define RT2860_SHIFT_Q 3 225 226 /* possible flags for registers INT_STATUS/INT_MASK */ 227 #define RT2860_TX_COHERENT (1 << 17) 228 #define RT2860_RX_COHERENT (1 << 16) 229 #define RT2860_MAC_INT_4 (1 << 15) 230 #define RT2860_MAC_INT_3 (1 << 14) 231 #define RT2860_MAC_INT_2 (1 << 13) 232 #define RT2860_MAC_INT_1 (1 << 12) 233 #define RT2860_MAC_INT_0 (1 << 11) 234 #define RT2860_TX_RX_COHERENT (1 << 10) 235 #define RT2860_MCU_CMD_INT (1 << 9) 236 #define RT2860_TX_DONE_INT5 (1 << 8) 237 #define RT2860_TX_DONE_INT4 (1 << 7) 238 #define RT2860_TX_DONE_INT3 (1 << 6) 239 #define RT2860_TX_DONE_INT2 (1 << 5) 240 #define RT2860_TX_DONE_INT1 (1 << 4) 241 #define RT2860_TX_DONE_INT0 (1 << 3) 242 #define RT2860_RX_DONE_INT (1 << 2) 243 #define RT2860_TX_DLY_INT (1 << 1) 244 #define RT2860_RX_DLY_INT (1 << 0) 245 246 /* possible flags for register WPDMA_GLO_CFG */ 247 #define RT2860_HDR_SEG_LEN_SHIFT 8 248 #define RT2860_BIG_ENDIAN (1 << 7) 249 #define RT2860_TX_WB_DDONE (1 << 6) 250 #define RT2860_WPDMA_BT_SIZE_SHIFT 4 251 #define RT2860_WPDMA_BT_SIZE16 0 252 #define RT2860_WPDMA_BT_SIZE32 1 253 #define RT2860_WPDMA_BT_SIZE64 2 254 #define RT2860_WPDMA_BT_SIZE128 3 255 #define RT2860_RX_DMA_BUSY (1 << 3) 256 #define RT2860_RX_DMA_EN (1 << 2) 257 #define RT2860_TX_DMA_BUSY (1 << 1) 258 #define RT2860_TX_DMA_EN (1 << 0) 259 260 /* possible flags for register DELAY_INT_CFG */ 261 #define RT2860_TXDLY_INT_EN (1U << 31) 262 #define RT2860_TXMAX_PINT_SHIFT 24 263 #define RT2860_TXMAX_PTIME_SHIFT 16 264 #define RT2860_RXDLY_INT_EN (1 << 15) 265 #define RT2860_RXMAX_PINT_SHIFT 8 266 #define RT2860_RXMAX_PTIME_SHIFT 0 267 268 /* possible flags for register GPIO_CTRL */ 269 #define RT2860_GPIO_D_SHIFT 8 270 #define RT2860_GPIO_O_SHIFT 0 271 272 /* possible flags for register USB_DMA_CFG */ 273 #define RT2860_USB_TX_BUSY (1U << 31) 274 #define RT2860_USB_RX_BUSY (1 << 30) 275 #define RT2860_USB_EPOUT_VLD_SHIFT 24 276 #define RT2860_USB_TX_EN (1 << 23) 277 #define RT2860_USB_RX_EN (1 << 22) 278 #define RT2860_USB_RX_AGG_EN (1 << 21) 279 #define RT2860_USB_TXOP_HALT (1 << 20) 280 #define RT2860_USB_TX_CLEAR (1 << 19) 281 #define RT2860_USB_PHY_WD_EN (1 << 16) 282 #define RT2860_USB_PHY_MAN_RST (1 << 15) 283 #define RT2860_USB_RX_AGG_LMT(x) ((x) << 8) /* in unit of 1KB */ 284 #define RT2860_USB_RX_AGG_TO(x) ((x) & 0xff) /* in unit of 33ns */ 285 286 /* possible flags for register US_CYC_CNT */ 287 #define RT2860_TEST_EN (1 << 24) 288 #define RT2860_TEST_SEL_SHIFT 16 289 #define RT2860_BT_MODE_EN (1 << 8) 290 #define RT2860_US_CYC_CNT_SHIFT 0 291 292 /* possible flags for register SYS_CTRL */ 293 #define RT2860_HST_PM_SEL (1 << 16) 294 #define RT2860_CAP_MODE (1 << 14) 295 #define RT2860_PME_OEN (1 << 13) 296 #define RT2860_CLKSELECT (1 << 12) 297 #define RT2860_PBF_CLK_EN (1 << 11) 298 #define RT2860_MAC_CLK_EN (1 << 10) 299 #define RT2860_DMA_CLK_EN (1 << 9) 300 #define RT2860_MCU_READY (1 << 7) 301 #define RT2860_ASY_RESET (1 << 4) 302 #define RT2860_PBF_RESET (1 << 3) 303 #define RT2860_MAC_RESET (1 << 2) 304 #define RT2860_DMA_RESET (1 << 1) 305 #define RT2860_MCU_RESET (1 << 0) 306 307 /* possible values for register HOST_CMD */ 308 #define RT2860_MCU_CMD_SLEEP 0x30 309 #define RT2860_MCU_CMD_WAKEUP 0x31 310 #define RT2860_MCU_CMD_LEDS 0x50 311 #define RT2860_MCU_CMD_LED_RSSI 0x51 312 #define RT2860_MCU_CMD_LED1 0x52 313 #define RT2860_MCU_CMD_LED2 0x53 314 #define RT2860_MCU_CMD_LED3 0x54 315 #define RT2860_MCU_CMD_RFRESET 0x72 316 #define RT2860_MCU_CMD_ANTSEL 0x73 317 #define RT2860_MCU_CMD_BBP 0x80 318 #define RT2860_MCU_CMD_PSLEVEL 0x83 319 320 /* possible flags for register PBF_CFG */ 321 #define RT2860_TX1Q_NUM_SHIFT 21 322 #define RT2860_TX2Q_NUM_SHIFT 16 323 #define RT2860_NULL0_MODE (1 << 15) 324 #define RT2860_NULL1_MODE (1 << 14) 325 #define RT2860_RX_DROP_MODE (1 << 13) 326 #define RT2860_TX0Q_MANUAL (1 << 12) 327 #define RT2860_TX1Q_MANUAL (1 << 11) 328 #define RT2860_TX2Q_MANUAL (1 << 10) 329 #define RT2860_RX0Q_MANUAL (1 << 9) 330 #define RT2860_HCCA_EN (1 << 8) 331 #define RT2860_TX0Q_EN (1 << 4) 332 #define RT2860_TX1Q_EN (1 << 3) 333 #define RT2860_TX2Q_EN (1 << 2) 334 #define RT2860_RX0Q_EN (1 << 1) 335 336 /* possible flags for register BUF_CTRL */ 337 #define RT2860_WRITE_TXQ(qid) (1 << (11 - (qid))) 338 #define RT2860_NULL0_KICK (1 << 7) 339 #define RT2860_NULL1_KICK (1 << 6) 340 #define RT2860_BUF_RESET (1 << 5) 341 #define RT2860_READ_TXQ(qid) (1 << (3 - (qid)) 342 #define RT2860_READ_RX0Q (1 << 0) 343 344 /* possible flags for registers MCU_INT_STA/MCU_INT_ENA */ 345 #define RT2860_MCU_MAC_INT_8 (1 << 24) 346 #define RT2860_MCU_MAC_INT_7 (1 << 23) 347 #define RT2860_MCU_MAC_INT_6 (1 << 22) 348 #define RT2860_MCU_MAC_INT_4 (1 << 20) 349 #define RT2860_MCU_MAC_INT_3 (1 << 19) 350 #define RT2860_MCU_MAC_INT_2 (1 << 18) 351 #define RT2860_MCU_MAC_INT_1 (1 << 17) 352 #define RT2860_MCU_MAC_INT_0 (1 << 16) 353 #define RT2860_DTX0_INT (1 << 11) 354 #define RT2860_DTX1_INT (1 << 10) 355 #define RT2860_DTX2_INT (1 << 9) 356 #define RT2860_DRX0_INT (1 << 8) 357 #define RT2860_HCMD_INT (1 << 7) 358 #define RT2860_N0TX_INT (1 << 6) 359 #define RT2860_N1TX_INT (1 << 5) 360 #define RT2860_BCNTX_INT (1 << 4) 361 #define RT2860_MTX0_INT (1 << 3) 362 #define RT2860_MTX1_INT (1 << 2) 363 #define RT2860_MTX2_INT (1 << 1) 364 #define RT2860_MRX0_INT (1 << 0) 365 366 /* possible flags for register TXRXQ_PCNT */ 367 #define RT2860_RX0Q_PCNT_MASK 0xff000000 368 #define RT2860_TX2Q_PCNT_MASK 0x00ff0000 369 #define RT2860_TX1Q_PCNT_MASK 0x0000ff00 370 #define RT2860_TX0Q_PCNT_MASK 0x000000ff 371 372 /* possible flags for register CAP_CTRL */ 373 #define RT2860_CAP_ADC_FEQ (1U << 31) 374 #define RT2860_CAP_START (1 << 30) 375 #define RT2860_MAN_TRIG (1 << 29) 376 #define RT2860_TRIG_OFFSET_SHIFT 16 377 #define RT2860_START_ADDR_SHIFT 0 378 379 /* possible flags for register RF_CSR_CFG */ 380 #define RT3070_RF_KICK (1 << 17) 381 #define RT3070_RF_WRITE (1 << 16) 382 383 /* possible flags for register EFUSE_CTRL */ 384 #define RT3070_SEL_EFUSE (1U << 31) 385 #define RT3070_EFSROM_KICK (1 << 30) 386 #define RT3070_EFSROM_AIN_MASK 0x03ff0000 387 #define RT3070_EFSROM_AIN_SHIFT 16 388 #define RT3070_EFSROM_MODE_MASK 0x000000c0 389 #define RT3070_EFUSE_AOUT_MASK 0x0000003f 390 391 /* possible flags for register MAC_SYS_CTRL */ 392 #define RT2860_RX_TS_EN (1 << 7) 393 #define RT2860_WLAN_HALT_EN (1 << 6) 394 #define RT2860_PBF_LOOP_EN (1 << 5) 395 #define RT2860_CONT_TX_TEST (1 << 4) 396 #define RT2860_MAC_RX_EN (1 << 3) 397 #define RT2860_MAC_TX_EN (1 << 2) 398 #define RT2860_BBP_HRST (1 << 1) 399 #define RT2860_MAC_SRST (1 << 0) 400 401 /* possible flags for register MAC_BSSID_DW1 */ 402 #define RT2860_MULTI_BCN_NUM_SHIFT 18 403 #define RT2860_MULTI_BSSID_MODE_SHIFT 16 404 405 /* possible flags for register MAX_LEN_CFG */ 406 #define RT2860_MIN_MPDU_LEN_SHIFT 16 407 #define RT2860_MAX_PSDU_LEN_SHIFT 12 408 #define RT2860_MAX_PSDU_LEN8K 0 409 #define RT2860_MAX_PSDU_LEN16K 1 410 #define RT2860_MAX_PSDU_LEN32K 2 411 #define RT2860_MAX_PSDU_LEN64K 3 412 #define RT2860_MAX_MPDU_LEN_SHIFT 0 413 414 /* possible flags for registers BBP_CSR_CFG/H2M_BBPAGENT */ 415 #define RT2860_BBP_RW_PARALLEL (1 << 19) 416 #define RT2860_BBP_PAR_DUR_112_5 (1 << 18) 417 #define RT2860_BBP_CSR_KICK (1 << 17) 418 #define RT2860_BBP_CSR_READ (1 << 16) 419 #define RT2860_BBP_ADDR_SHIFT 8 420 #define RT2860_BBP_DATA_SHIFT 0 421 422 /* possible flags for register RF_CSR_CFG0 */ 423 #define RT2860_RF_REG_CTRL (1U << 31) 424 #define RT2860_RF_LE_SEL1 (1 << 30) 425 #define RT2860_RF_LE_STBY (1 << 29) 426 #define RT2860_RF_REG_WIDTH_SHIFT 24 427 #define RT2860_RF_REG_0_SHIFT 0 428 429 /* possible flags for register RF_CSR_CFG1 */ 430 #define RT2860_RF_DUR_5 (1 << 24) 431 #define RT2860_RF_REG_1_SHIFT 0 432 433 /* possible flags for register LED_CFG */ 434 #define RT2860_LED_POL (1 << 30) 435 #define RT2860_Y_LED_MODE_SHIFT 28 436 #define RT2860_G_LED_MODE_SHIFT 26 437 #define RT2860_R_LED_MODE_SHIFT 24 438 #define RT2860_LED_MODE_OFF 0 439 #define RT2860_LED_MODE_BLINK_TX 1 440 #define RT2860_LED_MODE_SLOW_BLINK 2 441 #define RT2860_LED_MODE_ON 3 442 #define RT2860_SLOW_BLK_TIME_SHIFT 16 443 #define RT2860_LED_OFF_TIME_SHIFT 8 444 #define RT2860_LED_ON_TIME_SHIFT 0 445 446 /* possible flags for register XIFS_TIME_CFG */ 447 #define RT2860_BB_RXEND_EN (1 << 29) 448 #define RT2860_EIFS_TIME_SHIFT 20 449 #define RT2860_OFDM_XIFS_TIME_SHIFT 16 450 #define RT2860_OFDM_SIFS_TIME_SHIFT 8 451 #define RT2860_CCK_SIFS_TIME_SHIFT 0 452 453 /* possible flags for register BKOFF_SLOT_CFG */ 454 #define RT2860_CC_DELAY_TIME_SHIFT 8 455 #define RT2860_SLOT_TIME 0 456 457 /* possible flags for register NAV_TIME_CFG */ 458 #define RT2860_NAV_UPD (1U << 31) 459 #define RT2860_NAV_UPD_VAL_SHIFT 16 460 #define RT2860_NAV_CLR_EN (1 << 15) 461 #define RT2860_NAV_TIMER_SHIFT 0 462 463 /* possible flags for register CH_TIME_CFG */ 464 #define RT2860_EIFS_AS_CH_BUSY (1 << 4) 465 #define RT2860_NAV_AS_CH_BUSY (1 << 3) 466 #define RT2860_RX_AS_CH_BUSY (1 << 2) 467 #define RT2860_TX_AS_CH_BUSY (1 << 1) 468 #define RT2860_CH_STA_TIMER_EN (1 << 0) 469 470 /* possible values for register BCN_TIME_CFG */ 471 #define RT2860_TSF_INS_COMP_SHIFT 24 472 #define RT2860_BCN_TX_EN (1 << 20) 473 #define RT2860_TBTT_TIMER_EN (1 << 19) 474 #define RT2860_TSF_SYNC_MODE_SHIFT 17 475 #define RT2860_TSF_SYNC_MODE_DIS 0 476 #define RT2860_TSF_SYNC_MODE_STA 1 477 #define RT2860_TSF_SYNC_MODE_IBSS 2 478 #define RT2860_TSF_SYNC_MODE_HOSTAP 3 479 #define RT2860_TSF_TIMER_EN (1 << 16) 480 #define RT2860_BCN_INTVAL_SHIFT 0 481 482 /* possible flags for register TBTT_SYNC_CFG */ 483 #define RT2860_BCN_CWMIN_SHIFT 20 484 #define RT2860_BCN_AIFSN_SHIFT 16 485 #define RT2860_BCN_EXP_WIN_SHIFT 8 486 #define RT2860_TBTT_ADJUST_SHIFT 0 487 488 /* possible flags for register INT_TIMER_CFG */ 489 #define RT2860_GP_TIMER_SHIFT 16 490 #define RT2860_PRE_TBTT_TIMER_SHIFT 0 491 492 /* possible flags for register INT_TIMER_EN */ 493 #define RT2860_GP_TIMER_EN (1 << 1) 494 #define RT2860_PRE_TBTT_INT_EN (1 << 0) 495 496 /* possible flags for register MAC_STATUS_REG */ 497 #define RT2860_RX_STATUS_BUSY (1 << 1) 498 #define RT2860_TX_STATUS_BUSY (1 << 0) 499 500 /* possible flags for register PWR_PIN_CFG */ 501 #define RT2860_IO_ADDA_PD (1 << 3) 502 #define RT2860_IO_PLL_PD (1 << 2) 503 #define RT2860_IO_RA_PE (1 << 1) 504 #define RT2860_IO_RF_PE (1 << 0) 505 506 /* possible flags for register AUTO_WAKEUP_CFG */ 507 #define RT2860_AUTO_WAKEUP_EN (1 << 15) 508 #define RT2860_SLEEP_TBTT_NUM_SHIFT 8 509 #define RT2860_WAKEUP_LEAD_TIME_SHIFT 0 510 511 /* possible flags for register TX_PIN_CFG */ 512 #define RT3593_LNA_PE_G2_POL (1U << 31) 513 #define RT3593_LNA_PE_A2_POL (1 << 30) 514 #define RT3593_LNA_PE_G2_EN (1 << 29) 515 #define RT3593_LNA_PE_A2_EN (1 << 28) 516 #define RT3593_LNA_PE2_EN (RT3593_LNA_PE_A2_EN | RT3593_LNA_PE_G2_EN) 517 #define RT3593_PA_PE_G2_POL (1 << 27) 518 #define RT3593_PA_PE_A2_POL (1 << 26) 519 #define RT3593_PA_PE_G2_EN (1 << 25) 520 #define RT3593_PA_PE_A2_EN (1 << 24) 521 #define RT2860_TRSW_POL (1 << 19) 522 #define RT2860_TRSW_EN (1 << 18) 523 #define RT2860_RFTR_POL (1 << 17) 524 #define RT2860_RFTR_EN (1 << 16) 525 #define RT2860_LNA_PE_G1_POL (1 << 15) 526 #define RT2860_LNA_PE_A1_POL (1 << 14) 527 #define RT2860_LNA_PE_G0_POL (1 << 13) 528 #define RT2860_LNA_PE_A0_POL (1 << 12) 529 #define RT2860_LNA_PE_G1_EN (1 << 11) 530 #define RT2860_LNA_PE_A1_EN (1 << 10) 531 #define RT2860_LNA_PE1_EN (RT2860_LNA_PE_A1_EN | RT2860_LNA_PE_G1_EN) 532 #define RT2860_LNA_PE_G0_EN (1 << 9) 533 #define RT2860_LNA_PE_A0_EN (1 << 8) 534 #define RT2860_LNA_PE0_EN (RT2860_LNA_PE_A0_EN | RT2860_LNA_PE_G0_EN) 535 #define RT2860_PA_PE_G1_POL (1 << 7) 536 #define RT2860_PA_PE_A1_POL (1 << 6) 537 #define RT2860_PA_PE_G0_POL (1 << 5) 538 #define RT2860_PA_PE_A0_POL (1 << 4) 539 #define RT2860_PA_PE_G1_EN (1 << 3) 540 #define RT2860_PA_PE_A1_EN (1 << 2) 541 #define RT2860_PA_PE_G0_EN (1 << 1) 542 #define RT2860_PA_PE_A0_EN (1 << 0) 543 544 /* possible flags for register TX_BAND_CFG */ 545 #define RT2860_5G_BAND_SEL_N (1 << 2) 546 #define RT2860_5G_BAND_SEL_P (1 << 1) 547 #define RT2860_TX_BAND_SEL (1 << 0) 548 549 /* possible flags for register TX_SW_CFG0 */ 550 #define RT2860_DLY_RFTR_EN_SHIFT 24 551 #define RT2860_DLY_TRSW_EN_SHIFT 16 552 #define RT2860_DLY_PAPE_EN_SHIFT 8 553 #define RT2860_DLY_TXPE_EN_SHIFT 0 554 555 /* possible flags for register TX_SW_CFG1 */ 556 #define RT2860_DLY_RFTR_DIS_SHIFT 16 557 #define RT2860_DLY_TRSW_DIS_SHIFT 8 558 #define RT2860_DLY_PAPE_DIS SHIFT 0 559 560 /* possible flags for register TX_SW_CFG2 */ 561 #define RT2860_DLY_LNA_EN_SHIFT 24 562 #define RT2860_DLY_LNA_DIS_SHIFT 16 563 #define RT2860_DLY_DAC_EN_SHIFT 8 564 #define RT2860_DLY_DAC_DIS_SHIFT 0 565 566 /* possible flags for register TXOP_THRES_CFG */ 567 #define RT2860_TXOP_REM_THRES_SHIFT 24 568 #define RT2860_CF_END_THRES_SHIFT 16 569 #define RT2860_RDG_IN_THRES 8 570 #define RT2860_RDG_OUT_THRES 0 571 572 /* possible flags for register TXOP_CTRL_CFG */ 573 #define RT2860_EXT_CW_MIN_SHIFT 16 574 #define RT2860_EXT_CCA_DLY_SHIFT 8 575 #define RT2860_EXT_CCA_EN (1 << 7) 576 #define RT2860_LSIG_TXOP_EN (1 << 6) 577 #define RT2860_TXOP_TRUN_EN_MIMOPS (1 << 4) 578 #define RT2860_TXOP_TRUN_EN_TXOP (1 << 3) 579 #define RT2860_TXOP_TRUN_EN_RATE (1 << 2) 580 #define RT2860_TXOP_TRUN_EN_AC (1 << 1) 581 #define RT2860_TXOP_TRUN_EN_TIMEOUT (1 << 0) 582 583 /* possible flags for register TX_RTS_CFG */ 584 #define RT2860_RTS_FBK_EN (1 << 24) 585 #define RT2860_RTS_THRES_SHIFT 8 586 #define RT2860_RTS_RTY_LIMIT_SHIFT 0 587 588 /* possible flags for register TX_TIMEOUT_CFG */ 589 #define RT2860_TXOP_TIMEOUT_SHIFT 16 590 #define RT2860_RX_ACK_TIMEOUT_SHIFT 8 591 #define RT2860_MPDU_LIFE_TIME_SHIFT 4 592 593 /* possible flags for register TX_RTY_CFG */ 594 #define RT2860_TX_AUTOFB_EN (1 << 30) 595 #define RT2860_AGG_RTY_MODE_TIMER (1 << 29) 596 #define RT2860_NAG_RTY_MODE_TIMER (1 << 28) 597 #define RT2860_LONG_RTY_THRES_SHIFT 16 598 #define RT2860_LONG_RTY_LIMIT_SHIFT 8 599 #define RT2860_SHORT_RTY_LIMIT_SHIFT 0 600 601 /* possible flags for register TX_LINK_CFG */ 602 #define RT2860_REMOTE_MFS_SHIFT 24 603 #define RT2860_REMOTE_MFB_SHIFT 16 604 #define RT2860_TX_CFACK_EN (1 << 12) 605 #define RT2860_TX_RDG_EN (1 << 11) 606 #define RT2860_TX_MRQ_EN (1 << 10) 607 #define RT2860_REMOTE_UMFS_EN (1 << 9) 608 #define RT2860_TX_MFB_EN (1 << 8) 609 #define RT2860_REMOTE_MFB_LT_SHIFT 0 610 611 /* possible flags for registers *_PROT_CFG */ 612 #define RT2860_RTSTH_EN (1 << 26) 613 #define RT2860_TXOP_ALLOW_GF40 (1 << 25) 614 #define RT2860_TXOP_ALLOW_GF20 (1 << 24) 615 #define RT2860_TXOP_ALLOW_MM40 (1 << 23) 616 #define RT2860_TXOP_ALLOW_MM20 (1 << 22) 617 #define RT2860_TXOP_ALLOW_OFDM (1 << 21) 618 #define RT2860_TXOP_ALLOW_CCK (1 << 20) 619 #define RT2860_TXOP_ALLOW_ALL (0x3f << 20) 620 #define RT2860_PROT_NAV_SHORT (1 << 18) 621 #define RT2860_PROT_NAV_LONG (2 << 18) 622 #define RT2860_PROT_CTRL_RTS_CTS (1 << 16) 623 #define RT2860_PROT_CTRL_CTS (2 << 16) 624 625 /* possible flags for registers EXP_{CTS,ACK}_TIME */ 626 #define RT2860_EXP_OFDM_TIME_SHIFT 16 627 #define RT2860_EXP_CCK_TIME_SHIFT 0 628 629 /* possible flags for register RX_FILTR_CFG */ 630 #define RT2860_DROP_CTRL_RSV (1 << 16) 631 #define RT2860_DROP_BAR (1 << 15) 632 #define RT2860_DROP_BA (1 << 14) 633 #define RT2860_DROP_PSPOLL (1 << 13) 634 #define RT2860_DROP_RTS (1 << 12) 635 #define RT2860_DROP_CTS (1 << 11) 636 #define RT2860_DROP_ACK (1 << 10) 637 #define RT2860_DROP_CFEND (1 << 9) 638 #define RT2860_DROP_CFACK (1 << 8) 639 #define RT2860_DROP_DUPL (1 << 7) 640 #define RT2860_DROP_BC (1 << 6) 641 #define RT2860_DROP_MC (1 << 5) 642 #define RT2860_DROP_VER_ERR (1 << 4) 643 #define RT2860_DROP_NOT_MYBSS (1 << 3) 644 #define RT2860_DROP_UC_NOME (1 << 2) 645 #define RT2860_DROP_PHY_ERR (1 << 1) 646 #define RT2860_DROP_CRC_ERR (1 << 0) 647 648 /* possible flags for register AUTO_RSP_CFG */ 649 #define RT2860_CTRL_PWR_BIT (1 << 7) 650 #define RT2860_BAC_ACK_POLICY (1 << 6) 651 #define RT2860_CCK_SHORT_EN (1 << 4) 652 #define RT2860_CTS_40M_REF_EN (1 << 3) 653 #define RT2860_CTS_40M_MODE_EN (1 << 2) 654 #define RT2860_BAC_ACKPOLICY_EN (1 << 1) 655 #define RT2860_AUTO_RSP_EN (1 << 0) 656 657 /* possible flags for register SIFS_COST_CFG */ 658 #define RT2860_OFDM_SIFS_COST_SHIFT 8 659 #define RT2860_CCK_SIFS_COST_SHIFT 0 660 661 /* possible flags for register TXOP_HLDR_ET */ 662 #define RT2860_TXOP_ETM1_EN (1 << 25) 663 #define RT2860_TXOP_ETM0_EN (1 << 24) 664 #define RT2860_TXOP_ETM_THRES_SHIFT 16 665 #define RT2860_TXOP_ETO_EN (1 << 8) 666 #define RT2860_TXOP_ETO_THRES_SHIFT 1 667 #define RT2860_PER_RX_RST_EN (1 << 0) 668 669 /* possible flags for register TX_STAT_FIFO */ 670 #define RT2860_TXQ_MCS_SHIFT 16 671 #define RT2860_TXQ_WCID_SHIFT 8 672 #define RT2860_TXQ_ACKREQ (1 << 7) 673 #define RT2860_TXQ_AGG (1 << 6) 674 #define RT2860_TXQ_OK (1 << 5) 675 #define RT2860_TXQ_PID_SHIFT 1 676 #define RT2860_TXQ_VLD (1 << 0) 677 678 /* possible flags for register WCID_ATTR */ 679 #define RT2860_MODE_NOSEC 0 680 #define RT2860_MODE_WEP40 1 681 #define RT2860_MODE_WEP104 2 682 #define RT2860_MODE_TKIP 3 683 #define RT2860_MODE_AES_CCMP 4 684 #define RT2860_MODE_CKIP40 5 685 #define RT2860_MODE_CKIP104 6 686 #define RT2860_MODE_CKIP128 7 687 #define RT2860_RX_PKEY_EN (1 << 0) 688 689 /* possible flags for register H2M_MAILBOX */ 690 #define RT2860_H2M_BUSY (1 << 24) 691 #define RT2860_TOKEN_NO_INTR 0xff 692 693 694 /* possible flags for MCU command RT2860_MCU_CMD_LEDS */ 695 #define RT2860_LED_RADIO (1 << 13) 696 #define RT2860_LED_LINK_2GHZ (1 << 14) 697 #define RT2860_LED_LINK_5GHZ (1 << 15) 698 699 700 /* possible flags for RT3020 RF register 1 */ 701 #define RT3070_RF_BLOCK (1 << 0) 702 #define RT3070_RX0_PD (1 << 2) 703 #define RT3070_TX0_PD (1 << 3) 704 #define RT3070_RX1_PD (1 << 4) 705 #define RT3070_TX1_PD (1 << 5) 706 #define RT3070_RX2_PD (1 << 6) 707 #define RT3070_TX2_PD (1 << 7) 708 709 /* possible flags for RT3020 RF register 7 */ 710 #define RT3070_TUNE (1 << 0) 711 712 /* possible flags for RT3020 RF register 15 */ 713 #define RT3070_TX_LO2 (1 << 3) 714 715 /* possible flags for RT3020 RF register 17 */ 716 #define RT3070_TX_LO1 (1 << 3) 717 718 /* possible flags for RT3020 RF register 20 */ 719 #define RT3070_RX_LO1 (1 << 3) 720 721 /* possible flags for RT3020 RF register 21 */ 722 #define RT3070_RX_LO2 (1 << 3) 723 #define RT3070_RX_CTB (1 << 7) 724 725 /* possible flags for RT3020 RF register 22 */ 726 #define RT3070_BB_LOOPBACK (1 << 0) 727 728 /* possible flags for RT3053 RF register 1 */ 729 #define RT3593_VCO (1 << 0) 730 731 /* possible flags for RT3053 RF register 2 */ 732 #define RT3593_RESCAL (1 << 7) 733 734 /* possible flags for RT3053 RF register 3 */ 735 #define RT3593_VCOCAL (1 << 7) 736 737 /* possible flags for RT3053 RF register 6 */ 738 #define RT3593_VCO_IC (1 << 6) 739 740 /* possible flags for RT3053 RF register 20 */ 741 #define RT3593_LDO_PLL_VC_MASK 0x0e 742 #define RT3593_LDO_RF_VC_MASK 0xe0 743 744 /* possible flags for RT3053 RF register 22 */ 745 #define RT3593_CP_IC_MASK 0xe0 746 #define RT3593_CP_IC_SHIFT 5 747 748 /* possible flags for RT3053 RF register 46 */ 749 #define RT3593_RX_CTB (1 << 5) 750 751 #define RT3090_DEF_LNA 10 752 753 /* RT2860 TX descriptor */ 754 struct rt2860_txd { 755 uint32_t sdp0; /* Segment Data Pointer 0 */ 756 uint16_t sdl1; /* Segment Data Length 1 */ 757 #define RT2860_TX_BURST (1 << 15) 758 #define RT2860_TX_LS1 (1 << 14) /* SDP1 is the last segment */ 759 760 uint16_t sdl0; /* Segment Data Length 0 */ 761 #define RT2860_TX_DDONE (1 << 15) 762 #define RT2860_TX_LS0 (1 << 14) /* SDP0 is the last segment */ 763 764 uint32_t sdp1; /* Segment Data Pointer 1 */ 765 uint8_t reserved[3]; 766 uint8_t flags; 767 #define RT2860_TX_QSEL_SHIFT 1 768 #define RT2860_TX_QSEL_MGMT (0 << 1) 769 #define RT2860_TX_QSEL_HCCA (1 << 1) 770 #define RT2860_TX_QSEL_EDCA (2 << 1) 771 #define RT2860_TX_WIV (1 << 0) 772 } __packed; 773 774 /* RT2870 TX descriptor */ 775 struct rt2870_txd { 776 uint16_t len; 777 uint8_t pad; 778 uint8_t flags; 779 } __packed; 780 781 /* TX Wireless Information */ 782 struct rt2860_txwi { 783 uint8_t flags; 784 #define RT2860_TX_MPDU_DSITY_SHIFT 5 785 #define RT2860_TX_AMPDU (1 << 4) 786 #define RT2860_TX_TS (1 << 3) 787 #define RT2860_TX_CFACK (1 << 2) 788 #define RT2860_TX_MMPS (1 << 1) 789 #define RT2860_TX_FRAG (1 << 0) 790 791 uint8_t txop; 792 #define RT2860_TX_TXOP_HT 0 793 #define RT2860_TX_TXOP_PIFS 1 794 #define RT2860_TX_TXOP_SIFS 2 795 #define RT2860_TX_TXOP_BACKOFF 3 796 797 uint16_t phy; 798 #define RT2860_PHY_MODE 0xc000 799 #define RT2860_PHY_CCK (0 << 14) 800 #define RT2860_PHY_OFDM (1 << 14) 801 #define RT2860_PHY_HT (2 << 14) 802 #define RT2860_PHY_HT_GF (3 << 14) 803 #define RT2860_PHY_SGI (1 << 8) 804 #define RT2860_PHY_BW40 (1 << 7) 805 #define RT2860_PHY_MCS 0x7f 806 #define RT2860_PHY_SHPRE (1 << 3) 807 808 uint8_t xflags; 809 #define RT2860_TX_BAWINSIZE_SHIFT 2 810 #define RT2860_TX_NSEQ (1 << 1) 811 #define RT2860_TX_ACK (1 << 0) 812 813 uint8_t wcid; /* Wireless Client ID */ 814 uint16_t len; 815 #define RT2860_TX_PID_SHIFT 12 816 817 uint32_t iv; 818 uint32_t eiv; 819 } __packed; 820 821 /* RT2860 RX descriptor */ 822 struct rt2860_rxd { 823 uint32_t sdp0; 824 uint16_t sdl1; /* unused */ 825 uint16_t sdl0; 826 #define RT2860_RX_DDONE (1 << 15) 827 #define RT2860_RX_LS0 (1 << 14) 828 829 uint32_t sdp1; /* unused */ 830 uint32_t flags; 831 #define RT2860_RX_DEC (1 << 16) 832 #define RT2860_RX_AMPDU (1 << 15) 833 #define RT2860_RX_L2PAD (1 << 14) 834 #define RT2860_RX_RSSI (1 << 13) 835 #define RT2860_RX_HTC (1 << 12) 836 #define RT2860_RX_AMSDU (1 << 11) 837 #define RT2860_RX_MICERR (1 << 10) 838 #define RT2860_RX_ICVERR (1 << 9) 839 #define RT2860_RX_CRCERR (1 << 8) 840 #define RT2860_RX_MYBSS (1 << 7) 841 #define RT2860_RX_BC (1 << 6) 842 #define RT2860_RX_MC (1 << 5) 843 #define RT2860_RX_UC2ME (1 << 4) 844 #define RT2860_RX_FRAG (1 << 3) 845 #define RT2860_RX_NULL (1 << 2) 846 #define RT2860_RX_DATA (1 << 1) 847 #define RT2860_RX_BA (1 << 0) 848 } __packed; 849 850 /* RT2870 RX descriptor */ 851 struct rt2870_rxd { 852 /* single 32-bit field */ 853 uint32_t flags; 854 } __packed; 855 856 /* RX Wireless Information */ 857 struct rt2860_rxwi { 858 uint8_t wcid; 859 uint8_t keyidx; 860 #define RT2860_RX_UDF_SHIFT 5 861 #define RT2860_RX_BSS_IDX_SHIFT 2 862 863 uint16_t len; 864 #define RT2860_RX_TID_SHIFT 12 865 866 uint16_t seq; 867 uint16_t phy; 868 uint8_t rssi[3]; 869 uint8_t reserved1; 870 uint8_t snr[2]; 871 uint16_t reserved2; 872 } __packed; 873 874 875 /* first DMA segment contains TXWI + 802.11 header + 32-bit padding */ 876 #define RT2860_TXWI_DMASZ \ 877 (sizeof (struct rt2860_txwi) + \ 878 sizeof (struct ieee80211_frame) + 6 + \ 879 sizeof (uint16_t)) 880 881 #define RT2860_RF1 0 882 #define RT2860_RF2 2 883 #define RT2860_RF3 1 884 #define RT2860_RF4 3 885 886 #define RT2860_RF_2820 1 /* 2T3R */ 887 #define RT2860_RF_2850 2 /* dual-band 2T3R */ 888 #define RT2860_RF_2720 3 /* 1T2R */ 889 #define RT2860_RF_2750 4 /* dual-band 1T2R */ 890 #define RT3070_RF_3020 5 /* 1T1R */ 891 #define RT3070_RF_2020 6 /* b/g */ 892 #define RT3070_RF_3021 7 /* 1T2R */ 893 #define RT3070_RF_3022 8 /* 2T2R */ 894 #define RT3070_RF_3052 9 /* dual-band 2T2R */ 895 #define RT3070_RF_3320 11 /* 1T1R */ 896 #define RT3070_RF_3053 13 /* dual-band 3T3R */ 897 898 /* USB commands for RT2870 only */ 899 #define RT2870_RESET 1 900 #define RT2870_WRITE_2 2 901 #define RT2870_WRITE_REGION_1 6 902 #define RT2870_READ_REGION_1 7 903 #define RT2870_EEPROM_READ 9 904 905 #define RT2860_EEPROM_DELAY 1 /* minimum hold time (microsecond) */ 906 907 #define RT2860_EEPROM_VERSION 0x01 908 #define RT2860_EEPROM_MAC01 0x02 909 #define RT2860_EEPROM_MAC23 0x03 910 #define RT2860_EEPROM_MAC45 0x04 911 #define RT2860_EEPROM_PCIE_PSLEVEL 0x11 912 #define RT2860_EEPROM_REV 0x12 913 #define RT2860_EEPROM_ANTENNA 0x1a 914 #define RT2860_EEPROM_CONFIG 0x1b 915 #define RT2860_EEPROM_COUNTRY 0x1c 916 #define RT2860_EEPROM_FREQ_LEDS 0x1d 917 #define RT2860_EEPROM_LED1 0x1e 918 #define RT2860_EEPROM_LED2 0x1f 919 #define RT2860_EEPROM_LED3 0x20 920 #define RT2860_EEPROM_LNA 0x22 921 #define RT2860_EEPROM_RSSI1_2GHZ 0x23 922 #define RT2860_EEPROM_RSSI2_2GHZ 0x24 923 #define RT2860_EEPROM_RSSI1_5GHZ 0x25 924 #define RT2860_EEPROM_RSSI2_5GHZ 0x26 925 #define RT2860_EEPROM_DELTAPWR 0x28 926 #define RT2860_EEPROM_PWR2GHZ_BASE1 0x29 927 #define RT2860_EEPROM_PWR2GHZ_BASE2 0x30 928 #define RT2860_EEPROM_TSSI1_2GHZ 0x37 929 #define RT2860_EEPROM_TSSI2_2GHZ 0x38 930 #define RT2860_EEPROM_TSSI3_2GHZ 0x39 931 #define RT2860_EEPROM_TSSI4_2GHZ 0x3a 932 #define RT2860_EEPROM_TSSI5_2GHZ 0x3b 933 #define RT2860_EEPROM_PWR5GHZ_BASE1 0x3c 934 #define RT2860_EEPROM_PWR5GHZ_BASE2 0x53 935 #define RT2860_EEPROM_TSSI1_5GHZ 0x6a 936 #define RT2860_EEPROM_TSSI2_5GHZ 0x6b 937 #define RT2860_EEPROM_TSSI3_5GHZ 0x6c 938 #define RT2860_EEPROM_TSSI4_5GHZ 0x6d 939 #define RT2860_EEPROM_TSSI5_5GHZ 0x6e 940 #define RT2860_EEPROM_RPWR 0x6f 941 #define RT2860_EEPROM_BBP_BASE 0x78 942 #define RT3071_EEPROM_RF_BASE 0x82 943 944 #define RT2860_RIDX_CCK1 0 945 #define RT2860_RIDX_CCK11 3 946 #define RT2860_RIDX_OFDM6 4 947 #define RT2860_RIDX_MAX 11 948 static const struct rt2860_rate { 949 uint8_t rate; 950 uint8_t mcs; 951 enum ieee80211_phytype phy; 952 uint8_t ctl_ridx; 953 uint16_t sp_ack_dur; 954 uint16_t lp_ack_dur; 955 } rt2860_rates[] = { 956 { 2, 0, IEEE80211_T_DS, 0, 314, 314 }, 957 { 4, 1, IEEE80211_T_DS, 1, 258, 162 }, 958 { 11, 2, IEEE80211_T_DS, 2, 223, 127 }, 959 { 22, 3, IEEE80211_T_DS, 3, 213, 117 }, 960 { 12, 0, IEEE80211_T_OFDM, 4, 60, 60 }, 961 { 18, 1, IEEE80211_T_OFDM, 4, 52, 52 }, 962 { 24, 2, IEEE80211_T_OFDM, 6, 48, 48 }, 963 { 36, 3, IEEE80211_T_OFDM, 6, 44, 44 }, 964 { 48, 4, IEEE80211_T_OFDM, 8, 44, 44 }, 965 { 72, 5, IEEE80211_T_OFDM, 8, 40, 40 }, 966 { 96, 6, IEEE80211_T_OFDM, 8, 40, 40 }, 967 { 108, 7, IEEE80211_T_OFDM, 8, 40, 40 } 968 }; 969 970 /* 971 * Control and status registers access macros. 972 */ 973 #define RAL_READ(sc, reg) \ 974 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 975 976 #define RAL_WRITE(sc, reg, val) \ 977 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 978 979 #define RAL_BARRIER_WRITE(sc) \ 980 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, 0x1800, \ 981 BUS_SPACE_BARRIER_WRITE) 982 983 #define RAL_BARRIER_READ_WRITE(sc) \ 984 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, 0x1800, \ 985 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 986 987 #define RAL_WRITE_REGION_1(sc, offset, datap, count) \ 988 bus_space_write_region_1((sc)->sc_st, (sc)->sc_sh, (offset), \ 989 (datap), (count)) 990 991 #define RAL_SET_REGION_4(sc, offset, val, count) \ 992 bus_space_set_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \ 993 (val), (count)) 994 995 /* 996 * EEPROM access macro. 997 */ 998 #define RT2860_EEPROM_CTL(sc, val) do { \ 999 RAL_WRITE((sc), RT2860_PCI_EECTRL, (val)); \ 1000 RAL_BARRIER_READ_WRITE((sc)); \ 1001 DELAY(RT2860_EEPROM_DELAY); \ 1002 } while (/* CONSTCOND */0) 1003 1004 /* 1005 * Default values for MAC registers; values taken from the reference driver. 1006 */ 1007 #define RT2860_DEF_MAC \ 1008 { RT2860_BCN_OFFSET0, 0xf8f0e8e0 }, \ 1009 { RT2860_LEGACY_BASIC_RATE, 0x0000013f }, \ 1010 { RT2860_HT_BASIC_RATE, 0x00008003 }, \ 1011 { RT2860_MAC_SYS_CTRL, 0x00000000 }, \ 1012 { RT2860_BKOFF_SLOT_CFG, 0x00000209 }, \ 1013 { RT2860_TX_SW_CFG0, 0x00000000 }, \ 1014 { RT2860_TX_SW_CFG1, 0x00080606 }, \ 1015 { RT2860_TX_LINK_CFG, 0x00001020 }, \ 1016 { RT2860_TX_TIMEOUT_CFG, 0x000a2090 }, \ 1017 { RT2860_LED_CFG, 0x7f031e46 }, \ 1018 { RT2860_WMM_AIFSN_CFG, 0x00002273 }, \ 1019 { RT2860_WMM_CWMIN_CFG, 0x00002344 }, \ 1020 { RT2860_WMM_CWMAX_CFG, 0x000034aa }, \ 1021 { RT2860_MAX_PCNT, 0x1f3fbf9f }, \ 1022 { RT2860_TX_RTY_CFG, 0x47d01f0f }, \ 1023 { RT2860_AUTO_RSP_CFG, 0x00000013 }, \ 1024 { RT2860_CCK_PROT_CFG, 0x05740003 }, \ 1025 { RT2860_OFDM_PROT_CFG, 0x05740003 }, \ 1026 { RT2860_GF20_PROT_CFG, 0x01744004 }, \ 1027 { RT2860_GF40_PROT_CFG, 0x03f44084 }, \ 1028 { RT2860_MM20_PROT_CFG, 0x01744004 }, \ 1029 { RT2860_MM40_PROT_CFG, 0x03f54084 }, \ 1030 { RT2860_TXOP_CTRL_CFG, 0x0000583f }, \ 1031 { RT2860_TXOP_HLDR_ET, 0x00000002 }, \ 1032 { RT2860_TX_RTS_CFG, 0x00092b20 }, \ 1033 { RT2860_EXP_ACK_TIME, 0x002400ca }, \ 1034 { RT2860_XIFS_TIME_CFG, 0x33a41010 }, \ 1035 { RT2860_PWR_PIN_CFG, 0x00000003 } 1036 1037 /* XXX only a few registers differ from above, try to merge? */ 1038 #define RT2870_DEF_MAC \ 1039 { RT2860_BCN_OFFSET0, 0xf8f0e8e0 }, \ 1040 { RT2860_LEGACY_BASIC_RATE, 0x0000013f }, \ 1041 { RT2860_HT_BASIC_RATE, 0x00008003 }, \ 1042 { RT2860_MAC_SYS_CTRL, 0x00000000 }, \ 1043 { RT2860_BKOFF_SLOT_CFG, 0x00000209 }, \ 1044 { RT2860_TX_SW_CFG0, 0x00000000 }, \ 1045 { RT2860_TX_SW_CFG1, 0x00080606 }, \ 1046 { RT2860_TX_LINK_CFG, 0x00001020 }, \ 1047 { RT2860_TX_TIMEOUT_CFG, 0x000a2090 }, \ 1048 { RT2860_LED_CFG, 0x7f031e46 }, \ 1049 { RT2860_WMM_AIFSN_CFG, 0x00002273 }, \ 1050 { RT2860_WMM_CWMIN_CFG, 0x00002344 }, \ 1051 { RT2860_WMM_CWMAX_CFG, 0x000034aa }, \ 1052 { RT2860_MAX_PCNT, 0x1f3fbf9f }, \ 1053 { RT2860_TX_RTY_CFG, 0x47d01f0f }, \ 1054 { RT2860_AUTO_RSP_CFG, 0x00000013 }, \ 1055 { RT2860_CCK_PROT_CFG, 0x05740003 }, \ 1056 { RT2860_OFDM_PROT_CFG, 0x05740003 }, \ 1057 { RT2860_PBF_CFG, 0x00f40006 }, \ 1058 { RT2860_WPDMA_GLO_CFG, 0x00000030 }, \ 1059 { RT2860_GF20_PROT_CFG, 0x01744004 }, \ 1060 { RT2860_GF40_PROT_CFG, 0x03f44084 }, \ 1061 { RT2860_MM20_PROT_CFG, 0x01744004 }, \ 1062 { RT2860_MM40_PROT_CFG, 0x03f44084 }, \ 1063 { RT2860_TXOP_CTRL_CFG, 0x0000583f }, \ 1064 { RT2860_TXOP_HLDR_ET, 0x00000002 }, \ 1065 { RT2860_TX_RTS_CFG, 0x00092b20 }, \ 1066 { RT2860_EXP_ACK_TIME, 0x002400ca }, \ 1067 { RT2860_XIFS_TIME_CFG, 0x33a41010 }, \ 1068 { RT2860_PWR_PIN_CFG, 0x00000003 } 1069 1070 /* 1071 * Default values for BBP registers; values taken from the reference driver. 1072 */ 1073 #define RT2860_DEF_BBP \ 1074 { 65, 0x2c }, \ 1075 { 66, 0x38 }, \ 1076 { 69, 0x12 }, \ 1077 { 70, 0x0a }, \ 1078 { 73, 0x10 }, \ 1079 { 81, 0x37 }, \ 1080 { 82, 0x62 }, \ 1081 { 83, 0x6a }, \ 1082 { 84, 0x99 }, \ 1083 { 86, 0x00 }, \ 1084 { 91, 0x04 }, \ 1085 { 92, 0x00 }, \ 1086 { 103, 0x00 }, \ 1087 { 105, 0x05 }, \ 1088 { 106, 0x35 } 1089 1090 /* 1091 * Default settings for RF registers; values derived from the reference driver. 1092 */ 1093 #define RT2860_RF2850 \ 1094 { 1, 0x100bb3, 0x1301e1, 0x05a014, 0x001402 }, \ 1095 { 2, 0x100bb3, 0x1301e1, 0x05a014, 0x001407 }, \ 1096 { 3, 0x100bb3, 0x1301e2, 0x05a014, 0x001402 }, \ 1097 { 4, 0x100bb3, 0x1301e2, 0x05a014, 0x001407 }, \ 1098 { 5, 0x100bb3, 0x1301e3, 0x05a014, 0x001402 }, \ 1099 { 6, 0x100bb3, 0x1301e3, 0x05a014, 0x001407 }, \ 1100 { 7, 0x100bb3, 0x1301e4, 0x05a014, 0x001402 }, \ 1101 { 8, 0x100bb3, 0x1301e4, 0x05a014, 0x001407 }, \ 1102 { 9, 0x100bb3, 0x1301e5, 0x05a014, 0x001402 }, \ 1103 { 10, 0x100bb3, 0x1301e5, 0x05a014, 0x001407 }, \ 1104 { 11, 0x100bb3, 0x1301e6, 0x05a014, 0x001402 }, \ 1105 { 12, 0x100bb3, 0x1301e6, 0x05a014, 0x001407 }, \ 1106 { 13, 0x100bb3, 0x1301e7, 0x05a014, 0x001402 }, \ 1107 { 14, 0x100bb3, 0x1301e8, 0x05a014, 0x001404 }, \ 1108 { 36, 0x100bb3, 0x130266, 0x056014, 0x001408 }, \ 1109 { 38, 0x100bb3, 0x130267, 0x056014, 0x001404 }, \ 1110 { 40, 0x100bb2, 0x1301a0, 0x056014, 0x001400 }, \ 1111 { 44, 0x100bb2, 0x1301a0, 0x056014, 0x001408 }, \ 1112 { 46, 0x100bb2, 0x1301a1, 0x056014, 0x001402 }, \ 1113 { 48, 0x100bb2, 0x1301a1, 0x056014, 0x001406 }, \ 1114 { 52, 0x100bb2, 0x1301a2, 0x056014, 0x001404 }, \ 1115 { 54, 0x100bb2, 0x1301a2, 0x056014, 0x001408 }, \ 1116 { 56, 0x100bb2, 0x1301a3, 0x056014, 0x001402 }, \ 1117 { 60, 0x100bb2, 0x1301a4, 0x056014, 0x001400 }, \ 1118 { 62, 0x100bb2, 0x1301a4, 0x056014, 0x001404 }, \ 1119 { 64, 0x100bb2, 0x1301a4, 0x056014, 0x001408 }, \ 1120 { 100, 0x100bb2, 0x1301ac, 0x05e014, 0x001400 }, \ 1121 { 102, 0x100bb2, 0x1701ac, 0x15e014, 0x001404 }, \ 1122 { 104, 0x100bb2, 0x1701ac, 0x15e014, 0x001408 }, \ 1123 { 108, 0x100bb3, 0x17028c, 0x15e014, 0x001404 }, \ 1124 { 110, 0x100bb3, 0x13028d, 0x05e014, 0x001400 }, \ 1125 { 112, 0x100bb3, 0x13028d, 0x05e014, 0x001406 }, \ 1126 { 116, 0x100bb3, 0x13028e, 0x05e014, 0x001408 }, \ 1127 { 118, 0x100bb3, 0x13028f, 0x05e014, 0x001404 }, \ 1128 { 120, 0x100bb1, 0x1300e0, 0x05e014, 0x001400 }, \ 1129 { 124, 0x100bb1, 0x1300e0, 0x05e014, 0x001404 }, \ 1130 { 126, 0x100bb1, 0x1300e0, 0x05e014, 0x001406 }, \ 1131 { 128, 0x100bb1, 0x1300e0, 0x05e014, 0x001408 }, \ 1132 { 132, 0x100bb1, 0x1300e1, 0x05e014, 0x001402 }, \ 1133 { 134, 0x100bb1, 0x1300e1, 0x05e014, 0x001404 }, \ 1134 { 136, 0x100bb1, 0x1300e1, 0x05e014, 0x001406 }, \ 1135 { 140, 0x100bb1, 0x1300e2, 0x05e014, 0x001400 }, \ 1136 { 149, 0x100bb1, 0x1300e2, 0x05e014, 0x001409 }, \ 1137 { 151, 0x100bb1, 0x1300e3, 0x05e014, 0x001401 }, \ 1138 { 153, 0x100bb1, 0x1300e3, 0x05e014, 0x001403 }, \ 1139 { 157, 0x100bb1, 0x1300e3, 0x05e014, 0x001407 }, \ 1140 { 159, 0x100bb1, 0x1300e3, 0x05e014, 0x001409 }, \ 1141 { 161, 0x100bb1, 0x1300e4, 0x05e014, 0x001401 }, \ 1142 { 165, 0x100bb1, 0x1300e4, 0x05e014, 0x001405 }, \ 1143 { 167, 0x100bb1, 0x1300f4, 0x05e014, 0x001407 }, \ 1144 { 169, 0x100bb1, 0x1300f4, 0x05e014, 0x001409 }, \ 1145 { 171, 0x100bb1, 0x1300f5, 0x05e014, 0x001401 }, \ 1146 { 173, 0x100bb1, 0x1300f5, 0x05e014, 0x001403 } 1147 1148 #define RT3070_RF3052 \ 1149 { 0xf1, 2, 2 }, \ 1150 { 0xf1, 2, 7 }, \ 1151 { 0xf2, 2, 2 }, \ 1152 { 0xf2, 2, 7 }, \ 1153 { 0xf3, 2, 2 }, \ 1154 { 0xf3, 2, 7 }, \ 1155 { 0xf4, 2, 2 }, \ 1156 { 0xf4, 2, 7 }, \ 1157 { 0xf5, 2, 2 }, \ 1158 { 0xf5, 2, 7 }, \ 1159 { 0xf6, 2, 2 }, \ 1160 { 0xf6, 2, 7 }, \ 1161 { 0xf7, 2, 2 }, \ 1162 { 0xf8, 2, 4 }, \ 1163 { 0x56, 0, 4 }, \ 1164 { 0x56, 0, 6 }, \ 1165 { 0x56, 0, 8 }, \ 1166 { 0x57, 0, 0 }, \ 1167 { 0x57, 0, 2 }, \ 1168 { 0x57, 0, 4 }, \ 1169 { 0x57, 0, 8 }, \ 1170 { 0x57, 0, 10 }, \ 1171 { 0x58, 0, 0 }, \ 1172 { 0x58, 0, 4 }, \ 1173 { 0x58, 0, 6 }, \ 1174 { 0x58, 0, 8 }, \ 1175 { 0x5b, 0, 8 }, \ 1176 { 0x5b, 0, 10 }, \ 1177 { 0x5c, 0, 0 }, \ 1178 { 0x5c, 0, 4 }, \ 1179 { 0x5c, 0, 6 }, \ 1180 { 0x5c, 0, 8 }, \ 1181 { 0x5d, 0, 0 }, \ 1182 { 0x5d, 0, 2 }, \ 1183 { 0x5d, 0, 4 }, \ 1184 { 0x5d, 0, 8 }, \ 1185 { 0x5d, 0, 10 }, \ 1186 { 0x5e, 0, 0 }, \ 1187 { 0x5e, 0, 4 }, \ 1188 { 0x5e, 0, 6 }, \ 1189 { 0x5e, 0, 8 }, \ 1190 { 0x5f, 0, 0 }, \ 1191 { 0x5f, 0, 9 }, \ 1192 { 0x5f, 0, 11 }, \ 1193 { 0x60, 0, 1 }, \ 1194 { 0x60, 0, 5 }, \ 1195 { 0x60, 0, 7 }, \ 1196 { 0x60, 0, 9 }, \ 1197 { 0x61, 0, 1 }, \ 1198 { 0x61, 0, 3 }, \ 1199 { 0x61, 0, 5 }, \ 1200 { 0x61, 0, 7 }, \ 1201 { 0x61, 0, 9 } 1202 1203 #define RT3070_DEF_RF \ 1204 { 4, 0x40 }, \ 1205 { 5, 0x03 }, \ 1206 { 6, 0x02 }, \ 1207 { 7, 0x70 }, \ 1208 { 9, 0x0f }, \ 1209 { 10, 0x41 }, \ 1210 { 11, 0x21 }, \ 1211 { 12, 0x7b }, \ 1212 { 14, 0x90 }, \ 1213 { 15, 0x58 }, \ 1214 { 16, 0xb3 }, \ 1215 { 17, 0x92 }, \ 1216 { 18, 0x2c }, \ 1217 { 19, 0x02 }, \ 1218 { 20, 0xba }, \ 1219 { 21, 0xdb }, \ 1220 { 24, 0x16 }, \ 1221 { 25, 0x01 }, \ 1222 { 29, 0x1f } 1223 1224 #define RT3572_DEF_RF \ 1225 { 0, 0x70 }, \ 1226 { 1, 0x81 }, \ 1227 { 2, 0xf1 }, \ 1228 { 3, 0x02 }, \ 1229 { 4, 0x4c }, \ 1230 { 5, 0x05 }, \ 1231 { 6, 0x4a }, \ 1232 { 7, 0xd8 }, \ 1233 { 9, 0xc3 }, \ 1234 { 10, 0xf1 }, \ 1235 { 11, 0xb9 }, \ 1236 { 12, 0x70 }, \ 1237 { 13, 0x65 }, \ 1238 { 14, 0xa0 }, \ 1239 { 15, 0x53 }, \ 1240 { 16, 0x4c }, \ 1241 { 17, 0x23 }, \ 1242 { 18, 0xac }, \ 1243 { 19, 0x93 }, \ 1244 { 20, 0xb3 }, \ 1245 { 21, 0xd0 }, \ 1246 { 22, 0x00 }, \ 1247 { 23, 0x3c }, \ 1248 { 24, 0x16 }, \ 1249 { 25, 0x15 }, \ 1250 { 26, 0x85 }, \ 1251 { 27, 0x00 }, \ 1252 { 28, 0x00 }, \ 1253 { 29, 0x9b }, \ 1254 { 30, 0x09 }, \ 1255 { 31, 0x10 } 1256